drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 static void i915_handle_rps_change(struct drm_device *dev)
 300 {
 301         drm_i915_private_t *dev_priv = dev->dev_private;
 302         u32 busy_up, busy_down, max_avg, min_avg;
 303         u8 new_delay = dev_priv->cur_delay;
 304
 305         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 306         busy_up = I915_READ(RCPREVBSYTUPAVG);
 307         busy_down = I915_READ(RCPREVBSYTDNAVG);
 308         max_avg = I915_READ(RCBMAXAVG);
 309         min_avg = I915_READ(RCBMINAVG);
 310
 311         /* Handle RCS change request from hw */
 312         if (busy_up > max_avg) {
 313                 if (dev_priv->cur_delay != dev_priv->max_delay)
 314                         new_delay = dev_priv->cur_delay - 1;
 315                 if (new_delay < dev_priv->max_delay)
 316                         new_delay = dev_priv->max_delay;
 317         } else if (busy_down < min_avg) {
 318                 if (dev_priv->cur_delay != dev_priv->min_delay)
 319                         new_delay = dev_priv->cur_delay + 1;
 320                 if (new_delay > dev_priv->min_delay)
 321                         new_delay = dev_priv->min_delay;
 322         }
 323
 324         if (ironlake_set_drps(dev, new_delay))
 325                 dev_priv->cur_delay = new_delay;
 326
 327         return;
 328 }
 329
 330 static void notify_ring(struct drm_device *dev,
 331                         struct intel_ring_buffer *ring)
 332 {
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334
 335         if (ring->obj == NULL)
 336                 return;
 337
 338         trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
 339
 340         wake_up_all(&ring->irq_queue);
 341         if (i915_enable_hangcheck) {
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer,
 344                           jiffies +
 345                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 346         }
 347 }
 348
 349 static void gen6_pm_rps_work(struct work_struct *work)
 350 {
 351         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 352                                                     rps_work);
 353         u32 pm_iir, pm_imr;
 354         u8 new_delay;
 355
 356         spin_lock_irq(&dev_priv->rps_lock);
 357         pm_iir = dev_priv->pm_iir;
 358         dev_priv->pm_iir = 0;
 359         pm_imr = I915_READ(GEN6_PMIMR);
 360         I915_WRITE(GEN6_PMIMR, 0);
 361         spin_unlock_irq(&dev_priv->rps_lock);
 362
 363         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 364                 return;
 365
 366         mutex_lock(&dev_priv->dev->struct_mutex);
 367
 368         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 369                 new_delay = dev_priv->cur_delay + 1;
 370         else
 371                 new_delay = dev_priv->cur_delay - 1;
 372
 373         gen6_set_rps(dev_priv->dev, new_delay);
 374
 375         mutex_unlock(&dev_priv->dev->struct_mutex);
 376 }
 377
 378 static void snb_gt_irq_handler(struct drm_device *dev,
 379                                struct drm_i915_private *dev_priv,
 380                                u32 gt_iir)
 381 {
 382
 383         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 384                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 385                 notify_ring(dev, &dev_priv->ring[RCS]);
 386         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 387                 notify_ring(dev, &dev_priv->ring[VCS]);
 388         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 389                 notify_ring(dev, &dev_priv->ring[BCS]);
 390
 391         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 392                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 393                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 394                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 395                 i915_handle_error(dev, false);
 396         }
 397 }
 398
 399 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 400                                 u32 pm_iir)
 401 {
 402         unsigned long flags;
 403
 404         /*
 405          * IIR bits should never already be set because IMR should
 406          * prevent an interrupt from being shown in IIR. The warning
 407          * displays a case where we've unsafely cleared
 408          * dev_priv->pm_iir. Although missing an interrupt of the same
 409          * type is not a problem, it displays a problem in the logic.
 410          *
 411          * The mask bit in IMR is cleared by rps_work.
 412          */
 413
 414         spin_lock_irqsave(&dev_priv->rps_lock, flags);
 415         dev_priv->pm_iir |= pm_iir;
 416         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 417         POSTING_READ(GEN6_PMIMR);
 418         spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 419
 420         queue_work(dev_priv->wq, &dev_priv->rps_work);
 421 }
 422
 423 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 424 {
 425         struct drm_device *dev = (struct drm_device *) arg;
 426         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 427         u32 iir, gt_iir, pm_iir;
 428         irqreturn_t ret = IRQ_NONE;
 429         unsigned long irqflags;
 430         int pipe;
 431         u32 pipe_stats[I915_MAX_PIPES];
 432         u32 vblank_status;
 433         int vblank = 0;
 434         bool blc_event;
 435
 436         atomic_inc(&dev_priv->irq_received);
 437
 438         vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
 439                 PIPE_VBLANK_INTERRUPT_STATUS;
 440
 441         while (true) {
 442                 iir = I915_READ(VLV_IIR);
 443                 gt_iir = I915_READ(GTIIR);
 444                 pm_iir = I915_READ(GEN6_PMIIR);
 445
 446                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 447                         goto out;
 448
 449                 ret = IRQ_HANDLED;
 450
 451                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 452
 453                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 454                 for_each_pipe(pipe) {
 455                         int reg = PIPESTAT(pipe);
 456                         pipe_stats[pipe] = I915_READ(reg);
 457
 458                         /*
 459                          * Clear the PIPE*STAT regs before the IIR
 460                          */
 461                         if (pipe_stats[pipe] & 0x8000ffff) {
 462                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 463                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 464                                                          pipe_name(pipe));
 465                                 I915_WRITE(reg, pipe_stats[pipe]);
 466                         }
 467                 }
 468                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 469
 470                 /* Consume port.  Then clear IIR or we'll miss events */
 471                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 472                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 473
 474                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 475                                          hotplug_status);
 476                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 477                                 queue_work(dev_priv->wq,
 478                                            &dev_priv->hotplug_work);
 479
 480                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 481                         I915_READ(PORT_HOTPLUG_STAT);
 482                 }
 483
 484
 485                 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
 486                         drm_handle_vblank(dev, 0);
 487                         vblank++;
 488                         intel_finish_page_flip(dev, 0);
 489                 }
 490
 491                 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
 492                         drm_handle_vblank(dev, 1);
 493                         vblank++;
 494                         intel_finish_page_flip(dev, 0);
 495                 }
 496
 497                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 498                         blc_event = true;
 499
 500                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 501                         gen6_queue_rps_work(dev_priv, pm_iir);
 502
 503                 I915_WRITE(GTIIR, gt_iir);
 504                 I915_WRITE(GEN6_PMIIR, pm_iir);
 505                 I915_WRITE(VLV_IIR, iir);
 506         }
 507
 508 out:
 509         return ret;
 510 }
 511
 512 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 513 {
 514         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 515         int pipe;
 516
 517         if (pch_iir & SDE_AUDIO_POWER_MASK)
 518                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 519                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 520                                  SDE_AUDIO_POWER_SHIFT);
 521
 522         if (pch_iir & SDE_GMBUS)
 523                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 524
 525         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 526                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 527
 528         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 529                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 530
 531         if (pch_iir & SDE_POISON)
 532                 DRM_ERROR("PCH poison interrupt\n");
 533
 534         if (pch_iir & SDE_FDI_MASK)
 535                 for_each_pipe(pipe)
 536                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 537                                          pipe_name(pipe),
 538                                          I915_READ(FDI_RX_IIR(pipe)));
 539
 540         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 541                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 542
 543         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 544                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 545
 546         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 547                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 548         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 549                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 550 }
 551
 552 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 553 {
 554         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 555         int pipe;
 556
 557         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 558                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 559                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 560                                  SDE_AUDIO_POWER_SHIFT_CPT);
 561
 562         if (pch_iir & SDE_AUX_MASK_CPT)
 563                 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 564
 565         if (pch_iir & SDE_GMBUS_CPT)
 566                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 567
 568         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 569                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 570
 571         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 572                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 573
 574         if (pch_iir & SDE_FDI_MASK_CPT)
 575                 for_each_pipe(pipe)
 576                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 577                                          pipe_name(pipe),
 578                                          I915_READ(FDI_RX_IIR(pipe)));
 579 }
 580
 581 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 582 {
 583         struct drm_device *dev = (struct drm_device *) arg;
 584         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 585         u32 de_iir, gt_iir, de_ier, pm_iir;
 586         irqreturn_t ret = IRQ_NONE;
 587         int i;
 588
 589         atomic_inc(&dev_priv->irq_received);
 590
 591         /* disable master interrupt before clearing iir  */
 592         de_ier = I915_READ(DEIER);
 593         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 594
 595         gt_iir = I915_READ(GTIIR);
 596         if (gt_iir) {
 597                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 598                 I915_WRITE(GTIIR, gt_iir);
 599                 ret = IRQ_HANDLED;
 600         }
 601
 602         de_iir = I915_READ(DEIIR);
 603         if (de_iir) {
 604                 if (de_iir & DE_GSE_IVB)
 605                         intel_opregion_gse_intr(dev);
 606
 607                 for (i = 0; i < 3; i++) {
 608                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 609                                 intel_prepare_page_flip(dev, i);
 610                                 intel_finish_page_flip_plane(dev, i);
 611                         }
 612                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 613                                 drm_handle_vblank(dev, i);
 614                 }
 615
 616                 /* check event from PCH */
 617                 if (de_iir & DE_PCH_EVENT_IVB) {
 618                         u32 pch_iir = I915_READ(SDEIIR);
 619
 620                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 621                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 622                         cpt_irq_handler(dev, pch_iir);
 623
 624                         /* clear PCH hotplug event before clear CPU irq */
 625                         I915_WRITE(SDEIIR, pch_iir);
 626                 }
 627
 628                 I915_WRITE(DEIIR, de_iir);
 629                 ret = IRQ_HANDLED;
 630         }
 631
 632         pm_iir = I915_READ(GEN6_PMIIR);
 633         if (pm_iir) {
 634                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 635                         gen6_queue_rps_work(dev_priv, pm_iir);
 636                 I915_WRITE(GEN6_PMIIR, pm_iir);
 637                 ret = IRQ_HANDLED;
 638         }
 639
 640         I915_WRITE(DEIER, de_ier);
 641         POSTING_READ(DEIER);
 642
 643         return ret;
 644 }
 645
 646 static void ilk_gt_irq_handler(struct drm_device *dev,
 647                                struct drm_i915_private *dev_priv,
 648                                u32 gt_iir)
 649 {
 650         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 651                 notify_ring(dev, &dev_priv->ring[RCS]);
 652         if (gt_iir & GT_BSD_USER_INTERRUPT)
 653                 notify_ring(dev, &dev_priv->ring[VCS]);
 654 }
 655
 656 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 657 {
 658         struct drm_device *dev = (struct drm_device *) arg;
 659         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 660         int ret = IRQ_NONE;
 661         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 662         u32 hotplug_mask;
 663
 664         atomic_inc(&dev_priv->irq_received);
 665
 666         /* disable master interrupt before clearing iir  */
 667         de_ier = I915_READ(DEIER);
 668         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 669         POSTING_READ(DEIER);
 670
 671         de_iir = I915_READ(DEIIR);
 672         gt_iir = I915_READ(GTIIR);
 673         pch_iir = I915_READ(SDEIIR);
 674         pm_iir = I915_READ(GEN6_PMIIR);
 675
 676         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 677             (!IS_GEN6(dev) || pm_iir == 0))
 678                 goto done;
 679
 680         if (HAS_PCH_CPT(dev))
 681                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 682         else
 683                 hotplug_mask = SDE_HOTPLUG_MASK;
 684
 685         ret = IRQ_HANDLED;
 686
 687         if (IS_GEN5(dev))
 688                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 689         else
 690                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 691
 692         if (de_iir & DE_GSE)
 693                 intel_opregion_gse_intr(dev);
 694
 695         if (de_iir & DE_PLANEA_FLIP_DONE) {
 696                 intel_prepare_page_flip(dev, 0);
 697                 intel_finish_page_flip_plane(dev, 0);
 698         }
 699
 700         if (de_iir & DE_PLANEB_FLIP_DONE) {
 701                 intel_prepare_page_flip(dev, 1);
 702                 intel_finish_page_flip_plane(dev, 1);
 703         }
 704
 705         if (de_iir & DE_PIPEA_VBLANK)
 706                 drm_handle_vblank(dev, 0);
 707
 708         if (de_iir & DE_PIPEB_VBLANK)
 709                 drm_handle_vblank(dev, 1);
 710
 711         /* check event from PCH */
 712         if (de_iir & DE_PCH_EVENT) {
 713                 if (pch_iir & hotplug_mask)
 714                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 715                 if (HAS_PCH_CPT(dev))
 716                         cpt_irq_handler(dev, pch_iir);
 717                 else
 718                         ibx_irq_handler(dev, pch_iir);
 719         }
 720
 721         if (de_iir & DE_PCU_EVENT) {
 722                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 723                 i915_handle_rps_change(dev);
 724         }
 725
 726         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 727                 gen6_queue_rps_work(dev_priv, pm_iir);
 728
 729         /* should clear PCH hotplug event before clear CPU irq */
 730         I915_WRITE(SDEIIR, pch_iir);
 731         I915_WRITE(GTIIR, gt_iir);
 732         I915_WRITE(DEIIR, de_iir);
 733         I915_WRITE(GEN6_PMIIR, pm_iir);
 734
 735 done:
 736         I915_WRITE(DEIER, de_ier);
 737         POSTING_READ(DEIER);
 738
 739         return ret;
 740 }
 741
 742 /**
 743  * i915_error_work_func - do process context error handling work
 744  * @work: work struct
 745  *
 746  * Fire an error uevent so userspace can see that a hang or error
 747  * was detected.
 748  */
 749 static void i915_error_work_func(struct work_struct *work)
 750 {
 751         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 752                                                     error_work);
 753         struct drm_device *dev = dev_priv->dev;
 754         char *error_event[] = { "ERROR=1", NULL };
 755         char *reset_event[] = { "RESET=1", NULL };
 756         char *reset_done_event[] = { "ERROR=0", NULL };
 757
 758         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 759
 760         if (atomic_read(&dev_priv->mm.wedged)) {
 761                 DRM_DEBUG_DRIVER("resetting chip\n");
 762                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 763                 if (!i915_reset(dev)) {
 764                         atomic_set(&dev_priv->mm.wedged, 0);
 765                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 766                 }
 767                 complete_all(&dev_priv->error_completion);
 768         }
 769 }
 770
 771 #ifdef CONFIG_DEBUG_FS
 772 static struct drm_i915_error_object *
 773 i915_error_object_create(struct drm_i915_private *dev_priv,
 774                          struct drm_i915_gem_object *src)
 775 {
 776         struct drm_i915_error_object *dst;
 777         int page, page_count;
 778         u32 reloc_offset;
 779
 780         if (src == NULL || src->pages == NULL)
 781                 return NULL;
 782
 783         page_count = src->base.size / PAGE_SIZE;
 784
 785         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 786         if (dst == NULL)
 787                 return NULL;
 788
 789         reloc_offset = src->gtt_offset;
 790         for (page = 0; page < page_count; page++) {
 791                 unsigned long flags;
 792                 void *d;
 793
 794                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 795                 if (d == NULL)
 796                         goto unwind;
 797
 798                 local_irq_save(flags);
 799                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 800                     src->has_global_gtt_mapping) {
 801                         void __iomem *s;
 802
 803                         /* Simply ignore tiling or any overlapping fence.
 804                          * It's part of the error state, and this hopefully
 805                          * captures what the GPU read.
 806                          */
 807
 808                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 809                                                      reloc_offset);
 810                         memcpy_fromio(d, s, PAGE_SIZE);
 811                         io_mapping_unmap_atomic(s);
 812                 } else {
 813                         void *s;
 814
 815                         drm_clflush_pages(&src->pages[page], 1);
 816
 817                         s = kmap_atomic(src->pages[page]);
 818                         memcpy(d, s, PAGE_SIZE);
 819                         kunmap_atomic(s);
 820
 821                         drm_clflush_pages(&src->pages[page], 1);
 822                 }
 823                 local_irq_restore(flags);
 824
 825                 dst->pages[page] = d;
 826
 827                 reloc_offset += PAGE_SIZE;
 828         }
 829         dst->page_count = page_count;
 830         dst->gtt_offset = src->gtt_offset;
 831
 832         return dst;
 833
 834 unwind:
 835         while (page--)
 836                 kfree(dst->pages[page]);
 837         kfree(dst);
 838         return NULL;
 839 }
 840
 841 static void
 842 i915_error_object_free(struct drm_i915_error_object *obj)
 843 {
 844         int page;
 845
 846         if (obj == NULL)
 847                 return;
 848
 849         for (page = 0; page < obj->page_count; page++)
 850                 kfree(obj->pages[page]);
 851
 852         kfree(obj);
 853 }
 854
 855 void
 856 i915_error_state_free(struct kref *error_ref)
 857 {
 858         struct drm_i915_error_state *error = container_of(error_ref,
 859                                                           typeof(*error), ref);
 860         int i;
 861
 862         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 863                 i915_error_object_free(error->ring[i].batchbuffer);
 864                 i915_error_object_free(error->ring[i].ringbuffer);
 865                 kfree(error->ring[i].requests);
 866         }
 867
 868         kfree(error->active_bo);
 869         kfree(error->overlay);
 870         kfree(error);
 871 }
 872 static void capture_bo(struct drm_i915_error_buffer *err,
 873                        struct drm_i915_gem_object *obj)
 874 {
 875         err->size = obj->base.size;
 876         err->name = obj->base.name;
 877         err->seqno = obj->last_rendering_seqno;
 878         err->gtt_offset = obj->gtt_offset;
 879         err->read_domains = obj->base.read_domains;
 880         err->write_domain = obj->base.write_domain;
 881         err->fence_reg = obj->fence_reg;
 882         err->pinned = 0;
 883         if (obj->pin_count > 0)
 884                 err->pinned = 1;
 885         if (obj->user_pin_count > 0)
 886                 err->pinned = -1;
 887         err->tiling = obj->tiling_mode;
 888         err->dirty = obj->dirty;
 889         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 890         err->ring = obj->ring ? obj->ring->id : -1;
 891         err->cache_level = obj->cache_level;
 892 }
 893
 894 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 895                              int count, struct list_head *head)
 896 {
 897         struct drm_i915_gem_object *obj;
 898         int i = 0;
 899
 900         list_for_each_entry(obj, head, mm_list) {
 901                 capture_bo(err++, obj);
 902                 if (++i == count)
 903                         break;
 904         }
 905
 906         return i;
 907 }
 908
 909 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 910                              int count, struct list_head *head)
 911 {
 912         struct drm_i915_gem_object *obj;
 913         int i = 0;
 914
 915         list_for_each_entry(obj, head, gtt_list) {
 916                 if (obj->pin_count == 0)
 917                         continue;
 918
 919                 capture_bo(err++, obj);
 920                 if (++i == count)
 921                         break;
 922         }
 923
 924         return i;
 925 }
 926
 927 static void i915_gem_record_fences(struct drm_device *dev,
 928                                    struct drm_i915_error_state *error)
 929 {
 930         struct drm_i915_private *dev_priv = dev->dev_private;
 931         int i;
 932
 933         /* Fences */
 934         switch (INTEL_INFO(dev)->gen) {
 935         case 7:
 936         case 6:
 937                 for (i = 0; i < 16; i++)
 938                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 939                 break;
 940         case 5:
 941         case 4:
 942                 for (i = 0; i < 16; i++)
 943                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 944                 break;
 945         case 3:
 946                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 947                         for (i = 0; i < 8; i++)
 948                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 949         case 2:
 950                 for (i = 0; i < 8; i++)
 951                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 952                 break;
 953
 954         }
 955 }
 956
 957 static struct drm_i915_error_object *
 958 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 959                              struct intel_ring_buffer *ring)
 960 {
 961         struct drm_i915_gem_object *obj;
 962         u32 seqno;
 963
 964         if (!ring->get_seqno)
 965                 return NULL;
 966
 967         seqno = ring->get_seqno(ring);
 968         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 969                 if (obj->ring != ring)
 970                         continue;
 971
 972                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 973                         continue;
 974
 975                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 976                         continue;
 977
 978                 /* We need to copy these to an anonymous buffer as the simplest
 979                  * method to avoid being overwritten by userspace.
 980                  */
 981                 return i915_error_object_create(dev_priv, obj);
 982         }
 983
 984         return NULL;
 985 }
 986
 987 static void i915_record_ring_state(struct drm_device *dev,
 988                                    struct drm_i915_error_state *error,
 989                                    struct intel_ring_buffer *ring)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992
 993         if (INTEL_INFO(dev)->gen >= 6) {
 994                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
 995                 error->semaphore_mboxes[ring->id][0]
 996                         = I915_READ(RING_SYNC_0(ring->mmio_base));
 997                 error->semaphore_mboxes[ring->id][1]
 998                         = I915_READ(RING_SYNC_1(ring->mmio_base));
 999         }
1000
1001         if (INTEL_INFO(dev)->gen >= 4) {
1002                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1003                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1004                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1005                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1006                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1007                 if (ring->id == RCS) {
1008                         error->instdone1 = I915_READ(INSTDONE1);
1009                         error->bbaddr = I915_READ64(BB_ADDR);
1010                 }
1011         } else {
1012                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1013                 error->ipeir[ring->id] = I915_READ(IPEIR);
1014                 error->ipehr[ring->id] = I915_READ(IPEHR);
1015                 error->instdone[ring->id] = I915_READ(INSTDONE);
1016         }
1017
1018         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1019         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1020         error->seqno[ring->id] = ring->get_seqno(ring);
1021         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1022         error->head[ring->id] = I915_READ_HEAD(ring);
1023         error->tail[ring->id] = I915_READ_TAIL(ring);
1024
1025         error->cpu_ring_head[ring->id] = ring->head;
1026         error->cpu_ring_tail[ring->id] = ring->tail;
1027 }
1028
1029 static void i915_gem_record_rings(struct drm_device *dev,
1030                                   struct drm_i915_error_state *error)
1031 {
1032         struct drm_i915_private *dev_priv = dev->dev_private;
1033         struct intel_ring_buffer *ring;
1034         struct drm_i915_gem_request *request;
1035         int i, count;
1036
1037         for_each_ring(ring, dev_priv, i) {
1038                 i915_record_ring_state(dev, error, ring);
1039
1040                 error->ring[i].batchbuffer =
1041                         i915_error_first_batchbuffer(dev_priv, ring);
1042
1043                 error->ring[i].ringbuffer =
1044                         i915_error_object_create(dev_priv, ring->obj);
1045
1046                 count = 0;
1047                 list_for_each_entry(request, &ring->request_list, list)
1048                         count++;
1049
1050                 error->ring[i].num_requests = count;
1051                 error->ring[i].requests =
1052                         kmalloc(count*sizeof(struct drm_i915_error_request),
1053                                 GFP_ATOMIC);
1054                 if (error->ring[i].requests == NULL) {
1055                         error->ring[i].num_requests = 0;
1056                         continue;
1057                 }
1058
1059                 count = 0;
1060                 list_for_each_entry(request, &ring->request_list, list) {
1061                         struct drm_i915_error_request *erq;
1062
1063                         erq = &error->ring[i].requests[count++];
1064                         erq->seqno = request->seqno;
1065                         erq->jiffies = request->emitted_jiffies;
1066                         erq->tail = request->tail;
1067                 }
1068         }
1069 }
1070
1071 /**
1072  * i915_capture_error_state - capture an error record for later analysis
1073  * @dev: drm device
1074  *
1075  * Should be called when an error is detected (either a hang or an error
1076  * interrupt) to capture error state from the time of the error.  Fills
1077  * out a structure which becomes available in debugfs for user level tools
1078  * to pick up.
1079  */
1080 static void i915_capture_error_state(struct drm_device *dev)
1081 {
1082         struct drm_i915_private *dev_priv = dev->dev_private;
1083         struct drm_i915_gem_object *obj;
1084         struct drm_i915_error_state *error;
1085         unsigned long flags;
1086         int i, pipe;
1087
1088         spin_lock_irqsave(&dev_priv->error_lock, flags);
1089         error = dev_priv->first_error;
1090         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1091         if (error)
1092                 return;
1093
1094         /* Account for pipe specific data like PIPE*STAT */
1095         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1096         if (!error) {
1097                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1098                 return;
1099         }
1100
1101         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1102                  dev->primary->index);
1103
1104         kref_init(&error->ref);
1105         error->eir = I915_READ(EIR);
1106         error->pgtbl_er = I915_READ(PGTBL_ER);
1107
1108         if (HAS_PCH_SPLIT(dev))
1109                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1110         else if (IS_VALLEYVIEW(dev))
1111                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1112         else if (IS_GEN2(dev))
1113                 error->ier = I915_READ16(IER);
1114         else
1115                 error->ier = I915_READ(IER);
1116
1117         for_each_pipe(pipe)
1118                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1119
1120         if (INTEL_INFO(dev)->gen >= 6) {
1121                 error->error = I915_READ(ERROR_GEN6);
1122                 error->done_reg = I915_READ(DONE_REG);
1123         }
1124
1125         i915_gem_record_fences(dev, error);
1126         i915_gem_record_rings(dev, error);
1127
1128         /* Record buffers on the active and pinned lists. */
1129         error->active_bo = NULL;
1130         error->pinned_bo = NULL;
1131
1132         i = 0;
1133         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1134                 i++;
1135         error->active_bo_count = i;
1136         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1137                 if (obj->pin_count)
1138                         i++;
1139         error->pinned_bo_count = i - error->active_bo_count;
1140
1141         error->active_bo = NULL;
1142         error->pinned_bo = NULL;
1143         if (i) {
1144                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1145                                            GFP_ATOMIC);
1146                 if (error->active_bo)
1147                         error->pinned_bo =
1148                                 error->active_bo + error->active_bo_count;
1149         }
1150
1151         if (error->active_bo)
1152                 error->active_bo_count =
1153                         capture_active_bo(error->active_bo,
1154                                           error->active_bo_count,
1155                                           &dev_priv->mm.active_list);
1156
1157         if (error->pinned_bo)
1158                 error->pinned_bo_count =
1159                         capture_pinned_bo(error->pinned_bo,
1160                                           error->pinned_bo_count,
1161                                           &dev_priv->mm.gtt_list);
1162
1163         do_gettimeofday(&error->time);
1164
1165         error->overlay = intel_overlay_capture_error_state(dev);
1166         error->display = intel_display_capture_error_state(dev);
1167
1168         spin_lock_irqsave(&dev_priv->error_lock, flags);
1169         if (dev_priv->first_error == NULL) {
1170                 dev_priv->first_error = error;
1171                 error = NULL;
1172         }
1173         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1174
1175         if (error)
1176                 i915_error_state_free(&error->ref);
1177 }
1178
1179 void i915_destroy_error_state(struct drm_device *dev)
1180 {
1181         struct drm_i915_private *dev_priv = dev->dev_private;
1182         struct drm_i915_error_state *error;
1183         unsigned long flags;
1184
1185         spin_lock_irqsave(&dev_priv->error_lock, flags);
1186         error = dev_priv->first_error;
1187         dev_priv->first_error = NULL;
1188         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1189
1190         if (error)
1191                 kref_put(&error->ref, i915_error_state_free);
1192 }
1193 #else
1194 #define i915_capture_error_state(x)
1195 #endif
1196
1197 static void i915_report_and_clear_eir(struct drm_device *dev)
1198 {
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         u32 eir = I915_READ(EIR);
1201         int pipe;
1202
1203         if (!eir)
1204                 return;
1205
1206         pr_err("render error detected, EIR: 0x%08x\n", eir);
1207
1208         if (IS_G4X(dev)) {
1209                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1210                         u32 ipeir = I915_READ(IPEIR_I965);
1211
1212                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1213                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1214                         pr_err("  INSTDONE: 0x%08x\n",
1215                                I915_READ(INSTDONE_I965));
1216                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1217                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1218                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1219                         I915_WRITE(IPEIR_I965, ipeir);
1220                         POSTING_READ(IPEIR_I965);
1221                 }
1222                 if (eir & GM45_ERROR_PAGE_TABLE) {
1223                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1224                         pr_err("page table error\n");
1225                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1226                         I915_WRITE(PGTBL_ER, pgtbl_err);
1227                         POSTING_READ(PGTBL_ER);
1228                 }
1229         }
1230
1231         if (!IS_GEN2(dev)) {
1232                 if (eir & I915_ERROR_PAGE_TABLE) {
1233                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1234                         pr_err("page table error\n");
1235                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1236                         I915_WRITE(PGTBL_ER, pgtbl_err);
1237                         POSTING_READ(PGTBL_ER);
1238                 }
1239         }
1240
1241         if (eir & I915_ERROR_MEMORY_REFRESH) {
1242                 pr_err("memory refresh error:\n");
1243                 for_each_pipe(pipe)
1244                         pr_err("pipe %c stat: 0x%08x\n",
1245                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1246                 /* pipestat has already been acked */
1247         }
1248         if (eir & I915_ERROR_INSTRUCTION) {
1249                 pr_err("instruction error\n");
1250                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1251                 if (INTEL_INFO(dev)->gen < 4) {
1252                         u32 ipeir = I915_READ(IPEIR);
1253
1254                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1255                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1256                         pr_err("  INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1257                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1258                         I915_WRITE(IPEIR, ipeir);
1259                         POSTING_READ(IPEIR);
1260                 } else {
1261                         u32 ipeir = I915_READ(IPEIR_I965);
1262
1263                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1264                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1265                         pr_err("  INSTDONE: 0x%08x\n",
1266                                I915_READ(INSTDONE_I965));
1267                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1268                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1269                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1270                         I915_WRITE(IPEIR_I965, ipeir);
1271                         POSTING_READ(IPEIR_I965);
1272                 }
1273         }
1274
1275         I915_WRITE(EIR, eir);
1276         POSTING_READ(EIR);
1277         eir = I915_READ(EIR);
1278         if (eir) {
1279                 /*
1280                  * some errors might have become stuck,
1281                  * mask them.
1282                  */
1283                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1284                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1285                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1286         }
1287 }
1288
1289 /**
1290  * i915_handle_error - handle an error interrupt
1291  * @dev: drm device
1292  *
1293  * Do some basic checking of regsiter state at error interrupt time and
1294  * dump it to the syslog.  Also call i915_capture_error_state() to make
1295  * sure we get a record and make it available in debugfs.  Fire a uevent
1296  * so userspace knows something bad happened (should trigger collection
1297  * of a ring dump etc.).
1298  */
1299 void i915_handle_error(struct drm_device *dev, bool wedged)
1300 {
1301         struct drm_i915_private *dev_priv = dev->dev_private;
1302         struct intel_ring_buffer *ring;
1303         int i;
1304
1305         i915_capture_error_state(dev);
1306         i915_report_and_clear_eir(dev);
1307
1308         if (wedged) {
1309                 INIT_COMPLETION(dev_priv->error_completion);
1310                 atomic_set(&dev_priv->mm.wedged, 1);
1311
1312                 /*
1313                  * Wakeup waiting processes so they don't hang
1314                  */
1315                 for_each_ring(ring, dev_priv, i)
1316                         wake_up_all(&ring->irq_queue);
1317         }
1318
1319         queue_work(dev_priv->wq, &dev_priv->error_work);
1320 }
1321
1322 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1323 {
1324         drm_i915_private_t *dev_priv = dev->dev_private;
1325         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1327         struct drm_i915_gem_object *obj;
1328         struct intel_unpin_work *work;
1329         unsigned long flags;
1330         bool stall_detected;
1331
1332         /* Ignore early vblank irqs */
1333         if (intel_crtc == NULL)
1334                 return;
1335
1336         spin_lock_irqsave(&dev->event_lock, flags);
1337         work = intel_crtc->unpin_work;
1338
1339         if (work == NULL || work->pending || !work->enable_stall_check) {
1340                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1341                 spin_unlock_irqrestore(&dev->event_lock, flags);
1342                 return;
1343         }
1344
1345         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1346         obj = work->pending_flip_obj;
1347         if (INTEL_INFO(dev)->gen >= 4) {
1348                 int dspsurf = DSPSURF(intel_crtc->plane);
1349                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1350                                         obj->gtt_offset;
1351         } else {
1352                 int dspaddr = DSPADDR(intel_crtc->plane);
1353                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1354                                                         crtc->y * crtc->fb->pitches[0] +
1355                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1356         }
1357
1358         spin_unlock_irqrestore(&dev->event_lock, flags);
1359
1360         if (stall_detected) {
1361                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1362                 intel_prepare_page_flip(dev, intel_crtc->plane);
1363         }
1364 }
1365
1366 /* Called from drm generic code, passed 'crtc' which
1367  * we use as a pipe index
1368  */
1369 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1370 {
1371         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1372         unsigned long irqflags;
1373
1374         if (!i915_pipe_enabled(dev, pipe))
1375                 return -EINVAL;
1376
1377         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1378         if (INTEL_INFO(dev)->gen >= 4)
1379                 i915_enable_pipestat(dev_priv, pipe,
1380                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1381         else
1382                 i915_enable_pipestat(dev_priv, pipe,
1383                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1384
1385         /* maintain vblank delivery even in deep C-states */
1386         if (dev_priv->info->gen == 3)
1387                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1388         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1389
1390         return 0;
1391 }
1392
1393 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1394 {
1395         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1396         unsigned long irqflags;
1397
1398         if (!i915_pipe_enabled(dev, pipe))
1399                 return -EINVAL;
1400
1401         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1402         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1403                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1404         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1405
1406         return 0;
1407 }
1408
1409 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1410 {
1411         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1412         unsigned long irqflags;
1413
1414         if (!i915_pipe_enabled(dev, pipe))
1415                 return -EINVAL;
1416
1417         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1418         ironlake_enable_display_irq(dev_priv,
1419                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1420         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1421
1422         return 0;
1423 }
1424
1425 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1426 {
1427         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1428         unsigned long irqflags;
1429         u32 dpfl, imr;
1430
1431         if (!i915_pipe_enabled(dev, pipe))
1432                 return -EINVAL;
1433
1434         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1435         dpfl = I915_READ(VLV_DPFLIPSTAT);
1436         imr = I915_READ(VLV_IMR);
1437         if (pipe == 0) {
1438                 dpfl |= PIPEA_VBLANK_INT_EN;
1439                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1440         } else {
1441                 dpfl |= PIPEA_VBLANK_INT_EN;
1442                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1443         }
1444         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1445         I915_WRITE(VLV_IMR, imr);
1446         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1447
1448         return 0;
1449 }
1450
1451 /* Called from drm generic code, passed 'crtc' which
1452  * we use as a pipe index
1453  */
1454 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1455 {
1456         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1457         unsigned long irqflags;
1458
1459         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1460         if (dev_priv->info->gen == 3)
1461                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1462
1463         i915_disable_pipestat(dev_priv, pipe,
1464                               PIPE_VBLANK_INTERRUPT_ENABLE |
1465                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1466         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1467 }
1468
1469 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1470 {
1471         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1472         unsigned long irqflags;
1473
1474         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1475         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1476                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1477         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1478 }
1479
1480 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1481 {
1482         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1483         unsigned long irqflags;
1484
1485         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1486         ironlake_disable_display_irq(dev_priv,
1487                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1488         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1489 }
1490
1491 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1492 {
1493         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1494         unsigned long irqflags;
1495         u32 dpfl, imr;
1496
1497         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1498         dpfl = I915_READ(VLV_DPFLIPSTAT);
1499         imr = I915_READ(VLV_IMR);
1500         if (pipe == 0) {
1501                 dpfl &= ~PIPEA_VBLANK_INT_EN;
1502                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1503         } else {
1504                 dpfl &= ~PIPEB_VBLANK_INT_EN;
1505                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1506         }
1507         I915_WRITE(VLV_IMR, imr);
1508         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1509         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1510 }
1511
1512 static u32
1513 ring_last_seqno(struct intel_ring_buffer *ring)
1514 {
1515         return list_entry(ring->request_list.prev,
1516                           struct drm_i915_gem_request, list)->seqno;
1517 }
1518
1519 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1520 {
1521         if (list_empty(&ring->request_list) ||
1522             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1523                 /* Issue a wake-up to catch stuck h/w. */
1524                 if (waitqueue_active(&ring->irq_queue)) {
1525                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1526                                   ring->name);
1527                         wake_up_all(&ring->irq_queue);
1528                         *err = true;
1529                 }
1530                 return true;
1531         }
1532         return false;
1533 }
1534
1535 static bool kick_ring(struct intel_ring_buffer *ring)
1536 {
1537         struct drm_device *dev = ring->dev;
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         u32 tmp = I915_READ_CTL(ring);
1540         if (tmp & RING_WAIT) {
1541                 DRM_ERROR("Kicking stuck wait on %s\n",
1542                           ring->name);
1543                 I915_WRITE_CTL(ring, tmp);
1544                 return true;
1545         }
1546         return false;
1547 }
1548
1549 static bool i915_hangcheck_hung(struct drm_device *dev)
1550 {
1551         drm_i915_private_t *dev_priv = dev->dev_private;
1552
1553         if (dev_priv->hangcheck_count++ > 1) {
1554                 bool hung = true;
1555
1556                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1557                 i915_handle_error(dev, true);
1558
1559                 if (!IS_GEN2(dev)) {
1560                         struct intel_ring_buffer *ring;
1561                         int i;
1562
1563                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1564                          * If so we can simply poke the RB_WAIT bit
1565                          * and break the hang. This should work on
1566                          * all but the second generation chipsets.
1567                          */
1568                         for_each_ring(ring, dev_priv, i)
1569                                 hung &= !kick_ring(ring);
1570                 }
1571
1572                 return hung;
1573         }
1574
1575         return false;
1576 }
1577
1578 /**
1579  * This is called when the chip hasn't reported back with completed
1580  * batchbuffers in a long time. The first time this is called we simply record
1581  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1582  * again, we assume the chip is wedged and try to fix it.
1583  */
1584 void i915_hangcheck_elapsed(unsigned long data)
1585 {
1586         struct drm_device *dev = (struct drm_device *)data;
1587         drm_i915_private_t *dev_priv = dev->dev_private;
1588         uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1589         struct intel_ring_buffer *ring;
1590         bool err = false, idle;
1591         int i;
1592
1593         if (!i915_enable_hangcheck)
1594                 return;
1595
1596         memset(acthd, 0, sizeof(acthd));
1597         idle = true;
1598         for_each_ring(ring, dev_priv, i) {
1599             idle &= i915_hangcheck_ring_idle(ring, &err);
1600             acthd[i] = intel_ring_get_active_head(ring);
1601         }
1602
1603         /* If all work is done then ACTHD clearly hasn't advanced. */
1604         if (idle) {
1605                 if (err) {
1606                         if (i915_hangcheck_hung(dev))
1607                                 return;
1608
1609                         goto repeat;
1610                 }
1611
1612                 dev_priv->hangcheck_count = 0;
1613                 return;
1614         }
1615
1616         if (INTEL_INFO(dev)->gen < 4) {
1617                 instdone = I915_READ(INSTDONE);
1618                 instdone1 = 0;
1619         } else {
1620                 instdone = I915_READ(INSTDONE_I965);
1621                 instdone1 = I915_READ(INSTDONE1);
1622         }
1623
1624         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1625             dev_priv->last_instdone == instdone &&
1626             dev_priv->last_instdone1 == instdone1) {
1627                 if (i915_hangcheck_hung(dev))
1628                         return;
1629         } else {
1630                 dev_priv->hangcheck_count = 0;
1631
1632                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1633                 dev_priv->last_instdone = instdone;
1634                 dev_priv->last_instdone1 = instdone1;
1635         }
1636
1637 repeat:
1638         /* Reset timer case chip hangs without another request being added */
1639         mod_timer(&dev_priv->hangcheck_timer,
1640                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1641 }
1642
1643 /* drm_dma.h hooks
1644 */
1645 static void ironlake_irq_preinstall(struct drm_device *dev)
1646 {
1647         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1648
1649         atomic_set(&dev_priv->irq_received, 0);
1650
1651
1652         I915_WRITE(HWSTAM, 0xeffe);
1653
1654         /* XXX hotplug from PCH */
1655
1656         I915_WRITE(DEIMR, 0xffffffff);
1657         I915_WRITE(DEIER, 0x0);
1658         POSTING_READ(DEIER);
1659
1660         /* and GT */
1661         I915_WRITE(GTIMR, 0xffffffff);
1662         I915_WRITE(GTIER, 0x0);
1663         POSTING_READ(GTIER);
1664
1665         /* south display irq */
1666         I915_WRITE(SDEIMR, 0xffffffff);
1667         I915_WRITE(SDEIER, 0x0);
1668         POSTING_READ(SDEIER);
1669 }
1670
1671 static void valleyview_irq_preinstall(struct drm_device *dev)
1672 {
1673         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1674         int pipe;
1675
1676         atomic_set(&dev_priv->irq_received, 0);
1677
1678         /* VLV magic */
1679         I915_WRITE(VLV_IMR, 0);
1680         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1681         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1682         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1683
1684         /* and GT */
1685         I915_WRITE(GTIIR, I915_READ(GTIIR));
1686         I915_WRITE(GTIIR, I915_READ(GTIIR));
1687         I915_WRITE(GTIMR, 0xffffffff);
1688         I915_WRITE(GTIER, 0x0);
1689         POSTING_READ(GTIER);
1690
1691         I915_WRITE(DPINVGTT, 0xff);
1692
1693         I915_WRITE(PORT_HOTPLUG_EN, 0);
1694         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1695         for_each_pipe(pipe)
1696                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1697         I915_WRITE(VLV_IIR, 0xffffffff);
1698         I915_WRITE(VLV_IMR, 0xffffffff);
1699         I915_WRITE(VLV_IER, 0x0);
1700         POSTING_READ(VLV_IER);
1701 }
1702
1703 /*
1704  * Enable digital hotplug on the PCH, and configure the DP short pulse
1705  * duration to 2ms (which is the minimum in the Display Port spec)
1706  *
1707  * This register is the same on all known PCH chips.
1708  */
1709
1710 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1711 {
1712         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1713         u32     hotplug;
1714
1715         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1716         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1717         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1718         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1719         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1720         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1721 }
1722
1723 static int ironlake_irq_postinstall(struct drm_device *dev)
1724 {
1725         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1726         /* enable kind of interrupts always enabled */
1727         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1728                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1729         u32 render_irqs;
1730         u32 hotplug_mask;
1731
1732         dev_priv->irq_mask = ~display_mask;
1733
1734         /* should always can generate irq */
1735         I915_WRITE(DEIIR, I915_READ(DEIIR));
1736         I915_WRITE(DEIMR, dev_priv->irq_mask);
1737         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1738         POSTING_READ(DEIER);
1739
1740         dev_priv->gt_irq_mask = ~0;
1741
1742         I915_WRITE(GTIIR, I915_READ(GTIIR));
1743         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1744
1745         if (IS_GEN6(dev))
1746                 render_irqs =
1747                         GT_USER_INTERRUPT |
1748                         GEN6_BSD_USER_INTERRUPT |
1749                         GEN6_BLITTER_USER_INTERRUPT;
1750         else
1751                 render_irqs =
1752                         GT_USER_INTERRUPT |
1753                         GT_PIPE_NOTIFY |
1754                         GT_BSD_USER_INTERRUPT;
1755         I915_WRITE(GTIER, render_irqs);
1756         POSTING_READ(GTIER);
1757
1758         if (HAS_PCH_CPT(dev)) {
1759                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1760                                 SDE_PORTB_HOTPLUG_CPT |
1761                                 SDE_PORTC_HOTPLUG_CPT |
1762                                 SDE_PORTD_HOTPLUG_CPT);
1763         } else {
1764                 hotplug_mask = (SDE_CRT_HOTPLUG |
1765                                 SDE_PORTB_HOTPLUG |
1766                                 SDE_PORTC_HOTPLUG |
1767                                 SDE_PORTD_HOTPLUG |
1768                                 SDE_AUX_MASK);
1769         }
1770
1771         dev_priv->pch_irq_mask = ~hotplug_mask;
1772
1773         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1774         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1775         I915_WRITE(SDEIER, hotplug_mask);
1776         POSTING_READ(SDEIER);
1777
1778         ironlake_enable_pch_hotplug(dev);
1779
1780         if (IS_IRONLAKE_M(dev)) {
1781                 /* Clear & enable PCU event interrupts */
1782                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1783                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1784                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1785         }
1786
1787         return 0;
1788 }
1789
1790 static int ivybridge_irq_postinstall(struct drm_device *dev)
1791 {
1792         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1793         /* enable kind of interrupts always enabled */
1794         u32 display_mask =
1795                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1796                 DE_PLANEC_FLIP_DONE_IVB |
1797                 DE_PLANEB_FLIP_DONE_IVB |
1798                 DE_PLANEA_FLIP_DONE_IVB;
1799         u32 render_irqs;
1800         u32 hotplug_mask;
1801
1802         dev_priv->irq_mask = ~display_mask;
1803
1804         /* should always can generate irq */
1805         I915_WRITE(DEIIR, I915_READ(DEIIR));
1806         I915_WRITE(DEIMR, dev_priv->irq_mask);
1807         I915_WRITE(DEIER,
1808                    display_mask |
1809                    DE_PIPEC_VBLANK_IVB |
1810                    DE_PIPEB_VBLANK_IVB |
1811                    DE_PIPEA_VBLANK_IVB);
1812         POSTING_READ(DEIER);
1813
1814         dev_priv->gt_irq_mask = ~0;
1815
1816         I915_WRITE(GTIIR, I915_READ(GTIIR));
1817         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1818
1819         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1820                 GEN6_BLITTER_USER_INTERRUPT;
1821         I915_WRITE(GTIER, render_irqs);
1822         POSTING_READ(GTIER);
1823
1824         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1825                         SDE_PORTB_HOTPLUG_CPT |
1826                         SDE_PORTC_HOTPLUG_CPT |
1827                         SDE_PORTD_HOTPLUG_CPT);
1828         dev_priv->pch_irq_mask = ~hotplug_mask;
1829
1830         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1831         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1832         I915_WRITE(SDEIER, hotplug_mask);
1833         POSTING_READ(SDEIER);
1834
1835         ironlake_enable_pch_hotplug(dev);
1836
1837         return 0;
1838 }
1839
1840 static int valleyview_irq_postinstall(struct drm_device *dev)
1841 {
1842         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1843         u32 render_irqs;
1844         u32 enable_mask;
1845         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1846         u16 msid;
1847
1848         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1849         enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1850                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1851
1852         dev_priv->irq_mask = ~enable_mask;
1853
1854         dev_priv->pipestat[0] = 0;
1855         dev_priv->pipestat[1] = 0;
1856
1857         /* Hack for broken MSIs on VLV */
1858         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1859         pci_read_config_word(dev->pdev, 0x98, &msid);
1860         msid &= 0xff; /* mask out delivery bits */
1861         msid |= (1<<14);
1862         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1863
1864         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1865         I915_WRITE(VLV_IER, enable_mask);
1866         I915_WRITE(VLV_IIR, 0xffffffff);
1867         I915_WRITE(PIPESTAT(0), 0xffff);
1868         I915_WRITE(PIPESTAT(1), 0xffff);
1869         POSTING_READ(VLV_IER);
1870
1871         I915_WRITE(VLV_IIR, 0xffffffff);
1872         I915_WRITE(VLV_IIR, 0xffffffff);
1873
1874         render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1875                 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1876                 GT_GEN6_BLT_USER_INTERRUPT |
1877                 GT_GEN6_BSD_USER_INTERRUPT |
1878                 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1879                 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1880                 GT_PIPE_NOTIFY |
1881                 GT_RENDER_CS_ERROR_INTERRUPT |
1882                 GT_SYNC_STATUS |
1883                 GT_USER_INTERRUPT;
1884
1885         dev_priv->gt_irq_mask = ~render_irqs;
1886
1887         I915_WRITE(GTIIR, I915_READ(GTIIR));
1888         I915_WRITE(GTIIR, I915_READ(GTIIR));
1889         I915_WRITE(GTIMR, 0);
1890         I915_WRITE(GTIER, render_irqs);
1891         POSTING_READ(GTIER);
1892
1893         /* ack & enable invalid PTE error interrupts */
1894 #if 0 /* FIXME: add support to irq handler for checking these bits */
1895         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1896         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1897 #endif
1898
1899         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1900 #if 0 /* FIXME: check register definitions; some have moved */
1901         /* Note HDMI and DP share bits */
1902         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1903                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1904         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1905                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1906         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1907                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1908         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1909                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1910         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1911                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1912         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1913                 hotplug_en |= CRT_HOTPLUG_INT_EN;
1914                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1915         }
1916 #endif
1917
1918         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1919
1920         return 0;
1921 }
1922
1923 static void valleyview_irq_uninstall(struct drm_device *dev)
1924 {
1925         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1926         int pipe;
1927
1928         if (!dev_priv)
1929                 return;
1930
1931         for_each_pipe(pipe)
1932                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1933
1934         I915_WRITE(HWSTAM, 0xffffffff);
1935         I915_WRITE(PORT_HOTPLUG_EN, 0);
1936         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1937         for_each_pipe(pipe)
1938                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1939         I915_WRITE(VLV_IIR, 0xffffffff);
1940         I915_WRITE(VLV_IMR, 0xffffffff);
1941         I915_WRITE(VLV_IER, 0x0);
1942         POSTING_READ(VLV_IER);
1943 }
1944
1945 static void ironlake_irq_uninstall(struct drm_device *dev)
1946 {
1947         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1948
1949         if (!dev_priv)
1950                 return;
1951
1952         I915_WRITE(HWSTAM, 0xffffffff);
1953
1954         I915_WRITE(DEIMR, 0xffffffff);
1955         I915_WRITE(DEIER, 0x0);
1956         I915_WRITE(DEIIR, I915_READ(DEIIR));
1957
1958         I915_WRITE(GTIMR, 0xffffffff);
1959         I915_WRITE(GTIER, 0x0);
1960         I915_WRITE(GTIIR, I915_READ(GTIIR));
1961
1962         I915_WRITE(SDEIMR, 0xffffffff);
1963         I915_WRITE(SDEIER, 0x0);
1964         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1965 }
1966
1967 static void i8xx_irq_preinstall(struct drm_device * dev)
1968 {
1969         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1970         int pipe;
1971
1972         atomic_set(&dev_priv->irq_received, 0);
1973
1974         for_each_pipe(pipe)
1975                 I915_WRITE(PIPESTAT(pipe), 0);
1976         I915_WRITE16(IMR, 0xffff);
1977         I915_WRITE16(IER, 0x0);
1978         POSTING_READ16(IER);
1979 }
1980
1981 static int i8xx_irq_postinstall(struct drm_device *dev)
1982 {
1983         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1984
1985         dev_priv->pipestat[0] = 0;
1986         dev_priv->pipestat[1] = 0;
1987
1988         I915_WRITE16(EMR,
1989                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1990
1991         /* Unmask the interrupts that we always want on. */
1992         dev_priv->irq_mask =
1993                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1994                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1995                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1996                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
1997                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1998         I915_WRITE16(IMR, dev_priv->irq_mask);
1999
2000         I915_WRITE16(IER,
2001                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2002                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2003                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2004                      I915_USER_INTERRUPT);
2005         POSTING_READ16(IER);
2006
2007         return 0;
2008 }
2009
2010 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2011 {
2012         struct drm_device *dev = (struct drm_device *) arg;
2013         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2014         u16 iir, new_iir;
2015         u32 pipe_stats[2];
2016         unsigned long irqflags;
2017         int irq_received;
2018         int pipe;
2019         u16 flip_mask =
2020                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2021                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2022
2023         atomic_inc(&dev_priv->irq_received);
2024
2025         iir = I915_READ16(IIR);
2026         if (iir == 0)
2027                 return IRQ_NONE;
2028
2029         while (iir & ~flip_mask) {
2030                 /* Can't rely on pipestat interrupt bit in iir as it might
2031                  * have been cleared after the pipestat interrupt was received.
2032                  * It doesn't set the bit in iir again, but it still produces
2033                  * interrupts (for non-MSI).
2034                  */
2035                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2036                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2037                         i915_handle_error(dev, false);
2038
2039                 for_each_pipe(pipe) {
2040                         int reg = PIPESTAT(pipe);
2041                         pipe_stats[pipe] = I915_READ(reg);
2042
2043                         /*
2044                          * Clear the PIPE*STAT regs before the IIR
2045                          */
2046                         if (pipe_stats[pipe] & 0x8000ffff) {
2047                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2048                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2049                                                          pipe_name(pipe));
2050                                 I915_WRITE(reg, pipe_stats[pipe]);
2051                                 irq_received = 1;
2052                         }
2053                 }
2054                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2055
2056                 I915_WRITE16(IIR, iir & ~flip_mask);
2057                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2058
2059                 i915_update_dri1_breadcrumb(dev);
2060
2061                 if (iir & I915_USER_INTERRUPT)
2062                         notify_ring(dev, &dev_priv->ring[RCS]);
2063
2064                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2065                     drm_handle_vblank(dev, 0)) {
2066                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2067                                 intel_prepare_page_flip(dev, 0);
2068                                 intel_finish_page_flip(dev, 0);
2069                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2070                         }
2071                 }
2072
2073                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2074                     drm_handle_vblank(dev, 1)) {
2075                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2076                                 intel_prepare_page_flip(dev, 1);
2077                                 intel_finish_page_flip(dev, 1);
2078                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2079                         }
2080                 }
2081
2082                 iir = new_iir;
2083         }
2084
2085         return IRQ_HANDLED;
2086 }
2087
2088 static void i8xx_irq_uninstall(struct drm_device * dev)
2089 {
2090         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2091         int pipe;
2092
2093         for_each_pipe(pipe) {
2094                 /* Clear enable bits; then clear status bits */
2095                 I915_WRITE(PIPESTAT(pipe), 0);
2096                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2097         }
2098         I915_WRITE16(IMR, 0xffff);
2099         I915_WRITE16(IER, 0x0);
2100         I915_WRITE16(IIR, I915_READ16(IIR));
2101 }
2102
2103 static void i915_irq_preinstall(struct drm_device * dev)
2104 {
2105         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2106         int pipe;
2107
2108         atomic_set(&dev_priv->irq_received, 0);
2109
2110         if (I915_HAS_HOTPLUG(dev)) {
2111                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2112                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2113         }
2114
2115         I915_WRITE16(HWSTAM, 0xeffe);
2116         for_each_pipe(pipe)
2117                 I915_WRITE(PIPESTAT(pipe), 0);
2118         I915_WRITE(IMR, 0xffffffff);
2119         I915_WRITE(IER, 0x0);
2120         POSTING_READ(IER);
2121 }
2122
2123 static int i915_irq_postinstall(struct drm_device *dev)
2124 {
2125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2126         u32 enable_mask;
2127
2128         dev_priv->pipestat[0] = 0;
2129         dev_priv->pipestat[1] = 0;
2130
2131         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2132
2133         /* Unmask the interrupts that we always want on. */
2134         dev_priv->irq_mask =
2135                 ~(I915_ASLE_INTERRUPT |
2136                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2137                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2138                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2139                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2140                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2141
2142         enable_mask =
2143                 I915_ASLE_INTERRUPT |
2144                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2145                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2146                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2147                 I915_USER_INTERRUPT;
2148
2149         if (I915_HAS_HOTPLUG(dev)) {
2150                 /* Enable in IER... */
2151                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2152                 /* and unmask in IMR */
2153                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2154         }
2155
2156         I915_WRITE(IMR, dev_priv->irq_mask);
2157         I915_WRITE(IER, enable_mask);
2158         POSTING_READ(IER);
2159
2160         if (I915_HAS_HOTPLUG(dev)) {
2161                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2162
2163                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2164                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2165                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2166                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2167                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2168                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2169                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2170                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2171                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2172                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2173                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2174                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2175                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2176                 }
2177
2178                 /* Ignore TV since it's buggy */
2179
2180                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2181         }
2182
2183         intel_opregion_enable_asle(dev);
2184
2185         return 0;
2186 }
2187
2188 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2189 {
2190         struct drm_device *dev = (struct drm_device *) arg;
2191         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2192         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2193         unsigned long irqflags;
2194         u32 flip_mask =
2195                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2196                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2197         u32 flip[2] = {
2198                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2199                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2200         };
2201         int pipe, ret = IRQ_NONE;
2202
2203         atomic_inc(&dev_priv->irq_received);
2204
2205         iir = I915_READ(IIR);
2206         do {
2207                 bool irq_received = (iir & ~flip_mask) != 0;
2208                 bool blc_event = false;
2209
2210                 /* Can't rely on pipestat interrupt bit in iir as it might
2211                  * have been cleared after the pipestat interrupt was received.
2212                  * It doesn't set the bit in iir again, but it still produces
2213                  * interrupts (for non-MSI).
2214                  */
2215                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2216                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2217                         i915_handle_error(dev, false);
2218
2219                 for_each_pipe(pipe) {
2220                         int reg = PIPESTAT(pipe);
2221                         pipe_stats[pipe] = I915_READ(reg);
2222
2223                         /* Clear the PIPE*STAT regs before the IIR */
2224                         if (pipe_stats[pipe] & 0x8000ffff) {
2225                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2226                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2227                                                          pipe_name(pipe));
2228                                 I915_WRITE(reg, pipe_stats[pipe]);
2229                                 irq_received = true;
2230                         }
2231                 }
2232                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2233
2234                 if (!irq_received)
2235                         break;
2236
2237                 /* Consume port.  Then clear IIR or we'll miss events */
2238                 if ((I915_HAS_HOTPLUG(dev)) &&
2239                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2240                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2241
2242                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2243                                   hotplug_status);
2244                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2245                                 queue_work(dev_priv->wq,
2246                                            &dev_priv->hotplug_work);
2247
2248                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2249                         POSTING_READ(PORT_HOTPLUG_STAT);
2250                 }
2251
2252                 I915_WRITE(IIR, iir & ~flip_mask);
2253                 new_iir = I915_READ(IIR); /* Flush posted writes */
2254
2255                 if (iir & I915_USER_INTERRUPT)
2256                         notify_ring(dev, &dev_priv->ring[RCS]);
2257
2258                 for_each_pipe(pipe) {
2259                         int plane = pipe;
2260                         if (IS_MOBILE(dev))
2261                                 plane = !plane;
2262                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2263                             drm_handle_vblank(dev, pipe)) {
2264                                 if (iir & flip[plane]) {
2265                                         intel_prepare_page_flip(dev, plane);
2266                                         intel_finish_page_flip(dev, pipe);
2267                                         flip_mask &= ~flip[plane];
2268                                 }
2269                         }
2270
2271                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2272                                 blc_event = true;
2273                 }
2274
2275                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2276                         intel_opregion_asle_intr(dev);
2277
2278                 /* With MSI, interrupts are only generated when iir
2279                  * transitions from zero to nonzero.  If another bit got
2280                  * set while we were handling the existing iir bits, then
2281                  * we would never get another interrupt.
2282                  *
2283                  * This is fine on non-MSI as well, as if we hit this path
2284                  * we avoid exiting the interrupt handler only to generate
2285                  * another one.
2286                  *
2287                  * Note that for MSI this could cause a stray interrupt report
2288                  * if an interrupt landed in the time between writing IIR and
2289                  * the posting read.  This should be rare enough to never
2290                  * trigger the 99% of 100,000 interrupts test for disabling
2291                  * stray interrupts.
2292                  */
2293                 ret = IRQ_HANDLED;
2294                 iir = new_iir;
2295         } while (iir & ~flip_mask);
2296
2297         i915_update_dri1_breadcrumb(dev);
2298
2299         return ret;
2300 }
2301
2302 static void i915_irq_uninstall(struct drm_device * dev)
2303 {
2304         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2305         int pipe;
2306
2307         if (I915_HAS_HOTPLUG(dev)) {
2308                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2309                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2310         }
2311
2312         I915_WRITE16(HWSTAM, 0xffff);
2313         for_each_pipe(pipe) {
2314                 /* Clear enable bits; then clear status bits */
2315                 I915_WRITE(PIPESTAT(pipe), 0);
2316                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2317         }
2318         I915_WRITE(IMR, 0xffffffff);
2319         I915_WRITE(IER, 0x0);
2320
2321         I915_WRITE(IIR, I915_READ(IIR));
2322 }
2323
2324 static void i965_irq_preinstall(struct drm_device * dev)
2325 {
2326         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2327         int pipe;
2328
2329         atomic_set(&dev_priv->irq_received, 0);
2330
2331         if (I915_HAS_HOTPLUG(dev)) {
2332                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2333                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2334         }
2335
2336         I915_WRITE(HWSTAM, 0xeffe);
2337         for_each_pipe(pipe)
2338                 I915_WRITE(PIPESTAT(pipe), 0);
2339         I915_WRITE(IMR, 0xffffffff);
2340         I915_WRITE(IER, 0x0);
2341         POSTING_READ(IER);
2342 }
2343
2344 static int i965_irq_postinstall(struct drm_device *dev)
2345 {
2346         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2347         u32 enable_mask;
2348         u32 error_mask;
2349
2350         /* Unmask the interrupts that we always want on. */
2351         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2352                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2353                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2354                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2355                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2356                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2357
2358         enable_mask = ~dev_priv->irq_mask;
2359         enable_mask |= I915_USER_INTERRUPT;
2360
2361         if (IS_G4X(dev))
2362                 enable_mask |= I915_BSD_USER_INTERRUPT;
2363
2364         dev_priv->pipestat[0] = 0;
2365         dev_priv->pipestat[1] = 0;
2366
2367         if (I915_HAS_HOTPLUG(dev)) {
2368                 /* Enable in IER... */
2369                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2370                 /* and unmask in IMR */
2371                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2372         }
2373
2374         /*
2375          * Enable some error detection, note the instruction error mask
2376          * bit is reserved, so we leave it masked.
2377          */
2378         if (IS_G4X(dev)) {
2379                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2380                                GM45_ERROR_MEM_PRIV |
2381                                GM45_ERROR_CP_PRIV |
2382                                I915_ERROR_MEMORY_REFRESH);
2383         } else {
2384                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2385                                I915_ERROR_MEMORY_REFRESH);
2386         }
2387         I915_WRITE(EMR, error_mask);
2388
2389         I915_WRITE(IMR, dev_priv->irq_mask);
2390         I915_WRITE(IER, enable_mask);
2391         POSTING_READ(IER);
2392
2393         if (I915_HAS_HOTPLUG(dev)) {
2394                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2395
2396                 /* Note HDMI and DP share bits */
2397                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2398                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2399                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2400                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2401                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2402                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2403                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2404                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2405                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2406                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2407                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2408                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2409
2410                         /* Programming the CRT detection parameters tends
2411                            to generate a spurious hotplug event about three
2412                            seconds later.  So just do it once.
2413                         */
2414                         if (IS_G4X(dev))
2415                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2416                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2417                 }
2418
2419                 /* Ignore TV since it's buggy */
2420
2421                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2422         }
2423
2424         intel_opregion_enable_asle(dev);
2425
2426         return 0;
2427 }
2428
2429 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2430 {
2431         struct drm_device *dev = (struct drm_device *) arg;
2432         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2433         u32 iir, new_iir;
2434         u32 pipe_stats[I915_MAX_PIPES];
2435         unsigned long irqflags;
2436         int irq_received;
2437         int ret = IRQ_NONE, pipe;
2438
2439         atomic_inc(&dev_priv->irq_received);
2440
2441         iir = I915_READ(IIR);
2442
2443         for (;;) {
2444                 bool blc_event = false;
2445
2446                 irq_received = iir != 0;
2447
2448                 /* Can't rely on pipestat interrupt bit in iir as it might
2449                  * have been cleared after the pipestat interrupt was received.
2450                  * It doesn't set the bit in iir again, but it still produces
2451                  * interrupts (for non-MSI).
2452                  */
2453                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2454                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2455                         i915_handle_error(dev, false);
2456
2457                 for_each_pipe(pipe) {
2458                         int reg = PIPESTAT(pipe);
2459                         pipe_stats[pipe] = I915_READ(reg);
2460
2461                         /*
2462                          * Clear the PIPE*STAT regs before the IIR
2463                          */
2464                         if (pipe_stats[pipe] & 0x8000ffff) {
2465                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2466                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2467                                                          pipe_name(pipe));
2468                                 I915_WRITE(reg, pipe_stats[pipe]);
2469                                 irq_received = 1;
2470                         }
2471                 }
2472                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2473
2474                 if (!irq_received)
2475                         break;
2476
2477                 ret = IRQ_HANDLED;
2478
2479                 /* Consume port.  Then clear IIR or we'll miss events */
2480                 if ((I915_HAS_HOTPLUG(dev)) &&
2481                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2482                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2483
2484                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2485                                   hotplug_status);
2486                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2487                                 queue_work(dev_priv->wq,
2488                                            &dev_priv->hotplug_work);
2489
2490                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2491                         I915_READ(PORT_HOTPLUG_STAT);
2492                 }
2493
2494                 I915_WRITE(IIR, iir);
2495                 new_iir = I915_READ(IIR); /* Flush posted writes */
2496
2497                 if (iir & I915_USER_INTERRUPT)
2498                         notify_ring(dev, &dev_priv->ring[RCS]);
2499                 if (iir & I915_BSD_USER_INTERRUPT)
2500                         notify_ring(dev, &dev_priv->ring[VCS]);
2501
2502                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2503                         intel_prepare_page_flip(dev, 0);
2504
2505                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2506                         intel_prepare_page_flip(dev, 1);
2507
2508                 for_each_pipe(pipe) {
2509                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2510                             drm_handle_vblank(dev, pipe)) {
2511                                 i915_pageflip_stall_check(dev, pipe);
2512                                 intel_finish_page_flip(dev, pipe);
2513                         }
2514
2515                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2516                                 blc_event = true;
2517                 }
2518
2519
2520                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2521                         intel_opregion_asle_intr(dev);
2522
2523                 /* With MSI, interrupts are only generated when iir
2524                  * transitions from zero to nonzero.  If another bit got
2525                  * set while we were handling the existing iir bits, then
2526                  * we would never get another interrupt.
2527                  *
2528                  * This is fine on non-MSI as well, as if we hit this path
2529                  * we avoid exiting the interrupt handler only to generate
2530                  * another one.
2531                  *
2532                  * Note that for MSI this could cause a stray interrupt report
2533                  * if an interrupt landed in the time between writing IIR and
2534                  * the posting read.  This should be rare enough to never
2535                  * trigger the 99% of 100,000 interrupts test for disabling
2536                  * stray interrupts.
2537                  */
2538                 iir = new_iir;
2539         }
2540
2541         i915_update_dri1_breadcrumb(dev);
2542
2543         return ret;
2544 }
2545
2546 static void i965_irq_uninstall(struct drm_device * dev)
2547 {
2548         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2549         int pipe;
2550
2551         if (!dev_priv)
2552                 return;
2553
2554         if (I915_HAS_HOTPLUG(dev)) {
2555                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2556                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2557         }
2558
2559         I915_WRITE(HWSTAM, 0xffffffff);
2560         for_each_pipe(pipe)
2561                 I915_WRITE(PIPESTAT(pipe), 0);
2562         I915_WRITE(IMR, 0xffffffff);
2563         I915_WRITE(IER, 0x0);
2564
2565         for_each_pipe(pipe)
2566                 I915_WRITE(PIPESTAT(pipe),
2567                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2568         I915_WRITE(IIR, I915_READ(IIR));
2569 }
2570
2571 void intel_irq_init(struct drm_device *dev)
2572 {
2573         struct drm_i915_private *dev_priv = dev->dev_private;
2574
2575         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2576         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2577         INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2578
2579         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2580         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2581         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2582                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2583                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2584         }
2585
2586         if (drm_core_check_feature(dev, DRIVER_MODESET))
2587                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2588         else
2589                 dev->driver->get_vblank_timestamp = NULL;
2590         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2591
2592         if (IS_VALLEYVIEW(dev)) {
2593                 dev->driver->irq_handler = valleyview_irq_handler;
2594                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2595                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2596                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2597                 dev->driver->enable_vblank = valleyview_enable_vblank;
2598                 dev->driver->disable_vblank = valleyview_disable_vblank;
2599         } else if (IS_IVYBRIDGE(dev)) {
2600                 /* Share pre & uninstall handlers with ILK/SNB */
2601                 dev->driver->irq_handler = ivybridge_irq_handler;
2602                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2603                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2604                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2605                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2606                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2607         } else if (IS_HASWELL(dev)) {
2608                 /* Share interrupts handling with IVB */
2609                 dev->driver->irq_handler = ivybridge_irq_handler;
2610                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2611                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2612                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2613                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2614                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2615         } else if (HAS_PCH_SPLIT(dev)) {
2616                 dev->driver->irq_handler = ironlake_irq_handler;
2617                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2618                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2619                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2620                 dev->driver->enable_vblank = ironlake_enable_vblank;
2621                 dev->driver->disable_vblank = ironlake_disable_vblank;
2622         } else {
2623                 if (INTEL_INFO(dev)->gen == 2) {
2624                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2625                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2626                         dev->driver->irq_handler = i8xx_irq_handler;
2627                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2628                 } else if (INTEL_INFO(dev)->gen == 3) {
2629                         /* IIR "flip pending" means done if this bit is set */
2630                         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2631
2632                         dev->driver->irq_preinstall = i915_irq_preinstall;
2633                         dev->driver->irq_postinstall = i915_irq_postinstall;
2634                         dev->driver->irq_uninstall = i915_irq_uninstall;
2635                         dev->driver->irq_handler = i915_irq_handler;
2636                 } else {
2637                         dev->driver->irq_preinstall = i965_irq_preinstall;
2638                         dev->driver->irq_postinstall = i965_irq_postinstall;
2639                         dev->driver->irq_uninstall = i965_irq_uninstall;
2640                         dev->driver->irq_handler = i965_irq_handler;
2641                 }
2642                 dev->driver->enable_vblank = i915_enable_vblank;
2643                 dev->driver->disable_vblank = i915_disable_vblank;
2644         }
2645 }