1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
145 u32 val = I915_READ(reg);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg), val);
152 I915_WRITE(reg, 0xffffffff);
154 I915_WRITE(reg, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
182 assert_spin_locked(&dev_priv->irq_lock);
183 WARN_ON(bits & ~mask);
185 val = I915_READ(PORT_HOTPLUG_EN);
188 I915_WRITE(PORT_HOTPLUG_EN, val);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
207 spin_lock_irq(&dev_priv->irq_lock);
208 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
209 spin_unlock_irq(&dev_priv->irq_lock);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
219 uint32_t interrupt_mask,
220 uint32_t enabled_irq_mask)
224 assert_spin_locked(&dev_priv->irq_lock);
226 WARN_ON(enabled_irq_mask & ~interrupt_mask);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
231 new_val = dev_priv->irq_mask;
232 new_val &= ~interrupt_mask;
233 new_val |= (~enabled_irq_mask & interrupt_mask);
235 if (new_val != dev_priv->irq_mask) {
236 dev_priv->irq_mask = new_val;
237 I915_WRITE(DEIMR, dev_priv->irq_mask);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
249 uint32_t interrupt_mask,
250 uint32_t enabled_irq_mask)
252 assert_spin_locked(&dev_priv->irq_lock);
254 WARN_ON(enabled_irq_mask & ~interrupt_mask);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
267 ilk_update_gt_irq(dev_priv, mask, mask);
270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
272 ilk_update_gt_irq(dev_priv, mask, 0);
275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
277 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
282 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
287 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
297 uint32_t interrupt_mask,
298 uint32_t enabled_irq_mask)
302 WARN_ON(enabled_irq_mask & ~interrupt_mask);
304 assert_spin_locked(&dev_priv->irq_lock);
306 new_val = dev_priv->pm_irq_mask;
307 new_val &= ~interrupt_mask;
308 new_val |= (~enabled_irq_mask & interrupt_mask);
310 if (new_val != dev_priv->pm_irq_mask) {
311 dev_priv->pm_irq_mask = new_val;
312 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
313 POSTING_READ(gen6_pm_imr(dev_priv));
317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
322 snb_update_pm_irq(dev_priv, mask, mask);
325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
328 snb_update_pm_irq(dev_priv, mask, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
336 __gen6_disable_pm_irq(dev_priv, mask);
339 void gen6_reset_rps_interrupts(struct drm_device *dev)
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 i915_reg_t reg = gen6_pm_iir(dev_priv);
344 spin_lock_irq(&dev_priv->irq_lock);
345 I915_WRITE(reg, dev_priv->pm_rps_events);
346 I915_WRITE(reg, dev_priv->pm_rps_events);
348 dev_priv->rps.pm_iir = 0;
349 spin_unlock_irq(&dev_priv->irq_lock);
352 void gen6_enable_rps_interrupts(struct drm_device *dev)
354 struct drm_i915_private *dev_priv = dev->dev_private;
356 spin_lock_irq(&dev_priv->irq_lock);
358 WARN_ON(dev_priv->rps.pm_iir);
359 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
360 dev_priv->rps.interrupts_enabled = true;
361 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
362 dev_priv->pm_rps_events);
363 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
365 spin_unlock_irq(&dev_priv->irq_lock);
368 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
371 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
372 * if GEN6_PM_UP_EI_EXPIRED is masked.
374 * TODO: verify if this can be reproduced on VLV,CHV.
376 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
377 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
379 if (INTEL_INFO(dev_priv)->gen >= 8)
380 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
385 void gen6_disable_rps_interrupts(struct drm_device *dev)
387 struct drm_i915_private *dev_priv = dev->dev_private;
389 spin_lock_irq(&dev_priv->irq_lock);
390 dev_priv->rps.interrupts_enabled = false;
391 spin_unlock_irq(&dev_priv->irq_lock);
393 cancel_work_sync(&dev_priv->rps.work);
395 spin_lock_irq(&dev_priv->irq_lock);
397 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
399 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
400 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
401 ~dev_priv->pm_rps_events);
403 spin_unlock_irq(&dev_priv->irq_lock);
405 synchronize_irq(dev->irq);
409 * bdw_update_port_irq - update DE port interrupt
410 * @dev_priv: driver private
411 * @interrupt_mask: mask of interrupt bits to update
412 * @enabled_irq_mask: mask of interrupt bits to enable
414 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
415 uint32_t interrupt_mask,
416 uint32_t enabled_irq_mask)
421 assert_spin_locked(&dev_priv->irq_lock);
423 WARN_ON(enabled_irq_mask & ~interrupt_mask);
425 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
428 old_val = I915_READ(GEN8_DE_PORT_IMR);
431 new_val &= ~interrupt_mask;
432 new_val |= (~enabled_irq_mask & interrupt_mask);
434 if (new_val != old_val) {
435 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
436 POSTING_READ(GEN8_DE_PORT_IMR);
441 * bdw_update_pipe_irq - update DE pipe interrupt
442 * @dev_priv: driver private
443 * @pipe: pipe whose interrupt to update
444 * @interrupt_mask: mask of interrupt bits to update
445 * @enabled_irq_mask: mask of interrupt bits to enable
447 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
449 uint32_t interrupt_mask,
450 uint32_t enabled_irq_mask)
454 assert_spin_locked(&dev_priv->irq_lock);
456 WARN_ON(enabled_irq_mask & ~interrupt_mask);
458 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
461 new_val = dev_priv->de_irq_mask[pipe];
462 new_val &= ~interrupt_mask;
463 new_val |= (~enabled_irq_mask & interrupt_mask);
465 if (new_val != dev_priv->de_irq_mask[pipe]) {
466 dev_priv->de_irq_mask[pipe] = new_val;
467 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
468 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
473 * ibx_display_interrupt_update - update SDEIMR
474 * @dev_priv: driver private
475 * @interrupt_mask: mask of interrupt bits to update
476 * @enabled_irq_mask: mask of interrupt bits to enable
478 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
479 uint32_t interrupt_mask,
480 uint32_t enabled_irq_mask)
482 uint32_t sdeimr = I915_READ(SDEIMR);
483 sdeimr &= ~interrupt_mask;
484 sdeimr |= (~enabled_irq_mask & interrupt_mask);
486 WARN_ON(enabled_irq_mask & ~interrupt_mask);
488 assert_spin_locked(&dev_priv->irq_lock);
490 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
493 I915_WRITE(SDEIMR, sdeimr);
494 POSTING_READ(SDEIMR);
498 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
499 u32 enable_mask, u32 status_mask)
501 i915_reg_t reg = PIPESTAT(pipe);
502 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
504 assert_spin_locked(&dev_priv->irq_lock);
505 WARN_ON(!intel_irqs_enabled(dev_priv));
507 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
508 status_mask & ~PIPESTAT_INT_STATUS_MASK,
509 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
510 pipe_name(pipe), enable_mask, status_mask))
513 if ((pipestat & enable_mask) == enable_mask)
516 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
518 /* Enable the interrupt, clear any pending status */
519 pipestat |= enable_mask | status_mask;
520 I915_WRITE(reg, pipestat);
525 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
526 u32 enable_mask, u32 status_mask)
528 i915_reg_t reg = PIPESTAT(pipe);
529 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
531 assert_spin_locked(&dev_priv->irq_lock);
532 WARN_ON(!intel_irqs_enabled(dev_priv));
534 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
535 status_mask & ~PIPESTAT_INT_STATUS_MASK,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe), enable_mask, status_mask))
540 if ((pipestat & enable_mask) == 0)
543 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
545 pipestat &= ~enable_mask;
546 I915_WRITE(reg, pipestat);
550 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
552 u32 enable_mask = status_mask << 16;
555 * On pipe A we don't support the PSR interrupt yet,
556 * on pipe B and C the same bit MBZ.
558 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
561 * On pipe B and C we don't support the PSR interrupt yet, on pipe
562 * A the same bit is for perf counters which we don't use either.
564 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
567 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
568 SPRITE0_FLIP_DONE_INT_EN_VLV |
569 SPRITE1_FLIP_DONE_INT_EN_VLV);
570 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
571 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
572 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
573 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
579 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
584 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
585 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
588 enable_mask = status_mask << 16;
589 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
593 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
598 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
599 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
602 enable_mask = status_mask << 16;
603 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
607 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
610 static void i915_enable_asle_pipestat(struct drm_device *dev)
612 struct drm_i915_private *dev_priv = dev->dev_private;
614 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
617 spin_lock_irq(&dev_priv->irq_lock);
619 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
620 if (INTEL_INFO(dev)->gen >= 4)
621 i915_enable_pipestat(dev_priv, PIPE_A,
622 PIPE_LEGACY_BLC_EVENT_STATUS);
624 spin_unlock_irq(&dev_priv->irq_lock);
628 * This timing diagram depicts the video signal in and
629 * around the vertical blanking period.
631 * Assumptions about the fictitious mode used in this example:
633 * vsync_start = vblank_start + 1
634 * vsync_end = vblank_start + 2
635 * vtotal = vblank_start + 3
638 * latch double buffered registers
639 * increment frame counter (ctg+)
640 * generate start of vblank interrupt (gen4+)
643 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
644 * | may be shifted forward 1-3 extra lines via PIPECONF
646 * | | start of vsync:
647 * | | generate vsync interrupt
649 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
650 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
651 * ----va---> <-----------------vb--------------------> <--------va-------------
652 * | | <----vs-----> |
653 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
654 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
655 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
657 * last visible pixel first visible pixel
658 * | increment frame counter (gen3/4)
659 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
661 * x = horizontal active
662 * _ = horizontal blanking
663 * hs = horizontal sync
664 * va = vertical active
665 * vb = vertical blanking
667 * vbs = vblank_start (number)
670 * - most events happen at the start of horizontal sync
671 * - frame start happens at the start of horizontal blank, 1-4 lines
672 * (depending on PIPECONF settings) after the start of vblank
673 * - gen3/4 pixel and frame counter are synchronized with the start
674 * of horizontal active on the first line of vertical active
677 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
679 /* Gen2 doesn't have a hardware frame counter */
683 /* Called from drm generic code, passed a 'crtc', which
684 * we use as a pipe index
686 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
688 struct drm_i915_private *dev_priv = dev->dev_private;
689 i915_reg_t high_frame, low_frame;
690 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
691 struct intel_crtc *intel_crtc =
692 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
693 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
695 htotal = mode->crtc_htotal;
696 hsync_start = mode->crtc_hsync_start;
697 vbl_start = mode->crtc_vblank_start;
698 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
699 vbl_start = DIV_ROUND_UP(vbl_start, 2);
701 /* Convert to pixel count */
704 /* Start of vblank event occurs at start of hsync */
705 vbl_start -= htotal - hsync_start;
707 high_frame = PIPEFRAME(pipe);
708 low_frame = PIPEFRAMEPIXEL(pipe);
711 * High & low register fields aren't synchronized, so make sure
712 * we get a low value that's stable across two reads of the high
716 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
717 low = I915_READ(low_frame);
718 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
719 } while (high1 != high2);
721 high1 >>= PIPE_FRAME_HIGH_SHIFT;
722 pixel = low & PIPE_PIXEL_MASK;
723 low >>= PIPE_FRAME_LOW_SHIFT;
726 * The frame counter increments at beginning of active.
727 * Cook up a vblank counter by also checking the pixel
728 * counter against vblank start.
730 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
733 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
735 struct drm_i915_private *dev_priv = dev->dev_private;
737 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
740 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
741 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
743 struct drm_device *dev = crtc->base.dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 const struct drm_display_mode *mode = &crtc->base.hwmode;
746 enum pipe pipe = crtc->pipe;
747 int position, vtotal;
749 vtotal = mode->crtc_vtotal;
750 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
754 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
756 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
759 * On HSW, the DSL reg (0x70000) appears to return 0 if we
760 * read it just before the start of vblank. So try it again
761 * so we don't accidentally end up spanning a vblank frame
762 * increment, causing the pipe_update_end() code to squak at us.
764 * The nature of this problem means we can't simply check the ISR
765 * bit and return the vblank start value; nor can we use the scanline
766 * debug register in the transcoder as it appears to have the same
767 * problem. We may need to extend this to include other platforms,
768 * but so far testing only shows the problem on HSW.
770 if (HAS_DDI(dev) && !position) {
773 for (i = 0; i < 100; i++) {
775 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
777 if (temp != position) {
785 * See update_scanline_offset() for the details on the
786 * scanline_offset adjustment.
788 return (position + crtc->scanline_offset) % vtotal;
791 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
792 unsigned int flags, int *vpos, int *hpos,
793 ktime_t *stime, ktime_t *etime,
794 const struct drm_display_mode *mode)
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
800 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
803 unsigned long irqflags;
805 if (WARN_ON(!mode->crtc_clock)) {
806 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
807 "pipe %c\n", pipe_name(pipe));
811 htotal = mode->crtc_htotal;
812 hsync_start = mode->crtc_hsync_start;
813 vtotal = mode->crtc_vtotal;
814 vbl_start = mode->crtc_vblank_start;
815 vbl_end = mode->crtc_vblank_end;
817 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
818 vbl_start = DIV_ROUND_UP(vbl_start, 2);
823 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
826 * Lock uncore.lock, as we will do multiple timing critical raw
827 * register reads, potentially with preemption disabled, so the
828 * following code must not block on uncore.lock.
830 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
832 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
834 /* Get optional system timestamp before query. */
836 *stime = ktime_get();
838 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
839 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register.
842 position = __intel_get_crtc_scanline(intel_crtc);
844 /* Have access to pixelcount since start of frame.
845 * We can split this into vertical and horizontal
848 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
850 /* convert to pixel counts */
856 * In interlaced modes, the pixel counter counts all pixels,
857 * so one field will have htotal more pixels. In order to avoid
858 * the reported position from jumping backwards when the pixel
859 * counter is beyond the length of the shorter field, just
860 * clamp the position the length of the shorter field. This
861 * matches how the scanline counter based position works since
862 * the scanline counter doesn't count the two half lines.
864 if (position >= vtotal)
865 position = vtotal - 1;
868 * Start of vblank interrupt is triggered at start of hsync,
869 * just prior to the first active line of vblank. However we
870 * consider lines to start at the leading edge of horizontal
871 * active. So, should we get here before we've crossed into
872 * the horizontal active of the first line in vblank, we would
873 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
874 * always add htotal-hsync_start to the current pixel position.
876 position = (position + htotal - hsync_start) % vtotal;
879 /* Get optional system timestamp after query. */
881 *etime = ktime_get();
883 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
885 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
887 in_vbl = position >= vbl_start && position < vbl_end;
890 * While in vblank, position will be negative
891 * counting up towards 0 at vbl_end. And outside
892 * vblank, position will be positive counting
895 if (position >= vbl_start)
898 position += vtotal - vbl_end;
900 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
904 *vpos = position / htotal;
905 *hpos = position - (*vpos * htotal);
910 ret |= DRM_SCANOUTPOS_IN_VBLANK;
915 int intel_get_crtc_scanline(struct intel_crtc *crtc)
917 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
918 unsigned long irqflags;
921 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
922 position = __intel_get_crtc_scanline(crtc);
923 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
928 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
930 struct timeval *vblank_time,
933 struct drm_crtc *crtc;
935 if (pipe >= INTEL_INFO(dev)->num_pipes) {
936 DRM_ERROR("Invalid crtc %u\n", pipe);
940 /* Get drm_crtc to timestamp: */
941 crtc = intel_get_crtc_for_pipe(dev, pipe);
943 DRM_ERROR("Invalid crtc %u\n", pipe);
947 if (!crtc->hwmode.crtc_clock) {
948 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
952 /* Helper routine in DRM core does all the work: */
953 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
958 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 busy_up, busy_down, max_avg, min_avg;
964 spin_lock(&mchdev_lock);
966 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
968 new_delay = dev_priv->ips.cur_delay;
970 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
971 busy_up = I915_READ(RCPREVBSYTUPAVG);
972 busy_down = I915_READ(RCPREVBSYTDNAVG);
973 max_avg = I915_READ(RCBMAXAVG);
974 min_avg = I915_READ(RCBMINAVG);
976 /* Handle RCS change request from hw */
977 if (busy_up > max_avg) {
978 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
979 new_delay = dev_priv->ips.cur_delay - 1;
980 if (new_delay < dev_priv->ips.max_delay)
981 new_delay = dev_priv->ips.max_delay;
982 } else if (busy_down < min_avg) {
983 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
984 new_delay = dev_priv->ips.cur_delay + 1;
985 if (new_delay > dev_priv->ips.min_delay)
986 new_delay = dev_priv->ips.min_delay;
989 if (ironlake_set_drps(dev, new_delay))
990 dev_priv->ips.cur_delay = new_delay;
992 spin_unlock(&mchdev_lock);
997 static void notify_ring(struct intel_engine_cs *ring)
999 if (!intel_ring_initialized(ring))
1002 trace_i915_gem_request_notify(ring);
1004 wake_up_all(&ring->irq_queue);
1007 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1008 struct intel_rps_ei *ei)
1010 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1011 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1012 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1015 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1016 const struct intel_rps_ei *old,
1017 const struct intel_rps_ei *now,
1021 unsigned int mul = 100;
1023 if (old->cz_clock == 0)
1026 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1029 time = now->cz_clock - old->cz_clock;
1030 time *= threshold * dev_priv->czclk_freq;
1032 /* Workload can be split between render + media, e.g. SwapBuffers
1033 * being blitted in X after being rendered in mesa. To account for
1034 * this we need to combine both engines into our activity counter.
1036 c0 = now->render_c0 - old->render_c0;
1037 c0 += now->media_c0 - old->media_c0;
1038 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1043 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1045 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1046 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1049 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1051 struct intel_rps_ei now;
1054 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1057 vlv_c0_read(dev_priv, &now);
1058 if (now.cz_clock == 0)
1061 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1062 if (!vlv_c0_above(dev_priv,
1063 &dev_priv->rps.down_ei, &now,
1064 dev_priv->rps.down_threshold))
1065 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1066 dev_priv->rps.down_ei = now;
1069 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1070 if (vlv_c0_above(dev_priv,
1071 &dev_priv->rps.up_ei, &now,
1072 dev_priv->rps.up_threshold))
1073 events |= GEN6_PM_RP_UP_THRESHOLD;
1074 dev_priv->rps.up_ei = now;
1080 static bool any_waiters(struct drm_i915_private *dev_priv)
1082 struct intel_engine_cs *ring;
1085 for_each_ring(ring, dev_priv, i)
1086 if (ring->irq_refcount)
1092 static void gen6_pm_rps_work(struct work_struct *work)
1094 struct drm_i915_private *dev_priv =
1095 container_of(work, struct drm_i915_private, rps.work);
1097 int new_delay, adj, min, max;
1100 spin_lock_irq(&dev_priv->irq_lock);
1101 /* Speed up work cancelation during disabling rps interrupts. */
1102 if (!dev_priv->rps.interrupts_enabled) {
1103 spin_unlock_irq(&dev_priv->irq_lock);
1108 * The RPS work is synced during runtime suspend, we don't require a
1109 * wakeref. TODO: instead of disabling the asserts make sure that we
1110 * always hold an RPM reference while the work is running.
1112 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1114 pm_iir = dev_priv->rps.pm_iir;
1115 dev_priv->rps.pm_iir = 0;
1116 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1117 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1118 client_boost = dev_priv->rps.client_boost;
1119 dev_priv->rps.client_boost = false;
1120 spin_unlock_irq(&dev_priv->irq_lock);
1122 /* Make sure we didn't queue anything we're not going to process. */
1123 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1125 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1128 mutex_lock(&dev_priv->rps.hw_lock);
1130 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1132 adj = dev_priv->rps.last_adj;
1133 new_delay = dev_priv->rps.cur_freq;
1134 min = dev_priv->rps.min_freq_softlimit;
1135 max = dev_priv->rps.max_freq_softlimit;
1138 new_delay = dev_priv->rps.max_freq_softlimit;
1140 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1143 else /* CHV needs even encode values */
1144 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1146 * For better performance, jump directly
1147 * to RPe if we're below it.
1149 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1150 new_delay = dev_priv->rps.efficient_freq;
1153 } else if (any_waiters(dev_priv)) {
1155 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1156 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1157 new_delay = dev_priv->rps.efficient_freq;
1159 new_delay = dev_priv->rps.min_freq_softlimit;
1161 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1164 else /* CHV needs even encode values */
1165 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1166 } else { /* unknown event */
1170 dev_priv->rps.last_adj = adj;
1172 /* sysfs frequency interfaces may have snuck in while servicing the
1176 new_delay = clamp_t(int, new_delay, min, max);
1178 intel_set_rps(dev_priv->dev, new_delay);
1180 mutex_unlock(&dev_priv->rps.hw_lock);
1182 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1187 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1189 * @work: workqueue struct
1191 * Doesn't actually do anything except notify userspace. As a consequence of
1192 * this event, userspace should try to remap the bad rows since statistically
1193 * it is likely the same row is more likely to go bad again.
1195 static void ivybridge_parity_work(struct work_struct *work)
1197 struct drm_i915_private *dev_priv =
1198 container_of(work, struct drm_i915_private, l3_parity.error_work);
1199 u32 error_status, row, bank, subbank;
1200 char *parity_event[6];
1204 /* We must turn off DOP level clock gating to access the L3 registers.
1205 * In order to prevent a get/put style interface, acquire struct mutex
1206 * any time we access those registers.
1208 mutex_lock(&dev_priv->dev->struct_mutex);
1210 /* If we've screwed up tracking, just let the interrupt fire again */
1211 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1214 misccpctl = I915_READ(GEN7_MISCCPCTL);
1215 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1216 POSTING_READ(GEN7_MISCCPCTL);
1218 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1222 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1225 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1227 reg = GEN7_L3CDERRST1(slice);
1229 error_status = I915_READ(reg);
1230 row = GEN7_PARITY_ERROR_ROW(error_status);
1231 bank = GEN7_PARITY_ERROR_BANK(error_status);
1232 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1234 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1237 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1238 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1239 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1240 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1241 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1242 parity_event[5] = NULL;
1244 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1245 KOBJ_CHANGE, parity_event);
1247 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1248 slice, row, bank, subbank);
1250 kfree(parity_event[4]);
1251 kfree(parity_event[3]);
1252 kfree(parity_event[2]);
1253 kfree(parity_event[1]);
1256 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1259 WARN_ON(dev_priv->l3_parity.which_slice);
1260 spin_lock_irq(&dev_priv->irq_lock);
1261 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1262 spin_unlock_irq(&dev_priv->irq_lock);
1264 mutex_unlock(&dev_priv->dev->struct_mutex);
1267 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1271 if (!HAS_L3_DPF(dev))
1274 spin_lock(&dev_priv->irq_lock);
1275 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1276 spin_unlock(&dev_priv->irq_lock);
1278 iir &= GT_PARITY_ERROR(dev);
1279 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1280 dev_priv->l3_parity.which_slice |= 1 << 1;
1282 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1283 dev_priv->l3_parity.which_slice |= 1 << 0;
1285 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1288 static void ilk_gt_irq_handler(struct drm_device *dev,
1289 struct drm_i915_private *dev_priv,
1293 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1294 notify_ring(&dev_priv->ring[RCS]);
1295 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1296 notify_ring(&dev_priv->ring[VCS]);
1299 static void snb_gt_irq_handler(struct drm_device *dev,
1300 struct drm_i915_private *dev_priv,
1305 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1306 notify_ring(&dev_priv->ring[RCS]);
1307 if (gt_iir & GT_BSD_USER_INTERRUPT)
1308 notify_ring(&dev_priv->ring[VCS]);
1309 if (gt_iir & GT_BLT_USER_INTERRUPT)
1310 notify_ring(&dev_priv->ring[BCS]);
1312 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1313 GT_BSD_CS_ERROR_INTERRUPT |
1314 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1315 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1317 if (gt_iir & GT_PARITY_ERROR(dev))
1318 ivybridge_parity_error_irq_handler(dev, gt_iir);
1321 static __always_inline void
1322 gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
1324 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1326 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1327 intel_lrc_irq_handler(ring);
1330 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1333 irqreturn_t ret = IRQ_NONE;
1335 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1336 u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
1338 I915_WRITE_FW(GEN8_GT_IIR(0), iir);
1341 gen8_cs_irq_handler(&dev_priv->ring[RCS],
1342 iir, GEN8_RCS_IRQ_SHIFT);
1344 gen8_cs_irq_handler(&dev_priv->ring[BCS],
1345 iir, GEN8_BCS_IRQ_SHIFT);
1347 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1350 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1351 u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
1353 I915_WRITE_FW(GEN8_GT_IIR(1), iir);
1356 gen8_cs_irq_handler(&dev_priv->ring[VCS],
1357 iir, GEN8_VCS1_IRQ_SHIFT);
1359 gen8_cs_irq_handler(&dev_priv->ring[VCS2],
1360 iir, GEN8_VCS2_IRQ_SHIFT);
1362 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1365 if (master_ctl & GEN8_GT_VECS_IRQ) {
1366 u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
1368 I915_WRITE_FW(GEN8_GT_IIR(3), iir);
1371 gen8_cs_irq_handler(&dev_priv->ring[VECS],
1372 iir, GEN8_VECS_IRQ_SHIFT);
1374 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1377 if (master_ctl & GEN8_GT_PM_IRQ) {
1378 u32 iir = I915_READ_FW(GEN8_GT_IIR(2));
1379 if (iir & dev_priv->pm_rps_events) {
1380 I915_WRITE_FW(GEN8_GT_IIR(2),
1381 iir & dev_priv->pm_rps_events);
1383 gen6_rps_irq_handler(dev_priv, iir);
1385 DRM_ERROR("The master control interrupt lied (PM)!\n");
1391 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1395 return val & PORTA_HOTPLUG_LONG_DETECT;
1397 return val & PORTB_HOTPLUG_LONG_DETECT;
1399 return val & PORTC_HOTPLUG_LONG_DETECT;
1405 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1409 return val & PORTE_HOTPLUG_LONG_DETECT;
1415 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1419 return val & PORTA_HOTPLUG_LONG_DETECT;
1421 return val & PORTB_HOTPLUG_LONG_DETECT;
1423 return val & PORTC_HOTPLUG_LONG_DETECT;
1425 return val & PORTD_HOTPLUG_LONG_DETECT;
1431 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1435 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1441 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1445 return val & PORTB_HOTPLUG_LONG_DETECT;
1447 return val & PORTC_HOTPLUG_LONG_DETECT;
1449 return val & PORTD_HOTPLUG_LONG_DETECT;
1455 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1459 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1461 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1463 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1470 * Get a bit mask of pins that have triggered, and which ones may be long.
1471 * This can be called multiple times with the same masks to accumulate
1472 * hotplug detection results from several registers.
1474 * Note that the caller is expected to zero out the masks initially.
1476 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1477 u32 hotplug_trigger, u32 dig_hotplug_reg,
1478 const u32 hpd[HPD_NUM_PINS],
1479 bool long_pulse_detect(enum port port, u32 val))
1484 for_each_hpd_pin(i) {
1485 if ((hpd[i] & hotplug_trigger) == 0)
1488 *pin_mask |= BIT(i);
1490 if (!intel_hpd_pin_to_port(i, &port))
1493 if (long_pulse_detect(port, dig_hotplug_reg))
1494 *long_mask |= BIT(i);
1497 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1498 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1502 static void gmbus_irq_handler(struct drm_device *dev)
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1506 wake_up_all(&dev_priv->gmbus_wait_queue);
1509 static void dp_aux_irq_handler(struct drm_device *dev)
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1513 wake_up_all(&dev_priv->gmbus_wait_queue);
1516 #if defined(CONFIG_DEBUG_FS)
1517 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1518 uint32_t crc0, uint32_t crc1,
1519 uint32_t crc2, uint32_t crc3,
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1524 struct intel_pipe_crc_entry *entry;
1527 spin_lock(&pipe_crc->lock);
1529 if (!pipe_crc->entries) {
1530 spin_unlock(&pipe_crc->lock);
1531 DRM_DEBUG_KMS("spurious interrupt\n");
1535 head = pipe_crc->head;
1536 tail = pipe_crc->tail;
1538 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1539 spin_unlock(&pipe_crc->lock);
1540 DRM_ERROR("CRC buffer overflowing\n");
1544 entry = &pipe_crc->entries[head];
1546 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1547 entry->crc[0] = crc0;
1548 entry->crc[1] = crc1;
1549 entry->crc[2] = crc2;
1550 entry->crc[3] = crc3;
1551 entry->crc[4] = crc4;
1553 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1554 pipe_crc->head = head;
1556 spin_unlock(&pipe_crc->lock);
1558 wake_up_interruptible(&pipe_crc->wq);
1562 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1563 uint32_t crc0, uint32_t crc1,
1564 uint32_t crc2, uint32_t crc3,
1569 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1571 struct drm_i915_private *dev_priv = dev->dev_private;
1573 display_pipe_crc_irq_handler(dev, pipe,
1574 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1578 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1582 display_pipe_crc_irq_handler(dev, pipe,
1583 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1584 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1585 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1586 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1587 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1590 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 uint32_t res1, res2;
1595 if (INTEL_INFO(dev)->gen >= 3)
1596 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1600 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1601 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1605 display_pipe_crc_irq_handler(dev, pipe,
1606 I915_READ(PIPE_CRC_RES_RED(pipe)),
1607 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1608 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1612 /* The RPS events need forcewake, so we add them to a work queue and mask their
1613 * IMR bits until the work is done. Other interrupts can be processed without
1614 * the work queue. */
1615 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1617 if (pm_iir & dev_priv->pm_rps_events) {
1618 spin_lock(&dev_priv->irq_lock);
1619 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1620 if (dev_priv->rps.interrupts_enabled) {
1621 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1622 queue_work(dev_priv->wq, &dev_priv->rps.work);
1624 spin_unlock(&dev_priv->irq_lock);
1627 if (INTEL_INFO(dev_priv)->gen >= 8)
1630 if (HAS_VEBOX(dev_priv->dev)) {
1631 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1632 notify_ring(&dev_priv->ring[VECS]);
1634 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1635 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1639 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1641 if (!drm_handle_vblank(dev, pipe))
1647 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 u32 pipe_stats[I915_MAX_PIPES] = { };
1653 spin_lock(&dev_priv->irq_lock);
1654 for_each_pipe(dev_priv, pipe) {
1656 u32 mask, iir_bit = 0;
1659 * PIPESTAT bits get signalled even when the interrupt is
1660 * disabled with the mask bits, and some of the status bits do
1661 * not generate interrupts at all (like the underrun bit). Hence
1662 * we need to be careful that we only handle what we want to
1666 /* fifo underruns are filterered in the underrun handler. */
1667 mask = PIPE_FIFO_UNDERRUN_STATUS;
1671 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1674 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1677 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1681 mask |= dev_priv->pipestat_irq_mask[pipe];
1686 reg = PIPESTAT(pipe);
1687 mask |= PIPESTAT_INT_ENABLE_MASK;
1688 pipe_stats[pipe] = I915_READ(reg) & mask;
1691 * Clear the PIPE*STAT regs before the IIR
1693 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1694 PIPESTAT_INT_STATUS_MASK))
1695 I915_WRITE(reg, pipe_stats[pipe]);
1697 spin_unlock(&dev_priv->irq_lock);
1699 for_each_pipe(dev_priv, pipe) {
1700 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1701 intel_pipe_handle_vblank(dev, pipe))
1702 intel_check_page_flip(dev, pipe);
1704 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1705 intel_prepare_page_flip(dev, pipe);
1706 intel_finish_page_flip(dev, pipe);
1709 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1710 i9xx_pipe_crc_irq_handler(dev, pipe);
1712 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1713 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1716 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1717 gmbus_irq_handler(dev);
1720 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1724 u32 pin_mask = 0, long_mask = 0;
1726 if (!hotplug_status)
1729 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1731 * Make sure hotplug status is cleared before we clear IIR, or else we
1732 * may miss hotplug events.
1734 POSTING_READ(PORT_HOTPLUG_STAT);
1736 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1737 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1739 if (hotplug_trigger) {
1740 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1741 hotplug_trigger, hpd_status_g4x,
1742 i9xx_port_hotplug_long_detect);
1744 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1747 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1748 dp_aux_irq_handler(dev);
1750 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1752 if (hotplug_trigger) {
1753 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1754 hotplug_trigger, hpd_status_i915,
1755 i9xx_port_hotplug_long_detect);
1756 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1761 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1763 struct drm_device *dev = arg;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 u32 iir, gt_iir, pm_iir;
1766 irqreturn_t ret = IRQ_NONE;
1768 if (!intel_irqs_enabled(dev_priv))
1771 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1772 disable_rpm_wakeref_asserts(dev_priv);
1775 /* Find, clear, then process each source of interrupt */
1777 gt_iir = I915_READ(GTIIR);
1779 I915_WRITE(GTIIR, gt_iir);
1781 pm_iir = I915_READ(GEN6_PMIIR);
1783 I915_WRITE(GEN6_PMIIR, pm_iir);
1785 iir = I915_READ(VLV_IIR);
1787 /* Consume port before clearing IIR or we'll miss events */
1788 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1789 i9xx_hpd_irq_handler(dev);
1790 I915_WRITE(VLV_IIR, iir);
1793 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1799 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1801 gen6_rps_irq_handler(dev_priv, pm_iir);
1802 /* Call regardless, as some status bits might not be
1803 * signalled in iir */
1804 valleyview_pipestat_irq_handler(dev, iir);
1808 enable_rpm_wakeref_asserts(dev_priv);
1813 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1815 struct drm_device *dev = arg;
1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 u32 master_ctl, iir;
1818 irqreturn_t ret = IRQ_NONE;
1820 if (!intel_irqs_enabled(dev_priv))
1823 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1824 disable_rpm_wakeref_asserts(dev_priv);
1827 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1828 iir = I915_READ(VLV_IIR);
1830 if (master_ctl == 0 && iir == 0)
1835 I915_WRITE(GEN8_MASTER_IRQ, 0);
1837 /* Find, clear, then process each source of interrupt */
1840 /* Consume port before clearing IIR or we'll miss events */
1841 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1842 i9xx_hpd_irq_handler(dev);
1843 I915_WRITE(VLV_IIR, iir);
1846 gen8_gt_irq_handler(dev_priv, master_ctl);
1848 /* Call regardless, as some status bits might not be
1849 * signalled in iir */
1850 valleyview_pipestat_irq_handler(dev, iir);
1852 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1853 POSTING_READ(GEN8_MASTER_IRQ);
1856 enable_rpm_wakeref_asserts(dev_priv);
1861 static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1862 const u32 hpd[HPD_NUM_PINS])
1864 struct drm_i915_private *dev_priv = to_i915(dev);
1865 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1868 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1869 * unless we touch the hotplug register, even if hotplug_trigger is
1870 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1873 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1874 if (!hotplug_trigger) {
1875 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1876 PORTD_HOTPLUG_STATUS_MASK |
1877 PORTC_HOTPLUG_STATUS_MASK |
1878 PORTB_HOTPLUG_STATUS_MASK;
1879 dig_hotplug_reg &= ~mask;
1882 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1883 if (!hotplug_trigger)
1886 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1887 dig_hotplug_reg, hpd,
1888 pch_port_hotplug_long_detect);
1890 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1893 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1897 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1899 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1901 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1902 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1903 SDE_AUDIO_POWER_SHIFT);
1904 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1908 if (pch_iir & SDE_AUX_MASK)
1909 dp_aux_irq_handler(dev);
1911 if (pch_iir & SDE_GMBUS)
1912 gmbus_irq_handler(dev);
1914 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1915 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1917 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1918 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1920 if (pch_iir & SDE_POISON)
1921 DRM_ERROR("PCH poison interrupt\n");
1923 if (pch_iir & SDE_FDI_MASK)
1924 for_each_pipe(dev_priv, pipe)
1925 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1927 I915_READ(FDI_RX_IIR(pipe)));
1929 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1930 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1932 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1933 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1935 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1936 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1938 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1939 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1942 static void ivb_err_int_handler(struct drm_device *dev)
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 u32 err_int = I915_READ(GEN7_ERR_INT);
1948 if (err_int & ERR_INT_POISON)
1949 DRM_ERROR("Poison interrupt\n");
1951 for_each_pipe(dev_priv, pipe) {
1952 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1953 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1955 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1956 if (IS_IVYBRIDGE(dev))
1957 ivb_pipe_crc_irq_handler(dev, pipe);
1959 hsw_pipe_crc_irq_handler(dev, pipe);
1963 I915_WRITE(GEN7_ERR_INT, err_int);
1966 static void cpt_serr_int_handler(struct drm_device *dev)
1968 struct drm_i915_private *dev_priv = dev->dev_private;
1969 u32 serr_int = I915_READ(SERR_INT);
1971 if (serr_int & SERR_INT_POISON)
1972 DRM_ERROR("PCH poison interrupt\n");
1974 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1975 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1977 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1978 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1980 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1981 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1983 I915_WRITE(SERR_INT, serr_int);
1986 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1988 struct drm_i915_private *dev_priv = dev->dev_private;
1990 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1992 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1994 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1995 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1996 SDE_AUDIO_POWER_SHIFT_CPT);
1997 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2001 if (pch_iir & SDE_AUX_MASK_CPT)
2002 dp_aux_irq_handler(dev);
2004 if (pch_iir & SDE_GMBUS_CPT)
2005 gmbus_irq_handler(dev);
2007 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2008 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2010 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2011 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2013 if (pch_iir & SDE_FDI_MASK_CPT)
2014 for_each_pipe(dev_priv, pipe)
2015 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2017 I915_READ(FDI_RX_IIR(pipe)));
2019 if (pch_iir & SDE_ERROR_CPT)
2020 cpt_serr_int_handler(dev);
2023 static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2027 ~SDE_PORTE_HOTPLUG_SPT;
2028 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2029 u32 pin_mask = 0, long_mask = 0;
2031 if (hotplug_trigger) {
2032 u32 dig_hotplug_reg;
2034 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2035 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2037 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2038 dig_hotplug_reg, hpd_spt,
2039 spt_port_hotplug_long_detect);
2042 if (hotplug2_trigger) {
2043 u32 dig_hotplug_reg;
2045 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2046 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2048 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2049 dig_hotplug_reg, hpd_spt,
2050 spt_port_hotplug2_long_detect);
2054 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2056 if (pch_iir & SDE_GMBUS_CPT)
2057 gmbus_irq_handler(dev);
2060 static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2061 const u32 hpd[HPD_NUM_PINS])
2063 struct drm_i915_private *dev_priv = to_i915(dev);
2064 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2066 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2067 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2069 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2070 dig_hotplug_reg, hpd,
2071 ilk_port_hotplug_long_detect);
2073 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2076 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2080 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2082 if (hotplug_trigger)
2083 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
2085 if (de_iir & DE_AUX_CHANNEL_A)
2086 dp_aux_irq_handler(dev);
2088 if (de_iir & DE_GSE)
2089 intel_opregion_asle_intr(dev);
2091 if (de_iir & DE_POISON)
2092 DRM_ERROR("Poison interrupt\n");
2094 for_each_pipe(dev_priv, pipe) {
2095 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2096 intel_pipe_handle_vblank(dev, pipe))
2097 intel_check_page_flip(dev, pipe);
2099 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2100 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2102 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2103 i9xx_pipe_crc_irq_handler(dev, pipe);
2105 /* plane/pipes map 1:1 on ilk+ */
2106 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2107 intel_prepare_page_flip(dev, pipe);
2108 intel_finish_page_flip_plane(dev, pipe);
2112 /* check event from PCH */
2113 if (de_iir & DE_PCH_EVENT) {
2114 u32 pch_iir = I915_READ(SDEIIR);
2116 if (HAS_PCH_CPT(dev))
2117 cpt_irq_handler(dev, pch_iir);
2119 ibx_irq_handler(dev, pch_iir);
2121 /* should clear PCH hotplug event before clear CPU irq */
2122 I915_WRITE(SDEIIR, pch_iir);
2125 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2126 ironlake_rps_change_irq_handler(dev);
2129 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2133 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2135 if (hotplug_trigger)
2136 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
2138 if (de_iir & DE_ERR_INT_IVB)
2139 ivb_err_int_handler(dev);
2141 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2142 dp_aux_irq_handler(dev);
2144 if (de_iir & DE_GSE_IVB)
2145 intel_opregion_asle_intr(dev);
2147 for_each_pipe(dev_priv, pipe) {
2148 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2149 intel_pipe_handle_vblank(dev, pipe))
2150 intel_check_page_flip(dev, pipe);
2152 /* plane/pipes map 1:1 on ilk+ */
2153 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2154 intel_prepare_page_flip(dev, pipe);
2155 intel_finish_page_flip_plane(dev, pipe);
2159 /* check event from PCH */
2160 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2161 u32 pch_iir = I915_READ(SDEIIR);
2163 cpt_irq_handler(dev, pch_iir);
2165 /* clear PCH hotplug event before clear CPU irq */
2166 I915_WRITE(SDEIIR, pch_iir);
2171 * To handle irqs with the minimum potential races with fresh interrupts, we:
2172 * 1 - Disable Master Interrupt Control.
2173 * 2 - Find the source(s) of the interrupt.
2174 * 3 - Clear the Interrupt Identity bits (IIR).
2175 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2176 * 5 - Re-enable Master Interrupt Control.
2178 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2180 struct drm_device *dev = arg;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2183 irqreturn_t ret = IRQ_NONE;
2185 if (!intel_irqs_enabled(dev_priv))
2188 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2189 disable_rpm_wakeref_asserts(dev_priv);
2191 /* disable master interrupt before clearing iir */
2192 de_ier = I915_READ(DEIER);
2193 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2194 POSTING_READ(DEIER);
2196 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2197 * interrupts will will be stored on its back queue, and then we'll be
2198 * able to process them after we restore SDEIER (as soon as we restore
2199 * it, we'll get an interrupt if SDEIIR still has something to process
2200 * due to its back queue). */
2201 if (!HAS_PCH_NOP(dev)) {
2202 sde_ier = I915_READ(SDEIER);
2203 I915_WRITE(SDEIER, 0);
2204 POSTING_READ(SDEIER);
2207 /* Find, clear, then process each source of interrupt */
2209 gt_iir = I915_READ(GTIIR);
2211 I915_WRITE(GTIIR, gt_iir);
2213 if (INTEL_INFO(dev)->gen >= 6)
2214 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2216 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2219 de_iir = I915_READ(DEIIR);
2221 I915_WRITE(DEIIR, de_iir);
2223 if (INTEL_INFO(dev)->gen >= 7)
2224 ivb_display_irq_handler(dev, de_iir);
2226 ilk_display_irq_handler(dev, de_iir);
2229 if (INTEL_INFO(dev)->gen >= 6) {
2230 u32 pm_iir = I915_READ(GEN6_PMIIR);
2232 I915_WRITE(GEN6_PMIIR, pm_iir);
2234 gen6_rps_irq_handler(dev_priv, pm_iir);
2238 I915_WRITE(DEIER, de_ier);
2239 POSTING_READ(DEIER);
2240 if (!HAS_PCH_NOP(dev)) {
2241 I915_WRITE(SDEIER, sde_ier);
2242 POSTING_READ(SDEIER);
2245 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2246 enable_rpm_wakeref_asserts(dev_priv);
2251 static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2252 const u32 hpd[HPD_NUM_PINS])
2254 struct drm_i915_private *dev_priv = to_i915(dev);
2255 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2257 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2258 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2260 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2261 dig_hotplug_reg, hpd,
2262 bxt_port_hotplug_long_detect);
2264 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2267 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2269 struct drm_device *dev = arg;
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2272 irqreturn_t ret = IRQ_NONE;
2275 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2277 if (!intel_irqs_enabled(dev_priv))
2280 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2281 disable_rpm_wakeref_asserts(dev_priv);
2283 if (INTEL_INFO(dev_priv)->gen >= 9)
2284 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2287 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2288 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2292 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2294 /* Find, clear, then process each source of interrupt */
2296 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2298 if (master_ctl & GEN8_DE_MISC_IRQ) {
2299 tmp = I915_READ(GEN8_DE_MISC_IIR);
2301 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2303 if (tmp & GEN8_DE_MISC_GSE)
2304 intel_opregion_asle_intr(dev);
2306 DRM_ERROR("Unexpected DE Misc interrupt\n");
2309 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2312 if (master_ctl & GEN8_DE_PORT_IRQ) {
2313 tmp = I915_READ(GEN8_DE_PORT_IIR);
2316 u32 hotplug_trigger = 0;
2318 if (IS_BROXTON(dev_priv))
2319 hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
2320 else if (IS_BROADWELL(dev_priv))
2321 hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
2323 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2326 if (tmp & aux_mask) {
2327 dp_aux_irq_handler(dev);
2331 if (hotplug_trigger) {
2332 if (IS_BROXTON(dev))
2333 bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
2335 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
2339 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2340 gmbus_irq_handler(dev);
2345 DRM_ERROR("Unexpected DE Port interrupt\n");
2348 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2351 for_each_pipe(dev_priv, pipe) {
2352 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2354 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2357 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2360 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2362 if (pipe_iir & GEN8_PIPE_VBLANK &&
2363 intel_pipe_handle_vblank(dev, pipe))
2364 intel_check_page_flip(dev, pipe);
2366 if (INTEL_INFO(dev_priv)->gen >= 9)
2367 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2369 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2372 intel_prepare_page_flip(dev, pipe);
2373 intel_finish_page_flip_plane(dev, pipe);
2376 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2377 hsw_pipe_crc_irq_handler(dev, pipe);
2379 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2380 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2384 if (INTEL_INFO(dev_priv)->gen >= 9)
2385 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2387 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2390 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2392 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2394 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2397 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2398 master_ctl & GEN8_DE_PCH_IRQ) {
2400 * FIXME(BDW): Assume for now that the new interrupt handling
2401 * scheme also closed the SDE interrupt handling race we've seen
2402 * on older pch-split platforms. But this needs testing.
2404 u32 pch_iir = I915_READ(SDEIIR);
2406 I915_WRITE(SDEIIR, pch_iir);
2409 if (HAS_PCH_SPT(dev_priv))
2410 spt_irq_handler(dev, pch_iir);
2412 cpt_irq_handler(dev, pch_iir);
2415 * Like on previous PCH there seems to be something
2416 * fishy going on with forwarding PCH interrupts.
2418 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2422 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2423 POSTING_READ_FW(GEN8_MASTER_IRQ);
2426 enable_rpm_wakeref_asserts(dev_priv);
2431 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2432 bool reset_completed)
2434 struct intel_engine_cs *ring;
2438 * Notify all waiters for GPU completion events that reset state has
2439 * been changed, and that they need to restart their wait after
2440 * checking for potential errors (and bail out to drop locks if there is
2441 * a gpu reset pending so that i915_error_work_func can acquire them).
2444 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2445 for_each_ring(ring, dev_priv, i)
2446 wake_up_all(&ring->irq_queue);
2448 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2449 wake_up_all(&dev_priv->pending_flip_queue);
2452 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2453 * reset state is cleared.
2455 if (reset_completed)
2456 wake_up_all(&dev_priv->gpu_error.reset_queue);
2460 * i915_reset_and_wakeup - do process context error handling work
2463 * Fire an error uevent so userspace can see that a hang or error
2466 static void i915_reset_and_wakeup(struct drm_device *dev)
2468 struct drm_i915_private *dev_priv = to_i915(dev);
2469 struct i915_gpu_error *error = &dev_priv->gpu_error;
2470 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2471 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2472 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2475 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2478 * Note that there's only one work item which does gpu resets, so we
2479 * need not worry about concurrent gpu resets potentially incrementing
2480 * error->reset_counter twice. We only need to take care of another
2481 * racing irq/hangcheck declaring the gpu dead for a second time. A
2482 * quick check for that is good enough: schedule_work ensures the
2483 * correct ordering between hang detection and this work item, and since
2484 * the reset in-progress bit is only ever set by code outside of this
2485 * work we don't need to worry about any other races.
2487 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2488 DRM_DEBUG_DRIVER("resetting chip\n");
2489 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2493 * In most cases it's guaranteed that we get here with an RPM
2494 * reference held, for example because there is a pending GPU
2495 * request that won't finish until the reset is done. This
2496 * isn't the case at least when we get here by doing a
2497 * simulated reset via debugs, so get an RPM reference.
2499 intel_runtime_pm_get(dev_priv);
2501 intel_prepare_reset(dev);
2504 * All state reset _must_ be completed before we update the
2505 * reset counter, for otherwise waiters might miss the reset
2506 * pending state and not properly drop locks, resulting in
2507 * deadlocks with the reset work.
2509 ret = i915_reset(dev);
2511 intel_finish_reset(dev);
2513 intel_runtime_pm_put(dev_priv);
2517 * After all the gem state is reset, increment the reset
2518 * counter and wake up everyone waiting for the reset to
2521 * Since unlock operations are a one-sided barrier only,
2522 * we need to insert a barrier here to order any seqno
2524 * the counter increment.
2526 smp_mb__before_atomic();
2527 atomic_inc(&dev_priv->gpu_error.reset_counter);
2529 kobject_uevent_env(&dev->primary->kdev->kobj,
2530 KOBJ_CHANGE, reset_done_event);
2532 atomic_or(I915_WEDGED, &error->reset_counter);
2536 * Note: The wake_up also serves as a memory barrier so that
2537 * waiters see the update value of the reset counter atomic_t.
2539 i915_error_wake_up(dev_priv, true);
2543 static void i915_report_and_clear_eir(struct drm_device *dev)
2545 struct drm_i915_private *dev_priv = dev->dev_private;
2546 uint32_t instdone[I915_NUM_INSTDONE_REG];
2547 u32 eir = I915_READ(EIR);
2553 pr_err("render error detected, EIR: 0x%08x\n", eir);
2555 i915_get_extra_instdone(dev, instdone);
2558 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2559 u32 ipeir = I915_READ(IPEIR_I965);
2561 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2562 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2563 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2564 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2565 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2566 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2567 I915_WRITE(IPEIR_I965, ipeir);
2568 POSTING_READ(IPEIR_I965);
2570 if (eir & GM45_ERROR_PAGE_TABLE) {
2571 u32 pgtbl_err = I915_READ(PGTBL_ER);
2572 pr_err("page table error\n");
2573 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2574 I915_WRITE(PGTBL_ER, pgtbl_err);
2575 POSTING_READ(PGTBL_ER);
2579 if (!IS_GEN2(dev)) {
2580 if (eir & I915_ERROR_PAGE_TABLE) {
2581 u32 pgtbl_err = I915_READ(PGTBL_ER);
2582 pr_err("page table error\n");
2583 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2584 I915_WRITE(PGTBL_ER, pgtbl_err);
2585 POSTING_READ(PGTBL_ER);
2589 if (eir & I915_ERROR_MEMORY_REFRESH) {
2590 pr_err("memory refresh error:\n");
2591 for_each_pipe(dev_priv, pipe)
2592 pr_err("pipe %c stat: 0x%08x\n",
2593 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2594 /* pipestat has already been acked */
2596 if (eir & I915_ERROR_INSTRUCTION) {
2597 pr_err("instruction error\n");
2598 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2599 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2600 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2601 if (INTEL_INFO(dev)->gen < 4) {
2602 u32 ipeir = I915_READ(IPEIR);
2604 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2605 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2606 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2607 I915_WRITE(IPEIR, ipeir);
2608 POSTING_READ(IPEIR);
2610 u32 ipeir = I915_READ(IPEIR_I965);
2612 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2613 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2614 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2615 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2616 I915_WRITE(IPEIR_I965, ipeir);
2617 POSTING_READ(IPEIR_I965);
2621 I915_WRITE(EIR, eir);
2623 eir = I915_READ(EIR);
2626 * some errors might have become stuck,
2629 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2630 I915_WRITE(EMR, I915_READ(EMR) | eir);
2631 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2636 * i915_handle_error - handle a gpu error
2639 * Do some basic checking of register state at error time and
2640 * dump it to the syslog. Also call i915_capture_error_state() to make
2641 * sure we get a record and make it available in debugfs. Fire a uevent
2642 * so userspace knows something bad happened (should trigger collection
2643 * of a ring dump etc.).
2645 void i915_handle_error(struct drm_device *dev, bool wedged,
2646 const char *fmt, ...)
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2652 va_start(args, fmt);
2653 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2656 i915_capture_error_state(dev, wedged, error_msg);
2657 i915_report_and_clear_eir(dev);
2660 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2661 &dev_priv->gpu_error.reset_counter);
2664 * Wakeup waiting processes so that the reset function
2665 * i915_reset_and_wakeup doesn't deadlock trying to grab
2666 * various locks. By bumping the reset counter first, the woken
2667 * processes will see a reset in progress and back off,
2668 * releasing their locks and then wait for the reset completion.
2669 * We must do this for _all_ gpu waiters that might hold locks
2670 * that the reset work needs to acquire.
2672 * Note: The wake_up serves as the required memory barrier to
2673 * ensure that the waiters see the updated value of the reset
2676 i915_error_wake_up(dev_priv, false);
2679 i915_reset_and_wakeup(dev);
2682 /* Called from drm generic code, passed 'crtc' which
2683 * we use as a pipe index
2685 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2687 struct drm_i915_private *dev_priv = dev->dev_private;
2688 unsigned long irqflags;
2690 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2691 if (INTEL_INFO(dev)->gen >= 4)
2692 i915_enable_pipestat(dev_priv, pipe,
2693 PIPE_START_VBLANK_INTERRUPT_STATUS);
2695 i915_enable_pipestat(dev_priv, pipe,
2696 PIPE_VBLANK_INTERRUPT_STATUS);
2697 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2702 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 unsigned long irqflags;
2706 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2707 DE_PIPE_VBLANK(pipe);
2709 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2710 ilk_enable_display_irq(dev_priv, bit);
2711 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2716 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2718 struct drm_i915_private *dev_priv = dev->dev_private;
2719 unsigned long irqflags;
2721 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2722 i915_enable_pipestat(dev_priv, pipe,
2723 PIPE_START_VBLANK_INTERRUPT_STATUS);
2724 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2729 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 unsigned long irqflags;
2734 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2735 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2736 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2741 /* Called from drm generic code, passed 'crtc' which
2742 * we use as a pipe index
2744 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 unsigned long irqflags;
2749 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2750 i915_disable_pipestat(dev_priv, pipe,
2751 PIPE_VBLANK_INTERRUPT_STATUS |
2752 PIPE_START_VBLANK_INTERRUPT_STATUS);
2753 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2756 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 unsigned long irqflags;
2760 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2761 DE_PIPE_VBLANK(pipe);
2763 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2764 ilk_disable_display_irq(dev_priv, bit);
2765 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2768 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 unsigned long irqflags;
2773 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2774 i915_disable_pipestat(dev_priv, pipe,
2775 PIPE_START_VBLANK_INTERRUPT_STATUS);
2776 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2779 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 unsigned long irqflags;
2784 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2785 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2786 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2790 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2792 return (list_empty(&ring->request_list) ||
2793 i915_seqno_passed(seqno, ring->last_submitted_seqno));
2797 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2799 if (INTEL_INFO(dev)->gen >= 8) {
2800 return (ipehr >> 23) == 0x1c;
2802 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2803 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2804 MI_SEMAPHORE_REGISTER);
2808 static struct intel_engine_cs *
2809 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2811 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2812 struct intel_engine_cs *signaller;
2815 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2816 for_each_ring(signaller, dev_priv, i) {
2817 if (ring == signaller)
2820 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2824 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2826 for_each_ring(signaller, dev_priv, i) {
2827 if(ring == signaller)
2830 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2835 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2836 ring->id, ipehr, offset);
2841 static struct intel_engine_cs *
2842 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2844 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2845 u32 cmd, ipehr, head;
2850 * This function does not support execlist mode - any attempt to
2851 * proceed further into this function will result in a kernel panic
2852 * when dereferencing ring->buffer, which is not set up in execlist
2855 * The correct way of doing it would be to derive the currently
2856 * executing ring buffer from the current context, which is derived
2857 * from the currently running request. Unfortunately, to get the
2858 * current request we would have to grab the struct_mutex before doing
2859 * anything else, which would be ill-advised since some other thread
2860 * might have grabbed it already and managed to hang itself, causing
2861 * the hang checker to deadlock.
2863 * Therefore, this function does not support execlist mode in its
2864 * current form. Just return NULL and move on.
2866 if (ring->buffer == NULL)
2869 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2870 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2874 * HEAD is likely pointing to the dword after the actual command,
2875 * so scan backwards until we find the MBOX. But limit it to just 3
2876 * or 4 dwords depending on the semaphore wait command size.
2877 * Note that we don't care about ACTHD here since that might
2878 * point at at batch, and semaphores are always emitted into the
2879 * ringbuffer itself.
2881 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2882 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2884 for (i = backwards; i; --i) {
2886 * Be paranoid and presume the hw has gone off into the wild -
2887 * our ring is smaller than what the hardware (and hence
2888 * HEAD_ADDR) allows. Also handles wrap-around.
2890 head &= ring->buffer->size - 1;
2892 /* This here seems to blow up */
2893 cmd = ioread32(ring->buffer->virtual_start + head);
2903 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2904 if (INTEL_INFO(ring->dev)->gen >= 8) {
2905 offset = ioread32(ring->buffer->virtual_start + head + 12);
2907 offset = ioread32(ring->buffer->virtual_start + head + 8);
2909 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2912 static int semaphore_passed(struct intel_engine_cs *ring)
2914 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2915 struct intel_engine_cs *signaller;
2918 ring->hangcheck.deadlock++;
2920 signaller = semaphore_waits_for(ring, &seqno);
2921 if (signaller == NULL)
2924 /* Prevent pathological recursion due to driver bugs */
2925 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2928 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2931 /* cursory check for an unkickable deadlock */
2932 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2933 semaphore_passed(signaller) < 0)
2939 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2941 struct intel_engine_cs *ring;
2944 for_each_ring(ring, dev_priv, i)
2945 ring->hangcheck.deadlock = 0;
2948 static bool subunits_stuck(struct intel_engine_cs *ring)
2950 u32 instdone[I915_NUM_INSTDONE_REG];
2954 if (ring->id != RCS)
2957 i915_get_extra_instdone(ring->dev, instdone);
2959 /* There might be unstable subunit states even when
2960 * actual head is not moving. Filter out the unstable ones by
2961 * accumulating the undone -> done transitions and only
2962 * consider those as progress.
2965 for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2966 const u32 tmp = instdone[i] | ring->hangcheck.instdone[i];
2968 if (tmp != ring->hangcheck.instdone[i])
2971 ring->hangcheck.instdone[i] |= tmp;
2977 static enum intel_ring_hangcheck_action
2978 head_stuck(struct intel_engine_cs *ring, u64 acthd)
2980 if (acthd != ring->hangcheck.acthd) {
2982 /* Clear subunit states on head movement */
2983 memset(ring->hangcheck.instdone, 0,
2984 sizeof(ring->hangcheck.instdone));
2986 if (acthd > ring->hangcheck.max_acthd) {
2987 ring->hangcheck.max_acthd = acthd;
2988 return HANGCHECK_ACTIVE;
2991 return HANGCHECK_ACTIVE_LOOP;
2994 if (!subunits_stuck(ring))
2995 return HANGCHECK_ACTIVE;
2997 return HANGCHECK_HUNG;
3000 static enum intel_ring_hangcheck_action
3001 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
3003 struct drm_device *dev = ring->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 enum intel_ring_hangcheck_action ha;
3008 ha = head_stuck(ring, acthd);
3009 if (ha != HANGCHECK_HUNG)
3013 return HANGCHECK_HUNG;
3015 /* Is the chip hanging on a WAIT_FOR_EVENT?
3016 * If so we can simply poke the RB_WAIT bit
3017 * and break the hang. This should work on
3018 * all but the second generation chipsets.
3020 tmp = I915_READ_CTL(ring);
3021 if (tmp & RING_WAIT) {
3022 i915_handle_error(dev, false,
3023 "Kicking stuck wait on %s",
3025 I915_WRITE_CTL(ring, tmp);
3026 return HANGCHECK_KICK;
3029 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3030 switch (semaphore_passed(ring)) {
3032 return HANGCHECK_HUNG;
3034 i915_handle_error(dev, false,
3035 "Kicking stuck semaphore on %s",
3037 I915_WRITE_CTL(ring, tmp);
3038 return HANGCHECK_KICK;
3040 return HANGCHECK_WAIT;
3044 return HANGCHECK_HUNG;
3048 * This is called when the chip hasn't reported back with completed
3049 * batchbuffers in a long time. We keep track per ring seqno progress and
3050 * if there are no progress, hangcheck score for that ring is increased.
3051 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3052 * we kick the ring. If we see no progress on three subsequent calls
3053 * we assume chip is wedged and try to fix it by resetting the chip.
3055 static void i915_hangcheck_elapsed(struct work_struct *work)
3057 struct drm_i915_private *dev_priv =
3058 container_of(work, typeof(*dev_priv),
3059 gpu_error.hangcheck_work.work);
3060 struct drm_device *dev = dev_priv->dev;
3061 struct intel_engine_cs *ring;
3063 int busy_count = 0, rings_hung = 0;
3064 bool stuck[I915_NUM_RINGS] = { 0 };
3069 if (!i915.enable_hangcheck)
3073 * The hangcheck work is synced during runtime suspend, we don't
3074 * require a wakeref. TODO: instead of disabling the asserts make
3075 * sure that we hold a reference when this work is running.
3077 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3079 /* As enabling the GPU requires fairly extensive mmio access,
3080 * periodically arm the mmio checker to see if we are triggering
3081 * any invalid access.
3083 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3085 for_each_ring(ring, dev_priv, i) {
3090 semaphore_clear_deadlocks(dev_priv);
3092 seqno = ring->get_seqno(ring, false);
3093 acthd = intel_ring_get_active_head(ring);
3095 if (ring->hangcheck.seqno == seqno) {
3096 if (ring_idle(ring, seqno)) {
3097 ring->hangcheck.action = HANGCHECK_IDLE;
3099 if (waitqueue_active(&ring->irq_queue)) {
3100 /* Issue a wake-up to catch stuck h/w. */
3101 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
3102 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3103 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3106 DRM_INFO("Fake missed irq on %s\n",
3108 wake_up_all(&ring->irq_queue);
3110 /* Safeguard against driver failure */
3111 ring->hangcheck.score += BUSY;
3115 /* We always increment the hangcheck score
3116 * if the ring is busy and still processing
3117 * the same request, so that no single request
3118 * can run indefinitely (such as a chain of
3119 * batches). The only time we do not increment
3120 * the hangcheck score on this ring, if this
3121 * ring is in a legitimate wait for another
3122 * ring. In that case the waiting ring is a
3123 * victim and we want to be sure we catch the
3124 * right culprit. Then every time we do kick
3125 * the ring, add a small increment to the
3126 * score so that we can catch a batch that is
3127 * being repeatedly kicked and so responsible
3128 * for stalling the machine.
3130 ring->hangcheck.action = ring_stuck(ring,
3133 switch (ring->hangcheck.action) {
3134 case HANGCHECK_IDLE:
3135 case HANGCHECK_WAIT:
3136 case HANGCHECK_ACTIVE:
3138 case HANGCHECK_ACTIVE_LOOP:
3139 ring->hangcheck.score += BUSY;
3141 case HANGCHECK_KICK:
3142 ring->hangcheck.score += KICK;
3144 case HANGCHECK_HUNG:
3145 ring->hangcheck.score += HUNG;
3151 ring->hangcheck.action = HANGCHECK_ACTIVE;
3153 /* Gradually reduce the count so that we catch DoS
3154 * attempts across multiple batches.
3156 if (ring->hangcheck.score > 0)
3157 ring->hangcheck.score--;
3159 /* Clear head and subunit states on seqno movement */
3160 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3162 memset(ring->hangcheck.instdone, 0,
3163 sizeof(ring->hangcheck.instdone));
3166 ring->hangcheck.seqno = seqno;
3167 ring->hangcheck.acthd = acthd;
3171 for_each_ring(ring, dev_priv, i) {
3172 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3173 DRM_INFO("%s on %s\n",
3174 stuck[i] ? "stuck" : "no progress",
3181 i915_handle_error(dev, true, "Ring hung");
3186 /* Reset timer case chip hangs without another request
3188 i915_queue_hangcheck(dev);
3191 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3194 void i915_queue_hangcheck(struct drm_device *dev)
3196 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3198 if (!i915.enable_hangcheck)
3201 /* Don't continually defer the hangcheck so that it is always run at
3202 * least once after work has been scheduled on any ring. Otherwise,
3203 * we will ignore a hung ring if a second ring is kept busy.
3206 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3207 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3210 static void ibx_irq_reset(struct drm_device *dev)
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3214 if (HAS_PCH_NOP(dev))
3217 GEN5_IRQ_RESET(SDE);
3219 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3220 I915_WRITE(SERR_INT, 0xffffffff);
3224 * SDEIER is also touched by the interrupt handler to work around missed PCH
3225 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3226 * instead we unconditionally enable all PCH interrupt sources here, but then
3227 * only unmask them as needed with SDEIMR.
3229 * This function needs to be called before interrupts are enabled.
3231 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3233 struct drm_i915_private *dev_priv = dev->dev_private;
3235 if (HAS_PCH_NOP(dev))
3238 WARN_ON(I915_READ(SDEIER) != 0);
3239 I915_WRITE(SDEIER, 0xffffffff);
3240 POSTING_READ(SDEIER);
3243 static void gen5_gt_irq_reset(struct drm_device *dev)
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3248 if (INTEL_INFO(dev)->gen >= 6)
3249 GEN5_IRQ_RESET(GEN6_PM);
3254 static void ironlake_irq_reset(struct drm_device *dev)
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3258 I915_WRITE(HWSTAM, 0xffffffff);
3262 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3264 gen5_gt_irq_reset(dev);
3269 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3273 i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
3274 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3276 for_each_pipe(dev_priv, pipe)
3277 I915_WRITE(PIPESTAT(pipe), 0xffff);
3279 GEN5_IRQ_RESET(VLV_);
3282 static void valleyview_irq_preinstall(struct drm_device *dev)
3284 struct drm_i915_private *dev_priv = dev->dev_private;
3287 I915_WRITE(VLV_IMR, 0);
3288 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3289 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3290 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3292 gen5_gt_irq_reset(dev);
3294 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3296 vlv_display_irq_reset(dev_priv);
3299 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3301 GEN8_IRQ_RESET_NDX(GT, 0);
3302 GEN8_IRQ_RESET_NDX(GT, 1);
3303 GEN8_IRQ_RESET_NDX(GT, 2);
3304 GEN8_IRQ_RESET_NDX(GT, 3);
3307 static void gen8_irq_reset(struct drm_device *dev)
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3312 I915_WRITE(GEN8_MASTER_IRQ, 0);
3313 POSTING_READ(GEN8_MASTER_IRQ);
3315 gen8_gt_irq_reset(dev_priv);
3317 for_each_pipe(dev_priv, pipe)
3318 if (intel_display_power_is_enabled(dev_priv,
3319 POWER_DOMAIN_PIPE(pipe)))
3320 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3322 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3323 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3324 GEN5_IRQ_RESET(GEN8_PCU_);
3326 if (HAS_PCH_SPLIT(dev))
3330 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3331 unsigned int pipe_mask)
3333 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3335 spin_lock_irq(&dev_priv->irq_lock);
3336 if (pipe_mask & 1 << PIPE_A)
3337 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3338 dev_priv->de_irq_mask[PIPE_A],
3339 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3340 if (pipe_mask & 1 << PIPE_B)
3341 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3342 dev_priv->de_irq_mask[PIPE_B],
3343 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3344 if (pipe_mask & 1 << PIPE_C)
3345 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3346 dev_priv->de_irq_mask[PIPE_C],
3347 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3348 spin_unlock_irq(&dev_priv->irq_lock);
3351 static void cherryview_irq_preinstall(struct drm_device *dev)
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3355 I915_WRITE(GEN8_MASTER_IRQ, 0);
3356 POSTING_READ(GEN8_MASTER_IRQ);
3358 gen8_gt_irq_reset(dev_priv);
3360 GEN5_IRQ_RESET(GEN8_PCU_);
3362 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3364 vlv_display_irq_reset(dev_priv);
3367 static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
3368 const u32 hpd[HPD_NUM_PINS])
3370 struct drm_i915_private *dev_priv = to_i915(dev);
3371 struct intel_encoder *encoder;
3372 u32 enabled_irqs = 0;
3374 for_each_intel_encoder(dev, encoder)
3375 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3376 enabled_irqs |= hpd[encoder->hpd_pin];
3378 return enabled_irqs;
3381 static void ibx_hpd_irq_setup(struct drm_device *dev)
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 u32 hotplug_irqs, hotplug, enabled_irqs;
3386 if (HAS_PCH_IBX(dev)) {
3387 hotplug_irqs = SDE_HOTPLUG_MASK;
3388 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
3390 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3391 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
3394 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3397 * Enable digital hotplug on the PCH, and configure the DP short pulse
3398 * duration to 2ms (which is the minimum in the Display Port spec).
3399 * The pulse duration bits are reserved on LPT+.
3401 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3402 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3403 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3404 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3405 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3407 * When CPU and PCH are on the same package, port A
3408 * HPD must be enabled in both north and south.
3410 if (HAS_PCH_LPT_LP(dev))
3411 hotplug |= PORTA_HOTPLUG_ENABLE;
3412 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3415 static void spt_hpd_irq_setup(struct drm_device *dev)
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 u32 hotplug_irqs, hotplug, enabled_irqs;
3420 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3421 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
3423 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3425 /* Enable digital hotplug on the PCH */
3426 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3427 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3428 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3429 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3431 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3432 hotplug |= PORTE_HOTPLUG_ENABLE;
3433 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3436 static void ilk_hpd_irq_setup(struct drm_device *dev)
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 u32 hotplug_irqs, hotplug, enabled_irqs;
3441 if (INTEL_INFO(dev)->gen >= 8) {
3442 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3443 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
3445 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3446 } else if (INTEL_INFO(dev)->gen >= 7) {
3447 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3448 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
3450 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3452 hotplug_irqs = DE_DP_A_HOTPLUG;
3453 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
3455 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3459 * Enable digital hotplug on the CPU, and configure the DP short pulse
3460 * duration to 2ms (which is the minimum in the Display Port spec)
3461 * The pulse duration bits are reserved on HSW+.
3463 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3464 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3465 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3466 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3468 ibx_hpd_irq_setup(dev);
3471 static void bxt_hpd_irq_setup(struct drm_device *dev)
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474 u32 hotplug_irqs, hotplug, enabled_irqs;
3476 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
3477 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3479 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3481 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3482 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3483 PORTA_HOTPLUG_ENABLE;
3484 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3487 static void ibx_irq_postinstall(struct drm_device *dev)
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3492 if (HAS_PCH_NOP(dev))
3495 if (HAS_PCH_IBX(dev))
3496 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3498 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3500 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3501 I915_WRITE(SDEIMR, ~mask);
3504 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 u32 pm_irqs, gt_irqs;
3509 pm_irqs = gt_irqs = 0;
3511 dev_priv->gt_irq_mask = ~0;
3512 if (HAS_L3_DPF(dev)) {
3513 /* L3 parity interrupt is always unmasked. */
3514 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3515 gt_irqs |= GT_PARITY_ERROR(dev);
3518 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3520 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3521 ILK_BSD_USER_INTERRUPT;
3523 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3526 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3528 if (INTEL_INFO(dev)->gen >= 6) {
3530 * RPS interrupts will get enabled/disabled on demand when RPS
3531 * itself is enabled/disabled.
3534 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3536 dev_priv->pm_irq_mask = 0xffffffff;
3537 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3541 static int ironlake_irq_postinstall(struct drm_device *dev)
3543 struct drm_i915_private *dev_priv = dev->dev_private;
3544 u32 display_mask, extra_mask;
3546 if (INTEL_INFO(dev)->gen >= 7) {
3547 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3548 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3549 DE_PLANEB_FLIP_DONE_IVB |
3550 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3551 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3552 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3553 DE_DP_A_HOTPLUG_IVB);
3555 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3556 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3558 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3560 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3561 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3565 dev_priv->irq_mask = ~display_mask;
3567 I915_WRITE(HWSTAM, 0xeffe);
3569 ibx_irq_pre_postinstall(dev);
3571 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3573 gen5_gt_irq_postinstall(dev);
3575 ibx_irq_postinstall(dev);
3577 if (IS_IRONLAKE_M(dev)) {
3578 /* Enable PCU event interrupts
3580 * spinlocking not required here for correctness since interrupt
3581 * setup is guaranteed to run in single-threaded context. But we
3582 * need it to make the assert_spin_locked happy. */
3583 spin_lock_irq(&dev_priv->irq_lock);
3584 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3585 spin_unlock_irq(&dev_priv->irq_lock);
3591 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3597 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3598 PIPE_FIFO_UNDERRUN_STATUS;
3600 for_each_pipe(dev_priv, pipe)
3601 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3602 POSTING_READ(PIPESTAT(PIPE_A));
3604 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3605 PIPE_CRC_DONE_INTERRUPT_STATUS;
3607 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3608 for_each_pipe(dev_priv, pipe)
3609 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3611 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3612 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3613 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3614 if (IS_CHERRYVIEW(dev_priv))
3615 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3616 dev_priv->irq_mask &= ~iir_mask;
3618 I915_WRITE(VLV_IIR, iir_mask);
3619 I915_WRITE(VLV_IIR, iir_mask);
3620 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3621 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3622 POSTING_READ(VLV_IMR);
3625 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3631 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3632 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3633 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3634 if (IS_CHERRYVIEW(dev_priv))
3635 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3637 dev_priv->irq_mask |= iir_mask;
3638 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3639 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3640 I915_WRITE(VLV_IIR, iir_mask);
3641 I915_WRITE(VLV_IIR, iir_mask);
3642 POSTING_READ(VLV_IIR);
3644 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3645 PIPE_CRC_DONE_INTERRUPT_STATUS;
3647 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3648 for_each_pipe(dev_priv, pipe)
3649 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3651 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3652 PIPE_FIFO_UNDERRUN_STATUS;
3654 for_each_pipe(dev_priv, pipe)
3655 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3656 POSTING_READ(PIPESTAT(PIPE_A));
3659 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3661 assert_spin_locked(&dev_priv->irq_lock);
3663 if (dev_priv->display_irqs_enabled)
3666 dev_priv->display_irqs_enabled = true;
3668 if (intel_irqs_enabled(dev_priv))
3669 valleyview_display_irqs_install(dev_priv);
3672 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3674 assert_spin_locked(&dev_priv->irq_lock);
3676 if (!dev_priv->display_irqs_enabled)
3679 dev_priv->display_irqs_enabled = false;
3681 if (intel_irqs_enabled(dev_priv))
3682 valleyview_display_irqs_uninstall(dev_priv);
3685 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3687 dev_priv->irq_mask = ~0;
3689 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3690 POSTING_READ(PORT_HOTPLUG_EN);
3692 I915_WRITE(VLV_IIR, 0xffffffff);
3693 I915_WRITE(VLV_IIR, 0xffffffff);
3694 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3695 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3696 POSTING_READ(VLV_IMR);
3698 /* Interrupt setup is already guaranteed to be single-threaded, this is
3699 * just to make the assert_spin_locked check happy. */
3700 spin_lock_irq(&dev_priv->irq_lock);
3701 if (dev_priv->display_irqs_enabled)
3702 valleyview_display_irqs_install(dev_priv);
3703 spin_unlock_irq(&dev_priv->irq_lock);
3706 static int valleyview_irq_postinstall(struct drm_device *dev)
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3710 vlv_display_irq_postinstall(dev_priv);
3712 gen5_gt_irq_postinstall(dev);
3714 /* ack & enable invalid PTE error interrupts */
3715 #if 0 /* FIXME: add support to irq handler for checking these bits */
3716 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3717 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3720 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3725 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3727 /* These are interrupts we'll toggle with the ring mask register */
3728 uint32_t gt_interrupts[] = {
3729 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3730 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3731 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3732 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3733 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3734 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3735 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3736 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3737 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3739 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3740 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3743 dev_priv->pm_irq_mask = 0xffffffff;
3744 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3745 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3747 * RPS interrupts will get enabled/disabled on demand when RPS itself
3748 * is enabled/disabled.
3750 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3751 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3754 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3756 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3757 uint32_t de_pipe_enables;
3758 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3759 u32 de_port_enables;
3762 if (INTEL_INFO(dev_priv)->gen >= 9) {
3763 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3764 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3765 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3767 if (IS_BROXTON(dev_priv))
3768 de_port_masked |= BXT_DE_PORT_GMBUS;
3770 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3771 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3774 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3775 GEN8_PIPE_FIFO_UNDERRUN;
3777 de_port_enables = de_port_masked;
3778 if (IS_BROXTON(dev_priv))
3779 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3780 else if (IS_BROADWELL(dev_priv))
3781 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3783 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3784 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3785 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3787 for_each_pipe(dev_priv, pipe)
3788 if (intel_display_power_is_enabled(dev_priv,
3789 POWER_DOMAIN_PIPE(pipe)))
3790 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3791 dev_priv->de_irq_mask[pipe],
3794 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3797 static int gen8_irq_postinstall(struct drm_device *dev)
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3801 if (HAS_PCH_SPLIT(dev))
3802 ibx_irq_pre_postinstall(dev);
3804 gen8_gt_irq_postinstall(dev_priv);
3805 gen8_de_irq_postinstall(dev_priv);
3807 if (HAS_PCH_SPLIT(dev))
3808 ibx_irq_postinstall(dev);
3810 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3811 POSTING_READ(GEN8_MASTER_IRQ);
3816 static int cherryview_irq_postinstall(struct drm_device *dev)
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3820 vlv_display_irq_postinstall(dev_priv);
3822 gen8_gt_irq_postinstall(dev_priv);
3824 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3825 POSTING_READ(GEN8_MASTER_IRQ);
3830 static void gen8_irq_uninstall(struct drm_device *dev)
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3837 gen8_irq_reset(dev);
3840 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3842 /* Interrupt setup is already guaranteed to be single-threaded, this is
3843 * just to make the assert_spin_locked check happy. */
3844 spin_lock_irq(&dev_priv->irq_lock);
3845 if (dev_priv->display_irqs_enabled)
3846 valleyview_display_irqs_uninstall(dev_priv);
3847 spin_unlock_irq(&dev_priv->irq_lock);
3849 vlv_display_irq_reset(dev_priv);
3851 dev_priv->irq_mask = ~0;
3854 static void valleyview_irq_uninstall(struct drm_device *dev)
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3861 I915_WRITE(VLV_MASTER_IER, 0);
3863 gen5_gt_irq_reset(dev);
3865 I915_WRITE(HWSTAM, 0xffffffff);
3867 vlv_display_irq_uninstall(dev_priv);
3870 static void cherryview_irq_uninstall(struct drm_device *dev)
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3877 I915_WRITE(GEN8_MASTER_IRQ, 0);
3878 POSTING_READ(GEN8_MASTER_IRQ);
3880 gen8_gt_irq_reset(dev_priv);
3882 GEN5_IRQ_RESET(GEN8_PCU_);
3884 vlv_display_irq_uninstall(dev_priv);
3887 static void ironlake_irq_uninstall(struct drm_device *dev)
3889 struct drm_i915_private *dev_priv = dev->dev_private;
3894 ironlake_irq_reset(dev);
3897 static void i8xx_irq_preinstall(struct drm_device * dev)
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3902 for_each_pipe(dev_priv, pipe)
3903 I915_WRITE(PIPESTAT(pipe), 0);
3904 I915_WRITE16(IMR, 0xffff);
3905 I915_WRITE16(IER, 0x0);
3906 POSTING_READ16(IER);
3909 static int i8xx_irq_postinstall(struct drm_device *dev)
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3914 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3916 /* Unmask the interrupts that we always want on. */
3917 dev_priv->irq_mask =
3918 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3919 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3920 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3921 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3922 I915_WRITE16(IMR, dev_priv->irq_mask);
3925 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3926 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3927 I915_USER_INTERRUPT);
3928 POSTING_READ16(IER);
3930 /* Interrupt setup is already guaranteed to be single-threaded, this is
3931 * just to make the assert_spin_locked check happy. */
3932 spin_lock_irq(&dev_priv->irq_lock);
3933 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3934 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3935 spin_unlock_irq(&dev_priv->irq_lock);
3941 * Returns true when a page flip has completed.
3943 static bool i8xx_handle_vblank(struct drm_device *dev,
3944 int plane, int pipe, u32 iir)
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3949 if (!intel_pipe_handle_vblank(dev, pipe))
3952 if ((iir & flip_pending) == 0)
3953 goto check_page_flip;
3955 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3956 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3957 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3958 * the flip is completed (no longer pending). Since this doesn't raise
3959 * an interrupt per se, we watch for the change at vblank.
3961 if (I915_READ16(ISR) & flip_pending)
3962 goto check_page_flip;
3964 intel_prepare_page_flip(dev, plane);
3965 intel_finish_page_flip(dev, pipe);
3969 intel_check_page_flip(dev, pipe);
3973 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3975 struct drm_device *dev = arg;
3976 struct drm_i915_private *dev_priv = dev->dev_private;
3981 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3982 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3985 if (!intel_irqs_enabled(dev_priv))
3988 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3989 disable_rpm_wakeref_asserts(dev_priv);
3992 iir = I915_READ16(IIR);
3996 while (iir & ~flip_mask) {
3997 /* Can't rely on pipestat interrupt bit in iir as it might
3998 * have been cleared after the pipestat interrupt was received.
3999 * It doesn't set the bit in iir again, but it still produces
4000 * interrupts (for non-MSI).
4002 spin_lock(&dev_priv->irq_lock);
4003 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4004 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4006 for_each_pipe(dev_priv, pipe) {
4007 i915_reg_t reg = PIPESTAT(pipe);
4008 pipe_stats[pipe] = I915_READ(reg);
4011 * Clear the PIPE*STAT regs before the IIR
4013 if (pipe_stats[pipe] & 0x8000ffff)
4014 I915_WRITE(reg, pipe_stats[pipe]);
4016 spin_unlock(&dev_priv->irq_lock);
4018 I915_WRITE16(IIR, iir & ~flip_mask);
4019 new_iir = I915_READ16(IIR); /* Flush posted writes */
4021 if (iir & I915_USER_INTERRUPT)
4022 notify_ring(&dev_priv->ring[RCS]);
4024 for_each_pipe(dev_priv, pipe) {
4029 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4030 i8xx_handle_vblank(dev, plane, pipe, iir))
4031 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4033 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4034 i9xx_pipe_crc_irq_handler(dev, pipe);
4036 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4037 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4046 enable_rpm_wakeref_asserts(dev_priv);
4051 static void i8xx_irq_uninstall(struct drm_device * dev)
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4056 for_each_pipe(dev_priv, pipe) {
4057 /* Clear enable bits; then clear status bits */
4058 I915_WRITE(PIPESTAT(pipe), 0);
4059 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4061 I915_WRITE16(IMR, 0xffff);
4062 I915_WRITE16(IER, 0x0);
4063 I915_WRITE16(IIR, I915_READ16(IIR));
4066 static void i915_irq_preinstall(struct drm_device * dev)
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4071 if (I915_HAS_HOTPLUG(dev)) {
4072 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4073 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4076 I915_WRITE16(HWSTAM, 0xeffe);
4077 for_each_pipe(dev_priv, pipe)
4078 I915_WRITE(PIPESTAT(pipe), 0);
4079 I915_WRITE(IMR, 0xffffffff);
4080 I915_WRITE(IER, 0x0);
4084 static int i915_irq_postinstall(struct drm_device *dev)
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4089 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4091 /* Unmask the interrupts that we always want on. */
4092 dev_priv->irq_mask =
4093 ~(I915_ASLE_INTERRUPT |
4094 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4095 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4096 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4097 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4100 I915_ASLE_INTERRUPT |
4101 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4102 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4103 I915_USER_INTERRUPT;
4105 if (I915_HAS_HOTPLUG(dev)) {
4106 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4107 POSTING_READ(PORT_HOTPLUG_EN);
4109 /* Enable in IER... */
4110 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4111 /* and unmask in IMR */
4112 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4115 I915_WRITE(IMR, dev_priv->irq_mask);
4116 I915_WRITE(IER, enable_mask);
4119 i915_enable_asle_pipestat(dev);
4121 /* Interrupt setup is already guaranteed to be single-threaded, this is
4122 * just to make the assert_spin_locked check happy. */
4123 spin_lock_irq(&dev_priv->irq_lock);
4124 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4125 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4126 spin_unlock_irq(&dev_priv->irq_lock);
4132 * Returns true when a page flip has completed.
4134 static bool i915_handle_vblank(struct drm_device *dev,
4135 int plane, int pipe, u32 iir)
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4140 if (!intel_pipe_handle_vblank(dev, pipe))
4143 if ((iir & flip_pending) == 0)
4144 goto check_page_flip;
4146 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4147 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4148 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4149 * the flip is completed (no longer pending). Since this doesn't raise
4150 * an interrupt per se, we watch for the change at vblank.
4152 if (I915_READ(ISR) & flip_pending)
4153 goto check_page_flip;
4155 intel_prepare_page_flip(dev, plane);
4156 intel_finish_page_flip(dev, pipe);
4160 intel_check_page_flip(dev, pipe);
4164 static irqreturn_t i915_irq_handler(int irq, void *arg)
4166 struct drm_device *dev = arg;
4167 struct drm_i915_private *dev_priv = dev->dev_private;
4168 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4170 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4171 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4172 int pipe, ret = IRQ_NONE;
4174 if (!intel_irqs_enabled(dev_priv))
4177 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4178 disable_rpm_wakeref_asserts(dev_priv);
4180 iir = I915_READ(IIR);
4182 bool irq_received = (iir & ~flip_mask) != 0;
4183 bool blc_event = false;
4185 /* Can't rely on pipestat interrupt bit in iir as it might
4186 * have been cleared after the pipestat interrupt was received.
4187 * It doesn't set the bit in iir again, but it still produces
4188 * interrupts (for non-MSI).
4190 spin_lock(&dev_priv->irq_lock);
4191 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4192 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4194 for_each_pipe(dev_priv, pipe) {
4195 i915_reg_t reg = PIPESTAT(pipe);
4196 pipe_stats[pipe] = I915_READ(reg);
4198 /* Clear the PIPE*STAT regs before the IIR */
4199 if (pipe_stats[pipe] & 0x8000ffff) {
4200 I915_WRITE(reg, pipe_stats[pipe]);
4201 irq_received = true;
4204 spin_unlock(&dev_priv->irq_lock);
4209 /* Consume port. Then clear IIR or we'll miss events */
4210 if (I915_HAS_HOTPLUG(dev) &&
4211 iir & I915_DISPLAY_PORT_INTERRUPT)
4212 i9xx_hpd_irq_handler(dev);
4214 I915_WRITE(IIR, iir & ~flip_mask);
4215 new_iir = I915_READ(IIR); /* Flush posted writes */
4217 if (iir & I915_USER_INTERRUPT)
4218 notify_ring(&dev_priv->ring[RCS]);
4220 for_each_pipe(dev_priv, pipe) {
4225 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4226 i915_handle_vblank(dev, plane, pipe, iir))
4227 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4229 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4232 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4233 i9xx_pipe_crc_irq_handler(dev, pipe);
4235 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4236 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4240 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4241 intel_opregion_asle_intr(dev);
4243 /* With MSI, interrupts are only generated when iir
4244 * transitions from zero to nonzero. If another bit got
4245 * set while we were handling the existing iir bits, then
4246 * we would never get another interrupt.
4248 * This is fine on non-MSI as well, as if we hit this path
4249 * we avoid exiting the interrupt handler only to generate
4252 * Note that for MSI this could cause a stray interrupt report
4253 * if an interrupt landed in the time between writing IIR and
4254 * the posting read. This should be rare enough to never
4255 * trigger the 99% of 100,000 interrupts test for disabling
4260 } while (iir & ~flip_mask);
4262 enable_rpm_wakeref_asserts(dev_priv);
4267 static void i915_irq_uninstall(struct drm_device * dev)
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4272 if (I915_HAS_HOTPLUG(dev)) {
4273 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4274 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4277 I915_WRITE16(HWSTAM, 0xffff);
4278 for_each_pipe(dev_priv, pipe) {
4279 /* Clear enable bits; then clear status bits */
4280 I915_WRITE(PIPESTAT(pipe), 0);
4281 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4283 I915_WRITE(IMR, 0xffffffff);
4284 I915_WRITE(IER, 0x0);
4286 I915_WRITE(IIR, I915_READ(IIR));
4289 static void i965_irq_preinstall(struct drm_device * dev)
4291 struct drm_i915_private *dev_priv = dev->dev_private;
4294 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4295 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4297 I915_WRITE(HWSTAM, 0xeffe);
4298 for_each_pipe(dev_priv, pipe)
4299 I915_WRITE(PIPESTAT(pipe), 0);
4300 I915_WRITE(IMR, 0xffffffff);
4301 I915_WRITE(IER, 0x0);
4305 static int i965_irq_postinstall(struct drm_device *dev)
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4311 /* Unmask the interrupts that we always want on. */
4312 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4313 I915_DISPLAY_PORT_INTERRUPT |
4314 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4315 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4316 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4317 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4318 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4320 enable_mask = ~dev_priv->irq_mask;
4321 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4322 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4323 enable_mask |= I915_USER_INTERRUPT;
4326 enable_mask |= I915_BSD_USER_INTERRUPT;
4328 /* Interrupt setup is already guaranteed to be single-threaded, this is
4329 * just to make the assert_spin_locked check happy. */
4330 spin_lock_irq(&dev_priv->irq_lock);
4331 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4332 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4333 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4334 spin_unlock_irq(&dev_priv->irq_lock);
4337 * Enable some error detection, note the instruction error mask
4338 * bit is reserved, so we leave it masked.
4341 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4342 GM45_ERROR_MEM_PRIV |
4343 GM45_ERROR_CP_PRIV |
4344 I915_ERROR_MEMORY_REFRESH);
4346 error_mask = ~(I915_ERROR_PAGE_TABLE |
4347 I915_ERROR_MEMORY_REFRESH);
4349 I915_WRITE(EMR, error_mask);
4351 I915_WRITE(IMR, dev_priv->irq_mask);
4352 I915_WRITE(IER, enable_mask);
4355 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4356 POSTING_READ(PORT_HOTPLUG_EN);
4358 i915_enable_asle_pipestat(dev);
4363 static void i915_hpd_irq_setup(struct drm_device *dev)
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4368 assert_spin_locked(&dev_priv->irq_lock);
4370 /* Note HDMI and DP share hotplug bits */
4371 /* enable bits are the same for all generations */
4372 hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
4373 /* Programming the CRT detection parameters tends
4374 to generate a spurious hotplug event about three
4375 seconds later. So just do it once.
4378 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4379 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4381 /* Ignore TV since it's buggy */
4382 i915_hotplug_interrupt_update_locked(dev_priv,
4383 HOTPLUG_INT_EN_MASK |
4384 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4385 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4389 static irqreturn_t i965_irq_handler(int irq, void *arg)
4391 struct drm_device *dev = arg;
4392 struct drm_i915_private *dev_priv = dev->dev_private;
4394 u32 pipe_stats[I915_MAX_PIPES];
4395 int ret = IRQ_NONE, pipe;
4397 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4398 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4400 if (!intel_irqs_enabled(dev_priv))
4403 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4404 disable_rpm_wakeref_asserts(dev_priv);
4406 iir = I915_READ(IIR);
4409 bool irq_received = (iir & ~flip_mask) != 0;
4410 bool blc_event = false;
4412 /* Can't rely on pipestat interrupt bit in iir as it might
4413 * have been cleared after the pipestat interrupt was received.
4414 * It doesn't set the bit in iir again, but it still produces
4415 * interrupts (for non-MSI).
4417 spin_lock(&dev_priv->irq_lock);
4418 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4419 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4421 for_each_pipe(dev_priv, pipe) {
4422 i915_reg_t reg = PIPESTAT(pipe);
4423 pipe_stats[pipe] = I915_READ(reg);
4426 * Clear the PIPE*STAT regs before the IIR
4428 if (pipe_stats[pipe] & 0x8000ffff) {
4429 I915_WRITE(reg, pipe_stats[pipe]);
4430 irq_received = true;
4433 spin_unlock(&dev_priv->irq_lock);
4440 /* Consume port. Then clear IIR or we'll miss events */
4441 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4442 i9xx_hpd_irq_handler(dev);
4444 I915_WRITE(IIR, iir & ~flip_mask);
4445 new_iir = I915_READ(IIR); /* Flush posted writes */
4447 if (iir & I915_USER_INTERRUPT)
4448 notify_ring(&dev_priv->ring[RCS]);
4449 if (iir & I915_BSD_USER_INTERRUPT)
4450 notify_ring(&dev_priv->ring[VCS]);
4452 for_each_pipe(dev_priv, pipe) {
4453 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4454 i915_handle_vblank(dev, pipe, pipe, iir))
4455 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4457 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4460 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4461 i9xx_pipe_crc_irq_handler(dev, pipe);
4463 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4464 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4467 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4468 intel_opregion_asle_intr(dev);
4470 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4471 gmbus_irq_handler(dev);
4473 /* With MSI, interrupts are only generated when iir
4474 * transitions from zero to nonzero. If another bit got
4475 * set while we were handling the existing iir bits, then
4476 * we would never get another interrupt.
4478 * This is fine on non-MSI as well, as if we hit this path
4479 * we avoid exiting the interrupt handler only to generate
4482 * Note that for MSI this could cause a stray interrupt report
4483 * if an interrupt landed in the time between writing IIR and
4484 * the posting read. This should be rare enough to never
4485 * trigger the 99% of 100,000 interrupts test for disabling
4491 enable_rpm_wakeref_asserts(dev_priv);
4496 static void i965_irq_uninstall(struct drm_device * dev)
4498 struct drm_i915_private *dev_priv = dev->dev_private;
4504 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4505 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4507 I915_WRITE(HWSTAM, 0xffffffff);
4508 for_each_pipe(dev_priv, pipe)
4509 I915_WRITE(PIPESTAT(pipe), 0);
4510 I915_WRITE(IMR, 0xffffffff);
4511 I915_WRITE(IER, 0x0);
4513 for_each_pipe(dev_priv, pipe)
4514 I915_WRITE(PIPESTAT(pipe),
4515 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4516 I915_WRITE(IIR, I915_READ(IIR));
4520 * intel_irq_init - initializes irq support
4521 * @dev_priv: i915 device instance
4523 * This function initializes all the irq support including work items, timers
4524 * and all the vtables. It does not setup the interrupt itself though.
4526 void intel_irq_init(struct drm_i915_private *dev_priv)
4528 struct drm_device *dev = dev_priv->dev;
4530 intel_hpd_init_work(dev_priv);
4532 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4533 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4535 /* Let's track the enabled rps events */
4536 if (IS_VALLEYVIEW(dev_priv))
4537 /* WaGsvRC0ResidencyMethod:vlv */
4538 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4540 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4542 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4543 i915_hangcheck_elapsed);
4545 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4547 if (IS_GEN2(dev_priv)) {
4548 dev->max_vblank_count = 0;
4549 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4550 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4551 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4552 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4554 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4555 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4559 * Opt out of the vblank disable timer on everything except gen2.
4560 * Gen2 doesn't have a hardware frame counter and so depends on
4561 * vblank interrupts to produce sane vblank seuquence numbers.
4563 if (!IS_GEN2(dev_priv))
4564 dev->vblank_disable_immediate = true;
4566 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4567 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4569 if (IS_CHERRYVIEW(dev_priv)) {
4570 dev->driver->irq_handler = cherryview_irq_handler;
4571 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4572 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4573 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4574 dev->driver->enable_vblank = valleyview_enable_vblank;
4575 dev->driver->disable_vblank = valleyview_disable_vblank;
4576 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4577 } else if (IS_VALLEYVIEW(dev_priv)) {
4578 dev->driver->irq_handler = valleyview_irq_handler;
4579 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4580 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4581 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4582 dev->driver->enable_vblank = valleyview_enable_vblank;
4583 dev->driver->disable_vblank = valleyview_disable_vblank;
4584 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4585 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4586 dev->driver->irq_handler = gen8_irq_handler;
4587 dev->driver->irq_preinstall = gen8_irq_reset;
4588 dev->driver->irq_postinstall = gen8_irq_postinstall;
4589 dev->driver->irq_uninstall = gen8_irq_uninstall;
4590 dev->driver->enable_vblank = gen8_enable_vblank;
4591 dev->driver->disable_vblank = gen8_disable_vblank;
4592 if (IS_BROXTON(dev))
4593 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4594 else if (HAS_PCH_SPT(dev))
4595 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4597 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4598 } else if (HAS_PCH_SPLIT(dev)) {
4599 dev->driver->irq_handler = ironlake_irq_handler;
4600 dev->driver->irq_preinstall = ironlake_irq_reset;
4601 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4602 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4603 dev->driver->enable_vblank = ironlake_enable_vblank;
4604 dev->driver->disable_vblank = ironlake_disable_vblank;
4605 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4607 if (INTEL_INFO(dev_priv)->gen == 2) {
4608 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4609 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4610 dev->driver->irq_handler = i8xx_irq_handler;
4611 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4612 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4613 dev->driver->irq_preinstall = i915_irq_preinstall;
4614 dev->driver->irq_postinstall = i915_irq_postinstall;
4615 dev->driver->irq_uninstall = i915_irq_uninstall;
4616 dev->driver->irq_handler = i915_irq_handler;
4618 dev->driver->irq_preinstall = i965_irq_preinstall;
4619 dev->driver->irq_postinstall = i965_irq_postinstall;
4620 dev->driver->irq_uninstall = i965_irq_uninstall;
4621 dev->driver->irq_handler = i965_irq_handler;
4623 if (I915_HAS_HOTPLUG(dev_priv))
4624 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4625 dev->driver->enable_vblank = i915_enable_vblank;
4626 dev->driver->disable_vblank = i915_disable_vblank;
4631 * intel_irq_install - enables the hardware interrupt
4632 * @dev_priv: i915 device instance
4634 * This function enables the hardware interrupt handling, but leaves the hotplug
4635 * handling still disabled. It is called after intel_irq_init().
4637 * In the driver load and resume code we need working interrupts in a few places
4638 * but don't want to deal with the hassle of concurrent probe and hotplug
4639 * workers. Hence the split into this two-stage approach.
4641 int intel_irq_install(struct drm_i915_private *dev_priv)
4644 * We enable some interrupt sources in our postinstall hooks, so mark
4645 * interrupts as enabled _before_ actually enabling them to avoid
4646 * special cases in our ordering checks.
4648 dev_priv->pm.irqs_enabled = true;
4650 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4654 * intel_irq_uninstall - finilizes all irq handling
4655 * @dev_priv: i915 device instance
4657 * This stops interrupt and hotplug handling and unregisters and frees all
4658 * resources acquired in the init functions.
4660 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4662 drm_irq_uninstall(dev_priv->dev);
4663 intel_hpd_cancel_work(dev_priv);
4664 dev_priv->pm.irqs_enabled = false;
4668 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4669 * @dev_priv: i915 device instance
4671 * This function is used to disable interrupts at runtime, both in the runtime
4672 * pm and the system suspend/resume code.
4674 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4676 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4677 dev_priv->pm.irqs_enabled = false;
4678 synchronize_irq(dev_priv->dev->irq);
4682 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4683 * @dev_priv: i915 device instance
4685 * This function is used to enable interrupts at runtime, both in the runtime
4686 * pm and the system suspend/resume code.
4688 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4690 dev_priv->pm.irqs_enabled = true;
4691 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4692 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);