1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #define MAX_NOPID ((u32)~0)
41 * Interrupts that are always left unmasked.
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
87 /* For display hotplug interrupt */
89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
129 i915_pipestat(int pipe)
139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
164 * intel_enable_asle - enable ASLE interrupt for OpRegion
166 void intel_enable_asle (struct drm_device *dev)
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
170 if (HAS_PCH_SPLIT(dev))
171 ironlake_enable_display_irq(dev_priv, DE_GSE);
173 i915_enable_pipestat(dev_priv, 1,
174 I915_LEGACY_BLC_EVENT_ENABLE);
176 i915_enable_pipestat(dev_priv, 0,
177 I915_LEGACY_BLC_EVENT_ENABLE);
182 * i915_pipe_enabled - check if a pipe is enabled
184 * @pipe: pipe to check
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
191 i915_pipe_enabled(struct drm_device *dev, int pipe)
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
196 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
202 /* Called from drm generic code, passed a 'crtc', which
203 * we use as a pipe index
205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
208 unsigned long high_frame;
209 unsigned long low_frame;
210 u32 high1, high2, low, count;
212 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
213 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
215 if (!i915_pipe_enabled(dev, pipe)) {
216 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
222 * High & low register fields aren't synchronized, so make sure
223 * we get a low value that's stable across two reads of the high
227 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
228 PIPE_FRAME_HIGH_SHIFT);
229 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
230 PIPE_FRAME_LOW_SHIFT);
231 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
232 PIPE_FRAME_HIGH_SHIFT);
233 } while (high1 != high2);
235 count = (high1 << 8) | low;
240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
243 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
245 if (!i915_pipe_enabled(dev, pipe)) {
246 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
251 return I915_READ(reg);
255 * Handle hotplug events outside the interrupt handler proper.
257 static void i915_hotplug_work_func(struct work_struct *work)
259 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
261 struct drm_device *dev = dev_priv->dev;
262 struct drm_mode_config *mode_config = &dev->mode_config;
263 struct drm_encoder *encoder;
265 if (mode_config->num_encoder) {
266 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
267 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
269 if (intel_encoder->hot_plug)
270 (*intel_encoder->hot_plug) (intel_encoder);
273 /* Just fire off a uevent and let userspace tell us what to do */
274 drm_helper_hpd_irq_event(dev);
277 static void i915_handle_rps_change(struct drm_device *dev)
279 drm_i915_private_t *dev_priv = dev->dev_private;
280 u32 busy_up, busy_down, max_avg, min_avg;
281 u8 new_delay = dev_priv->cur_delay;
283 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
284 busy_up = I915_READ(RCPREVBSYTUPAVG);
285 busy_down = I915_READ(RCPREVBSYTDNAVG);
286 max_avg = I915_READ(RCBMAXAVG);
287 min_avg = I915_READ(RCBMINAVG);
289 /* Handle RCS change request from hw */
290 if (busy_up > max_avg) {
291 if (dev_priv->cur_delay != dev_priv->max_delay)
292 new_delay = dev_priv->cur_delay - 1;
293 if (new_delay < dev_priv->max_delay)
294 new_delay = dev_priv->max_delay;
295 } else if (busy_down < min_avg) {
296 if (dev_priv->cur_delay != dev_priv->min_delay)
297 new_delay = dev_priv->cur_delay + 1;
298 if (new_delay > dev_priv->min_delay)
299 new_delay = dev_priv->min_delay;
302 if (ironlake_set_drps(dev, new_delay))
303 dev_priv->cur_delay = new_delay;
308 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
312 u32 de_iir, gt_iir, de_ier, pch_iir;
313 struct drm_i915_master_private *master_priv;
314 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
316 /* disable master interrupt before clearing iir */
317 de_ier = I915_READ(DEIER);
318 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
319 (void)I915_READ(DEIER);
321 de_iir = I915_READ(DEIIR);
322 gt_iir = I915_READ(GTIIR);
323 pch_iir = I915_READ(SDEIIR);
325 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
330 if (dev->primary->master) {
331 master_priv = dev->primary->master->driver_priv;
332 if (master_priv->sarea_priv)
333 master_priv->sarea_priv->last_dispatch =
334 READ_BREADCRUMB(dev_priv);
337 if (gt_iir & GT_PIPE_NOTIFY) {
338 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
339 render_ring->irq_gem_seqno = seqno;
340 trace_i915_gem_request_complete(dev, seqno);
341 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
345 if (gt_iir & GT_BSD_USER_INTERRUPT)
346 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
350 ironlake_opregion_gse_intr(dev);
352 if (de_iir & DE_PLANEA_FLIP_DONE) {
353 intel_prepare_page_flip(dev, 0);
354 intel_finish_page_flip(dev, 0);
357 if (de_iir & DE_PLANEB_FLIP_DONE) {
358 intel_prepare_page_flip(dev, 1);
359 intel_finish_page_flip(dev, 1);
362 if (de_iir & DE_PIPEA_VBLANK)
363 drm_handle_vblank(dev, 0);
365 if (de_iir & DE_PIPEB_VBLANK)
366 drm_handle_vblank(dev, 1);
368 /* check event from PCH */
369 if ((de_iir & DE_PCH_EVENT) &&
370 (pch_iir & SDE_HOTPLUG_MASK)) {
371 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
374 if (de_iir & DE_PCU_EVENT) {
375 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
376 i915_handle_rps_change(dev);
379 /* should clear PCH hotplug event before clear CPU irq */
380 I915_WRITE(SDEIIR, pch_iir);
381 I915_WRITE(GTIIR, gt_iir);
382 I915_WRITE(DEIIR, de_iir);
385 I915_WRITE(DEIER, de_ier);
386 (void)I915_READ(DEIER);
392 * i915_error_work_func - do process context error handling work
395 * Fire an error uevent so userspace can see that a hang or error
398 static void i915_error_work_func(struct work_struct *work)
400 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
402 struct drm_device *dev = dev_priv->dev;
403 char *error_event[] = { "ERROR=1", NULL };
404 char *reset_event[] = { "RESET=1", NULL };
405 char *reset_done_event[] = { "ERROR=0", NULL };
407 DRM_DEBUG_DRIVER("generating error event\n");
408 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
410 if (atomic_read(&dev_priv->mm.wedged)) {
412 DRM_DEBUG_DRIVER("resetting chip\n");
413 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
414 if (!i965_reset(dev, GDRST_RENDER)) {
415 atomic_set(&dev_priv->mm.wedged, 0);
416 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
419 DRM_DEBUG_DRIVER("reboot required\n");
424 static struct drm_i915_error_object *
425 i915_error_object_create(struct drm_device *dev,
426 struct drm_gem_object *src)
428 struct drm_i915_error_object *dst;
429 struct drm_i915_gem_object *src_priv;
430 int page, page_count;
435 src_priv = to_intel_bo(src);
436 if (src_priv->pages == NULL)
439 page_count = src->size / PAGE_SIZE;
441 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
445 for (page = 0; page < page_count; page++) {
446 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
451 local_irq_save(flags);
452 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
453 memcpy(d, s, PAGE_SIZE);
454 kunmap_atomic(s, KM_IRQ0);
455 local_irq_restore(flags);
456 dst->pages[page] = d;
458 dst->page_count = page_count;
459 dst->gtt_offset = src_priv->gtt_offset;
465 kfree(dst->pages[page]);
471 i915_error_object_free(struct drm_i915_error_object *obj)
478 for (page = 0; page < obj->page_count; page++)
479 kfree(obj->pages[page]);
485 i915_error_state_free(struct drm_device *dev,
486 struct drm_i915_error_state *error)
488 i915_error_object_free(error->batchbuffer[0]);
489 i915_error_object_free(error->batchbuffer[1]);
490 i915_error_object_free(error->ringbuffer);
491 kfree(error->active_bo);
496 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
500 if (IS_I830(dev) || IS_845G(dev))
501 cmd = MI_BATCH_BUFFER;
502 else if (IS_I965G(dev))
503 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
504 MI_BATCH_NON_SECURE_I965);
506 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
508 return ring[0] == cmd ? ring[1] : 0;
512 i915_ringbuffer_last_batch(struct drm_device *dev)
514 struct drm_i915_private *dev_priv = dev->dev_private;
518 /* Locate the current position in the ringbuffer and walk back
519 * to find the most recently dispatched batch buffer.
522 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
523 ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
525 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
526 bbaddr = i915_get_bbaddr(dev, ring);
532 ring = (u32 *)(dev_priv->render_ring.virtual_start
533 + dev_priv->render_ring.size);
534 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
535 bbaddr = i915_get_bbaddr(dev, ring);
545 * i915_capture_error_state - capture an error record for later analysis
548 * Should be called when an error is detected (either a hang or an error
549 * interrupt) to capture error state from the time of the error. Fills
550 * out a structure which becomes available in debugfs for user level tools
553 static void i915_capture_error_state(struct drm_device *dev)
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 struct drm_i915_gem_object *obj_priv;
557 struct drm_i915_error_state *error;
558 struct drm_gem_object *batchbuffer[2];
563 spin_lock_irqsave(&dev_priv->error_lock, flags);
564 error = dev_priv->first_error;
565 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
569 error = kmalloc(sizeof(*error), GFP_ATOMIC);
571 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
575 error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
576 error->eir = I915_READ(EIR);
577 error->pgtbl_er = I915_READ(PGTBL_ER);
578 error->pipeastat = I915_READ(PIPEASTAT);
579 error->pipebstat = I915_READ(PIPEBSTAT);
580 error->instpm = I915_READ(INSTPM);
581 if (!IS_I965G(dev)) {
582 error->ipeir = I915_READ(IPEIR);
583 error->ipehr = I915_READ(IPEHR);
584 error->instdone = I915_READ(INSTDONE);
585 error->acthd = I915_READ(ACTHD);
588 error->ipeir = I915_READ(IPEIR_I965);
589 error->ipehr = I915_READ(IPEHR_I965);
590 error->instdone = I915_READ(INSTDONE_I965);
591 error->instps = I915_READ(INSTPS);
592 error->instdone1 = I915_READ(INSTDONE1);
593 error->acthd = I915_READ(ACTHD_I965);
594 error->bbaddr = I915_READ64(BB_ADDR);
597 bbaddr = i915_ringbuffer_last_batch(dev);
599 /* Grab the current batchbuffer, most likely to have crashed. */
600 batchbuffer[0] = NULL;
601 batchbuffer[1] = NULL;
603 list_for_each_entry(obj_priv,
604 &dev_priv->render_ring.active_list, list) {
606 struct drm_gem_object *obj = &obj_priv->base;
608 if (batchbuffer[0] == NULL &&
609 bbaddr >= obj_priv->gtt_offset &&
610 bbaddr < obj_priv->gtt_offset + obj->size)
611 batchbuffer[0] = obj;
613 if (batchbuffer[1] == NULL &&
614 error->acthd >= obj_priv->gtt_offset &&
615 error->acthd < obj_priv->gtt_offset + obj->size &&
616 batchbuffer[0] != obj)
617 batchbuffer[1] = obj;
622 /* We need to copy these to an anonymous buffer as the simplest
623 * method to avoid being overwritten by userpace.
625 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
626 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
628 /* Record the ringbuffer */
629 error->ringbuffer = i915_error_object_create(dev,
630 dev_priv->render_ring.gem_object);
632 /* Record buffers on the active list. */
633 error->active_bo = NULL;
634 error->active_bo_count = 0;
637 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
640 if (error->active_bo) {
642 list_for_each_entry(obj_priv,
643 &dev_priv->render_ring.active_list, list) {
644 struct drm_gem_object *obj = &obj_priv->base;
646 error->active_bo[i].size = obj->size;
647 error->active_bo[i].name = obj->name;
648 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
649 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
650 error->active_bo[i].read_domains = obj->read_domains;
651 error->active_bo[i].write_domain = obj->write_domain;
652 error->active_bo[i].fence_reg = obj_priv->fence_reg;
653 error->active_bo[i].pinned = 0;
654 if (obj_priv->pin_count > 0)
655 error->active_bo[i].pinned = 1;
656 if (obj_priv->user_pin_count > 0)
657 error->active_bo[i].pinned = -1;
658 error->active_bo[i].tiling = obj_priv->tiling_mode;
659 error->active_bo[i].dirty = obj_priv->dirty;
660 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
665 error->active_bo_count = i;
668 do_gettimeofday(&error->time);
670 spin_lock_irqsave(&dev_priv->error_lock, flags);
671 if (dev_priv->first_error == NULL) {
672 dev_priv->first_error = error;
675 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
678 i915_error_state_free(dev, error);
681 void i915_destroy_error_state(struct drm_device *dev)
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct drm_i915_error_state *error;
686 spin_lock(&dev_priv->error_lock);
687 error = dev_priv->first_error;
688 dev_priv->first_error = NULL;
689 spin_unlock(&dev_priv->error_lock);
692 i915_error_state_free(dev, error);
695 static void i915_report_and_clear_eir(struct drm_device *dev)
697 struct drm_i915_private *dev_priv = dev->dev_private;
698 u32 eir = I915_READ(EIR);
703 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
707 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
708 u32 ipeir = I915_READ(IPEIR_I965);
710 printk(KERN_ERR " IPEIR: 0x%08x\n",
711 I915_READ(IPEIR_I965));
712 printk(KERN_ERR " IPEHR: 0x%08x\n",
713 I915_READ(IPEHR_I965));
714 printk(KERN_ERR " INSTDONE: 0x%08x\n",
715 I915_READ(INSTDONE_I965));
716 printk(KERN_ERR " INSTPS: 0x%08x\n",
718 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
719 I915_READ(INSTDONE1));
720 printk(KERN_ERR " ACTHD: 0x%08x\n",
721 I915_READ(ACTHD_I965));
722 I915_WRITE(IPEIR_I965, ipeir);
723 (void)I915_READ(IPEIR_I965);
725 if (eir & GM45_ERROR_PAGE_TABLE) {
726 u32 pgtbl_err = I915_READ(PGTBL_ER);
727 printk(KERN_ERR "page table error\n");
728 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
730 I915_WRITE(PGTBL_ER, pgtbl_err);
731 (void)I915_READ(PGTBL_ER);
736 if (eir & I915_ERROR_PAGE_TABLE) {
737 u32 pgtbl_err = I915_READ(PGTBL_ER);
738 printk(KERN_ERR "page table error\n");
739 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
741 I915_WRITE(PGTBL_ER, pgtbl_err);
742 (void)I915_READ(PGTBL_ER);
746 if (eir & I915_ERROR_MEMORY_REFRESH) {
747 u32 pipea_stats = I915_READ(PIPEASTAT);
748 u32 pipeb_stats = I915_READ(PIPEBSTAT);
750 printk(KERN_ERR "memory refresh error\n");
751 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
753 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
755 /* pipestat has already been acked */
757 if (eir & I915_ERROR_INSTRUCTION) {
758 printk(KERN_ERR "instruction error\n");
759 printk(KERN_ERR " INSTPM: 0x%08x\n",
761 if (!IS_I965G(dev)) {
762 u32 ipeir = I915_READ(IPEIR);
764 printk(KERN_ERR " IPEIR: 0x%08x\n",
766 printk(KERN_ERR " IPEHR: 0x%08x\n",
768 printk(KERN_ERR " INSTDONE: 0x%08x\n",
769 I915_READ(INSTDONE));
770 printk(KERN_ERR " ACTHD: 0x%08x\n",
772 I915_WRITE(IPEIR, ipeir);
773 (void)I915_READ(IPEIR);
775 u32 ipeir = I915_READ(IPEIR_I965);
777 printk(KERN_ERR " IPEIR: 0x%08x\n",
778 I915_READ(IPEIR_I965));
779 printk(KERN_ERR " IPEHR: 0x%08x\n",
780 I915_READ(IPEHR_I965));
781 printk(KERN_ERR " INSTDONE: 0x%08x\n",
782 I915_READ(INSTDONE_I965));
783 printk(KERN_ERR " INSTPS: 0x%08x\n",
785 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
786 I915_READ(INSTDONE1));
787 printk(KERN_ERR " ACTHD: 0x%08x\n",
788 I915_READ(ACTHD_I965));
789 I915_WRITE(IPEIR_I965, ipeir);
790 (void)I915_READ(IPEIR_I965);
794 I915_WRITE(EIR, eir);
795 (void)I915_READ(EIR);
796 eir = I915_READ(EIR);
799 * some errors might have become stuck,
802 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
803 I915_WRITE(EMR, I915_READ(EMR) | eir);
804 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
809 * i915_handle_error - handle an error interrupt
812 * Do some basic checking of regsiter state at error interrupt time and
813 * dump it to the syslog. Also call i915_capture_error_state() to make
814 * sure we get a record and make it available in debugfs. Fire a uevent
815 * so userspace knows something bad happened (should trigger collection
816 * of a ring dump etc.).
818 static void i915_handle_error(struct drm_device *dev, bool wedged)
820 struct drm_i915_private *dev_priv = dev->dev_private;
822 i915_capture_error_state(dev);
823 i915_report_and_clear_eir(dev);
826 atomic_set(&dev_priv->mm.wedged, 1);
829 * Wakeup waiting processes so they don't hang
831 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
834 queue_work(dev_priv->wq, &dev_priv->error_work);
837 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
839 struct drm_device *dev = (struct drm_device *) arg;
840 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
841 struct drm_i915_master_private *master_priv;
843 u32 pipea_stats, pipeb_stats;
847 unsigned long irqflags;
850 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
852 atomic_inc(&dev_priv->irq_received);
854 if (HAS_PCH_SPLIT(dev))
855 return ironlake_irq_handler(dev);
857 iir = I915_READ(IIR);
860 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
861 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
863 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
864 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
868 irq_received = iir != 0;
870 /* Can't rely on pipestat interrupt bit in iir as it might
871 * have been cleared after the pipestat interrupt was received.
872 * It doesn't set the bit in iir again, but it still produces
873 * interrupts (for non-MSI).
875 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
876 pipea_stats = I915_READ(PIPEASTAT);
877 pipeb_stats = I915_READ(PIPEBSTAT);
879 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
880 i915_handle_error(dev, false);
883 * Clear the PIPE(A|B)STAT regs before the IIR
885 if (pipea_stats & 0x8000ffff) {
886 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
887 DRM_DEBUG_DRIVER("pipe a underrun\n");
888 I915_WRITE(PIPEASTAT, pipea_stats);
892 if (pipeb_stats & 0x8000ffff) {
893 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
894 DRM_DEBUG_DRIVER("pipe b underrun\n");
895 I915_WRITE(PIPEBSTAT, pipeb_stats);
898 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
905 /* Consume port. Then clear IIR or we'll miss events */
906 if ((I915_HAS_HOTPLUG(dev)) &&
907 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
908 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
910 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
912 if (hotplug_status & dev_priv->hotplug_supported_mask)
913 queue_work(dev_priv->wq,
914 &dev_priv->hotplug_work);
916 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
917 I915_READ(PORT_HOTPLUG_STAT);
920 I915_WRITE(IIR, iir);
921 new_iir = I915_READ(IIR); /* Flush posted writes */
923 if (dev->primary->master) {
924 master_priv = dev->primary->master->driver_priv;
925 if (master_priv->sarea_priv)
926 master_priv->sarea_priv->last_dispatch =
927 READ_BREADCRUMB(dev_priv);
930 if (iir & I915_USER_INTERRUPT) {
932 render_ring->get_gem_seqno(dev, render_ring);
933 render_ring->irq_gem_seqno = seqno;
934 trace_i915_gem_request_complete(dev, seqno);
935 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
936 dev_priv->hangcheck_count = 0;
937 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
940 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
941 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
943 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
944 intel_prepare_page_flip(dev, 0);
946 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
947 intel_prepare_page_flip(dev, 1);
949 if (pipea_stats & vblank_status) {
951 drm_handle_vblank(dev, 0);
952 intel_finish_page_flip(dev, 0);
955 if (pipeb_stats & vblank_status) {
957 drm_handle_vblank(dev, 1);
958 intel_finish_page_flip(dev, 1);
961 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
962 (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
963 (iir & I915_ASLE_INTERRUPT))
964 opregion_asle_intr(dev);
966 /* With MSI, interrupts are only generated when iir
967 * transitions from zero to nonzero. If another bit got
968 * set while we were handling the existing iir bits, then
969 * we would never get another interrupt.
971 * This is fine on non-MSI as well, as if we hit this path
972 * we avoid exiting the interrupt handler only to generate
975 * Note that for MSI this could cause a stray interrupt report
976 * if an interrupt landed in the time between writing IIR and
977 * the posting read. This should be rare enough to never
978 * trigger the 99% of 100,000 interrupts test for disabling
987 static int i915_emit_irq(struct drm_device * dev)
989 drm_i915_private_t *dev_priv = dev->dev_private;
990 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
992 i915_kernel_lost_context(dev);
994 DRM_DEBUG_DRIVER("\n");
997 if (dev_priv->counter > 0x7FFFFFFFUL)
998 dev_priv->counter = 1;
999 if (master_priv->sarea_priv)
1000 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1003 OUT_RING(MI_STORE_DWORD_INDEX);
1004 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1005 OUT_RING(dev_priv->counter);
1006 OUT_RING(MI_USER_INTERRUPT);
1009 return dev_priv->counter;
1012 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1014 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1015 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1017 if (dev_priv->trace_irq_seqno == 0)
1018 render_ring->user_irq_get(dev, render_ring);
1020 dev_priv->trace_irq_seqno = seqno;
1023 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1025 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1026 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1028 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1030 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1031 READ_BREADCRUMB(dev_priv));
1033 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1034 if (master_priv->sarea_priv)
1035 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1039 if (master_priv->sarea_priv)
1040 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1042 render_ring->user_irq_get(dev, render_ring);
1043 DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1044 READ_BREADCRUMB(dev_priv) >= irq_nr);
1045 render_ring->user_irq_put(dev, render_ring);
1047 if (ret == -EBUSY) {
1048 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1049 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1055 /* Needs the lock as it touches the ring.
1057 int i915_irq_emit(struct drm_device *dev, void *data,
1058 struct drm_file *file_priv)
1060 drm_i915_private_t *dev_priv = dev->dev_private;
1061 drm_i915_irq_emit_t *emit = data;
1064 if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1065 DRM_ERROR("called with no initialization\n");
1069 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1071 mutex_lock(&dev->struct_mutex);
1072 result = i915_emit_irq(dev);
1073 mutex_unlock(&dev->struct_mutex);
1075 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1076 DRM_ERROR("copy_to_user\n");
1083 /* Doesn't need the hardware lock.
1085 int i915_irq_wait(struct drm_device *dev, void *data,
1086 struct drm_file *file_priv)
1088 drm_i915_private_t *dev_priv = dev->dev_private;
1089 drm_i915_irq_wait_t *irqwait = data;
1092 DRM_ERROR("called with no initialization\n");
1096 return i915_wait_irq(dev, irqwait->irq_seq);
1099 /* Called from drm generic code, passed 'crtc' which
1100 * we use as a pipe index
1102 int i915_enable_vblank(struct drm_device *dev, int pipe)
1104 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1105 unsigned long irqflags;
1106 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1109 pipeconf = I915_READ(pipeconf_reg);
1110 if (!(pipeconf & PIPEACONF_ENABLE))
1113 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1114 if (HAS_PCH_SPLIT(dev))
1115 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1116 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1117 else if (IS_I965G(dev))
1118 i915_enable_pipestat(dev_priv, pipe,
1119 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1121 i915_enable_pipestat(dev_priv, pipe,
1122 PIPE_VBLANK_INTERRUPT_ENABLE);
1123 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1127 /* Called from drm generic code, passed 'crtc' which
1128 * we use as a pipe index
1130 void i915_disable_vblank(struct drm_device *dev, int pipe)
1132 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1133 unsigned long irqflags;
1135 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1136 if (HAS_PCH_SPLIT(dev))
1137 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1138 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1140 i915_disable_pipestat(dev_priv, pipe,
1141 PIPE_VBLANK_INTERRUPT_ENABLE |
1142 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1143 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1146 void i915_enable_interrupt (struct drm_device *dev)
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1150 if (!HAS_PCH_SPLIT(dev))
1151 opregion_enable_asle(dev);
1152 dev_priv->irq_enabled = 1;
1156 /* Set the vblank monitor pipe
1158 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1159 struct drm_file *file_priv)
1161 drm_i915_private_t *dev_priv = dev->dev_private;
1164 DRM_ERROR("called with no initialization\n");
1171 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1172 struct drm_file *file_priv)
1174 drm_i915_private_t *dev_priv = dev->dev_private;
1175 drm_i915_vblank_pipe_t *pipe = data;
1178 DRM_ERROR("called with no initialization\n");
1182 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1188 * Schedule buffer swap at given vertical blank.
1190 int i915_vblank_swap(struct drm_device *dev, void *data,
1191 struct drm_file *file_priv)
1193 /* The delayed swap mechanism was fundamentally racy, and has been
1194 * removed. The model was that the client requested a delayed flip/swap
1195 * from the kernel, then waited for vblank before continuing to perform
1196 * rendering. The problem was that the kernel might wake the client
1197 * up before it dispatched the vblank swap (since the lock has to be
1198 * held while touching the ringbuffer), in which case the client would
1199 * clear and start the next frame before the swap occurred, and
1200 * flicker would occur in addition to likely missing the vblank.
1202 * In the absence of this ioctl, userland falls back to a correct path
1203 * of waiting for a vblank, then dispatching the swap on its own.
1204 * Context switching to userland and back is plenty fast enough for
1205 * meeting the requirements of vblank swapping.
1210 struct drm_i915_gem_request *
1211 i915_get_tail_request(struct drm_device *dev)
1213 drm_i915_private_t *dev_priv = dev->dev_private;
1214 return list_entry(dev_priv->render_ring.request_list.prev,
1215 struct drm_i915_gem_request, list);
1219 * This is called when the chip hasn't reported back with completed
1220 * batchbuffers in a long time. The first time this is called we simply record
1221 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1222 * again, we assume the chip is wedged and try to fix it.
1224 void i915_hangcheck_elapsed(unsigned long data)
1226 struct drm_device *dev = (struct drm_device *)data;
1227 drm_i915_private_t *dev_priv = dev->dev_private;
1230 /* No reset support on this chip yet. */
1235 acthd = I915_READ(ACTHD);
1237 acthd = I915_READ(ACTHD_I965);
1239 /* If all work is done then ACTHD clearly hasn't advanced. */
1240 if (list_empty(&dev_priv->render_ring.request_list) ||
1241 i915_seqno_passed(i915_get_gem_seqno(dev,
1242 &dev_priv->render_ring),
1243 i915_get_tail_request(dev)->seqno)) {
1244 dev_priv->hangcheck_count = 0;
1248 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1249 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1250 i915_handle_error(dev, true);
1254 /* Reset timer case chip hangs without another request being added */
1255 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1257 if (acthd != dev_priv->last_acthd)
1258 dev_priv->hangcheck_count = 0;
1260 dev_priv->hangcheck_count++;
1262 dev_priv->last_acthd = acthd;
1267 static void ironlake_irq_preinstall(struct drm_device *dev)
1269 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1271 I915_WRITE(HWSTAM, 0xeffe);
1273 /* XXX hotplug from PCH */
1275 I915_WRITE(DEIMR, 0xffffffff);
1276 I915_WRITE(DEIER, 0x0);
1277 (void) I915_READ(DEIER);
1280 I915_WRITE(GTIMR, 0xffffffff);
1281 I915_WRITE(GTIER, 0x0);
1282 (void) I915_READ(GTIER);
1284 /* south display irq */
1285 I915_WRITE(SDEIMR, 0xffffffff);
1286 I915_WRITE(SDEIER, 0x0);
1287 (void) I915_READ(SDEIER);
1290 static int ironlake_irq_postinstall(struct drm_device *dev)
1292 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1293 /* enable kind of interrupts always enabled */
1294 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1295 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1296 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1297 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1298 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1300 dev_priv->irq_mask_reg = ~display_mask;
1301 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1303 /* should always can generate irq */
1304 I915_WRITE(DEIIR, I915_READ(DEIIR));
1305 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1306 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1307 (void) I915_READ(DEIER);
1309 /* user interrupt should be enabled, but masked initial */
1310 dev_priv->gt_irq_mask_reg = ~render_mask;
1311 dev_priv->gt_irq_enable_reg = render_mask;
1313 I915_WRITE(GTIIR, I915_READ(GTIIR));
1314 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1315 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1316 (void) I915_READ(GTIER);
1318 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1319 dev_priv->pch_irq_enable_reg = hotplug_mask;
1321 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1322 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1323 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1324 (void) I915_READ(SDEIER);
1326 if (IS_IRONLAKE_M(dev)) {
1327 /* Clear & enable PCU event interrupts */
1328 I915_WRITE(DEIIR, DE_PCU_EVENT);
1329 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1330 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1336 void i915_driver_irq_preinstall(struct drm_device * dev)
1338 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1340 atomic_set(&dev_priv->irq_received, 0);
1342 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1343 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1345 if (HAS_PCH_SPLIT(dev)) {
1346 ironlake_irq_preinstall(dev);
1350 if (I915_HAS_HOTPLUG(dev)) {
1351 I915_WRITE(PORT_HOTPLUG_EN, 0);
1352 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1355 I915_WRITE(HWSTAM, 0xeffe);
1356 I915_WRITE(PIPEASTAT, 0);
1357 I915_WRITE(PIPEBSTAT, 0);
1358 I915_WRITE(IMR, 0xffffffff);
1359 I915_WRITE(IER, 0x0);
1360 (void) I915_READ(IER);
1364 * Must be called after intel_modeset_init or hotplug interrupts won't be
1365 * enabled correctly.
1367 int i915_driver_irq_postinstall(struct drm_device *dev)
1369 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1370 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1373 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1376 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1378 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1380 if (HAS_PCH_SPLIT(dev))
1381 return ironlake_irq_postinstall(dev);
1383 /* Unmask the interrupts that we always want on. */
1384 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1386 dev_priv->pipestat[0] = 0;
1387 dev_priv->pipestat[1] = 0;
1389 if (I915_HAS_HOTPLUG(dev)) {
1390 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1392 /* Note HDMI and DP share bits */
1393 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1394 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1395 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1396 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1397 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1398 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1399 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1400 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1401 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1402 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1403 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1404 hotplug_en |= CRT_HOTPLUG_INT_EN;
1405 /* Ignore TV since it's buggy */
1407 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1409 /* Enable in IER... */
1410 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1411 /* and unmask in IMR */
1412 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1416 * Enable some error detection, note the instruction error mask
1417 * bit is reserved, so we leave it masked.
1420 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1421 GM45_ERROR_MEM_PRIV |
1422 GM45_ERROR_CP_PRIV |
1423 I915_ERROR_MEMORY_REFRESH);
1425 error_mask = ~(I915_ERROR_PAGE_TABLE |
1426 I915_ERROR_MEMORY_REFRESH);
1428 I915_WRITE(EMR, error_mask);
1430 /* Disable pipe interrupt enables, clear pending pipe status */
1431 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1432 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1433 /* Clear pending interrupt status */
1434 I915_WRITE(IIR, I915_READ(IIR));
1436 I915_WRITE(IER, enable_mask);
1437 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1438 (void) I915_READ(IER);
1440 opregion_enable_asle(dev);
1445 static void ironlake_irq_uninstall(struct drm_device *dev)
1447 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1448 I915_WRITE(HWSTAM, 0xffffffff);
1450 I915_WRITE(DEIMR, 0xffffffff);
1451 I915_WRITE(DEIER, 0x0);
1452 I915_WRITE(DEIIR, I915_READ(DEIIR));
1454 I915_WRITE(GTIMR, 0xffffffff);
1455 I915_WRITE(GTIER, 0x0);
1456 I915_WRITE(GTIIR, I915_READ(GTIIR));
1459 void i915_driver_irq_uninstall(struct drm_device * dev)
1461 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1466 dev_priv->vblank_pipe = 0;
1468 if (HAS_PCH_SPLIT(dev)) {
1469 ironlake_irq_uninstall(dev);
1473 if (I915_HAS_HOTPLUG(dev)) {
1474 I915_WRITE(PORT_HOTPLUG_EN, 0);
1475 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1478 I915_WRITE(HWSTAM, 0xffffffff);
1479 I915_WRITE(PIPEASTAT, 0);
1480 I915_WRITE(PIPEBSTAT, 0);
1481 I915_WRITE(IMR, 0xffffffff);
1482 I915_WRITE(IER, 0x0);
1484 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1485 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1486 I915_WRITE(IIR, I915_READ(IIR));