1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #define MAX_NOPID ((u32)~0)
41 * Interrupts that are always left unmasked.
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
67 /* For display hotplug interrupt */
69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
71 if ((dev_priv->irq_mask & mask) != 0) {
72 dev_priv->irq_mask &= ~mask;
73 I915_WRITE(DEIMR, dev_priv->irq_mask);
79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
81 if ((dev_priv->irq_mask & mask) != mask) {
82 dev_priv->irq_mask |= mask;
83 I915_WRITE(DEIMR, dev_priv->irq_mask);
89 i915_pipestat(int pipe)
99 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
101 if ((dev_priv->pipestat[pipe] & mask) != mask) {
102 u32 reg = i915_pipestat(pipe);
104 dev_priv->pipestat[pipe] |= mask;
105 /* Enable the interrupt, clear any pending status */
106 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
112 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
114 if ((dev_priv->pipestat[pipe] & mask) != 0) {
115 u32 reg = i915_pipestat(pipe);
117 dev_priv->pipestat[pipe] &= ~mask;
118 I915_WRITE(reg, dev_priv->pipestat[pipe]);
124 * intel_enable_asle - enable ASLE interrupt for OpRegion
126 void intel_enable_asle(struct drm_device *dev)
128 drm_i915_private_t *dev_priv = dev->dev_private;
129 unsigned long irqflags;
131 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
133 if (HAS_PCH_SPLIT(dev))
134 ironlake_enable_display_irq(dev_priv, DE_GSE);
136 i915_enable_pipestat(dev_priv, 1,
137 PIPE_LEGACY_BLC_EVENT_ENABLE);
138 if (INTEL_INFO(dev)->gen >= 4)
139 i915_enable_pipestat(dev_priv, 0,
140 PIPE_LEGACY_BLC_EVENT_ENABLE);
143 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
147 * i915_pipe_enabled - check if a pipe is enabled
149 * @pipe: pipe to check
151 * Reading certain registers when the pipe is disabled can hang the chip.
152 * Use this routine to make sure the PLL is running and the pipe is active
153 * before reading such registers if unsure.
156 i915_pipe_enabled(struct drm_device *dev, int pipe)
158 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
159 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
162 /* Called from drm generic code, passed a 'crtc', which
163 * we use as a pipe index
165 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
168 unsigned long high_frame;
169 unsigned long low_frame;
170 u32 high1, high2, low;
172 if (!i915_pipe_enabled(dev, pipe)) {
173 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
178 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
179 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
182 * High & low register fields aren't synchronized, so make sure
183 * we get a low value that's stable across two reads of the high
187 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
188 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
189 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
190 } while (high1 != high2);
192 high1 >>= PIPE_FRAME_HIGH_SHIFT;
193 low >>= PIPE_FRAME_LOW_SHIFT;
194 return (high1 << 8) | low;
197 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
202 if (!i915_pipe_enabled(dev, pipe)) {
203 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
208 return I915_READ(reg);
211 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
212 int *vpos, int *hpos)
214 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
215 u32 vbl = 0, position = 0;
216 int vbl_start, vbl_end, htotal, vtotal;
220 if (!i915_pipe_enabled(dev, pipe)) {
221 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
227 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
229 if (INTEL_INFO(dev)->gen >= 4) {
230 /* No obvious pixelcount register. Only query vertical
231 * scanout position from Display scan line register.
233 position = I915_READ(PIPEDSL(pipe));
235 /* Decode into vertical scanout position. Don't have
236 * horizontal scanout position.
238 *vpos = position & 0x1fff;
241 /* Have access to pixelcount since start of frame.
242 * We can split this into vertical and horizontal
245 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
247 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
248 *vpos = position / htotal;
249 *hpos = position - (*vpos * htotal);
252 /* Query vblank area. */
253 vbl = I915_READ(VBLANK(pipe));
255 /* Test position against vblank region. */
256 vbl_start = vbl & 0x1fff;
257 vbl_end = (vbl >> 16) & 0x1fff;
259 if ((*vpos < vbl_start) || (*vpos > vbl_end))
262 /* Inside "upper part" of vblank area? Apply corrective offset: */
263 if (in_vbl && (*vpos >= vbl_start))
264 *vpos = *vpos - vtotal;
266 /* Readouts valid? */
268 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
272 ret |= DRM_SCANOUTPOS_INVBL;
277 int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
279 struct timeval *vblank_time,
282 struct drm_i915_private *dev_priv = dev->dev_private;
283 struct drm_crtc *crtc;
285 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
286 DRM_ERROR("Invalid crtc %d\n", pipe);
290 /* Get drm_crtc to timestamp: */
291 crtc = intel_get_crtc_for_pipe(dev, pipe);
293 DRM_ERROR("Invalid crtc %d\n", pipe);
297 if (!crtc->enabled) {
298 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
302 /* Helper routine in DRM core does all the work: */
303 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
309 * Handle hotplug events outside the interrupt handler proper.
311 static void i915_hotplug_work_func(struct work_struct *work)
313 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
315 struct drm_device *dev = dev_priv->dev;
316 struct drm_mode_config *mode_config = &dev->mode_config;
317 struct intel_encoder *encoder;
319 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
320 if (encoder->hot_plug)
321 encoder->hot_plug(encoder);
323 /* Just fire off a uevent and let userspace tell us what to do */
324 drm_helper_hpd_irq_event(dev);
327 static void i915_handle_rps_change(struct drm_device *dev)
329 drm_i915_private_t *dev_priv = dev->dev_private;
330 u32 busy_up, busy_down, max_avg, min_avg;
331 u8 new_delay = dev_priv->cur_delay;
333 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
334 busy_up = I915_READ(RCPREVBSYTUPAVG);
335 busy_down = I915_READ(RCPREVBSYTDNAVG);
336 max_avg = I915_READ(RCBMAXAVG);
337 min_avg = I915_READ(RCBMINAVG);
339 /* Handle RCS change request from hw */
340 if (busy_up > max_avg) {
341 if (dev_priv->cur_delay != dev_priv->max_delay)
342 new_delay = dev_priv->cur_delay - 1;
343 if (new_delay < dev_priv->max_delay)
344 new_delay = dev_priv->max_delay;
345 } else if (busy_down < min_avg) {
346 if (dev_priv->cur_delay != dev_priv->min_delay)
347 new_delay = dev_priv->cur_delay + 1;
348 if (new_delay > dev_priv->min_delay)
349 new_delay = dev_priv->min_delay;
352 if (ironlake_set_drps(dev, new_delay))
353 dev_priv->cur_delay = new_delay;
358 static void notify_ring(struct drm_device *dev,
359 struct intel_ring_buffer *ring)
361 struct drm_i915_private *dev_priv = dev->dev_private;
364 if (ring->obj == NULL)
367 seqno = ring->get_seqno(ring);
368 trace_i915_gem_request_complete(dev, seqno);
370 ring->irq_seqno = seqno;
371 wake_up_all(&ring->irq_queue);
373 dev_priv->hangcheck_count = 0;
374 mod_timer(&dev_priv->hangcheck_timer,
375 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
378 static void gen6_pm_irq_handler(struct drm_device *dev)
380 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
381 u8 new_delay = dev_priv->cur_delay;
384 pm_iir = I915_READ(GEN6_PMIIR);
388 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
389 if (dev_priv->cur_delay != dev_priv->max_delay)
390 new_delay = dev_priv->cur_delay + 1;
391 if (new_delay > dev_priv->max_delay)
392 new_delay = dev_priv->max_delay;
393 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
394 if (dev_priv->cur_delay != dev_priv->min_delay)
395 new_delay = dev_priv->cur_delay - 1;
396 if (new_delay < dev_priv->min_delay) {
397 new_delay = dev_priv->min_delay;
398 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
399 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
400 ((new_delay << 16) & 0x3f0000));
402 /* Make sure we continue to get down interrupts
403 * until we hit the minimum frequency */
404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
410 gen6_set_rps(dev, new_delay);
411 dev_priv->cur_delay = new_delay;
413 I915_WRITE(GEN6_PMIIR, pm_iir);
416 static void pch_irq_handler(struct drm_device *dev)
418 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
421 pch_iir = I915_READ(SDEIIR);
423 if (pch_iir & SDE_AUDIO_POWER_MASK)
424 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
425 (pch_iir & SDE_AUDIO_POWER_MASK) >>
426 SDE_AUDIO_POWER_SHIFT);
428 if (pch_iir & SDE_GMBUS)
429 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
431 if (pch_iir & SDE_AUDIO_HDCP_MASK)
432 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
434 if (pch_iir & SDE_AUDIO_TRANS_MASK)
435 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
437 if (pch_iir & SDE_POISON)
438 DRM_ERROR("PCH poison interrupt\n");
440 if (pch_iir & SDE_FDI_MASK) {
443 fdia = I915_READ(FDI_RXA_IIR);
444 fdib = I915_READ(FDI_RXB_IIR);
445 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
448 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
449 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
451 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
452 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
454 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
455 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
456 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
457 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
460 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
462 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
464 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
466 struct drm_i915_master_private *master_priv;
467 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
470 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
472 /* disable master interrupt before clearing iir */
473 de_ier = I915_READ(DEIER);
474 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
477 de_iir = I915_READ(DEIIR);
478 gt_iir = I915_READ(GTIIR);
479 pch_iir = I915_READ(SDEIIR);
480 pm_iir = I915_READ(GEN6_PMIIR);
482 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
483 (!IS_GEN6(dev) || pm_iir == 0))
486 if (HAS_PCH_CPT(dev))
487 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
489 hotplug_mask = SDE_HOTPLUG_MASK;
493 if (dev->primary->master) {
494 master_priv = dev->primary->master->driver_priv;
495 if (master_priv->sarea_priv)
496 master_priv->sarea_priv->last_dispatch =
497 READ_BREADCRUMB(dev_priv);
500 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
501 notify_ring(dev, &dev_priv->ring[RCS]);
502 if (gt_iir & bsd_usr_interrupt)
503 notify_ring(dev, &dev_priv->ring[VCS]);
504 if (gt_iir & GT_BLT_USER_INTERRUPT)
505 notify_ring(dev, &dev_priv->ring[BCS]);
508 intel_opregion_gse_intr(dev);
510 if (de_iir & DE_PLANEA_FLIP_DONE) {
511 intel_prepare_page_flip(dev, 0);
512 intel_finish_page_flip_plane(dev, 0);
515 if (de_iir & DE_PLANEB_FLIP_DONE) {
516 intel_prepare_page_flip(dev, 1);
517 intel_finish_page_flip_plane(dev, 1);
520 if (de_iir & DE_PIPEA_VBLANK)
521 drm_handle_vblank(dev, 0);
523 if (de_iir & DE_PIPEB_VBLANK)
524 drm_handle_vblank(dev, 1);
526 /* check event from PCH */
527 if (de_iir & DE_PCH_EVENT) {
528 if (pch_iir & hotplug_mask)
529 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
530 pch_irq_handler(dev);
533 if (de_iir & DE_PCU_EVENT) {
534 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
535 i915_handle_rps_change(dev);
539 gen6_pm_irq_handler(dev);
541 /* should clear PCH hotplug event before clear CPU irq */
542 I915_WRITE(SDEIIR, pch_iir);
543 I915_WRITE(GTIIR, gt_iir);
544 I915_WRITE(DEIIR, de_iir);
547 I915_WRITE(DEIER, de_ier);
554 * i915_error_work_func - do process context error handling work
557 * Fire an error uevent so userspace can see that a hang or error
560 static void i915_error_work_func(struct work_struct *work)
562 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
564 struct drm_device *dev = dev_priv->dev;
565 char *error_event[] = { "ERROR=1", NULL };
566 char *reset_event[] = { "RESET=1", NULL };
567 char *reset_done_event[] = { "ERROR=0", NULL };
569 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
571 if (atomic_read(&dev_priv->mm.wedged)) {
572 DRM_DEBUG_DRIVER("resetting chip\n");
573 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
574 if (!i915_reset(dev, GRDOM_RENDER)) {
575 atomic_set(&dev_priv->mm.wedged, 0);
576 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
578 complete_all(&dev_priv->error_completion);
582 #ifdef CONFIG_DEBUG_FS
583 static struct drm_i915_error_object *
584 i915_error_object_create(struct drm_i915_private *dev_priv,
585 struct drm_i915_gem_object *src)
587 struct drm_i915_error_object *dst;
588 int page, page_count;
591 if (src == NULL || src->pages == NULL)
594 page_count = src->base.size / PAGE_SIZE;
596 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
600 reloc_offset = src->gtt_offset;
601 for (page = 0; page < page_count; page++) {
606 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
610 local_irq_save(flags);
611 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
613 memcpy_fromio(d, s, PAGE_SIZE);
614 io_mapping_unmap_atomic(s);
615 local_irq_restore(flags);
617 dst->pages[page] = d;
619 reloc_offset += PAGE_SIZE;
621 dst->page_count = page_count;
622 dst->gtt_offset = src->gtt_offset;
628 kfree(dst->pages[page]);
634 i915_error_object_free(struct drm_i915_error_object *obj)
641 for (page = 0; page < obj->page_count; page++)
642 kfree(obj->pages[page]);
648 i915_error_state_free(struct drm_device *dev,
649 struct drm_i915_error_state *error)
651 i915_error_object_free(error->batchbuffer[0]);
652 i915_error_object_free(error->batchbuffer[1]);
653 i915_error_object_free(error->ringbuffer);
654 kfree(error->active_bo);
655 kfree(error->overlay);
659 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
661 struct list_head *head)
663 struct drm_i915_gem_object *obj;
666 list_for_each_entry(obj, head, mm_list) {
667 err->size = obj->base.size;
668 err->name = obj->base.name;
669 err->seqno = obj->last_rendering_seqno;
670 err->gtt_offset = obj->gtt_offset;
671 err->read_domains = obj->base.read_domains;
672 err->write_domain = obj->base.write_domain;
673 err->fence_reg = obj->fence_reg;
675 if (obj->pin_count > 0)
677 if (obj->user_pin_count > 0)
679 err->tiling = obj->tiling_mode;
680 err->dirty = obj->dirty;
681 err->purgeable = obj->madv != I915_MADV_WILLNEED;
682 err->ring = obj->ring ? obj->ring->id : 0;
683 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
694 static void i915_gem_record_fences(struct drm_device *dev,
695 struct drm_i915_error_state *error)
697 struct drm_i915_private *dev_priv = dev->dev_private;
701 switch (INTEL_INFO(dev)->gen) {
703 for (i = 0; i < 16; i++)
704 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
708 for (i = 0; i < 16; i++)
709 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
712 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
713 for (i = 0; i < 8; i++)
714 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
716 for (i = 0; i < 8; i++)
717 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
723 static struct drm_i915_error_object *
724 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
725 struct intel_ring_buffer *ring)
727 struct drm_i915_gem_object *obj;
730 if (!ring->get_seqno)
733 seqno = ring->get_seqno(ring);
734 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
735 if (obj->ring != ring)
738 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
741 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
744 /* We need to copy these to an anonymous buffer as the simplest
745 * method to avoid being overwritten by userspace.
747 return i915_error_object_create(dev_priv, obj);
754 * i915_capture_error_state - capture an error record for later analysis
757 * Should be called when an error is detected (either a hang or an error
758 * interrupt) to capture error state from the time of the error. Fills
759 * out a structure which becomes available in debugfs for user level tools
762 static void i915_capture_error_state(struct drm_device *dev)
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 struct drm_i915_gem_object *obj;
766 struct drm_i915_error_state *error;
770 spin_lock_irqsave(&dev_priv->error_lock, flags);
771 error = dev_priv->first_error;
772 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
776 error = kmalloc(sizeof(*error), GFP_ATOMIC);
778 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
782 DRM_DEBUG_DRIVER("generating error event\n");
784 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
785 error->eir = I915_READ(EIR);
786 error->pgtbl_er = I915_READ(PGTBL_ER);
787 error->pipeastat = I915_READ(PIPEASTAT);
788 error->pipebstat = I915_READ(PIPEBSTAT);
789 error->instpm = I915_READ(INSTPM);
791 if (INTEL_INFO(dev)->gen >= 6) {
792 error->error = I915_READ(ERROR_GEN6);
794 error->bcs_acthd = I915_READ(BCS_ACTHD);
795 error->bcs_ipehr = I915_READ(BCS_IPEHR);
796 error->bcs_ipeir = I915_READ(BCS_IPEIR);
797 error->bcs_instdone = I915_READ(BCS_INSTDONE);
798 error->bcs_seqno = 0;
799 if (dev_priv->ring[BCS].get_seqno)
800 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
802 error->vcs_acthd = I915_READ(VCS_ACTHD);
803 error->vcs_ipehr = I915_READ(VCS_IPEHR);
804 error->vcs_ipeir = I915_READ(VCS_IPEIR);
805 error->vcs_instdone = I915_READ(VCS_INSTDONE);
806 error->vcs_seqno = 0;
807 if (dev_priv->ring[VCS].get_seqno)
808 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
810 if (INTEL_INFO(dev)->gen >= 4) {
811 error->ipeir = I915_READ(IPEIR_I965);
812 error->ipehr = I915_READ(IPEHR_I965);
813 error->instdone = I915_READ(INSTDONE_I965);
814 error->instps = I915_READ(INSTPS);
815 error->instdone1 = I915_READ(INSTDONE1);
816 error->acthd = I915_READ(ACTHD_I965);
817 error->bbaddr = I915_READ64(BB_ADDR);
819 error->ipeir = I915_READ(IPEIR);
820 error->ipehr = I915_READ(IPEHR);
821 error->instdone = I915_READ(INSTDONE);
822 error->acthd = I915_READ(ACTHD);
825 i915_gem_record_fences(dev, error);
827 /* Record the active batchbuffers */
828 for (i = 0; i < I915_NUM_RINGS; i++)
829 error->batchbuffer[i] =
830 i915_error_first_batchbuffer(dev_priv,
833 /* Record the ringbuffer */
834 error->ringbuffer = i915_error_object_create(dev_priv,
835 dev_priv->ring[RCS].obj);
837 /* Record buffers on the active and pinned lists. */
838 error->active_bo = NULL;
839 error->pinned_bo = NULL;
842 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
844 error->active_bo_count = i;
845 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
847 error->pinned_bo_count = i - error->active_bo_count;
850 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
852 if (error->active_bo)
854 error->active_bo + error->active_bo_count;
857 if (error->active_bo)
858 error->active_bo_count =
859 capture_bo_list(error->active_bo,
860 error->active_bo_count,
861 &dev_priv->mm.active_list);
863 if (error->pinned_bo)
864 error->pinned_bo_count =
865 capture_bo_list(error->pinned_bo,
866 error->pinned_bo_count,
867 &dev_priv->mm.pinned_list);
869 do_gettimeofday(&error->time);
871 error->overlay = intel_overlay_capture_error_state(dev);
872 error->display = intel_display_capture_error_state(dev);
874 spin_lock_irqsave(&dev_priv->error_lock, flags);
875 if (dev_priv->first_error == NULL) {
876 dev_priv->first_error = error;
879 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
882 i915_error_state_free(dev, error);
885 void i915_destroy_error_state(struct drm_device *dev)
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 struct drm_i915_error_state *error;
890 spin_lock(&dev_priv->error_lock);
891 error = dev_priv->first_error;
892 dev_priv->first_error = NULL;
893 spin_unlock(&dev_priv->error_lock);
896 i915_error_state_free(dev, error);
899 #define i915_capture_error_state(x)
902 static void i915_report_and_clear_eir(struct drm_device *dev)
904 struct drm_i915_private *dev_priv = dev->dev_private;
905 u32 eir = I915_READ(EIR);
910 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
914 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
915 u32 ipeir = I915_READ(IPEIR_I965);
917 printk(KERN_ERR " IPEIR: 0x%08x\n",
918 I915_READ(IPEIR_I965));
919 printk(KERN_ERR " IPEHR: 0x%08x\n",
920 I915_READ(IPEHR_I965));
921 printk(KERN_ERR " INSTDONE: 0x%08x\n",
922 I915_READ(INSTDONE_I965));
923 printk(KERN_ERR " INSTPS: 0x%08x\n",
925 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
926 I915_READ(INSTDONE1));
927 printk(KERN_ERR " ACTHD: 0x%08x\n",
928 I915_READ(ACTHD_I965));
929 I915_WRITE(IPEIR_I965, ipeir);
930 POSTING_READ(IPEIR_I965);
932 if (eir & GM45_ERROR_PAGE_TABLE) {
933 u32 pgtbl_err = I915_READ(PGTBL_ER);
934 printk(KERN_ERR "page table error\n");
935 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
937 I915_WRITE(PGTBL_ER, pgtbl_err);
938 POSTING_READ(PGTBL_ER);
943 if (eir & I915_ERROR_PAGE_TABLE) {
944 u32 pgtbl_err = I915_READ(PGTBL_ER);
945 printk(KERN_ERR "page table error\n");
946 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
948 I915_WRITE(PGTBL_ER, pgtbl_err);
949 POSTING_READ(PGTBL_ER);
953 if (eir & I915_ERROR_MEMORY_REFRESH) {
954 u32 pipea_stats = I915_READ(PIPEASTAT);
955 u32 pipeb_stats = I915_READ(PIPEBSTAT);
957 printk(KERN_ERR "memory refresh error\n");
958 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
960 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
962 /* pipestat has already been acked */
964 if (eir & I915_ERROR_INSTRUCTION) {
965 printk(KERN_ERR "instruction error\n");
966 printk(KERN_ERR " INSTPM: 0x%08x\n",
968 if (INTEL_INFO(dev)->gen < 4) {
969 u32 ipeir = I915_READ(IPEIR);
971 printk(KERN_ERR " IPEIR: 0x%08x\n",
973 printk(KERN_ERR " IPEHR: 0x%08x\n",
975 printk(KERN_ERR " INSTDONE: 0x%08x\n",
976 I915_READ(INSTDONE));
977 printk(KERN_ERR " ACTHD: 0x%08x\n",
979 I915_WRITE(IPEIR, ipeir);
982 u32 ipeir = I915_READ(IPEIR_I965);
984 printk(KERN_ERR " IPEIR: 0x%08x\n",
985 I915_READ(IPEIR_I965));
986 printk(KERN_ERR " IPEHR: 0x%08x\n",
987 I915_READ(IPEHR_I965));
988 printk(KERN_ERR " INSTDONE: 0x%08x\n",
989 I915_READ(INSTDONE_I965));
990 printk(KERN_ERR " INSTPS: 0x%08x\n",
992 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
993 I915_READ(INSTDONE1));
994 printk(KERN_ERR " ACTHD: 0x%08x\n",
995 I915_READ(ACTHD_I965));
996 I915_WRITE(IPEIR_I965, ipeir);
997 POSTING_READ(IPEIR_I965);
1001 I915_WRITE(EIR, eir);
1003 eir = I915_READ(EIR);
1006 * some errors might have become stuck,
1009 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1010 I915_WRITE(EMR, I915_READ(EMR) | eir);
1011 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1016 * i915_handle_error - handle an error interrupt
1019 * Do some basic checking of regsiter state at error interrupt time and
1020 * dump it to the syslog. Also call i915_capture_error_state() to make
1021 * sure we get a record and make it available in debugfs. Fire a uevent
1022 * so userspace knows something bad happened (should trigger collection
1023 * of a ring dump etc.).
1025 void i915_handle_error(struct drm_device *dev, bool wedged)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1029 i915_capture_error_state(dev);
1030 i915_report_and_clear_eir(dev);
1033 INIT_COMPLETION(dev_priv->error_completion);
1034 atomic_set(&dev_priv->mm.wedged, 1);
1037 * Wakeup waiting processes so they don't hang
1039 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1041 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1043 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1046 queue_work(dev_priv->wq, &dev_priv->error_work);
1049 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1051 drm_i915_private_t *dev_priv = dev->dev_private;
1052 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054 struct drm_i915_gem_object *obj;
1055 struct intel_unpin_work *work;
1056 unsigned long flags;
1057 bool stall_detected;
1059 /* Ignore early vblank irqs */
1060 if (intel_crtc == NULL)
1063 spin_lock_irqsave(&dev->event_lock, flags);
1064 work = intel_crtc->unpin_work;
1066 if (work == NULL || work->pending || !work->enable_stall_check) {
1067 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1068 spin_unlock_irqrestore(&dev->event_lock, flags);
1072 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1073 obj = work->pending_flip_obj;
1074 if (INTEL_INFO(dev)->gen >= 4) {
1075 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
1076 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1078 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
1079 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1080 crtc->y * crtc->fb->pitch +
1081 crtc->x * crtc->fb->bits_per_pixel/8);
1084 spin_unlock_irqrestore(&dev->event_lock, flags);
1086 if (stall_detected) {
1087 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1088 intel_prepare_page_flip(dev, intel_crtc->plane);
1092 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1094 struct drm_device *dev = (struct drm_device *) arg;
1095 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1096 struct drm_i915_master_private *master_priv;
1098 u32 pipea_stats, pipeb_stats;
1101 unsigned long irqflags;
1105 atomic_inc(&dev_priv->irq_received);
1107 if (HAS_PCH_SPLIT(dev))
1108 return ironlake_irq_handler(dev);
1110 iir = I915_READ(IIR);
1112 if (INTEL_INFO(dev)->gen >= 4)
1113 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1115 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1118 irq_received = iir != 0;
1120 /* Can't rely on pipestat interrupt bit in iir as it might
1121 * have been cleared after the pipestat interrupt was received.
1122 * It doesn't set the bit in iir again, but it still produces
1123 * interrupts (for non-MSI).
1125 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1126 pipea_stats = I915_READ(PIPEASTAT);
1127 pipeb_stats = I915_READ(PIPEBSTAT);
1129 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1130 i915_handle_error(dev, false);
1133 * Clear the PIPE(A|B)STAT regs before the IIR
1135 if (pipea_stats & 0x8000ffff) {
1136 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
1137 DRM_DEBUG_DRIVER("pipe a underrun\n");
1138 I915_WRITE(PIPEASTAT, pipea_stats);
1142 if (pipeb_stats & 0x8000ffff) {
1143 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
1144 DRM_DEBUG_DRIVER("pipe b underrun\n");
1145 I915_WRITE(PIPEBSTAT, pipeb_stats);
1148 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1155 /* Consume port. Then clear IIR or we'll miss events */
1156 if ((I915_HAS_HOTPLUG(dev)) &&
1157 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1158 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1160 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1162 if (hotplug_status & dev_priv->hotplug_supported_mask)
1163 queue_work(dev_priv->wq,
1164 &dev_priv->hotplug_work);
1166 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1167 I915_READ(PORT_HOTPLUG_STAT);
1170 I915_WRITE(IIR, iir);
1171 new_iir = I915_READ(IIR); /* Flush posted writes */
1173 if (dev->primary->master) {
1174 master_priv = dev->primary->master->driver_priv;
1175 if (master_priv->sarea_priv)
1176 master_priv->sarea_priv->last_dispatch =
1177 READ_BREADCRUMB(dev_priv);
1180 if (iir & I915_USER_INTERRUPT)
1181 notify_ring(dev, &dev_priv->ring[RCS]);
1182 if (iir & I915_BSD_USER_INTERRUPT)
1183 notify_ring(dev, &dev_priv->ring[VCS]);
1185 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1186 intel_prepare_page_flip(dev, 0);
1187 if (dev_priv->flip_pending_is_done)
1188 intel_finish_page_flip_plane(dev, 0);
1191 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1192 intel_prepare_page_flip(dev, 1);
1193 if (dev_priv->flip_pending_is_done)
1194 intel_finish_page_flip_plane(dev, 1);
1197 if (pipea_stats & vblank_status) {
1199 drm_handle_vblank(dev, 0);
1200 if (!dev_priv->flip_pending_is_done) {
1201 i915_pageflip_stall_check(dev, 0);
1202 intel_finish_page_flip(dev, 0);
1206 if (pipeb_stats & vblank_status) {
1208 drm_handle_vblank(dev, 1);
1209 if (!dev_priv->flip_pending_is_done) {
1210 i915_pageflip_stall_check(dev, 1);
1211 intel_finish_page_flip(dev, 1);
1215 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1216 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1217 (iir & I915_ASLE_INTERRUPT))
1218 intel_opregion_asle_intr(dev);
1220 /* With MSI, interrupts are only generated when iir
1221 * transitions from zero to nonzero. If another bit got
1222 * set while we were handling the existing iir bits, then
1223 * we would never get another interrupt.
1225 * This is fine on non-MSI as well, as if we hit this path
1226 * we avoid exiting the interrupt handler only to generate
1229 * Note that for MSI this could cause a stray interrupt report
1230 * if an interrupt landed in the time between writing IIR and
1231 * the posting read. This should be rare enough to never
1232 * trigger the 99% of 100,000 interrupts test for disabling
1241 static int i915_emit_irq(struct drm_device * dev)
1243 drm_i915_private_t *dev_priv = dev->dev_private;
1244 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1246 i915_kernel_lost_context(dev);
1248 DRM_DEBUG_DRIVER("\n");
1250 dev_priv->counter++;
1251 if (dev_priv->counter > 0x7FFFFFFFUL)
1252 dev_priv->counter = 1;
1253 if (master_priv->sarea_priv)
1254 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1256 if (BEGIN_LP_RING(4) == 0) {
1257 OUT_RING(MI_STORE_DWORD_INDEX);
1258 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1259 OUT_RING(dev_priv->counter);
1260 OUT_RING(MI_USER_INTERRUPT);
1264 return dev_priv->counter;
1267 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1269 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1270 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1272 if (dev_priv->trace_irq_seqno == 0 &&
1273 ring->irq_get(ring))
1274 dev_priv->trace_irq_seqno = seqno;
1277 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1279 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1280 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1282 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1284 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1285 READ_BREADCRUMB(dev_priv));
1287 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1288 if (master_priv->sarea_priv)
1289 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1293 if (master_priv->sarea_priv)
1294 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1296 if (ring->irq_get(ring)) {
1297 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1298 READ_BREADCRUMB(dev_priv) >= irq_nr);
1299 ring->irq_put(ring);
1300 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1303 if (ret == -EBUSY) {
1304 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1305 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1311 /* Needs the lock as it touches the ring.
1313 int i915_irq_emit(struct drm_device *dev, void *data,
1314 struct drm_file *file_priv)
1316 drm_i915_private_t *dev_priv = dev->dev_private;
1317 drm_i915_irq_emit_t *emit = data;
1320 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1321 DRM_ERROR("called with no initialization\n");
1325 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1327 mutex_lock(&dev->struct_mutex);
1328 result = i915_emit_irq(dev);
1329 mutex_unlock(&dev->struct_mutex);
1331 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1332 DRM_ERROR("copy_to_user\n");
1339 /* Doesn't need the hardware lock.
1341 int i915_irq_wait(struct drm_device *dev, void *data,
1342 struct drm_file *file_priv)
1344 drm_i915_private_t *dev_priv = dev->dev_private;
1345 drm_i915_irq_wait_t *irqwait = data;
1348 DRM_ERROR("called with no initialization\n");
1352 return i915_wait_irq(dev, irqwait->irq_seq);
1355 /* Called from drm generic code, passed 'crtc' which
1356 * we use as a pipe index
1358 int i915_enable_vblank(struct drm_device *dev, int pipe)
1360 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1361 unsigned long irqflags;
1363 if (!i915_pipe_enabled(dev, pipe))
1366 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1367 if (HAS_PCH_SPLIT(dev))
1368 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1369 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1370 else if (INTEL_INFO(dev)->gen >= 4)
1371 i915_enable_pipestat(dev_priv, pipe,
1372 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1374 i915_enable_pipestat(dev_priv, pipe,
1375 PIPE_VBLANK_INTERRUPT_ENABLE);
1376 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1380 /* Called from drm generic code, passed 'crtc' which
1381 * we use as a pipe index
1383 void i915_disable_vblank(struct drm_device *dev, int pipe)
1385 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1386 unsigned long irqflags;
1388 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1389 if (HAS_PCH_SPLIT(dev))
1390 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1391 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1393 i915_disable_pipestat(dev_priv, pipe,
1394 PIPE_VBLANK_INTERRUPT_ENABLE |
1395 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1396 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1399 void i915_enable_interrupt (struct drm_device *dev)
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1403 if (!HAS_PCH_SPLIT(dev))
1404 intel_opregion_enable_asle(dev);
1405 dev_priv->irq_enabled = 1;
1409 /* Set the vblank monitor pipe
1411 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1412 struct drm_file *file_priv)
1414 drm_i915_private_t *dev_priv = dev->dev_private;
1417 DRM_ERROR("called with no initialization\n");
1424 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1425 struct drm_file *file_priv)
1427 drm_i915_private_t *dev_priv = dev->dev_private;
1428 drm_i915_vblank_pipe_t *pipe = data;
1431 DRM_ERROR("called with no initialization\n");
1435 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1441 * Schedule buffer swap at given vertical blank.
1443 int i915_vblank_swap(struct drm_device *dev, void *data,
1444 struct drm_file *file_priv)
1446 /* The delayed swap mechanism was fundamentally racy, and has been
1447 * removed. The model was that the client requested a delayed flip/swap
1448 * from the kernel, then waited for vblank before continuing to perform
1449 * rendering. The problem was that the kernel might wake the client
1450 * up before it dispatched the vblank swap (since the lock has to be
1451 * held while touching the ringbuffer), in which case the client would
1452 * clear and start the next frame before the swap occurred, and
1453 * flicker would occur in addition to likely missing the vblank.
1455 * In the absence of this ioctl, userland falls back to a correct path
1456 * of waiting for a vblank, then dispatching the swap on its own.
1457 * Context switching to userland and back is plenty fast enough for
1458 * meeting the requirements of vblank swapping.
1464 ring_last_seqno(struct intel_ring_buffer *ring)
1466 return list_entry(ring->request_list.prev,
1467 struct drm_i915_gem_request, list)->seqno;
1470 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1472 if (list_empty(&ring->request_list) ||
1473 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1474 /* Issue a wake-up to catch stuck h/w. */
1475 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1476 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1478 ring->waiting_seqno,
1479 ring->get_seqno(ring));
1480 wake_up_all(&ring->irq_queue);
1488 static bool kick_ring(struct intel_ring_buffer *ring)
1490 struct drm_device *dev = ring->dev;
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 u32 tmp = I915_READ_CTL(ring);
1493 if (tmp & RING_WAIT) {
1494 DRM_ERROR("Kicking stuck wait on %s\n",
1496 I915_WRITE_CTL(ring, tmp);
1500 (tmp & RING_WAIT_SEMAPHORE)) {
1501 DRM_ERROR("Kicking stuck semaphore on %s\n",
1503 I915_WRITE_CTL(ring, tmp);
1510 * This is called when the chip hasn't reported back with completed
1511 * batchbuffers in a long time. The first time this is called we simply record
1512 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1513 * again, we assume the chip is wedged and try to fix it.
1515 void i915_hangcheck_elapsed(unsigned long data)
1517 struct drm_device *dev = (struct drm_device *)data;
1518 drm_i915_private_t *dev_priv = dev->dev_private;
1519 uint32_t acthd, instdone, instdone1;
1522 /* If all work is done then ACTHD clearly hasn't advanced. */
1523 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1524 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1525 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1526 dev_priv->hangcheck_count = 0;
1532 if (INTEL_INFO(dev)->gen < 4) {
1533 acthd = I915_READ(ACTHD);
1534 instdone = I915_READ(INSTDONE);
1537 acthd = I915_READ(ACTHD_I965);
1538 instdone = I915_READ(INSTDONE_I965);
1539 instdone1 = I915_READ(INSTDONE1);
1542 if (dev_priv->last_acthd == acthd &&
1543 dev_priv->last_instdone == instdone &&
1544 dev_priv->last_instdone1 == instdone1) {
1545 if (dev_priv->hangcheck_count++ > 1) {
1546 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1548 if (!IS_GEN2(dev)) {
1549 /* Is the chip hanging on a WAIT_FOR_EVENT?
1550 * If so we can simply poke the RB_WAIT bit
1551 * and break the hang. This should work on
1552 * all but the second generation chipsets.
1555 if (kick_ring(&dev_priv->ring[RCS]))
1559 kick_ring(&dev_priv->ring[VCS]))
1563 kick_ring(&dev_priv->ring[BCS]))
1567 i915_handle_error(dev, true);
1571 dev_priv->hangcheck_count = 0;
1573 dev_priv->last_acthd = acthd;
1574 dev_priv->last_instdone = instdone;
1575 dev_priv->last_instdone1 = instdone1;
1579 /* Reset timer case chip hangs without another request being added */
1580 mod_timer(&dev_priv->hangcheck_timer,
1581 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1586 static void ironlake_irq_preinstall(struct drm_device *dev)
1588 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1590 I915_WRITE(HWSTAM, 0xeffe);
1592 /* XXX hotplug from PCH */
1594 I915_WRITE(DEIMR, 0xffffffff);
1595 I915_WRITE(DEIER, 0x0);
1596 POSTING_READ(DEIER);
1599 I915_WRITE(GTIMR, 0xffffffff);
1600 I915_WRITE(GTIER, 0x0);
1601 POSTING_READ(GTIER);
1603 /* south display irq */
1604 I915_WRITE(SDEIMR, 0xffffffff);
1605 I915_WRITE(SDEIER, 0x0);
1606 POSTING_READ(SDEIER);
1609 static int ironlake_irq_postinstall(struct drm_device *dev)
1611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1612 /* enable kind of interrupts always enabled */
1613 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1614 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1618 dev_priv->irq_mask = ~display_mask;
1620 /* should always can generate irq */
1621 I915_WRITE(DEIIR, I915_READ(DEIIR));
1622 I915_WRITE(DEIMR, dev_priv->irq_mask);
1623 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1624 POSTING_READ(DEIER);
1626 dev_priv->gt_irq_mask = ~0;
1628 I915_WRITE(GTIIR, I915_READ(GTIIR));
1629 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1634 GT_GEN6_BSD_USER_INTERRUPT |
1635 GT_BLT_USER_INTERRUPT;
1640 GT_BSD_USER_INTERRUPT;
1641 I915_WRITE(GTIER, render_irqs);
1642 POSTING_READ(GTIER);
1644 if (HAS_PCH_CPT(dev)) {
1645 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT |
1646 SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1648 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1649 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1650 hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
1651 I915_WRITE(FDI_RXA_IMR, 0);
1652 I915_WRITE(FDI_RXB_IMR, 0);
1655 dev_priv->pch_irq_mask = ~hotplug_mask;
1657 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1658 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1659 I915_WRITE(SDEIER, hotplug_mask);
1660 POSTING_READ(SDEIER);
1662 if (IS_IRONLAKE_M(dev)) {
1663 /* Clear & enable PCU event interrupts */
1664 I915_WRITE(DEIIR, DE_PCU_EVENT);
1665 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1666 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1672 void i915_driver_irq_preinstall(struct drm_device * dev)
1674 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1676 atomic_set(&dev_priv->irq_received, 0);
1678 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1679 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1681 if (HAS_PCH_SPLIT(dev)) {
1682 ironlake_irq_preinstall(dev);
1686 if (I915_HAS_HOTPLUG(dev)) {
1687 I915_WRITE(PORT_HOTPLUG_EN, 0);
1688 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1691 I915_WRITE(HWSTAM, 0xeffe);
1692 I915_WRITE(PIPEASTAT, 0);
1693 I915_WRITE(PIPEBSTAT, 0);
1694 I915_WRITE(IMR, 0xffffffff);
1695 I915_WRITE(IER, 0x0);
1700 * Must be called after intel_modeset_init or hotplug interrupts won't be
1701 * enabled correctly.
1703 int i915_driver_irq_postinstall(struct drm_device *dev)
1705 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1706 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1709 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1711 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1713 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1715 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1717 if (HAS_PCH_SPLIT(dev))
1718 return ironlake_irq_postinstall(dev);
1720 /* Unmask the interrupts that we always want on. */
1721 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1723 dev_priv->pipestat[0] = 0;
1724 dev_priv->pipestat[1] = 0;
1726 if (I915_HAS_HOTPLUG(dev)) {
1727 /* Enable in IER... */
1728 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1729 /* and unmask in IMR */
1730 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1734 * Enable some error detection, note the instruction error mask
1735 * bit is reserved, so we leave it masked.
1738 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1739 GM45_ERROR_MEM_PRIV |
1740 GM45_ERROR_CP_PRIV |
1741 I915_ERROR_MEMORY_REFRESH);
1743 error_mask = ~(I915_ERROR_PAGE_TABLE |
1744 I915_ERROR_MEMORY_REFRESH);
1746 I915_WRITE(EMR, error_mask);
1748 I915_WRITE(IMR, dev_priv->irq_mask);
1749 I915_WRITE(IER, enable_mask);
1752 if (I915_HAS_HOTPLUG(dev)) {
1753 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1755 /* Note HDMI and DP share bits */
1756 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1757 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1758 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1759 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1760 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1761 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1762 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1763 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1764 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1765 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1766 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1767 hotplug_en |= CRT_HOTPLUG_INT_EN;
1769 /* Programming the CRT detection parameters tends
1770 to generate a spurious hotplug event about three
1771 seconds later. So just do it once.
1774 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1775 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1778 /* Ignore TV since it's buggy */
1780 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1783 intel_opregion_enable_asle(dev);
1788 static void ironlake_irq_uninstall(struct drm_device *dev)
1790 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1791 I915_WRITE(HWSTAM, 0xffffffff);
1793 I915_WRITE(DEIMR, 0xffffffff);
1794 I915_WRITE(DEIER, 0x0);
1795 I915_WRITE(DEIIR, I915_READ(DEIIR));
1797 I915_WRITE(GTIMR, 0xffffffff);
1798 I915_WRITE(GTIER, 0x0);
1799 I915_WRITE(GTIIR, I915_READ(GTIIR));
1802 void i915_driver_irq_uninstall(struct drm_device * dev)
1804 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1809 dev_priv->vblank_pipe = 0;
1811 if (HAS_PCH_SPLIT(dev)) {
1812 ironlake_irq_uninstall(dev);
1816 if (I915_HAS_HOTPLUG(dev)) {
1817 I915_WRITE(PORT_HOTPLUG_EN, 0);
1818 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1821 I915_WRITE(HWSTAM, 0xffffffff);
1822 I915_WRITE(PIPEASTAT, 0);
1823 I915_WRITE(PIPEBSTAT, 0);
1824 I915_WRITE(IMR, 0xffffffff);
1825 I915_WRITE(IER, 0x0);
1827 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1828 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1829 I915_WRITE(IIR, I915_READ(IIR));