drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 static void i915_handle_rps_change(struct drm_device *dev)
 300 {
 301         drm_i915_private_t *dev_priv = dev->dev_private;
 302         u32 busy_up, busy_down, max_avg, min_avg;
 303         u8 new_delay = dev_priv->cur_delay;
 304
 305         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 306         busy_up = I915_READ(RCPREVBSYTUPAVG);
 307         busy_down = I915_READ(RCPREVBSYTDNAVG);
 308         max_avg = I915_READ(RCBMAXAVG);
 309         min_avg = I915_READ(RCBMINAVG);
 310
 311         /* Handle RCS change request from hw */
 312         if (busy_up > max_avg) {
 313                 if (dev_priv->cur_delay != dev_priv->max_delay)
 314                         new_delay = dev_priv->cur_delay - 1;
 315                 if (new_delay < dev_priv->max_delay)
 316                         new_delay = dev_priv->max_delay;
 317         } else if (busy_down < min_avg) {
 318                 if (dev_priv->cur_delay != dev_priv->min_delay)
 319                         new_delay = dev_priv->cur_delay + 1;
 320                 if (new_delay > dev_priv->min_delay)
 321                         new_delay = dev_priv->min_delay;
 322         }
 323
 324         if (ironlake_set_drps(dev, new_delay))
 325                 dev_priv->cur_delay = new_delay;
 326
 327         return;
 328 }
 329
 330 static void notify_ring(struct drm_device *dev,
 331                         struct intel_ring_buffer *ring)
 332 {
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334
 335         if (ring->obj == NULL)
 336                 return;
 337
 338         trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
 339
 340         wake_up_all(&ring->irq_queue);
 341         if (i915_enable_hangcheck) {
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer,
 344                           jiffies +
 345                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 346         }
 347 }
 348
 349 static void gen6_pm_rps_work(struct work_struct *work)
 350 {
 351         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 352                                                     rps_work);
 353         u32 pm_iir, pm_imr;
 354         u8 new_delay;
 355
 356         spin_lock_irq(&dev_priv->rps_lock);
 357         pm_iir = dev_priv->pm_iir;
 358         dev_priv->pm_iir = 0;
 359         pm_imr = I915_READ(GEN6_PMIMR);
 360         I915_WRITE(GEN6_PMIMR, 0);
 361         spin_unlock_irq(&dev_priv->rps_lock);
 362
 363         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 364                 return;
 365
 366         mutex_lock(&dev_priv->dev->struct_mutex);
 367
 368         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 369                 new_delay = dev_priv->cur_delay + 1;
 370         else
 371                 new_delay = dev_priv->cur_delay - 1;
 372
 373         gen6_set_rps(dev_priv->dev, new_delay);
 374
 375         mutex_unlock(&dev_priv->dev->struct_mutex);
 376 }
 377
 378
 379 /**
 380  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 381  * occurred.
 382  * @work: workqueue struct
 383  *
 384  * Doesn't actually do anything except notify userspace. As a consequence of
 385  * this event, userspace should try to remap the bad rows since statistically
 386  * it is likely the same row is more likely to go bad again.
 387  */
 388 static void ivybridge_parity_work(struct work_struct *work)
 389 {
 390         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 391                                                     parity_error_work);
 392         u32 error_status, row, bank, subbank;
 393         char *parity_event[5];
 394         uint32_t misccpctl;
 395         unsigned long flags;
 396
 397         /* We must turn off DOP level clock gating to access the L3 registers.
 398          * In order to prevent a get/put style interface, acquire struct mutex
 399          * any time we access those registers.
 400          */
 401         mutex_lock(&dev_priv->dev->struct_mutex);
 402
 403         misccpctl = I915_READ(GEN7_MISCCPCTL);
 404         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 405         POSTING_READ(GEN7_MISCCPCTL);
 406
 407         error_status = I915_READ(GEN7_L3CDERRST1);
 408         row = GEN7_PARITY_ERROR_ROW(error_status);
 409         bank = GEN7_PARITY_ERROR_BANK(error_status);
 410         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 411
 412         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 413                                     GEN7_L3CDERRST1_ENABLE);
 414         POSTING_READ(GEN7_L3CDERRST1);
 415
 416         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 417
 418         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 419         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 420         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 421         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 422
 423         mutex_unlock(&dev_priv->dev->struct_mutex);
 424
 425         parity_event[0] = "L3_PARITY_ERROR=1";
 426         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 427         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 428         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 429         parity_event[4] = NULL;
 430
 431         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 432                            KOBJ_CHANGE, parity_event);
 433
 434         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 435                   row, bank, subbank);
 436
 437         kfree(parity_event[3]);
 438         kfree(parity_event[2]);
 439         kfree(parity_event[1]);
 440 }
 441
 442 static void ivybridge_handle_parity_error(struct drm_device *dev)
 443 {
 444         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 445         unsigned long flags;
 446
 447         if (!IS_IVYBRIDGE(dev))
 448                 return;
 449
 450         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 451         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 452         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 453         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 454
 455         queue_work(dev_priv->wq, &dev_priv->parity_error_work);
 456 }
 457
 458 static void snb_gt_irq_handler(struct drm_device *dev,
 459                                struct drm_i915_private *dev_priv,
 460                                u32 gt_iir)
 461 {
 462
 463         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 464                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 465                 notify_ring(dev, &dev_priv->ring[RCS]);
 466         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 467                 notify_ring(dev, &dev_priv->ring[VCS]);
 468         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 469                 notify_ring(dev, &dev_priv->ring[BCS]);
 470
 471         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 472                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 473                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 474                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 475                 i915_handle_error(dev, false);
 476         }
 477
 478         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 479                 ivybridge_handle_parity_error(dev);
 480 }
 481
 482 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 483                                 u32 pm_iir)
 484 {
 485         unsigned long flags;
 486
 487         /*
 488          * IIR bits should never already be set because IMR should
 489          * prevent an interrupt from being shown in IIR. The warning
 490          * displays a case where we've unsafely cleared
 491          * dev_priv->pm_iir. Although missing an interrupt of the same
 492          * type is not a problem, it displays a problem in the logic.
 493          *
 494          * The mask bit in IMR is cleared by rps_work.
 495          */
 496
 497         spin_lock_irqsave(&dev_priv->rps_lock, flags);
 498         WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 499         dev_priv->pm_iir |= pm_iir;
 500         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 501         POSTING_READ(GEN6_PMIMR);
 502         spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 503
 504         queue_work(dev_priv->wq, &dev_priv->rps_work);
 505 }
 506
 507 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 508 {
 509         struct drm_device *dev = (struct drm_device *) arg;
 510         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 511         u32 iir, gt_iir, pm_iir;
 512         irqreturn_t ret = IRQ_NONE;
 513         unsigned long irqflags;
 514         int pipe;
 515         u32 pipe_stats[I915_MAX_PIPES];
 516         u32 vblank_status;
 517         int vblank = 0;
 518         bool blc_event;
 519
 520         atomic_inc(&dev_priv->irq_received);
 521
 522         vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
 523                 PIPE_VBLANK_INTERRUPT_STATUS;
 524
 525         while (true) {
 526                 iir = I915_READ(VLV_IIR);
 527                 gt_iir = I915_READ(GTIIR);
 528                 pm_iir = I915_READ(GEN6_PMIIR);
 529
 530                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 531                         goto out;
 532
 533                 ret = IRQ_HANDLED;
 534
 535                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 536
 537                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 538                 for_each_pipe(pipe) {
 539                         int reg = PIPESTAT(pipe);
 540                         pipe_stats[pipe] = I915_READ(reg);
 541
 542                         /*
 543                          * Clear the PIPE*STAT regs before the IIR
 544                          */
 545                         if (pipe_stats[pipe] & 0x8000ffff) {
 546                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 547                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 548                                                          pipe_name(pipe));
 549                                 I915_WRITE(reg, pipe_stats[pipe]);
 550                         }
 551                 }
 552                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 553
 554                 /* Consume port.  Then clear IIR or we'll miss events */
 555                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 556                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 557
 558                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 559                                          hotplug_status);
 560                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 561                                 queue_work(dev_priv->wq,
 562                                            &dev_priv->hotplug_work);
 563
 564                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 565                         I915_READ(PORT_HOTPLUG_STAT);
 566                 }
 567
 568
 569                 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
 570                         drm_handle_vblank(dev, 0);
 571                         vblank++;
 572                         intel_finish_page_flip(dev, 0);
 573                 }
 574
 575                 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
 576                         drm_handle_vblank(dev, 1);
 577                         vblank++;
 578                         intel_finish_page_flip(dev, 0);
 579                 }
 580
 581                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 582                         blc_event = true;
 583
 584                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 585                         gen6_queue_rps_work(dev_priv, pm_iir);
 586
 587                 I915_WRITE(GTIIR, gt_iir);
 588                 I915_WRITE(GEN6_PMIIR, pm_iir);
 589                 I915_WRITE(VLV_IIR, iir);
 590         }
 591
 592 out:
 593         return ret;
 594 }
 595
 596 static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
 597 {
 598         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 599         int pipe;
 600
 601         if (pch_iir & SDE_AUDIO_POWER_MASK)
 602                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 603                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 604                                  SDE_AUDIO_POWER_SHIFT);
 605
 606         if (pch_iir & SDE_GMBUS)
 607                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 608
 609         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 610                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 611
 612         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 613                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 614
 615         if (pch_iir & SDE_POISON)
 616                 DRM_ERROR("PCH poison interrupt\n");
 617
 618         if (pch_iir & SDE_FDI_MASK)
 619                 for_each_pipe(pipe)
 620                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 621                                          pipe_name(pipe),
 622                                          I915_READ(FDI_RX_IIR(pipe)));
 623
 624         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 625                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 626
 627         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 628                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 629
 630         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 631                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 632         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 633                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 634 }
 635
 636 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 637 {
 638         struct drm_device *dev = (struct drm_device *) arg;
 639         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 640         u32 de_iir, gt_iir, de_ier, pm_iir;
 641         irqreturn_t ret = IRQ_NONE;
 642         int i;
 643
 644         atomic_inc(&dev_priv->irq_received);
 645
 646         /* disable master interrupt before clearing iir  */
 647         de_ier = I915_READ(DEIER);
 648         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 649
 650         gt_iir = I915_READ(GTIIR);
 651         if (gt_iir) {
 652                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 653                 I915_WRITE(GTIIR, gt_iir);
 654                 ret = IRQ_HANDLED;
 655         }
 656
 657         de_iir = I915_READ(DEIIR);
 658         if (de_iir) {
 659                 if (de_iir & DE_GSE_IVB)
 660                         intel_opregion_gse_intr(dev);
 661
 662                 for (i = 0; i < 3; i++) {
 663                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 664                                 intel_prepare_page_flip(dev, i);
 665                                 intel_finish_page_flip_plane(dev, i);
 666                         }
 667                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 668                                 drm_handle_vblank(dev, i);
 669                 }
 670
 671                 /* check event from PCH */
 672                 if (de_iir & DE_PCH_EVENT_IVB) {
 673                         u32 pch_iir = I915_READ(SDEIIR);
 674
 675                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 676                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 677                         pch_irq_handler(dev, pch_iir);
 678
 679                         /* clear PCH hotplug event before clear CPU irq */
 680                         I915_WRITE(SDEIIR, pch_iir);
 681                 }
 682
 683                 I915_WRITE(DEIIR, de_iir);
 684                 ret = IRQ_HANDLED;
 685         }
 686
 687         pm_iir = I915_READ(GEN6_PMIIR);
 688         if (pm_iir) {
 689                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 690                         gen6_queue_rps_work(dev_priv, pm_iir);
 691                 I915_WRITE(GEN6_PMIIR, pm_iir);
 692                 ret = IRQ_HANDLED;
 693         }
 694
 695         I915_WRITE(DEIER, de_ier);
 696         POSTING_READ(DEIER);
 697
 698         return ret;
 699 }
 700
 701 static void ilk_gt_irq_handler(struct drm_device *dev,
 702                                struct drm_i915_private *dev_priv,
 703                                u32 gt_iir)
 704 {
 705         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 706                 notify_ring(dev, &dev_priv->ring[RCS]);
 707         if (gt_iir & GT_BSD_USER_INTERRUPT)
 708                 notify_ring(dev, &dev_priv->ring[VCS]);
 709 }
 710
 711 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 712 {
 713         struct drm_device *dev = (struct drm_device *) arg;
 714         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 715         int ret = IRQ_NONE;
 716         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 717         u32 hotplug_mask;
 718
 719         atomic_inc(&dev_priv->irq_received);
 720
 721         /* disable master interrupt before clearing iir  */
 722         de_ier = I915_READ(DEIER);
 723         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 724         POSTING_READ(DEIER);
 725
 726         de_iir = I915_READ(DEIIR);
 727         gt_iir = I915_READ(GTIIR);
 728         pch_iir = I915_READ(SDEIIR);
 729         pm_iir = I915_READ(GEN6_PMIIR);
 730
 731         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 732             (!IS_GEN6(dev) || pm_iir == 0))
 733                 goto done;
 734
 735         if (HAS_PCH_CPT(dev))
 736                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 737         else
 738                 hotplug_mask = SDE_HOTPLUG_MASK;
 739
 740         ret = IRQ_HANDLED;
 741
 742         if (IS_GEN5(dev))
 743                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 744         else
 745                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 746
 747         if (de_iir & DE_GSE)
 748                 intel_opregion_gse_intr(dev);
 749
 750         if (de_iir & DE_PLANEA_FLIP_DONE) {
 751                 intel_prepare_page_flip(dev, 0);
 752                 intel_finish_page_flip_plane(dev, 0);
 753         }
 754
 755         if (de_iir & DE_PLANEB_FLIP_DONE) {
 756                 intel_prepare_page_flip(dev, 1);
 757                 intel_finish_page_flip_plane(dev, 1);
 758         }
 759
 760         if (de_iir & DE_PIPEA_VBLANK)
 761                 drm_handle_vblank(dev, 0);
 762
 763         if (de_iir & DE_PIPEB_VBLANK)
 764                 drm_handle_vblank(dev, 1);
 765
 766         /* check event from PCH */
 767         if (de_iir & DE_PCH_EVENT) {
 768                 if (pch_iir & hotplug_mask)
 769                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 770                 pch_irq_handler(dev, pch_iir);
 771         }
 772
 773         if (de_iir & DE_PCU_EVENT) {
 774                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 775                 i915_handle_rps_change(dev);
 776         }
 777
 778         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 779                 gen6_queue_rps_work(dev_priv, pm_iir);
 780
 781         /* should clear PCH hotplug event before clear CPU irq */
 782         I915_WRITE(SDEIIR, pch_iir);
 783         I915_WRITE(GTIIR, gt_iir);
 784         I915_WRITE(DEIIR, de_iir);
 785         I915_WRITE(GEN6_PMIIR, pm_iir);
 786
 787 done:
 788         I915_WRITE(DEIER, de_ier);
 789         POSTING_READ(DEIER);
 790
 791         return ret;
 792 }
 793
 794 /**
 795  * i915_error_work_func - do process context error handling work
 796  * @work: work struct
 797  *
 798  * Fire an error uevent so userspace can see that a hang or error
 799  * was detected.
 800  */
 801 static void i915_error_work_func(struct work_struct *work)
 802 {
 803         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 804                                                     error_work);
 805         struct drm_device *dev = dev_priv->dev;
 806         char *error_event[] = { "ERROR=1", NULL };
 807         char *reset_event[] = { "RESET=1", NULL };
 808         char *reset_done_event[] = { "ERROR=0", NULL };
 809
 810         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 811
 812         if (atomic_read(&dev_priv->mm.wedged)) {
 813                 DRM_DEBUG_DRIVER("resetting chip\n");
 814                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 815                 if (!i915_reset(dev)) {
 816                         atomic_set(&dev_priv->mm.wedged, 0);
 817                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 818                 }
 819                 complete_all(&dev_priv->error_completion);
 820         }
 821 }
 822
 823 #ifdef CONFIG_DEBUG_FS
 824 static struct drm_i915_error_object *
 825 i915_error_object_create(struct drm_i915_private *dev_priv,
 826                          struct drm_i915_gem_object *src)
 827 {
 828         struct drm_i915_error_object *dst;
 829         int page, page_count;
 830         u32 reloc_offset;
 831
 832         if (src == NULL || src->pages == NULL)
 833                 return NULL;
 834
 835         page_count = src->base.size / PAGE_SIZE;
 836
 837         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 838         if (dst == NULL)
 839                 return NULL;
 840
 841         reloc_offset = src->gtt_offset;
 842         for (page = 0; page < page_count; page++) {
 843                 unsigned long flags;
 844                 void *d;
 845
 846                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 847                 if (d == NULL)
 848                         goto unwind;
 849
 850                 local_irq_save(flags);
 851                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 852                     src->has_global_gtt_mapping) {
 853                         void __iomem *s;
 854
 855                         /* Simply ignore tiling or any overlapping fence.
 856                          * It's part of the error state, and this hopefully
 857                          * captures what the GPU read.
 858                          */
 859
 860                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 861                                                      reloc_offset);
 862                         memcpy_fromio(d, s, PAGE_SIZE);
 863                         io_mapping_unmap_atomic(s);
 864                 } else {
 865                         void *s;
 866
 867                         drm_clflush_pages(&src->pages[page], 1);
 868
 869                         s = kmap_atomic(src->pages[page]);
 870                         memcpy(d, s, PAGE_SIZE);
 871                         kunmap_atomic(s);
 872
 873                         drm_clflush_pages(&src->pages[page], 1);
 874                 }
 875                 local_irq_restore(flags);
 876
 877                 dst->pages[page] = d;
 878
 879                 reloc_offset += PAGE_SIZE;
 880         }
 881         dst->page_count = page_count;
 882         dst->gtt_offset = src->gtt_offset;
 883
 884         return dst;
 885
 886 unwind:
 887         while (page--)
 888                 kfree(dst->pages[page]);
 889         kfree(dst);
 890         return NULL;
 891 }
 892
 893 static void
 894 i915_error_object_free(struct drm_i915_error_object *obj)
 895 {
 896         int page;
 897
 898         if (obj == NULL)
 899                 return;
 900
 901         for (page = 0; page < obj->page_count; page++)
 902                 kfree(obj->pages[page]);
 903
 904         kfree(obj);
 905 }
 906
 907 void
 908 i915_error_state_free(struct kref *error_ref)
 909 {
 910         struct drm_i915_error_state *error = container_of(error_ref,
 911                                                           typeof(*error), ref);
 912         int i;
 913
 914         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 915                 i915_error_object_free(error->ring[i].batchbuffer);
 916                 i915_error_object_free(error->ring[i].ringbuffer);
 917                 kfree(error->ring[i].requests);
 918         }
 919
 920         kfree(error->active_bo);
 921         kfree(error->overlay);
 922         kfree(error);
 923 }
 924 static void capture_bo(struct drm_i915_error_buffer *err,
 925                        struct drm_i915_gem_object *obj)
 926 {
 927         err->size = obj->base.size;
 928         err->name = obj->base.name;
 929         err->seqno = obj->last_rendering_seqno;
 930         err->gtt_offset = obj->gtt_offset;
 931         err->read_domains = obj->base.read_domains;
 932         err->write_domain = obj->base.write_domain;
 933         err->fence_reg = obj->fence_reg;
 934         err->pinned = 0;
 935         if (obj->pin_count > 0)
 936                 err->pinned = 1;
 937         if (obj->user_pin_count > 0)
 938                 err->pinned = -1;
 939         err->tiling = obj->tiling_mode;
 940         err->dirty = obj->dirty;
 941         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 942         err->ring = obj->ring ? obj->ring->id : -1;
 943         err->cache_level = obj->cache_level;
 944 }
 945
 946 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 947                              int count, struct list_head *head)
 948 {
 949         struct drm_i915_gem_object *obj;
 950         int i = 0;
 951
 952         list_for_each_entry(obj, head, mm_list) {
 953                 capture_bo(err++, obj);
 954                 if (++i == count)
 955                         break;
 956         }
 957
 958         return i;
 959 }
 960
 961 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 962                              int count, struct list_head *head)
 963 {
 964         struct drm_i915_gem_object *obj;
 965         int i = 0;
 966
 967         list_for_each_entry(obj, head, gtt_list) {
 968                 if (obj->pin_count == 0)
 969                         continue;
 970
 971                 capture_bo(err++, obj);
 972                 if (++i == count)
 973                         break;
 974         }
 975
 976         return i;
 977 }
 978
 979 static void i915_gem_record_fences(struct drm_device *dev,
 980                                    struct drm_i915_error_state *error)
 981 {
 982         struct drm_i915_private *dev_priv = dev->dev_private;
 983         int i;
 984
 985         /* Fences */
 986         switch (INTEL_INFO(dev)->gen) {
 987         case 7:
 988         case 6:
 989                 for (i = 0; i < 16; i++)
 990                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 991                 break;
 992         case 5:
 993         case 4:
 994                 for (i = 0; i < 16; i++)
 995                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 996                 break;
 997         case 3:
 998                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 999                         for (i = 0; i < 8; i++)
1000                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1001         case 2:
1002                 for (i = 0; i < 8; i++)
1003                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1004                 break;
1005
1006         }
1007 }
1008
1009 static struct drm_i915_error_object *
1010 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1011                              struct intel_ring_buffer *ring)
1012 {
1013         struct drm_i915_gem_object *obj;
1014         u32 seqno;
1015
1016         if (!ring->get_seqno)
1017                 return NULL;
1018
1019         seqno = ring->get_seqno(ring);
1020         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1021                 if (obj->ring != ring)
1022                         continue;
1023
1024                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
1025                         continue;
1026
1027                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1028                         continue;
1029
1030                 /* We need to copy these to an anonymous buffer as the simplest
1031                  * method to avoid being overwritten by userspace.
1032                  */
1033                 return i915_error_object_create(dev_priv, obj);
1034         }
1035
1036         return NULL;
1037 }
1038
1039 static void i915_record_ring_state(struct drm_device *dev,
1040                                    struct drm_i915_error_state *error,
1041                                    struct intel_ring_buffer *ring)
1042 {
1043         struct drm_i915_private *dev_priv = dev->dev_private;
1044
1045         if (INTEL_INFO(dev)->gen >= 6) {
1046                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1047                 error->semaphore_mboxes[ring->id][0]
1048                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1049                 error->semaphore_mboxes[ring->id][1]
1050                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1051         }
1052
1053         if (INTEL_INFO(dev)->gen >= 4) {
1054                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1055                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1056                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1057                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1058                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1059                 if (ring->id == RCS) {
1060                         error->instdone1 = I915_READ(INSTDONE1);
1061                         error->bbaddr = I915_READ64(BB_ADDR);
1062                 }
1063         } else {
1064                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1065                 error->ipeir[ring->id] = I915_READ(IPEIR);
1066                 error->ipehr[ring->id] = I915_READ(IPEHR);
1067                 error->instdone[ring->id] = I915_READ(INSTDONE);
1068         }
1069
1070         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1071         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1072         error->seqno[ring->id] = ring->get_seqno(ring);
1073         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1074         error->head[ring->id] = I915_READ_HEAD(ring);
1075         error->tail[ring->id] = I915_READ_TAIL(ring);
1076
1077         error->cpu_ring_head[ring->id] = ring->head;
1078         error->cpu_ring_tail[ring->id] = ring->tail;
1079 }
1080
1081 static void i915_gem_record_rings(struct drm_device *dev,
1082                                   struct drm_i915_error_state *error)
1083 {
1084         struct drm_i915_private *dev_priv = dev->dev_private;
1085         struct intel_ring_buffer *ring;
1086         struct drm_i915_gem_request *request;
1087         int i, count;
1088
1089         for_each_ring(ring, dev_priv, i) {
1090                 i915_record_ring_state(dev, error, ring);
1091
1092                 error->ring[i].batchbuffer =
1093                         i915_error_first_batchbuffer(dev_priv, ring);
1094
1095                 error->ring[i].ringbuffer =
1096                         i915_error_object_create(dev_priv, ring->obj);
1097
1098                 count = 0;
1099                 list_for_each_entry(request, &ring->request_list, list)
1100                         count++;
1101
1102                 error->ring[i].num_requests = count;
1103                 error->ring[i].requests =
1104                         kmalloc(count*sizeof(struct drm_i915_error_request),
1105                                 GFP_ATOMIC);
1106                 if (error->ring[i].requests == NULL) {
1107                         error->ring[i].num_requests = 0;
1108                         continue;
1109                 }
1110
1111                 count = 0;
1112                 list_for_each_entry(request, &ring->request_list, list) {
1113                         struct drm_i915_error_request *erq;
1114
1115                         erq = &error->ring[i].requests[count++];
1116                         erq->seqno = request->seqno;
1117                         erq->jiffies = request->emitted_jiffies;
1118                         erq->tail = request->tail;
1119                 }
1120         }
1121 }
1122
1123 /**
1124  * i915_capture_error_state - capture an error record for later analysis
1125  * @dev: drm device
1126  *
1127  * Should be called when an error is detected (either a hang or an error
1128  * interrupt) to capture error state from the time of the error.  Fills
1129  * out a structure which becomes available in debugfs for user level tools
1130  * to pick up.
1131  */
1132 static void i915_capture_error_state(struct drm_device *dev)
1133 {
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135         struct drm_i915_gem_object *obj;
1136         struct drm_i915_error_state *error;
1137         unsigned long flags;
1138         int i, pipe;
1139
1140         spin_lock_irqsave(&dev_priv->error_lock, flags);
1141         error = dev_priv->first_error;
1142         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1143         if (error)
1144                 return;
1145
1146         /* Account for pipe specific data like PIPE*STAT */
1147         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1148         if (!error) {
1149                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1150                 return;
1151         }
1152
1153         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1154                  dev->primary->index);
1155
1156         kref_init(&error->ref);
1157         error->eir = I915_READ(EIR);
1158         error->pgtbl_er = I915_READ(PGTBL_ER);
1159         error->ccid = I915_READ(CCID);
1160
1161         if (HAS_PCH_SPLIT(dev))
1162                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1163         else if (IS_VALLEYVIEW(dev))
1164                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1165         else if (IS_GEN2(dev))
1166                 error->ier = I915_READ16(IER);
1167         else
1168                 error->ier = I915_READ(IER);
1169
1170         for_each_pipe(pipe)
1171                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1172
1173         if (INTEL_INFO(dev)->gen >= 6) {
1174                 error->error = I915_READ(ERROR_GEN6);
1175                 error->done_reg = I915_READ(DONE_REG);
1176         }
1177
1178         i915_gem_record_fences(dev, error);
1179         i915_gem_record_rings(dev, error);
1180
1181         /* Record buffers on the active and pinned lists. */
1182         error->active_bo = NULL;
1183         error->pinned_bo = NULL;
1184
1185         i = 0;
1186         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1187                 i++;
1188         error->active_bo_count = i;
1189         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1190                 if (obj->pin_count)
1191                         i++;
1192         error->pinned_bo_count = i - error->active_bo_count;
1193
1194         error->active_bo = NULL;
1195         error->pinned_bo = NULL;
1196         if (i) {
1197                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1198                                            GFP_ATOMIC);
1199                 if (error->active_bo)
1200                         error->pinned_bo =
1201                                 error->active_bo + error->active_bo_count;
1202         }
1203
1204         if (error->active_bo)
1205                 error->active_bo_count =
1206                         capture_active_bo(error->active_bo,
1207                                           error->active_bo_count,
1208                                           &dev_priv->mm.active_list);
1209
1210         if (error->pinned_bo)
1211                 error->pinned_bo_count =
1212                         capture_pinned_bo(error->pinned_bo,
1213                                           error->pinned_bo_count,
1214                                           &dev_priv->mm.gtt_list);
1215
1216         do_gettimeofday(&error->time);
1217
1218         error->overlay = intel_overlay_capture_error_state(dev);
1219         error->display = intel_display_capture_error_state(dev);
1220
1221         spin_lock_irqsave(&dev_priv->error_lock, flags);
1222         if (dev_priv->first_error == NULL) {
1223                 dev_priv->first_error = error;
1224                 error = NULL;
1225         }
1226         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1227
1228         if (error)
1229                 i915_error_state_free(&error->ref);
1230 }
1231
1232 void i915_destroy_error_state(struct drm_device *dev)
1233 {
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         struct drm_i915_error_state *error;
1236         unsigned long flags;
1237
1238         spin_lock_irqsave(&dev_priv->error_lock, flags);
1239         error = dev_priv->first_error;
1240         dev_priv->first_error = NULL;
1241         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1242
1243         if (error)
1244                 kref_put(&error->ref, i915_error_state_free);
1245 }
1246 #else
1247 #define i915_capture_error_state(x)
1248 #endif
1249
1250 static void i915_report_and_clear_eir(struct drm_device *dev)
1251 {
1252         struct drm_i915_private *dev_priv = dev->dev_private;
1253         u32 eir = I915_READ(EIR);
1254         int pipe;
1255
1256         if (!eir)
1257                 return;
1258
1259         pr_err("render error detected, EIR: 0x%08x\n", eir);
1260
1261         if (IS_G4X(dev)) {
1262                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1263                         u32 ipeir = I915_READ(IPEIR_I965);
1264
1265                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1266                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1267                         pr_err("  INSTDONE: 0x%08x\n",
1268                                I915_READ(INSTDONE_I965));
1269                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1270                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1271                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1272                         I915_WRITE(IPEIR_I965, ipeir);
1273                         POSTING_READ(IPEIR_I965);
1274                 }
1275                 if (eir & GM45_ERROR_PAGE_TABLE) {
1276                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1277                         pr_err("page table error\n");
1278                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1279                         I915_WRITE(PGTBL_ER, pgtbl_err);
1280                         POSTING_READ(PGTBL_ER);
1281                 }
1282         }
1283
1284         if (!IS_GEN2(dev)) {
1285                 if (eir & I915_ERROR_PAGE_TABLE) {
1286                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1287                         pr_err("page table error\n");
1288                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1289                         I915_WRITE(PGTBL_ER, pgtbl_err);
1290                         POSTING_READ(PGTBL_ER);
1291                 }
1292         }
1293
1294         if (eir & I915_ERROR_MEMORY_REFRESH) {
1295                 pr_err("memory refresh error:\n");
1296                 for_each_pipe(pipe)
1297                         pr_err("pipe %c stat: 0x%08x\n",
1298                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1299                 /* pipestat has already been acked */
1300         }
1301         if (eir & I915_ERROR_INSTRUCTION) {
1302                 pr_err("instruction error\n");
1303                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1304                 if (INTEL_INFO(dev)->gen < 4) {
1305                         u32 ipeir = I915_READ(IPEIR);
1306
1307                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1308                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1309                         pr_err("  INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1310                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1311                         I915_WRITE(IPEIR, ipeir);
1312                         POSTING_READ(IPEIR);
1313                 } else {
1314                         u32 ipeir = I915_READ(IPEIR_I965);
1315
1316                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1317                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1318                         pr_err("  INSTDONE: 0x%08x\n",
1319                                I915_READ(INSTDONE_I965));
1320                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1321                         pr_err("  INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1322                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1323                         I915_WRITE(IPEIR_I965, ipeir);
1324                         POSTING_READ(IPEIR_I965);
1325                 }
1326         }
1327
1328         I915_WRITE(EIR, eir);
1329         POSTING_READ(EIR);
1330         eir = I915_READ(EIR);
1331         if (eir) {
1332                 /*
1333                  * some errors might have become stuck,
1334                  * mask them.
1335                  */
1336                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1337                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1338                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1339         }
1340 }
1341
1342 /**
1343  * i915_handle_error - handle an error interrupt
1344  * @dev: drm device
1345  *
1346  * Do some basic checking of regsiter state at error interrupt time and
1347  * dump it to the syslog.  Also call i915_capture_error_state() to make
1348  * sure we get a record and make it available in debugfs.  Fire a uevent
1349  * so userspace knows something bad happened (should trigger collection
1350  * of a ring dump etc.).
1351  */
1352 void i915_handle_error(struct drm_device *dev, bool wedged)
1353 {
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355         struct intel_ring_buffer *ring;
1356         int i;
1357
1358         i915_capture_error_state(dev);
1359         i915_report_and_clear_eir(dev);
1360
1361         if (wedged) {
1362                 INIT_COMPLETION(dev_priv->error_completion);
1363                 atomic_set(&dev_priv->mm.wedged, 1);
1364
1365                 /*
1366                  * Wakeup waiting processes so they don't hang
1367                  */
1368                 for_each_ring(ring, dev_priv, i)
1369                         wake_up_all(&ring->irq_queue);
1370         }
1371
1372         queue_work(dev_priv->wq, &dev_priv->error_work);
1373 }
1374
1375 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1376 {
1377         drm_i915_private_t *dev_priv = dev->dev_private;
1378         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1380         struct drm_i915_gem_object *obj;
1381         struct intel_unpin_work *work;
1382         unsigned long flags;
1383         bool stall_detected;
1384
1385         /* Ignore early vblank irqs */
1386         if (intel_crtc == NULL)
1387                 return;
1388
1389         spin_lock_irqsave(&dev->event_lock, flags);
1390         work = intel_crtc->unpin_work;
1391
1392         if (work == NULL || work->pending || !work->enable_stall_check) {
1393                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1394                 spin_unlock_irqrestore(&dev->event_lock, flags);
1395                 return;
1396         }
1397
1398         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1399         obj = work->pending_flip_obj;
1400         if (INTEL_INFO(dev)->gen >= 4) {
1401                 int dspsurf = DSPSURF(intel_crtc->plane);
1402                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1403                                         obj->gtt_offset;
1404         } else {
1405                 int dspaddr = DSPADDR(intel_crtc->plane);
1406                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1407                                                         crtc->y * crtc->fb->pitches[0] +
1408                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1409         }
1410
1411         spin_unlock_irqrestore(&dev->event_lock, flags);
1412
1413         if (stall_detected) {
1414                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1415                 intel_prepare_page_flip(dev, intel_crtc->plane);
1416         }
1417 }
1418
1419 /* Called from drm generic code, passed 'crtc' which
1420  * we use as a pipe index
1421  */
1422 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1423 {
1424         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1425         unsigned long irqflags;
1426
1427         if (!i915_pipe_enabled(dev, pipe))
1428                 return -EINVAL;
1429
1430         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1431         if (INTEL_INFO(dev)->gen >= 4)
1432                 i915_enable_pipestat(dev_priv, pipe,
1433                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1434         else
1435                 i915_enable_pipestat(dev_priv, pipe,
1436                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1437
1438         /* maintain vblank delivery even in deep C-states */
1439         if (dev_priv->info->gen == 3)
1440                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1441         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1442
1443         return 0;
1444 }
1445
1446 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1447 {
1448         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1449         unsigned long irqflags;
1450
1451         if (!i915_pipe_enabled(dev, pipe))
1452                 return -EINVAL;
1453
1454         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1455         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1456                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1457         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1458
1459         return 0;
1460 }
1461
1462 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1463 {
1464         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1465         unsigned long irqflags;
1466
1467         if (!i915_pipe_enabled(dev, pipe))
1468                 return -EINVAL;
1469
1470         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1471         ironlake_enable_display_irq(dev_priv,
1472                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1473         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1474
1475         return 0;
1476 }
1477
1478 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1479 {
1480         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1481         unsigned long irqflags;
1482         u32 dpfl, imr;
1483
1484         if (!i915_pipe_enabled(dev, pipe))
1485                 return -EINVAL;
1486
1487         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1488         dpfl = I915_READ(VLV_DPFLIPSTAT);
1489         imr = I915_READ(VLV_IMR);
1490         if (pipe == 0) {
1491                 dpfl |= PIPEA_VBLANK_INT_EN;
1492                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1493         } else {
1494                 dpfl |= PIPEA_VBLANK_INT_EN;
1495                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1496         }
1497         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1498         I915_WRITE(VLV_IMR, imr);
1499         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1500
1501         return 0;
1502 }
1503
1504 /* Called from drm generic code, passed 'crtc' which
1505  * we use as a pipe index
1506  */
1507 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1508 {
1509         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1510         unsigned long irqflags;
1511
1512         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1513         if (dev_priv->info->gen == 3)
1514                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1515
1516         i915_disable_pipestat(dev_priv, pipe,
1517                               PIPE_VBLANK_INTERRUPT_ENABLE |
1518                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1519         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1520 }
1521
1522 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1523 {
1524         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1525         unsigned long irqflags;
1526
1527         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1528         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1529                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1530         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1531 }
1532
1533 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1534 {
1535         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1536         unsigned long irqflags;
1537
1538         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1539         ironlake_disable_display_irq(dev_priv,
1540                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1541         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1542 }
1543
1544 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1545 {
1546         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1547         unsigned long irqflags;
1548         u32 dpfl, imr;
1549
1550         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1551         dpfl = I915_READ(VLV_DPFLIPSTAT);
1552         imr = I915_READ(VLV_IMR);
1553         if (pipe == 0) {
1554                 dpfl &= ~PIPEA_VBLANK_INT_EN;
1555                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1556         } else {
1557                 dpfl &= ~PIPEB_VBLANK_INT_EN;
1558                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1559         }
1560         I915_WRITE(VLV_IMR, imr);
1561         I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1562         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1563 }
1564
1565 static u32
1566 ring_last_seqno(struct intel_ring_buffer *ring)
1567 {
1568         return list_entry(ring->request_list.prev,
1569                           struct drm_i915_gem_request, list)->seqno;
1570 }
1571
1572 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1573 {
1574         if (list_empty(&ring->request_list) ||
1575             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1576                 /* Issue a wake-up to catch stuck h/w. */
1577                 if (waitqueue_active(&ring->irq_queue)) {
1578                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1579                                   ring->name);
1580                         wake_up_all(&ring->irq_queue);
1581                         *err = true;
1582                 }
1583                 return true;
1584         }
1585         return false;
1586 }
1587
1588 static bool kick_ring(struct intel_ring_buffer *ring)
1589 {
1590         struct drm_device *dev = ring->dev;
1591         struct drm_i915_private *dev_priv = dev->dev_private;
1592         u32 tmp = I915_READ_CTL(ring);
1593         if (tmp & RING_WAIT) {
1594                 DRM_ERROR("Kicking stuck wait on %s\n",
1595                           ring->name);
1596                 I915_WRITE_CTL(ring, tmp);
1597                 return true;
1598         }
1599         return false;
1600 }
1601
1602 static bool i915_hangcheck_hung(struct drm_device *dev)
1603 {
1604         drm_i915_private_t *dev_priv = dev->dev_private;
1605
1606         if (dev_priv->hangcheck_count++ > 1) {
1607                 bool hung = true;
1608
1609                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1610                 i915_handle_error(dev, true);
1611
1612                 if (!IS_GEN2(dev)) {
1613                         struct intel_ring_buffer *ring;
1614                         int i;
1615
1616                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1617                          * If so we can simply poke the RB_WAIT bit
1618                          * and break the hang. This should work on
1619                          * all but the second generation chipsets.
1620                          */
1621                         for_each_ring(ring, dev_priv, i)
1622                                 hung &= !kick_ring(ring);
1623                 }
1624
1625                 return hung;
1626         }
1627
1628         return false;
1629 }
1630
1631 /**
1632  * This is called when the chip hasn't reported back with completed
1633  * batchbuffers in a long time. The first time this is called we simply record
1634  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1635  * again, we assume the chip is wedged and try to fix it.
1636  */
1637 void i915_hangcheck_elapsed(unsigned long data)
1638 {
1639         struct drm_device *dev = (struct drm_device *)data;
1640         drm_i915_private_t *dev_priv = dev->dev_private;
1641         uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1642         struct intel_ring_buffer *ring;
1643         bool err = false, idle;
1644         int i;
1645
1646         if (!i915_enable_hangcheck)
1647                 return;
1648
1649         memset(acthd, 0, sizeof(acthd));
1650         idle = true;
1651         for_each_ring(ring, dev_priv, i) {
1652             idle &= i915_hangcheck_ring_idle(ring, &err);
1653             acthd[i] = intel_ring_get_active_head(ring);
1654         }
1655
1656         /* If all work is done then ACTHD clearly hasn't advanced. */
1657         if (idle) {
1658                 if (err) {
1659                         if (i915_hangcheck_hung(dev))
1660                                 return;
1661
1662                         goto repeat;
1663                 }
1664
1665                 dev_priv->hangcheck_count = 0;
1666                 return;
1667         }
1668
1669         if (INTEL_INFO(dev)->gen < 4) {
1670                 instdone = I915_READ(INSTDONE);
1671                 instdone1 = 0;
1672         } else {
1673                 instdone = I915_READ(INSTDONE_I965);
1674                 instdone1 = I915_READ(INSTDONE1);
1675         }
1676
1677         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1678             dev_priv->last_instdone == instdone &&
1679             dev_priv->last_instdone1 == instdone1) {
1680                 if (i915_hangcheck_hung(dev))
1681                         return;
1682         } else {
1683                 dev_priv->hangcheck_count = 0;
1684
1685                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1686                 dev_priv->last_instdone = instdone;
1687                 dev_priv->last_instdone1 = instdone1;
1688         }
1689
1690 repeat:
1691         /* Reset timer case chip hangs without another request being added */
1692         mod_timer(&dev_priv->hangcheck_timer,
1693                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1694 }
1695
1696 /* drm_dma.h hooks
1697 */
1698 static void ironlake_irq_preinstall(struct drm_device *dev)
1699 {
1700         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1701
1702         atomic_set(&dev_priv->irq_received, 0);
1703
1704         I915_WRITE(HWSTAM, 0xeffe);
1705
1706         /* XXX hotplug from PCH */
1707
1708         I915_WRITE(DEIMR, 0xffffffff);
1709         I915_WRITE(DEIER, 0x0);
1710         POSTING_READ(DEIER);
1711
1712         /* and GT */
1713         I915_WRITE(GTIMR, 0xffffffff);
1714         I915_WRITE(GTIER, 0x0);
1715         POSTING_READ(GTIER);
1716
1717         /* south display irq */
1718         I915_WRITE(SDEIMR, 0xffffffff);
1719         I915_WRITE(SDEIER, 0x0);
1720         POSTING_READ(SDEIER);
1721 }
1722
1723 static void valleyview_irq_preinstall(struct drm_device *dev)
1724 {
1725         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1726         int pipe;
1727
1728         atomic_set(&dev_priv->irq_received, 0);
1729
1730         /* VLV magic */
1731         I915_WRITE(VLV_IMR, 0);
1732         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1733         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1734         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1735
1736         /* and GT */
1737         I915_WRITE(GTIIR, I915_READ(GTIIR));
1738         I915_WRITE(GTIIR, I915_READ(GTIIR));
1739         I915_WRITE(GTIMR, 0xffffffff);
1740         I915_WRITE(GTIER, 0x0);
1741         POSTING_READ(GTIER);
1742
1743         I915_WRITE(DPINVGTT, 0xff);
1744
1745         I915_WRITE(PORT_HOTPLUG_EN, 0);
1746         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1747         for_each_pipe(pipe)
1748                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1749         I915_WRITE(VLV_IIR, 0xffffffff);
1750         I915_WRITE(VLV_IMR, 0xffffffff);
1751         I915_WRITE(VLV_IER, 0x0);
1752         POSTING_READ(VLV_IER);
1753 }
1754
1755 /*
1756  * Enable digital hotplug on the PCH, and configure the DP short pulse
1757  * duration to 2ms (which is the minimum in the Display Port spec)
1758  *
1759  * This register is the same on all known PCH chips.
1760  */
1761
1762 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1763 {
1764         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1765         u32     hotplug;
1766
1767         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1768         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1769         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1770         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1771         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1772         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1773 }
1774
1775 static int ironlake_irq_postinstall(struct drm_device *dev)
1776 {
1777         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1778         /* enable kind of interrupts always enabled */
1779         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1780                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1781         u32 render_irqs;
1782         u32 hotplug_mask;
1783
1784         dev_priv->irq_mask = ~display_mask;
1785
1786         /* should always can generate irq */
1787         I915_WRITE(DEIIR, I915_READ(DEIIR));
1788         I915_WRITE(DEIMR, dev_priv->irq_mask);
1789         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1790         POSTING_READ(DEIER);
1791
1792         dev_priv->gt_irq_mask = ~0;
1793
1794         I915_WRITE(GTIIR, I915_READ(GTIIR));
1795         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1796
1797         if (IS_GEN6(dev))
1798                 render_irqs =
1799                         GT_USER_INTERRUPT |
1800                         GEN6_BSD_USER_INTERRUPT |
1801                         GEN6_BLITTER_USER_INTERRUPT;
1802         else
1803                 render_irqs =
1804                         GT_USER_INTERRUPT |
1805                         GT_PIPE_NOTIFY |
1806                         GT_BSD_USER_INTERRUPT;
1807         I915_WRITE(GTIER, render_irqs);
1808         POSTING_READ(GTIER);
1809
1810         if (HAS_PCH_CPT(dev)) {
1811                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1812                                 SDE_PORTB_HOTPLUG_CPT |
1813                                 SDE_PORTC_HOTPLUG_CPT |
1814                                 SDE_PORTD_HOTPLUG_CPT);
1815         } else {
1816                 hotplug_mask = (SDE_CRT_HOTPLUG |
1817                                 SDE_PORTB_HOTPLUG |
1818                                 SDE_PORTC_HOTPLUG |
1819                                 SDE_PORTD_HOTPLUG |
1820                                 SDE_AUX_MASK);
1821         }
1822
1823         dev_priv->pch_irq_mask = ~hotplug_mask;
1824
1825         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1826         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1827         I915_WRITE(SDEIER, hotplug_mask);
1828         POSTING_READ(SDEIER);
1829
1830         ironlake_enable_pch_hotplug(dev);
1831
1832         if (IS_IRONLAKE_M(dev)) {
1833                 /* Clear & enable PCU event interrupts */
1834                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1835                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1836                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int ivybridge_irq_postinstall(struct drm_device *dev)
1843 {
1844         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1845         /* enable kind of interrupts always enabled */
1846         u32 display_mask =
1847                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1848                 DE_PLANEC_FLIP_DONE_IVB |
1849                 DE_PLANEB_FLIP_DONE_IVB |
1850                 DE_PLANEA_FLIP_DONE_IVB;
1851         u32 render_irqs;
1852         u32 hotplug_mask;
1853
1854         dev_priv->irq_mask = ~display_mask;
1855
1856         /* should always can generate irq */
1857         I915_WRITE(DEIIR, I915_READ(DEIIR));
1858         I915_WRITE(DEIMR, dev_priv->irq_mask);
1859         I915_WRITE(DEIER,
1860                    display_mask |
1861                    DE_PIPEC_VBLANK_IVB |
1862                    DE_PIPEB_VBLANK_IVB |
1863                    DE_PIPEA_VBLANK_IVB);
1864         POSTING_READ(DEIER);
1865
1866         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1867
1868         I915_WRITE(GTIIR, I915_READ(GTIIR));
1869         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1870
1871         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1872                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1873         I915_WRITE(GTIER, render_irqs);
1874         POSTING_READ(GTIER);
1875
1876         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1877                         SDE_PORTB_HOTPLUG_CPT |
1878                         SDE_PORTC_HOTPLUG_CPT |
1879                         SDE_PORTD_HOTPLUG_CPT);
1880         dev_priv->pch_irq_mask = ~hotplug_mask;
1881
1882         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1883         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1884         I915_WRITE(SDEIER, hotplug_mask);
1885         POSTING_READ(SDEIER);
1886
1887         ironlake_enable_pch_hotplug(dev);
1888
1889         return 0;
1890 }
1891
1892 static int valleyview_irq_postinstall(struct drm_device *dev)
1893 {
1894         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1895         u32 render_irqs;
1896         u32 enable_mask;
1897         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1898         u16 msid;
1899
1900         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1901         enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1902                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1903
1904         dev_priv->irq_mask = ~enable_mask;
1905
1906         dev_priv->pipestat[0] = 0;
1907         dev_priv->pipestat[1] = 0;
1908
1909         /* Hack for broken MSIs on VLV */
1910         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1911         pci_read_config_word(dev->pdev, 0x98, &msid);
1912         msid &= 0xff; /* mask out delivery bits */
1913         msid |= (1<<14);
1914         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1915
1916         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1917         I915_WRITE(VLV_IER, enable_mask);
1918         I915_WRITE(VLV_IIR, 0xffffffff);
1919         I915_WRITE(PIPESTAT(0), 0xffff);
1920         I915_WRITE(PIPESTAT(1), 0xffff);
1921         POSTING_READ(VLV_IER);
1922
1923         I915_WRITE(VLV_IIR, 0xffffffff);
1924         I915_WRITE(VLV_IIR, 0xffffffff);
1925
1926         render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1927                 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1928                 GT_GEN6_BLT_USER_INTERRUPT |
1929                 GT_GEN6_BSD_USER_INTERRUPT |
1930                 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1931                 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1932                 GT_PIPE_NOTIFY |
1933                 GT_RENDER_CS_ERROR_INTERRUPT |
1934                 GT_SYNC_STATUS |
1935                 GT_USER_INTERRUPT;
1936
1937         dev_priv->gt_irq_mask = ~render_irqs;
1938
1939         I915_WRITE(GTIIR, I915_READ(GTIIR));
1940         I915_WRITE(GTIIR, I915_READ(GTIIR));
1941         I915_WRITE(GTIMR, 0);
1942         I915_WRITE(GTIER, render_irqs);
1943         POSTING_READ(GTIER);
1944
1945         /* ack & enable invalid PTE error interrupts */
1946 #if 0 /* FIXME: add support to irq handler for checking these bits */
1947         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1948         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1949 #endif
1950
1951         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1952 #if 0 /* FIXME: check register definitions; some have moved */
1953         /* Note HDMI and DP share bits */
1954         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1955                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1956         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1957                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1958         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1959                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1960         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1961                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1962         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1963                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1964         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1965                 hotplug_en |= CRT_HOTPLUG_INT_EN;
1966                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1967         }
1968 #endif
1969
1970         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1971
1972         return 0;
1973 }
1974
1975 static void valleyview_irq_uninstall(struct drm_device *dev)
1976 {
1977         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1978         int pipe;
1979
1980         if (!dev_priv)
1981                 return;
1982
1983         for_each_pipe(pipe)
1984                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1985
1986         I915_WRITE(HWSTAM, 0xffffffff);
1987         I915_WRITE(PORT_HOTPLUG_EN, 0);
1988         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1989         for_each_pipe(pipe)
1990                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1991         I915_WRITE(VLV_IIR, 0xffffffff);
1992         I915_WRITE(VLV_IMR, 0xffffffff);
1993         I915_WRITE(VLV_IER, 0x0);
1994         POSTING_READ(VLV_IER);
1995 }
1996
1997 static void ironlake_irq_uninstall(struct drm_device *dev)
1998 {
1999         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2000
2001         if (!dev_priv)
2002                 return;
2003
2004         I915_WRITE(HWSTAM, 0xffffffff);
2005
2006         I915_WRITE(DEIMR, 0xffffffff);
2007         I915_WRITE(DEIER, 0x0);
2008         I915_WRITE(DEIIR, I915_READ(DEIIR));
2009
2010         I915_WRITE(GTIMR, 0xffffffff);
2011         I915_WRITE(GTIER, 0x0);
2012         I915_WRITE(GTIIR, I915_READ(GTIIR));
2013
2014         I915_WRITE(SDEIMR, 0xffffffff);
2015         I915_WRITE(SDEIER, 0x0);
2016         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2017 }
2018
2019 static void i8xx_irq_preinstall(struct drm_device * dev)
2020 {
2021         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2022         int pipe;
2023
2024         atomic_set(&dev_priv->irq_received, 0);
2025
2026         for_each_pipe(pipe)
2027                 I915_WRITE(PIPESTAT(pipe), 0);
2028         I915_WRITE16(IMR, 0xffff);
2029         I915_WRITE16(IER, 0x0);
2030         POSTING_READ16(IER);
2031 }
2032
2033 static int i8xx_irq_postinstall(struct drm_device *dev)
2034 {
2035         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2036
2037         dev_priv->pipestat[0] = 0;
2038         dev_priv->pipestat[1] = 0;
2039
2040         I915_WRITE16(EMR,
2041                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2042
2043         /* Unmask the interrupts that we always want on. */
2044         dev_priv->irq_mask =
2045                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2046                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2047                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2048                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2049                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2050         I915_WRITE16(IMR, dev_priv->irq_mask);
2051
2052         I915_WRITE16(IER,
2053                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2054                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2055                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2056                      I915_USER_INTERRUPT);
2057         POSTING_READ16(IER);
2058
2059         return 0;
2060 }
2061
2062 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2063 {
2064         struct drm_device *dev = (struct drm_device *) arg;
2065         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2066         u16 iir, new_iir;
2067         u32 pipe_stats[2];
2068         unsigned long irqflags;
2069         int irq_received;
2070         int pipe;
2071         u16 flip_mask =
2072                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2073                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2074
2075         atomic_inc(&dev_priv->irq_received);
2076
2077         iir = I915_READ16(IIR);
2078         if (iir == 0)
2079                 return IRQ_NONE;
2080
2081         while (iir & ~flip_mask) {
2082                 /* Can't rely on pipestat interrupt bit in iir as it might
2083                  * have been cleared after the pipestat interrupt was received.
2084                  * It doesn't set the bit in iir again, but it still produces
2085                  * interrupts (for non-MSI).
2086                  */
2087                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2088                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2089                         i915_handle_error(dev, false);
2090
2091                 for_each_pipe(pipe) {
2092                         int reg = PIPESTAT(pipe);
2093                         pipe_stats[pipe] = I915_READ(reg);
2094
2095                         /*
2096                          * Clear the PIPE*STAT regs before the IIR
2097                          */
2098                         if (pipe_stats[pipe] & 0x8000ffff) {
2099                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2100                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2101                                                          pipe_name(pipe));
2102                                 I915_WRITE(reg, pipe_stats[pipe]);
2103                                 irq_received = 1;
2104                         }
2105                 }
2106                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2107
2108                 I915_WRITE16(IIR, iir & ~flip_mask);
2109                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2110
2111                 i915_update_dri1_breadcrumb(dev);
2112
2113                 if (iir & I915_USER_INTERRUPT)
2114                         notify_ring(dev, &dev_priv->ring[RCS]);
2115
2116                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2117                     drm_handle_vblank(dev, 0)) {
2118                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2119                                 intel_prepare_page_flip(dev, 0);
2120                                 intel_finish_page_flip(dev, 0);
2121                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2122                         }
2123                 }
2124
2125                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2126                     drm_handle_vblank(dev, 1)) {
2127                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2128                                 intel_prepare_page_flip(dev, 1);
2129                                 intel_finish_page_flip(dev, 1);
2130                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2131                         }
2132                 }
2133
2134                 iir = new_iir;
2135         }
2136
2137         return IRQ_HANDLED;
2138 }
2139
2140 static void i8xx_irq_uninstall(struct drm_device * dev)
2141 {
2142         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2143         int pipe;
2144
2145         for_each_pipe(pipe) {
2146                 /* Clear enable bits; then clear status bits */
2147                 I915_WRITE(PIPESTAT(pipe), 0);
2148                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2149         }
2150         I915_WRITE16(IMR, 0xffff);
2151         I915_WRITE16(IER, 0x0);
2152         I915_WRITE16(IIR, I915_READ16(IIR));
2153 }
2154
2155 static void i915_irq_preinstall(struct drm_device * dev)
2156 {
2157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2158         int pipe;
2159
2160         atomic_set(&dev_priv->irq_received, 0);
2161
2162         if (I915_HAS_HOTPLUG(dev)) {
2163                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2164                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2165         }
2166
2167         I915_WRITE16(HWSTAM, 0xeffe);
2168         for_each_pipe(pipe)
2169                 I915_WRITE(PIPESTAT(pipe), 0);
2170         I915_WRITE(IMR, 0xffffffff);
2171         I915_WRITE(IER, 0x0);
2172         POSTING_READ(IER);
2173 }
2174
2175 static int i915_irq_postinstall(struct drm_device *dev)
2176 {
2177         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2178         u32 enable_mask;
2179
2180         dev_priv->pipestat[0] = 0;
2181         dev_priv->pipestat[1] = 0;
2182
2183         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2184
2185         /* Unmask the interrupts that we always want on. */
2186         dev_priv->irq_mask =
2187                 ~(I915_ASLE_INTERRUPT |
2188                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2189                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2190                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2191                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2192                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2193
2194         enable_mask =
2195                 I915_ASLE_INTERRUPT |
2196                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2197                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2198                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2199                 I915_USER_INTERRUPT;
2200
2201         if (I915_HAS_HOTPLUG(dev)) {
2202                 /* Enable in IER... */
2203                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2204                 /* and unmask in IMR */
2205                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2206         }
2207
2208         I915_WRITE(IMR, dev_priv->irq_mask);
2209         I915_WRITE(IER, enable_mask);
2210         POSTING_READ(IER);
2211
2212         if (I915_HAS_HOTPLUG(dev)) {
2213                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2214
2215                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2216                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2217                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2218                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2219                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2220                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2221                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2222                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2223                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2224                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2225                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2226                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2227                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2228                 }
2229
2230                 /* Ignore TV since it's buggy */
2231
2232                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2233         }
2234
2235         intel_opregion_enable_asle(dev);
2236
2237         return 0;
2238 }
2239
2240 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2241 {
2242         struct drm_device *dev = (struct drm_device *) arg;
2243         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2244         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2245         unsigned long irqflags;
2246         u32 flip_mask =
2247                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2248                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2249         u32 flip[2] = {
2250                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2251                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2252         };
2253         int pipe, ret = IRQ_NONE;
2254
2255         atomic_inc(&dev_priv->irq_received);
2256
2257         iir = I915_READ(IIR);
2258         do {
2259                 bool irq_received = (iir & ~flip_mask) != 0;
2260                 bool blc_event = false;
2261
2262                 /* Can't rely on pipestat interrupt bit in iir as it might
2263                  * have been cleared after the pipestat interrupt was received.
2264                  * It doesn't set the bit in iir again, but it still produces
2265                  * interrupts (for non-MSI).
2266                  */
2267                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2268                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2269                         i915_handle_error(dev, false);
2270
2271                 for_each_pipe(pipe) {
2272                         int reg = PIPESTAT(pipe);
2273                         pipe_stats[pipe] = I915_READ(reg);
2274
2275                         /* Clear the PIPE*STAT regs before the IIR */
2276                         if (pipe_stats[pipe] & 0x8000ffff) {
2277                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2278                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2279                                                          pipe_name(pipe));
2280                                 I915_WRITE(reg, pipe_stats[pipe]);
2281                                 irq_received = true;
2282                         }
2283                 }
2284                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2285
2286                 if (!irq_received)
2287                         break;
2288
2289                 /* Consume port.  Then clear IIR or we'll miss events */
2290                 if ((I915_HAS_HOTPLUG(dev)) &&
2291                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2292                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2293
2294                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2295                                   hotplug_status);
2296                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2297                                 queue_work(dev_priv->wq,
2298                                            &dev_priv->hotplug_work);
2299
2300                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2301                         POSTING_READ(PORT_HOTPLUG_STAT);
2302                 }
2303
2304                 I915_WRITE(IIR, iir & ~flip_mask);
2305                 new_iir = I915_READ(IIR); /* Flush posted writes */
2306
2307                 if (iir & I915_USER_INTERRUPT)
2308                         notify_ring(dev, &dev_priv->ring[RCS]);
2309
2310                 for_each_pipe(pipe) {
2311                         int plane = pipe;
2312                         if (IS_MOBILE(dev))
2313                                 plane = !plane;
2314                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2315                             drm_handle_vblank(dev, pipe)) {
2316                                 if (iir & flip[plane]) {
2317                                         intel_prepare_page_flip(dev, plane);
2318                                         intel_finish_page_flip(dev, pipe);
2319                                         flip_mask &= ~flip[plane];
2320                                 }
2321                         }
2322
2323                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2324                                 blc_event = true;
2325                 }
2326
2327                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2328                         intel_opregion_asle_intr(dev);
2329
2330                 /* With MSI, interrupts are only generated when iir
2331                  * transitions from zero to nonzero.  If another bit got
2332                  * set while we were handling the existing iir bits, then
2333                  * we would never get another interrupt.
2334                  *
2335                  * This is fine on non-MSI as well, as if we hit this path
2336                  * we avoid exiting the interrupt handler only to generate
2337                  * another one.
2338                  *
2339                  * Note that for MSI this could cause a stray interrupt report
2340                  * if an interrupt landed in the time between writing IIR and
2341                  * the posting read.  This should be rare enough to never
2342                  * trigger the 99% of 100,000 interrupts test for disabling
2343                  * stray interrupts.
2344                  */
2345                 ret = IRQ_HANDLED;
2346                 iir = new_iir;
2347         } while (iir & ~flip_mask);
2348
2349         i915_update_dri1_breadcrumb(dev);
2350
2351         return ret;
2352 }
2353
2354 static void i915_irq_uninstall(struct drm_device * dev)
2355 {
2356         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2357         int pipe;
2358
2359         if (I915_HAS_HOTPLUG(dev)) {
2360                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2361                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2362         }
2363
2364         I915_WRITE16(HWSTAM, 0xffff);
2365         for_each_pipe(pipe) {
2366                 /* Clear enable bits; then clear status bits */
2367                 I915_WRITE(PIPESTAT(pipe), 0);
2368                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2369         }
2370         I915_WRITE(IMR, 0xffffffff);
2371         I915_WRITE(IER, 0x0);
2372
2373         I915_WRITE(IIR, I915_READ(IIR));
2374 }
2375
2376 static void i965_irq_preinstall(struct drm_device * dev)
2377 {
2378         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2379         int pipe;
2380
2381         atomic_set(&dev_priv->irq_received, 0);
2382
2383         I915_WRITE(PORT_HOTPLUG_EN, 0);
2384         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2385
2386         I915_WRITE(HWSTAM, 0xeffe);
2387         for_each_pipe(pipe)
2388                 I915_WRITE(PIPESTAT(pipe), 0);
2389         I915_WRITE(IMR, 0xffffffff);
2390         I915_WRITE(IER, 0x0);
2391         POSTING_READ(IER);
2392 }
2393
2394 static int i965_irq_postinstall(struct drm_device *dev)
2395 {
2396         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2397         u32 hotplug_en;
2398         u32 enable_mask;
2399         u32 error_mask;
2400
2401         /* Unmask the interrupts that we always want on. */
2402         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2403                                I915_DISPLAY_PORT_INTERRUPT |
2404                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2405                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2406                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2407                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2408                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2409
2410         enable_mask = ~dev_priv->irq_mask;
2411         enable_mask |= I915_USER_INTERRUPT;
2412
2413         if (IS_G4X(dev))
2414                 enable_mask |= I915_BSD_USER_INTERRUPT;
2415
2416         dev_priv->pipestat[0] = 0;
2417         dev_priv->pipestat[1] = 0;
2418
2419         /*
2420          * Enable some error detection, note the instruction error mask
2421          * bit is reserved, so we leave it masked.
2422          */
2423         if (IS_G4X(dev)) {
2424                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2425                                GM45_ERROR_MEM_PRIV |
2426                                GM45_ERROR_CP_PRIV |
2427                                I915_ERROR_MEMORY_REFRESH);
2428         } else {
2429                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2430                                I915_ERROR_MEMORY_REFRESH);
2431         }
2432         I915_WRITE(EMR, error_mask);
2433
2434         I915_WRITE(IMR, dev_priv->irq_mask);
2435         I915_WRITE(IER, enable_mask);
2436         POSTING_READ(IER);
2437
2438         /* Note HDMI and DP share hotplug bits */
2439         hotplug_en = 0;
2440         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2441                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2442         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2443                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2444         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2445                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2446         if (IS_G4X(dev)) {
2447                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2448                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2449                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2450                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2451         } else {
2452                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2453                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2454                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2455                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2456         }
2457         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2458                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2459
2460                 /* Programming the CRT detection parameters tends
2461                    to generate a spurious hotplug event about three
2462                    seconds later.  So just do it once.
2463                    */
2464                 if (IS_G4X(dev))
2465                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2466                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2467         }
2468
2469         /* Ignore TV since it's buggy */
2470
2471         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2472
2473         intel_opregion_enable_asle(dev);
2474
2475         return 0;
2476 }
2477
2478 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2479 {
2480         struct drm_device *dev = (struct drm_device *) arg;
2481         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2482         u32 iir, new_iir;
2483         u32 pipe_stats[I915_MAX_PIPES];
2484         unsigned long irqflags;
2485         int irq_received;
2486         int ret = IRQ_NONE, pipe;
2487
2488         atomic_inc(&dev_priv->irq_received);
2489
2490         iir = I915_READ(IIR);
2491
2492         for (;;) {
2493                 bool blc_event = false;
2494
2495                 irq_received = iir != 0;
2496
2497                 /* Can't rely on pipestat interrupt bit in iir as it might
2498                  * have been cleared after the pipestat interrupt was received.
2499                  * It doesn't set the bit in iir again, but it still produces
2500                  * interrupts (for non-MSI).
2501                  */
2502                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2503                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2504                         i915_handle_error(dev, false);
2505
2506                 for_each_pipe(pipe) {
2507                         int reg = PIPESTAT(pipe);
2508                         pipe_stats[pipe] = I915_READ(reg);
2509
2510                         /*
2511                          * Clear the PIPE*STAT regs before the IIR
2512                          */
2513                         if (pipe_stats[pipe] & 0x8000ffff) {
2514                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2515                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2516                                                          pipe_name(pipe));
2517                                 I915_WRITE(reg, pipe_stats[pipe]);
2518                                 irq_received = 1;
2519                         }
2520                 }
2521                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2522
2523                 if (!irq_received)
2524                         break;
2525
2526                 ret = IRQ_HANDLED;
2527
2528                 /* Consume port.  Then clear IIR or we'll miss events */
2529                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2530                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2531
2532                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2533                                   hotplug_status);
2534                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2535                                 queue_work(dev_priv->wq,
2536                                            &dev_priv->hotplug_work);
2537
2538                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2539                         I915_READ(PORT_HOTPLUG_STAT);
2540                 }
2541
2542                 I915_WRITE(IIR, iir);
2543                 new_iir = I915_READ(IIR); /* Flush posted writes */
2544
2545                 if (iir & I915_USER_INTERRUPT)
2546                         notify_ring(dev, &dev_priv->ring[RCS]);
2547                 if (iir & I915_BSD_USER_INTERRUPT)
2548                         notify_ring(dev, &dev_priv->ring[VCS]);
2549
2550                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2551                         intel_prepare_page_flip(dev, 0);
2552
2553                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2554                         intel_prepare_page_flip(dev, 1);
2555
2556                 for_each_pipe(pipe) {
2557                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2558                             drm_handle_vblank(dev, pipe)) {
2559                                 i915_pageflip_stall_check(dev, pipe);
2560                                 intel_finish_page_flip(dev, pipe);
2561                         }
2562
2563                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2564                                 blc_event = true;
2565                 }
2566
2567
2568                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2569                         intel_opregion_asle_intr(dev);
2570
2571                 /* With MSI, interrupts are only generated when iir
2572                  * transitions from zero to nonzero.  If another bit got
2573                  * set while we were handling the existing iir bits, then
2574                  * we would never get another interrupt.
2575                  *
2576                  * This is fine on non-MSI as well, as if we hit this path
2577                  * we avoid exiting the interrupt handler only to generate
2578                  * another one.
2579                  *
2580                  * Note that for MSI this could cause a stray interrupt report
2581                  * if an interrupt landed in the time between writing IIR and
2582                  * the posting read.  This should be rare enough to never
2583                  * trigger the 99% of 100,000 interrupts test for disabling
2584                  * stray interrupts.
2585                  */
2586                 iir = new_iir;
2587         }
2588
2589         i915_update_dri1_breadcrumb(dev);
2590
2591         return ret;
2592 }
2593
2594 static void i965_irq_uninstall(struct drm_device * dev)
2595 {
2596         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2597         int pipe;
2598
2599         if (!dev_priv)
2600                 return;
2601
2602         I915_WRITE(PORT_HOTPLUG_EN, 0);
2603         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2604
2605         I915_WRITE(HWSTAM, 0xffffffff);
2606         for_each_pipe(pipe)
2607                 I915_WRITE(PIPESTAT(pipe), 0);
2608         I915_WRITE(IMR, 0xffffffff);
2609         I915_WRITE(IER, 0x0);
2610
2611         for_each_pipe(pipe)
2612                 I915_WRITE(PIPESTAT(pipe),
2613                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2614         I915_WRITE(IIR, I915_READ(IIR));
2615 }
2616
2617 void intel_irq_init(struct drm_device *dev)
2618 {
2619         struct drm_i915_private *dev_priv = dev->dev_private;
2620
2621         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2622         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2623         INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2624         INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
2625
2626         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2627         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2628         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2629                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2630                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2631         }
2632
2633         if (drm_core_check_feature(dev, DRIVER_MODESET))
2634                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2635         else
2636                 dev->driver->get_vblank_timestamp = NULL;
2637         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2638
2639         if (IS_VALLEYVIEW(dev)) {
2640                 dev->driver->irq_handler = valleyview_irq_handler;
2641                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2642                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2643                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2644                 dev->driver->enable_vblank = valleyview_enable_vblank;
2645                 dev->driver->disable_vblank = valleyview_disable_vblank;
2646         } else if (IS_IVYBRIDGE(dev)) {
2647                 /* Share pre & uninstall handlers with ILK/SNB */
2648                 dev->driver->irq_handler = ivybridge_irq_handler;
2649                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2650                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2651                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2652                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2653                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2654         } else if (IS_HASWELL(dev)) {
2655                 /* Share interrupts handling with IVB */
2656                 dev->driver->irq_handler = ivybridge_irq_handler;
2657                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2658                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2659                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2660                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2661                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2662         } else if (HAS_PCH_SPLIT(dev)) {
2663                 dev->driver->irq_handler = ironlake_irq_handler;
2664                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2665                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2666                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2667                 dev->driver->enable_vblank = ironlake_enable_vblank;
2668                 dev->driver->disable_vblank = ironlake_disable_vblank;
2669         } else {
2670                 if (INTEL_INFO(dev)->gen == 2) {
2671                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2672                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2673                         dev->driver->irq_handler = i8xx_irq_handler;
2674                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2675                 } else if (INTEL_INFO(dev)->gen == 3) {
2676                         /* IIR "flip pending" means done if this bit is set */
2677                         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2678
2679                         dev->driver->irq_preinstall = i915_irq_preinstall;
2680                         dev->driver->irq_postinstall = i915_irq_postinstall;
2681                         dev->driver->irq_uninstall = i915_irq_uninstall;
2682                         dev->driver->irq_handler = i915_irq_handler;
2683                 } else {
2684                         dev->driver->irq_preinstall = i965_irq_preinstall;
2685                         dev->driver->irq_postinstall = i965_irq_postinstall;
2686                         dev->driver->irq_uninstall = i965_irq_uninstall;
2687                         dev->driver->irq_handler = i965_irq_handler;
2688                 }
2689                 dev->driver->enable_vblank = i915_enable_vblank;
2690                 dev->driver->disable_vblank = i915_disable_vblank;
2691         }
2692 }