2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
30 #include "i915_selftest.h"
32 #define GEN_DEFAULT_PIPEOFFSETS \
33 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
34 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
35 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
36 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
37 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
39 #define GEN_CHV_PIPEOFFSETS \
40 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
41 CHV_PIPE_C_OFFSET }, \
42 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
43 CHV_TRANSCODER_C_OFFSET, }, \
44 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
45 CHV_PALETTE_C_OFFSET }
47 #define CURSOR_OFFSETS \
48 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
50 #define IVB_CURSOR_OFFSETS \
51 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
54 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
56 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
58 /* Keep in gen based order, and chronological order within a gen */
59 #define GEN2_FEATURES \
60 .gen = 2, .num_pipes = 1, \
61 .has_overlay = 1, .overlay_needs_physical = 1, \
62 .has_gmch_display = 1, \
63 .hws_needs_physical = 1, \
64 .unfenced_needs_alignment = 1, \
65 .ring_mask = RENDER_RING, \
66 GEN_DEFAULT_PIPEOFFSETS, \
69 static const struct intel_device_info intel_i830_info = {
71 .platform = INTEL_I830,
72 .is_mobile = 1, .cursor_needs_physical = 1,
73 .num_pipes = 2, /* legal, last one wins */
76 static const struct intel_device_info intel_i845g_info = {
78 .platform = INTEL_I845G,
81 static const struct intel_device_info intel_i85x_info = {
83 .platform = INTEL_I85X, .is_mobile = 1,
84 .num_pipes = 2, /* legal, last one wins */
85 .cursor_needs_physical = 1,
89 static const struct intel_device_info intel_i865g_info = {
91 .platform = INTEL_I865G,
94 #define GEN3_FEATURES \
95 .gen = 3, .num_pipes = 2, \
96 .has_gmch_display = 1, \
97 .ring_mask = RENDER_RING, \
98 GEN_DEFAULT_PIPEOFFSETS, \
101 static const struct intel_device_info intel_i915g_info = {
103 .platform = INTEL_I915G, .cursor_needs_physical = 1,
104 .has_overlay = 1, .overlay_needs_physical = 1,
105 .hws_needs_physical = 1,
106 .unfenced_needs_alignment = 1,
109 static const struct intel_device_info intel_i915gm_info = {
111 .platform = INTEL_I915GM,
113 .cursor_needs_physical = 1,
114 .has_overlay = 1, .overlay_needs_physical = 1,
117 .hws_needs_physical = 1,
118 .unfenced_needs_alignment = 1,
121 static const struct intel_device_info intel_i945g_info = {
123 .platform = INTEL_I945G,
124 .has_hotplug = 1, .cursor_needs_physical = 1,
125 .has_overlay = 1, .overlay_needs_physical = 1,
126 .hws_needs_physical = 1,
127 .unfenced_needs_alignment = 1,
130 static const struct intel_device_info intel_i945gm_info = {
132 .platform = INTEL_I945GM, .is_mobile = 1,
133 .has_hotplug = 1, .cursor_needs_physical = 1,
134 .has_overlay = 1, .overlay_needs_physical = 1,
137 .hws_needs_physical = 1,
138 .unfenced_needs_alignment = 1,
141 static const struct intel_device_info intel_g33_info = {
143 .platform = INTEL_G33,
148 static const struct intel_device_info intel_pineview_info = {
150 .platform = INTEL_PINEVIEW, .is_mobile = 1,
155 #define GEN4_FEATURES \
156 .gen = 4, .num_pipes = 2, \
158 .has_gmch_display = 1, \
159 .ring_mask = RENDER_RING, \
160 GEN_DEFAULT_PIPEOFFSETS, \
163 static const struct intel_device_info intel_i965g_info = {
165 .platform = INTEL_I965G,
167 .hws_needs_physical = 1,
170 static const struct intel_device_info intel_i965gm_info = {
172 .platform = INTEL_I965GM,
173 .is_mobile = 1, .has_fbc = 1,
176 .hws_needs_physical = 1,
179 static const struct intel_device_info intel_g45_info = {
181 .platform = INTEL_G45,
183 .ring_mask = RENDER_RING | BSD_RING,
186 static const struct intel_device_info intel_gm45_info = {
188 .platform = INTEL_GM45,
189 .is_mobile = 1, .has_fbc = 1,
192 .ring_mask = RENDER_RING | BSD_RING,
195 #define GEN5_FEATURES \
196 .gen = 5, .num_pipes = 2, \
198 .has_gmbus_irq = 1, \
199 .ring_mask = RENDER_RING | BSD_RING, \
200 GEN_DEFAULT_PIPEOFFSETS, \
203 static const struct intel_device_info intel_ironlake_d_info = {
205 .platform = INTEL_IRONLAKE,
208 static const struct intel_device_info intel_ironlake_m_info = {
210 .platform = INTEL_IRONLAKE,
214 #define GEN6_FEATURES \
215 .gen = 6, .num_pipes = 2, \
218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
222 .has_gmbus_irq = 1, \
223 .has_hw_contexts = 1, \
224 .has_aliasing_ppgtt = 1, \
225 GEN_DEFAULT_PIPEOFFSETS, \
228 static const struct intel_device_info intel_sandybridge_d_info = {
230 .platform = INTEL_SANDYBRIDGE,
233 static const struct intel_device_info intel_sandybridge_m_info = {
235 .platform = INTEL_SANDYBRIDGE,
239 #define GEN7_FEATURES \
240 .gen = 7, .num_pipes = 3, \
243 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
247 .has_gmbus_irq = 1, \
248 .has_hw_contexts = 1, \
249 .has_aliasing_ppgtt = 1, \
250 .has_full_ppgtt = 1, \
251 GEN_DEFAULT_PIPEOFFSETS, \
254 static const struct intel_device_info intel_ivybridge_d_info = {
256 .platform = INTEL_IVYBRIDGE,
260 static const struct intel_device_info intel_ivybridge_m_info = {
262 .platform = INTEL_IVYBRIDGE,
267 static const struct intel_device_info intel_ivybridge_q_info = {
269 .platform = INTEL_IVYBRIDGE,
270 .num_pipes = 0, /* legal, last one wins */
274 static const struct intel_device_info intel_valleyview_info = {
275 .platform = INTEL_VALLEYVIEW,
283 .has_hw_contexts = 1,
284 .has_gmch_display = 1,
286 .has_aliasing_ppgtt = 1,
288 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
289 .display_mmio_offset = VLV_DISPLAY_BASE,
290 GEN_DEFAULT_PIPEOFFSETS,
294 #define HSW_FEATURES \
296 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
300 .has_resource_streamer = 1, \
302 .has_rc6p = 0 /* RC6p removed-by HSW */, \
305 static const struct intel_device_info intel_haswell_info = {
307 .platform = INTEL_HASWELL,
311 #define BDW_FEATURES \
314 .has_logical_ring_contexts = 1, \
315 .has_full_48bit_ppgtt = 1, \
318 static const struct intel_device_info intel_broadwell_info = {
321 .platform = INTEL_BROADWELL,
324 static const struct intel_device_info intel_broadwell_gt3_info = {
327 .platform = INTEL_BROADWELL,
328 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
331 static const struct intel_device_info intel_cherryview_info = {
332 .gen = 8, .num_pipes = 3,
335 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
336 .platform = INTEL_CHERRYVIEW,
337 .has_64bit_reloc = 1,
340 .has_resource_streamer = 1,
343 .has_hw_contexts = 1,
344 .has_logical_ring_contexts = 1,
345 .has_gmch_display = 1,
346 .has_aliasing_ppgtt = 1,
348 .display_mmio_offset = VLV_DISPLAY_BASE,
354 static const struct intel_device_info intel_skylake_info = {
356 .platform = INTEL_SKYLAKE,
363 static const struct intel_device_info intel_skylake_gt3_info = {
365 .platform = INTEL_SKYLAKE,
370 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
373 #define GEN9_LP_FEATURES \
377 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
379 .has_64bit_reloc = 1, \
383 .has_runtime_pm = 1, \
384 .has_pooled_eu = 0, \
386 .has_resource_streamer = 1, \
389 .has_gmbus_irq = 1, \
390 .has_hw_contexts = 1, \
391 .has_logical_ring_contexts = 1, \
393 .has_decoupled_mmio = 1, \
394 .has_aliasing_ppgtt = 1, \
395 .has_full_ppgtt = 1, \
396 .has_full_48bit_ppgtt = 1, \
397 GEN_DEFAULT_PIPEOFFSETS, \
398 IVB_CURSOR_OFFSETS, \
401 static const struct intel_device_info intel_broxton_info = {
403 .platform = INTEL_BROXTON,
407 static const struct intel_device_info intel_geminilake_info = {
409 .platform = INTEL_GEMINILAKE,
410 .is_alpha_support = 1,
412 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
415 static const struct intel_device_info intel_kabylake_info = {
417 .platform = INTEL_KABYLAKE,
424 static const struct intel_device_info intel_kabylake_gt3_info = {
426 .platform = INTEL_KABYLAKE,
431 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
435 * Make sure any device matches here are from most specific to most
436 * general. For example, since the Quanta match is based on the subsystem
437 * and subvendor IDs, we need it to come before the more general IVB
438 * PCI ID matches, otherwise we'll use the wrong info struct above.
440 static const struct pci_device_id pciidlist[] = {
441 INTEL_I830_IDS(&intel_i830_info),
442 INTEL_I845G_IDS(&intel_i845g_info),
443 INTEL_I85X_IDS(&intel_i85x_info),
444 INTEL_I865G_IDS(&intel_i865g_info),
445 INTEL_I915G_IDS(&intel_i915g_info),
446 INTEL_I915GM_IDS(&intel_i915gm_info),
447 INTEL_I945G_IDS(&intel_i945g_info),
448 INTEL_I945GM_IDS(&intel_i945gm_info),
449 INTEL_I965G_IDS(&intel_i965g_info),
450 INTEL_G33_IDS(&intel_g33_info),
451 INTEL_I965GM_IDS(&intel_i965gm_info),
452 INTEL_GM45_IDS(&intel_gm45_info),
453 INTEL_G45_IDS(&intel_g45_info),
454 INTEL_PINEVIEW_IDS(&intel_pineview_info),
455 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
456 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
457 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
458 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
459 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
460 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
461 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
462 INTEL_HSW_IDS(&intel_haswell_info),
463 INTEL_VLV_IDS(&intel_valleyview_info),
464 INTEL_BDW_GT12_IDS(&intel_broadwell_info),
465 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
466 INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
467 INTEL_CHV_IDS(&intel_cherryview_info),
468 INTEL_SKL_GT1_IDS(&intel_skylake_info),
469 INTEL_SKL_GT2_IDS(&intel_skylake_info),
470 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
471 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
472 INTEL_BXT_IDS(&intel_broxton_info),
473 INTEL_GLK_IDS(&intel_geminilake_info),
474 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
475 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
476 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
477 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
480 MODULE_DEVICE_TABLE(pci, pciidlist);
482 static void i915_pci_remove(struct pci_dev *pdev)
484 struct drm_device *dev = pci_get_drvdata(pdev);
486 i915_driver_unload(dev);
490 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
492 struct intel_device_info *intel_info =
493 (struct intel_device_info *) ent->driver_data;
496 if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
497 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
498 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
499 "to enable support in this kernel version, or check for kernel updates.\n");
503 /* Only bind to function 0 of the device. Early generations
504 * used function 1 as a placeholder for multi-head. This causes
505 * us confusion instead, especially on the systems where both
506 * functions have the same PCI-ID!
508 if (PCI_FUNC(pdev->devfn))
512 * apple-gmux is needed on dual GPU MacBook Pro
513 * to probe the panel if we're the inactive GPU.
515 if (vga_switcheroo_client_probe_defer(pdev))
516 return -EPROBE_DEFER;
518 err = i915_driver_load(pdev, ent);
522 err = i915_live_selftests(pdev);
524 i915_pci_remove(pdev);
525 return err > 0 ? -ENOTTY : err;
531 static struct pci_driver i915_pci_driver = {
533 .id_table = pciidlist,
534 .probe = i915_pci_probe,
535 .remove = i915_pci_remove,
536 .driver.pm = &i915_pm_ops,
539 static int __init i915_init(void)
544 err = i915_mock_selftests();
546 return err > 0 ? 0 : err;
549 * Enable KMS by default, unless explicitly overriden by
550 * either the i915.modeset prarameter or by the
551 * vga_text_mode_force boot option.
554 if (i915.modeset == 0)
557 if (vgacon_text_force() && i915.modeset == -1)
561 /* Silently fail loading to not upset userspace. */
562 DRM_DEBUG_DRIVER("KMS disabled.\n");
566 return pci_register_driver(&i915_pci_driver);
569 static void __exit i915_exit(void)
571 if (!i915_pci_driver.driver.owner)
574 pci_unregister_driver(&i915_pci_driver);
577 module_init(i915_init);
578 module_exit(i915_exit);
580 MODULE_AUTHOR("Tungsten Graphics, Inc.");
581 MODULE_AUTHOR("Intel Corporation");
583 MODULE_DESCRIPTION(DRIVER_DESC);
584 MODULE_LICENSE("GPL and additional rights");