1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
34 #define INTEL_GMCH_ENABLED 0x4
35 #define INTEL_GMCH_MEM_MASK 0x1
36 #define INTEL_GMCH_MEM_64M 0x1
37 #define INTEL_GMCH_MEM_128M 0
39 #define INTEL_GMCH_GMS_MASK (0xf << 4)
40 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
48 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
51 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
52 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
53 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
54 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
56 /* PCI config space */
58 #define HPLLCC 0xc0 /* 855 only */
59 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
60 #define GC_CLOCK_133_200 (0 << 0)
61 #define GC_CLOCK_100_200 (1 << 0)
62 #define GC_CLOCK_100_133 (2 << 0)
63 #define GC_CLOCK_166_250 (3 << 0)
64 #define GCFGC 0xf0 /* 915+ only */
65 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
66 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
67 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
68 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
69 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
70 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
71 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
72 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
73 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
74 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
75 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
76 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
77 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
78 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
79 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
80 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
81 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
82 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
83 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
84 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
85 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
86 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
87 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
92 #define VGA_ST01_MDA 0x3ba
93 #define VGA_ST01_CGA 0x3da
95 #define VGA_MSR_WRITE 0x3c2
96 #define VGA_MSR_READ 0x3cc
97 #define VGA_MSR_MEM_EN (1<<1)
98 #define VGA_MSR_CGA_MODE (1<<0)
100 #define VGA_SR_INDEX 0x3c4
101 #define VGA_SR_DATA 0x3c5
103 #define VGA_AR_INDEX 0x3c0
104 #define VGA_AR_VID_EN (1<<5)
105 #define VGA_AR_DATA_WRITE 0x3c0
106 #define VGA_AR_DATA_READ 0x3c1
108 #define VGA_GR_INDEX 0x3ce
109 #define VGA_GR_DATA 0x3cf
111 #define VGA_GR_MEM_READ_MODE_SHIFT 3
112 #define VGA_GR_MEM_READ_MODE_PLANE 1
114 #define VGA_GR_MEM_MODE_MASK 0xc
115 #define VGA_GR_MEM_MODE_SHIFT 2
116 #define VGA_GR_MEM_A0000_AFFFF 0
117 #define VGA_GR_MEM_A0000_BFFFF 1
118 #define VGA_GR_MEM_B0000_B7FFF 2
119 #define VGA_GR_MEM_B0000_BFFFF 3
121 #define VGA_DACMASK 0x3c6
122 #define VGA_DACRX 0x3c7
123 #define VGA_DACWX 0x3c8
124 #define VGA_DACDATA 0x3c9
126 #define VGA_CR_INDEX_MDA 0x3b4
127 #define VGA_CR_DATA_MDA 0x3b5
128 #define VGA_CR_INDEX_CGA 0x3d4
129 #define VGA_CR_DATA_CGA 0x3d5
132 * Memory interface instructions used by the kernel
134 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
136 #define MI_NOOP MI_INSTR(0, 0)
137 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
138 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
139 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
140 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
141 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
142 #define MI_FLUSH MI_INSTR(0x04, 0)
143 #define MI_READ_FLUSH (1 << 0)
144 #define MI_EXE_FLUSH (1 << 1)
145 #define MI_NO_WRITE_FLUSH (1 << 2)
146 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
147 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
148 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
149 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
150 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
151 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
152 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
153 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
154 #define MI_STORE_DWORD_INDEX_SHIFT 2
155 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
156 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
157 #define MI_BATCH_NON_SECURE (1)
158 #define MI_BATCH_NON_SECURE_I965 (1<<8)
159 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
162 * 3D instructions used by the kernel
164 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
166 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
167 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
168 #define SC_UPDATE_SCISSOR (0x1<<1)
169 #define SC_ENABLE_MASK (0x1<<0)
170 #define SC_ENABLE (0x1<<0)
171 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
172 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
173 #define SCI_YMIN_MASK (0xffff<<16)
174 #define SCI_XMIN_MASK (0xffff<<0)
175 #define SCI_YMAX_MASK (0xffff<<16)
176 #define SCI_XMAX_MASK (0xffff<<0)
177 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
178 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
179 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
180 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
181 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
182 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
183 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
184 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
185 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
186 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
187 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
188 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
189 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
190 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
191 #define BLT_DEPTH_8 (0<<24)
192 #define BLT_DEPTH_16_565 (1<<24)
193 #define BLT_DEPTH_16_1555 (2<<24)
194 #define BLT_DEPTH_32 (3<<24)
195 #define BLT_ROP_GXCOPY (0xcc<<16)
196 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
197 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
198 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
199 #define ASYNC_FLIP (1<<22)
200 #define DISPLAY_PLANE_A (0<<20)
201 #define DISPLAY_PLANE_B (1<<20)
206 #define FENCE_REG_830_0 0x2000
207 #define FENCE_REG_945_8 0x3000
208 #define I830_FENCE_START_MASK 0x07f80000
209 #define I830_FENCE_TILING_Y_SHIFT 12
210 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
211 #define I830_FENCE_PITCH_SHIFT 4
212 #define I830_FENCE_REG_VALID (1<<0)
213 #define I915_FENCE_MAX_PITCH_VAL 0x10
214 #define I830_FENCE_MAX_PITCH_VAL 6
215 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
217 #define I915_FENCE_START_MASK 0x0ff00000
218 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
220 #define FENCE_REG_965_0 0x03000
221 #define I965_FENCE_PITCH_SHIFT 2
222 #define I965_FENCE_TILING_Y_SHIFT 1
223 #define I965_FENCE_REG_VALID (1<<0)
224 #define I965_FENCE_MAX_PITCH_VAL 0x0400
227 * Instruction and interrupt control regs
229 #define PGTBL_ER 0x02024
230 #define PRB0_TAIL 0x02030
231 #define PRB0_HEAD 0x02034
232 #define PRB0_START 0x02038
233 #define PRB0_CTL 0x0203c
234 #define TAIL_ADDR 0x001FFFF8
235 #define HEAD_WRAP_COUNT 0xFFE00000
236 #define HEAD_WRAP_ONE 0x00200000
237 #define HEAD_ADDR 0x001FFFFC
238 #define RING_NR_PAGES 0x001FF000
239 #define RING_REPORT_MASK 0x00000006
240 #define RING_REPORT_64K 0x00000002
241 #define RING_REPORT_128K 0x00000004
242 #define RING_NO_REPORT 0x00000000
243 #define RING_VALID_MASK 0x00000001
244 #define RING_VALID 0x00000001
245 #define RING_INVALID 0x00000000
246 #define PRB1_TAIL 0x02040 /* 915+ only */
247 #define PRB1_HEAD 0x02044 /* 915+ only */
248 #define PRB1_START 0x02048 /* 915+ only */
249 #define PRB1_CTL 0x0204c /* 915+ only */
250 #define IPEIR_I965 0x02064
251 #define IPEHR_I965 0x02068
252 #define INSTDONE_I965 0x0206c
253 #define INSTPS 0x02070 /* 965+ only */
254 #define INSTDONE1 0x0207c /* 965+ only */
255 #define ACTHD_I965 0x02074
256 #define HWS_PGA 0x02080
257 #define HWS_ADDRESS_MASK 0xfffff000
258 #define HWS_START_ADDRESS_SHIFT 4
259 #define IPEIR 0x02088
260 #define IPEHR 0x0208c
261 #define INSTDONE 0x02090
262 #define NOPID 0x02094
263 #define HWSTAM 0x02098
264 #define SCPD0 0x0209c /* 915+ only */
269 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
270 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
271 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
272 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
273 #define I915_HWB_OOM_INTERRUPT (1<<13)
274 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
275 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
276 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
277 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
278 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
279 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
280 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
281 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
282 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
283 #define I915_DEBUG_INTERRUPT (1<<2)
284 #define I915_USER_INTERRUPT (1<<1)
285 #define I915_ASLE_INTERRUPT (1<<0)
289 #define GM45_ERROR_PAGE_TABLE (1<<5)
290 #define GM45_ERROR_MEM_PRIV (1<<4)
291 #define I915_ERROR_PAGE_TABLE (1<<4)
292 #define GM45_ERROR_CP_PRIV (1<<3)
293 #define I915_ERROR_MEMORY_REFRESH (1<<1)
294 #define I915_ERROR_INSTRUCTION (1<<0)
295 #define INSTPM 0x020c0
296 #define ACTHD 0x020c8
297 #define FW_BLC 0x020d8
298 #define FW_BLC2 0x020dc
299 #define FW_BLC_SELF 0x020e0 /* 915+ only */
300 #define FW_BLC_SELF_EN (1<<15)
301 #define MM_BURST_LENGTH 0x00700000
302 #define MM_FIFO_WATERMARK 0x0001F000
303 #define LM_BURST_LENGTH 0x00000700
304 #define LM_FIFO_WATERMARK 0x0000001F
305 #define MI_ARB_STATE 0x020e4 /* 915+ only */
306 #define CACHE_MODE_0 0x02120 /* 915+ only */
307 #define CM0_MASK_SHIFT 16
308 #define CM0_IZ_OPT_DISABLE (1<<6)
309 #define CM0_ZR_OPT_DISABLE (1<<5)
310 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
311 #define CM0_COLOR_EVICT_DISABLE (1<<3)
312 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
313 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
314 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
318 * Framebuffer compression (915+ only)
321 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
322 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
323 #define FBC_CONTROL 0x03208
324 #define FBC_CTL_EN (1<<31)
325 #define FBC_CTL_PERIODIC (1<<30)
326 #define FBC_CTL_INTERVAL_SHIFT (16)
327 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
328 #define FBC_CTL_STRIDE_SHIFT (5)
329 #define FBC_CTL_FENCENO (1<<0)
330 #define FBC_COMMAND 0x0320c
331 #define FBC_CMD_COMPRESS (1<<0)
332 #define FBC_STATUS 0x03210
333 #define FBC_STAT_COMPRESSING (1<<31)
334 #define FBC_STAT_COMPRESSED (1<<30)
335 #define FBC_STAT_MODIFIED (1<<29)
336 #define FBC_STAT_CURRENT_LINE (1<<0)
337 #define FBC_CONTROL2 0x03214
338 #define FBC_CTL_FENCE_DBL (0<<4)
339 #define FBC_CTL_IDLE_IMM (0<<2)
340 #define FBC_CTL_IDLE_FULL (1<<2)
341 #define FBC_CTL_IDLE_LINE (2<<2)
342 #define FBC_CTL_IDLE_DEBUG (3<<2)
343 #define FBC_CTL_CPU_FENCE (1<<1)
344 #define FBC_CTL_PLANEA (0<<0)
345 #define FBC_CTL_PLANEB (1<<0)
346 #define FBC_FENCE_OFF 0x0321b
348 #define FBC_LL_SIZE (1536)
361 # define GPIO_CLOCK_DIR_MASK (1 << 0)
362 # define GPIO_CLOCK_DIR_IN (0 << 1)
363 # define GPIO_CLOCK_DIR_OUT (1 << 1)
364 # define GPIO_CLOCK_VAL_MASK (1 << 2)
365 # define GPIO_CLOCK_VAL_OUT (1 << 3)
366 # define GPIO_CLOCK_VAL_IN (1 << 4)
367 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
368 # define GPIO_DATA_DIR_MASK (1 << 8)
369 # define GPIO_DATA_DIR_IN (0 << 9)
370 # define GPIO_DATA_DIR_OUT (1 << 9)
371 # define GPIO_DATA_VAL_MASK (1 << 10)
372 # define GPIO_DATA_VAL_OUT (1 << 11)
373 # define GPIO_DATA_VAL_IN (1 << 12)
374 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
377 * Clock control & power management
382 #define VGA_PD 0x6010
383 #define VGA0_PD_P2_DIV_4 (1 << 7)
384 #define VGA0_PD_P1_DIV_2 (1 << 5)
385 #define VGA0_PD_P1_SHIFT 0
386 #define VGA0_PD_P1_MASK (0x1f << 0)
387 #define VGA1_PD_P2_DIV_4 (1 << 15)
388 #define VGA1_PD_P1_DIV_2 (1 << 13)
389 #define VGA1_PD_P1_SHIFT 8
390 #define VGA1_PD_P1_MASK (0x1f << 8)
391 #define DPLL_A 0x06014
392 #define DPLL_B 0x06018
393 #define DPLL_VCO_ENABLE (1 << 31)
394 #define DPLL_DVO_HIGH_SPEED (1 << 30)
395 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
396 #define DPLL_VGA_MODE_DIS (1 << 28)
397 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
398 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
399 #define DPLL_MODE_MASK (3 << 26)
400 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
401 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
402 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
403 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
404 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
405 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
406 #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
408 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
409 #define I915_CRC_ERROR_ENABLE (1UL<<29)
410 #define I915_CRC_DONE_ENABLE (1UL<<28)
411 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
412 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
413 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
414 #define I915_DPST_EVENT_ENABLE (1UL<<23)
415 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
416 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
417 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
418 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
419 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
420 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
421 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
422 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
423 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
424 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
425 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
426 #define I915_DPST_EVENT_STATUS (1UL<<7)
427 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
428 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
429 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
430 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
431 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
432 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
434 #define SRX_INDEX 0x3c4
435 #define SRX_DATA 0x3c5
437 #define SR01_SCREEN_OFF (1<<5)
440 #define PPCR_ON (1<<0)
443 #define DVOB_ON (1<<31)
445 #define DVOC_ON (1<<31)
447 #define LVDS_ON (1<<31)
450 #define ADPA_DPMS_MASK (~(3<<10))
451 #define ADPA_DPMS_ON (0<<10)
452 #define ADPA_DPMS_SUSPEND (1<<10)
453 #define ADPA_DPMS_STANDBY (2<<10)
454 #define ADPA_DPMS_OFF (3<<10)
456 #define RING_TAIL 0x00
457 #define TAIL_ADDR 0x001FFFF8
458 #define RING_HEAD 0x04
459 #define HEAD_WRAP_COUNT 0xFFE00000
460 #define HEAD_WRAP_ONE 0x00200000
461 #define HEAD_ADDR 0x001FFFFC
462 #define RING_START 0x08
463 #define START_ADDR 0xFFFFF000
464 #define RING_LEN 0x0C
465 #define RING_NR_PAGES 0x001FF000
466 #define RING_REPORT_MASK 0x00000006
467 #define RING_REPORT_64K 0x00000002
468 #define RING_REPORT_128K 0x00000004
469 #define RING_NO_REPORT 0x00000000
470 #define RING_VALID_MASK 0x00000001
471 #define RING_VALID 0x00000001
472 #define RING_INVALID 0x00000000
474 /* Scratch pad debug 0 reg:
476 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
478 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
479 * this field (only one bit may be set).
481 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
482 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
483 #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
484 /* i830, required in DVO non-gang */
485 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
486 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
487 #define PLL_REF_INPUT_DREFCLK (0 << 13)
488 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
489 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
490 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
491 #define PLL_REF_INPUT_MASK (3 << 13)
492 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
494 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
495 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
496 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
497 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
498 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
501 * Parallel to Serial Load Pulse phase selection.
502 * Selects the phase for the 10X DPLL clock for the PCIe
503 * digital display port. The range is 4 to 13; 10 or more
504 * is just a flip delay. The default is 6
506 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
507 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
509 * SDVO multiplier for 945G/GM. Not used on 965.
511 #define SDVO_MULTIPLIER_MASK 0x000000ff
512 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
513 #define SDVO_MULTIPLIER_SHIFT_VGA 0
514 #define DPLL_A_MD 0x0601c /* 965+ only */
516 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
518 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
520 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
521 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
522 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
523 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
524 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
526 * SDVO/UDI pixel multiplier.
528 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
529 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
530 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
531 * dummy bytes in the datastream at an increased clock rate, with both sides of
532 * the link knowing how many bytes are fill.
534 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
535 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
536 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
537 * through an SDVO command.
539 * This register field has values of multiplication factor minus 1, with
540 * a maximum multiplier of 5 for SDVO.
542 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
543 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
545 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
546 * This best be set to the default value (3) or the CRT won't work. No,
547 * I don't entirely understand what this does...
549 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
550 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
551 #define DPLL_B_MD 0x06020 /* 965+ only */
556 #define FP_N_DIV_MASK 0x003f0000
557 #define FP_N_IGD_DIV_MASK 0x00ff0000
558 #define FP_N_DIV_SHIFT 16
559 #define FP_M1_DIV_MASK 0x00003f00
560 #define FP_M1_DIV_SHIFT 8
561 #define FP_M2_DIV_MASK 0x0000003f
562 #define FP_M2_IGD_DIV_MASK 0x000000ff
563 #define FP_M2_DIV_SHIFT 0
564 #define DPLL_TEST 0x606c
565 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
566 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
567 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
568 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
569 #define DPLLB_TEST_N_BYPASS (1 << 19)
570 #define DPLLB_TEST_M_BYPASS (1 << 18)
571 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
572 #define DPLLA_TEST_N_BYPASS (1 << 3)
573 #define DPLLA_TEST_M_BYPASS (1 << 2)
574 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
575 #define D_STATE 0x6104
576 #define DSTATE_PLL_D3_OFF (1<<3)
577 #define DSTATE_GFX_CLOCK_GATING (1<<1)
578 #define DSTATE_DOT_CLOCK_GATING (1<<0)
579 #define DSPCLK_GATE_D 0x6200
580 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
581 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
582 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
583 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
584 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
585 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
586 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
587 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
588 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
589 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
590 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
591 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
592 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
593 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
594 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
595 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
596 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
597 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
598 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
599 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
600 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
601 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
602 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
603 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
604 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
605 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
606 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
607 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
609 * This bit must be set on the 830 to prevent hangs when turning off the
612 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
613 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
614 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
615 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
616 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
618 #define RENCLK_GATE_D1 0x6204
619 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
620 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
621 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
622 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
623 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
624 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
625 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
626 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
627 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
628 /** This bit must be unset on 855,865 */
629 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
630 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
631 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
632 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
633 /** This bit must be set on 855,865. */
634 # define SV_CLOCK_GATE_DISABLE (1 << 0)
635 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
636 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
637 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
638 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
639 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
640 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
641 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
642 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
643 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
644 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
645 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
646 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
647 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
648 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
649 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
650 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
651 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
653 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
654 /** This bit must always be set on 965G/965GM */
655 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
656 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
657 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
658 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
659 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
660 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
661 /** This bit must always be set on 965G */
662 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
663 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
664 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
665 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
666 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
667 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
668 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
669 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
670 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
671 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
672 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
673 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
674 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
675 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
676 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
677 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
678 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
679 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
680 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
682 #define RENCLK_GATE_D2 0x6208
683 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
684 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
685 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
686 #define RAMCLK_GATE_D 0x6210 /* CRL only */
687 #define DEUC 0x6214 /* CRL only */
693 #define PALETTE_A 0x0a000
694 #define PALETTE_B 0x0a800
701 * This mirrors the MCHBAR MMIO space whose location is determined by
702 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
703 * every way. It is not accessible from the CP register read instructions.
706 #define MCHBAR_MIRROR_BASE 0x10000
708 /** 915-945 and GM965 MCH register controlling DRAM channel access */
710 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
711 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
712 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
713 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
714 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
715 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
717 /** 965 MCH register controlling DRAM channel configuration */
718 #define C0DRB3 0x10206
719 #define C1DRB3 0x10606
721 /* Clocking configuration register */
722 #define CLKCFG 0x10c00
723 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
724 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
725 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
726 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
727 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
728 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
729 /* Note, below two are guess */
730 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
731 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
732 #define CLKCFG_FSB_MASK (7 << 0)
733 #define CLKCFG_MEM_533 (1 << 4)
734 #define CLKCFG_MEM_667 (2 << 4)
735 #define CLKCFG_MEM_800 (3 << 4)
736 #define CLKCFG_MEM_MASK (7 << 4)
738 /** GM965 GM45 render standby register */
739 #define MCHBAR_RENDER_STANDBY 0x111B8
741 #define PEG_BAND_GAP_DATA 0x14d68
747 #define OVADD 0x30000
748 #define DOVSTA 0x30008
749 #define OC_BUF (0x3<<20)
750 #define OGAMC5 0x30010
751 #define OGAMC4 0x30014
752 #define OGAMC3 0x30018
753 #define OGAMC2 0x3001c
754 #define OGAMC1 0x30020
755 #define OGAMC0 0x30024
758 * Display engine regs
761 /* Pipe A timing regs */
762 #define HTOTAL_A 0x60000
763 #define HBLANK_A 0x60004
764 #define HSYNC_A 0x60008
765 #define VTOTAL_A 0x6000c
766 #define VBLANK_A 0x60010
767 #define VSYNC_A 0x60014
768 #define PIPEASRC 0x6001c
769 #define BCLRPAT_A 0x60020
771 /* Pipe B timing regs */
772 #define HTOTAL_B 0x61000
773 #define HBLANK_B 0x61004
774 #define HSYNC_B 0x61008
775 #define VTOTAL_B 0x6100c
776 #define VBLANK_B 0x61010
777 #define VSYNC_B 0x61014
778 #define PIPEBSRC 0x6101c
779 #define BCLRPAT_B 0x61020
781 /* VGA port control */
783 #define ADPA_DAC_ENABLE (1<<31)
784 #define ADPA_DAC_DISABLE 0
785 #define ADPA_PIPE_SELECT_MASK (1<<30)
786 #define ADPA_PIPE_A_SELECT 0
787 #define ADPA_PIPE_B_SELECT (1<<30)
788 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
789 #define ADPA_SETS_HVPOLARITY 0
790 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
791 #define ADPA_VSYNC_CNTL_ENABLE 0
792 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
793 #define ADPA_HSYNC_CNTL_ENABLE 0
794 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
795 #define ADPA_VSYNC_ACTIVE_LOW 0
796 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
797 #define ADPA_HSYNC_ACTIVE_LOW 0
798 #define ADPA_DPMS_MASK (~(3<<10))
799 #define ADPA_DPMS_ON (0<<10)
800 #define ADPA_DPMS_SUSPEND (1<<10)
801 #define ADPA_DPMS_STANDBY (2<<10)
802 #define ADPA_DPMS_OFF (3<<10)
804 /* Hotplug control (945+ only) */
805 #define PORT_HOTPLUG_EN 0x61110
806 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
807 #define DPB_HOTPLUG_INT_EN (1 << 29)
808 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
809 #define DPC_HOTPLUG_INT_EN (1 << 28)
810 #define HDMID_HOTPLUG_INT_EN (1 << 27)
811 #define DPD_HOTPLUG_INT_EN (1 << 27)
812 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
813 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
814 #define TV_HOTPLUG_INT_EN (1 << 18)
815 #define CRT_EOS_INT_EN (1 << 10)
816 #define CRT_HOTPLUG_INT_EN (1 << 9)
817 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
818 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
819 /* must use period 64 on GM45 according to docs */
820 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
821 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
822 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
823 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
824 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
825 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
826 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
827 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
828 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
829 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
830 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
831 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
832 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
833 #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f
834 #define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \
835 HDMIC_HOTPLUG_INT_EN | \
836 HDMID_HOTPLUG_INT_EN | \
837 SDVOB_HOTPLUG_INT_EN | \
838 SDVOC_HOTPLUG_INT_EN | \
839 TV_HOTPLUG_INT_EN | \
843 #define PORT_HOTPLUG_STAT 0x61114
844 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
845 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
846 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
847 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
848 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
849 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
850 #define CRT_EOS_INT_STATUS (1 << 12)
851 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
852 #define TV_HOTPLUG_INT_STATUS (1 << 10)
853 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
854 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
855 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
856 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
857 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
858 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
860 /* SDVO port control */
861 #define SDVOB 0x61140
862 #define SDVOC 0x61160
863 #define SDVO_ENABLE (1 << 31)
864 #define SDVO_PIPE_B_SELECT (1 << 30)
865 #define SDVO_STALL_SELECT (1 << 29)
866 #define SDVO_INTERRUPT_ENABLE (1 << 26)
868 * 915G/GM SDVO pixel multiplier.
870 * Programmed value is multiplier - 1, up to 5x.
872 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
874 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
875 #define SDVO_PORT_MULTIPLY_SHIFT 23
876 #define SDVO_PHASE_SELECT_MASK (15 << 19)
877 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
878 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
879 #define SDVOC_GANG_MODE (1 << 16)
880 #define SDVO_ENCODING_SDVO (0x0 << 10)
881 #define SDVO_ENCODING_HDMI (0x2 << 10)
882 /** Requird for HDMI operation */
883 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
884 #define SDVO_BORDER_ENABLE (1 << 7)
885 #define SDVO_AUDIO_ENABLE (1 << 6)
886 /** New with 965, default is to be set */
887 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
888 /** New with 965, default is to be set */
889 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
890 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
891 #define SDVO_DETECTED (1 << 2)
892 /* Bits to be preserved when writing */
893 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
894 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
896 /* DVO port control */
900 #define DVO_ENABLE (1 << 31)
901 #define DVO_PIPE_B_SELECT (1 << 30)
902 #define DVO_PIPE_STALL_UNUSED (0 << 28)
903 #define DVO_PIPE_STALL (1 << 28)
904 #define DVO_PIPE_STALL_TV (2 << 28)
905 #define DVO_PIPE_STALL_MASK (3 << 28)
906 #define DVO_USE_VGA_SYNC (1 << 15)
907 #define DVO_DATA_ORDER_I740 (0 << 14)
908 #define DVO_DATA_ORDER_FP (1 << 14)
909 #define DVO_VSYNC_DISABLE (1 << 11)
910 #define DVO_HSYNC_DISABLE (1 << 10)
911 #define DVO_VSYNC_TRISTATE (1 << 9)
912 #define DVO_HSYNC_TRISTATE (1 << 8)
913 #define DVO_BORDER_ENABLE (1 << 7)
914 #define DVO_DATA_ORDER_GBRG (1 << 6)
915 #define DVO_DATA_ORDER_RGGB (0 << 6)
916 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
917 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
918 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
919 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
920 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
921 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
922 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
923 #define DVO_PRESERVE_MASK (0x7<<24)
924 #define DVOA_SRCDIM 0x61124
925 #define DVOB_SRCDIM 0x61144
926 #define DVOC_SRCDIM 0x61164
927 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
928 #define DVO_SRCDIM_VERTICAL_SHIFT 0
930 /* LVDS port control */
933 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
934 * the DPLL semantics change when the LVDS is assigned to that pipe.
936 #define LVDS_PORT_EN (1 << 31)
937 /* Selects pipe B for LVDS data. Must be set on pre-965. */
938 #define LVDS_PIPEB_SELECT (1 << 30)
940 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
943 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
944 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
945 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
947 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
948 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
951 #define LVDS_A3_POWER_MASK (3 << 6)
952 #define LVDS_A3_POWER_DOWN (0 << 6)
953 #define LVDS_A3_POWER_UP (3 << 6)
955 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
958 #define LVDS_CLKB_POWER_MASK (3 << 4)
959 #define LVDS_CLKB_POWER_DOWN (0 << 4)
960 #define LVDS_CLKB_POWER_UP (3 << 4)
962 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
963 * setting for whether we are in dual-channel mode. The B3 pair will
964 * additionally only be powered up when LVDS_A3_POWER_UP is set.
966 #define LVDS_B0B3_POWER_MASK (3 << 2)
967 #define LVDS_B0B3_POWER_DOWN (0 << 2)
968 #define LVDS_B0B3_POWER_UP (3 << 2)
970 /* Panel power sequencing */
971 #define PP_STATUS 0x61200
972 #define PP_ON (1 << 31)
974 * Indicates that all dependencies of the panel are on:
978 * - LVDS/DVOB/DVOC on
980 #define PP_READY (1 << 30)
981 #define PP_SEQUENCE_NONE (0 << 28)
982 #define PP_SEQUENCE_ON (1 << 28)
983 #define PP_SEQUENCE_OFF (2 << 28)
984 #define PP_SEQUENCE_MASK 0x30000000
985 #define PP_CONTROL 0x61204
986 #define POWER_TARGET_ON (1 << 0)
987 #define PP_ON_DELAYS 0x61208
988 #define PP_OFF_DELAYS 0x6120c
989 #define PP_DIVISOR 0x61210
992 #define PFIT_CONTROL 0x61230
993 #define PFIT_ENABLE (1 << 31)
994 #define PFIT_PIPE_MASK (3 << 29)
995 #define PFIT_PIPE_SHIFT 29
996 #define VERT_INTERP_DISABLE (0 << 10)
997 #define VERT_INTERP_BILINEAR (1 << 10)
998 #define VERT_INTERP_MASK (3 << 10)
999 #define VERT_AUTO_SCALE (1 << 9)
1000 #define HORIZ_INTERP_DISABLE (0 << 6)
1001 #define HORIZ_INTERP_BILINEAR (1 << 6)
1002 #define HORIZ_INTERP_MASK (3 << 6)
1003 #define HORIZ_AUTO_SCALE (1 << 5)
1004 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1005 #define PFIT_FILTER_FUZZY (0 << 24)
1006 #define PFIT_SCALING_AUTO (0 << 26)
1007 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1008 #define PFIT_SCALING_PILLAR (2 << 26)
1009 #define PFIT_SCALING_LETTER (3 << 26)
1010 #define PFIT_PGM_RATIOS 0x61234
1011 #define PFIT_VERT_SCALE_MASK 0xfff00000
1012 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1014 #define PFIT_VERT_SCALE_SHIFT 20
1015 #define PFIT_VERT_SCALE_MASK 0xfff00000
1016 #define PFIT_HORIZ_SCALE_SHIFT 4
1017 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1019 #define PFIT_VERT_SCALE_SHIFT_965 16
1020 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1021 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1022 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1024 #define PFIT_AUTO_RATIOS 0x61238
1026 /* Backlight control */
1027 #define BLC_PWM_CTL 0x61254
1028 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1029 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1030 #define BLM_COMBINATION_MODE (1 << 30)
1032 * This is the most significant 15 bits of the number of backlight cycles in a
1033 * complete cycle of the modulated backlight control.
1035 * The actual value is this field multiplied by two.
1037 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1038 #define BLM_LEGACY_MODE (1 << 16)
1040 * This is the number of cycles out of the backlight modulation cycle for which
1041 * the backlight is on.
1043 * This field must be no greater than the number of cycles in the complete
1044 * backlight modulation cycle.
1046 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1047 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1049 /* TV port control */
1050 #define TV_CTL 0x68000
1051 /** Enables the TV encoder */
1052 # define TV_ENC_ENABLE (1 << 31)
1053 /** Sources the TV encoder input from pipe B instead of A. */
1054 # define TV_ENC_PIPEB_SELECT (1 << 30)
1055 /** Outputs composite video (DAC A only) */
1056 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1057 /** Outputs SVideo video (DAC B/C) */
1058 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1059 /** Outputs Component video (DAC A/B/C) */
1060 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1061 /** Outputs Composite and SVideo (DAC A/B/C) */
1062 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1063 # define TV_TRILEVEL_SYNC (1 << 21)
1064 /** Enables slow sync generation (945GM only) */
1065 # define TV_SLOW_SYNC (1 << 20)
1066 /** Selects 4x oversampling for 480i and 576p */
1067 # define TV_OVERSAMPLE_4X (0 << 18)
1068 /** Selects 2x oversampling for 720p and 1080i */
1069 # define TV_OVERSAMPLE_2X (1 << 18)
1070 /** Selects no oversampling for 1080p */
1071 # define TV_OVERSAMPLE_NONE (2 << 18)
1072 /** Selects 8x oversampling */
1073 # define TV_OVERSAMPLE_8X (3 << 18)
1074 /** Selects progressive mode rather than interlaced */
1075 # define TV_PROGRESSIVE (1 << 17)
1076 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1077 # define TV_PAL_BURST (1 << 16)
1078 /** Field for setting delay of Y compared to C */
1079 # define TV_YC_SKEW_MASK (7 << 12)
1080 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1081 # define TV_ENC_SDP_FIX (1 << 11)
1083 * Enables a fix for the 915GM only.
1085 * Not sure what it does.
1087 # define TV_ENC_C0_FIX (1 << 10)
1088 /** Bits that must be preserved by software */
1089 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1090 # define TV_FUSE_STATE_MASK (3 << 4)
1091 /** Read-only state that reports all features enabled */
1092 # define TV_FUSE_STATE_ENABLED (0 << 4)
1093 /** Read-only state that reports that Macrovision is disabled in hardware*/
1094 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1095 /** Read-only state that reports that TV-out is disabled in hardware. */
1096 # define TV_FUSE_STATE_DISABLED (2 << 4)
1097 /** Normal operation */
1098 # define TV_TEST_MODE_NORMAL (0 << 0)
1099 /** Encoder test pattern 1 - combo pattern */
1100 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1101 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1102 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1103 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1104 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1105 /** Encoder test pattern 4 - random noise */
1106 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1107 /** Encoder test pattern 5 - linear color ramps */
1108 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1110 * This test mode forces the DACs to 50% of full output.
1112 * This is used for load detection in combination with TVDAC_SENSE_MASK
1114 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1115 # define TV_TEST_MODE_MASK (7 << 0)
1117 #define TV_DAC 0x68004
1119 * Reports that DAC state change logic has reported change (RO).
1121 * This gets cleared when TV_DAC_STATE_EN is cleared
1123 # define TVDAC_STATE_CHG (1 << 31)
1124 # define TVDAC_SENSE_MASK (7 << 28)
1125 /** Reports that DAC A voltage is above the detect threshold */
1126 # define TVDAC_A_SENSE (1 << 30)
1127 /** Reports that DAC B voltage is above the detect threshold */
1128 # define TVDAC_B_SENSE (1 << 29)
1129 /** Reports that DAC C voltage is above the detect threshold */
1130 # define TVDAC_C_SENSE (1 << 28)
1132 * Enables DAC state detection logic, for load-based TV detection.
1134 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1135 * to off, for load detection to work.
1137 # define TVDAC_STATE_CHG_EN (1 << 27)
1138 /** Sets the DAC A sense value to high */
1139 # define TVDAC_A_SENSE_CTL (1 << 26)
1140 /** Sets the DAC B sense value to high */
1141 # define TVDAC_B_SENSE_CTL (1 << 25)
1142 /** Sets the DAC C sense value to high */
1143 # define TVDAC_C_SENSE_CTL (1 << 24)
1144 /** Overrides the ENC_ENABLE and DAC voltage levels */
1145 # define DAC_CTL_OVERRIDE (1 << 7)
1146 /** Sets the slew rate. Must be preserved in software */
1147 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1148 # define DAC_A_1_3_V (0 << 4)
1149 # define DAC_A_1_1_V (1 << 4)
1150 # define DAC_A_0_7_V (2 << 4)
1151 # define DAC_A_MASK (3 << 4)
1152 # define DAC_B_1_3_V (0 << 2)
1153 # define DAC_B_1_1_V (1 << 2)
1154 # define DAC_B_0_7_V (2 << 2)
1155 # define DAC_B_MASK (3 << 2)
1156 # define DAC_C_1_3_V (0 << 0)
1157 # define DAC_C_1_1_V (1 << 0)
1158 # define DAC_C_0_7_V (2 << 0)
1159 # define DAC_C_MASK (3 << 0)
1162 * CSC coefficients are stored in a floating point format with 9 bits of
1163 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1164 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1165 * -1 (0x3) being the only legal negative value.
1167 #define TV_CSC_Y 0x68010
1168 # define TV_RY_MASK 0x07ff0000
1169 # define TV_RY_SHIFT 16
1170 # define TV_GY_MASK 0x00000fff
1171 # define TV_GY_SHIFT 0
1173 #define TV_CSC_Y2 0x68014
1174 # define TV_BY_MASK 0x07ff0000
1175 # define TV_BY_SHIFT 16
1177 * Y attenuation for component video.
1179 * Stored in 1.9 fixed point.
1181 # define TV_AY_MASK 0x000003ff
1182 # define TV_AY_SHIFT 0
1184 #define TV_CSC_U 0x68018
1185 # define TV_RU_MASK 0x07ff0000
1186 # define TV_RU_SHIFT 16
1187 # define TV_GU_MASK 0x000007ff
1188 # define TV_GU_SHIFT 0
1190 #define TV_CSC_U2 0x6801c
1191 # define TV_BU_MASK 0x07ff0000
1192 # define TV_BU_SHIFT 16
1194 * U attenuation for component video.
1196 * Stored in 1.9 fixed point.
1198 # define TV_AU_MASK 0x000003ff
1199 # define TV_AU_SHIFT 0
1201 #define TV_CSC_V 0x68020
1202 # define TV_RV_MASK 0x0fff0000
1203 # define TV_RV_SHIFT 16
1204 # define TV_GV_MASK 0x000007ff
1205 # define TV_GV_SHIFT 0
1207 #define TV_CSC_V2 0x68024
1208 # define TV_BV_MASK 0x07ff0000
1209 # define TV_BV_SHIFT 16
1211 * V attenuation for component video.
1213 * Stored in 1.9 fixed point.
1215 # define TV_AV_MASK 0x000007ff
1216 # define TV_AV_SHIFT 0
1218 #define TV_CLR_KNOBS 0x68028
1219 /** 2s-complement brightness adjustment */
1220 # define TV_BRIGHTNESS_MASK 0xff000000
1221 # define TV_BRIGHTNESS_SHIFT 24
1222 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1223 # define TV_CONTRAST_MASK 0x00ff0000
1224 # define TV_CONTRAST_SHIFT 16
1225 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1226 # define TV_SATURATION_MASK 0x0000ff00
1227 # define TV_SATURATION_SHIFT 8
1228 /** Hue adjustment, as an integer phase angle in degrees */
1229 # define TV_HUE_MASK 0x000000ff
1230 # define TV_HUE_SHIFT 0
1232 #define TV_CLR_LEVEL 0x6802c
1233 /** Controls the DAC level for black */
1234 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1235 # define TV_BLACK_LEVEL_SHIFT 16
1236 /** Controls the DAC level for blanking */
1237 # define TV_BLANK_LEVEL_MASK 0x000001ff
1238 # define TV_BLANK_LEVEL_SHIFT 0
1240 #define TV_H_CTL_1 0x68030
1241 /** Number of pixels in the hsync. */
1242 # define TV_HSYNC_END_MASK 0x1fff0000
1243 # define TV_HSYNC_END_SHIFT 16
1244 /** Total number of pixels minus one in the line (display and blanking). */
1245 # define TV_HTOTAL_MASK 0x00001fff
1246 # define TV_HTOTAL_SHIFT 0
1248 #define TV_H_CTL_2 0x68034
1249 /** Enables the colorburst (needed for non-component color) */
1250 # define TV_BURST_ENA (1 << 31)
1251 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1252 # define TV_HBURST_START_SHIFT 16
1253 # define TV_HBURST_START_MASK 0x1fff0000
1254 /** Length of the colorburst */
1255 # define TV_HBURST_LEN_SHIFT 0
1256 # define TV_HBURST_LEN_MASK 0x0001fff
1258 #define TV_H_CTL_3 0x68038
1259 /** End of hblank, measured in pixels minus one from start of hsync */
1260 # define TV_HBLANK_END_SHIFT 16
1261 # define TV_HBLANK_END_MASK 0x1fff0000
1262 /** Start of hblank, measured in pixels minus one from start of hsync */
1263 # define TV_HBLANK_START_SHIFT 0
1264 # define TV_HBLANK_START_MASK 0x0001fff
1266 #define TV_V_CTL_1 0x6803c
1268 # define TV_NBR_END_SHIFT 16
1269 # define TV_NBR_END_MASK 0x07ff0000
1271 # define TV_VI_END_F1_SHIFT 8
1272 # define TV_VI_END_F1_MASK 0x00003f00
1274 # define TV_VI_END_F2_SHIFT 0
1275 # define TV_VI_END_F2_MASK 0x0000003f
1277 #define TV_V_CTL_2 0x68040
1278 /** Length of vsync, in half lines */
1279 # define TV_VSYNC_LEN_MASK 0x07ff0000
1280 # define TV_VSYNC_LEN_SHIFT 16
1281 /** Offset of the start of vsync in field 1, measured in one less than the
1282 * number of half lines.
1284 # define TV_VSYNC_START_F1_MASK 0x00007f00
1285 # define TV_VSYNC_START_F1_SHIFT 8
1287 * Offset of the start of vsync in field 2, measured in one less than the
1288 * number of half lines.
1290 # define TV_VSYNC_START_F2_MASK 0x0000007f
1291 # define TV_VSYNC_START_F2_SHIFT 0
1293 #define TV_V_CTL_3 0x68044
1294 /** Enables generation of the equalization signal */
1295 # define TV_EQUAL_ENA (1 << 31)
1296 /** Length of vsync, in half lines */
1297 # define TV_VEQ_LEN_MASK 0x007f0000
1298 # define TV_VEQ_LEN_SHIFT 16
1299 /** Offset of the start of equalization in field 1, measured in one less than
1300 * the number of half lines.
1302 # define TV_VEQ_START_F1_MASK 0x0007f00
1303 # define TV_VEQ_START_F1_SHIFT 8
1305 * Offset of the start of equalization in field 2, measured in one less than
1306 * the number of half lines.
1308 # define TV_VEQ_START_F2_MASK 0x000007f
1309 # define TV_VEQ_START_F2_SHIFT 0
1311 #define TV_V_CTL_4 0x68048
1313 * Offset to start of vertical colorburst, measured in one less than the
1314 * number of lines from vertical start.
1316 # define TV_VBURST_START_F1_MASK 0x003f0000
1317 # define TV_VBURST_START_F1_SHIFT 16
1319 * Offset to the end of vertical colorburst, measured in one less than the
1320 * number of lines from the start of NBR.
1322 # define TV_VBURST_END_F1_MASK 0x000000ff
1323 # define TV_VBURST_END_F1_SHIFT 0
1325 #define TV_V_CTL_5 0x6804c
1327 * Offset to start of vertical colorburst, measured in one less than the
1328 * number of lines from vertical start.
1330 # define TV_VBURST_START_F2_MASK 0x003f0000
1331 # define TV_VBURST_START_F2_SHIFT 16
1333 * Offset to the end of vertical colorburst, measured in one less than the
1334 * number of lines from the start of NBR.
1336 # define TV_VBURST_END_F2_MASK 0x000000ff
1337 # define TV_VBURST_END_F2_SHIFT 0
1339 #define TV_V_CTL_6 0x68050
1341 * Offset to start of vertical colorburst, measured in one less than the
1342 * number of lines from vertical start.
1344 # define TV_VBURST_START_F3_MASK 0x003f0000
1345 # define TV_VBURST_START_F3_SHIFT 16
1347 * Offset to the end of vertical colorburst, measured in one less than the
1348 * number of lines from the start of NBR.
1350 # define TV_VBURST_END_F3_MASK 0x000000ff
1351 # define TV_VBURST_END_F3_SHIFT 0
1353 #define TV_V_CTL_7 0x68054
1355 * Offset to start of vertical colorburst, measured in one less than the
1356 * number of lines from vertical start.
1358 # define TV_VBURST_START_F4_MASK 0x003f0000
1359 # define TV_VBURST_START_F4_SHIFT 16
1361 * Offset to the end of vertical colorburst, measured in one less than the
1362 * number of lines from the start of NBR.
1364 # define TV_VBURST_END_F4_MASK 0x000000ff
1365 # define TV_VBURST_END_F4_SHIFT 0
1367 #define TV_SC_CTL_1 0x68060
1368 /** Turns on the first subcarrier phase generation DDA */
1369 # define TV_SC_DDA1_EN (1 << 31)
1370 /** Turns on the first subcarrier phase generation DDA */
1371 # define TV_SC_DDA2_EN (1 << 30)
1372 /** Turns on the first subcarrier phase generation DDA */
1373 # define TV_SC_DDA3_EN (1 << 29)
1374 /** Sets the subcarrier DDA to reset frequency every other field */
1375 # define TV_SC_RESET_EVERY_2 (0 << 24)
1376 /** Sets the subcarrier DDA to reset frequency every fourth field */
1377 # define TV_SC_RESET_EVERY_4 (1 << 24)
1378 /** Sets the subcarrier DDA to reset frequency every eighth field */
1379 # define TV_SC_RESET_EVERY_8 (2 << 24)
1380 /** Sets the subcarrier DDA to never reset the frequency */
1381 # define TV_SC_RESET_NEVER (3 << 24)
1382 /** Sets the peak amplitude of the colorburst.*/
1383 # define TV_BURST_LEVEL_MASK 0x00ff0000
1384 # define TV_BURST_LEVEL_SHIFT 16
1385 /** Sets the increment of the first subcarrier phase generation DDA */
1386 # define TV_SCDDA1_INC_MASK 0x00000fff
1387 # define TV_SCDDA1_INC_SHIFT 0
1389 #define TV_SC_CTL_2 0x68064
1390 /** Sets the rollover for the second subcarrier phase generation DDA */
1391 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1392 # define TV_SCDDA2_SIZE_SHIFT 16
1393 /** Sets the increent of the second subcarrier phase generation DDA */
1394 # define TV_SCDDA2_INC_MASK 0x00007fff
1395 # define TV_SCDDA2_INC_SHIFT 0
1397 #define TV_SC_CTL_3 0x68068
1398 /** Sets the rollover for the third subcarrier phase generation DDA */
1399 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1400 # define TV_SCDDA3_SIZE_SHIFT 16
1401 /** Sets the increent of the third subcarrier phase generation DDA */
1402 # define TV_SCDDA3_INC_MASK 0x00007fff
1403 # define TV_SCDDA3_INC_SHIFT 0
1405 #define TV_WIN_POS 0x68070
1406 /** X coordinate of the display from the start of horizontal active */
1407 # define TV_XPOS_MASK 0x1fff0000
1408 # define TV_XPOS_SHIFT 16
1409 /** Y coordinate of the display from the start of vertical active (NBR) */
1410 # define TV_YPOS_MASK 0x00000fff
1411 # define TV_YPOS_SHIFT 0
1413 #define TV_WIN_SIZE 0x68074
1414 /** Horizontal size of the display window, measured in pixels*/
1415 # define TV_XSIZE_MASK 0x1fff0000
1416 # define TV_XSIZE_SHIFT 16
1418 * Vertical size of the display window, measured in pixels.
1420 * Must be even for interlaced modes.
1422 # define TV_YSIZE_MASK 0x00000fff
1423 # define TV_YSIZE_SHIFT 0
1425 #define TV_FILTER_CTL_1 0x68080
1427 * Enables automatic scaling calculation.
1429 * If set, the rest of the registers are ignored, and the calculated values can
1430 * be read back from the register.
1432 # define TV_AUTO_SCALE (1 << 31)
1434 * Disables the vertical filter.
1436 * This is required on modes more than 1024 pixels wide */
1437 # define TV_V_FILTER_BYPASS (1 << 29)
1438 /** Enables adaptive vertical filtering */
1439 # define TV_VADAPT (1 << 28)
1440 # define TV_VADAPT_MODE_MASK (3 << 26)
1441 /** Selects the least adaptive vertical filtering mode */
1442 # define TV_VADAPT_MODE_LEAST (0 << 26)
1443 /** Selects the moderately adaptive vertical filtering mode */
1444 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1445 /** Selects the most adaptive vertical filtering mode */
1446 # define TV_VADAPT_MODE_MOST (3 << 26)
1448 * Sets the horizontal scaling factor.
1450 * This should be the fractional part of the horizontal scaling factor divided
1451 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1453 * (src width - 1) / ((oversample * dest width) - 1)
1455 # define TV_HSCALE_FRAC_MASK 0x00003fff
1456 # define TV_HSCALE_FRAC_SHIFT 0
1458 #define TV_FILTER_CTL_2 0x68084
1460 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1462 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1464 # define TV_VSCALE_INT_MASK 0x00038000
1465 # define TV_VSCALE_INT_SHIFT 15
1467 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1469 * \sa TV_VSCALE_INT_MASK
1471 # define TV_VSCALE_FRAC_MASK 0x00007fff
1472 # define TV_VSCALE_FRAC_SHIFT 0
1474 #define TV_FILTER_CTL_3 0x68088
1476 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1478 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1480 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1482 # define TV_VSCALE_IP_INT_MASK 0x00038000
1483 # define TV_VSCALE_IP_INT_SHIFT 15
1485 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1487 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1489 * \sa TV_VSCALE_IP_INT_MASK
1491 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1492 # define TV_VSCALE_IP_FRAC_SHIFT 0
1494 #define TV_CC_CONTROL 0x68090
1495 # define TV_CC_ENABLE (1 << 31)
1497 * Specifies which field to send the CC data in.
1499 * CC data is usually sent in field 0.
1501 # define TV_CC_FID_MASK (1 << 27)
1502 # define TV_CC_FID_SHIFT 27
1503 /** Sets the horizontal position of the CC data. Usually 135. */
1504 # define TV_CC_HOFF_MASK 0x03ff0000
1505 # define TV_CC_HOFF_SHIFT 16
1506 /** Sets the vertical position of the CC data. Usually 21 */
1507 # define TV_CC_LINE_MASK 0x0000003f
1508 # define TV_CC_LINE_SHIFT 0
1510 #define TV_CC_DATA 0x68094
1511 # define TV_CC_RDY (1 << 31)
1512 /** Second word of CC data to be transmitted. */
1513 # define TV_CC_DATA_2_MASK 0x007f0000
1514 # define TV_CC_DATA_2_SHIFT 16
1515 /** First word of CC data to be transmitted. */
1516 # define TV_CC_DATA_1_MASK 0x0000007f
1517 # define TV_CC_DATA_1_SHIFT 0
1519 #define TV_H_LUMA_0 0x68100
1520 #define TV_H_LUMA_59 0x681ec
1521 #define TV_H_CHROMA_0 0x68200
1522 #define TV_H_CHROMA_59 0x682ec
1523 #define TV_V_LUMA_0 0x68300
1524 #define TV_V_LUMA_42 0x683a8
1525 #define TV_V_CHROMA_0 0x68400
1526 #define TV_V_CHROMA_42 0x684a8
1529 #define DP_A 0x64000 /* eDP */
1530 #define DP_B 0x64100
1531 #define DP_C 0x64200
1532 #define DP_D 0x64300
1534 #define DP_PORT_EN (1 << 31)
1535 #define DP_PIPEB_SELECT (1 << 30)
1537 /* Link training mode - select a suitable mode for each stage */
1538 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1539 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
1540 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1541 #define DP_LINK_TRAIN_OFF (3 << 28)
1542 #define DP_LINK_TRAIN_MASK (3 << 28)
1543 #define DP_LINK_TRAIN_SHIFT 28
1545 /* Signal voltages. These are mostly controlled by the other end */
1546 #define DP_VOLTAGE_0_4 (0 << 25)
1547 #define DP_VOLTAGE_0_6 (1 << 25)
1548 #define DP_VOLTAGE_0_8 (2 << 25)
1549 #define DP_VOLTAGE_1_2 (3 << 25)
1550 #define DP_VOLTAGE_MASK (7 << 25)
1551 #define DP_VOLTAGE_SHIFT 25
1553 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1556 #define DP_PRE_EMPHASIS_0 (0 << 22)
1557 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
1558 #define DP_PRE_EMPHASIS_6 (2 << 22)
1559 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
1560 #define DP_PRE_EMPHASIS_MASK (7 << 22)
1561 #define DP_PRE_EMPHASIS_SHIFT 22
1563 /* How many wires to use. I guess 3 was too hard */
1564 #define DP_PORT_WIDTH_1 (0 << 19)
1565 #define DP_PORT_WIDTH_2 (1 << 19)
1566 #define DP_PORT_WIDTH_4 (3 << 19)
1567 #define DP_PORT_WIDTH_MASK (7 << 19)
1569 /* Mystic DPCD version 1.1 special mode */
1570 #define DP_ENHANCED_FRAMING (1 << 18)
1573 #define DP_PLL_FREQ_270MHZ (0 << 16)
1574 #define DP_PLL_FREQ_160MHZ (1 << 16)
1575 #define DP_PLL_FREQ_MASK (3 << 16)
1577 /** locked once port is enabled */
1578 #define DP_PORT_REVERSAL (1 << 15)
1581 #define DP_PLL_ENABLE (1 << 14)
1583 /** sends the clock on lane 15 of the PEG for debug */
1584 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1586 #define DP_SCRAMBLING_DISABLE (1 << 12)
1587 #define DP_SCRAMBLING_DISABLE_IGDNG (1 << 7)
1589 /** limit RGB values to avoid confusing TVs */
1590 #define DP_COLOR_RANGE_16_235 (1 << 8)
1592 /** Turn on the audio link */
1593 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1595 /** vs and hs sync polarity */
1596 #define DP_SYNC_VS_HIGH (1 << 4)
1597 #define DP_SYNC_HS_HIGH (1 << 3)
1600 #define DP_DETECTED (1 << 2)
1602 /** The aux channel provides a way to talk to the
1603 * signal sink for DDC etc. Max packet size supported
1604 * is 20 bytes in each direction, hence the 5 fixed
1607 #define DPA_AUX_CH_CTL 0x64010
1608 #define DPA_AUX_CH_DATA1 0x64014
1609 #define DPA_AUX_CH_DATA2 0x64018
1610 #define DPA_AUX_CH_DATA3 0x6401c
1611 #define DPA_AUX_CH_DATA4 0x64020
1612 #define DPA_AUX_CH_DATA5 0x64024
1614 #define DPB_AUX_CH_CTL 0x64110
1615 #define DPB_AUX_CH_DATA1 0x64114
1616 #define DPB_AUX_CH_DATA2 0x64118
1617 #define DPB_AUX_CH_DATA3 0x6411c
1618 #define DPB_AUX_CH_DATA4 0x64120
1619 #define DPB_AUX_CH_DATA5 0x64124
1621 #define DPC_AUX_CH_CTL 0x64210
1622 #define DPC_AUX_CH_DATA1 0x64214
1623 #define DPC_AUX_CH_DATA2 0x64218
1624 #define DPC_AUX_CH_DATA3 0x6421c
1625 #define DPC_AUX_CH_DATA4 0x64220
1626 #define DPC_AUX_CH_DATA5 0x64224
1628 #define DPD_AUX_CH_CTL 0x64310
1629 #define DPD_AUX_CH_DATA1 0x64314
1630 #define DPD_AUX_CH_DATA2 0x64318
1631 #define DPD_AUX_CH_DATA3 0x6431c
1632 #define DPD_AUX_CH_DATA4 0x64320
1633 #define DPD_AUX_CH_DATA5 0x64324
1635 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1636 #define DP_AUX_CH_CTL_DONE (1 << 30)
1637 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1638 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1639 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1640 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1641 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1642 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1643 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1644 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1645 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1646 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1647 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1648 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1649 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1650 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1651 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1652 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1653 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1654 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1655 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1658 * Computing GMCH M and N values for the Display Port link
1660 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1662 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1664 * The GMCH value is used internally
1666 * bytes_per_pixel is the number of bytes coming out of the plane,
1667 * which is after the LUTs, so we want the bytes for our color format.
1668 * For our current usage, this is always 3, one byte for R, G and B.
1670 #define PIPEA_GMCH_DATA_M 0x70050
1671 #define PIPEB_GMCH_DATA_M 0x71050
1673 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1674 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1675 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1677 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
1679 #define PIPEA_GMCH_DATA_N 0x70054
1680 #define PIPEB_GMCH_DATA_N 0x71054
1681 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
1684 * Computing Link M and N values for the Display Port link
1686 * Link M / N = pixel_clock / ls_clk
1688 * (the DP spec calls pixel_clock the 'strm_clk')
1690 * The Link value is transmitted in the Main Stream
1691 * Attributes and VB-ID.
1694 #define PIPEA_DP_LINK_M 0x70060
1695 #define PIPEB_DP_LINK_M 0x71060
1696 #define PIPEA_DP_LINK_M_MASK (0xffffff)
1698 #define PIPEA_DP_LINK_N 0x70064
1699 #define PIPEB_DP_LINK_N 0x71064
1700 #define PIPEA_DP_LINK_N_MASK (0xffffff)
1702 /* Display & cursor control */
1705 #define PIPEADSL 0x70000
1706 #define PIPEACONF 0x70008
1707 #define PIPEACONF_ENABLE (1<<31)
1708 #define PIPEACONF_DISABLE 0
1709 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1710 #define I965_PIPECONF_ACTIVE (1<<30)
1711 #define PIPEACONF_SINGLE_WIDE 0
1712 #define PIPEACONF_PIPE_UNLOCKED 0
1713 #define PIPEACONF_PIPE_LOCKED (1<<25)
1714 #define PIPEACONF_PALETTE 0
1715 #define PIPEACONF_GAMMA (1<<24)
1716 #define PIPECONF_FORCE_BORDER (1<<25)
1717 #define PIPECONF_PROGRESSIVE (0 << 21)
1718 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1719 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1720 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
1721 #define PIPEASTAT 0x70024
1722 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1723 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1724 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1725 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1726 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1727 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1728 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1729 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1730 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1731 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1732 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1733 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1734 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1735 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1736 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1737 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1738 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1739 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1740 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1741 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1742 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1743 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1744 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1745 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1746 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1747 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1748 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1749 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1750 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1752 #define DSPARB 0x70030
1753 #define DSPARB_CSTART_MASK (0x7f << 7)
1754 #define DSPARB_CSTART_SHIFT 7
1755 #define DSPARB_BSTART_MASK (0x7f)
1756 #define DSPARB_BSTART_SHIFT 0
1757 #define DSPARB_BEND_SHIFT 9 /* on 855 */
1758 #define DSPARB_AEND_SHIFT 0
1760 #define DSPFW1 0x70034
1761 #define DSPFW2 0x70038
1762 #define DSPFW3 0x7003c
1763 #define IGD_SELF_REFRESH_EN (1<<30)
1765 /* FIFO watermark sizes etc */
1766 #define I915_FIFO_LINE_SIZE 64
1767 #define I830_FIFO_LINE_SIZE 32
1768 #define I945_FIFO_SIZE 127 /* 945 & 965 */
1769 #define I915_FIFO_SIZE 95
1770 #define I855GM_FIFO_SIZE 127 /* In cachelines */
1771 #define I830_FIFO_SIZE 95
1772 #define I915_MAX_WM 0x3f
1774 #define IGD_DISPLAY_FIFO 512 /* in 64byte unit */
1775 #define IGD_FIFO_LINE_SIZE 64
1776 #define IGD_MAX_WM 0x1ff
1777 #define IGD_DFT_WM 0x3f
1778 #define IGD_DFT_HPLLOFF_WM 0
1779 #define IGD_GUARD_WM 10
1780 #define IGD_CURSOR_FIFO 64
1781 #define IGD_CURSOR_MAX_WM 0x3f
1782 #define IGD_CURSOR_DFT_WM 0
1783 #define IGD_CURSOR_GUARD_WM 5
1786 * The two pipe frame counter registers are not synchronized, so
1787 * reading a stable value is somewhat tricky. The following code
1791 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1792 * PIPE_FRAME_HIGH_SHIFT;
1793 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1794 * PIPE_FRAME_LOW_SHIFT);
1795 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1796 * PIPE_FRAME_HIGH_SHIFT);
1797 * } while (high1 != high2);
1798 * frame = (high1 << 8) | low1;
1800 #define PIPEAFRAMEHIGH 0x70040
1801 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
1802 #define PIPE_FRAME_HIGH_SHIFT 0
1803 #define PIPEAFRAMEPIXEL 0x70044
1804 #define PIPE_FRAME_LOW_MASK 0xff000000
1805 #define PIPE_FRAME_LOW_SHIFT 24
1806 #define PIPE_PIXEL_MASK 0x00ffffff
1807 #define PIPE_PIXEL_SHIFT 0
1808 /* GM45+ just has to be different */
1809 #define PIPEA_FRMCOUNT_GM45 0x70040
1810 #define PIPEA_FLIPCOUNT_GM45 0x70044
1812 /* Cursor A & B regs */
1813 #define CURACNTR 0x70080
1814 /* Old style CUR*CNTR flags (desktop 8xx) */
1815 #define CURSOR_ENABLE 0x80000000
1816 #define CURSOR_GAMMA_ENABLE 0x40000000
1817 #define CURSOR_STRIDE_MASK 0x30000000
1818 #define CURSOR_FORMAT_SHIFT 24
1819 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
1820 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
1821 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
1822 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
1823 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
1824 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
1825 /* New style CUR*CNTR flags */
1826 #define CURSOR_MODE 0x27
1827 #define CURSOR_MODE_DISABLE 0x00
1828 #define CURSOR_MODE_64_32B_AX 0x07
1829 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1830 #define MCURSOR_PIPE_SELECT (1 << 28)
1831 #define MCURSOR_PIPE_A 0x00
1832 #define MCURSOR_PIPE_B (1 << 28)
1833 #define MCURSOR_GAMMA_ENABLE (1 << 26)
1834 #define CURABASE 0x70084
1835 #define CURAPOS 0x70088
1836 #define CURSOR_POS_MASK 0x007FF
1837 #define CURSOR_POS_SIGN 0x8000
1838 #define CURSOR_X_SHIFT 0
1839 #define CURSOR_Y_SHIFT 16
1840 #define CURSIZE 0x700a0
1841 #define CURBCNTR 0x700c0
1842 #define CURBBASE 0x700c4
1843 #define CURBPOS 0x700c8
1845 /* Display A control */
1846 #define DSPACNTR 0x70180
1847 #define DISPLAY_PLANE_ENABLE (1<<31)
1848 #define DISPLAY_PLANE_DISABLE 0
1849 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1850 #define DISPPLANE_GAMMA_DISABLE 0
1851 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1852 #define DISPPLANE_8BPP (0x2<<26)
1853 #define DISPPLANE_15_16BPP (0x4<<26)
1854 #define DISPPLANE_16BPP (0x5<<26)
1855 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1856 #define DISPPLANE_32BPP (0x7<<26)
1857 #define DISPPLANE_STEREO_ENABLE (1<<25)
1858 #define DISPPLANE_STEREO_DISABLE 0
1859 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1860 #define DISPPLANE_SEL_PIPE_A 0
1861 #define DISPPLANE_SEL_PIPE_B (1<<24)
1862 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1863 #define DISPPLANE_SRC_KEY_DISABLE 0
1864 #define DISPPLANE_LINE_DOUBLE (1<<20)
1865 #define DISPPLANE_NO_LINE_DOUBLE 0
1866 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1867 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1868 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */
1869 #define DISPPLANE_TILED (1<<10)
1870 #define DSPAADDR 0x70184
1871 #define DSPASTRIDE 0x70188
1872 #define DSPAPOS 0x7018C /* reserved */
1873 #define DSPASIZE 0x70190
1874 #define DSPASURF 0x7019C /* 965+ only */
1875 #define DSPATILEOFF 0x701A4 /* 965+ only */
1878 #define SWF00 0x71410
1879 #define SWF01 0x71414
1880 #define SWF02 0x71418
1881 #define SWF03 0x7141c
1882 #define SWF04 0x71420
1883 #define SWF05 0x71424
1884 #define SWF06 0x71428
1885 #define SWF10 0x70410
1886 #define SWF11 0x70414
1887 #define SWF14 0x71420
1888 #define SWF30 0x72414
1889 #define SWF31 0x72418
1890 #define SWF32 0x7241c
1893 #define PIPEBDSL 0x71000
1894 #define PIPEBCONF 0x71008
1895 #define PIPEBSTAT 0x71024
1896 #define PIPEBFRAMEHIGH 0x71040
1897 #define PIPEBFRAMEPIXEL 0x71044
1898 #define PIPEB_FRMCOUNT_GM45 0x71040
1899 #define PIPEB_FLIPCOUNT_GM45 0x71044
1902 /* Display B control */
1903 #define DSPBCNTR 0x71180
1904 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1905 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1906 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1907 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1908 #define DSPBADDR 0x71184
1909 #define DSPBSTRIDE 0x71188
1910 #define DSPBPOS 0x7118C
1911 #define DSPBSIZE 0x71190
1912 #define DSPBSURF 0x7119C
1913 #define DSPBTILEOFF 0x711A4
1916 #define VGACNTRL 0x71400
1917 # define VGA_DISP_DISABLE (1 << 31)
1918 # define VGA_2X_MODE (1 << 30)
1919 # define VGA_PIPE_B_SELECT (1 << 29)
1923 #define CPU_VGACNTRL 0x41000
1925 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
1926 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
1927 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
1928 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
1929 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
1930 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
1931 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
1932 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
1933 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
1935 /* refresh rate hardware control */
1936 #define RR_HW_CTL 0x45300
1937 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
1938 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
1940 #define FDI_PLL_BIOS_0 0x46000
1941 #define FDI_PLL_BIOS_1 0x46004
1942 #define FDI_PLL_BIOS_2 0x46008
1943 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
1944 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
1945 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
1947 #define FDI_PLL_FREQ_CTL 0x46030
1948 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
1949 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
1950 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
1953 #define PIPEA_DATA_M1 0x60030
1954 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
1955 #define TU_SIZE_MASK 0x7e000000
1956 #define PIPEA_DATA_M1_OFFSET 0
1957 #define PIPEA_DATA_N1 0x60034
1958 #define PIPEA_DATA_N1_OFFSET 0
1960 #define PIPEA_DATA_M2 0x60038
1961 #define PIPEA_DATA_M2_OFFSET 0
1962 #define PIPEA_DATA_N2 0x6003c
1963 #define PIPEA_DATA_N2_OFFSET 0
1965 #define PIPEA_LINK_M1 0x60040
1966 #define PIPEA_LINK_M1_OFFSET 0
1967 #define PIPEA_LINK_N1 0x60044
1968 #define PIPEA_LINK_N1_OFFSET 0
1970 #define PIPEA_LINK_M2 0x60048
1971 #define PIPEA_LINK_M2_OFFSET 0
1972 #define PIPEA_LINK_N2 0x6004c
1973 #define PIPEA_LINK_N2_OFFSET 0
1975 /* PIPEB timing regs are same start from 0x61000 */
1977 #define PIPEB_DATA_M1 0x61030
1978 #define PIPEB_DATA_M1_OFFSET 0
1979 #define PIPEB_DATA_N1 0x61034
1980 #define PIPEB_DATA_N1_OFFSET 0
1982 #define PIPEB_DATA_M2 0x61038
1983 #define PIPEB_DATA_M2_OFFSET 0
1984 #define PIPEB_DATA_N2 0x6103c
1985 #define PIPEB_DATA_N2_OFFSET 0
1987 #define PIPEB_LINK_M1 0x61040
1988 #define PIPEB_LINK_M1_OFFSET 0
1989 #define PIPEB_LINK_N1 0x61044
1990 #define PIPEB_LINK_N1_OFFSET 0
1992 #define PIPEB_LINK_M2 0x61048
1993 #define PIPEB_LINK_M2_OFFSET 0
1994 #define PIPEB_LINK_N2 0x6104c
1995 #define PIPEB_LINK_N2_OFFSET 0
1997 /* CPU panel fitter */
1998 #define PFA_CTL_1 0x68080
1999 #define PFB_CTL_1 0x68880
2000 #define PF_ENABLE (1<<31)
2001 #define PFA_WIN_SZ 0x68074
2002 #define PFB_WIN_SZ 0x68874
2004 /* legacy palette */
2005 #define LGC_PALETTE_A 0x4a000
2006 #define LGC_PALETTE_B 0x4a800
2009 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2010 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2011 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2012 #define DE_PLANEB_FLIP_DONE (1 << 27)
2013 #define DE_PLANEA_FLIP_DONE (1 << 26)
2014 #define DE_PCU_EVENT (1 << 25)
2015 #define DE_GTT_FAULT (1 << 24)
2016 #define DE_POISON (1 << 23)
2017 #define DE_PERFORM_COUNTER (1 << 22)
2018 #define DE_PCH_EVENT (1 << 21)
2019 #define DE_AUX_CHANNEL_A (1 << 20)
2020 #define DE_DP_A_HOTPLUG (1 << 19)
2021 #define DE_GSE (1 << 18)
2022 #define DE_PIPEB_VBLANK (1 << 15)
2023 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2024 #define DE_PIPEB_ODD_FIELD (1 << 13)
2025 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2026 #define DE_PIPEB_VSYNC (1 << 11)
2027 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2028 #define DE_PIPEA_VBLANK (1 << 7)
2029 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2030 #define DE_PIPEA_ODD_FIELD (1 << 5)
2031 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2032 #define DE_PIPEA_VSYNC (1 << 3)
2033 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2035 #define DEISR 0x44000
2036 #define DEIMR 0x44004
2037 #define DEIIR 0x44008
2038 #define DEIER 0x4400c
2041 #define GT_SYNC_STATUS (1 << 2)
2042 #define GT_USER_INTERRUPT (1 << 0)
2044 #define GTISR 0x44010
2045 #define GTIMR 0x44014
2046 #define GTIIR 0x44018
2047 #define GTIER 0x4401c
2049 #define DISP_ARB_CTL 0x45000
2050 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2054 /* south display engine interrupt */
2055 #define SDE_CRT_HOTPLUG (1 << 11)
2056 #define SDE_PORTD_HOTPLUG (1 << 10)
2057 #define SDE_PORTC_HOTPLUG (1 << 9)
2058 #define SDE_PORTB_HOTPLUG (1 << 8)
2059 #define SDE_SDVOB_HOTPLUG (1 << 6)
2061 #define SDEISR 0xc4000
2062 #define SDEIMR 0xc4004
2063 #define SDEIIR 0xc4008
2064 #define SDEIER 0xc400c
2066 /* digital port hotplug */
2067 #define PCH_PORT_HOTPLUG 0xc4030
2068 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2069 #define PORTD_PULSE_DURATION_2ms (0)
2070 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2071 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2072 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2073 #define PORTD_HOTPLUG_NO_DETECT (0)
2074 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2075 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2076 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2077 #define PORTC_PULSE_DURATION_2ms (0)
2078 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2079 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2080 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2081 #define PORTC_HOTPLUG_NO_DETECT (0)
2082 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2083 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2084 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2085 #define PORTB_PULSE_DURATION_2ms (0)
2086 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2087 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2088 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2089 #define PORTB_HOTPLUG_NO_DETECT (0)
2090 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2091 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2093 #define PCH_GPIOA 0xc5010
2094 #define PCH_GPIOB 0xc5014
2095 #define PCH_GPIOC 0xc5018
2096 #define PCH_GPIOD 0xc501c
2097 #define PCH_GPIOE 0xc5020
2098 #define PCH_GPIOF 0xc5024
2100 #define PCH_DPLL_A 0xc6014
2101 #define PCH_DPLL_B 0xc6018
2103 #define PCH_FPA0 0xc6040
2104 #define PCH_FPA1 0xc6044
2105 #define PCH_FPB0 0xc6048
2106 #define PCH_FPB1 0xc604c
2108 #define PCH_DPLL_TEST 0xc606c
2110 #define PCH_DREF_CONTROL 0xC6200
2111 #define DREF_CONTROL_MASK 0x7fc3
2112 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2113 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2114 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2115 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2116 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2117 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2118 #define DREF_SSC_SOURCE_MASK (2<<11)
2119 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2120 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2121 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2122 #define DREF_NONSPREAD_SOURCE_MASK (2<<9)
2123 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2124 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2125 #define DREF_SSC4_DOWNSPREAD (0<<6)
2126 #define DREF_SSC4_CENTERSPREAD (1<<6)
2127 #define DREF_SSC1_DISABLE (0<<1)
2128 #define DREF_SSC1_ENABLE (1<<1)
2129 #define DREF_SSC4_DISABLE (0)
2130 #define DREF_SSC4_ENABLE (1)
2132 #define PCH_RAWCLK_FREQ 0xc6204
2133 #define FDL_TP1_TIMER_SHIFT 12
2134 #define FDL_TP1_TIMER_MASK (3<<12)
2135 #define FDL_TP2_TIMER_SHIFT 10
2136 #define FDL_TP2_TIMER_MASK (3<<10)
2137 #define RAWCLK_FREQ_MASK 0x3ff
2139 #define PCH_DPLL_TMR_CFG 0xc6208
2141 #define PCH_SSC4_PARMS 0xc6210
2142 #define PCH_SSC4_AUX_PARMS 0xc6214
2146 #define TRANS_HTOTAL_A 0xe0000
2147 #define TRANS_HTOTAL_SHIFT 16
2148 #define TRANS_HACTIVE_SHIFT 0
2149 #define TRANS_HBLANK_A 0xe0004
2150 #define TRANS_HBLANK_END_SHIFT 16
2151 #define TRANS_HBLANK_START_SHIFT 0
2152 #define TRANS_HSYNC_A 0xe0008
2153 #define TRANS_HSYNC_END_SHIFT 16
2154 #define TRANS_HSYNC_START_SHIFT 0
2155 #define TRANS_VTOTAL_A 0xe000c
2156 #define TRANS_VTOTAL_SHIFT 16
2157 #define TRANS_VACTIVE_SHIFT 0
2158 #define TRANS_VBLANK_A 0xe0010
2159 #define TRANS_VBLANK_END_SHIFT 16
2160 #define TRANS_VBLANK_START_SHIFT 0
2161 #define TRANS_VSYNC_A 0xe0014
2162 #define TRANS_VSYNC_END_SHIFT 16
2163 #define TRANS_VSYNC_START_SHIFT 0
2165 #define TRANSA_DATA_M1 0xe0030
2166 #define TRANSA_DATA_N1 0xe0034
2167 #define TRANSA_DATA_M2 0xe0038
2168 #define TRANSA_DATA_N2 0xe003c
2169 #define TRANSA_DP_LINK_M1 0xe0040
2170 #define TRANSA_DP_LINK_N1 0xe0044
2171 #define TRANSA_DP_LINK_M2 0xe0048
2172 #define TRANSA_DP_LINK_N2 0xe004c
2174 #define TRANS_HTOTAL_B 0xe1000
2175 #define TRANS_HBLANK_B 0xe1004
2176 #define TRANS_HSYNC_B 0xe1008
2177 #define TRANS_VTOTAL_B 0xe100c
2178 #define TRANS_VBLANK_B 0xe1010
2179 #define TRANS_VSYNC_B 0xe1014
2181 #define TRANSB_DATA_M1 0xe1030
2182 #define TRANSB_DATA_N1 0xe1034
2183 #define TRANSB_DATA_M2 0xe1038
2184 #define TRANSB_DATA_N2 0xe103c
2185 #define TRANSB_DP_LINK_M1 0xe1040
2186 #define TRANSB_DP_LINK_N1 0xe1044
2187 #define TRANSB_DP_LINK_M2 0xe1048
2188 #define TRANSB_DP_LINK_N2 0xe104c
2190 #define TRANSACONF 0xf0008
2191 #define TRANSBCONF 0xf1008
2192 #define TRANS_DISABLE (0<<31)
2193 #define TRANS_ENABLE (1<<31)
2194 #define TRANS_STATE_MASK (1<<30)
2195 #define TRANS_STATE_DISABLE (0<<30)
2196 #define TRANS_STATE_ENABLE (1<<30)
2197 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
2198 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
2199 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
2200 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
2201 #define TRANS_DP_AUDIO_ONLY (1<<26)
2202 #define TRANS_DP_VIDEO_AUDIO (0<<26)
2203 #define TRANS_PROGRESSIVE (0<<21)
2204 #define TRANS_8BPC (0<<5)
2205 #define TRANS_10BPC (1<<5)
2206 #define TRANS_6BPC (2<<5)
2207 #define TRANS_12BPC (3<<5)
2209 #define FDI_RXA_CHICKEN 0xc200c
2210 #define FDI_RXB_CHICKEN 0xc2010
2211 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2214 #define FDI_TXA_CTL 0x60100
2215 #define FDI_TXB_CTL 0x61100
2216 #define FDI_TX_DISABLE (0<<31)
2217 #define FDI_TX_ENABLE (1<<31)
2218 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2219 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2220 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2221 #define FDI_LINK_TRAIN_NONE (3<<28)
2222 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2223 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2224 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2225 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2226 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2227 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2228 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2229 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2230 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2231 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2232 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2233 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2234 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2235 /* IGDNG: hardwired to 1 */
2236 #define FDI_TX_PLL_ENABLE (1<<14)
2237 /* both Tx and Rx */
2238 #define FDI_SCRAMBLING_ENABLE (0<<7)
2239 #define FDI_SCRAMBLING_DISABLE (1<<7)
2241 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2242 #define FDI_RXA_CTL 0xf000c
2243 #define FDI_RXB_CTL 0xf100c
2244 #define FDI_RX_ENABLE (1<<31)
2245 #define FDI_RX_DISABLE (0<<31)
2246 /* train, dp width same as FDI_TX */
2247 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2248 #define FDI_8BPC (0<<16)
2249 #define FDI_10BPC (1<<16)
2250 #define FDI_6BPC (2<<16)
2251 #define FDI_12BPC (3<<16)
2252 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2253 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2254 #define FDI_RX_PLL_ENABLE (1<<13)
2255 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2256 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2257 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2258 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2259 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2260 #define FDI_SEL_RAWCLK (0<<4)
2261 #define FDI_SEL_PCDCLK (1<<4)
2263 #define FDI_RXA_MISC 0xf0010
2264 #define FDI_RXB_MISC 0xf1010
2265 #define FDI_RXA_TUSIZE1 0xf0030
2266 #define FDI_RXA_TUSIZE2 0xf0038
2267 #define FDI_RXB_TUSIZE1 0xf1030
2268 #define FDI_RXB_TUSIZE2 0xf1038
2270 /* FDI_RX interrupt register format */
2271 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
2272 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2273 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2274 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2275 #define FDI_RX_FS_CODE_ERR (1<<6)
2276 #define FDI_RX_FE_CODE_ERR (1<<5)
2277 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2278 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
2279 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2280 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2281 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2283 #define FDI_RXA_IIR 0xf0014
2284 #define FDI_RXA_IMR 0xf0018
2285 #define FDI_RXB_IIR 0xf1014
2286 #define FDI_RXB_IMR 0xf1018
2288 #define FDI_PLL_CTL_1 0xfe000
2289 #define FDI_PLL_CTL_2 0xfe004
2292 #define PCH_ADPA 0xe1100
2293 #define ADPA_TRANS_SELECT_MASK (1<<30)
2294 #define ADPA_TRANS_A_SELECT 0
2295 #define ADPA_TRANS_B_SELECT (1<<30)
2296 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2297 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2298 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2299 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2300 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2301 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2302 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2303 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2304 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2305 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2306 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2307 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2308 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2309 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2310 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2311 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2312 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2313 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2314 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2317 #define HDMIB 0xe1140
2318 #define PORT_ENABLE (1 << 31)
2319 #define TRANSCODER_A (0)
2320 #define TRANSCODER_B (1 << 30)
2321 #define COLOR_FORMAT_8bpc (0)
2322 #define COLOR_FORMAT_12bpc (3 << 26)
2323 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
2324 #define SDVO_ENCODING (0)
2325 #define TMDS_ENCODING (2 << 10)
2326 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2327 #define SDVOB_BORDER_ENABLE (1 << 7)
2328 #define AUDIO_ENABLE (1 << 6)
2329 #define VSYNC_ACTIVE_HIGH (1 << 4)
2330 #define HSYNC_ACTIVE_HIGH (1 << 3)
2331 #define PORT_DETECTED (1 << 2)
2333 #define HDMIC 0xe1150
2334 #define HDMID 0xe1160
2336 #define PCH_LVDS 0xe1180
2337 #define LVDS_DETECTED (1 << 1)
2339 #define BLC_PWM_CPU_CTL2 0x48250
2340 #define PWM_ENABLE (1 << 31)
2341 #define PWM_PIPE_A (0 << 29)
2342 #define PWM_PIPE_B (1 << 29)
2343 #define BLC_PWM_CPU_CTL 0x48254
2345 #define BLC_PWM_PCH_CTL1 0xc8250
2346 #define PWM_PCH_ENABLE (1 << 31)
2347 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2348 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2349 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2350 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2352 #define BLC_PWM_PCH_CTL2 0xc8254
2354 #define PCH_PP_STATUS 0xc7200
2355 #define PCH_PP_CONTROL 0xc7204
2356 #define EDP_FORCE_VDD (1 << 3)
2357 #define EDP_BLC_ENABLE (1 << 2)
2358 #define PANEL_POWER_RESET (1 << 1)
2359 #define PANEL_POWER_OFF (0 << 0)
2360 #define PANEL_POWER_ON (1 << 0)
2361 #define PCH_PP_ON_DELAYS 0xc7208
2362 #define EDP_PANEL (1 << 30)
2363 #define PCH_PP_OFF_DELAYS 0xc720c
2364 #define PCH_PP_DIVISOR 0xc7210
2366 #define PCH_DP_B 0xe4100
2367 #define PCH_DPB_AUX_CH_CTL 0xe4110
2368 #define PCH_DPB_AUX_CH_DATA1 0xe4114
2369 #define PCH_DPB_AUX_CH_DATA2 0xe4118
2370 #define PCH_DPB_AUX_CH_DATA3 0xe411c
2371 #define PCH_DPB_AUX_CH_DATA4 0xe4120
2372 #define PCH_DPB_AUX_CH_DATA5 0xe4124
2374 #define PCH_DP_C 0xe4200
2375 #define PCH_DPC_AUX_CH_CTL 0xe4210
2376 #define PCH_DPC_AUX_CH_DATA1 0xe4214
2377 #define PCH_DPC_AUX_CH_DATA2 0xe4218
2378 #define PCH_DPC_AUX_CH_DATA3 0xe421c
2379 #define PCH_DPC_AUX_CH_DATA4 0xe4220
2380 #define PCH_DPC_AUX_CH_DATA5 0xe4224
2382 #define PCH_DP_D 0xe4300
2383 #define PCH_DPD_AUX_CH_CTL 0xe4310
2384 #define PCH_DPD_AUX_CH_DATA1 0xe4314
2385 #define PCH_DPD_AUX_CH_DATA2 0xe4318
2386 #define PCH_DPD_AUX_CH_DATA3 0xe431c
2387 #define PCH_DPD_AUX_CH_DATA4 0xe4320
2388 #define PCH_DPD_AUX_CH_DATA5 0xe4324
2390 #endif /* _I915_REG_H_ */