3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "intel_drv.h"
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private;
37 if (HAS_PCH_SPLIT(dev)) {
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
43 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
46 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
53 if (!i915_pipe_enabled(dev, pipe))
56 if (HAS_PCH_SPLIT(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
60 array = dev_priv->save_palette_a;
62 array = dev_priv->save_palette_b;
64 for(i = 0; i < 256; i++)
65 array[i] = I915_READ(reg + (i << 2));
68 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
70 struct drm_i915_private *dev_priv = dev->dev_private;
71 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
75 if (!i915_pipe_enabled(dev, pipe))
78 if (HAS_PCH_SPLIT(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
82 array = dev_priv->save_palette_a;
84 array = dev_priv->save_palette_b;
86 for(i = 0; i < 256; i++)
87 I915_WRITE(reg + (i << 2), array[i]);
90 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
92 struct drm_i915_private *dev_priv = dev->dev_private;
94 I915_WRITE8(index_port, reg);
95 return I915_READ8(data_port);
98 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
100 struct drm_i915_private *dev_priv = dev->dev_private;
103 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
104 return I915_READ8(VGA_AR_DATA_READ);
107 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
109 struct drm_i915_private *dev_priv = dev->dev_private;
112 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
113 I915_WRITE8(VGA_AR_DATA_WRITE, val);
116 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
118 struct drm_i915_private *dev_priv = dev->dev_private;
120 I915_WRITE8(index_port, reg);
121 I915_WRITE8(data_port, val);
124 static void i915_save_vga(struct drm_device *dev)
126 struct drm_i915_private *dev_priv = dev->dev_private;
128 u16 cr_index, cr_data, st01;
130 /* VGA color palette registers */
131 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
134 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
135 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
136 cr_index = VGA_CR_INDEX_CGA;
137 cr_data = VGA_CR_DATA_CGA;
140 cr_index = VGA_CR_INDEX_MDA;
141 cr_data = VGA_CR_DATA_MDA;
145 /* CRT controller regs */
146 i915_write_indexed(dev, cr_index, cr_data, 0x11,
147 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
149 for (i = 0; i <= 0x24; i++)
150 dev_priv->saveCR[i] =
151 i915_read_indexed(dev, cr_index, cr_data, i);
152 /* Make sure we don't turn off CR group 0 writes */
153 dev_priv->saveCR[0x11] &= ~0x80;
155 /* Attribute controller registers */
157 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
158 for (i = 0; i <= 0x14; i++)
159 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
161 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
164 /* Graphics controller registers */
165 for (i = 0; i < 9; i++)
166 dev_priv->saveGR[i] =
167 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
169 dev_priv->saveGR[0x10] =
170 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
171 dev_priv->saveGR[0x11] =
172 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
173 dev_priv->saveGR[0x18] =
174 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
176 /* Sequencer registers */
177 for (i = 0; i < 8; i++)
178 dev_priv->saveSR[i] =
179 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
182 static void i915_restore_vga(struct drm_device *dev)
184 struct drm_i915_private *dev_priv = dev->dev_private;
186 u16 cr_index, cr_data, st01;
189 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
190 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
191 cr_index = VGA_CR_INDEX_CGA;
192 cr_data = VGA_CR_DATA_CGA;
195 cr_index = VGA_CR_INDEX_MDA;
196 cr_data = VGA_CR_DATA_MDA;
200 /* Sequencer registers, don't write SR07 */
201 for (i = 0; i < 7; i++)
202 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
203 dev_priv->saveSR[i]);
205 /* CRT controller regs */
206 /* Enable CR group 0 writes */
207 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
208 for (i = 0; i <= 0x24; i++)
209 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
211 /* Graphics controller regs */
212 for (i = 0; i < 9; i++)
213 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
214 dev_priv->saveGR[i]);
216 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
217 dev_priv->saveGR[0x10]);
218 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
219 dev_priv->saveGR[0x11]);
220 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
221 dev_priv->saveGR[0x18]);
223 /* Attribute controller registers */
224 I915_READ8(st01); /* switch back to index mode */
225 for (i = 0; i <= 0x14; i++)
226 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
227 I915_READ8(st01); /* switch back to index mode */
228 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
231 /* VGA color palette registers */
232 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
235 static void i915_save_modeset_reg(struct drm_device *dev)
237 struct drm_i915_private *dev_priv = dev->dev_private;
240 if (drm_core_check_feature(dev, DRIVER_MODESET))
244 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
245 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
246 dev_priv->saveCURABASE = I915_READ(CURABASE);
247 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
248 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
249 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
251 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
253 if (HAS_PCH_SPLIT(dev)) {
254 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
255 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
258 /* Pipe & plane A info */
259 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
260 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
261 if (HAS_PCH_SPLIT(dev)) {
262 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
263 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
264 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
266 dev_priv->saveFPA0 = I915_READ(FPA0);
267 dev_priv->saveFPA1 = I915_READ(FPA1);
268 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
270 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
271 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
272 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
273 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
274 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
275 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
276 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
277 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
278 if (!HAS_PCH_SPLIT(dev))
279 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
281 if (HAS_PCH_SPLIT(dev)) {
282 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
283 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
284 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
285 dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
287 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
288 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
290 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
291 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
292 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
294 dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
295 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
296 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
297 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
298 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
299 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
300 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
303 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
304 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
305 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
306 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
307 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
308 if (INTEL_INFO(dev)->gen >= 4) {
309 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
310 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
312 i915_save_palette(dev, PIPE_A);
313 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
315 /* Pipe & plane B info */
316 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
317 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
318 if (HAS_PCH_SPLIT(dev)) {
319 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
320 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
321 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
323 dev_priv->saveFPB0 = I915_READ(FPB0);
324 dev_priv->saveFPB1 = I915_READ(FPB1);
325 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
327 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
328 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
329 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
330 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
331 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
332 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
333 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
334 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
335 if (!HAS_PCH_SPLIT(dev))
336 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
338 if (HAS_PCH_SPLIT(dev)) {
339 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
340 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
341 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
342 dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
344 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
345 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
347 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
348 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
349 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
351 dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
352 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
353 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
354 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
355 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
356 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
357 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
360 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
361 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
362 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
363 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
364 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
365 if (INTEL_INFO(dev)->gen >= 4) {
366 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
367 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
369 i915_save_palette(dev, PIPE_B);
370 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
373 switch (INTEL_INFO(dev)->gen) {
375 for (i = 0; i < 16; i++)
376 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
380 for (i = 0; i < 16; i++)
381 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
384 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
385 for (i = 0; i < 8; i++)
386 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
388 for (i = 0; i < 8; i++)
389 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
396 static void i915_restore_modeset_reg(struct drm_device *dev)
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 int dpll_a_reg, fpa0_reg, fpa1_reg;
400 int dpll_b_reg, fpb0_reg, fpb1_reg;
403 if (drm_core_check_feature(dev, DRIVER_MODESET))
407 switch (INTEL_INFO(dev)->gen) {
409 for (i = 0; i < 16; i++)
410 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
414 for (i = 0; i < 16; i++)
415 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
419 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
420 for (i = 0; i < 8; i++)
421 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
422 for (i = 0; i < 8; i++)
423 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
428 if (HAS_PCH_SPLIT(dev)) {
429 dpll_a_reg = PCH_DPLL_A;
430 dpll_b_reg = PCH_DPLL_B;
444 if (HAS_PCH_SPLIT(dev)) {
445 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
446 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
449 /* Pipe & plane A info */
450 /* Prime the clock */
451 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
452 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
454 POSTING_READ(dpll_a_reg);
457 I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
458 I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
459 /* Actually enable it */
460 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
461 POSTING_READ(dpll_a_reg);
463 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
464 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
465 POSTING_READ(DPLL_A_MD);
470 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
471 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
472 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
473 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
474 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
475 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
476 if (!HAS_PCH_SPLIT(dev))
477 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
479 if (HAS_PCH_SPLIT(dev)) {
480 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
481 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
482 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
483 I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
485 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
486 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
488 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
489 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
490 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
492 I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
493 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
494 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
495 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
496 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
497 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
498 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
501 /* Restore plane info */
502 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
503 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
504 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
505 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
506 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
507 if (INTEL_INFO(dev)->gen >= 4) {
508 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
509 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
512 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
514 i915_restore_palette(dev, PIPE_A);
515 /* Enable the plane */
516 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
517 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
519 /* Pipe & plane B info */
520 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
521 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
523 POSTING_READ(dpll_b_reg);
526 I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
527 I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
528 /* Actually enable it */
529 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
530 POSTING_READ(dpll_b_reg);
532 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
533 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
534 POSTING_READ(DPLL_B_MD);
539 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
540 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
541 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
542 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
543 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
544 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
545 if (!HAS_PCH_SPLIT(dev))
546 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
548 if (HAS_PCH_SPLIT(dev)) {
549 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
550 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
551 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
552 I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
554 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
555 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
557 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
558 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
559 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
561 I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
562 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
563 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
564 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
565 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
566 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
567 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
570 /* Restore plane info */
571 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
572 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
573 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
574 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
575 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
576 if (INTEL_INFO(dev)->gen >= 4) {
577 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
578 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
581 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
583 i915_restore_palette(dev, PIPE_B);
584 /* Enable the plane */
585 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
586 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
589 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
590 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
591 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
592 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
593 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
594 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
596 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
601 void i915_save_display(struct drm_device *dev)
603 struct drm_i915_private *dev_priv = dev->dev_private;
605 /* Display arbitration control */
606 dev_priv->saveDSPARB = I915_READ(DSPARB);
608 /* This is only meaningful in non-KMS mode */
609 /* Don't save them in KMS mode */
610 i915_save_modeset_reg(dev);
613 if (HAS_PCH_SPLIT(dev)) {
614 dev_priv->saveADPA = I915_READ(PCH_ADPA);
616 dev_priv->saveADPA = I915_READ(ADPA);
620 if (HAS_PCH_SPLIT(dev)) {
621 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
622 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
623 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
624 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
625 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
626 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
628 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
629 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
630 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
631 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
632 if (INTEL_INFO(dev)->gen >= 4)
633 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
634 if (IS_MOBILE(dev) && !IS_I830(dev))
635 dev_priv->saveLVDS = I915_READ(LVDS);
638 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
639 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
641 if (HAS_PCH_SPLIT(dev)) {
642 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
643 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
644 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
646 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
647 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
648 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
651 /* Display Port state */
652 if (SUPPORTS_INTEGRATED_DP(dev)) {
653 dev_priv->saveDP_B = I915_READ(DP_B);
654 dev_priv->saveDP_C = I915_READ(DP_C);
655 dev_priv->saveDP_D = I915_READ(DP_D);
656 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
657 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
658 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
659 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
660 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
661 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
662 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
663 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
665 /* FIXME: save TV & SDVO state */
667 /* Only save FBC state on the platform that supports FBC */
668 if (I915_HAS_FBC(dev)) {
669 if (HAS_PCH_SPLIT(dev)) {
670 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
671 } else if (IS_GM45(dev)) {
672 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
674 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
675 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
676 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
677 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
682 dev_priv->saveVGA0 = I915_READ(VGA0);
683 dev_priv->saveVGA1 = I915_READ(VGA1);
684 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
685 if (HAS_PCH_SPLIT(dev))
686 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
688 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
693 void i915_restore_display(struct drm_device *dev)
695 struct drm_i915_private *dev_priv = dev->dev_private;
697 /* Display arbitration */
698 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
700 /* Display port ratios (must be done before clock is set) */
701 if (SUPPORTS_INTEGRATED_DP(dev)) {
702 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
703 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
704 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
705 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
706 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
707 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
708 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
709 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
712 /* This is only meaningful in non-KMS mode */
713 /* Don't restore them in KMS mode */
714 i915_restore_modeset_reg(dev);
717 if (HAS_PCH_SPLIT(dev))
718 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
720 I915_WRITE(ADPA, dev_priv->saveADPA);
723 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
724 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
726 if (HAS_PCH_SPLIT(dev)) {
727 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
728 } else if (IS_MOBILE(dev) && !IS_I830(dev))
729 I915_WRITE(LVDS, dev_priv->saveLVDS);
731 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
732 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
734 if (HAS_PCH_SPLIT(dev)) {
735 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
736 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
737 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
738 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
739 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
740 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
741 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
742 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
743 I915_WRITE(RSTDBYCTL,
744 dev_priv->saveMCHBAR_RENDER_STANDBY);
746 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
747 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
748 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
749 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
750 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
751 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
752 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
755 /* Display Port state */
756 if (SUPPORTS_INTEGRATED_DP(dev)) {
757 I915_WRITE(DP_B, dev_priv->saveDP_B);
758 I915_WRITE(DP_C, dev_priv->saveDP_C);
759 I915_WRITE(DP_D, dev_priv->saveDP_D);
761 /* FIXME: restore TV & SDVO state */
763 /* only restore FBC info on the platform that supports FBC*/
764 if (I915_HAS_FBC(dev)) {
765 if (HAS_PCH_SPLIT(dev)) {
766 ironlake_disable_fbc(dev);
767 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
768 } else if (IS_GM45(dev)) {
769 g4x_disable_fbc(dev);
770 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
772 i8xx_disable_fbc(dev);
773 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
774 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
775 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
776 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
780 if (HAS_PCH_SPLIT(dev))
781 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
783 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
784 I915_WRITE(VGA0, dev_priv->saveVGA0);
785 I915_WRITE(VGA1, dev_priv->saveVGA1);
786 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
787 POSTING_READ(VGA_PD);
790 i915_restore_vga(dev);
793 int i915_save_state(struct drm_device *dev)
795 struct drm_i915_private *dev_priv = dev->dev_private;
798 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
800 /* Hardware status page */
801 dev_priv->saveHWS = I915_READ(HWS_PGA);
803 i915_save_display(dev);
805 /* Interrupt state */
806 if (HAS_PCH_SPLIT(dev)) {
807 dev_priv->saveDEIER = I915_READ(DEIER);
808 dev_priv->saveDEIMR = I915_READ(DEIMR);
809 dev_priv->saveGTIER = I915_READ(GTIER);
810 dev_priv->saveGTIMR = I915_READ(GTIMR);
811 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
812 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
813 dev_priv->saveMCHBAR_RENDER_STANDBY =
814 I915_READ(RSTDBYCTL);
816 dev_priv->saveIER = I915_READ(IER);
817 dev_priv->saveIMR = I915_READ(IMR);
820 if (IS_IRONLAKE_M(dev))
821 ironlake_disable_drps(dev);
823 gen6_disable_rps(dev);
825 /* Cache mode state */
826 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
828 /* Memory Arbitration state */
829 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
832 for (i = 0; i < 16; i++) {
833 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
834 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
836 for (i = 0; i < 3; i++)
837 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
842 int i915_restore_state(struct drm_device *dev)
844 struct drm_i915_private *dev_priv = dev->dev_private;
847 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
849 /* Hardware status page */
850 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
852 i915_restore_display(dev);
854 /* Interrupt state */
855 if (HAS_PCH_SPLIT(dev)) {
856 I915_WRITE(DEIER, dev_priv->saveDEIER);
857 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
858 I915_WRITE(GTIER, dev_priv->saveGTIER);
859 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
860 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
861 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
863 I915_WRITE (IER, dev_priv->saveIER);
864 I915_WRITE (IMR, dev_priv->saveIMR);
867 /* Clock gating state */
868 intel_enable_clock_gating(dev);
870 if (IS_IRONLAKE_M(dev)) {
871 ironlake_enable_drps(dev);
872 intel_init_emon(dev);
876 gen6_enable_rps(dev_priv);
878 /* Cache mode state */
879 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
881 /* Memory arbitration state */
882 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
884 for (i = 0; i < 16; i++) {
885 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
886 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
888 for (i = 0; i < 3; i++)
889 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
891 intel_i2c_reset(dev);