2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
54 * The struct i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct i915_audio_component_ops *ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
63 } hdmi_audio_clock[] = {
64 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
67 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
69 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
72 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
76 /* HDMI N/CTS table */
77 #define TMDS_297M 297000
78 #define TMDS_296M 296703
85 { 44100, TMDS_296M, 4459, 234375 },
86 { 44100, TMDS_297M, 4704, 247500 },
87 { 48000, TMDS_296M, 5824, 281250 },
88 { 48000, TMDS_297M, 5120, 247500 },
89 { 32000, TMDS_296M, 5824, 421875 },
90 { 32000, TMDS_297M, 3072, 222750 },
91 { 88200, TMDS_296M, 8918, 234375 },
92 { 88200, TMDS_297M, 9408, 247500 },
93 { 96000, TMDS_296M, 11648, 281250 },
94 { 96000, TMDS_297M, 10240, 247500 },
95 { 176400, TMDS_296M, 17836, 234375 },
96 { 176400, TMDS_297M, 18816, 247500 },
97 { 192000, TMDS_296M, 23296, 281250 },
98 { 192000, TMDS_297M, 20480, 247500 },
101 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
102 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
106 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
107 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
111 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
112 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
113 adjusted_mode->crtc_clock);
117 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
118 hdmi_audio_clock[i].clock,
119 hdmi_audio_clock[i].config);
121 return hdmi_audio_clock[i].config;
124 static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
128 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
129 if ((rate == aud_ncts[i].sample_rate) &&
130 (mode->clock == aud_ncts[i].clock)) {
131 return aud_ncts[i].n;
137 static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
143 n_up = (n >> 12) & 0xff;
144 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
145 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
146 (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
147 AUD_CONFIG_N_PROG_ENABLE);
151 /* check whether N/CTS/M need be set manually */
152 static bool audio_rate_need_prog(struct intel_crtc *crtc,
153 const struct drm_display_mode *mode)
155 if (((mode->clock == TMDS_297M) ||
156 (mode->clock == TMDS_296M)) &&
157 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
163 static bool intel_eld_uptodate(struct drm_connector *connector,
164 int reg_eldv, uint32_t bits_eldv,
165 int reg_elda, uint32_t bits_elda,
168 struct drm_i915_private *dev_priv = connector->dev->dev_private;
169 uint8_t *eld = connector->eld;
173 tmp = I915_READ(reg_eldv);
179 tmp = I915_READ(reg_elda);
181 I915_WRITE(reg_elda, tmp);
183 for (i = 0; i < drm_eld_size(eld) / 4; i++)
184 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
190 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
192 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
195 DRM_DEBUG_KMS("Disable audio codec\n");
197 tmp = I915_READ(G4X_AUD_VID_DID);
198 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
199 eldv = G4X_ELDV_DEVCL_DEVBLC;
201 eldv = G4X_ELDV_DEVCTG;
204 tmp = I915_READ(G4X_AUD_CNTL_ST);
206 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
209 static void g4x_audio_codec_enable(struct drm_connector *connector,
210 struct intel_encoder *encoder,
211 const struct drm_display_mode *adjusted_mode)
213 struct drm_i915_private *dev_priv = connector->dev->dev_private;
214 uint8_t *eld = connector->eld;
219 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
221 tmp = I915_READ(G4X_AUD_VID_DID);
222 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
223 eldv = G4X_ELDV_DEVCL_DEVBLC;
225 eldv = G4X_ELDV_DEVCTG;
227 if (intel_eld_uptodate(connector,
228 G4X_AUD_CNTL_ST, eldv,
229 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
233 tmp = I915_READ(G4X_AUD_CNTL_ST);
234 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
235 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
236 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
238 len = min(drm_eld_size(eld) / 4, len);
239 DRM_DEBUG_DRIVER("ELD size %d\n", len);
240 for (i = 0; i < len; i++)
241 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
243 tmp = I915_READ(G4X_AUD_CNTL_ST);
245 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
248 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
250 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
251 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
252 enum pipe pipe = intel_crtc->pipe;
255 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
257 mutex_lock(&dev_priv->av_mutex);
259 /* Disable timestamps */
260 tmp = I915_READ(HSW_AUD_CFG(pipe));
261 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
262 tmp |= AUD_CONFIG_N_PROG_ENABLE;
263 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
264 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
265 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
266 tmp |= AUD_CONFIG_N_VALUE_INDEX;
267 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
270 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
271 tmp &= ~AUDIO_ELD_VALID(pipe);
272 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
273 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
275 mutex_unlock(&dev_priv->av_mutex);
278 static void hsw_audio_codec_enable(struct drm_connector *connector,
279 struct intel_encoder *encoder,
280 const struct drm_display_mode *adjusted_mode)
282 struct drm_i915_private *dev_priv = connector->dev->dev_private;
283 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
284 enum pipe pipe = intel_crtc->pipe;
285 struct i915_audio_component *acomp = dev_priv->audio_component;
286 const uint8_t *eld = connector->eld;
287 struct intel_digital_port *intel_dig_port =
288 enc_to_dig_port(&encoder->base);
289 enum port port = intel_dig_port->port;
294 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
295 pipe_name(pipe), drm_eld_size(eld));
297 mutex_lock(&dev_priv->av_mutex);
299 /* Enable audio presence detect, invalidate ELD */
300 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
301 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
302 tmp &= ~AUDIO_ELD_VALID(pipe);
303 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
306 * FIXME: We're supposed to wait for vblank here, but we have vblanks
307 * disabled during the mode set. The proper fix would be to push the
308 * rest of the setup into a vblank work item, queued here, but the
309 * infrastructure is not there yet.
312 /* Reset ELD write address */
313 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
314 tmp &= ~IBX_ELD_ADDRESS_MASK;
315 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
317 /* Up to 84 bytes of hw ELD buffer */
318 len = min(drm_eld_size(eld), 84);
319 for (i = 0; i < len / 4; i++)
320 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
323 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
324 tmp |= AUDIO_ELD_VALID(pipe);
325 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
327 /* Enable timestamps */
328 tmp = I915_READ(HSW_AUD_CFG(pipe));
329 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
330 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
331 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
332 tmp |= AUD_CONFIG_N_VALUE_INDEX;
334 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
336 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
337 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
340 else if (port >= PORT_A && port <= PORT_E)
341 rate = acomp->aud_sample_rate[port];
343 DRM_ERROR("invalid port: %d\n", port);
346 n = audio_config_get_n(adjusted_mode, rate);
348 tmp = audio_config_setup_n_reg(n, tmp);
350 DRM_DEBUG_KMS("no suitable N value is found\n");
353 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
355 mutex_unlock(&dev_priv->av_mutex);
358 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
360 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
361 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
362 struct intel_digital_port *intel_dig_port =
363 enc_to_dig_port(&encoder->base);
364 enum port port = intel_dig_port->port;
365 enum pipe pipe = intel_crtc->pipe;
370 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
371 port_name(port), pipe_name(pipe));
373 if (WARN_ON(port == PORT_A))
376 if (HAS_PCH_IBX(dev_priv->dev)) {
377 aud_config = IBX_AUD_CFG(pipe);
378 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
379 } else if (IS_VALLEYVIEW(dev_priv)) {
380 aud_config = VLV_AUD_CFG(pipe);
381 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
383 aud_config = CPT_AUD_CFG(pipe);
384 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
387 /* Disable timestamps */
388 tmp = I915_READ(aud_config);
389 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
390 tmp |= AUD_CONFIG_N_PROG_ENABLE;
391 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
392 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
393 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
394 tmp |= AUD_CONFIG_N_VALUE_INDEX;
395 I915_WRITE(aud_config, tmp);
397 eldv = IBX_ELD_VALID(port);
400 tmp = I915_READ(aud_cntrl_st2);
402 I915_WRITE(aud_cntrl_st2, tmp);
405 static void ilk_audio_codec_enable(struct drm_connector *connector,
406 struct intel_encoder *encoder,
407 const struct drm_display_mode *adjusted_mode)
409 struct drm_i915_private *dev_priv = connector->dev->dev_private;
410 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
411 struct intel_digital_port *intel_dig_port =
412 enc_to_dig_port(&encoder->base);
413 enum port port = intel_dig_port->port;
414 enum pipe pipe = intel_crtc->pipe;
415 uint8_t *eld = connector->eld;
424 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
425 port_name(port), pipe_name(pipe), drm_eld_size(eld));
427 if (WARN_ON(port == PORT_A))
431 * FIXME: We're supposed to wait for vblank here, but we have vblanks
432 * disabled during the mode set. The proper fix would be to push the
433 * rest of the setup into a vblank work item, queued here, but the
434 * infrastructure is not there yet.
437 if (HAS_PCH_IBX(connector->dev)) {
438 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
439 aud_config = IBX_AUD_CFG(pipe);
440 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
441 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
442 } else if (IS_VALLEYVIEW(connector->dev)) {
443 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
444 aud_config = VLV_AUD_CFG(pipe);
445 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
446 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
448 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
449 aud_config = CPT_AUD_CFG(pipe);
450 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
451 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
454 eldv = IBX_ELD_VALID(port);
457 tmp = I915_READ(aud_cntrl_st2);
459 I915_WRITE(aud_cntrl_st2, tmp);
461 /* Reset ELD write address */
462 tmp = I915_READ(aud_cntl_st);
463 tmp &= ~IBX_ELD_ADDRESS_MASK;
464 I915_WRITE(aud_cntl_st, tmp);
466 /* Up to 84 bytes of hw ELD buffer */
467 len = min(drm_eld_size(eld), 84);
468 for (i = 0; i < len / 4; i++)
469 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
472 tmp = I915_READ(aud_cntrl_st2);
474 I915_WRITE(aud_cntrl_st2, tmp);
476 /* Enable timestamps */
477 tmp = I915_READ(aud_config);
478 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
479 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
480 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
481 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
482 tmp |= AUD_CONFIG_N_VALUE_INDEX;
484 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
485 I915_WRITE(aud_config, tmp);
489 * intel_audio_codec_enable - Enable the audio codec for HD audio
490 * @intel_encoder: encoder on which to enable audio
492 * The enable sequences may only be performed after enabling the transcoder and
493 * port, and after completed link training.
495 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
497 struct drm_encoder *encoder = &intel_encoder->base;
498 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
499 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
500 struct drm_connector *connector;
501 struct drm_device *dev = encoder->dev;
502 struct drm_i915_private *dev_priv = dev->dev_private;
503 struct i915_audio_component *acomp = dev_priv->audio_component;
504 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
505 enum port port = intel_dig_port->port;
507 connector = drm_select_eld(encoder);
511 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
514 connector->encoder->base.id,
515 connector->encoder->name);
518 connector->eld[5] &= ~(3 << 2);
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
520 connector->eld[5] |= (1 << 2);
522 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
524 if (dev_priv->display.audio_codec_enable)
525 dev_priv->display.audio_codec_enable(connector, intel_encoder,
528 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
529 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
533 * intel_audio_codec_disable - Disable the audio codec for HD audio
534 * @intel_encoder: encoder on which to disable audio
536 * The disable sequences must be performed before disabling the transcoder or
539 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
541 struct drm_encoder *encoder = &intel_encoder->base;
542 struct drm_device *dev = encoder->dev;
543 struct drm_i915_private *dev_priv = dev->dev_private;
544 struct i915_audio_component *acomp = dev_priv->audio_component;
545 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
546 enum port port = intel_dig_port->port;
548 if (dev_priv->display.audio_codec_disable)
549 dev_priv->display.audio_codec_disable(intel_encoder);
551 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
552 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
556 * intel_init_audio - Set up chip specific audio functions
559 void intel_init_audio(struct drm_device *dev)
561 struct drm_i915_private *dev_priv = dev->dev_private;
564 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
565 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
566 } else if (IS_VALLEYVIEW(dev)) {
567 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
568 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
569 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
570 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
571 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
572 } else if (HAS_PCH_SPLIT(dev)) {
573 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
574 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
578 static void i915_audio_component_get_power(struct device *dev)
580 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
583 static void i915_audio_component_put_power(struct device *dev)
585 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
588 static void i915_audio_component_codec_wake_override(struct device *dev,
591 struct drm_i915_private *dev_priv = dev_to_i915(dev);
594 if (!IS_SKYLAKE(dev_priv))
598 * Enable/disable generating the codec wake signal, overriding the
599 * internal logic to generate the codec wake to controller.
601 tmp = I915_READ(HSW_AUD_CHICKENBIT);
602 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
603 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
604 usleep_range(1000, 1500);
607 tmp = I915_READ(HSW_AUD_CHICKENBIT);
608 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
609 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
610 usleep_range(1000, 1500);
614 /* Get CDCLK in kHz */
615 static int i915_audio_component_get_cdclk_freq(struct device *dev)
617 struct drm_i915_private *dev_priv = dev_to_i915(dev);
620 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
623 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
624 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
626 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
631 static int i915_audio_component_sync_audio_rate(struct device *dev,
634 struct drm_i915_private *dev_priv = dev_to_i915(dev);
635 struct drm_device *drm_dev = dev_priv->dev;
636 struct intel_encoder *intel_encoder;
637 struct intel_digital_port *intel_dig_port;
638 struct intel_crtc *crtc;
639 struct drm_display_mode *mode;
640 struct i915_audio_component *acomp = dev_priv->audio_component;
645 /* HSW, BDW SKL need this fix */
646 if (!IS_SKYLAKE(dev_priv) &&
647 !IS_BROADWELL(dev_priv) &&
648 !IS_HASWELL(dev_priv))
651 mutex_lock(&dev_priv->av_mutex);
652 /* 1. get the pipe */
653 for_each_intel_encoder(drm_dev, intel_encoder) {
654 if (intel_encoder->type != INTEL_OUTPUT_HDMI)
656 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
657 if (port == intel_dig_port->port) {
658 crtc = to_intel_crtc(intel_encoder->base.crtc);
660 DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__);
668 if (pipe == INVALID_PIPE) {
669 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
670 mutex_unlock(&dev_priv->av_mutex);
673 DRM_DEBUG_KMS("pipe %c connects port %c\n",
674 pipe_name(pipe), port_name(port));
675 mode = &crtc->config->base.adjusted_mode;
677 /* port must be valid now, otherwise the pipe will be invalid */
678 acomp->aud_sample_rate[port] = rate;
680 /* 2. check whether to set the N/CTS/M manually or not */
681 if (!audio_rate_need_prog(crtc, mode)) {
682 tmp = I915_READ(HSW_AUD_CFG(pipe));
683 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
684 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
685 mutex_unlock(&dev_priv->av_mutex);
689 n = audio_config_get_n(mode, rate);
691 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
693 tmp = I915_READ(HSW_AUD_CFG(pipe));
694 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
695 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
696 mutex_unlock(&dev_priv->av_mutex);
700 /* 3. set the N/CTS/M */
701 tmp = I915_READ(HSW_AUD_CFG(pipe));
702 tmp = audio_config_setup_n_reg(n, tmp);
703 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
705 mutex_unlock(&dev_priv->av_mutex);
709 static const struct i915_audio_component_ops i915_audio_component_ops = {
710 .owner = THIS_MODULE,
711 .get_power = i915_audio_component_get_power,
712 .put_power = i915_audio_component_put_power,
713 .codec_wake_override = i915_audio_component_codec_wake_override,
714 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
715 .sync_audio_rate = i915_audio_component_sync_audio_rate,
718 static int i915_audio_component_bind(struct device *i915_dev,
719 struct device *hda_dev, void *data)
721 struct i915_audio_component *acomp = data;
722 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
725 if (WARN_ON(acomp->ops || acomp->dev))
728 drm_modeset_lock_all(dev_priv->dev);
729 acomp->ops = &i915_audio_component_ops;
730 acomp->dev = i915_dev;
731 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
732 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
733 acomp->aud_sample_rate[i] = 0;
734 dev_priv->audio_component = acomp;
735 drm_modeset_unlock_all(dev_priv->dev);
740 static void i915_audio_component_unbind(struct device *i915_dev,
741 struct device *hda_dev, void *data)
743 struct i915_audio_component *acomp = data;
744 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
746 drm_modeset_lock_all(dev_priv->dev);
749 dev_priv->audio_component = NULL;
750 drm_modeset_unlock_all(dev_priv->dev);
753 static const struct component_ops i915_audio_component_bind_ops = {
754 .bind = i915_audio_component_bind,
755 .unbind = i915_audio_component_unbind,
759 * i915_audio_component_init - initialize and register the audio component
760 * @dev_priv: i915 device instance
762 * This will register with the component framework a child component which
763 * will bind dynamically to the snd_hda_intel driver's corresponding master
764 * component when the latter is registered. During binding the child
765 * initializes an instance of struct i915_audio_component which it receives
766 * from the master. The master can then start to use the interface defined by
767 * this struct. Each side can break the binding at any point by deregistering
768 * its own component after which each side's component unbind callback is
771 * We ignore any error during registration and continue with reduced
772 * functionality (i.e. without HDMI audio).
774 void i915_audio_component_init(struct drm_i915_private *dev_priv)
778 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
780 DRM_ERROR("failed to add audio component (%d)\n", ret);
781 /* continue with reduced functionality */
785 dev_priv->audio_component_registered = true;
789 * i915_audio_component_cleanup - deregister the audio component
790 * @dev_priv: i915 device instance
792 * Deregisters the audio component, breaking any existing binding to the
793 * corresponding snd_hda_intel driver's master component.
795 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
797 if (!dev_priv->audio_component_registered)
800 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
801 dev_priv->audio_component_registered = false;