2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
26 * the VBT from the rest of the driver. Add the parsed, clean data to struct
27 * intel_vbt_data within struct drm_i915_private.
30 #ifndef _INTEL_BIOS_H_
31 #define _INTEL_BIOS_H_
33 struct edp_power_seq {
41 /* MIPI Sequence Block definitions */
44 MIPI_SEQ_ASSERT_RESET,
48 MIPI_SEQ_DEASSERT_RESET,
49 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
50 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
51 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
52 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */
53 MIPI_SEQ_POWER_ON, /* sequence block v3+ */
54 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */
58 enum mipi_seq_element {
59 MIPI_SEQ_ELEM_END = 0,
60 MIPI_SEQ_ELEM_SEND_PKT,
63 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */
64 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */
65 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */
69 #define MIPI_DSI_UNDEFINED_PANEL_ID 0
70 #define MIPI_DSI_GENERIC_PANEL_ID 1
76 u32 enable_dithering:1;
80 u32 panel_arch_type:2;
83 #define NON_BURST_SYNC_PULSE 0x1
84 #define NON_BURST_SYNC_EVENTS 0x2
85 #define BURST_MODE 0x3
86 u32 video_transfer_mode:2;
89 #define PPS_BLC_PMIC 0
94 #define PIXEL_FORMAT_RGB565 0x1
95 #define PIXEL_FORMAT_RGB666 0x2
96 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
97 #define PIXEL_FORMAT_RGB888 0x4
98 u32 videomode_color_format:4;
101 #define ENABLE_ROTATION_0 0x0
102 #define ENABLE_ROTATION_90 0x1
103 #define ENABLE_ROTATION_180 0x2
104 #define ENABLE_ROTATION_270 0x3
109 /* 2 byte Port Description */
110 #define DUAL_LINK_NOT_SUPPORTED 0
111 #define DUAL_LINK_FRONT_BACK 1
112 #define DUAL_LINK_PIXEL_ALT 2
121 u32 target_burst_mode_freq;
125 #define BYTE_CLK_SEL_20MHZ 0
126 #define BYTE_CLK_SEL_10MHZ 1
127 #define BYTE_CLK_SEL_5MHZ 2
133 u16 dphy_param_valid:1;
134 u16 eot_pkt_disabled:1;
135 u16 enable_clk_stop:1;
140 u32 turn_around_timeout;
141 u32 device_reset_timer;
142 u32 master_init_timer;
146 /* 4 byte Dphy Params */
155 u32 clk_lane_switch_cnt;
160 /* timings based on dphy spec */
169 u16 tclk_prepare_clkzero;
175 u16 ths_prepare_hszero;
194 /* all delays have a unit of 100us */
195 struct mipi_pps_data {
198 u16 bl_disable_delay;
200 u16 panel_power_cycle_delay;
203 #endif /* _INTEL_BIOS_H_ */