2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_edid.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
38 /* Here's the desired hotplug mode */
39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
44 ADPA_CRT_HOTPLUG_ENABLE)
47 struct intel_encoder base;
48 /* DPMS state is stored in the connector, which we need in the
49 * encoder's enable/disable callbacks */
50 struct intel_connector *connector;
51 bool force_hotplug_required;
55 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
57 return container_of(intel_attached_encoder(connector),
58 struct intel_crt, base);
61 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
63 return container_of(encoder, struct intel_crt, base);
66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
69 struct drm_device *dev = encoder->base.dev;
70 struct drm_i915_private *dev_priv = dev->dev_private;
71 struct intel_crt *crt = intel_encoder_to_crt(encoder);
74 tmp = I915_READ(crt->adpa_reg);
76 if (!(tmp & ADPA_DAC_ENABLE))
80 *pipe = PORT_TO_PIPE_CPT(tmp);
82 *pipe = PORT_TO_PIPE(tmp);
87 /* Note: The caller is required to filter out dpms modes not supported by the
89 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
91 struct drm_device *dev = encoder->base.dev;
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct intel_crt *crt = intel_encoder_to_crt(encoder);
96 temp = I915_READ(crt->adpa_reg);
97 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
98 temp &= ~ADPA_DAC_ENABLE;
101 case DRM_MODE_DPMS_ON:
102 temp |= ADPA_DAC_ENABLE;
104 case DRM_MODE_DPMS_STANDBY:
105 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
107 case DRM_MODE_DPMS_SUSPEND:
108 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
110 case DRM_MODE_DPMS_OFF:
111 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
115 I915_WRITE(crt->adpa_reg, temp);
118 static void intel_disable_crt(struct intel_encoder *encoder)
120 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
123 static void intel_enable_crt(struct intel_encoder *encoder)
125 struct intel_crt *crt = intel_encoder_to_crt(encoder);
127 intel_crt_set_dpms(encoder, crt->connector->base.dpms);
131 static void intel_crt_dpms(struct drm_connector *connector, int mode)
133 struct drm_device *dev = connector->dev;
134 struct intel_encoder *encoder = intel_attached_encoder(connector);
135 struct drm_crtc *crtc;
138 /* PCH platforms and VLV only support on/off. */
139 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
140 mode = DRM_MODE_DPMS_OFF;
142 if (mode == connector->dpms)
145 old_dpms = connector->dpms;
146 connector->dpms = mode;
148 /* Only need to change hw state when actually enabled */
149 crtc = encoder->base.crtc;
151 encoder->connectors_active = false;
155 /* We need the pipe to run for anything but OFF. */
156 if (mode == DRM_MODE_DPMS_OFF)
157 encoder->connectors_active = false;
159 encoder->connectors_active = true;
161 if (mode < old_dpms) {
162 /* From off to on, enable the pipe first. */
163 intel_crtc_update_dpms(crtc);
165 intel_crt_set_dpms(encoder, mode);
167 intel_crt_set_dpms(encoder, mode);
169 intel_crtc_update_dpms(crtc);
172 intel_modeset_check_state(connector->dev);
175 static int intel_crt_mode_valid(struct drm_connector *connector,
176 struct drm_display_mode *mode)
178 struct drm_device *dev = connector->dev;
181 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
182 return MODE_NO_DBLESCAN;
184 if (mode->clock < 25000)
185 return MODE_CLOCK_LOW;
191 if (mode->clock > max_clock)
192 return MODE_CLOCK_HIGH;
194 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
195 if (HAS_PCH_LPT(dev) &&
196 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
197 return MODE_CLOCK_HIGH;
202 static bool intel_crt_compute_config(struct intel_encoder *encoder,
203 struct intel_crtc_config *pipe_config)
205 struct drm_device *dev = encoder->base.dev;
207 if (HAS_PCH_SPLIT(dev))
208 pipe_config->has_pch_encoder = true;
210 /* LPT FDI RX only supports 8bpc. */
211 if (HAS_PCH_LPT(dev))
212 pipe_config->pipe_bpp = 24;
217 static void intel_crt_mode_set(struct drm_encoder *encoder,
218 struct drm_display_mode *mode,
219 struct drm_display_mode *adjusted_mode)
222 struct drm_device *dev = encoder->dev;
223 struct drm_crtc *crtc = encoder->crtc;
224 struct intel_crt *crt =
225 intel_encoder_to_crt(to_intel_encoder(encoder));
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 struct drm_i915_private *dev_priv = dev->dev_private;
230 if (HAS_PCH_SPLIT(dev))
231 adpa = ADPA_HOTPLUG_BITS;
235 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
236 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
237 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
238 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
240 /* For CPT allow 3 pipe config, for others just use A or B */
241 if (HAS_PCH_LPT(dev))
242 ; /* Those bits don't exist here */
243 else if (HAS_PCH_CPT(dev))
244 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
245 else if (intel_crtc->pipe == 0)
246 adpa |= ADPA_PIPE_A_SELECT;
248 adpa |= ADPA_PIPE_B_SELECT;
250 if (!HAS_PCH_SPLIT(dev))
251 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
253 I915_WRITE(crt->adpa_reg, adpa);
256 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
258 struct drm_device *dev = connector->dev;
259 struct intel_crt *crt = intel_attached_crt(connector);
260 struct drm_i915_private *dev_priv = dev->dev_private;
264 /* The first time through, trigger an explicit detection cycle */
265 if (crt->force_hotplug_required) {
266 bool turn_off_dac = HAS_PCH_SPLIT(dev);
269 crt->force_hotplug_required = 0;
271 save_adpa = adpa = I915_READ(crt->adpa_reg);
272 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
274 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
276 adpa &= ~ADPA_DAC_ENABLE;
278 I915_WRITE(crt->adpa_reg, adpa);
280 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
282 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
285 I915_WRITE(crt->adpa_reg, save_adpa);
286 POSTING_READ(crt->adpa_reg);
290 /* Check the status to see if both blue and green are on now */
291 adpa = I915_READ(crt->adpa_reg);
292 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
296 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
301 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
303 struct drm_device *dev = connector->dev;
304 struct intel_crt *crt = intel_attached_crt(connector);
305 struct drm_i915_private *dev_priv = dev->dev_private;
310 save_adpa = adpa = I915_READ(crt->adpa_reg);
311 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
313 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
315 I915_WRITE(crt->adpa_reg, adpa);
317 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
319 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
320 I915_WRITE(crt->adpa_reg, save_adpa);
323 /* Check the status to see if both blue and green are on now */
324 adpa = I915_READ(crt->adpa_reg);
325 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
330 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
332 /* FIXME: debug force function and remove */
339 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
341 * Not for i915G/i915GM
343 * \return true if CRT is connected.
344 * \return false if CRT is disconnected.
346 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
348 struct drm_device *dev = connector->dev;
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 hotplug_en, orig, stat;
354 if (HAS_PCH_SPLIT(dev))
355 return intel_ironlake_crt_detect_hotplug(connector);
357 if (IS_VALLEYVIEW(dev))
358 return valleyview_crt_detect_hotplug(connector);
361 * On 4 series desktop, CRT detect sequence need to be done twice
362 * to get a reliable result.
365 if (IS_G4X(dev) && !IS_GM45(dev))
369 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
370 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
372 for (i = 0; i < tries ; i++) {
373 /* turn on the FORCE_DETECT */
374 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
375 /* wait for FORCE_DETECT to go off */
376 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
377 CRT_HOTPLUG_FORCE_DETECT) == 0,
379 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
382 stat = I915_READ(PORT_HOTPLUG_STAT);
383 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
386 /* clear the interrupt we just generated, if any */
387 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
389 /* and put the bits back */
390 I915_WRITE(PORT_HOTPLUG_EN, orig);
395 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
396 struct i2c_adapter *i2c)
400 edid = drm_get_edid(connector, i2c);
402 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
403 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
404 intel_gmbus_force_bit(i2c, true);
405 edid = drm_get_edid(connector, i2c);
406 intel_gmbus_force_bit(i2c, false);
412 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
413 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
414 struct i2c_adapter *adapter)
419 edid = intel_crt_get_edid(connector, adapter);
423 ret = intel_connector_update_modes(connector, edid);
429 static bool intel_crt_detect_ddc(struct drm_connector *connector)
431 struct intel_crt *crt = intel_attached_crt(connector);
432 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
434 struct i2c_adapter *i2c;
436 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
438 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
439 edid = intel_crt_get_edid(connector, i2c);
442 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
445 * This may be a DVI-I connector with a shared DDC
446 * link between analog and digital outputs, so we
447 * have to check the EDID input spec of the attached device.
450 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
454 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
456 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
464 static enum drm_connector_status
465 intel_crt_load_detect(struct intel_crt *crt)
467 struct drm_device *dev = crt->base.base.dev;
468 struct drm_i915_private *dev_priv = dev->dev_private;
469 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
470 uint32_t save_bclrpat;
471 uint32_t save_vtotal;
472 uint32_t vtotal, vactive;
474 uint32_t vblank, vblank_start, vblank_end;
476 uint32_t bclrpat_reg;
480 uint32_t pipeconf_reg;
481 uint32_t pipe_dsl_reg;
483 enum drm_connector_status status;
485 DRM_DEBUG_KMS("starting load-detect on CRT\n");
487 bclrpat_reg = BCLRPAT(pipe);
488 vtotal_reg = VTOTAL(pipe);
489 vblank_reg = VBLANK(pipe);
490 vsync_reg = VSYNC(pipe);
491 pipeconf_reg = PIPECONF(pipe);
492 pipe_dsl_reg = PIPEDSL(pipe);
494 save_bclrpat = I915_READ(bclrpat_reg);
495 save_vtotal = I915_READ(vtotal_reg);
496 vblank = I915_READ(vblank_reg);
498 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
499 vactive = (save_vtotal & 0x7ff) + 1;
501 vblank_start = (vblank & 0xfff) + 1;
502 vblank_end = ((vblank >> 16) & 0xfff) + 1;
504 /* Set the border color to purple. */
505 I915_WRITE(bclrpat_reg, 0x500050);
508 uint32_t pipeconf = I915_READ(pipeconf_reg);
509 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
510 POSTING_READ(pipeconf_reg);
511 /* Wait for next Vblank to substitue
512 * border color for Color info */
513 intel_wait_for_vblank(dev, pipe);
514 st00 = I915_READ8(VGA_MSR_WRITE);
515 status = ((st00 & (1 << 4)) != 0) ?
516 connector_status_connected :
517 connector_status_disconnected;
519 I915_WRITE(pipeconf_reg, pipeconf);
521 bool restore_vblank = false;
525 * If there isn't any border, add some.
526 * Yes, this will flicker
528 if (vblank_start <= vactive && vblank_end >= vtotal) {
529 uint32_t vsync = I915_READ(vsync_reg);
530 uint32_t vsync_start = (vsync & 0xffff) + 1;
532 vblank_start = vsync_start;
533 I915_WRITE(vblank_reg,
535 ((vblank_end - 1) << 16));
536 restore_vblank = true;
538 /* sample in the vertical border, selecting the larger one */
539 if (vblank_start - vactive >= vtotal - vblank_end)
540 vsample = (vblank_start + vactive) >> 1;
542 vsample = (vtotal + vblank_end) >> 1;
545 * Wait for the border to be displayed
547 while (I915_READ(pipe_dsl_reg) >= vactive)
549 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
552 * Watch ST00 for an entire scanline
558 /* Read the ST00 VGA status register */
559 st00 = I915_READ8(VGA_MSR_WRITE);
562 } while ((I915_READ(pipe_dsl_reg) == dsl));
564 /* restore vblank if necessary */
566 I915_WRITE(vblank_reg, vblank);
568 * If more than 3/4 of the scanline detected a monitor,
569 * then it is assumed to be present. This works even on i830,
570 * where there isn't any way to force the border color across
573 status = detect * 4 > count * 3 ?
574 connector_status_connected :
575 connector_status_disconnected;
578 /* Restore previous settings */
579 I915_WRITE(bclrpat_reg, save_bclrpat);
584 static enum drm_connector_status
585 intel_crt_detect(struct drm_connector *connector, bool force)
587 struct drm_device *dev = connector->dev;
588 struct intel_crt *crt = intel_attached_crt(connector);
589 enum drm_connector_status status;
590 struct intel_load_detect_pipe tmp;
592 if (I915_HAS_HOTPLUG(dev)) {
593 /* We can not rely on the HPD pin always being correctly wired
594 * up, for example many KVM do not pass it through, and so
595 * only trust an assertion that the monitor is connected.
597 if (intel_crt_detect_hotplug(connector)) {
598 DRM_DEBUG_KMS("CRT detected via hotplug\n");
599 return connector_status_connected;
601 DRM_DEBUG_KMS("CRT not detected via hotplug\n");
604 if (intel_crt_detect_ddc(connector))
605 return connector_status_connected;
607 /* Load detection is broken on HPD capable machines. Whoever wants a
608 * broken monitor (without edid) to work behind a broken kvm (that fails
609 * to have the right resistors for HP detection) needs to fix this up.
610 * For now just bail out. */
611 if (I915_HAS_HOTPLUG(dev))
612 return connector_status_disconnected;
615 return connector->status;
617 /* for pre-945g platforms use load detect */
618 if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
619 if (intel_crt_detect_ddc(connector))
620 status = connector_status_connected;
622 status = intel_crt_load_detect(crt);
623 intel_release_load_detect_pipe(connector, &tmp);
625 status = connector_status_unknown;
630 static void intel_crt_destroy(struct drm_connector *connector)
632 drm_sysfs_connector_remove(connector);
633 drm_connector_cleanup(connector);
637 static int intel_crt_get_modes(struct drm_connector *connector)
639 struct drm_device *dev = connector->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
642 struct i2c_adapter *i2c;
644 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
645 ret = intel_crt_ddc_get_modes(connector, i2c);
646 if (ret || !IS_G4X(dev))
649 /* Try to probe digital port for output in DVI-I -> VGA mode. */
650 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
651 return intel_crt_ddc_get_modes(connector, i2c);
654 static int intel_crt_set_property(struct drm_connector *connector,
655 struct drm_property *property,
661 static void intel_crt_reset(struct drm_connector *connector)
663 struct drm_device *dev = connector->dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
665 struct intel_crt *crt = intel_attached_crt(connector);
667 if (HAS_PCH_SPLIT(dev)) {
670 adpa = I915_READ(crt->adpa_reg);
671 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
672 adpa |= ADPA_HOTPLUG_BITS;
673 I915_WRITE(crt->adpa_reg, adpa);
674 POSTING_READ(crt->adpa_reg);
676 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
677 crt->force_hotplug_required = 1;
683 * Routines for controlling stuff on the analog port
686 static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
687 .mode_set = intel_crt_mode_set,
690 static const struct drm_connector_funcs intel_crt_connector_funcs = {
691 .reset = intel_crt_reset,
692 .dpms = intel_crt_dpms,
693 .detect = intel_crt_detect,
694 .fill_modes = drm_helper_probe_single_connector_modes,
695 .destroy = intel_crt_destroy,
696 .set_property = intel_crt_set_property,
699 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
700 .mode_valid = intel_crt_mode_valid,
701 .get_modes = intel_crt_get_modes,
702 .best_encoder = intel_best_encoder,
705 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
706 .destroy = intel_encoder_destroy,
709 static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
711 DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
715 static const struct dmi_system_id intel_no_crt[] = {
717 .callback = intel_no_crt_dmi_callback,
720 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
721 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
727 void intel_crt_init(struct drm_device *dev)
729 struct drm_connector *connector;
730 struct intel_crt *crt;
731 struct intel_connector *intel_connector;
732 struct drm_i915_private *dev_priv = dev->dev_private;
734 /* Skip machines without VGA that falsely report hotplug events */
735 if (dmi_check_system(intel_no_crt))
738 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
742 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
743 if (!intel_connector) {
748 connector = &intel_connector->base;
749 crt->connector = intel_connector;
750 drm_connector_init(dev, &intel_connector->base,
751 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
753 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
754 DRM_MODE_ENCODER_DAC);
756 intel_connector_attach_encoder(intel_connector, &crt->base);
758 crt->base.type = INTEL_OUTPUT_ANALOG;
759 crt->base.cloneable = true;
761 crt->base.crtc_mask = (1 << 0);
763 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
766 connector->interlace_allowed = 0;
768 connector->interlace_allowed = 1;
769 connector->doublescan_allowed = 0;
771 if (HAS_PCH_SPLIT(dev))
772 crt->adpa_reg = PCH_ADPA;
773 else if (IS_VALLEYVIEW(dev))
774 crt->adpa_reg = VLV_ADPA;
776 crt->adpa_reg = ADPA;
778 crt->base.compute_config = intel_crt_compute_config;
779 crt->base.disable = intel_disable_crt;
780 crt->base.enable = intel_enable_crt;
781 if (I915_HAS_HOTPLUG(dev))
782 crt->base.hpd_pin = HPD_CRT;
784 crt->base.get_hw_state = intel_ddi_get_hw_state;
786 crt->base.get_hw_state = intel_crt_get_hw_state;
787 intel_connector->get_hw_state = intel_connector_get_hw_state;
789 drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
790 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
792 drm_sysfs_connector_add(connector);
794 if (!I915_HAS_HOTPLUG(dev))
795 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
798 * Configure the automatic hotplug detection stuff
800 crt->force_hotplug_required = 0;
803 * TODO: find a proper way to discover whether we need to set the the
804 * polarity and link reversal bits or not, instead of relying on the
807 if (HAS_PCH_LPT(dev)) {
808 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
809 FDI_RX_LINK_REVERSAL_OVERRIDE;
811 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;