drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  *
  36  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  37  * FW_LOADED, FW_FAILED.
  38  *
  39  * Once the firmware is written into the registers status will be moved from
  40  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  41  * be moved to FW_FAILED.
  42  */
  43
  44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
  46
  47 MODULE_FIRMWARE(I915_CSR_SKL);
  48 MODULE_FIRMWARE(I915_CSR_BXT);
  49
  50 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 23)
  51
  52 #define CSR_MAX_FW_SIZE                 0x2FFF
  53 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  54
  55 struct intel_css_header {
  56         /* 0x09 for DMC */
  57         uint32_t module_type;
  58
  59         /* Includes the DMC specific header in dwords */
  60         uint32_t header_len;
  61
  62         /* always value would be 0x10000 */
  63         uint32_t header_ver;
  64
  65         /* Not used */
  66         uint32_t module_id;
  67
  68         /* Not used */
  69         uint32_t module_vendor;
  70
  71         /* in YYYYMMDD format */
  72         uint32_t date;
  73
  74         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  75         uint32_t size;
  76
  77         /* Not used */
  78         uint32_t key_size;
  79
  80         /* Not used */
  81         uint32_t modulus_size;
  82
  83         /* Not used */
  84         uint32_t exponent_size;
  85
  86         /* Not used */
  87         uint32_t reserved1[12];
  88
  89         /* Major Minor */
  90         uint32_t version;
  91
  92         /* Not used */
  93         uint32_t reserved2[8];
  94
  95         /* Not used */
  96         uint32_t kernel_header_info;
  97 } __packed;
  98
  99 struct intel_fw_info {
 100         uint16_t reserved1;
 101
 102         /* Stepping (A, B, C, ..., *). * is a wildcard */
 103         char stepping;
 104
 105         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 106         char substepping;
 107
 108         uint32_t offset;
 109         uint32_t reserved2;
 110 } __packed;
 111
 112 struct intel_package_header {
 113         /* DMC container header length in dwords */
 114         unsigned char header_len;
 115
 116         /* always value would be 0x01 */
 117         unsigned char header_ver;
 118
 119         unsigned char reserved[10];
 120
 121         /* Number of valid entries in the FWInfo array below */
 122         uint32_t num_entries;
 123
 124         struct intel_fw_info fw_info[20];
 125 } __packed;
 126
 127 struct intel_dmc_header {
 128         /* always value would be 0x40403E3E */
 129         uint32_t signature;
 130
 131         /* DMC binary header length */
 132         unsigned char header_len;
 133
 134         /* 0x01 */
 135         unsigned char header_ver;
 136
 137         /* Reserved */
 138         uint16_t dmcc_ver;
 139
 140         /* Major, Minor */
 141         uint32_t        project;
 142
 143         /* Firmware program size (excluding header) in dwords */
 144         uint32_t        fw_size;
 145
 146         /* Major Minor version */
 147         uint32_t fw_version;
 148
 149         /* Number of valid MMIO cycles present. */
 150         uint32_t mmio_count;
 151
 152         /* MMIO address */
 153         uint32_t mmioaddr[8];
 154
 155         /* MMIO data */
 156         uint32_t mmiodata[8];
 157
 158         /* FW filename  */
 159         unsigned char dfile[32];
 160
 161         uint32_t reserved1[2];
 162 } __packed;
 163
 164 struct stepping_info {
 165         char stepping;
 166         char substepping;
 167 };
 168
 169 static const struct stepping_info skl_stepping_info[] = {
 170         {'A', '0'}, {'B', '0'}, {'C', '0'},
 171         {'D', '0'}, {'E', '0'}, {'F', '0'},
 172         {'G', '0'}, {'H', '0'}, {'I', '0'}
 173 };
 174
 175 static const struct stepping_info bxt_stepping_info[] = {
 176         {'A', '0'}, {'A', '1'}, {'A', '2'},
 177         {'B', '0'}, {'B', '1'}, {'B', '2'}
 178 };
 179
 180 static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
 181 {
 182         const struct stepping_info *si;
 183         unsigned int size;
 184
 185         if (IS_SKYLAKE(dev)) {
 186                 size = ARRAY_SIZE(skl_stepping_info);
 187                 si = skl_stepping_info;
 188         } else if (IS_BROXTON(dev)) {
 189                 size = ARRAY_SIZE(bxt_stepping_info);
 190                 si = bxt_stepping_info;
 191         } else {
 192                 return NULL;
 193         }
 194
 195         if (INTEL_REVID(dev) < size)
 196                 return si + INTEL_REVID(dev);
 197
 198         return NULL;
 199 }
 200
 201 /**
 202  * intel_csr_load_program() - write the firmware from memory to register.
 203  * @dev_priv: i915 drm device.
 204  *
 205  * CSR firmware is read from a .bin file and kept in internal memory one time.
 206  * Everytime display comes back from low power state this function is called to
 207  * copy the firmware from internal memory to registers.
 208  */
 209 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 210 {
 211         u32 *payload = dev_priv->csr.dmc_payload;
 212         uint32_t i, fw_size;
 213
 214         if (!IS_GEN9(dev_priv)) {
 215                 DRM_ERROR("No CSR support available for this platform\n");
 216                 return;
 217         }
 218
 219         if (!dev_priv->csr.dmc_payload) {
 220                 DRM_ERROR("Tried to program CSR with empty payload\n");
 221                 return;
 222         }
 223
 224         fw_size = dev_priv->csr.dmc_fw_size;
 225         for (i = 0; i < fw_size; i++)
 226                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 227
 228         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 229                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 230                            dev_priv->csr.mmiodata[i]);
 231         }
 232 }
 233
 234 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 235                               const struct firmware *fw)
 236 {
 237         struct drm_device *dev = dev_priv->dev;
 238         struct intel_css_header *css_header;
 239         struct intel_package_header *package_header;
 240         struct intel_dmc_header *dmc_header;
 241         struct intel_csr *csr = &dev_priv->csr;
 242         const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
 243         char stepping, substepping;
 244         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 245         uint32_t i;
 246         uint32_t *dmc_payload;
 247
 248         if (!fw)
 249                 return NULL;
 250
 251         if (!stepping_info) {
 252                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
 253                 return NULL;
 254         }
 255
 256         stepping = stepping_info->stepping;
 257         substepping = stepping_info->substepping;
 258
 259         /* Extract CSS Header information*/
 260         css_header = (struct intel_css_header *)fw->data;
 261         if (sizeof(struct intel_css_header) !=
 262             (css_header->header_len * 4)) {
 263                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 264                           (css_header->header_len * 4));
 265                 return NULL;
 266         }
 267
 268         csr->version = css_header->version;
 269
 270         if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
 271                 DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
 272                          " please upgrade to v%u.%u or later"
 273                          " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
 274                          CSR_VERSION_MAJOR(csr->version),
 275                          CSR_VERSION_MINOR(csr->version),
 276                          CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
 277                          CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
 278                 return NULL;
 279         }
 280
 281         readcount += sizeof(struct intel_css_header);
 282
 283         /* Extract Package Header information*/
 284         package_header = (struct intel_package_header *)
 285                 &fw->data[readcount];
 286         if (sizeof(struct intel_package_header) !=
 287             (package_header->header_len * 4)) {
 288                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 289                           (package_header->header_len * 4));
 290                 return NULL;
 291         }
 292         readcount += sizeof(struct intel_package_header);
 293
 294         /* Search for dmc_offset to find firware binary. */
 295         for (i = 0; i < package_header->num_entries; i++) {
 296                 if (package_header->fw_info[i].substepping == '*' &&
 297                     stepping == package_header->fw_info[i].stepping) {
 298                         dmc_offset = package_header->fw_info[i].offset;
 299                         break;
 300                 } else if (stepping == package_header->fw_info[i].stepping &&
 301                         substepping == package_header->fw_info[i].substepping) {
 302                         dmc_offset = package_header->fw_info[i].offset;
 303                         break;
 304                 } else if (package_header->fw_info[i].stepping == '*' &&
 305                            package_header->fw_info[i].substepping == '*')
 306                         dmc_offset = package_header->fw_info[i].offset;
 307         }
 308         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 309                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
 310                 return NULL;
 311         }
 312         readcount += dmc_offset;
 313
 314         /* Extract dmc_header information. */
 315         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 316         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 317                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 318                           (dmc_header->header_len));
 319                 return NULL;
 320         }
 321         readcount += sizeof(struct intel_dmc_header);
 322
 323         /* Cache the dmc header info. */
 324         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 325                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 326                           dmc_header->mmio_count);
 327                 return NULL;
 328         }
 329         csr->mmio_count = dmc_header->mmio_count;
 330         for (i = 0; i < dmc_header->mmio_count; i++) {
 331                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 332                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 333                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 334                                   dmc_header->mmioaddr[i]);
 335                         return NULL;
 336                 }
 337                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 338                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 339         }
 340
 341         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 342         nbytes = dmc_header->fw_size * 4;
 343         if (nbytes > CSR_MAX_FW_SIZE) {
 344                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 345                 return NULL;
 346         }
 347         csr->dmc_fw_size = dmc_header->fw_size;
 348
 349         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 350         if (!dmc_payload) {
 351                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 352                 return NULL;
 353         }
 354
 355         memcpy(dmc_payload, &fw->data[readcount], nbytes);
 356
 357         return dmc_payload;
 358 }
 359
 360 static void csr_load_work_fn(struct work_struct *work)
 361 {
 362         struct drm_i915_private *dev_priv;
 363         struct intel_csr *csr;
 364         const struct firmware *fw;
 365         int ret;
 366
 367         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 368         csr = &dev_priv->csr;
 369
 370         ret = request_firmware(&fw, dev_priv->csr.fw_path,
 371                                &dev_priv->dev->pdev->dev);
 372         if (!fw)
 373                 goto out;
 374
 375         dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 376         if (!dev_priv->csr.dmc_payload)
 377                 goto out;
 378
 379         /* load csr program during system boot, as needed for DC states */
 380         intel_csr_load_program(dev_priv);
 381
 382 out:
 383         if (dev_priv->csr.dmc_payload) {
 384                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 385
 386                 DRM_INFO("Finished loading %s (v%u.%u)\n",
 387                          dev_priv->csr.fw_path,
 388                          CSR_VERSION_MAJOR(csr->version),
 389                          CSR_VERSION_MINOR(csr->version));
 390         } else {
 391                 DRM_ERROR("Failed to load DMC firmware, disabling rpm\n");
 392         }
 393
 394         release_firmware(fw);
 395 }
 396
 397 /**
 398  * intel_csr_ucode_init() - initialize the firmware loading.
 399  * @dev_priv: i915 drm device.
 400  *
 401  * This function is called at the time of loading the display driver to read
 402  * firmware from a .bin file and copied into a internal memory.
 403  */
 404 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 405 {
 406         struct intel_csr *csr = &dev_priv->csr;
 407
 408         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 409
 410         if (!HAS_CSR(dev_priv))
 411                 return;
 412
 413         if (IS_SKYLAKE(dev_priv))
 414                 csr->fw_path = I915_CSR_SKL;
 415         else if (IS_BROXTON(dev_priv))
 416                 csr->fw_path = I915_CSR_BXT;
 417         else {
 418                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 419                 return;
 420         }
 421
 422         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 423
 424         /*
 425          * Obtain a runtime pm reference, until CSR is loaded,
 426          * to avoid entering runtime-suspend.
 427          */
 428         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 429
 430         schedule_work(&dev_priv->csr.work);
 431 }
 432
 433 /**
 434  * intel_csr_ucode_fini() - unload the CSR firmware.
 435  * @dev_priv: i915 drm device.
 436  *
 437  * Firmmware unloading includes freeing the internal momory and reset the
 438  * firmware loading status.
 439  */
 440 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 441 {
 442         if (!HAS_CSR(dev_priv))
 443                 return;
 444
 445         flush_work(&dev_priv->csr.work);
 446
 447         kfree(dev_priv->csr.dmc_payload);
 448 }