2 * Copyright © 2014 Intel Corporation
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24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
37 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
38 MODULE_FIRMWARE(I915_CSR_KBL);
39 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
41 #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
42 MODULE_FIRMWARE(I915_CSR_SKL);
43 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
45 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
46 MODULE_FIRMWARE(I915_CSR_BXT);
47 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
49 #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
54 #define CSR_MAX_FW_SIZE 0x2FFF
55 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
57 struct intel_css_header {
61 /* Includes the DMC specific header in dwords */
64 /* always value would be 0x10000 */
71 uint32_t module_vendor;
73 /* in YYYYMMDD format */
76 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
83 uint32_t modulus_size;
86 uint32_t exponent_size;
89 uint32_t reserved1[12];
95 uint32_t reserved2[8];
98 uint32_t kernel_header_info;
101 struct intel_fw_info {
104 /* Stepping (A, B, C, ..., *). * is a wildcard */
107 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
114 struct intel_package_header {
115 /* DMC container header length in dwords */
116 unsigned char header_len;
118 /* always value would be 0x01 */
119 unsigned char header_ver;
121 unsigned char reserved[10];
123 /* Number of valid entries in the FWInfo array below */
124 uint32_t num_entries;
126 struct intel_fw_info fw_info[20];
129 struct intel_dmc_header {
130 /* always value would be 0x40403E3E */
133 /* DMC binary header length */
134 unsigned char header_len;
137 unsigned char header_ver;
145 /* Firmware program size (excluding header) in dwords */
148 /* Major Minor version */
151 /* Number of valid MMIO cycles present. */
155 uint32_t mmioaddr[8];
158 uint32_t mmiodata[8];
161 unsigned char dfile[32];
163 uint32_t reserved1[2];
166 struct stepping_info {
171 static const struct stepping_info skl_stepping_info[] = {
172 {'A', '0'}, {'B', '0'}, {'C', '0'},
173 {'D', '0'}, {'E', '0'}, {'F', '0'},
174 {'G', '0'}, {'H', '0'}, {'I', '0'},
175 {'J', '0'}, {'K', '0'}
178 static const struct stepping_info bxt_stepping_info[] = {
179 {'A', '0'}, {'A', '1'}, {'A', '2'},
180 {'B', '0'}, {'B', '1'}, {'B', '2'}
183 static const struct stepping_info no_stepping_info = { '*', '*' };
185 static const struct stepping_info *
186 intel_get_stepping_info(struct drm_i915_private *dev_priv)
188 const struct stepping_info *si;
191 if (IS_SKYLAKE(dev_priv)) {
192 size = ARRAY_SIZE(skl_stepping_info);
193 si = skl_stepping_info;
194 } else if (IS_BROXTON(dev_priv)) {
195 size = ARRAY_SIZE(bxt_stepping_info);
196 si = bxt_stepping_info;
201 if (INTEL_REVID(dev_priv) < size)
202 return si + INTEL_REVID(dev_priv);
204 return &no_stepping_info;
207 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
211 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
213 if (IS_BROXTON(dev_priv))
214 mask |= DC_STATE_DEBUG_MASK_CORES;
216 /* The below bit doesn't need to be cleared ever afterwards */
217 val = I915_READ(DC_STATE_DEBUG);
218 if ((val & mask) != mask) {
220 I915_WRITE(DC_STATE_DEBUG, val);
221 POSTING_READ(DC_STATE_DEBUG);
226 * intel_csr_load_program() - write the firmware from memory to register.
227 * @dev_priv: i915 drm device.
229 * CSR firmware is read from a .bin file and kept in internal memory one time.
230 * Everytime display comes back from low power state this function is called to
231 * copy the firmware from internal memory to registers.
233 void intel_csr_load_program(struct drm_i915_private *dev_priv)
235 u32 *payload = dev_priv->csr.dmc_payload;
238 if (!IS_GEN9(dev_priv)) {
239 DRM_ERROR("No CSR support available for this platform\n");
243 if (!dev_priv->csr.dmc_payload) {
244 DRM_ERROR("Tried to program CSR with empty payload\n");
248 fw_size = dev_priv->csr.dmc_fw_size;
249 for (i = 0; i < fw_size; i++)
250 I915_WRITE(CSR_PROGRAM(i), payload[i]);
252 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
253 I915_WRITE(dev_priv->csr.mmioaddr[i],
254 dev_priv->csr.mmiodata[i]);
257 dev_priv->csr.dc_state = 0;
259 gen9_set_dc_state_debugmask(dev_priv);
262 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
263 const struct firmware *fw)
265 struct intel_css_header *css_header;
266 struct intel_package_header *package_header;
267 struct intel_dmc_header *dmc_header;
268 struct intel_csr *csr = &dev_priv->csr;
269 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
270 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
272 uint32_t *dmc_payload;
273 uint32_t required_version;
278 /* Extract CSS Header information*/
279 css_header = (struct intel_css_header *)fw->data;
280 if (sizeof(struct intel_css_header) !=
281 (css_header->header_len * 4)) {
282 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
283 (css_header->header_len * 4));
287 csr->version = css_header->version;
289 if (IS_KABYLAKE(dev_priv)) {
290 required_version = KBL_CSR_VERSION_REQUIRED;
291 } else if (IS_SKYLAKE(dev_priv)) {
292 required_version = SKL_CSR_VERSION_REQUIRED;
293 } else if (IS_BROXTON(dev_priv)) {
294 required_version = BXT_CSR_VERSION_REQUIRED;
296 MISSING_CASE(INTEL_REVID(dev_priv));
297 required_version = 0;
300 if (csr->version != required_version) {
301 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
302 " please use v%u.%u [" FIRMWARE_URL "].\n",
303 CSR_VERSION_MAJOR(csr->version),
304 CSR_VERSION_MINOR(csr->version),
305 CSR_VERSION_MAJOR(required_version),
306 CSR_VERSION_MINOR(required_version));
310 readcount += sizeof(struct intel_css_header);
312 /* Extract Package Header information*/
313 package_header = (struct intel_package_header *)
314 &fw->data[readcount];
315 if (sizeof(struct intel_package_header) !=
316 (package_header->header_len * 4)) {
317 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
318 (package_header->header_len * 4));
321 readcount += sizeof(struct intel_package_header);
323 /* Search for dmc_offset to find firware binary. */
324 for (i = 0; i < package_header->num_entries; i++) {
325 if (package_header->fw_info[i].substepping == '*' &&
326 si->stepping == package_header->fw_info[i].stepping) {
327 dmc_offset = package_header->fw_info[i].offset;
329 } else if (si->stepping == package_header->fw_info[i].stepping &&
330 si->substepping == package_header->fw_info[i].substepping) {
331 dmc_offset = package_header->fw_info[i].offset;
333 } else if (package_header->fw_info[i].stepping == '*' &&
334 package_header->fw_info[i].substepping == '*')
335 dmc_offset = package_header->fw_info[i].offset;
337 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
338 DRM_ERROR("Firmware not supported for %c stepping\n",
342 readcount += dmc_offset;
344 /* Extract dmc_header information. */
345 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
346 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
347 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
348 (dmc_header->header_len));
351 readcount += sizeof(struct intel_dmc_header);
353 /* Cache the dmc header info. */
354 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
355 DRM_ERROR("Firmware has wrong mmio count %u\n",
356 dmc_header->mmio_count);
359 csr->mmio_count = dmc_header->mmio_count;
360 for (i = 0; i < dmc_header->mmio_count; i++) {
361 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
362 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
363 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
364 dmc_header->mmioaddr[i]);
367 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
368 csr->mmiodata[i] = dmc_header->mmiodata[i];
371 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
372 nbytes = dmc_header->fw_size * 4;
373 if (nbytes > CSR_MAX_FW_SIZE) {
374 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
377 csr->dmc_fw_size = dmc_header->fw_size;
379 dmc_payload = kmalloc(nbytes, GFP_KERNEL);
381 DRM_ERROR("Memory allocation failed for dmc payload\n");
385 return memcpy(dmc_payload, &fw->data[readcount], nbytes);
388 static void csr_load_work_fn(struct work_struct *work)
390 struct drm_i915_private *dev_priv;
391 struct intel_csr *csr;
392 const struct firmware *fw;
395 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
396 csr = &dev_priv->csr;
398 ret = request_firmware(&fw, dev_priv->csr.fw_path,
399 &dev_priv->drm.pdev->dev);
401 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
403 if (dev_priv->csr.dmc_payload) {
404 intel_csr_load_program(dev_priv);
406 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
408 DRM_INFO("Finished loading %s (v%u.%u)\n",
409 dev_priv->csr.fw_path,
410 CSR_VERSION_MAJOR(csr->version),
411 CSR_VERSION_MINOR(csr->version));
413 dev_notice(dev_priv->drm.dev,
414 "Failed to load DMC firmware"
415 " [" FIRMWARE_URL "],"
416 " disabling runtime power management.\n");
419 release_firmware(fw);
423 * intel_csr_ucode_init() - initialize the firmware loading.
424 * @dev_priv: i915 drm device.
426 * This function is called at the time of loading the display driver to read
427 * firmware from a .bin file and copied into a internal memory.
429 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
431 struct intel_csr *csr = &dev_priv->csr;
433 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
435 if (!HAS_CSR(dev_priv))
438 if (IS_KABYLAKE(dev_priv))
439 csr->fw_path = I915_CSR_KBL;
440 else if (IS_SKYLAKE(dev_priv))
441 csr->fw_path = I915_CSR_SKL;
442 else if (IS_BROXTON(dev_priv))
443 csr->fw_path = I915_CSR_BXT;
445 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
449 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
452 * Obtain a runtime pm reference, until CSR is loaded,
453 * to avoid entering runtime-suspend.
455 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
457 schedule_work(&dev_priv->csr.work);
461 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
462 * @dev_priv: i915 drm device
464 * Prepare the DMC firmware before entering system suspend. This includes
465 * flushing pending work items and releasing any resources acquired during
468 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
470 if (!HAS_CSR(dev_priv))
473 flush_work(&dev_priv->csr.work);
475 /* Drop the reference held in case DMC isn't loaded. */
476 if (!dev_priv->csr.dmc_payload)
477 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
481 * intel_csr_ucode_resume() - init CSR firmware during system resume
482 * @dev_priv: i915 drm device
484 * Reinitialize the DMC firmware during system resume, reacquiring any
485 * resources released in intel_csr_ucode_suspend().
487 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
489 if (!HAS_CSR(dev_priv))
493 * Reacquire the reference to keep RPM disabled in case DMC isn't
496 if (!dev_priv->csr.dmc_payload)
497 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
501 * intel_csr_ucode_fini() - unload the CSR firmware.
502 * @dev_priv: i915 drm device.
504 * Firmmware unloading includes freeing the internal memory and reset the
505 * firmware loading status.
507 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
509 if (!HAS_CSR(dev_priv))
512 intel_csr_ucode_suspend(dev_priv);
514 kfree(dev_priv->csr.dmc_payload);