2 * Copyright © 2014 Intel Corporation
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24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
36 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
37 * FW_LOADED, FW_FAILED.
39 * Once the firmware is written into the registers status will be moved from
40 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
41 * be moved to FW_FAILED.
44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
47 #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
49 MODULE_FIRMWARE(I915_CSR_SKL);
50 MODULE_FIRMWARE(I915_CSR_BXT);
52 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
54 #define CSR_MAX_FW_SIZE 0x2FFF
55 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
57 struct intel_css_header {
61 /* Includes the DMC specific header in dwords */
64 /* always value would be 0x10000 */
71 uint32_t module_vendor;
73 /* in YYYYMMDD format */
76 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
83 uint32_t modulus_size;
86 uint32_t exponent_size;
89 uint32_t reserved1[12];
95 uint32_t reserved2[8];
98 uint32_t kernel_header_info;
101 struct intel_fw_info {
104 /* Stepping (A, B, C, ..., *). * is a wildcard */
107 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
114 struct intel_package_header {
115 /* DMC container header length in dwords */
116 unsigned char header_len;
118 /* always value would be 0x01 */
119 unsigned char header_ver;
121 unsigned char reserved[10];
123 /* Number of valid entries in the FWInfo array below */
124 uint32_t num_entries;
126 struct intel_fw_info fw_info[20];
129 struct intel_dmc_header {
130 /* always value would be 0x40403E3E */
133 /* DMC binary header length */
134 unsigned char header_len;
137 unsigned char header_ver;
145 /* Firmware program size (excluding header) in dwords */
148 /* Major Minor version */
151 /* Number of valid MMIO cycles present. */
155 uint32_t mmioaddr[8];
158 uint32_t mmiodata[8];
161 unsigned char dfile[32];
163 uint32_t reserved1[2];
166 struct stepping_info {
172 * Kabylake derivated from Skylake H0, so SKL H0
173 * is the right firmware for KBL A0 (revid 0).
175 static const struct stepping_info kbl_stepping_info[] = {
176 {'H', '0'}, {'I', '0'}
179 static const struct stepping_info skl_stepping_info[] = {
180 {'A', '0'}, {'B', '0'}, {'C', '0'},
181 {'D', '0'}, {'E', '0'}, {'F', '0'},
182 {'G', '0'}, {'H', '0'}, {'I', '0'},
183 {'J', '0'}, {'K', '0'}
186 static const struct stepping_info bxt_stepping_info[] = {
187 {'A', '0'}, {'A', '1'}, {'A', '2'},
188 {'B', '0'}, {'B', '1'}, {'B', '2'}
191 static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
193 const struct stepping_info *si;
196 if (IS_KABYLAKE(dev)) {
197 size = ARRAY_SIZE(kbl_stepping_info);
198 si = kbl_stepping_info;
199 } else if (IS_SKYLAKE(dev)) {
200 size = ARRAY_SIZE(skl_stepping_info);
201 si = skl_stepping_info;
202 } else if (IS_BROXTON(dev)) {
203 size = ARRAY_SIZE(bxt_stepping_info);
204 si = bxt_stepping_info;
209 if (INTEL_REVID(dev) < size)
210 return si + INTEL_REVID(dev);
216 * intel_csr_load_program() - write the firmware from memory to register.
217 * @dev_priv: i915 drm device.
219 * CSR firmware is read from a .bin file and kept in internal memory one time.
220 * Everytime display comes back from low power state this function is called to
221 * copy the firmware from internal memory to registers.
223 void intel_csr_load_program(struct drm_i915_private *dev_priv)
225 u32 *payload = dev_priv->csr.dmc_payload;
228 if (!IS_GEN9(dev_priv)) {
229 DRM_ERROR("No CSR support available for this platform\n");
233 if (!dev_priv->csr.dmc_payload) {
234 DRM_ERROR("Tried to program CSR with empty payload\n");
238 fw_size = dev_priv->csr.dmc_fw_size;
239 for (i = 0; i < fw_size; i++)
240 I915_WRITE(CSR_PROGRAM(i), payload[i]);
242 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
243 I915_WRITE(dev_priv->csr.mmioaddr[i],
244 dev_priv->csr.mmiodata[i]);
248 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
249 const struct firmware *fw)
251 struct drm_device *dev = dev_priv->dev;
252 struct intel_css_header *css_header;
253 struct intel_package_header *package_header;
254 struct intel_dmc_header *dmc_header;
255 struct intel_csr *csr = &dev_priv->csr;
256 const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
257 char stepping, substepping;
258 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
260 uint32_t *dmc_payload;
265 if (!stepping_info) {
266 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
270 stepping = stepping_info->stepping;
271 substepping = stepping_info->substepping;
273 /* Extract CSS Header information*/
274 css_header = (struct intel_css_header *)fw->data;
275 if (sizeof(struct intel_css_header) !=
276 (css_header->header_len * 4)) {
277 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
278 (css_header->header_len * 4));
282 csr->version = css_header->version;
284 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
285 csr->version < SKL_CSR_VERSION_REQUIRED) {
286 DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
287 " please upgrade to v%u.%u or later"
288 " [" FIRMWARE_URL "].\n",
289 CSR_VERSION_MAJOR(csr->version),
290 CSR_VERSION_MINOR(csr->version),
291 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
292 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
296 readcount += sizeof(struct intel_css_header);
298 /* Extract Package Header information*/
299 package_header = (struct intel_package_header *)
300 &fw->data[readcount];
301 if (sizeof(struct intel_package_header) !=
302 (package_header->header_len * 4)) {
303 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
304 (package_header->header_len * 4));
307 readcount += sizeof(struct intel_package_header);
309 /* Search for dmc_offset to find firware binary. */
310 for (i = 0; i < package_header->num_entries; i++) {
311 if (package_header->fw_info[i].substepping == '*' &&
312 stepping == package_header->fw_info[i].stepping) {
313 dmc_offset = package_header->fw_info[i].offset;
315 } else if (stepping == package_header->fw_info[i].stepping &&
316 substepping == package_header->fw_info[i].substepping) {
317 dmc_offset = package_header->fw_info[i].offset;
319 } else if (package_header->fw_info[i].stepping == '*' &&
320 package_header->fw_info[i].substepping == '*')
321 dmc_offset = package_header->fw_info[i].offset;
323 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
324 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
327 readcount += dmc_offset;
329 /* Extract dmc_header information. */
330 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
331 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
332 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
333 (dmc_header->header_len));
336 readcount += sizeof(struct intel_dmc_header);
338 /* Cache the dmc header info. */
339 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
340 DRM_ERROR("Firmware has wrong mmio count %u\n",
341 dmc_header->mmio_count);
344 csr->mmio_count = dmc_header->mmio_count;
345 for (i = 0; i < dmc_header->mmio_count; i++) {
346 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
347 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
348 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
349 dmc_header->mmioaddr[i]);
352 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
353 csr->mmiodata[i] = dmc_header->mmiodata[i];
356 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
357 nbytes = dmc_header->fw_size * 4;
358 if (nbytes > CSR_MAX_FW_SIZE) {
359 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
362 csr->dmc_fw_size = dmc_header->fw_size;
364 dmc_payload = kmalloc(nbytes, GFP_KERNEL);
366 DRM_ERROR("Memory allocation failed for dmc payload\n");
370 memcpy(dmc_payload, &fw->data[readcount], nbytes);
375 static void csr_load_work_fn(struct work_struct *work)
377 struct drm_i915_private *dev_priv;
378 struct intel_csr *csr;
379 const struct firmware *fw;
382 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
383 csr = &dev_priv->csr;
385 ret = request_firmware(&fw, dev_priv->csr.fw_path,
386 &dev_priv->dev->pdev->dev);
390 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
391 if (!dev_priv->csr.dmc_payload)
394 /* load csr program during system boot, as needed for DC states */
395 intel_csr_load_program(dev_priv);
398 if (dev_priv->csr.dmc_payload) {
399 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
401 DRM_INFO("Finished loading %s (v%u.%u)\n",
402 dev_priv->csr.fw_path,
403 CSR_VERSION_MAJOR(csr->version),
404 CSR_VERSION_MINOR(csr->version));
406 dev_notice(dev_priv->dev->dev,
407 "Failed to load DMC firmware"
408 " [" FIRMWARE_URL "],"
409 " disabling runtime power management.\n");
412 release_firmware(fw);
416 * intel_csr_ucode_init() - initialize the firmware loading.
417 * @dev_priv: i915 drm device.
419 * This function is called at the time of loading the display driver to read
420 * firmware from a .bin file and copied into a internal memory.
422 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
424 struct intel_csr *csr = &dev_priv->csr;
426 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
428 if (!HAS_CSR(dev_priv))
431 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
432 csr->fw_path = I915_CSR_SKL;
433 else if (IS_BROXTON(dev_priv))
434 csr->fw_path = I915_CSR_BXT;
436 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
440 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
443 * Obtain a runtime pm reference, until CSR is loaded,
444 * to avoid entering runtime-suspend.
446 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
448 schedule_work(&dev_priv->csr.work);
452 * intel_csr_ucode_fini() - unload the CSR firmware.
453 * @dev_priv: i915 drm device.
455 * Firmmware unloading includes freeing the internal momory and reset the
456 * firmware loading status.
458 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
460 if (!HAS_CSR(dev_priv))
463 flush_work(&dev_priv->csr.work);
465 kfree(dev_priv->csr.dmc_payload);