2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
63 struct drm_encoder *encoder = &intel_encoder->base;
64 int type = intel_encoder->type;
66 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
67 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
68 struct intel_digital_port *intel_dig_port =
69 enc_to_dig_port(encoder);
70 return intel_dig_port->port;
72 } else if (type == INTEL_OUTPUT_ANALOG) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
90 struct drm_i915_private *dev_priv = dev->dev_private;
93 const u32 *ddi_translations = ((use_fdi_mode) ?
94 hsw_ddi_translations_fdi :
95 hsw_ddi_translations_dp);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode ? "FDI" : "DP");
101 WARN((use_fdi_mode && (port != PORT_E)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
106 I915_WRITE(reg, ddi_translations[i]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device *dev)
121 for (port = PORT_A; port < PORT_E; port++)
122 intel_prepare_ddi_buffers(dev, port, false);
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
128 intel_prepare_ddi_buffers(dev, PORT_E, true);
131 static const long hsw_ddi_buf_ctl_values[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW,
133 DDI_BUF_EMP_400MV_3_5DB_HSW,
134 DDI_BUF_EMP_400MV_6DB_HSW,
135 DDI_BUF_EMP_400MV_9_5DB_HSW,
136 DDI_BUF_EMP_600MV_0DB_HSW,
137 DDI_BUF_EMP_600MV_3_5DB_HSW,
138 DDI_BUF_EMP_600MV_6DB_HSW,
139 DDI_BUF_EMP_800MV_0DB_HSW,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
146 uint32_t reg = DDI_BUF_CTL(port);
149 for (i = 0; i < 8; i++) {
151 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc *crtc)
168 struct drm_device *dev = crtc->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
171 u32 temp, i, rx_ctl_val;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 * WaFDIAutoLinkSetTimingOverrride:hsw
180 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
181 FDI_RX_PWRDN_LANE0_VAL(2) |
182 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
184 /* Enable the PCH Receiver FDI PLL */
185 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
187 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
188 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
189 POSTING_READ(_FDI_RXA_CTL);
192 /* Switch from Rawclk to PCDclk */
193 rx_ctl_val |= FDI_PCDCLK;
194 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
196 /* Configure Port Clock Select */
197 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
199 /* Start the training iterating through available voltages and emphasis,
200 * testing each value twice. */
201 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
202 /* Configure DP_TP_CTL with auto-training */
203 I915_WRITE(DP_TP_CTL(PORT_E),
204 DP_TP_CTL_FDI_AUTOTRAIN |
205 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
206 DP_TP_CTL_LINK_TRAIN_PAT1 |
209 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
210 * DDI E does not support port reversal, the functionality is
211 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
212 * port reversal bit */
213 I915_WRITE(DDI_BUF_CTL(PORT_E),
215 ((intel_crtc->config.fdi_lanes - 1) << 1) |
216 hsw_ddi_buf_ctl_values[i / 2]);
217 POSTING_READ(DDI_BUF_CTL(PORT_E));
221 /* Program PCH FDI Receiver TU */
222 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
224 /* Enable PCH FDI Receiver with auto-training */
225 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
226 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
227 POSTING_READ(_FDI_RXA_CTL);
229 /* Wait for FDI receiver lane calibration */
232 /* Unset FDI_RX_MISC pwrdn lanes */
233 temp = I915_READ(_FDI_RXA_MISC);
234 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
235 I915_WRITE(_FDI_RXA_MISC, temp);
236 POSTING_READ(_FDI_RXA_MISC);
238 /* Wait for FDI auto training time */
241 temp = I915_READ(DP_TP_STATUS(PORT_E));
242 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
243 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
245 /* Enable normal pixel sending for FDI */
246 I915_WRITE(DP_TP_CTL(PORT_E),
247 DP_TP_CTL_FDI_AUTOTRAIN |
248 DP_TP_CTL_LINK_TRAIN_NORMAL |
249 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
255 temp = I915_READ(DDI_BUF_CTL(PORT_E));
256 temp &= ~DDI_BUF_CTL_ENABLE;
257 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
258 POSTING_READ(DDI_BUF_CTL(PORT_E));
260 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
261 temp = I915_READ(DP_TP_CTL(PORT_E));
262 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
263 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
264 I915_WRITE(DP_TP_CTL(PORT_E), temp);
265 POSTING_READ(DP_TP_CTL(PORT_E));
267 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
269 rx_ctl_val &= ~FDI_RX_ENABLE;
270 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
271 POSTING_READ(_FDI_RXA_CTL);
273 /* Reset FDI_RX_MISC pwrdn lanes */
274 temp = I915_READ(_FDI_RXA_MISC);
275 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
276 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
277 I915_WRITE(_FDI_RXA_MISC, temp);
278 POSTING_READ(_FDI_RXA_MISC);
281 DRM_ERROR("FDI link training failed!\n");
284 static void intel_ddi_mode_set(struct drm_encoder *encoder,
285 struct drm_display_mode *mode,
286 struct drm_display_mode *adjusted_mode)
288 struct drm_crtc *crtc = encoder->crtc;
289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
290 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
291 int port = intel_ddi_get_encoder_port(intel_encoder);
292 int pipe = intel_crtc->pipe;
293 int type = intel_encoder->type;
295 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
296 port_name(port), pipe_name(pipe));
298 intel_crtc->eld_vld = false;
299 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
300 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
301 struct intel_digital_port *intel_dig_port =
302 enc_to_dig_port(encoder);
304 intel_dp->DP = intel_dig_port->port_reversal |
305 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
306 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
308 if (intel_dp->has_audio) {
309 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
310 pipe_name(intel_crtc->pipe));
313 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
314 intel_write_eld(encoder, adjusted_mode);
317 intel_dp_init_link_config(intel_dp);
319 } else if (type == INTEL_OUTPUT_HDMI) {
320 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
322 if (intel_hdmi->has_audio) {
323 /* Proper support for digital audio needs a new logic
324 * and a new set of registers, so we leave it for future
327 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
328 pipe_name(intel_crtc->pipe));
331 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
332 intel_write_eld(encoder, adjusted_mode);
335 intel_hdmi->set_infoframes(encoder, adjusted_mode);
339 static struct intel_encoder *
340 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
342 struct drm_device *dev = crtc->dev;
343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
344 struct intel_encoder *intel_encoder, *ret = NULL;
345 int num_encoders = 0;
347 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
352 if (num_encoders != 1)
353 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
354 pipe_name(intel_crtc->pipe));
360 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
362 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
363 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
367 switch (intel_crtc->ddi_pll_sel) {
368 case PORT_CLK_SEL_SPLL:
369 plls->spll_refcount--;
370 if (plls->spll_refcount == 0) {
371 DRM_DEBUG_KMS("Disabling SPLL\n");
372 val = I915_READ(SPLL_CTL);
373 WARN_ON(!(val & SPLL_PLL_ENABLE));
374 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
375 POSTING_READ(SPLL_CTL);
378 case PORT_CLK_SEL_WRPLL1:
379 plls->wrpll1_refcount--;
380 if (plls->wrpll1_refcount == 0) {
381 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
382 val = I915_READ(WRPLL_CTL1);
383 WARN_ON(!(val & WRPLL_PLL_ENABLE));
384 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
385 POSTING_READ(WRPLL_CTL1);
388 case PORT_CLK_SEL_WRPLL2:
389 plls->wrpll2_refcount--;
390 if (plls->wrpll2_refcount == 0) {
391 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
392 val = I915_READ(WRPLL_CTL2);
393 WARN_ON(!(val & WRPLL_PLL_ENABLE));
394 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
395 POSTING_READ(WRPLL_CTL2);
400 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
401 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
402 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
404 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
408 #define LC_FREQ_2K (LC_FREQ * 2000)
414 /* Constraints for PLL good behavior */
420 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
426 static unsigned wrpll_get_budget_for_freq(int clock)
500 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
501 unsigned r2, unsigned n2, unsigned p,
502 struct wrpll_rnp *best)
504 uint64_t a, b, c, d, diff, diff_best;
506 /* No best (r,n,p) yet */
515 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
519 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
522 * and we would like delta <= budget.
524 * If the discrepancy is above the PPM-based budget, always prefer to
525 * improve upon the previous solution. However, if you're within the
526 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
528 a = freq2k * budget * p * r2;
529 b = freq2k * budget * best->p * best->r2;
530 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
531 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
532 (LC_FREQ_2K * best->n2));
534 d = 1000000 * diff_best;
536 if (a < c && b < d) {
537 /* If both are above the budget, pick the closer */
538 if (best->p * best->r2 * diff < p * r2 * diff_best) {
543 } else if (a >= c && b < d) {
544 /* If A is below the threshold but B is above it? Update. */
548 } else if (a >= c && b >= d) {
549 /* Both are below the limit, so pick the higher n2/(r2*r2) */
550 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
556 /* Otherwise a < c && b >= d, do nothing */
560 intel_ddi_calculate_wrpll(int clock /* in Hz */,
561 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
565 struct wrpll_rnp best = { 0, 0, 0 };
568 freq2k = clock / 100;
570 budget = wrpll_get_budget_for_freq(clock);
572 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
573 * and directly pass the LC PLL to it. */
574 if (freq2k == 5400000) {
582 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
585 * We want R so that REF_MIN <= Ref <= REF_MAX.
586 * Injecting R2 = 2 * R gives:
587 * REF_MAX * r2 > LC_FREQ * 2 and
588 * REF_MIN * r2 < LC_FREQ * 2
590 * Which means the desired boundaries for r2 are:
591 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
594 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
595 r2 <= LC_FREQ * 2 / REF_MIN;
599 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
601 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
602 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
603 * VCO_MAX * r2 > n2 * LC_FREQ and
604 * VCO_MIN * r2 < n2 * LC_FREQ)
606 * Which means the desired boundaries for n2 are:
607 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
609 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
610 n2 <= VCO_MAX * r2 / LC_FREQ;
613 for (p = P_MIN; p <= P_MAX; p += P_INC)
614 wrpll_update_rnp(freq2k, budget,
623 DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
624 clock, *p_out, *n2_out, *r2_out);
627 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
630 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
631 struct drm_encoder *encoder = &intel_encoder->base;
632 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
633 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
634 int type = intel_encoder->type;
635 enum pipe pipe = intel_crtc->pipe;
637 int clock = intel_crtc->config.port_clock;
639 /* TODO: reuse PLLs when possible (compare values) */
641 intel_ddi_put_crtc_pll(crtc);
643 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
644 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
646 switch (intel_dp->link_bw) {
647 case DP_LINK_BW_1_62:
648 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
651 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
654 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
657 DRM_ERROR("Link bandwidth %d unsupported\n",
662 /* We don't need to turn any PLL on because we'll use LCPLL. */
665 } else if (type == INTEL_OUTPUT_HDMI) {
668 if (plls->wrpll1_refcount == 0) {
669 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
671 plls->wrpll1_refcount++;
673 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
674 } else if (plls->wrpll2_refcount == 0) {
675 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
677 plls->wrpll2_refcount++;
679 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
681 DRM_ERROR("No WRPLLs available!\n");
685 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
686 "WRPLL already enabled\n");
688 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
690 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
691 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
692 WRPLL_DIVIDER_POST(p);
694 } else if (type == INTEL_OUTPUT_ANALOG) {
695 if (plls->spll_refcount == 0) {
696 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
698 plls->spll_refcount++;
700 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
702 DRM_ERROR("SPLL already in use\n");
706 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
707 "SPLL already enabled\n");
709 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
712 WARN(1, "Invalid DDI encoder type %d\n", type);
716 I915_WRITE(reg, val);
722 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
724 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
726 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
727 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
728 int type = intel_encoder->type;
731 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
733 temp = TRANS_MSA_SYNC_CLK;
734 switch (intel_crtc->config.pipe_bpp) {
736 temp |= TRANS_MSA_6_BPC;
739 temp |= TRANS_MSA_8_BPC;
742 temp |= TRANS_MSA_10_BPC;
745 temp |= TRANS_MSA_12_BPC;
750 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
754 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
758 struct drm_encoder *encoder = &intel_encoder->base;
759 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
760 enum pipe pipe = intel_crtc->pipe;
761 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
762 enum port port = intel_ddi_get_encoder_port(intel_encoder);
763 int type = intel_encoder->type;
766 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
767 temp = TRANS_DDI_FUNC_ENABLE;
768 temp |= TRANS_DDI_SELECT_PORT(port);
770 switch (intel_crtc->config.pipe_bpp) {
772 temp |= TRANS_DDI_BPC_6;
775 temp |= TRANS_DDI_BPC_8;
778 temp |= TRANS_DDI_BPC_10;
781 temp |= TRANS_DDI_BPC_12;
787 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
788 temp |= TRANS_DDI_PVSYNC;
789 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
790 temp |= TRANS_DDI_PHSYNC;
792 if (cpu_transcoder == TRANSCODER_EDP) {
795 /* Can only use the always-on power well for eDP when
796 * not using the panel fitter, and when not using motion
797 * blur mitigation (which we don't support). */
798 if (intel_crtc->config.pch_pfit.size)
799 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
801 temp |= TRANS_DDI_EDP_INPUT_A_ON;
804 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
807 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
815 if (type == INTEL_OUTPUT_HDMI) {
816 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
818 if (intel_hdmi->has_hdmi_sink)
819 temp |= TRANS_DDI_MODE_SELECT_HDMI;
821 temp |= TRANS_DDI_MODE_SELECT_DVI;
823 } else if (type == INTEL_OUTPUT_ANALOG) {
824 temp |= TRANS_DDI_MODE_SELECT_FDI;
825 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
827 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
828 type == INTEL_OUTPUT_EDP) {
829 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
831 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
833 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
835 WARN(1, "Invalid encoder type %d for pipe %c\n",
836 intel_encoder->type, pipe_name(pipe));
839 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
842 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
843 enum transcoder cpu_transcoder)
845 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
846 uint32_t val = I915_READ(reg);
848 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
849 val |= TRANS_DDI_PORT_NONE;
850 I915_WRITE(reg, val);
853 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
855 struct drm_device *dev = intel_connector->base.dev;
856 struct drm_i915_private *dev_priv = dev->dev_private;
857 struct intel_encoder *intel_encoder = intel_connector->encoder;
858 int type = intel_connector->base.connector_type;
859 enum port port = intel_ddi_get_encoder_port(intel_encoder);
861 enum transcoder cpu_transcoder;
864 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
868 cpu_transcoder = TRANSCODER_EDP;
870 cpu_transcoder = (enum transcoder) pipe;
872 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
874 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
875 case TRANS_DDI_MODE_SELECT_HDMI:
876 case TRANS_DDI_MODE_SELECT_DVI:
877 return (type == DRM_MODE_CONNECTOR_HDMIA);
879 case TRANS_DDI_MODE_SELECT_DP_SST:
880 if (type == DRM_MODE_CONNECTOR_eDP)
882 case TRANS_DDI_MODE_SELECT_DP_MST:
883 return (type == DRM_MODE_CONNECTOR_DisplayPort);
885 case TRANS_DDI_MODE_SELECT_FDI:
886 return (type == DRM_MODE_CONNECTOR_VGA);
893 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
896 struct drm_device *dev = encoder->base.dev;
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 enum port port = intel_ddi_get_encoder_port(encoder);
902 tmp = I915_READ(DDI_BUF_CTL(port));
904 if (!(tmp & DDI_BUF_CTL_ENABLE))
907 if (port == PORT_A) {
908 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
910 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
911 case TRANS_DDI_EDP_INPUT_A_ON:
912 case TRANS_DDI_EDP_INPUT_A_ONOFF:
915 case TRANS_DDI_EDP_INPUT_B_ONOFF:
918 case TRANS_DDI_EDP_INPUT_C_ONOFF:
925 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
926 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
928 if ((tmp & TRANS_DDI_PORT_MASK)
929 == TRANS_DDI_SELECT_PORT(port)) {
936 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
941 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
945 enum port port = I915_MAX_PORTS;
946 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
950 if (cpu_transcoder == TRANSCODER_EDP) {
953 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
954 temp &= TRANS_DDI_PORT_MASK;
956 for (i = PORT_B; i <= PORT_E; i++)
957 if (temp == TRANS_DDI_SELECT_PORT(i))
961 if (port == I915_MAX_PORTS) {
962 WARN(1, "Pipe %c enabled on an unknown port\n",
964 ret = PORT_CLK_SEL_NONE;
966 ret = I915_READ(PORT_CLK_SEL(port));
967 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
968 "0x%08x\n", pipe_name(pipe), port_name(port),
975 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
977 struct drm_i915_private *dev_priv = dev->dev_private;
979 struct intel_crtc *intel_crtc;
981 for_each_pipe(pipe) {
983 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
985 if (!intel_crtc->active)
988 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
991 switch (intel_crtc->ddi_pll_sel) {
992 case PORT_CLK_SEL_SPLL:
993 dev_priv->ddi_plls.spll_refcount++;
995 case PORT_CLK_SEL_WRPLL1:
996 dev_priv->ddi_plls.wrpll1_refcount++;
998 case PORT_CLK_SEL_WRPLL2:
999 dev_priv->ddi_plls.wrpll2_refcount++;
1005 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1007 struct drm_crtc *crtc = &intel_crtc->base;
1008 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1009 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1010 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1011 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1013 if (cpu_transcoder != TRANSCODER_EDP)
1014 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1015 TRANS_CLK_SEL_PORT(port));
1018 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1020 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1021 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1023 if (cpu_transcoder != TRANSCODER_EDP)
1024 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1025 TRANS_CLK_SEL_DISABLED);
1028 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1030 struct drm_encoder *encoder = &intel_encoder->base;
1031 struct drm_crtc *crtc = encoder->crtc;
1032 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1034 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1035 int type = intel_encoder->type;
1037 if (type == INTEL_OUTPUT_EDP) {
1038 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1039 ironlake_edp_panel_vdd_on(intel_dp);
1040 ironlake_edp_panel_on(intel_dp);
1041 ironlake_edp_panel_vdd_off(intel_dp, true);
1044 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1045 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1047 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1048 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1050 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1051 intel_dp_start_link_train(intel_dp);
1052 intel_dp_complete_link_train(intel_dp);
1054 intel_dp_stop_link_train(intel_dp);
1058 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1060 struct drm_encoder *encoder = &intel_encoder->base;
1061 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1062 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1063 int type = intel_encoder->type;
1067 val = I915_READ(DDI_BUF_CTL(port));
1068 if (val & DDI_BUF_CTL_ENABLE) {
1069 val &= ~DDI_BUF_CTL_ENABLE;
1070 I915_WRITE(DDI_BUF_CTL(port), val);
1074 val = I915_READ(DP_TP_CTL(port));
1075 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1076 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1077 I915_WRITE(DP_TP_CTL(port), val);
1080 intel_wait_ddi_buf_idle(dev_priv, port);
1082 if (type == INTEL_OUTPUT_EDP) {
1083 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1084 ironlake_edp_panel_vdd_on(intel_dp);
1085 ironlake_edp_panel_off(intel_dp);
1088 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1091 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1093 struct drm_encoder *encoder = &intel_encoder->base;
1094 struct drm_crtc *crtc = encoder->crtc;
1095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1096 int pipe = intel_crtc->pipe;
1097 struct drm_device *dev = encoder->dev;
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1100 int type = intel_encoder->type;
1103 if (type == INTEL_OUTPUT_HDMI) {
1104 struct intel_digital_port *intel_dig_port =
1105 enc_to_dig_port(encoder);
1107 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1108 * are ignored so nothing special needs to be done besides
1109 * enabling the port.
1111 I915_WRITE(DDI_BUF_CTL(port),
1112 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
1113 } else if (type == INTEL_OUTPUT_EDP) {
1114 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1117 intel_dp_stop_link_train(intel_dp);
1119 ironlake_edp_backlight_on(intel_dp);
1122 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1123 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1124 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1125 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1129 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1131 struct drm_encoder *encoder = &intel_encoder->base;
1132 struct drm_crtc *crtc = encoder->crtc;
1133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134 int pipe = intel_crtc->pipe;
1135 int type = intel_encoder->type;
1136 struct drm_device *dev = encoder->dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private;
1140 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1141 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1142 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1144 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1147 if (type == INTEL_OUTPUT_EDP) {
1148 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1150 ironlake_edp_backlight_off(intel_dp);
1154 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1156 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1158 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1161 else if (IS_ULT(dev_priv->dev))
1167 void intel_ddi_pll_init(struct drm_device *dev)
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 uint32_t val = I915_READ(LCPLL_CTL);
1172 /* The LCPLL register should be turned on by the BIOS. For now let's
1173 * just check its state and print errors in case something is wrong.
1174 * Don't even try to turn it on.
1177 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1178 intel_ddi_get_cdclk_freq(dev_priv));
1180 if (val & LCPLL_CD_SOURCE_FCLK)
1181 DRM_ERROR("CDCLK source is not LCPLL\n");
1183 if (val & LCPLL_PLL_DISABLE)
1184 DRM_ERROR("LCPLL is disabled\n");
1187 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1189 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1190 struct intel_dp *intel_dp = &intel_dig_port->dp;
1191 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1192 enum port port = intel_dig_port->port;
1196 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1197 val = I915_READ(DDI_BUF_CTL(port));
1198 if (val & DDI_BUF_CTL_ENABLE) {
1199 val &= ~DDI_BUF_CTL_ENABLE;
1200 I915_WRITE(DDI_BUF_CTL(port), val);
1204 val = I915_READ(DP_TP_CTL(port));
1205 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1206 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1207 I915_WRITE(DP_TP_CTL(port), val);
1208 POSTING_READ(DP_TP_CTL(port));
1211 intel_wait_ddi_buf_idle(dev_priv, port);
1214 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1215 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1216 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1217 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1218 I915_WRITE(DP_TP_CTL(port), val);
1219 POSTING_READ(DP_TP_CTL(port));
1221 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1222 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1223 POSTING_READ(DDI_BUF_CTL(port));
1228 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1230 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1231 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1234 intel_ddi_post_disable(intel_encoder);
1236 val = I915_READ(_FDI_RXA_CTL);
1237 val &= ~FDI_RX_ENABLE;
1238 I915_WRITE(_FDI_RXA_CTL, val);
1240 val = I915_READ(_FDI_RXA_MISC);
1241 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1242 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1243 I915_WRITE(_FDI_RXA_MISC, val);
1245 val = I915_READ(_FDI_RXA_CTL);
1247 I915_WRITE(_FDI_RXA_CTL, val);
1249 val = I915_READ(_FDI_RXA_CTL);
1250 val &= ~FDI_RX_PLL_ENABLE;
1251 I915_WRITE(_FDI_RXA_CTL, val);
1254 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1256 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1257 int type = intel_encoder->type;
1259 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1260 intel_dp_check_link_status(intel_dp);
1263 static void intel_ddi_get_config(struct intel_encoder *encoder,
1264 struct intel_crtc_config *pipe_config)
1266 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1267 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1268 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1269 u32 temp, flags = 0;
1271 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1272 if (temp & TRANS_DDI_PHSYNC)
1273 flags |= DRM_MODE_FLAG_PHSYNC;
1275 flags |= DRM_MODE_FLAG_NHSYNC;
1276 if (temp & TRANS_DDI_PVSYNC)
1277 flags |= DRM_MODE_FLAG_PVSYNC;
1279 flags |= DRM_MODE_FLAG_NVSYNC;
1281 pipe_config->adjusted_mode.flags |= flags;
1284 static void intel_ddi_destroy(struct drm_encoder *encoder)
1286 /* HDMI has nothing special to destroy, so we can go with this. */
1287 intel_dp_encoder_destroy(encoder);
1290 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1291 struct intel_crtc_config *pipe_config)
1293 int type = encoder->type;
1294 int port = intel_ddi_get_encoder_port(encoder);
1296 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1299 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1301 if (type == INTEL_OUTPUT_HDMI)
1302 return intel_hdmi_compute_config(encoder, pipe_config);
1304 return intel_dp_compute_config(encoder, pipe_config);
1307 static const struct drm_encoder_funcs intel_ddi_funcs = {
1308 .destroy = intel_ddi_destroy,
1311 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1312 .mode_set = intel_ddi_mode_set,
1315 void intel_ddi_init(struct drm_device *dev, enum port port)
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct intel_digital_port *intel_dig_port;
1319 struct intel_encoder *intel_encoder;
1320 struct drm_encoder *encoder;
1321 struct intel_connector *hdmi_connector = NULL;
1322 struct intel_connector *dp_connector = NULL;
1324 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1325 if (!intel_dig_port)
1328 dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1329 if (!dp_connector) {
1330 kfree(intel_dig_port);
1334 intel_encoder = &intel_dig_port->base;
1335 encoder = &intel_encoder->base;
1337 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1338 DRM_MODE_ENCODER_TMDS);
1339 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1341 intel_encoder->compute_config = intel_ddi_compute_config;
1342 intel_encoder->enable = intel_enable_ddi;
1343 intel_encoder->pre_enable = intel_ddi_pre_enable;
1344 intel_encoder->disable = intel_disable_ddi;
1345 intel_encoder->post_disable = intel_ddi_post_disable;
1346 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1347 intel_encoder->get_config = intel_ddi_get_config;
1349 intel_dig_port->port = port;
1350 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
1351 DDI_BUF_PORT_REVERSAL;
1352 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1354 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1355 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1356 intel_encoder->cloneable = false;
1357 intel_encoder->hot_plug = intel_ddi_hot_plug;
1359 if (!intel_dp_init_connector(intel_dig_port, dp_connector)) {
1360 drm_encoder_cleanup(encoder);
1361 kfree(intel_dig_port);
1362 kfree(dp_connector);
1366 if (intel_encoder->type != INTEL_OUTPUT_EDP) {
1367 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1369 if (!hdmi_connector) {
1373 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1374 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);