drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  38  * them for both DP and FDI transports, allowing those ports to
  39  * automatically adapt to HDMI connections as well
  40  */
  41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  42         { 0x00FFFFFF, 0x0006000E, 0x0 },
  43         { 0x00D75FFF, 0x0005000A, 0x0 },
  44         { 0x00C30FFF, 0x00040006, 0x0 },
  45         { 0x80AAAFFF, 0x000B0000, 0x0 },
  46         { 0x00FFFFFF, 0x0005000A, 0x0 },
  47         { 0x00D75FFF, 0x000C0004, 0x0 },
  48         { 0x80C30FFF, 0x000B0000, 0x0 },
  49         { 0x00FFFFFF, 0x00040006, 0x0 },
  50         { 0x80D75FFF, 0x000B0000, 0x0 },
  51 };
  52
  53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  54         { 0x00FFFFFF, 0x0007000E, 0x0 },
  55         { 0x00D75FFF, 0x000F000A, 0x0 },
  56         { 0x00C30FFF, 0x00060006, 0x0 },
  57         { 0x00AAAFFF, 0x001E0000, 0x0 },
  58         { 0x00FFFFFF, 0x000F000A, 0x0 },
  59         { 0x00D75FFF, 0x00160004, 0x0 },
  60         { 0x00C30FFF, 0x001E0000, 0x0 },
  61         { 0x00FFFFFF, 0x00060006, 0x0 },
  62         { 0x00D75FFF, 0x001E0000, 0x0 },
  63 };
  64
  65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  66                                         /* Idx  NT mV d T mV d  db      */
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  68         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  69         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  70         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  71         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  72         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  73         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  74         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  75         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  76         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  77         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  78         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  79 };
  80
  81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  82         { 0x00FFFFFF, 0x00000012, 0x0 },
  83         { 0x00EBAFFF, 0x00020011, 0x0 },
  84         { 0x00C71FFF, 0x0006000F, 0x0 },
  85         { 0x00AAAFFF, 0x000E000A, 0x0 },
  86         { 0x00FFFFFF, 0x00020011, 0x0 },
  87         { 0x00DB6FFF, 0x0005000F, 0x0 },
  88         { 0x00BEEFFF, 0x000A000C, 0x0 },
  89         { 0x00FFFFFF, 0x0005000F, 0x0 },
  90         { 0x00DB6FFF, 0x000A000C, 0x0 },
  91 };
  92
  93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  94         { 0x00FFFFFF, 0x0007000E, 0x0 },
  95         { 0x00D75FFF, 0x000E000A, 0x0 },
  96         { 0x00BEFFFF, 0x00140006, 0x0 },
  97         { 0x80B2CFFF, 0x001B0002, 0x0 },
  98         { 0x00FFFFFF, 0x000E000A, 0x0 },
  99         { 0x00DB6FFF, 0x00160005, 0x0 },
 100         { 0x80C71FFF, 0x001A0002, 0x0 },
 101         { 0x00F7DFFF, 0x00180004, 0x0 },
 102         { 0x80D75FFF, 0x001B0002, 0x0 },
 103 };
 104
 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 106         { 0x00FFFFFF, 0x0001000E, 0x0 },
 107         { 0x00D75FFF, 0x0004000A, 0x0 },
 108         { 0x00C30FFF, 0x00070006, 0x0 },
 109         { 0x00AAAFFF, 0x000C0000, 0x0 },
 110         { 0x00FFFFFF, 0x0004000A, 0x0 },
 111         { 0x00D75FFF, 0x00090004, 0x0 },
 112         { 0x00C30FFF, 0x000C0000, 0x0 },
 113         { 0x00FFFFFF, 0x00070006, 0x0 },
 114         { 0x00D75FFF, 0x000C0000, 0x0 },
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 118                                         /* Idx  NT mV d T mV df db      */
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 120         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 121         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 122         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 124         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 125         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 126         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 127         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 128         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 129 };
 130
 131 /* Skylake H and S */
 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 133         { 0x00002016, 0x000000A0, 0x0 },
 134         { 0x00005012, 0x0000009B, 0x0 },
 135         { 0x00007011, 0x00000088, 0x0 },
 136         { 0x80009010, 0x000000C0, 0x1 },        /* Uses I_boost level 0x1 */
 137         { 0x00002016, 0x0000009B, 0x0 },
 138         { 0x00005012, 0x00000088, 0x0 },
 139         { 0x80007011, 0x000000C0, 0x1 },        /* Uses I_boost level 0x1 */
 140         { 0x00002016, 0x000000DF, 0x0 },
 141         { 0x80005012, 0x000000C0, 0x1 },        /* Uses I_boost level 0x1 */
 142 };
 143
 144 /* Skylake U */
 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 146         { 0x0000201B, 0x000000A2, 0x0 },
 147         { 0x00005012, 0x00000088, 0x0 },
 148         { 0x00007011, 0x00000087, 0x0 },
 149         { 0x80009010, 0x000000C0, 0x1 },        /* Uses I_boost level 0x1 */
 150         { 0x0000201B, 0x0000009D, 0x0 },
 151         { 0x80005012, 0x000000C0, 0x1 },        /* Uses I_boost level 0x1 */
 152         { 0x80007011, 0x000000C0, 0x1 },        /* Uses I_boost level 0x1 */
 153         { 0x00002016, 0x00000088, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },        /* Uses I_boost level 0x1 */
 155 };
 156
 157 /* Skylake Y */
 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 159         { 0x00000018, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x00007011, 0x00000087, 0x0 },
 162         { 0x80009010, 0x000000C0, 0x3 },        /* Uses I_boost level 0x3 */
 163         { 0x00000018, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x3 },        /* Uses I_boost level 0x3 */
 165         { 0x80007011, 0x000000C0, 0x3 },        /* Uses I_boost level 0x3 */
 166         { 0x00000018, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x3 },        /* Uses I_boost level 0x3 */
 168 };
 169
 170 /*
 171  * Skylake H and S
 172  * eDP 1.4 low vswing translation parameters
 173  */
 174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 175         { 0x00000018, 0x000000A8, 0x0 },
 176         { 0x00004013, 0x000000A9, 0x0 },
 177         { 0x00007011, 0x000000A2, 0x0 },
 178         { 0x00009010, 0x0000009C, 0x0 },
 179         { 0x00000018, 0x000000A9, 0x0 },
 180         { 0x00006013, 0x000000A2, 0x0 },
 181         { 0x00007011, 0x000000A6, 0x0 },
 182         { 0x00000018, 0x000000AB, 0x0 },
 183         { 0x00007013, 0x0000009F, 0x0 },
 184         { 0x00000018, 0x000000DF, 0x0 },
 185 };
 186
 187 /*
 188  * Skylake U
 189  * eDP 1.4 low vswing translation parameters
 190  */
 191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 192         { 0x00000018, 0x000000A8, 0x0 },
 193         { 0x00004013, 0x000000A9, 0x0 },
 194         { 0x00007011, 0x000000A2, 0x0 },
 195         { 0x00009010, 0x0000009C, 0x0 },
 196         { 0x00000018, 0x000000A9, 0x0 },
 197         { 0x00006013, 0x000000A2, 0x0 },
 198         { 0x00007011, 0x000000A6, 0x0 },
 199         { 0x00002016, 0x000000AB, 0x0 },
 200         { 0x00005013, 0x0000009F, 0x0 },
 201         { 0x00000018, 0x000000DF, 0x0 },
 202 };
 203
 204 /*
 205  * Skylake Y
 206  * eDP 1.4 low vswing translation parameters
 207  */
 208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 209         { 0x00000018, 0x000000A8, 0x0 },
 210         { 0x00004013, 0x000000AB, 0x0 },
 211         { 0x00007011, 0x000000A4, 0x0 },
 212         { 0x00009010, 0x000000DF, 0x0 },
 213         { 0x00000018, 0x000000AA, 0x0 },
 214         { 0x00006013, 0x000000A4, 0x0 },
 215         { 0x00007011, 0x0000009D, 0x0 },
 216         { 0x00000018, 0x000000A0, 0x0 },
 217         { 0x00006012, 0x000000DF, 0x0 },
 218         { 0x00000018, 0x0000008A, 0x0 },
 219 };
 220
 221 /* Skylake U, H and S */
 222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 223         { 0x00000018, 0x000000AC, 0x0 },
 224         { 0x00005012, 0x0000009D, 0x0 },
 225         { 0x00007011, 0x00000088, 0x0 },
 226         { 0x00000018, 0x000000A1, 0x0 },
 227         { 0x00000018, 0x00000098, 0x0 },
 228         { 0x00004013, 0x00000088, 0x0 },
 229         { 0x00006012, 0x00000087, 0x0 },
 230         { 0x00000018, 0x000000DF, 0x0 },
 231         { 0x00003015, 0x00000087, 0x0 },        /* Default */
 232         { 0x00003015, 0x000000C7, 0x0 },
 233         { 0x00000018, 0x000000C7, 0x0 },
 234 };
 235
 236 /* Skylake Y */
 237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 238         { 0x00000018, 0x000000A1, 0x0 },
 239         { 0x00005012, 0x000000DF, 0x0 },
 240         { 0x00007011, 0x00000084, 0x0 },
 241         { 0x00000018, 0x000000A4, 0x0 },
 242         { 0x00000018, 0x0000009D, 0x0 },
 243         { 0x00004013, 0x00000080, 0x0 },
 244         { 0x00006013, 0x000000C7, 0x0 },
 245         { 0x00000018, 0x0000008A, 0x0 },
 246         { 0x00003015, 0x000000C7, 0x0 },        /* Default */
 247         { 0x80003015, 0x000000C7, 0x7 },        /* Uses I_boost level 0x7 */
 248         { 0x00000018, 0x000000C7, 0x0 },
 249 };
 250
 251 struct bxt_ddi_buf_trans {
 252         u32 margin;     /* swing value */
 253         u32 scale;      /* scale value */
 254         u32 enable;     /* scale enable */
 255         u32 deemphasis;
 256         bool default_index; /* true if the entry represents default value */
 257 };
 258
 259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 260                                         /* Idx  NT mV diff      db  */
 261         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 262         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 263         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 264         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 265         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 266         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 267         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 268         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 269         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 270         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 271 };
 272
 273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 274                                         /* Idx  NT mV diff      db  */
 275         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 276         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 277         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 278         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 279         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 280         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 281         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 282         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 283         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 284         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 285 };
 286
 287 /* BSpec has 2 recommended values - entries 0 and 8.
 288  * Using the entry with higher vswing.
 289  */
 290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 291                                         /* Idx  NT mV diff      db  */
 292         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 293         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 294         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 295         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 296         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 297         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 298         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 299         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 300         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 301         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 302 };
 303
 304 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 305                                     enum port port, int type);
 306
 307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
 308                                  struct intel_digital_port **dig_port,
 309                                  enum port *port)
 310 {
 311         struct drm_encoder *encoder = &intel_encoder->base;
 312
 313         switch (intel_encoder->type) {
 314         case INTEL_OUTPUT_DP_MST:
 315                 *dig_port = enc_to_mst(encoder)->primary;
 316                 *port = (*dig_port)->port;
 317                 break;
 318         case INTEL_OUTPUT_DISPLAYPORT:
 319         case INTEL_OUTPUT_EDP:
 320         case INTEL_OUTPUT_HDMI:
 321         case INTEL_OUTPUT_UNKNOWN:
 322                 *dig_port = enc_to_dig_port(encoder);
 323                 *port = (*dig_port)->port;
 324                 break;
 325         case INTEL_OUTPUT_ANALOG:
 326                 *dig_port = NULL;
 327                 *port = PORT_E;
 328                 break;
 329         default:
 330                 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
 331                 break;
 332         }
 333 }
 334
 335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 336 {
 337         struct intel_digital_port *dig_port;
 338         enum port port;
 339
 340         ddi_get_encoder_port(intel_encoder, &dig_port, &port);
 341
 342         return port;
 343 }
 344
 345 static bool
 346 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
 347 {
 348         return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg);
 349 }
 350
 351 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
 352                                                         int *n_entries)
 353 {
 354         const struct ddi_buf_trans *ddi_translations;
 355
 356         if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
 357                 ddi_translations = skl_y_ddi_translations_dp;
 358                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 359         } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
 360                 ddi_translations = skl_u_ddi_translations_dp;
 361                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 362         } else {
 363                 ddi_translations = skl_ddi_translations_dp;
 364                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 365         }
 366
 367         return ddi_translations;
 368 }
 369
 370 static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
 371                                                          int *n_entries)
 372 {
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374         const struct ddi_buf_trans *ddi_translations;
 375
 376         if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
 377                 if (dev_priv->edp_low_vswing) {
 378                         ddi_translations = skl_y_ddi_translations_edp;
 379                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 380                 } else {
 381                         ddi_translations = skl_y_ddi_translations_dp;
 382                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 383                 }
 384         } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
 385                 if (dev_priv->edp_low_vswing) {
 386                         ddi_translations = skl_u_ddi_translations_edp;
 387                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 388                 } else {
 389                         ddi_translations = skl_u_ddi_translations_dp;
 390                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 391                 }
 392         } else {
 393                 if (dev_priv->edp_low_vswing) {
 394                         ddi_translations = skl_ddi_translations_edp;
 395                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 396                 } else {
 397                         ddi_translations = skl_ddi_translations_dp;
 398                         *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 399                 }
 400         }
 401
 402         return ddi_translations;
 403 }
 404
 405 static const struct ddi_buf_trans *
 406 skl_get_buf_trans_hdmi(struct drm_device *dev,
 407                        int *n_entries)
 408 {
 409         const struct ddi_buf_trans *ddi_translations;
 410
 411         if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
 412                 ddi_translations = skl_y_ddi_translations_hdmi;
 413                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 414         } else {
 415                 ddi_translations = skl_ddi_translations_hdmi;
 416                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 417         }
 418
 419         return ddi_translations;
 420 }
 421
 422 /*
 423  * Starting with Haswell, DDI port buffers must be programmed with correct
 424  * values in advance. The buffer values are different for FDI and DP modes,
 425  * but the HDMI/DVI fields are shared among those. So we program the DDI
 426  * in either FDI or DP modes only, as HDMI connections will work with both
 427  * of those
 428  */
 429 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
 430                                       bool supports_hdmi)
 431 {
 432         struct drm_i915_private *dev_priv = dev->dev_private;
 433         u32 iboost_bit = 0;
 434         int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 435             size;
 436         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 437         const struct ddi_buf_trans *ddi_translations_fdi;
 438         const struct ddi_buf_trans *ddi_translations_dp;
 439         const struct ddi_buf_trans *ddi_translations_edp;
 440         const struct ddi_buf_trans *ddi_translations_hdmi;
 441         const struct ddi_buf_trans *ddi_translations;
 442
 443         if (IS_BROXTON(dev)) {
 444                 if (!supports_hdmi)
 445                         return;
 446
 447                 /* Vswing programming for HDMI */
 448                 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
 449                                         INTEL_OUTPUT_HDMI);
 450                 return;
 451         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 452                 ddi_translations_fdi = NULL;
 453                 ddi_translations_dp =
 454                                 skl_get_buf_trans_dp(dev, &n_dp_entries);
 455                 ddi_translations_edp =
 456                                 skl_get_buf_trans_edp(dev, &n_edp_entries);
 457                 ddi_translations_hdmi =
 458                                 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
 459                 hdmi_default_entry = 8;
 460                 /* If we're boosting the current, set bit 31 of trans1 */
 461                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
 462                     dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 463                         iboost_bit = 1<<31;
 464         } else if (IS_BROADWELL(dev)) {
 465                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 466                 ddi_translations_dp = bdw_ddi_translations_dp;
 467                 ddi_translations_edp = bdw_ddi_translations_edp;
 468                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 469                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 470                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 471                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 472                 hdmi_default_entry = 7;
 473         } else if (IS_HASWELL(dev)) {
 474                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 475                 ddi_translations_dp = hsw_ddi_translations_dp;
 476                 ddi_translations_edp = hsw_ddi_translations_dp;
 477                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 478                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 479                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 480                 hdmi_default_entry = 6;
 481         } else {
 482                 WARN(1, "ddi translation table missing\n");
 483                 ddi_translations_edp = bdw_ddi_translations_dp;
 484                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 485                 ddi_translations_dp = bdw_ddi_translations_dp;
 486                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 487                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 488                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 489                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 490                 hdmi_default_entry = 7;
 491         }
 492
 493         switch (port) {
 494         case PORT_A:
 495                 ddi_translations = ddi_translations_edp;
 496                 size = n_edp_entries;
 497                 break;
 498         case PORT_B:
 499         case PORT_C:
 500                 ddi_translations = ddi_translations_dp;
 501                 size = n_dp_entries;
 502                 break;
 503         case PORT_D:
 504                 if (intel_dp_is_edp(dev, PORT_D)) {
 505                         ddi_translations = ddi_translations_edp;
 506                         size = n_edp_entries;
 507                 } else {
 508                         ddi_translations = ddi_translations_dp;
 509                         size = n_dp_entries;
 510                 }
 511                 break;
 512         case PORT_E:
 513                 if (ddi_translations_fdi)
 514                         ddi_translations = ddi_translations_fdi;
 515                 else
 516                         ddi_translations = ddi_translations_dp;
 517                 size = n_dp_entries;
 518                 break;
 519         default:
 520                 BUG();
 521         }
 522
 523         for (i = 0; i < size; i++) {
 524                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 525                            ddi_translations[i].trans1 | iboost_bit);
 526                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 527                            ddi_translations[i].trans2);
 528         }
 529
 530         if (!supports_hdmi)
 531                 return;
 532
 533         /* Choose a good default if VBT is badly populated */
 534         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 535             hdmi_level >= n_hdmi_entries)
 536                 hdmi_level = hdmi_default_entry;
 537
 538         /* Entry 9 is for HDMI: */
 539         I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 540                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 541         I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 542                    ddi_translations_hdmi[hdmi_level].trans2);
 543 }
 544
 545 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 546  * mode and port E for FDI.
 547  */
 548 void intel_prepare_ddi(struct drm_device *dev)
 549 {
 550         struct intel_encoder *intel_encoder;
 551         bool visited[I915_MAX_PORTS] = { 0, };
 552
 553         if (!HAS_DDI(dev))
 554                 return;
 555
 556         for_each_intel_encoder(dev, intel_encoder) {
 557                 struct intel_digital_port *intel_dig_port;
 558                 enum port port;
 559                 bool supports_hdmi;
 560
 561                 if (intel_encoder->type == INTEL_OUTPUT_DSI)
 562                         continue;
 563
 564                 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
 565                 if (visited[port])
 566                         continue;
 567
 568                 supports_hdmi = intel_dig_port &&
 569                                 intel_dig_port_supports_hdmi(intel_dig_port);
 570
 571                 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
 572                 visited[port] = true;
 573         }
 574 }
 575
 576 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 577                                     enum port port)
 578 {
 579         i915_reg_t reg = DDI_BUF_CTL(port);
 580         int i;
 581
 582         for (i = 0; i < 16; i++) {
 583                 udelay(1);
 584                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 585                         return;
 586         }
 587         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 588 }
 589
 590 /* Starting with Haswell, different DDI ports can work in FDI mode for
 591  * connection to the PCH-located connectors. For this, it is necessary to train
 592  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 593  *
 594  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 595  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 596  * DDI A (which is used for eDP)
 597  */
 598
 599 void hsw_fdi_link_train(struct drm_crtc *crtc)
 600 {
 601         struct drm_device *dev = crtc->dev;
 602         struct drm_i915_private *dev_priv = dev->dev_private;
 603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 604         u32 temp, i, rx_ctl_val;
 605
 606         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 607          * mode set "sequence for CRT port" document:
 608          * - TP1 to TP2 time with the default value
 609          * - FDI delay to 90h
 610          *
 611          * WaFDIAutoLinkSetTimingOverrride:hsw
 612          */
 613         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 614                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 615                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 616
 617         /* Enable the PCH Receiver FDI PLL */
 618         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 619                      FDI_RX_PLL_ENABLE |
 620                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 621         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 622         POSTING_READ(FDI_RX_CTL(PIPE_A));
 623         udelay(220);
 624
 625         /* Switch from Rawclk to PCDclk */
 626         rx_ctl_val |= FDI_PCDCLK;
 627         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 628
 629         /* Configure Port Clock Select */
 630         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
 631         WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 632
 633         /* Start the training iterating through available voltages and emphasis,
 634          * testing each value twice. */
 635         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 636                 /* Configure DP_TP_CTL with auto-training */
 637                 I915_WRITE(DP_TP_CTL(PORT_E),
 638                                         DP_TP_CTL_FDI_AUTOTRAIN |
 639                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 640                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 641                                         DP_TP_CTL_ENABLE);
 642
 643                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 644                  * DDI E does not support port reversal, the functionality is
 645                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 646                  * port reversal bit */
 647                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 648                            DDI_BUF_CTL_ENABLE |
 649                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 650                            DDI_BUF_TRANS_SELECT(i / 2));
 651                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 652
 653                 udelay(600);
 654
 655                 /* Program PCH FDI Receiver TU */
 656                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 657
 658                 /* Enable PCH FDI Receiver with auto-training */
 659                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 660                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 661                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 662
 663                 /* Wait for FDI receiver lane calibration */
 664                 udelay(30);
 665
 666                 /* Unset FDI_RX_MISC pwrdn lanes */
 667                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 668                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 669                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 670                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 671
 672                 /* Wait for FDI auto training time */
 673                 udelay(5);
 674
 675                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 676                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 677                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 678                         break;
 679                 }
 680
 681                 /*
 682                  * Leave things enabled even if we failed to train FDI.
 683                  * Results in less fireworks from the state checker.
 684                  */
 685                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 686                         DRM_ERROR("FDI link training failed!\n");
 687                         break;
 688                 }
 689
 690                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 691                 temp &= ~DDI_BUF_CTL_ENABLE;
 692                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 693                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 694
 695                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 696                 temp = I915_READ(DP_TP_CTL(PORT_E));
 697                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 698                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 699                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 700                 POSTING_READ(DP_TP_CTL(PORT_E));
 701
 702                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 703
 704                 rx_ctl_val &= ~FDI_RX_ENABLE;
 705                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 706                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 707
 708                 /* Reset FDI_RX_MISC pwrdn lanes */
 709                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 710                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 711                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 712                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 713                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 714         }
 715
 716         /* Enable normal pixel sending for FDI */
 717         I915_WRITE(DP_TP_CTL(PORT_E),
 718                    DP_TP_CTL_FDI_AUTOTRAIN |
 719                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 720                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 721                    DP_TP_CTL_ENABLE);
 722 }
 723
 724 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 725 {
 726         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 727         struct intel_digital_port *intel_dig_port =
 728                 enc_to_dig_port(&encoder->base);
 729
 730         intel_dp->DP = intel_dig_port->saved_port_bits |
 731                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 732         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 733 }
 734
 735 static struct intel_encoder *
 736 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 740         struct intel_encoder *intel_encoder, *ret = NULL;
 741         int num_encoders = 0;
 742
 743         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 744                 ret = intel_encoder;
 745                 num_encoders++;
 746         }
 747
 748         if (num_encoders != 1)
 749                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 750                      pipe_name(intel_crtc->pipe));
 751
 752         BUG_ON(ret == NULL);
 753         return ret;
 754 }
 755
 756 struct intel_encoder *
 757 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 758 {
 759         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 760         struct intel_encoder *ret = NULL;
 761         struct drm_atomic_state *state;
 762         struct drm_connector *connector;
 763         struct drm_connector_state *connector_state;
 764         int num_encoders = 0;
 765         int i;
 766
 767         state = crtc_state->base.state;
 768
 769         for_each_connector_in_state(state, connector, connector_state, i) {
 770                 if (connector_state->crtc != crtc_state->base.crtc)
 771                         continue;
 772
 773                 ret = to_intel_encoder(connector_state->best_encoder);
 774                 num_encoders++;
 775         }
 776
 777         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 778              pipe_name(crtc->pipe));
 779
 780         BUG_ON(ret == NULL);
 781         return ret;
 782 }
 783
 784 #define LC_FREQ 2700
 785 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 786
 787 #define P_MIN 2
 788 #define P_MAX 64
 789 #define P_INC 2
 790
 791 /* Constraints for PLL good behavior */
 792 #define REF_MIN 48
 793 #define REF_MAX 400
 794 #define VCO_MIN 2400
 795 #define VCO_MAX 4800
 796
 797 #define abs_diff(a, b) ({                       \
 798         typeof(a) __a = (a);                    \
 799         typeof(b) __b = (b);                    \
 800         (void) (&__a == &__b);                  \
 801         __a > __b ? (__a - __b) : (__b - __a); })
 802
 803 struct hsw_wrpll_rnp {
 804         unsigned p, n2, r2;
 805 };
 806
 807 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
 808 {
 809         unsigned budget;
 810
 811         switch (clock) {
 812         case 25175000:
 813         case 25200000:
 814         case 27000000:
 815         case 27027000:
 816         case 37762500:
 817         case 37800000:
 818         case 40500000:
 819         case 40541000:
 820         case 54000000:
 821         case 54054000:
 822         case 59341000:
 823         case 59400000:
 824         case 72000000:
 825         case 74176000:
 826         case 74250000:
 827         case 81000000:
 828         case 81081000:
 829         case 89012000:
 830         case 89100000:
 831         case 108000000:
 832         case 108108000:
 833         case 111264000:
 834         case 111375000:
 835         case 148352000:
 836         case 148500000:
 837         case 162000000:
 838         case 162162000:
 839         case 222525000:
 840         case 222750000:
 841         case 296703000:
 842         case 297000000:
 843                 budget = 0;
 844                 break;
 845         case 233500000:
 846         case 245250000:
 847         case 247750000:
 848         case 253250000:
 849         case 298000000:
 850                 budget = 1500;
 851                 break;
 852         case 169128000:
 853         case 169500000:
 854         case 179500000:
 855         case 202000000:
 856                 budget = 2000;
 857                 break;
 858         case 256250000:
 859         case 262500000:
 860         case 270000000:
 861         case 272500000:
 862         case 273750000:
 863         case 280750000:
 864         case 281250000:
 865         case 286000000:
 866         case 291750000:
 867                 budget = 4000;
 868                 break;
 869         case 267250000:
 870         case 268500000:
 871                 budget = 5000;
 872                 break;
 873         default:
 874                 budget = 1000;
 875                 break;
 876         }
 877
 878         return budget;
 879 }
 880
 881 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 882                                  unsigned r2, unsigned n2, unsigned p,
 883                                  struct hsw_wrpll_rnp *best)
 884 {
 885         uint64_t a, b, c, d, diff, diff_best;
 886
 887         /* No best (r,n,p) yet */
 888         if (best->p == 0) {
 889                 best->p = p;
 890                 best->n2 = n2;
 891                 best->r2 = r2;
 892                 return;
 893         }
 894
 895         /*
 896          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 897          * freq2k.
 898          *
 899          * delta = 1e6 *
 900          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 901          *         freq2k;
 902          *
 903          * and we would like delta <= budget.
 904          *
 905          * If the discrepancy is above the PPM-based budget, always prefer to
 906          * improve upon the previous solution.  However, if you're within the
 907          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 908          */
 909         a = freq2k * budget * p * r2;
 910         b = freq2k * budget * best->p * best->r2;
 911         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 912         diff_best = abs_diff(freq2k * best->p * best->r2,
 913                              LC_FREQ_2K * best->n2);
 914         c = 1000000 * diff;
 915         d = 1000000 * diff_best;
 916
 917         if (a < c && b < d) {
 918                 /* If both are above the budget, pick the closer */
 919                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 920                         best->p = p;
 921                         best->n2 = n2;
 922                         best->r2 = r2;
 923                 }
 924         } else if (a >= c && b < d) {
 925                 /* If A is below the threshold but B is above it?  Update. */
 926                 best->p = p;
 927                 best->n2 = n2;
 928                 best->r2 = r2;
 929         } else if (a >= c && b >= d) {
 930                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 931                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 932                         best->p = p;
 933                         best->n2 = n2;
 934                         best->r2 = r2;
 935                 }
 936         }
 937         /* Otherwise a < c && b >= d, do nothing */
 938 }
 939
 940 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 941                                    i915_reg_t reg)
 942 {
 943         int refclk = LC_FREQ;
 944         int n, p, r;
 945         u32 wrpll;
 946
 947         wrpll = I915_READ(reg);
 948         switch (wrpll & WRPLL_PLL_REF_MASK) {
 949         case WRPLL_PLL_SSC:
 950         case WRPLL_PLL_NON_SSC:
 951                 /*
 952                  * We could calculate spread here, but our checking
 953                  * code only cares about 5% accuracy, and spread is a max of
 954                  * 0.5% downspread.
 955                  */
 956                 refclk = 135;
 957                 break;
 958         case WRPLL_PLL_LCPLL:
 959                 refclk = LC_FREQ;
 960                 break;
 961         default:
 962                 WARN(1, "bad wrpll refclk\n");
 963                 return 0;
 964         }
 965
 966         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 967         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 968         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 969
 970         /* Convert to KHz, p & r have a fixed point portion */
 971         return (refclk * n * 100) / (p * r);
 972 }
 973
 974 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 975                                uint32_t dpll)
 976 {
 977         i915_reg_t cfgcr1_reg, cfgcr2_reg;
 978         uint32_t cfgcr1_val, cfgcr2_val;
 979         uint32_t p0, p1, p2, dco_freq;
 980
 981         cfgcr1_reg = DPLL_CFGCR1(dpll);
 982         cfgcr2_reg = DPLL_CFGCR2(dpll);
 983
 984         cfgcr1_val = I915_READ(cfgcr1_reg);
 985         cfgcr2_val = I915_READ(cfgcr2_reg);
 986
 987         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 988         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 989
 990         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 991                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 992         else
 993                 p1 = 1;
 994
 995
 996         switch (p0) {
 997         case DPLL_CFGCR2_PDIV_1:
 998                 p0 = 1;
 999                 break;
1000         case DPLL_CFGCR2_PDIV_2:
1001                 p0 = 2;
1002                 break;
1003         case DPLL_CFGCR2_PDIV_3:
1004                 p0 = 3;
1005                 break;
1006         case DPLL_CFGCR2_PDIV_7:
1007                 p0 = 7;
1008                 break;
1009         }
1010
1011         switch (p2) {
1012         case DPLL_CFGCR2_KDIV_5:
1013                 p2 = 5;
1014                 break;
1015         case DPLL_CFGCR2_KDIV_2:
1016                 p2 = 2;
1017                 break;
1018         case DPLL_CFGCR2_KDIV_3:
1019                 p2 = 3;
1020                 break;
1021         case DPLL_CFGCR2_KDIV_1:
1022                 p2 = 1;
1023                 break;
1024         }
1025
1026         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1027
1028         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1029                 1000) / 0x8000;
1030
1031         return dco_freq / (p0 * p1 * p2 * 5);
1032 }
1033
1034 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1035 {
1036         int dotclock;
1037
1038         if (pipe_config->has_pch_encoder)
1039                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1040                                                     &pipe_config->fdi_m_n);
1041         else if (pipe_config->has_dp_encoder)
1042                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1043                                                     &pipe_config->dp_m_n);
1044         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1045                 dotclock = pipe_config->port_clock * 2 / 3;
1046         else
1047                 dotclock = pipe_config->port_clock;
1048
1049         if (pipe_config->pixel_multiplier)
1050                 dotclock /= pipe_config->pixel_multiplier;
1051
1052         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1053 }
1054
1055 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1056                                 struct intel_crtc_state *pipe_config)
1057 {
1058         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1059         int link_clock = 0;
1060         uint32_t dpll_ctl1, dpll;
1061
1062         dpll = pipe_config->ddi_pll_sel;
1063
1064         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1065
1066         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1067                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1068         } else {
1069                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1070                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1071
1072                 switch (link_clock) {
1073                 case DPLL_CTRL1_LINK_RATE_810:
1074                         link_clock = 81000;
1075                         break;
1076                 case DPLL_CTRL1_LINK_RATE_1080:
1077                         link_clock = 108000;
1078                         break;
1079                 case DPLL_CTRL1_LINK_RATE_1350:
1080                         link_clock = 135000;
1081                         break;
1082                 case DPLL_CTRL1_LINK_RATE_1620:
1083                         link_clock = 162000;
1084                         break;
1085                 case DPLL_CTRL1_LINK_RATE_2160:
1086                         link_clock = 216000;
1087                         break;
1088                 case DPLL_CTRL1_LINK_RATE_2700:
1089                         link_clock = 270000;
1090                         break;
1091                 default:
1092                         WARN(1, "Unsupported link rate\n");
1093                         break;
1094                 }
1095                 link_clock *= 2;
1096         }
1097
1098         pipe_config->port_clock = link_clock;
1099
1100         ddi_dotclock_get(pipe_config);
1101 }
1102
1103 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1104                               struct intel_crtc_state *pipe_config)
1105 {
1106         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1107         int link_clock = 0;
1108         u32 val, pll;
1109
1110         val = pipe_config->ddi_pll_sel;
1111         switch (val & PORT_CLK_SEL_MASK) {
1112         case PORT_CLK_SEL_LCPLL_810:
1113                 link_clock = 81000;
1114                 break;
1115         case PORT_CLK_SEL_LCPLL_1350:
1116                 link_clock = 135000;
1117                 break;
1118         case PORT_CLK_SEL_LCPLL_2700:
1119                 link_clock = 270000;
1120                 break;
1121         case PORT_CLK_SEL_WRPLL1:
1122                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1123                 break;
1124         case PORT_CLK_SEL_WRPLL2:
1125                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1126                 break;
1127         case PORT_CLK_SEL_SPLL:
1128                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1129                 if (pll == SPLL_PLL_FREQ_810MHz)
1130                         link_clock = 81000;
1131                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1132                         link_clock = 135000;
1133                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1134                         link_clock = 270000;
1135                 else {
1136                         WARN(1, "bad spll freq\n");
1137                         return;
1138                 }
1139                 break;
1140         default:
1141                 WARN(1, "bad port clock sel\n");
1142                 return;
1143         }
1144
1145         pipe_config->port_clock = link_clock * 2;
1146
1147         ddi_dotclock_get(pipe_config);
1148 }
1149
1150 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1151                                 enum intel_dpll_id dpll)
1152 {
1153         struct intel_shared_dpll *pll;
1154         struct intel_dpll_hw_state *state;
1155         intel_clock_t clock;
1156
1157         /* For DDI ports we always use a shared PLL. */
1158         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1159                 return 0;
1160
1161         pll = &dev_priv->shared_dplls[dpll];
1162         state = &pll->config.hw_state;
1163
1164         clock.m1 = 2;
1165         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1166         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1167                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1168         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1169         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1170         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1171
1172         return chv_calc_dpll_params(100000, &clock);
1173 }
1174
1175 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1176                                 struct intel_crtc_state *pipe_config)
1177 {
1178         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1179         enum port port = intel_ddi_get_encoder_port(encoder);
1180         uint32_t dpll = port;
1181
1182         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1183
1184         ddi_dotclock_get(pipe_config);
1185 }
1186
1187 void intel_ddi_clock_get(struct intel_encoder *encoder,
1188                          struct intel_crtc_state *pipe_config)
1189 {
1190         struct drm_device *dev = encoder->base.dev;
1191
1192         if (INTEL_INFO(dev)->gen <= 8)
1193                 hsw_ddi_clock_get(encoder, pipe_config);
1194         else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1195                 skl_ddi_clock_get(encoder, pipe_config);
1196         else if (IS_BROXTON(dev))
1197                 bxt_ddi_clock_get(encoder, pipe_config);
1198 }
1199
1200 static void
1201 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1202                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1203 {
1204         uint64_t freq2k;
1205         unsigned p, n2, r2;
1206         struct hsw_wrpll_rnp best = { 0, 0, 0 };
1207         unsigned budget;
1208
1209         freq2k = clock / 100;
1210
1211         budget = hsw_wrpll_get_budget_for_freq(clock);
1212
1213         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1214          * and directly pass the LC PLL to it. */
1215         if (freq2k == 5400000) {
1216                 *n2_out = 2;
1217                 *p_out = 1;
1218                 *r2_out = 2;
1219                 return;
1220         }
1221
1222         /*
1223          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1224          * the WR PLL.
1225          *
1226          * We want R so that REF_MIN <= Ref <= REF_MAX.
1227          * Injecting R2 = 2 * R gives:
1228          *   REF_MAX * r2 > LC_FREQ * 2 and
1229          *   REF_MIN * r2 < LC_FREQ * 2
1230          *
1231          * Which means the desired boundaries for r2 are:
1232          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1233          *
1234          */
1235         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1236              r2 <= LC_FREQ * 2 / REF_MIN;
1237              r2++) {
1238
1239                 /*
1240                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1241                  *
1242                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1243                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1244                  *   VCO_MAX * r2 > n2 * LC_FREQ and
1245                  *   VCO_MIN * r2 < n2 * LC_FREQ)
1246                  *
1247                  * Which means the desired boundaries for n2 are:
1248                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1249                  */
1250                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1251                      n2 <= VCO_MAX * r2 / LC_FREQ;
1252                      n2++) {
1253
1254                         for (p = P_MIN; p <= P_MAX; p += P_INC)
1255                                 hsw_wrpll_update_rnp(freq2k, budget,
1256                                                      r2, n2, p, &best);
1257                 }
1258         }
1259
1260         *n2_out = best.n2;
1261         *p_out = best.p;
1262         *r2_out = best.r2;
1263 }
1264
1265 static bool
1266 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1267                    struct intel_crtc_state *crtc_state,
1268                    struct intel_encoder *intel_encoder)
1269 {
1270         int clock = crtc_state->port_clock;
1271
1272         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1273                 struct intel_shared_dpll *pll;
1274                 uint32_t val;
1275                 unsigned p, n2, r2;
1276
1277                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1278
1279                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1280                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1281                       WRPLL_DIVIDER_POST(p);
1282
1283                 memset(&crtc_state->dpll_hw_state, 0,
1284                        sizeof(crtc_state->dpll_hw_state));
1285
1286                 crtc_state->dpll_hw_state.wrpll = val;
1287
1288                 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1289                 if (pll == NULL) {
1290                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1291                                          pipe_name(intel_crtc->pipe));
1292                         return false;
1293                 }
1294
1295                 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1296         } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1297                 struct drm_atomic_state *state = crtc_state->base.state;
1298                 struct intel_shared_dpll_config *spll =
1299                         &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1300
1301                 if (spll->crtc_mask &&
1302                     WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1303                         return false;
1304
1305                 crtc_state->shared_dpll = DPLL_ID_SPLL;
1306                 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1307                 spll->crtc_mask |= 1 << intel_crtc->pipe;
1308         }
1309
1310         return true;
1311 }
1312
1313 struct skl_wrpll_context {
1314         uint64_t min_deviation;         /* current minimal deviation */
1315         uint64_t central_freq;          /* chosen central freq */
1316         uint64_t dco_freq;              /* chosen dco freq */
1317         unsigned int p;                 /* chosen divider */
1318 };
1319
1320 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1321 {
1322         memset(ctx, 0, sizeof(*ctx));
1323
1324         ctx->min_deviation = U64_MAX;
1325 }
1326
1327 /* DCO freq must be within +1%/-6%  of the DCO central freq */
1328 #define SKL_DCO_MAX_PDEVIATION  100
1329 #define SKL_DCO_MAX_NDEVIATION  600
1330
1331 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1332                                   uint64_t central_freq,
1333                                   uint64_t dco_freq,
1334                                   unsigned int divider)
1335 {
1336         uint64_t deviation;
1337
1338         deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1339                               central_freq);
1340
1341         /* positive deviation */
1342         if (dco_freq >= central_freq) {
1343                 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1344                     deviation < ctx->min_deviation) {
1345                         ctx->min_deviation = deviation;
1346                         ctx->central_freq = central_freq;
1347                         ctx->dco_freq = dco_freq;
1348                         ctx->p = divider;
1349                 }
1350         /* negative deviation */
1351         } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1352                    deviation < ctx->min_deviation) {
1353                 ctx->min_deviation = deviation;
1354                 ctx->central_freq = central_freq;
1355                 ctx->dco_freq = dco_freq;
1356                 ctx->p = divider;
1357         }
1358 }
1359
1360 static void skl_wrpll_get_multipliers(unsigned int p,
1361                                       unsigned int *p0 /* out */,
1362                                       unsigned int *p1 /* out */,
1363                                       unsigned int *p2 /* out */)
1364 {
1365         /* even dividers */
1366         if (p % 2 == 0) {
1367                 unsigned int half = p / 2;
1368
1369                 if (half == 1 || half == 2 || half == 3 || half == 5) {
1370                         *p0 = 2;
1371                         *p1 = 1;
1372                         *p2 = half;
1373                 } else if (half % 2 == 0) {
1374                         *p0 = 2;
1375                         *p1 = half / 2;
1376                         *p2 = 2;
1377                 } else if (half % 3 == 0) {
1378                         *p0 = 3;
1379                         *p1 = half / 3;
1380                         *p2 = 2;
1381                 } else if (half % 7 == 0) {
1382                         *p0 = 7;
1383                         *p1 = half / 7;
1384                         *p2 = 2;
1385                 }
1386         } else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
1387                 *p0 = 3;
1388                 *p1 = 1;
1389                 *p2 = p / 3;
1390         } else if (p == 5 || p == 7) {
1391                 *p0 = p;
1392                 *p1 = 1;
1393                 *p2 = 1;
1394         } else if (p == 15) {
1395                 *p0 = 3;
1396                 *p1 = 1;
1397                 *p2 = 5;
1398         } else if (p == 21) {
1399                 *p0 = 7;
1400                 *p1 = 1;
1401                 *p2 = 3;
1402         } else if (p == 35) {
1403                 *p0 = 7;
1404                 *p1 = 1;
1405                 *p2 = 5;
1406         }
1407 }
1408
1409 struct skl_wrpll_params {
1410         uint32_t        dco_fraction;
1411         uint32_t        dco_integer;
1412         uint32_t        qdiv_ratio;
1413         uint32_t        qdiv_mode;
1414         uint32_t        kdiv;
1415         uint32_t        pdiv;
1416         uint32_t        central_freq;
1417 };
1418
1419 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1420                                       uint64_t afe_clock,
1421                                       uint64_t central_freq,
1422                                       uint32_t p0, uint32_t p1, uint32_t p2)
1423 {
1424         uint64_t dco_freq;
1425
1426         switch (central_freq) {
1427         case 9600000000ULL:
1428                 params->central_freq = 0;
1429                 break;
1430         case 9000000000ULL:
1431                 params->central_freq = 1;
1432                 break;
1433         case 8400000000ULL:
1434                 params->central_freq = 3;
1435         }
1436
1437         switch (p0) {
1438         case 1:
1439                 params->pdiv = 0;
1440                 break;
1441         case 2:
1442                 params->pdiv = 1;
1443                 break;
1444         case 3:
1445                 params->pdiv = 2;
1446                 break;
1447         case 7:
1448                 params->pdiv = 4;
1449                 break;
1450         default:
1451                 WARN(1, "Incorrect PDiv\n");
1452         }
1453
1454         switch (p2) {
1455         case 5:
1456                 params->kdiv = 0;
1457                 break;
1458         case 2:
1459                 params->kdiv = 1;
1460                 break;
1461         case 3:
1462                 params->kdiv = 2;
1463                 break;
1464         case 1:
1465                 params->kdiv = 3;
1466                 break;
1467         default:
1468                 WARN(1, "Incorrect KDiv\n");
1469         }
1470
1471         params->qdiv_ratio = p1;
1472         params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1473
1474         dco_freq = p0 * p1 * p2 * afe_clock;
1475
1476         /*
1477          * Intermediate values are in Hz.
1478          * Divide by MHz to match bsepc
1479          */
1480         params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1481         params->dco_fraction =
1482                 div_u64((div_u64(dco_freq, 24) -
1483                          params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1484 }
1485
1486 static bool
1487 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1488                         struct skl_wrpll_params *wrpll_params)
1489 {
1490         uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1491         uint64_t dco_central_freq[3] = {8400000000ULL,
1492                                         9000000000ULL,
1493                                         9600000000ULL};
1494         static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
1495                                              24, 28, 30, 32, 36, 40, 42, 44,
1496                                              48, 52, 54, 56, 60, 64, 66, 68,
1497                                              70, 72, 76, 78, 80, 84, 88, 90,
1498                                              92, 96, 98 };
1499         static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1500         static const struct {
1501                 const int *list;
1502                 int n_dividers;
1503         } dividers[] = {
1504                 { even_dividers, ARRAY_SIZE(even_dividers) },
1505                 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1506         };
1507         struct skl_wrpll_context ctx;
1508         unsigned int dco, d, i;
1509         unsigned int p0, p1, p2;
1510
1511         skl_wrpll_context_init(&ctx);
1512
1513         for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1514                 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1515                         for (i = 0; i < dividers[d].n_dividers; i++) {
1516                                 unsigned int p = dividers[d].list[i];
1517                                 uint64_t dco_freq = p * afe_clock;
1518
1519                                 skl_wrpll_try_divider(&ctx,
1520                                                       dco_central_freq[dco],
1521                                                       dco_freq,
1522                                                       p);
1523                                 /*
1524                                  * Skip the remaining dividers if we're sure to
1525                                  * have found the definitive divider, we can't
1526                                  * improve a 0 deviation.
1527                                  */
1528                                 if (ctx.min_deviation == 0)
1529                                         goto skip_remaining_dividers;
1530                         }
1531                 }
1532
1533 skip_remaining_dividers:
1534                 /*
1535                  * If a solution is found with an even divider, prefer
1536                  * this one.
1537                  */
1538                 if (d == 0 && ctx.p)
1539                         break;
1540         }
1541
1542         if (!ctx.p) {
1543                 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1544                 return false;
1545         }
1546
1547         /*
1548          * gcc incorrectly analyses that these can be used without being
1549          * initialized. To be fair, it's hard to guess.
1550          */
1551         p0 = p1 = p2 = 0;
1552         skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1553         skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1554                                   p0, p1, p2);
1555
1556         return true;
1557 }
1558
1559 static bool
1560 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1561                    struct intel_crtc_state *crtc_state,
1562                    struct intel_encoder *intel_encoder)
1563 {
1564         struct intel_shared_dpll *pll;
1565         uint32_t ctrl1, cfgcr1, cfgcr2;
1566         int clock = crtc_state->port_clock;
1567
1568         /*
1569          * See comment in intel_dpll_hw_state to understand why we always use 0
1570          * as the DPLL id in this function.
1571          */
1572
1573         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1574
1575         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1576                 struct skl_wrpll_params wrpll_params = { 0, };
1577
1578                 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1579
1580                 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1581                         return false;
1582
1583                 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1584                          DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1585                          wrpll_params.dco_integer;
1586
1587                 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1588                          DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1589                          DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1590                          DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1591                          wrpll_params.central_freq;
1592         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1593                    intel_encoder->type == INTEL_OUTPUT_DP_MST) {
1594                 switch (crtc_state->port_clock / 2) {
1595                 case 81000:
1596                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1597                         break;
1598                 case 135000:
1599                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1600                         break;
1601                 case 270000:
1602                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1603                         break;
1604                 }
1605
1606                 cfgcr1 = cfgcr2 = 0;
1607         } else /* eDP */
1608                 return true;
1609
1610         memset(&crtc_state->dpll_hw_state, 0,
1611                sizeof(crtc_state->dpll_hw_state));
1612
1613         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1614         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1615         crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1616
1617         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1618         if (pll == NULL) {
1619                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1620                                  pipe_name(intel_crtc->pipe));
1621                 return false;
1622         }
1623
1624         /* shared DPLL id 0 is DPLL 1 */
1625         crtc_state->ddi_pll_sel = pll->id + 1;
1626
1627         return true;
1628 }
1629
1630 /* bxt clock parameters */
1631 struct bxt_clk_div {
1632         int clock;
1633         uint32_t p1;
1634         uint32_t p2;
1635         uint32_t m2_int;
1636         uint32_t m2_frac;
1637         bool m2_frac_en;
1638         uint32_t n;
1639 };
1640
1641 /* pre-calculated values for DP linkrates */
1642 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1643         {162000, 4, 2, 32, 1677722, 1, 1},
1644         {270000, 4, 1, 27,       0, 0, 1},
1645         {540000, 2, 1, 27,       0, 0, 1},
1646         {216000, 3, 2, 32, 1677722, 1, 1},
1647         {243000, 4, 1, 24, 1258291, 1, 1},
1648         {324000, 4, 1, 32, 1677722, 1, 1},
1649         {432000, 3, 1, 32, 1677722, 1, 1}
1650 };
1651
1652 static bool
1653 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1654                    struct intel_crtc_state *crtc_state,
1655                    struct intel_encoder *intel_encoder)
1656 {
1657         struct intel_shared_dpll *pll;
1658         struct bxt_clk_div clk_div = {0};
1659         int vco = 0;
1660         uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1661         uint32_t lanestagger;
1662         int clock = crtc_state->port_clock;
1663
1664         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1665                 intel_clock_t best_clock;
1666
1667                 /* Calculate HDMI div */
1668                 /*
1669                  * FIXME: tie the following calculation into
1670                  * i9xx_crtc_compute_clock
1671                  */
1672                 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1673                         DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1674                                          clock, pipe_name(intel_crtc->pipe));
1675                         return false;
1676                 }
1677
1678                 clk_div.p1 = best_clock.p1;
1679                 clk_div.p2 = best_clock.p2;
1680                 WARN_ON(best_clock.m1 != 2);
1681                 clk_div.n = best_clock.n;
1682                 clk_div.m2_int = best_clock.m2 >> 22;
1683                 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1684                 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1685
1686                 vco = best_clock.vco;
1687         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1688                         intel_encoder->type == INTEL_OUTPUT_EDP) {
1689                 int i;
1690
1691                 clk_div = bxt_dp_clk_val[0];
1692                 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1693                         if (bxt_dp_clk_val[i].clock == clock) {
1694                                 clk_div = bxt_dp_clk_val[i];
1695                                 break;
1696                         }
1697                 }
1698                 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1699         }
1700
1701         if (vco >= 6200000 && vco <= 6700000) {
1702                 prop_coef = 4;
1703                 int_coef = 9;
1704                 gain_ctl = 3;
1705                 targ_cnt = 8;
1706         } else if ((vco > 5400000 && vco < 6200000) ||
1707                         (vco >= 4800000 && vco < 5400000)) {
1708                 prop_coef = 5;
1709                 int_coef = 11;
1710                 gain_ctl = 3;
1711                 targ_cnt = 9;
1712         } else if (vco == 5400000) {
1713                 prop_coef = 3;
1714                 int_coef = 8;
1715                 gain_ctl = 1;
1716                 targ_cnt = 9;
1717         } else {
1718                 DRM_ERROR("Invalid VCO\n");
1719                 return false;
1720         }
1721
1722         memset(&crtc_state->dpll_hw_state, 0,
1723                sizeof(crtc_state->dpll_hw_state));
1724
1725         if (clock > 270000)
1726                 lanestagger = 0x18;
1727         else if (clock > 135000)
1728                 lanestagger = 0x0d;
1729         else if (clock > 67000)
1730                 lanestagger = 0x07;
1731         else if (clock > 33000)
1732                 lanestagger = 0x04;
1733         else
1734                 lanestagger = 0x02;
1735
1736         crtc_state->dpll_hw_state.ebb0 =
1737                 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1738         crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1739         crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1740         crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1741
1742         if (clk_div.m2_frac_en)
1743                 crtc_state->dpll_hw_state.pll3 =
1744                         PORT_PLL_M2_FRAC_ENABLE;
1745
1746         crtc_state->dpll_hw_state.pll6 =
1747                 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1748         crtc_state->dpll_hw_state.pll6 |=
1749                 PORT_PLL_GAIN_CTL(gain_ctl);
1750
1751         crtc_state->dpll_hw_state.pll8 = targ_cnt;
1752
1753         crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1754
1755         crtc_state->dpll_hw_state.pll10 =
1756                 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1757                 | PORT_PLL_DCO_AMP_OVR_EN_H;
1758
1759         crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1760
1761         crtc_state->dpll_hw_state.pcsdw12 =
1762                 LANESTAGGER_STRAP_OVRD | lanestagger;
1763
1764         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1765         if (pll == NULL) {
1766                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1767                         pipe_name(intel_crtc->pipe));
1768                 return false;
1769         }
1770
1771         /* shared DPLL id 0 is DPLL A */
1772         crtc_state->ddi_pll_sel = pll->id;
1773
1774         return true;
1775 }
1776
1777 /*
1778  * Tries to find a *shared* PLL for the CRTC and store it in
1779  * intel_crtc->ddi_pll_sel.
1780  *
1781  * For private DPLLs, compute_config() should do the selection for us. This
1782  * function should be folded into compute_config() eventually.
1783  */
1784 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1785                           struct intel_crtc_state *crtc_state)
1786 {
1787         struct drm_device *dev = intel_crtc->base.dev;
1788         struct intel_encoder *intel_encoder =
1789                 intel_ddi_get_crtc_new_encoder(crtc_state);
1790
1791         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1792                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1793                                           intel_encoder);
1794         else if (IS_BROXTON(dev))
1795                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1796                                           intel_encoder);
1797         else
1798                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1799                                           intel_encoder);
1800 }
1801
1802 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1803 {
1804         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1807         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1808         int type = intel_encoder->type;
1809         uint32_t temp;
1810
1811         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1812                 temp = TRANS_MSA_SYNC_CLK;
1813                 switch (intel_crtc->config->pipe_bpp) {
1814                 case 18:
1815                         temp |= TRANS_MSA_6_BPC;
1816                         break;
1817                 case 24:
1818                         temp |= TRANS_MSA_8_BPC;
1819                         break;
1820                 case 30:
1821                         temp |= TRANS_MSA_10_BPC;
1822                         break;
1823                 case 36:
1824                         temp |= TRANS_MSA_12_BPC;
1825                         break;
1826                 default:
1827                         BUG();
1828                 }
1829                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1830         }
1831 }
1832
1833 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1834 {
1835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1836         struct drm_device *dev = crtc->dev;
1837         struct drm_i915_private *dev_priv = dev->dev_private;
1838         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1839         uint32_t temp;
1840         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1841         if (state == true)
1842                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1843         else
1844                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1845         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1846 }
1847
1848 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1849 {
1850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1851         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1852         struct drm_encoder *encoder = &intel_encoder->base;
1853         struct drm_device *dev = crtc->dev;
1854         struct drm_i915_private *dev_priv = dev->dev_private;
1855         enum pipe pipe = intel_crtc->pipe;
1856         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1857         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1858         int type = intel_encoder->type;
1859         uint32_t temp;
1860
1861         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1862         temp = TRANS_DDI_FUNC_ENABLE;
1863         temp |= TRANS_DDI_SELECT_PORT(port);
1864
1865         switch (intel_crtc->config->pipe_bpp) {
1866         case 18:
1867                 temp |= TRANS_DDI_BPC_6;
1868                 break;
1869         case 24:
1870                 temp |= TRANS_DDI_BPC_8;
1871                 break;
1872         case 30:
1873                 temp |= TRANS_DDI_BPC_10;
1874                 break;
1875         case 36:
1876                 temp |= TRANS_DDI_BPC_12;
1877                 break;
1878         default:
1879                 BUG();
1880         }
1881
1882         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1883                 temp |= TRANS_DDI_PVSYNC;
1884         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1885                 temp |= TRANS_DDI_PHSYNC;
1886
1887         if (cpu_transcoder == TRANSCODER_EDP) {
1888                 switch (pipe) {
1889                 case PIPE_A:
1890                         /* On Haswell, can only use the always-on power well for
1891                          * eDP when not using the panel fitter, and when not
1892                          * using motion blur mitigation (which we don't
1893                          * support). */
1894                         if (IS_HASWELL(dev) &&
1895                             (intel_crtc->config->pch_pfit.enabled ||
1896                              intel_crtc->config->pch_pfit.force_thru))
1897                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1898                         else
1899                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1900                         break;
1901                 case PIPE_B:
1902                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1903                         break;
1904                 case PIPE_C:
1905                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1906                         break;
1907                 default:
1908                         BUG();
1909                         break;
1910                 }
1911         }
1912
1913         if (type == INTEL_OUTPUT_HDMI) {
1914                 if (intel_crtc->config->has_hdmi_sink)
1915                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1916                 else
1917                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1918
1919         } else if (type == INTEL_OUTPUT_ANALOG) {
1920                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1921                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1922
1923         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1924                    type == INTEL_OUTPUT_EDP) {
1925                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1926
1927                 if (intel_dp->is_mst) {
1928                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1929                 } else
1930                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1931
1932                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1933         } else if (type == INTEL_OUTPUT_DP_MST) {
1934                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1935
1936                 if (intel_dp->is_mst) {
1937                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1938                 } else
1939                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1940
1941                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1942         } else {
1943                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1944                      intel_encoder->type, pipe_name(pipe));
1945         }
1946
1947         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1948 }
1949
1950 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1951                                        enum transcoder cpu_transcoder)
1952 {
1953         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1954         uint32_t val = I915_READ(reg);
1955
1956         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1957         val |= TRANS_DDI_PORT_NONE;
1958         I915_WRITE(reg, val);
1959 }
1960
1961 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1962 {
1963         struct drm_device *dev = intel_connector->base.dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         struct intel_encoder *intel_encoder = intel_connector->encoder;
1966         int type = intel_connector->base.connector_type;
1967         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1968         enum pipe pipe = 0;
1969         enum transcoder cpu_transcoder;
1970         enum intel_display_power_domain power_domain;
1971         uint32_t tmp;
1972
1973         power_domain = intel_display_port_power_domain(intel_encoder);
1974         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1975                 return false;
1976
1977         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1978                 return false;
1979
1980         if (port == PORT_A)
1981                 cpu_transcoder = TRANSCODER_EDP;
1982         else
1983                 cpu_transcoder = (enum transcoder) pipe;
1984
1985         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1986
1987         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1988         case TRANS_DDI_MODE_SELECT_HDMI:
1989         case TRANS_DDI_MODE_SELECT_DVI:
1990                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1991
1992         case TRANS_DDI_MODE_SELECT_DP_SST:
1993                 if (type == DRM_MODE_CONNECTOR_eDP)
1994                         return true;
1995                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1996         case TRANS_DDI_MODE_SELECT_DP_MST:
1997                 /* if the transcoder is in MST state then
1998                  * connector isn't connected */
1999                 return false;
2000
2001         case TRANS_DDI_MODE_SELECT_FDI:
2002                 return (type == DRM_MODE_CONNECTOR_VGA);
2003
2004         default:
2005                 return false;
2006         }
2007 }
2008
2009 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2010                             enum pipe *pipe)
2011 {
2012         struct drm_device *dev = encoder->base.dev;
2013         struct drm_i915_private *dev_priv = dev->dev_private;
2014         enum port port = intel_ddi_get_encoder_port(encoder);
2015         enum intel_display_power_domain power_domain;
2016         u32 tmp;
2017         int i;
2018
2019         power_domain = intel_display_port_power_domain(encoder);
2020         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2021                 return false;
2022
2023         tmp = I915_READ(DDI_BUF_CTL(port));
2024
2025         if (!(tmp & DDI_BUF_CTL_ENABLE))
2026                 return false;
2027
2028         if (port == PORT_A) {
2029                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2030
2031                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2032                 case TRANS_DDI_EDP_INPUT_A_ON:
2033                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2034                         *pipe = PIPE_A;
2035                         break;
2036                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2037                         *pipe = PIPE_B;
2038                         break;
2039                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2040                         *pipe = PIPE_C;
2041                         break;
2042                 }
2043
2044                 return true;
2045         } else {
2046                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2047                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2048
2049                         if ((tmp & TRANS_DDI_PORT_MASK)
2050                             == TRANS_DDI_SELECT_PORT(port)) {
2051                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2052                                         return false;
2053
2054                                 *pipe = i;
2055                                 return true;
2056                         }
2057                 }
2058         }
2059
2060         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2061
2062         return false;
2063 }
2064
2065 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2066 {
2067         struct drm_crtc *crtc = &intel_crtc->base;
2068         struct drm_device *dev = crtc->dev;
2069         struct drm_i915_private *dev_priv = dev->dev_private;
2070         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2071         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2072         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2073
2074         if (cpu_transcoder != TRANSCODER_EDP)
2075                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2076                            TRANS_CLK_SEL_PORT(port));
2077 }
2078
2079 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2080 {
2081         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2082         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2083
2084         if (cpu_transcoder != TRANSCODER_EDP)
2085                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2086                            TRANS_CLK_SEL_DISABLED);
2087 }
2088
2089 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2090                                enum port port, int type)
2091 {
2092         struct drm_i915_private *dev_priv = dev->dev_private;
2093         const struct ddi_buf_trans *ddi_translations;
2094         uint8_t iboost;
2095         uint8_t dp_iboost, hdmi_iboost;
2096         int n_entries;
2097         u32 reg;
2098
2099         /* VBT may override standard boost values */
2100         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2101         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2102
2103         if (type == INTEL_OUTPUT_DISPLAYPORT) {
2104                 if (dp_iboost) {
2105                         iboost = dp_iboost;
2106                 } else {
2107                         ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2108                         iboost = ddi_translations[level].i_boost;
2109                 }
2110         } else if (type == INTEL_OUTPUT_EDP) {
2111                 if (dp_iboost) {
2112                         iboost = dp_iboost;
2113                 } else {
2114                         ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2115                         iboost = ddi_translations[level].i_boost;
2116                 }
2117         } else if (type == INTEL_OUTPUT_HDMI) {
2118                 if (hdmi_iboost) {
2119                         iboost = hdmi_iboost;
2120                 } else {
2121                         ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2122                         iboost = ddi_translations[level].i_boost;
2123                 }
2124         } else {
2125                 return;
2126         }
2127
2128         /* Make sure that the requested I_boost is valid */
2129         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2130                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2131                 return;
2132         }
2133
2134         reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2135         reg &= ~BALANCE_LEG_MASK(port);
2136         reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2137
2138         if (iboost)
2139                 reg |= iboost << BALANCE_LEG_SHIFT(port);
2140         else
2141                 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2142
2143         I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2144 }
2145
2146 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2147                                     enum port port, int type)
2148 {
2149         struct drm_i915_private *dev_priv = dev->dev_private;
2150         const struct bxt_ddi_buf_trans *ddi_translations;
2151         u32 n_entries, i;
2152         uint32_t val;
2153
2154         if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2155                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2156                 ddi_translations = bxt_ddi_translations_edp;
2157         } else if (type == INTEL_OUTPUT_DISPLAYPORT
2158                         || type == INTEL_OUTPUT_EDP) {
2159                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2160                 ddi_translations = bxt_ddi_translations_dp;
2161         } else if (type == INTEL_OUTPUT_HDMI) {
2162                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2163                 ddi_translations = bxt_ddi_translations_hdmi;
2164         } else {
2165                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2166                                 type);
2167                 return;
2168         }
2169
2170         /* Check if default value has to be used */
2171         if (level >= n_entries ||
2172             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2173                 for (i = 0; i < n_entries; i++) {
2174                         if (ddi_translations[i].default_index) {
2175                                 level = i;
2176                                 break;
2177                         }
2178                 }
2179         }
2180
2181         /*
2182          * While we write to the group register to program all lanes at once we
2183          * can read only lane registers and we pick lanes 0/1 for that.
2184          */
2185         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2186         val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2187         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2188
2189         val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2190         val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2191         val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2192                ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2193         I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2194
2195         val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2196         val &= ~SCALE_DCOMP_METHOD;
2197         if (ddi_translations[level].enable)
2198                 val |= SCALE_DCOMP_METHOD;
2199
2200         if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2201                 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2202
2203         I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2204
2205         val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2206         val &= ~DE_EMPHASIS;
2207         val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2208         I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2209
2210         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2211         val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2212         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2213 }
2214
2215 static uint32_t translate_signal_level(int signal_levels)
2216 {
2217         uint32_t level;
2218
2219         switch (signal_levels) {
2220         default:
2221                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2222                               signal_levels);
2223         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2224                 level = 0;
2225                 break;
2226         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2227                 level = 1;
2228                 break;
2229         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2230                 level = 2;
2231                 break;
2232         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2233                 level = 3;
2234                 break;
2235
2236         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2237                 level = 4;
2238                 break;
2239         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2240                 level = 5;
2241                 break;
2242         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2243                 level = 6;
2244                 break;
2245
2246         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2247                 level = 7;
2248                 break;
2249         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2250                 level = 8;
2251                 break;
2252
2253         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2254                 level = 9;
2255                 break;
2256         }
2257
2258         return level;
2259 }
2260
2261 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2262 {
2263         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2264         struct drm_device *dev = dport->base.base.dev;
2265         struct intel_encoder *encoder = &dport->base;
2266         uint8_t train_set = intel_dp->train_set[0];
2267         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2268                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2269         enum port port = dport->port;
2270         uint32_t level;
2271
2272         level = translate_signal_level(signal_levels);
2273
2274         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2275                 skl_ddi_set_iboost(dev, level, port, encoder->type);
2276         else if (IS_BROXTON(dev))
2277                 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2278
2279         return DDI_BUF_TRANS_SELECT(level);
2280 }
2281
2282 void intel_ddi_clk_select(struct intel_encoder *encoder,
2283                           const struct intel_crtc_state *pipe_config)
2284 {
2285         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2286         enum port port = intel_ddi_get_encoder_port(encoder);
2287
2288         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2289                 uint32_t dpll = pipe_config->ddi_pll_sel;
2290                 uint32_t val;
2291
2292                 /*
2293                  * DPLL0 is used for eDP and is the only "private" DPLL (as
2294                  * opposed to shared) on SKL
2295                  */
2296                 if (encoder->type == INTEL_OUTPUT_EDP) {
2297                         WARN_ON(dpll != SKL_DPLL0);
2298
2299                         val = I915_READ(DPLL_CTRL1);
2300
2301                         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2302                                  DPLL_CTRL1_SSC(dpll) |
2303                                  DPLL_CTRL1_LINK_RATE_MASK(dpll));
2304                         val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
2305
2306                         I915_WRITE(DPLL_CTRL1, val);
2307                         POSTING_READ(DPLL_CTRL1);
2308                 }
2309
2310                 /* DDI -> PLL mapping  */
2311                 val = I915_READ(DPLL_CTRL2);
2312
2313                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2314                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2315                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2316                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2317
2318                 I915_WRITE(DPLL_CTRL2, val);
2319
2320         } else if (INTEL_INFO(dev_priv)->gen < 9) {
2321                 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2322                 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
2323         }
2324 }
2325
2326 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2327 {
2328         struct drm_encoder *encoder = &intel_encoder->base;
2329         struct drm_device *dev = encoder->dev;
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2332         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2333         int type = intel_encoder->type;
2334         int hdmi_level;
2335
2336         if (type == INTEL_OUTPUT_EDP) {
2337                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2338                 intel_edp_panel_on(intel_dp);
2339         }
2340
2341         intel_ddi_clk_select(intel_encoder, crtc->config);
2342
2343         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2344                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2345
2346                 intel_dp_set_link_params(intel_dp, crtc->config);
2347
2348                 intel_ddi_init_dp_buf_reg(intel_encoder);
2349
2350                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2351                 intel_dp_start_link_train(intel_dp);
2352                 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
2353                         intel_dp_stop_link_train(intel_dp);
2354         } else if (type == INTEL_OUTPUT_HDMI) {
2355                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2356
2357                 if (IS_BROXTON(dev)) {
2358                         hdmi_level = dev_priv->vbt.
2359                                 ddi_port_info[port].hdmi_level_shift;
2360                         bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2361                                         INTEL_OUTPUT_HDMI);
2362                 }
2363                 intel_hdmi->set_infoframes(encoder,
2364                                            crtc->config->has_hdmi_sink,
2365                                            &crtc->config->base.adjusted_mode);
2366         }
2367 }
2368
2369 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
2370 {
2371         struct drm_encoder *encoder = &intel_encoder->base;
2372         struct drm_device *dev = encoder->dev;
2373         struct drm_i915_private *dev_priv = dev->dev_private;
2374         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2375         int type = intel_encoder->type;
2376         uint32_t val;
2377         bool wait = false;
2378
2379         val = I915_READ(DDI_BUF_CTL(port));
2380         if (val & DDI_BUF_CTL_ENABLE) {
2381                 val &= ~DDI_BUF_CTL_ENABLE;
2382                 I915_WRITE(DDI_BUF_CTL(port), val);
2383                 wait = true;
2384         }
2385
2386         val = I915_READ(DP_TP_CTL(port));
2387         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2388         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2389         I915_WRITE(DP_TP_CTL(port), val);
2390
2391         if (wait)
2392                 intel_wait_ddi_buf_idle(dev_priv, port);
2393
2394         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2395                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2396                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2397                 intel_edp_panel_vdd_on(intel_dp);
2398                 intel_edp_panel_off(intel_dp);
2399         }
2400
2401         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2402                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2403                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
2404         else if (INTEL_INFO(dev)->gen < 9)
2405                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2406 }
2407
2408 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
2409 {
2410         struct drm_encoder *encoder = &intel_encoder->base;
2411         struct drm_crtc *crtc = encoder->crtc;
2412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2413         struct drm_device *dev = encoder->dev;
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2416         int type = intel_encoder->type;
2417
2418         if (type == INTEL_OUTPUT_HDMI) {
2419                 struct intel_digital_port *intel_dig_port =
2420                         enc_to_dig_port(encoder);
2421
2422                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2423                  * are ignored so nothing special needs to be done besides
2424                  * enabling the port.
2425                  */
2426                 I915_WRITE(DDI_BUF_CTL(port),
2427                            intel_dig_port->saved_port_bits |
2428                            DDI_BUF_CTL_ENABLE);
2429         } else if (type == INTEL_OUTPUT_EDP) {
2430                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2431
2432                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2433                         intel_dp_stop_link_train(intel_dp);
2434
2435                 intel_edp_backlight_on(intel_dp);
2436                 intel_psr_enable(intel_dp);
2437                 intel_edp_drrs_enable(intel_dp);
2438         }
2439
2440         if (intel_crtc->config->has_audio) {
2441                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2442                 intel_audio_codec_enable(intel_encoder);
2443         }
2444 }
2445
2446 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2447 {
2448         struct drm_encoder *encoder = &intel_encoder->base;
2449         struct drm_crtc *crtc = encoder->crtc;
2450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451         int type = intel_encoder->type;
2452         struct drm_device *dev = encoder->dev;
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454
2455         if (intel_crtc->config->has_audio) {
2456                 intel_audio_codec_disable(intel_encoder);
2457                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2458         }
2459
2460         if (type == INTEL_OUTPUT_EDP) {
2461                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2462
2463                 intel_edp_drrs_disable(intel_dp);
2464                 intel_psr_disable(intel_dp);
2465                 intel_edp_backlight_off(intel_dp);
2466         }
2467 }
2468
2469 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
2470                                struct intel_shared_dpll *pll)
2471 {
2472         I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2473         POSTING_READ(WRPLL_CTL(pll->id));
2474         udelay(20);
2475 }
2476
2477 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
2478                                 struct intel_shared_dpll *pll)
2479 {
2480         I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2481         POSTING_READ(SPLL_CTL);
2482         udelay(20);
2483 }
2484
2485 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2486                                   struct intel_shared_dpll *pll)
2487 {
2488         uint32_t val;
2489
2490         val = I915_READ(WRPLL_CTL(pll->id));
2491         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2492         POSTING_READ(WRPLL_CTL(pll->id));
2493 }
2494
2495 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2496                                  struct intel_shared_dpll *pll)
2497 {
2498         uint32_t val;
2499
2500         val = I915_READ(SPLL_CTL);
2501         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2502         POSTING_READ(SPLL_CTL);
2503 }
2504
2505 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2506                                        struct intel_shared_dpll *pll,
2507                                        struct intel_dpll_hw_state *hw_state)
2508 {
2509         uint32_t val;
2510
2511         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2512                 return false;
2513
2514         val = I915_READ(WRPLL_CTL(pll->id));
2515         hw_state->wrpll = val;
2516
2517         return val & WRPLL_PLL_ENABLE;
2518 }
2519
2520 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2521                                       struct intel_shared_dpll *pll,
2522                                       struct intel_dpll_hw_state *hw_state)
2523 {
2524         uint32_t val;
2525
2526         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2527                 return false;
2528
2529         val = I915_READ(SPLL_CTL);
2530         hw_state->spll = val;
2531
2532         return val & SPLL_PLL_ENABLE;
2533 }
2534
2535
2536 static const char * const hsw_ddi_pll_names[] = {
2537         "WRPLL 1",
2538         "WRPLL 2",
2539         "SPLL"
2540 };
2541
2542 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2543 {
2544         int i;
2545
2546         dev_priv->num_shared_dpll = 3;
2547
2548         for (i = 0; i < 2; i++) {
2549                 dev_priv->shared_dplls[i].id = i;
2550                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2551                 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2552                 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
2553                 dev_priv->shared_dplls[i].get_hw_state =
2554                         hsw_ddi_wrpll_get_hw_state;
2555         }
2556
2557         /* SPLL is special, but needs to be initialized anyway.. */
2558         dev_priv->shared_dplls[i].id = i;
2559         dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2560         dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2561         dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2562         dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2563
2564 }
2565
2566 static const char * const skl_ddi_pll_names[] = {
2567         "DPLL 1",
2568         "DPLL 2",
2569         "DPLL 3",
2570 };
2571
2572 struct skl_dpll_regs {
2573         i915_reg_t ctl, cfgcr1, cfgcr2;
2574 };
2575
2576 /* this array is indexed by the *shared* pll id */
2577 static const struct skl_dpll_regs skl_dpll_regs[3] = {
2578         {
2579                 /* DPLL 1 */
2580                 .ctl = LCPLL2_CTL,
2581                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2582                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
2583         },
2584         {
2585                 /* DPLL 2 */
2586                 .ctl = WRPLL_CTL(0),
2587                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2588                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
2589         },
2590         {
2591                 /* DPLL 3 */
2592                 .ctl = WRPLL_CTL(1),
2593                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2594                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
2595         },
2596 };
2597
2598 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2599                                struct intel_shared_dpll *pll)
2600 {
2601         uint32_t val;
2602         unsigned int dpll;
2603         const struct skl_dpll_regs *regs = skl_dpll_regs;
2604
2605         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2606         dpll = pll->id + 1;
2607
2608         val = I915_READ(DPLL_CTRL1);
2609
2610         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2611                  DPLL_CTRL1_LINK_RATE_MASK(dpll));
2612         val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2613
2614         I915_WRITE(DPLL_CTRL1, val);
2615         POSTING_READ(DPLL_CTRL1);
2616
2617         I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2618         I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2619         POSTING_READ(regs[pll->id].cfgcr1);
2620         POSTING_READ(regs[pll->id].cfgcr2);
2621
2622         /* the enable bit is always bit 31 */
2623         I915_WRITE(regs[pll->id].ctl,
2624                    I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2625
2626         if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2627                 DRM_ERROR("DPLL %d not locked\n", dpll);
2628 }
2629
2630 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2631                                 struct intel_shared_dpll *pll)
2632 {
2633         const struct skl_dpll_regs *regs = skl_dpll_regs;
2634
2635         /* the enable bit is always bit 31 */
2636         I915_WRITE(regs[pll->id].ctl,
2637                    I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2638         POSTING_READ(regs[pll->id].ctl);
2639 }
2640
2641 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2642                                      struct intel_shared_dpll *pll,
2643                                      struct intel_dpll_hw_state *hw_state)
2644 {
2645         uint32_t val;
2646         unsigned int dpll;
2647         const struct skl_dpll_regs *regs = skl_dpll_regs;
2648
2649         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2650                 return false;
2651
2652         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2653         dpll = pll->id + 1;
2654
2655         val = I915_READ(regs[pll->id].ctl);
2656         if (!(val & LCPLL_PLL_ENABLE))
2657                 return false;
2658
2659         val = I915_READ(DPLL_CTRL1);
2660         hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2661
2662         /* avoid reading back stale values if HDMI mode is not enabled */
2663         if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2664                 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2665                 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2666         }
2667
2668         return true;
2669 }
2670
2671 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2672 {
2673         int i;
2674
2675         dev_priv->num_shared_dpll = 3;
2676
2677         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2678                 dev_priv->shared_dplls[i].id = i;
2679                 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2680                 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2681                 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2682                 dev_priv->shared_dplls[i].get_hw_state =
2683                         skl_ddi_pll_get_hw_state;
2684         }
2685 }
2686
2687 static void broxton_phy_init(struct drm_i915_private *dev_priv,
2688                              enum dpio_phy phy)
2689 {
2690         enum port port;
2691         uint32_t val;
2692
2693         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2694         val |= GT_DISPLAY_POWER_ON(phy);
2695         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2696
2697         /* Considering 10ms timeout until BSpec is updated */
2698         if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2699                 DRM_ERROR("timeout during PHY%d power on\n", phy);
2700
2701         for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2702              port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2703                 int lane;
2704
2705                 for (lane = 0; lane < 4; lane++) {
2706                         val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2707                         /*
2708                          * Note that on CHV this flag is called UPAR, but has
2709                          * the same function.
2710                          */
2711                         val &= ~LATENCY_OPTIM;
2712                         if (lane != 1)
2713                                 val |= LATENCY_OPTIM;
2714
2715                         I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2716                 }
2717         }
2718
2719         /* Program PLL Rcomp code offset */
2720         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2721         val &= ~IREF0RC_OFFSET_MASK;
2722         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2723         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2724
2725         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2726         val &= ~IREF1RC_OFFSET_MASK;
2727         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2728         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2729
2730         /* Program power gating */
2731         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2732         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2733                 SUS_CLK_CONFIG;
2734         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2735
2736         if (phy == DPIO_PHY0) {
2737                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2738                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2739                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2740         }
2741
2742         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2743         val &= ~OCL2_LDOFUSE_PWR_DIS;
2744         /*
2745          * On PHY1 disable power on the second channel, since no port is
2746          * connected there. On PHY0 both channels have a port, so leave it
2747          * enabled.
2748          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2749          * power down the second channel on PHY0 as well.
2750          */
2751         if (phy == DPIO_PHY1)
2752                 val |= OCL2_LDOFUSE_PWR_DIS;
2753         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2754
2755         if (phy == DPIO_PHY0) {
2756                 uint32_t grc_code;
2757                 /*
2758                  * PHY0 isn't connected to an RCOMP resistor so copy over
2759                  * the corresponding calibrated value from PHY1, and disable
2760                  * the automatic calibration on PHY0.
2761                  */
2762                 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2763                              10))
2764                         DRM_ERROR("timeout waiting for PHY1 GRC\n");
2765
2766                 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2767                 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2768                 grc_code = val << GRC_CODE_FAST_SHIFT |
2769                            val << GRC_CODE_SLOW_SHIFT |
2770                            val;
2771                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2772
2773                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2774                 val |= GRC_DIS | GRC_RDY_OVRD;
2775                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2776         }
2777
2778         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2779         val |= COMMON_RESET_DIS;
2780         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2781 }
2782
2783 void broxton_ddi_phy_init(struct drm_device *dev)
2784 {
2785         /* Enable PHY1 first since it provides Rcomp for PHY0 */
2786         broxton_phy_init(dev->dev_private, DPIO_PHY1);
2787         broxton_phy_init(dev->dev_private, DPIO_PHY0);
2788 }
2789
2790 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2791                                enum dpio_phy phy)
2792 {
2793         uint32_t val;
2794
2795         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2796         val &= ~COMMON_RESET_DIS;
2797         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2798 }
2799
2800 void broxton_ddi_phy_uninit(struct drm_device *dev)
2801 {
2802         struct drm_i915_private *dev_priv = dev->dev_private;
2803
2804         broxton_phy_uninit(dev_priv, DPIO_PHY1);
2805         broxton_phy_uninit(dev_priv, DPIO_PHY0);
2806
2807         /* FIXME: do this in broxton_phy_uninit per phy */
2808         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2809 }
2810
2811 static const char * const bxt_ddi_pll_names[] = {
2812         "PORT PLL A",
2813         "PORT PLL B",
2814         "PORT PLL C",
2815 };
2816
2817 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2818                                 struct intel_shared_dpll *pll)
2819 {
2820         uint32_t temp;
2821         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2822
2823         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2824         temp &= ~PORT_PLL_REF_SEL;
2825         /* Non-SSC reference */
2826         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2827
2828         /* Disable 10 bit clock */
2829         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2830         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2831         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2832
2833         /* Write P1 & P2 */
2834         temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2835         temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2836         temp |= pll->config.hw_state.ebb0;
2837         I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2838
2839         /* Write M2 integer */
2840         temp = I915_READ(BXT_PORT_PLL(port, 0));
2841         temp &= ~PORT_PLL_M2_MASK;
2842         temp |= pll->config.hw_state.pll0;
2843         I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2844
2845         /* Write N */
2846         temp = I915_READ(BXT_PORT_PLL(port, 1));
2847         temp &= ~PORT_PLL_N_MASK;
2848         temp |= pll->config.hw_state.pll1;
2849         I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2850
2851         /* Write M2 fraction */
2852         temp = I915_READ(BXT_PORT_PLL(port, 2));
2853         temp &= ~PORT_PLL_M2_FRAC_MASK;
2854         temp |= pll->config.hw_state.pll2;
2855         I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2856
2857         /* Write M2 fraction enable */
2858         temp = I915_READ(BXT_PORT_PLL(port, 3));
2859         temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2860         temp |= pll->config.hw_state.pll3;
2861         I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2862
2863         /* Write coeff */
2864         temp = I915_READ(BXT_PORT_PLL(port, 6));
2865         temp &= ~PORT_PLL_PROP_COEFF_MASK;
2866         temp &= ~PORT_PLL_INT_COEFF_MASK;
2867         temp &= ~PORT_PLL_GAIN_CTL_MASK;
2868         temp |= pll->config.hw_state.pll6;
2869         I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2870
2871         /* Write calibration val */
2872         temp = I915_READ(BXT_PORT_PLL(port, 8));
2873         temp &= ~PORT_PLL_TARGET_CNT_MASK;
2874         temp |= pll->config.hw_state.pll8;
2875         I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2876
2877         temp = I915_READ(BXT_PORT_PLL(port, 9));
2878         temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2879         temp |= pll->config.hw_state.pll9;
2880         I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2881
2882         temp = I915_READ(BXT_PORT_PLL(port, 10));
2883         temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2884         temp &= ~PORT_PLL_DCO_AMP_MASK;
2885         temp |= pll->config.hw_state.pll10;
2886         I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2887
2888         /* Recalibrate with new settings */
2889         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2890         temp |= PORT_PLL_RECALIBRATE;
2891         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2892         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2893         temp |= pll->config.hw_state.ebb4;
2894         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2895
2896         /* Enable PLL */
2897         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2898         temp |= PORT_PLL_ENABLE;
2899         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2900         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2901
2902         if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2903                         PORT_PLL_LOCK), 200))
2904                 DRM_ERROR("PLL %d not locked\n", port);
2905
2906         /*
2907          * While we write to the group register to program all lanes at once we
2908          * can read only lane registers and we pick lanes 0/1 for that.
2909          */
2910         temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2911         temp &= ~LANE_STAGGER_MASK;
2912         temp &= ~LANESTAGGER_STRAP_OVRD;
2913         temp |= pll->config.hw_state.pcsdw12;
2914         I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2915 }
2916
2917 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2918                                         struct intel_shared_dpll *pll)
2919 {
2920         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2921         uint32_t temp;
2922
2923         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2924         temp &= ~PORT_PLL_ENABLE;
2925         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2926         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2927 }
2928
2929 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2930                                         struct intel_shared_dpll *pll,
2931                                         struct intel_dpll_hw_state *hw_state)
2932 {
2933         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2934         uint32_t val;
2935
2936         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2937                 return false;
2938
2939         val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2940         if (!(val & PORT_PLL_ENABLE))
2941                 return false;
2942
2943         hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2944         hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2945
2946         hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2947         hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2948
2949         hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2950         hw_state->pll0 &= PORT_PLL_M2_MASK;
2951
2952         hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2953         hw_state->pll1 &= PORT_PLL_N_MASK;
2954
2955         hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2956         hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2957
2958         hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2959         hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2960
2961         hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2962         hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2963                           PORT_PLL_INT_COEFF_MASK |
2964                           PORT_PLL_GAIN_CTL_MASK;
2965
2966         hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2967         hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2968
2969         hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2970         hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2971
2972         hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2973         hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2974                            PORT_PLL_DCO_AMP_MASK;
2975
2976         /*
2977          * While we write to the group register to program all lanes at once we
2978          * can read only lane registers. We configure all lanes the same way, so
2979          * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2980          */
2981         hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2982         if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
2983                 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2984                                  hw_state->pcsdw12,
2985                                  I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2986         hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2987
2988         return true;
2989 }
2990
2991 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2992 {
2993         int i;
2994
2995         dev_priv->num_shared_dpll = 3;
2996
2997         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2998                 dev_priv->shared_dplls[i].id = i;
2999                 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
3000                 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
3001                 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
3002                 dev_priv->shared_dplls[i].get_hw_state =
3003                         bxt_ddi_pll_get_hw_state;
3004         }
3005 }
3006
3007 void intel_ddi_pll_init(struct drm_device *dev)
3008 {
3009         struct drm_i915_private *dev_priv = dev->dev_private;
3010         uint32_t val = I915_READ(LCPLL_CTL);
3011
3012         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
3013                 skl_shared_dplls_init(dev_priv);
3014         else if (IS_BROXTON(dev))
3015                 bxt_shared_dplls_init(dev_priv);
3016         else
3017                 hsw_shared_dplls_init(dev_priv);
3018
3019         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
3020                 int cdclk_freq;
3021
3022                 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
3023                 dev_priv->skl_boot_cdclk = cdclk_freq;
3024                 if (skl_sanitize_cdclk(dev_priv))
3025                         DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
3026                 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
3027                         DRM_ERROR("LCPLL1 is disabled\n");
3028         } else if (IS_BROXTON(dev)) {
3029                 broxton_init_cdclk(dev);
3030                 broxton_ddi_phy_init(dev);
3031         } else {
3032                 /*
3033                  * The LCPLL register should be turned on by the BIOS. For now
3034                  * let's just check its state and print errors in case
3035                  * something is wrong.  Don't even try to turn it on.
3036                  */
3037
3038                 if (val & LCPLL_CD_SOURCE_FCLK)
3039                         DRM_ERROR("CDCLK source is not LCPLL\n");
3040
3041                 if (val & LCPLL_PLL_DISABLE)
3042                         DRM_ERROR("LCPLL is disabled\n");
3043         }
3044 }
3045
3046 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3047 {
3048         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3049         struct drm_i915_private *dev_priv =
3050                 to_i915(intel_dig_port->base.base.dev);
3051         enum port port = intel_dig_port->port;
3052         uint32_t val;
3053         bool wait = false;
3054
3055         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3056                 val = I915_READ(DDI_BUF_CTL(port));
3057                 if (val & DDI_BUF_CTL_ENABLE) {
3058                         val &= ~DDI_BUF_CTL_ENABLE;
3059                         I915_WRITE(DDI_BUF_CTL(port), val);
3060                         wait = true;
3061                 }
3062
3063                 val = I915_READ(DP_TP_CTL(port));
3064                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3065                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3066                 I915_WRITE(DP_TP_CTL(port), val);
3067                 POSTING_READ(DP_TP_CTL(port));
3068
3069                 if (wait)
3070                         intel_wait_ddi_buf_idle(dev_priv, port);
3071         }
3072
3073         val = DP_TP_CTL_ENABLE |
3074               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3075         if (intel_dp->is_mst)
3076                 val |= DP_TP_CTL_MODE_MST;
3077         else {
3078                 val |= DP_TP_CTL_MODE_SST;
3079                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3080                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3081         }
3082         I915_WRITE(DP_TP_CTL(port), val);
3083         POSTING_READ(DP_TP_CTL(port));
3084
3085         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3086         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3087         POSTING_READ(DDI_BUF_CTL(port));
3088
3089         udelay(600);
3090 }
3091
3092 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3093 {
3094         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3095         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3096         uint32_t val;
3097
3098         intel_ddi_post_disable(intel_encoder);
3099
3100         val = I915_READ(FDI_RX_CTL(PIPE_A));
3101         val &= ~FDI_RX_ENABLE;
3102         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3103
3104         val = I915_READ(FDI_RX_MISC(PIPE_A));
3105         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3106         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3107         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3108
3109         val = I915_READ(FDI_RX_CTL(PIPE_A));
3110         val &= ~FDI_PCDCLK;
3111         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3112
3113         val = I915_READ(FDI_RX_CTL(PIPE_A));
3114         val &= ~FDI_RX_PLL_ENABLE;
3115         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3116 }
3117
3118 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3119                                  struct intel_crtc *intel_crtc)
3120 {
3121         u32 temp;
3122
3123         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3124                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3125                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3126                         return true;
3127         }
3128         return false;
3129 }
3130
3131 void intel_ddi_get_config(struct intel_encoder *encoder,
3132                           struct intel_crtc_state *pipe_config)
3133 {
3134         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3135         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
3136         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3137         struct intel_hdmi *intel_hdmi;
3138         u32 temp, flags = 0;
3139
3140         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3141         if (temp & TRANS_DDI_PHSYNC)
3142                 flags |= DRM_MODE_FLAG_PHSYNC;
3143         else
3144                 flags |= DRM_MODE_FLAG_NHSYNC;
3145         if (temp & TRANS_DDI_PVSYNC)
3146                 flags |= DRM_MODE_FLAG_PVSYNC;
3147         else
3148                 flags |= DRM_MODE_FLAG_NVSYNC;
3149
3150         pipe_config->base.adjusted_mode.flags |= flags;
3151
3152         switch (temp & TRANS_DDI_BPC_MASK) {
3153         case TRANS_DDI_BPC_6:
3154                 pipe_config->pipe_bpp = 18;
3155                 break;
3156         case TRANS_DDI_BPC_8:
3157                 pipe_config->pipe_bpp = 24;
3158                 break;
3159         case TRANS_DDI_BPC_10:
3160                 pipe_config->pipe_bpp = 30;
3161                 break;
3162         case TRANS_DDI_BPC_12:
3163                 pipe_config->pipe_bpp = 36;
3164                 break;
3165         default:
3166                 break;
3167         }
3168
3169         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3170         case TRANS_DDI_MODE_SELECT_HDMI:
3171                 pipe_config->has_hdmi_sink = true;
3172                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3173
3174                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
3175                         pipe_config->has_infoframe = true;
3176                 break;
3177         case TRANS_DDI_MODE_SELECT_DVI:
3178         case TRANS_DDI_MODE_SELECT_FDI:
3179                 break;
3180         case TRANS_DDI_MODE_SELECT_DP_SST:
3181         case TRANS_DDI_MODE_SELECT_DP_MST:
3182                 pipe_config->has_dp_encoder = true;
3183                 pipe_config->lane_count =
3184                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3185                 intel_dp_get_m_n(intel_crtc, pipe_config);
3186                 break;
3187         default:
3188                 break;
3189         }
3190
3191         pipe_config->has_audio =
3192                 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
3193
3194         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3195             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3196                 /*
3197                  * This is a big fat ugly hack.
3198                  *
3199                  * Some machines in UEFI boot mode provide us a VBT that has 18
3200                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3201                  * unknown we fail to light up. Yet the same BIOS boots up with
3202                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3203                  * max, not what it tells us to use.
3204                  *
3205                  * Note: This will still be broken if the eDP panel is not lit
3206                  * up by the BIOS, and thus we can't get the mode at module
3207                  * load.
3208                  */
3209                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3210                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3211                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3212         }
3213
3214         intel_ddi_clock_get(encoder, pipe_config);
3215 }
3216
3217 static void intel_ddi_destroy(struct drm_encoder *encoder)
3218 {
3219         /* HDMI has nothing special to destroy, so we can go with this. */
3220         intel_dp_encoder_destroy(encoder);
3221 }
3222
3223 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3224                                      struct intel_crtc_state *pipe_config)
3225 {
3226         int type = encoder->type;
3227         int port = intel_ddi_get_encoder_port(encoder);
3228
3229         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3230
3231         if (port == PORT_A)
3232                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3233
3234         if (type == INTEL_OUTPUT_HDMI)
3235                 return intel_hdmi_compute_config(encoder, pipe_config);
3236         else
3237                 return intel_dp_compute_config(encoder, pipe_config);
3238 }
3239
3240 static const struct drm_encoder_funcs intel_ddi_funcs = {
3241         .destroy = intel_ddi_destroy,
3242 };
3243
3244 static struct intel_connector *
3245 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3246 {
3247         struct intel_connector *connector;
3248         enum port port = intel_dig_port->port;
3249
3250         connector = intel_connector_alloc();
3251         if (!connector)
3252                 return NULL;
3253
3254         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3255         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3256                 kfree(connector);
3257                 return NULL;
3258         }
3259
3260         return connector;
3261 }
3262
3263 static struct intel_connector *
3264 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3265 {
3266         struct intel_connector *connector;
3267         enum port port = intel_dig_port->port;
3268
3269         connector = intel_connector_alloc();
3270         if (!connector)
3271                 return NULL;
3272
3273         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3274         intel_hdmi_init_connector(intel_dig_port, connector);
3275
3276         return connector;
3277 }
3278
3279 void intel_ddi_init(struct drm_device *dev, enum port port)
3280 {
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         struct intel_digital_port *intel_dig_port;
3283         struct intel_encoder *intel_encoder;
3284         struct drm_encoder *encoder;
3285         bool init_hdmi, init_dp;
3286
3287         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3288                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3289         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3290         if (!init_dp && !init_hdmi) {
3291                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3292                               port_name(port));
3293                 return;
3294         }
3295
3296         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3297         if (!intel_dig_port)
3298                 return;
3299
3300         intel_encoder = &intel_dig_port->base;
3301         encoder = &intel_encoder->base;
3302
3303         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3304                          DRM_MODE_ENCODER_TMDS, NULL);
3305
3306         intel_encoder->compute_config = intel_ddi_compute_config;
3307         intel_encoder->enable = intel_enable_ddi;
3308         intel_encoder->pre_enable = intel_ddi_pre_enable;
3309         intel_encoder->disable = intel_disable_ddi;
3310         intel_encoder->post_disable = intel_ddi_post_disable;
3311         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3312         intel_encoder->get_config = intel_ddi_get_config;
3313
3314         intel_dig_port->port = port;
3315         dev_priv->dig_port_map[port] = intel_encoder;
3316         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3317                                           (DDI_BUF_PORT_REVERSAL |
3318                                            DDI_A_4_LANES);
3319
3320         /*
3321          * Bspec says that DDI_A_4_LANES is the only supported configuration
3322          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
3323          * wasn't lit up at boot.  Force this bit on in our internal
3324          * configuration so that we use the proper lane count for our
3325          * calculations.
3326          */
3327         if (IS_BROXTON(dev) && port == PORT_A) {
3328                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3329                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3330                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
3331                 }
3332         }
3333
3334         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
3335         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3336         intel_encoder->cloneable = 0;
3337
3338         if (init_dp) {
3339                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3340                         goto err;
3341
3342                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3343                 /*
3344                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3345                  * interrupts to check the external panel connection.
3346                  */
3347                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
3348                         dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3349                 else
3350                         dev_priv->hotplug.irq_port[port] = intel_dig_port;
3351         }
3352
3353         /* In theory we don't need the encoder->type check, but leave it just in
3354          * case we have some really bad VBTs... */
3355         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3356                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3357                         goto err;
3358         }
3359
3360         return;
3361
3362 err:
3363         drm_encoder_cleanup(encoder);
3364         kfree(intel_dig_port);
3365 }