drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  38  * them for both DP and FDI transports, allowing those ports to
  39  * automatically adapt to HDMI connections as well
  40  */
  41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  42         { 0x00FFFFFF, 0x0006000E, 0x0 },
  43         { 0x00D75FFF, 0x0005000A, 0x0 },
  44         { 0x00C30FFF, 0x00040006, 0x0 },
  45         { 0x80AAAFFF, 0x000B0000, 0x0 },
  46         { 0x00FFFFFF, 0x0005000A, 0x0 },
  47         { 0x00D75FFF, 0x000C0004, 0x0 },
  48         { 0x80C30FFF, 0x000B0000, 0x0 },
  49         { 0x00FFFFFF, 0x00040006, 0x0 },
  50         { 0x80D75FFF, 0x000B0000, 0x0 },
  51 };
  52
  53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  54         { 0x00FFFFFF, 0x0007000E, 0x0 },
  55         { 0x00D75FFF, 0x000F000A, 0x0 },
  56         { 0x00C30FFF, 0x00060006, 0x0 },
  57         { 0x00AAAFFF, 0x001E0000, 0x0 },
  58         { 0x00FFFFFF, 0x000F000A, 0x0 },
  59         { 0x00D75FFF, 0x00160004, 0x0 },
  60         { 0x00C30FFF, 0x001E0000, 0x0 },
  61         { 0x00FFFFFF, 0x00060006, 0x0 },
  62         { 0x00D75FFF, 0x001E0000, 0x0 },
  63 };
  64
  65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  66                                         /* Idx  NT mV d T mV d  db      */
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  68         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  69         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  70         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  71         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  72         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  73         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  74         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  75         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  76         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  77         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  78         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  79 };
  80
  81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  82         { 0x00FFFFFF, 0x00000012, 0x0 },
  83         { 0x00EBAFFF, 0x00020011, 0x0 },
  84         { 0x00C71FFF, 0x0006000F, 0x0 },
  85         { 0x00AAAFFF, 0x000E000A, 0x0 },
  86         { 0x00FFFFFF, 0x00020011, 0x0 },
  87         { 0x00DB6FFF, 0x0005000F, 0x0 },
  88         { 0x00BEEFFF, 0x000A000C, 0x0 },
  89         { 0x00FFFFFF, 0x0005000F, 0x0 },
  90         { 0x00DB6FFF, 0x000A000C, 0x0 },
  91 };
  92
  93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  94         { 0x00FFFFFF, 0x0007000E, 0x0 },
  95         { 0x00D75FFF, 0x000E000A, 0x0 },
  96         { 0x00BEFFFF, 0x00140006, 0x0 },
  97         { 0x80B2CFFF, 0x001B0002, 0x0 },
  98         { 0x00FFFFFF, 0x000E000A, 0x0 },
  99         { 0x00DB6FFF, 0x00160005, 0x0 },
 100         { 0x80C71FFF, 0x001A0002, 0x0 },
 101         { 0x00F7DFFF, 0x00180004, 0x0 },
 102         { 0x80D75FFF, 0x001B0002, 0x0 },
 103 };
 104
 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 106         { 0x00FFFFFF, 0x0001000E, 0x0 },
 107         { 0x00D75FFF, 0x0004000A, 0x0 },
 108         { 0x00C30FFF, 0x00070006, 0x0 },
 109         { 0x00AAAFFF, 0x000C0000, 0x0 },
 110         { 0x00FFFFFF, 0x0004000A, 0x0 },
 111         { 0x00D75FFF, 0x00090004, 0x0 },
 112         { 0x00C30FFF, 0x000C0000, 0x0 },
 113         { 0x00FFFFFF, 0x00070006, 0x0 },
 114         { 0x00D75FFF, 0x000C0000, 0x0 },
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 118                                         /* Idx  NT mV d T mV df db      */
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 120         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 121         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 122         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 124         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 125         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 126         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 127         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 128         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 129 };
 130
 131 /* Skylake H and S */
 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 133         { 0x00002016, 0x000000A0, 0x0 },
 134         { 0x00005012, 0x0000009B, 0x0 },
 135         { 0x00007011, 0x00000088, 0x0 },
 136         { 0x80009010, 0x000000C0, 0x1 },
 137         { 0x00002016, 0x0000009B, 0x0 },
 138         { 0x00005012, 0x00000088, 0x0 },
 139         { 0x80007011, 0x000000C0, 0x1 },
 140         { 0x00002016, 0x000000DF, 0x0 },
 141         { 0x80005012, 0x000000C0, 0x1 },
 142 };
 143
 144 /* Skylake U */
 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 146         { 0x0000201B, 0x000000A2, 0x0 },
 147         { 0x00005012, 0x00000088, 0x0 },
 148         { 0x80007011, 0x000000CD, 0x0 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x0000201B, 0x0000009D, 0x0 },
 151         { 0x80005012, 0x000000C0, 0x1 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x00000088, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake Y */
 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 159         { 0x00000018, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x0 },
 162         { 0x80009010, 0x000000C0, 0x3 },
 163         { 0x00000018, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x3 },
 165         { 0x80007011, 0x000000C0, 0x3 },
 166         { 0x00000018, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x3 },
 168 };
 169
 170 /*
 171  * Skylake H and S
 172  * eDP 1.4 low vswing translation parameters
 173  */
 174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 175         { 0x00000018, 0x000000A8, 0x0 },
 176         { 0x00004013, 0x000000A9, 0x0 },
 177         { 0x00007011, 0x000000A2, 0x0 },
 178         { 0x00009010, 0x0000009C, 0x0 },
 179         { 0x00000018, 0x000000A9, 0x0 },
 180         { 0x00006013, 0x000000A2, 0x0 },
 181         { 0x00007011, 0x000000A6, 0x0 },
 182         { 0x00000018, 0x000000AB, 0x0 },
 183         { 0x00007013, 0x0000009F, 0x0 },
 184         { 0x00000018, 0x000000DF, 0x0 },
 185 };
 186
 187 /*
 188  * Skylake U
 189  * eDP 1.4 low vswing translation parameters
 190  */
 191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 192         { 0x00000018, 0x000000A8, 0x0 },
 193         { 0x00004013, 0x000000A9, 0x0 },
 194         { 0x00007011, 0x000000A2, 0x0 },
 195         { 0x00009010, 0x0000009C, 0x0 },
 196         { 0x00000018, 0x000000A9, 0x0 },
 197         { 0x00006013, 0x000000A2, 0x0 },
 198         { 0x00007011, 0x000000A6, 0x0 },
 199         { 0x00002016, 0x000000AB, 0x0 },
 200         { 0x00005013, 0x0000009F, 0x0 },
 201         { 0x00000018, 0x000000DF, 0x0 },
 202 };
 203
 204 /*
 205  * Skylake Y
 206  * eDP 1.4 low vswing translation parameters
 207  */
 208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 209         { 0x00000018, 0x000000A8, 0x0 },
 210         { 0x00004013, 0x000000AB, 0x0 },
 211         { 0x00007011, 0x000000A4, 0x0 },
 212         { 0x00009010, 0x000000DF, 0x0 },
 213         { 0x00000018, 0x000000AA, 0x0 },
 214         { 0x00006013, 0x000000A4, 0x0 },
 215         { 0x00007011, 0x0000009D, 0x0 },
 216         { 0x00000018, 0x000000A0, 0x0 },
 217         { 0x00006012, 0x000000DF, 0x0 },
 218         { 0x00000018, 0x0000008A, 0x0 },
 219 };
 220
 221 /* Skylake U, H and S */
 222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 223         { 0x00000018, 0x000000AC, 0x0 },
 224         { 0x00005012, 0x0000009D, 0x0 },
 225         { 0x00007011, 0x00000088, 0x0 },
 226         { 0x00000018, 0x000000A1, 0x0 },
 227         { 0x00000018, 0x00000098, 0x0 },
 228         { 0x00004013, 0x00000088, 0x0 },
 229         { 0x80006012, 0x000000CD, 0x1 },
 230         { 0x00000018, 0x000000DF, 0x0 },
 231         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 232         { 0x80003015, 0x000000C0, 0x1 },
 233         { 0x80000018, 0x000000C0, 0x1 },
 234 };
 235
 236 /* Skylake Y */
 237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 238         { 0x00000018, 0x000000A1, 0x0 },
 239         { 0x00005012, 0x000000DF, 0x0 },
 240         { 0x80007011, 0x000000CB, 0x3 },
 241         { 0x00000018, 0x000000A4, 0x0 },
 242         { 0x00000018, 0x0000009D, 0x0 },
 243         { 0x00004013, 0x00000080, 0x0 },
 244         { 0x80006013, 0x000000C0, 0x3 },
 245         { 0x00000018, 0x0000008A, 0x0 },
 246         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 247         { 0x80003015, 0x000000C0, 0x3 },
 248         { 0x80000018, 0x000000C0, 0x3 },
 249 };
 250
 251 struct bxt_ddi_buf_trans {
 252         u32 margin;     /* swing value */
 253         u32 scale;      /* scale value */
 254         u32 enable;     /* scale enable */
 255         u32 deemphasis;
 256         bool default_index; /* true if the entry represents default value */
 257 };
 258
 259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 260                                         /* Idx  NT mV diff      db  */
 261         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 262         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 263         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 264         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 265         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 266         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 267         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 268         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 269         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 270         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 271 };
 272
 273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 274                                         /* Idx  NT mV diff      db  */
 275         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 276         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 277         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 278         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 279         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 280         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 281         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 282         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 283         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 284         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 285 };
 286
 287 /* BSpec has 2 recommended values - entries 0 and 8.
 288  * Using the entry with higher vswing.
 289  */
 290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 291                                         /* Idx  NT mV diff      db  */
 292         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 293         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 294         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 295         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 296         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 297         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 298         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 299         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 300         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 301         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 302 };
 303
 304 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
 305                                     u32 level, enum port port, int type);
 306
 307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
 308                                  struct intel_digital_port **dig_port,
 309                                  enum port *port)
 310 {
 311         struct drm_encoder *encoder = &intel_encoder->base;
 312
 313         switch (intel_encoder->type) {
 314         case INTEL_OUTPUT_DP_MST:
 315                 *dig_port = enc_to_mst(encoder)->primary;
 316                 *port = (*dig_port)->port;
 317                 break;
 318         case INTEL_OUTPUT_DISPLAYPORT:
 319         case INTEL_OUTPUT_EDP:
 320         case INTEL_OUTPUT_HDMI:
 321         case INTEL_OUTPUT_UNKNOWN:
 322                 *dig_port = enc_to_dig_port(encoder);
 323                 *port = (*dig_port)->port;
 324                 break;
 325         case INTEL_OUTPUT_ANALOG:
 326                 *dig_port = NULL;
 327                 *port = PORT_E;
 328                 break;
 329         default:
 330                 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
 331                 break;
 332         }
 333 }
 334
 335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 336 {
 337         struct intel_digital_port *dig_port;
 338         enum port port;
 339
 340         ddi_get_encoder_port(intel_encoder, &dig_port, &port);
 341
 342         return port;
 343 }
 344
 345 static const struct ddi_buf_trans *
 346 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 347 {
 348         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 349                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 350                 return skl_y_ddi_translations_dp;
 351         } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 352                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 353                 return skl_u_ddi_translations_dp;
 354         } else {
 355                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 356                 return skl_ddi_translations_dp;
 357         }
 358 }
 359
 360 static const struct ddi_buf_trans *
 361 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 362 {
 363         if (dev_priv->edp_low_vswing) {
 364                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 365                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 366                         return skl_y_ddi_translations_edp;
 367                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 368                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 369                         return skl_u_ddi_translations_edp;
 370                 } else {
 371                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 372                         return skl_ddi_translations_edp;
 373                 }
 374         }
 375
 376         return skl_get_buf_trans_dp(dev_priv, n_entries);
 377 }
 378
 379 static const struct ddi_buf_trans *
 380 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 381 {
 382         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 383                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 384                 return skl_y_ddi_translations_hdmi;
 385         } else {
 386                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 387                 return skl_ddi_translations_hdmi;
 388         }
 389 }
 390
 391 /*
 392  * Starting with Haswell, DDI port buffers must be programmed with correct
 393  * values in advance. The buffer values are different for FDI and DP modes,
 394  * but the HDMI/DVI fields are shared among those. So we program the DDI
 395  * in either FDI or DP modes only, as HDMI connections will work with both
 396  * of those
 397  */
 398 void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
 399 {
 400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 401         u32 iboost_bit = 0;
 402         int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 403             size;
 404         int hdmi_level;
 405         enum port port;
 406         const struct ddi_buf_trans *ddi_translations_fdi;
 407         const struct ddi_buf_trans *ddi_translations_dp;
 408         const struct ddi_buf_trans *ddi_translations_edp;
 409         const struct ddi_buf_trans *ddi_translations_hdmi;
 410         const struct ddi_buf_trans *ddi_translations;
 411
 412         port = intel_ddi_get_encoder_port(encoder);
 413         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 414
 415         if (IS_BROXTON(dev_priv)) {
 416                 if (encoder->type != INTEL_OUTPUT_HDMI)
 417                         return;
 418
 419                 /* Vswing programming for HDMI */
 420                 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
 421                                         INTEL_OUTPUT_HDMI);
 422                 return;
 423         }
 424
 425         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 426                 ddi_translations_fdi = NULL;
 427                 ddi_translations_dp =
 428                                 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
 429                 ddi_translations_edp =
 430                                 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
 431                 ddi_translations_hdmi =
 432                                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 433                 hdmi_default_entry = 8;
 434                 /* If we're boosting the current, set bit 31 of trans1 */
 435                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
 436                     dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 437                         iboost_bit = 1<<31;
 438
 439                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 440                             port != PORT_A && port != PORT_E &&
 441                             n_edp_entries > 9))
 442                         n_edp_entries = 9;
 443         } else if (IS_BROADWELL(dev_priv)) {
 444                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 445                 ddi_translations_dp = bdw_ddi_translations_dp;
 446                 ddi_translations_edp = bdw_ddi_translations_edp;
 447                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 448                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 449                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 450                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 451                 hdmi_default_entry = 7;
 452         } else if (IS_HASWELL(dev_priv)) {
 453                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 454                 ddi_translations_dp = hsw_ddi_translations_dp;
 455                 ddi_translations_edp = hsw_ddi_translations_dp;
 456                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 457                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 458                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 459                 hdmi_default_entry = 6;
 460         } else {
 461                 WARN(1, "ddi translation table missing\n");
 462                 ddi_translations_edp = bdw_ddi_translations_dp;
 463                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 464                 ddi_translations_dp = bdw_ddi_translations_dp;
 465                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 466                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 467                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 468                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 469                 hdmi_default_entry = 7;
 470         }
 471
 472         switch (encoder->type) {
 473         case INTEL_OUTPUT_EDP:
 474                 ddi_translations = ddi_translations_edp;
 475                 size = n_edp_entries;
 476                 break;
 477         case INTEL_OUTPUT_DISPLAYPORT:
 478         case INTEL_OUTPUT_HDMI:
 479                 ddi_translations = ddi_translations_dp;
 480                 size = n_dp_entries;
 481                 break;
 482         case INTEL_OUTPUT_ANALOG:
 483                 ddi_translations = ddi_translations_fdi;
 484                 size = n_dp_entries;
 485                 break;
 486         default:
 487                 BUG();
 488         }
 489
 490         for (i = 0; i < size; i++) {
 491                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 492                            ddi_translations[i].trans1 | iboost_bit);
 493                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 494                            ddi_translations[i].trans2);
 495         }
 496
 497         if (encoder->type != INTEL_OUTPUT_HDMI)
 498                 return;
 499
 500         /* Choose a good default if VBT is badly populated */
 501         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 502             hdmi_level >= n_hdmi_entries)
 503                 hdmi_level = hdmi_default_entry;
 504
 505         /* Entry 9 is for HDMI: */
 506         I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 507                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 508         I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 509                    ddi_translations_hdmi[hdmi_level].trans2);
 510 }
 511
 512 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 513                                     enum port port)
 514 {
 515         i915_reg_t reg = DDI_BUF_CTL(port);
 516         int i;
 517
 518         for (i = 0; i < 16; i++) {
 519                 udelay(1);
 520                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 521                         return;
 522         }
 523         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 524 }
 525
 526 /* Starting with Haswell, different DDI ports can work in FDI mode for
 527  * connection to the PCH-located connectors. For this, it is necessary to train
 528  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 529  *
 530  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 531  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 532  * DDI A (which is used for eDP)
 533  */
 534
 535 void hsw_fdi_link_train(struct drm_crtc *crtc)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         struct drm_i915_private *dev_priv = dev->dev_private;
 539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 540         struct intel_encoder *encoder;
 541         u32 temp, i, rx_ctl_val;
 542
 543         for_each_encoder_on_crtc(dev, crtc, encoder) {
 544                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 545                 intel_prepare_ddi_buffer(encoder);
 546         }
 547
 548         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 549          * mode set "sequence for CRT port" document:
 550          * - TP1 to TP2 time with the default value
 551          * - FDI delay to 90h
 552          *
 553          * WaFDIAutoLinkSetTimingOverrride:hsw
 554          */
 555         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 556                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 557                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 558
 559         /* Enable the PCH Receiver FDI PLL */
 560         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 561                      FDI_RX_PLL_ENABLE |
 562                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 563         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 564         POSTING_READ(FDI_RX_CTL(PIPE_A));
 565         udelay(220);
 566
 567         /* Switch from Rawclk to PCDclk */
 568         rx_ctl_val |= FDI_PCDCLK;
 569         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 570
 571         /* Configure Port Clock Select */
 572         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
 573         WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 574
 575         /* Start the training iterating through available voltages and emphasis,
 576          * testing each value twice. */
 577         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 578                 /* Configure DP_TP_CTL with auto-training */
 579                 I915_WRITE(DP_TP_CTL(PORT_E),
 580                                         DP_TP_CTL_FDI_AUTOTRAIN |
 581                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 582                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 583                                         DP_TP_CTL_ENABLE);
 584
 585                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 586                  * DDI E does not support port reversal, the functionality is
 587                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 588                  * port reversal bit */
 589                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 590                            DDI_BUF_CTL_ENABLE |
 591                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 592                            DDI_BUF_TRANS_SELECT(i / 2));
 593                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 594
 595                 udelay(600);
 596
 597                 /* Program PCH FDI Receiver TU */
 598                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 599
 600                 /* Enable PCH FDI Receiver with auto-training */
 601                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 602                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 603                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 604
 605                 /* Wait for FDI receiver lane calibration */
 606                 udelay(30);
 607
 608                 /* Unset FDI_RX_MISC pwrdn lanes */
 609                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 610                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 611                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 612                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 613
 614                 /* Wait for FDI auto training time */
 615                 udelay(5);
 616
 617                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 618                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 619                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 620                         break;
 621                 }
 622
 623                 /*
 624                  * Leave things enabled even if we failed to train FDI.
 625                  * Results in less fireworks from the state checker.
 626                  */
 627                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 628                         DRM_ERROR("FDI link training failed!\n");
 629                         break;
 630                 }
 631
 632                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 633                 temp &= ~DDI_BUF_CTL_ENABLE;
 634                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 635                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 636
 637                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 638                 temp = I915_READ(DP_TP_CTL(PORT_E));
 639                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 640                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 641                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 642                 POSTING_READ(DP_TP_CTL(PORT_E));
 643
 644                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 645
 646                 rx_ctl_val &= ~FDI_RX_ENABLE;
 647                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 648                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 649
 650                 /* Reset FDI_RX_MISC pwrdn lanes */
 651                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 652                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 653                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 654                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 655                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 656         }
 657
 658         /* Enable normal pixel sending for FDI */
 659         I915_WRITE(DP_TP_CTL(PORT_E),
 660                    DP_TP_CTL_FDI_AUTOTRAIN |
 661                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 662                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 663                    DP_TP_CTL_ENABLE);
 664 }
 665
 666 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 667 {
 668         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 669         struct intel_digital_port *intel_dig_port =
 670                 enc_to_dig_port(&encoder->base);
 671
 672         intel_dp->DP = intel_dig_port->saved_port_bits |
 673                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 674         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 675 }
 676
 677 static struct intel_encoder *
 678 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 682         struct intel_encoder *intel_encoder, *ret = NULL;
 683         int num_encoders = 0;
 684
 685         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 686                 ret = intel_encoder;
 687                 num_encoders++;
 688         }
 689
 690         if (num_encoders != 1)
 691                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 692                      pipe_name(intel_crtc->pipe));
 693
 694         BUG_ON(ret == NULL);
 695         return ret;
 696 }
 697
 698 struct intel_encoder *
 699 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 700 {
 701         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 702         struct intel_encoder *ret = NULL;
 703         struct drm_atomic_state *state;
 704         struct drm_connector *connector;
 705         struct drm_connector_state *connector_state;
 706         int num_encoders = 0;
 707         int i;
 708
 709         state = crtc_state->base.state;
 710
 711         for_each_connector_in_state(state, connector, connector_state, i) {
 712                 if (connector_state->crtc != crtc_state->base.crtc)
 713                         continue;
 714
 715                 ret = to_intel_encoder(connector_state->best_encoder);
 716                 num_encoders++;
 717         }
 718
 719         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 720              pipe_name(crtc->pipe));
 721
 722         BUG_ON(ret == NULL);
 723         return ret;
 724 }
 725
 726 #define LC_FREQ 2700
 727 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 728
 729 #define P_MIN 2
 730 #define P_MAX 64
 731 #define P_INC 2
 732
 733 /* Constraints for PLL good behavior */
 734 #define REF_MIN 48
 735 #define REF_MAX 400
 736 #define VCO_MIN 2400
 737 #define VCO_MAX 4800
 738
 739 #define abs_diff(a, b) ({                       \
 740         typeof(a) __a = (a);                    \
 741         typeof(b) __b = (b);                    \
 742         (void) (&__a == &__b);                  \
 743         __a > __b ? (__a - __b) : (__b - __a); })
 744
 745 struct hsw_wrpll_rnp {
 746         unsigned p, n2, r2;
 747 };
 748
 749 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
 750 {
 751         unsigned budget;
 752
 753         switch (clock) {
 754         case 25175000:
 755         case 25200000:
 756         case 27000000:
 757         case 27027000:
 758         case 37762500:
 759         case 37800000:
 760         case 40500000:
 761         case 40541000:
 762         case 54000000:
 763         case 54054000:
 764         case 59341000:
 765         case 59400000:
 766         case 72000000:
 767         case 74176000:
 768         case 74250000:
 769         case 81000000:
 770         case 81081000:
 771         case 89012000:
 772         case 89100000:
 773         case 108000000:
 774         case 108108000:
 775         case 111264000:
 776         case 111375000:
 777         case 148352000:
 778         case 148500000:
 779         case 162000000:
 780         case 162162000:
 781         case 222525000:
 782         case 222750000:
 783         case 296703000:
 784         case 297000000:
 785                 budget = 0;
 786                 break;
 787         case 233500000:
 788         case 245250000:
 789         case 247750000:
 790         case 253250000:
 791         case 298000000:
 792                 budget = 1500;
 793                 break;
 794         case 169128000:
 795         case 169500000:
 796         case 179500000:
 797         case 202000000:
 798                 budget = 2000;
 799                 break;
 800         case 256250000:
 801         case 262500000:
 802         case 270000000:
 803         case 272500000:
 804         case 273750000:
 805         case 280750000:
 806         case 281250000:
 807         case 286000000:
 808         case 291750000:
 809                 budget = 4000;
 810                 break;
 811         case 267250000:
 812         case 268500000:
 813                 budget = 5000;
 814                 break;
 815         default:
 816                 budget = 1000;
 817                 break;
 818         }
 819
 820         return budget;
 821 }
 822
 823 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 824                                  unsigned r2, unsigned n2, unsigned p,
 825                                  struct hsw_wrpll_rnp *best)
 826 {
 827         uint64_t a, b, c, d, diff, diff_best;
 828
 829         /* No best (r,n,p) yet */
 830         if (best->p == 0) {
 831                 best->p = p;
 832                 best->n2 = n2;
 833                 best->r2 = r2;
 834                 return;
 835         }
 836
 837         /*
 838          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 839          * freq2k.
 840          *
 841          * delta = 1e6 *
 842          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 843          *         freq2k;
 844          *
 845          * and we would like delta <= budget.
 846          *
 847          * If the discrepancy is above the PPM-based budget, always prefer to
 848          * improve upon the previous solution.  However, if you're within the
 849          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 850          */
 851         a = freq2k * budget * p * r2;
 852         b = freq2k * budget * best->p * best->r2;
 853         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 854         diff_best = abs_diff(freq2k * best->p * best->r2,
 855                              LC_FREQ_2K * best->n2);
 856         c = 1000000 * diff;
 857         d = 1000000 * diff_best;
 858
 859         if (a < c && b < d) {
 860                 /* If both are above the budget, pick the closer */
 861                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 862                         best->p = p;
 863                         best->n2 = n2;
 864                         best->r2 = r2;
 865                 }
 866         } else if (a >= c && b < d) {
 867                 /* If A is below the threshold but B is above it?  Update. */
 868                 best->p = p;
 869                 best->n2 = n2;
 870                 best->r2 = r2;
 871         } else if (a >= c && b >= d) {
 872                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 873                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 874                         best->p = p;
 875                         best->n2 = n2;
 876                         best->r2 = r2;
 877                 }
 878         }
 879         /* Otherwise a < c && b >= d, do nothing */
 880 }
 881
 882 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 883                                    i915_reg_t reg)
 884 {
 885         int refclk = LC_FREQ;
 886         int n, p, r;
 887         u32 wrpll;
 888
 889         wrpll = I915_READ(reg);
 890         switch (wrpll & WRPLL_PLL_REF_MASK) {
 891         case WRPLL_PLL_SSC:
 892         case WRPLL_PLL_NON_SSC:
 893                 /*
 894                  * We could calculate spread here, but our checking
 895                  * code only cares about 5% accuracy, and spread is a max of
 896                  * 0.5% downspread.
 897                  */
 898                 refclk = 135;
 899                 break;
 900         case WRPLL_PLL_LCPLL:
 901                 refclk = LC_FREQ;
 902                 break;
 903         default:
 904                 WARN(1, "bad wrpll refclk\n");
 905                 return 0;
 906         }
 907
 908         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 909         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 910         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 911
 912         /* Convert to KHz, p & r have a fixed point portion */
 913         return (refclk * n * 100) / (p * r);
 914 }
 915
 916 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 917                                uint32_t dpll)
 918 {
 919         i915_reg_t cfgcr1_reg, cfgcr2_reg;
 920         uint32_t cfgcr1_val, cfgcr2_val;
 921         uint32_t p0, p1, p2, dco_freq;
 922
 923         cfgcr1_reg = DPLL_CFGCR1(dpll);
 924         cfgcr2_reg = DPLL_CFGCR2(dpll);
 925
 926         cfgcr1_val = I915_READ(cfgcr1_reg);
 927         cfgcr2_val = I915_READ(cfgcr2_reg);
 928
 929         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 930         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 931
 932         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 933                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 934         else
 935                 p1 = 1;
 936
 937
 938         switch (p0) {
 939         case DPLL_CFGCR2_PDIV_1:
 940                 p0 = 1;
 941                 break;
 942         case DPLL_CFGCR2_PDIV_2:
 943                 p0 = 2;
 944                 break;
 945         case DPLL_CFGCR2_PDIV_3:
 946                 p0 = 3;
 947                 break;
 948         case DPLL_CFGCR2_PDIV_7:
 949                 p0 = 7;
 950                 break;
 951         }
 952
 953         switch (p2) {
 954         case DPLL_CFGCR2_KDIV_5:
 955                 p2 = 5;
 956                 break;
 957         case DPLL_CFGCR2_KDIV_2:
 958                 p2 = 2;
 959                 break;
 960         case DPLL_CFGCR2_KDIV_3:
 961                 p2 = 3;
 962                 break;
 963         case DPLL_CFGCR2_KDIV_1:
 964                 p2 = 1;
 965                 break;
 966         }
 967
 968         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 969
 970         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 971                 1000) / 0x8000;
 972
 973         return dco_freq / (p0 * p1 * p2 * 5);
 974 }
 975
 976 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 977 {
 978         int dotclock;
 979
 980         if (pipe_config->has_pch_encoder)
 981                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 982                                                     &pipe_config->fdi_m_n);
 983         else if (pipe_config->has_dp_encoder)
 984                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 985                                                     &pipe_config->dp_m_n);
 986         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
 987                 dotclock = pipe_config->port_clock * 2 / 3;
 988         else
 989                 dotclock = pipe_config->port_clock;
 990
 991         if (pipe_config->pixel_multiplier)
 992                 dotclock /= pipe_config->pixel_multiplier;
 993
 994         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 995 }
 996
 997 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 998                                 struct intel_crtc_state *pipe_config)
 999 {
1000         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1001         int link_clock = 0;
1002         uint32_t dpll_ctl1, dpll;
1003
1004         dpll = pipe_config->ddi_pll_sel;
1005
1006         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1007
1008         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1009                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1010         } else {
1011                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1012                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1013
1014                 switch (link_clock) {
1015                 case DPLL_CTRL1_LINK_RATE_810:
1016                         link_clock = 81000;
1017                         break;
1018                 case DPLL_CTRL1_LINK_RATE_1080:
1019                         link_clock = 108000;
1020                         break;
1021                 case DPLL_CTRL1_LINK_RATE_1350:
1022                         link_clock = 135000;
1023                         break;
1024                 case DPLL_CTRL1_LINK_RATE_1620:
1025                         link_clock = 162000;
1026                         break;
1027                 case DPLL_CTRL1_LINK_RATE_2160:
1028                         link_clock = 216000;
1029                         break;
1030                 case DPLL_CTRL1_LINK_RATE_2700:
1031                         link_clock = 270000;
1032                         break;
1033                 default:
1034                         WARN(1, "Unsupported link rate\n");
1035                         break;
1036                 }
1037                 link_clock *= 2;
1038         }
1039
1040         pipe_config->port_clock = link_clock;
1041
1042         ddi_dotclock_get(pipe_config);
1043 }
1044
1045 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1046                               struct intel_crtc_state *pipe_config)
1047 {
1048         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1049         int link_clock = 0;
1050         u32 val, pll;
1051
1052         val = pipe_config->ddi_pll_sel;
1053         switch (val & PORT_CLK_SEL_MASK) {
1054         case PORT_CLK_SEL_LCPLL_810:
1055                 link_clock = 81000;
1056                 break;
1057         case PORT_CLK_SEL_LCPLL_1350:
1058                 link_clock = 135000;
1059                 break;
1060         case PORT_CLK_SEL_LCPLL_2700:
1061                 link_clock = 270000;
1062                 break;
1063         case PORT_CLK_SEL_WRPLL1:
1064                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1065                 break;
1066         case PORT_CLK_SEL_WRPLL2:
1067                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1068                 break;
1069         case PORT_CLK_SEL_SPLL:
1070                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1071                 if (pll == SPLL_PLL_FREQ_810MHz)
1072                         link_clock = 81000;
1073                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1074                         link_clock = 135000;
1075                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1076                         link_clock = 270000;
1077                 else {
1078                         WARN(1, "bad spll freq\n");
1079                         return;
1080                 }
1081                 break;
1082         default:
1083                 WARN(1, "bad port clock sel\n");
1084                 return;
1085         }
1086
1087         pipe_config->port_clock = link_clock * 2;
1088
1089         ddi_dotclock_get(pipe_config);
1090 }
1091
1092 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1093                                 enum intel_dpll_id dpll)
1094 {
1095         struct intel_shared_dpll *pll;
1096         struct intel_dpll_hw_state *state;
1097         intel_clock_t clock;
1098
1099         /* For DDI ports we always use a shared PLL. */
1100         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1101                 return 0;
1102
1103         pll = &dev_priv->shared_dplls[dpll];
1104         state = &pll->config.hw_state;
1105
1106         clock.m1 = 2;
1107         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1108         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1109                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1110         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1111         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1112         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1113
1114         return chv_calc_dpll_params(100000, &clock);
1115 }
1116
1117 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1118                                 struct intel_crtc_state *pipe_config)
1119 {
1120         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1121         enum port port = intel_ddi_get_encoder_port(encoder);
1122         uint32_t dpll = port;
1123
1124         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1125
1126         ddi_dotclock_get(pipe_config);
1127 }
1128
1129 void intel_ddi_clock_get(struct intel_encoder *encoder,
1130                          struct intel_crtc_state *pipe_config)
1131 {
1132         struct drm_device *dev = encoder->base.dev;
1133
1134         if (INTEL_INFO(dev)->gen <= 8)
1135                 hsw_ddi_clock_get(encoder, pipe_config);
1136         else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1137                 skl_ddi_clock_get(encoder, pipe_config);
1138         else if (IS_BROXTON(dev))
1139                 bxt_ddi_clock_get(encoder, pipe_config);
1140 }
1141
1142 static void
1143 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1144                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1145 {
1146         uint64_t freq2k;
1147         unsigned p, n2, r2;
1148         struct hsw_wrpll_rnp best = { 0, 0, 0 };
1149         unsigned budget;
1150
1151         freq2k = clock / 100;
1152
1153         budget = hsw_wrpll_get_budget_for_freq(clock);
1154
1155         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1156          * and directly pass the LC PLL to it. */
1157         if (freq2k == 5400000) {
1158                 *n2_out = 2;
1159                 *p_out = 1;
1160                 *r2_out = 2;
1161                 return;
1162         }
1163
1164         /*
1165          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1166          * the WR PLL.
1167          *
1168          * We want R so that REF_MIN <= Ref <= REF_MAX.
1169          * Injecting R2 = 2 * R gives:
1170          *   REF_MAX * r2 > LC_FREQ * 2 and
1171          *   REF_MIN * r2 < LC_FREQ * 2
1172          *
1173          * Which means the desired boundaries for r2 are:
1174          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1175          *
1176          */
1177         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1178              r2 <= LC_FREQ * 2 / REF_MIN;
1179              r2++) {
1180
1181                 /*
1182                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1183                  *
1184                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1185                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1186                  *   VCO_MAX * r2 > n2 * LC_FREQ and
1187                  *   VCO_MIN * r2 < n2 * LC_FREQ)
1188                  *
1189                  * Which means the desired boundaries for n2 are:
1190                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1191                  */
1192                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1193                      n2 <= VCO_MAX * r2 / LC_FREQ;
1194                      n2++) {
1195
1196                         for (p = P_MIN; p <= P_MAX; p += P_INC)
1197                                 hsw_wrpll_update_rnp(freq2k, budget,
1198                                                      r2, n2, p, &best);
1199                 }
1200         }
1201
1202         *n2_out = best.n2;
1203         *p_out = best.p;
1204         *r2_out = best.r2;
1205 }
1206
1207 static bool
1208 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1209                    struct intel_crtc_state *crtc_state,
1210                    struct intel_encoder *intel_encoder)
1211 {
1212         int clock = crtc_state->port_clock;
1213
1214         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1215                 struct intel_shared_dpll *pll;
1216                 uint32_t val;
1217                 unsigned p, n2, r2;
1218
1219                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1220
1221                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1222                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1223                       WRPLL_DIVIDER_POST(p);
1224
1225                 memset(&crtc_state->dpll_hw_state, 0,
1226                        sizeof(crtc_state->dpll_hw_state));
1227
1228                 crtc_state->dpll_hw_state.wrpll = val;
1229
1230                 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1231                 if (pll == NULL) {
1232                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1233                                          pipe_name(intel_crtc->pipe));
1234                         return false;
1235                 }
1236
1237                 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1238         } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1239                 struct drm_atomic_state *state = crtc_state->base.state;
1240                 struct intel_shared_dpll_config *spll =
1241                         &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1242
1243                 if (spll->crtc_mask &&
1244                     WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1245                         return false;
1246
1247                 crtc_state->shared_dpll = DPLL_ID_SPLL;
1248                 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1249                 spll->crtc_mask |= 1 << intel_crtc->pipe;
1250         }
1251
1252         return true;
1253 }
1254
1255 struct skl_wrpll_context {
1256         uint64_t min_deviation;         /* current minimal deviation */
1257         uint64_t central_freq;          /* chosen central freq */
1258         uint64_t dco_freq;              /* chosen dco freq */
1259         unsigned int p;                 /* chosen divider */
1260 };
1261
1262 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1263 {
1264         memset(ctx, 0, sizeof(*ctx));
1265
1266         ctx->min_deviation = U64_MAX;
1267 }
1268
1269 /* DCO freq must be within +1%/-6%  of the DCO central freq */
1270 #define SKL_DCO_MAX_PDEVIATION  100
1271 #define SKL_DCO_MAX_NDEVIATION  600
1272
1273 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1274                                   uint64_t central_freq,
1275                                   uint64_t dco_freq,
1276                                   unsigned int divider)
1277 {
1278         uint64_t deviation;
1279
1280         deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1281                               central_freq);
1282
1283         /* positive deviation */
1284         if (dco_freq >= central_freq) {
1285                 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1286                     deviation < ctx->min_deviation) {
1287                         ctx->min_deviation = deviation;
1288                         ctx->central_freq = central_freq;
1289                         ctx->dco_freq = dco_freq;
1290                         ctx->p = divider;
1291                 }
1292         /* negative deviation */
1293         } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1294                    deviation < ctx->min_deviation) {
1295                 ctx->min_deviation = deviation;
1296                 ctx->central_freq = central_freq;
1297                 ctx->dco_freq = dco_freq;
1298                 ctx->p = divider;
1299         }
1300 }
1301
1302 static void skl_wrpll_get_multipliers(unsigned int p,
1303                                       unsigned int *p0 /* out */,
1304                                       unsigned int *p1 /* out */,
1305                                       unsigned int *p2 /* out */)
1306 {
1307         /* even dividers */
1308         if (p % 2 == 0) {
1309                 unsigned int half = p / 2;
1310
1311                 if (half == 1 || half == 2 || half == 3 || half == 5) {
1312                         *p0 = 2;
1313                         *p1 = 1;
1314                         *p2 = half;
1315                 } else if (half % 2 == 0) {
1316                         *p0 = 2;
1317                         *p1 = half / 2;
1318                         *p2 = 2;
1319                 } else if (half % 3 == 0) {
1320                         *p0 = 3;
1321                         *p1 = half / 3;
1322                         *p2 = 2;
1323                 } else if (half % 7 == 0) {
1324                         *p0 = 7;
1325                         *p1 = half / 7;
1326                         *p2 = 2;
1327                 }
1328         } else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
1329                 *p0 = 3;
1330                 *p1 = 1;
1331                 *p2 = p / 3;
1332         } else if (p == 5 || p == 7) {
1333                 *p0 = p;
1334                 *p1 = 1;
1335                 *p2 = 1;
1336         } else if (p == 15) {
1337                 *p0 = 3;
1338                 *p1 = 1;
1339                 *p2 = 5;
1340         } else if (p == 21) {
1341                 *p0 = 7;
1342                 *p1 = 1;
1343                 *p2 = 3;
1344         } else if (p == 35) {
1345                 *p0 = 7;
1346                 *p1 = 1;
1347                 *p2 = 5;
1348         }
1349 }
1350
1351 struct skl_wrpll_params {
1352         uint32_t        dco_fraction;
1353         uint32_t        dco_integer;
1354         uint32_t        qdiv_ratio;
1355         uint32_t        qdiv_mode;
1356         uint32_t        kdiv;
1357         uint32_t        pdiv;
1358         uint32_t        central_freq;
1359 };
1360
1361 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1362                                       uint64_t afe_clock,
1363                                       uint64_t central_freq,
1364                                       uint32_t p0, uint32_t p1, uint32_t p2)
1365 {
1366         uint64_t dco_freq;
1367
1368         switch (central_freq) {
1369         case 9600000000ULL:
1370                 params->central_freq = 0;
1371                 break;
1372         case 9000000000ULL:
1373                 params->central_freq = 1;
1374                 break;
1375         case 8400000000ULL:
1376                 params->central_freq = 3;
1377         }
1378
1379         switch (p0) {
1380         case 1:
1381                 params->pdiv = 0;
1382                 break;
1383         case 2:
1384                 params->pdiv = 1;
1385                 break;
1386         case 3:
1387                 params->pdiv = 2;
1388                 break;
1389         case 7:
1390                 params->pdiv = 4;
1391                 break;
1392         default:
1393                 WARN(1, "Incorrect PDiv\n");
1394         }
1395
1396         switch (p2) {
1397         case 5:
1398                 params->kdiv = 0;
1399                 break;
1400         case 2:
1401                 params->kdiv = 1;
1402                 break;
1403         case 3:
1404                 params->kdiv = 2;
1405                 break;
1406         case 1:
1407                 params->kdiv = 3;
1408                 break;
1409         default:
1410                 WARN(1, "Incorrect KDiv\n");
1411         }
1412
1413         params->qdiv_ratio = p1;
1414         params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1415
1416         dco_freq = p0 * p1 * p2 * afe_clock;
1417
1418         /*
1419          * Intermediate values are in Hz.
1420          * Divide by MHz to match bsepc
1421          */
1422         params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1423         params->dco_fraction =
1424                 div_u64((div_u64(dco_freq, 24) -
1425                          params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1426 }
1427
1428 static bool
1429 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1430                         struct skl_wrpll_params *wrpll_params)
1431 {
1432         uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1433         uint64_t dco_central_freq[3] = {8400000000ULL,
1434                                         9000000000ULL,
1435                                         9600000000ULL};
1436         static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
1437                                              24, 28, 30, 32, 36, 40, 42, 44,
1438                                              48, 52, 54, 56, 60, 64, 66, 68,
1439                                              70, 72, 76, 78, 80, 84, 88, 90,
1440                                              92, 96, 98 };
1441         static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1442         static const struct {
1443                 const int *list;
1444                 int n_dividers;
1445         } dividers[] = {
1446                 { even_dividers, ARRAY_SIZE(even_dividers) },
1447                 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1448         };
1449         struct skl_wrpll_context ctx;
1450         unsigned int dco, d, i;
1451         unsigned int p0, p1, p2;
1452
1453         skl_wrpll_context_init(&ctx);
1454
1455         for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1456                 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1457                         for (i = 0; i < dividers[d].n_dividers; i++) {
1458                                 unsigned int p = dividers[d].list[i];
1459                                 uint64_t dco_freq = p * afe_clock;
1460
1461                                 skl_wrpll_try_divider(&ctx,
1462                                                       dco_central_freq[dco],
1463                                                       dco_freq,
1464                                                       p);
1465                                 /*
1466                                  * Skip the remaining dividers if we're sure to
1467                                  * have found the definitive divider, we can't
1468                                  * improve a 0 deviation.
1469                                  */
1470                                 if (ctx.min_deviation == 0)
1471                                         goto skip_remaining_dividers;
1472                         }
1473                 }
1474
1475 skip_remaining_dividers:
1476                 /*
1477                  * If a solution is found with an even divider, prefer
1478                  * this one.
1479                  */
1480                 if (d == 0 && ctx.p)
1481                         break;
1482         }
1483
1484         if (!ctx.p) {
1485                 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1486                 return false;
1487         }
1488
1489         /*
1490          * gcc incorrectly analyses that these can be used without being
1491          * initialized. To be fair, it's hard to guess.
1492          */
1493         p0 = p1 = p2 = 0;
1494         skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1495         skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1496                                   p0, p1, p2);
1497
1498         return true;
1499 }
1500
1501 static bool
1502 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1503                    struct intel_crtc_state *crtc_state,
1504                    struct intel_encoder *intel_encoder)
1505 {
1506         struct intel_shared_dpll *pll;
1507         uint32_t ctrl1, cfgcr1, cfgcr2;
1508         int clock = crtc_state->port_clock;
1509
1510         /*
1511          * See comment in intel_dpll_hw_state to understand why we always use 0
1512          * as the DPLL id in this function.
1513          */
1514
1515         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1516
1517         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1518                 struct skl_wrpll_params wrpll_params = { 0, };
1519
1520                 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1521
1522                 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1523                         return false;
1524
1525                 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1526                          DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1527                          wrpll_params.dco_integer;
1528
1529                 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1530                          DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1531                          DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1532                          DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1533                          wrpll_params.central_freq;
1534         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1535                    intel_encoder->type == INTEL_OUTPUT_DP_MST) {
1536                 switch (crtc_state->port_clock / 2) {
1537                 case 81000:
1538                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1539                         break;
1540                 case 135000:
1541                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1542                         break;
1543                 case 270000:
1544                         ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1545                         break;
1546                 }
1547
1548                 cfgcr1 = cfgcr2 = 0;
1549         } else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
1550                 return true;
1551         } else
1552                 return false;
1553
1554         memset(&crtc_state->dpll_hw_state, 0,
1555                sizeof(crtc_state->dpll_hw_state));
1556
1557         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1558         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1559         crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1560
1561         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1562         if (pll == NULL) {
1563                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1564                                  pipe_name(intel_crtc->pipe));
1565                 return false;
1566         }
1567
1568         /* shared DPLL id 0 is DPLL 1 */
1569         crtc_state->ddi_pll_sel = pll->id + 1;
1570
1571         return true;
1572 }
1573
1574 /* bxt clock parameters */
1575 struct bxt_clk_div {
1576         int clock;
1577         uint32_t p1;
1578         uint32_t p2;
1579         uint32_t m2_int;
1580         uint32_t m2_frac;
1581         bool m2_frac_en;
1582         uint32_t n;
1583 };
1584
1585 /* pre-calculated values for DP linkrates */
1586 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1587         {162000, 4, 2, 32, 1677722, 1, 1},
1588         {270000, 4, 1, 27,       0, 0, 1},
1589         {540000, 2, 1, 27,       0, 0, 1},
1590         {216000, 3, 2, 32, 1677722, 1, 1},
1591         {243000, 4, 1, 24, 1258291, 1, 1},
1592         {324000, 4, 1, 32, 1677722, 1, 1},
1593         {432000, 3, 1, 32, 1677722, 1, 1}
1594 };
1595
1596 static bool
1597 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1598                    struct intel_crtc_state *crtc_state,
1599                    struct intel_encoder *intel_encoder)
1600 {
1601         struct intel_shared_dpll *pll;
1602         struct bxt_clk_div clk_div = {0};
1603         int vco = 0;
1604         uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1605         uint32_t lanestagger;
1606         int clock = crtc_state->port_clock;
1607
1608         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1609                 intel_clock_t best_clock;
1610
1611                 /* Calculate HDMI div */
1612                 /*
1613                  * FIXME: tie the following calculation into
1614                  * i9xx_crtc_compute_clock
1615                  */
1616                 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1617                         DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1618                                          clock, pipe_name(intel_crtc->pipe));
1619                         return false;
1620                 }
1621
1622                 clk_div.p1 = best_clock.p1;
1623                 clk_div.p2 = best_clock.p2;
1624                 WARN_ON(best_clock.m1 != 2);
1625                 clk_div.n = best_clock.n;
1626                 clk_div.m2_int = best_clock.m2 >> 22;
1627                 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1628                 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1629
1630                 vco = best_clock.vco;
1631         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1632                         intel_encoder->type == INTEL_OUTPUT_EDP) {
1633                 int i;
1634
1635                 clk_div = bxt_dp_clk_val[0];
1636                 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1637                         if (bxt_dp_clk_val[i].clock == clock) {
1638                                 clk_div = bxt_dp_clk_val[i];
1639                                 break;
1640                         }
1641                 }
1642                 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1643         }
1644
1645         if (vco >= 6200000 && vco <= 6700000) {
1646                 prop_coef = 4;
1647                 int_coef = 9;
1648                 gain_ctl = 3;
1649                 targ_cnt = 8;
1650         } else if ((vco > 5400000 && vco < 6200000) ||
1651                         (vco >= 4800000 && vco < 5400000)) {
1652                 prop_coef = 5;
1653                 int_coef = 11;
1654                 gain_ctl = 3;
1655                 targ_cnt = 9;
1656         } else if (vco == 5400000) {
1657                 prop_coef = 3;
1658                 int_coef = 8;
1659                 gain_ctl = 1;
1660                 targ_cnt = 9;
1661         } else {
1662                 DRM_ERROR("Invalid VCO\n");
1663                 return false;
1664         }
1665
1666         memset(&crtc_state->dpll_hw_state, 0,
1667                sizeof(crtc_state->dpll_hw_state));
1668
1669         if (clock > 270000)
1670                 lanestagger = 0x18;
1671         else if (clock > 135000)
1672                 lanestagger = 0x0d;
1673         else if (clock > 67000)
1674                 lanestagger = 0x07;
1675         else if (clock > 33000)
1676                 lanestagger = 0x04;
1677         else
1678                 lanestagger = 0x02;
1679
1680         crtc_state->dpll_hw_state.ebb0 =
1681                 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1682         crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1683         crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1684         crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1685
1686         if (clk_div.m2_frac_en)
1687                 crtc_state->dpll_hw_state.pll3 =
1688                         PORT_PLL_M2_FRAC_ENABLE;
1689
1690         crtc_state->dpll_hw_state.pll6 =
1691                 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1692         crtc_state->dpll_hw_state.pll6 |=
1693                 PORT_PLL_GAIN_CTL(gain_ctl);
1694
1695         crtc_state->dpll_hw_state.pll8 = targ_cnt;
1696
1697         crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1698
1699         crtc_state->dpll_hw_state.pll10 =
1700                 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1701                 | PORT_PLL_DCO_AMP_OVR_EN_H;
1702
1703         crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1704
1705         crtc_state->dpll_hw_state.pcsdw12 =
1706                 LANESTAGGER_STRAP_OVRD | lanestagger;
1707
1708         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1709         if (pll == NULL) {
1710                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1711                         pipe_name(intel_crtc->pipe));
1712                 return false;
1713         }
1714
1715         /* shared DPLL id 0 is DPLL A */
1716         crtc_state->ddi_pll_sel = pll->id;
1717
1718         return true;
1719 }
1720
1721 /*
1722  * Tries to find a *shared* PLL for the CRTC and store it in
1723  * intel_crtc->ddi_pll_sel.
1724  *
1725  * For private DPLLs, compute_config() should do the selection for us. This
1726  * function should be folded into compute_config() eventually.
1727  */
1728 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1729                           struct intel_crtc_state *crtc_state)
1730 {
1731         struct drm_device *dev = intel_crtc->base.dev;
1732         struct intel_encoder *intel_encoder =
1733                 intel_ddi_get_crtc_new_encoder(crtc_state);
1734
1735         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1736                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1737                                           intel_encoder);
1738         else if (IS_BROXTON(dev))
1739                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1740                                           intel_encoder);
1741         else
1742                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1743                                           intel_encoder);
1744 }
1745
1746 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1747 {
1748         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1750         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1751         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1752         int type = intel_encoder->type;
1753         uint32_t temp;
1754
1755         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1756                 temp = TRANS_MSA_SYNC_CLK;
1757                 switch (intel_crtc->config->pipe_bpp) {
1758                 case 18:
1759                         temp |= TRANS_MSA_6_BPC;
1760                         break;
1761                 case 24:
1762                         temp |= TRANS_MSA_8_BPC;
1763                         break;
1764                 case 30:
1765                         temp |= TRANS_MSA_10_BPC;
1766                         break;
1767                 case 36:
1768                         temp |= TRANS_MSA_12_BPC;
1769                         break;
1770                 default:
1771                         BUG();
1772                 }
1773                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1774         }
1775 }
1776
1777 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1778 {
1779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780         struct drm_device *dev = crtc->dev;
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1783         uint32_t temp;
1784         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1785         if (state == true)
1786                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1787         else
1788                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1789         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1790 }
1791
1792 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1793 {
1794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1795         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1796         struct drm_encoder *encoder = &intel_encoder->base;
1797         struct drm_device *dev = crtc->dev;
1798         struct drm_i915_private *dev_priv = dev->dev_private;
1799         enum pipe pipe = intel_crtc->pipe;
1800         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1801         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1802         int type = intel_encoder->type;
1803         uint32_t temp;
1804
1805         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1806         temp = TRANS_DDI_FUNC_ENABLE;
1807         temp |= TRANS_DDI_SELECT_PORT(port);
1808
1809         switch (intel_crtc->config->pipe_bpp) {
1810         case 18:
1811                 temp |= TRANS_DDI_BPC_6;
1812                 break;
1813         case 24:
1814                 temp |= TRANS_DDI_BPC_8;
1815                 break;
1816         case 30:
1817                 temp |= TRANS_DDI_BPC_10;
1818                 break;
1819         case 36:
1820                 temp |= TRANS_DDI_BPC_12;
1821                 break;
1822         default:
1823                 BUG();
1824         }
1825
1826         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1827                 temp |= TRANS_DDI_PVSYNC;
1828         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1829                 temp |= TRANS_DDI_PHSYNC;
1830
1831         if (cpu_transcoder == TRANSCODER_EDP) {
1832                 switch (pipe) {
1833                 case PIPE_A:
1834                         /* On Haswell, can only use the always-on power well for
1835                          * eDP when not using the panel fitter, and when not
1836                          * using motion blur mitigation (which we don't
1837                          * support). */
1838                         if (IS_HASWELL(dev) &&
1839                             (intel_crtc->config->pch_pfit.enabled ||
1840                              intel_crtc->config->pch_pfit.force_thru))
1841                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1842                         else
1843                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1844                         break;
1845                 case PIPE_B:
1846                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1847                         break;
1848                 case PIPE_C:
1849                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1850                         break;
1851                 default:
1852                         BUG();
1853                         break;
1854                 }
1855         }
1856
1857         if (type == INTEL_OUTPUT_HDMI) {
1858                 if (intel_crtc->config->has_hdmi_sink)
1859                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1860                 else
1861                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1862
1863         } else if (type == INTEL_OUTPUT_ANALOG) {
1864                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1865                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1866
1867         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1868                    type == INTEL_OUTPUT_EDP) {
1869                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1870
1871                 if (intel_dp->is_mst) {
1872                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1873                 } else
1874                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1875
1876                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1877         } else if (type == INTEL_OUTPUT_DP_MST) {
1878                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1879
1880                 if (intel_dp->is_mst) {
1881                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1882                 } else
1883                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1884
1885                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1886         } else {
1887                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1888                      intel_encoder->type, pipe_name(pipe));
1889         }
1890
1891         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1892 }
1893
1894 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1895                                        enum transcoder cpu_transcoder)
1896 {
1897         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1898         uint32_t val = I915_READ(reg);
1899
1900         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1901         val |= TRANS_DDI_PORT_NONE;
1902         I915_WRITE(reg, val);
1903 }
1904
1905 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1906 {
1907         struct drm_device *dev = intel_connector->base.dev;
1908         struct drm_i915_private *dev_priv = dev->dev_private;
1909         struct intel_encoder *intel_encoder = intel_connector->encoder;
1910         int type = intel_connector->base.connector_type;
1911         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1912         enum pipe pipe = 0;
1913         enum transcoder cpu_transcoder;
1914         enum intel_display_power_domain power_domain;
1915         uint32_t tmp;
1916
1917         power_domain = intel_display_port_power_domain(intel_encoder);
1918         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1919                 return false;
1920
1921         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1922                 return false;
1923
1924         if (port == PORT_A)
1925                 cpu_transcoder = TRANSCODER_EDP;
1926         else
1927                 cpu_transcoder = (enum transcoder) pipe;
1928
1929         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1930
1931         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1932         case TRANS_DDI_MODE_SELECT_HDMI:
1933         case TRANS_DDI_MODE_SELECT_DVI:
1934                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1935
1936         case TRANS_DDI_MODE_SELECT_DP_SST:
1937                 if (type == DRM_MODE_CONNECTOR_eDP)
1938                         return true;
1939                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1940         case TRANS_DDI_MODE_SELECT_DP_MST:
1941                 /* if the transcoder is in MST state then
1942                  * connector isn't connected */
1943                 return false;
1944
1945         case TRANS_DDI_MODE_SELECT_FDI:
1946                 return (type == DRM_MODE_CONNECTOR_VGA);
1947
1948         default:
1949                 return false;
1950         }
1951 }
1952
1953 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1954                             enum pipe *pipe)
1955 {
1956         struct drm_device *dev = encoder->base.dev;
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         enum port port = intel_ddi_get_encoder_port(encoder);
1959         enum intel_display_power_domain power_domain;
1960         u32 tmp;
1961         int i;
1962
1963         power_domain = intel_display_port_power_domain(encoder);
1964         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1965                 return false;
1966
1967         tmp = I915_READ(DDI_BUF_CTL(port));
1968
1969         if (!(tmp & DDI_BUF_CTL_ENABLE))
1970                 return false;
1971
1972         if (port == PORT_A) {
1973                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1974
1975                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1976                 case TRANS_DDI_EDP_INPUT_A_ON:
1977                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1978                         *pipe = PIPE_A;
1979                         break;
1980                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1981                         *pipe = PIPE_B;
1982                         break;
1983                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1984                         *pipe = PIPE_C;
1985                         break;
1986                 }
1987
1988                 return true;
1989         } else {
1990                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1991                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1992
1993                         if ((tmp & TRANS_DDI_PORT_MASK)
1994                             == TRANS_DDI_SELECT_PORT(port)) {
1995                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1996                                         return false;
1997
1998                                 *pipe = i;
1999                                 return true;
2000                         }
2001                 }
2002         }
2003
2004         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2005
2006         return false;
2007 }
2008
2009 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2010 {
2011         struct drm_crtc *crtc = &intel_crtc->base;
2012         struct drm_device *dev = crtc->dev;
2013         struct drm_i915_private *dev_priv = dev->dev_private;
2014         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2015         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2016         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2017
2018         if (cpu_transcoder != TRANSCODER_EDP)
2019                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2020                            TRANS_CLK_SEL_PORT(port));
2021 }
2022
2023 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2024 {
2025         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2026         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2027
2028         if (cpu_transcoder != TRANSCODER_EDP)
2029                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2030                            TRANS_CLK_SEL_DISABLED);
2031 }
2032
2033 static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2034                                u32 level, enum port port, int type)
2035 {
2036         const struct ddi_buf_trans *ddi_translations;
2037         uint8_t iboost;
2038         uint8_t dp_iboost, hdmi_iboost;
2039         int n_entries;
2040         u32 reg;
2041
2042         /* VBT may override standard boost values */
2043         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2044         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2045
2046         if (type == INTEL_OUTPUT_DISPLAYPORT) {
2047                 if (dp_iboost) {
2048                         iboost = dp_iboost;
2049                 } else {
2050                         ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
2051                         iboost = ddi_translations[level].i_boost;
2052                 }
2053         } else if (type == INTEL_OUTPUT_EDP) {
2054                 if (dp_iboost) {
2055                         iboost = dp_iboost;
2056                 } else {
2057                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
2058
2059                         if (WARN_ON(port != PORT_A &&
2060                                     port != PORT_E && n_entries > 9))
2061                                 n_entries = 9;
2062
2063                         iboost = ddi_translations[level].i_boost;
2064                 }
2065         } else if (type == INTEL_OUTPUT_HDMI) {
2066                 if (hdmi_iboost) {
2067                         iboost = hdmi_iboost;
2068                 } else {
2069                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
2070                         iboost = ddi_translations[level].i_boost;
2071                 }
2072         } else {
2073                 return;
2074         }
2075
2076         /* Make sure that the requested I_boost is valid */
2077         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2078                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2079                 return;
2080         }
2081
2082         reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2083         reg &= ~BALANCE_LEG_MASK(port);
2084         reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2085
2086         if (iboost)
2087                 reg |= iboost << BALANCE_LEG_SHIFT(port);
2088         else
2089                 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2090
2091         I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2092 }
2093
2094 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
2095                                     u32 level, enum port port, int type)
2096 {
2097         const struct bxt_ddi_buf_trans *ddi_translations;
2098         u32 n_entries, i;
2099         uint32_t val;
2100
2101         if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2102                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2103                 ddi_translations = bxt_ddi_translations_edp;
2104         } else if (type == INTEL_OUTPUT_DISPLAYPORT
2105                         || type == INTEL_OUTPUT_EDP) {
2106                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2107                 ddi_translations = bxt_ddi_translations_dp;
2108         } else if (type == INTEL_OUTPUT_HDMI) {
2109                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2110                 ddi_translations = bxt_ddi_translations_hdmi;
2111         } else {
2112                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2113                                 type);
2114                 return;
2115         }
2116
2117         /* Check if default value has to be used */
2118         if (level >= n_entries ||
2119             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2120                 for (i = 0; i < n_entries; i++) {
2121                         if (ddi_translations[i].default_index) {
2122                                 level = i;
2123                                 break;
2124                         }
2125                 }
2126         }
2127
2128         /*
2129          * While we write to the group register to program all lanes at once we
2130          * can read only lane registers and we pick lanes 0/1 for that.
2131          */
2132         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2133         val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2134         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2135
2136         val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2137         val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2138         val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2139                ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2140         I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2141
2142         val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2143         val &= ~SCALE_DCOMP_METHOD;
2144         if (ddi_translations[level].enable)
2145                 val |= SCALE_DCOMP_METHOD;
2146
2147         if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2148                 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2149
2150         I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2151
2152         val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2153         val &= ~DE_EMPHASIS;
2154         val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2155         I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2156
2157         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2158         val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2159         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2160 }
2161
2162 static uint32_t translate_signal_level(int signal_levels)
2163 {
2164         uint32_t level;
2165
2166         switch (signal_levels) {
2167         default:
2168                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2169                               signal_levels);
2170         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2171                 level = 0;
2172                 break;
2173         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2174                 level = 1;
2175                 break;
2176         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2177                 level = 2;
2178                 break;
2179         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2180                 level = 3;
2181                 break;
2182
2183         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2184                 level = 4;
2185                 break;
2186         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2187                 level = 5;
2188                 break;
2189         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2190                 level = 6;
2191                 break;
2192
2193         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2194                 level = 7;
2195                 break;
2196         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2197                 level = 8;
2198                 break;
2199
2200         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2201                 level = 9;
2202                 break;
2203         }
2204
2205         return level;
2206 }
2207
2208 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2209 {
2210         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2211         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2212         struct intel_encoder *encoder = &dport->base;
2213         uint8_t train_set = intel_dp->train_set[0];
2214         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2215                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2216         enum port port = dport->port;
2217         uint32_t level;
2218
2219         level = translate_signal_level(signal_levels);
2220
2221         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2222                 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
2223         else if (IS_BROXTON(dev_priv))
2224                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2225
2226         return DDI_BUF_TRANS_SELECT(level);
2227 }
2228
2229 void intel_ddi_clk_select(struct intel_encoder *encoder,
2230                           const struct intel_crtc_state *pipe_config)
2231 {
2232         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2233         enum port port = intel_ddi_get_encoder_port(encoder);
2234
2235         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2236                 uint32_t dpll = pipe_config->ddi_pll_sel;
2237                 uint32_t val;
2238
2239                 /*
2240                  * DPLL0 is used for eDP and is the only "private" DPLL (as
2241                  * opposed to shared) on SKL
2242                  */
2243                 if (encoder->type == INTEL_OUTPUT_EDP) {
2244                         WARN_ON(dpll != SKL_DPLL0);
2245
2246                         val = I915_READ(DPLL_CTRL1);
2247
2248                         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2249                                  DPLL_CTRL1_SSC(dpll) |
2250                                  DPLL_CTRL1_LINK_RATE_MASK(dpll));
2251                         val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
2252
2253                         I915_WRITE(DPLL_CTRL1, val);
2254                         POSTING_READ(DPLL_CTRL1);
2255                 }
2256
2257                 /* DDI -> PLL mapping  */
2258                 val = I915_READ(DPLL_CTRL2);
2259
2260                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2261                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2262                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2263                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2264
2265                 I915_WRITE(DPLL_CTRL2, val);
2266
2267         } else if (INTEL_INFO(dev_priv)->gen < 9) {
2268                 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2269                 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
2270         }
2271 }
2272
2273 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2274 {
2275         struct drm_encoder *encoder = &intel_encoder->base;
2276         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2277         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2278         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2279         int type = intel_encoder->type;
2280
2281         intel_prepare_ddi_buffer(intel_encoder);
2282
2283         if (type == INTEL_OUTPUT_EDP) {
2284                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2285                 intel_edp_panel_on(intel_dp);
2286         }
2287
2288         intel_ddi_clk_select(intel_encoder, crtc->config);
2289
2290         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2291                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2292
2293                 intel_dp_set_link_params(intel_dp, crtc->config);
2294
2295                 intel_ddi_init_dp_buf_reg(intel_encoder);
2296
2297                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2298                 intel_dp_start_link_train(intel_dp);
2299                 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
2300                         intel_dp_stop_link_train(intel_dp);
2301         } else if (type == INTEL_OUTPUT_HDMI) {
2302                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2303
2304                 intel_hdmi->set_infoframes(encoder,
2305                                            crtc->config->has_hdmi_sink,
2306                                            &crtc->config->base.adjusted_mode);
2307         }
2308 }
2309
2310 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
2311 {
2312         struct drm_encoder *encoder = &intel_encoder->base;
2313         struct drm_device *dev = encoder->dev;
2314         struct drm_i915_private *dev_priv = dev->dev_private;
2315         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2316         int type = intel_encoder->type;
2317         uint32_t val;
2318         bool wait = false;
2319
2320         val = I915_READ(DDI_BUF_CTL(port));
2321         if (val & DDI_BUF_CTL_ENABLE) {
2322                 val &= ~DDI_BUF_CTL_ENABLE;
2323                 I915_WRITE(DDI_BUF_CTL(port), val);
2324                 wait = true;
2325         }
2326
2327         val = I915_READ(DP_TP_CTL(port));
2328         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2329         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2330         I915_WRITE(DP_TP_CTL(port), val);
2331
2332         if (wait)
2333                 intel_wait_ddi_buf_idle(dev_priv, port);
2334
2335         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2336                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2337                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2338                 intel_edp_panel_vdd_on(intel_dp);
2339                 intel_edp_panel_off(intel_dp);
2340         }
2341
2342         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2343                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2344                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
2345         else if (INTEL_INFO(dev)->gen < 9)
2346                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2347 }
2348
2349 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
2350 {
2351         struct drm_encoder *encoder = &intel_encoder->base;
2352         struct drm_crtc *crtc = encoder->crtc;
2353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2354         struct drm_device *dev = encoder->dev;
2355         struct drm_i915_private *dev_priv = dev->dev_private;
2356         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2357         int type = intel_encoder->type;
2358
2359         if (type == INTEL_OUTPUT_HDMI) {
2360                 struct intel_digital_port *intel_dig_port =
2361                         enc_to_dig_port(encoder);
2362
2363                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2364                  * are ignored so nothing special needs to be done besides
2365                  * enabling the port.
2366                  */
2367                 I915_WRITE(DDI_BUF_CTL(port),
2368                            intel_dig_port->saved_port_bits |
2369                            DDI_BUF_CTL_ENABLE);
2370         } else if (type == INTEL_OUTPUT_EDP) {
2371                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2372
2373                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2374                         intel_dp_stop_link_train(intel_dp);
2375
2376                 intel_edp_backlight_on(intel_dp);
2377                 intel_psr_enable(intel_dp);
2378                 intel_edp_drrs_enable(intel_dp);
2379         }
2380
2381         if (intel_crtc->config->has_audio) {
2382                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2383                 intel_audio_codec_enable(intel_encoder);
2384         }
2385 }
2386
2387 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2388 {
2389         struct drm_encoder *encoder = &intel_encoder->base;
2390         struct drm_crtc *crtc = encoder->crtc;
2391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2392         int type = intel_encoder->type;
2393         struct drm_device *dev = encoder->dev;
2394         struct drm_i915_private *dev_priv = dev->dev_private;
2395
2396         if (intel_crtc->config->has_audio) {
2397                 intel_audio_codec_disable(intel_encoder);
2398                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2399         }
2400
2401         if (type == INTEL_OUTPUT_EDP) {
2402                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2403
2404                 intel_edp_drrs_disable(intel_dp);
2405                 intel_psr_disable(intel_dp);
2406                 intel_edp_backlight_off(intel_dp);
2407         }
2408 }
2409
2410 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
2411                                struct intel_shared_dpll *pll)
2412 {
2413         I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2414         POSTING_READ(WRPLL_CTL(pll->id));
2415         udelay(20);
2416 }
2417
2418 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
2419                                 struct intel_shared_dpll *pll)
2420 {
2421         I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2422         POSTING_READ(SPLL_CTL);
2423         udelay(20);
2424 }
2425
2426 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2427                                   struct intel_shared_dpll *pll)
2428 {
2429         uint32_t val;
2430
2431         val = I915_READ(WRPLL_CTL(pll->id));
2432         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2433         POSTING_READ(WRPLL_CTL(pll->id));
2434 }
2435
2436 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2437                                  struct intel_shared_dpll *pll)
2438 {
2439         uint32_t val;
2440
2441         val = I915_READ(SPLL_CTL);
2442         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2443         POSTING_READ(SPLL_CTL);
2444 }
2445
2446 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2447                                        struct intel_shared_dpll *pll,
2448                                        struct intel_dpll_hw_state *hw_state)
2449 {
2450         uint32_t val;
2451
2452         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2453                 return false;
2454
2455         val = I915_READ(WRPLL_CTL(pll->id));
2456         hw_state->wrpll = val;
2457
2458         return val & WRPLL_PLL_ENABLE;
2459 }
2460
2461 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2462                                       struct intel_shared_dpll *pll,
2463                                       struct intel_dpll_hw_state *hw_state)
2464 {
2465         uint32_t val;
2466
2467         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2468                 return false;
2469
2470         val = I915_READ(SPLL_CTL);
2471         hw_state->spll = val;
2472
2473         return val & SPLL_PLL_ENABLE;
2474 }
2475
2476
2477 static const char * const hsw_ddi_pll_names[] = {
2478         "WRPLL 1",
2479         "WRPLL 2",
2480         "SPLL"
2481 };
2482
2483 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2484 {
2485         int i;
2486
2487         dev_priv->num_shared_dpll = 3;
2488
2489         for (i = 0; i < 2; i++) {
2490                 dev_priv->shared_dplls[i].id = i;
2491                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2492                 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2493                 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
2494                 dev_priv->shared_dplls[i].get_hw_state =
2495                         hsw_ddi_wrpll_get_hw_state;
2496         }
2497
2498         /* SPLL is special, but needs to be initialized anyway.. */
2499         dev_priv->shared_dplls[i].id = i;
2500         dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2501         dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2502         dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2503         dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2504
2505 }
2506
2507 static const char * const skl_ddi_pll_names[] = {
2508         "DPLL 1",
2509         "DPLL 2",
2510         "DPLL 3",
2511 };
2512
2513 struct skl_dpll_regs {
2514         i915_reg_t ctl, cfgcr1, cfgcr2;
2515 };
2516
2517 /* this array is indexed by the *shared* pll id */
2518 static const struct skl_dpll_regs skl_dpll_regs[3] = {
2519         {
2520                 /* DPLL 1 */
2521                 .ctl = LCPLL2_CTL,
2522                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2523                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
2524         },
2525         {
2526                 /* DPLL 2 */
2527                 .ctl = WRPLL_CTL(0),
2528                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2529                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
2530         },
2531         {
2532                 /* DPLL 3 */
2533                 .ctl = WRPLL_CTL(1),
2534                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2535                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
2536         },
2537 };
2538
2539 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2540                                struct intel_shared_dpll *pll)
2541 {
2542         uint32_t val;
2543         unsigned int dpll;
2544         const struct skl_dpll_regs *regs = skl_dpll_regs;
2545
2546         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2547         dpll = pll->id + 1;
2548
2549         val = I915_READ(DPLL_CTRL1);
2550
2551         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2552                  DPLL_CTRL1_LINK_RATE_MASK(dpll));
2553         val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2554
2555         I915_WRITE(DPLL_CTRL1, val);
2556         POSTING_READ(DPLL_CTRL1);
2557
2558         I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2559         I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2560         POSTING_READ(regs[pll->id].cfgcr1);
2561         POSTING_READ(regs[pll->id].cfgcr2);
2562
2563         /* the enable bit is always bit 31 */
2564         I915_WRITE(regs[pll->id].ctl,
2565                    I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2566
2567         if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2568                 DRM_ERROR("DPLL %d not locked\n", dpll);
2569 }
2570
2571 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2572                                 struct intel_shared_dpll *pll)
2573 {
2574         const struct skl_dpll_regs *regs = skl_dpll_regs;
2575
2576         /* the enable bit is always bit 31 */
2577         I915_WRITE(regs[pll->id].ctl,
2578                    I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2579         POSTING_READ(regs[pll->id].ctl);
2580 }
2581
2582 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2583                                      struct intel_shared_dpll *pll,
2584                                      struct intel_dpll_hw_state *hw_state)
2585 {
2586         uint32_t val;
2587         unsigned int dpll;
2588         const struct skl_dpll_regs *regs = skl_dpll_regs;
2589
2590         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2591                 return false;
2592
2593         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2594         dpll = pll->id + 1;
2595
2596         val = I915_READ(regs[pll->id].ctl);
2597         if (!(val & LCPLL_PLL_ENABLE))
2598                 return false;
2599
2600         val = I915_READ(DPLL_CTRL1);
2601         hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2602
2603         /* avoid reading back stale values if HDMI mode is not enabled */
2604         if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2605                 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2606                 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2607         }
2608
2609         return true;
2610 }
2611
2612 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2613 {
2614         int i;
2615
2616         dev_priv->num_shared_dpll = 3;
2617
2618         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2619                 dev_priv->shared_dplls[i].id = i;
2620                 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2621                 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2622                 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2623                 dev_priv->shared_dplls[i].get_hw_state =
2624                         skl_ddi_pll_get_hw_state;
2625         }
2626 }
2627
2628 static void broxton_phy_init(struct drm_i915_private *dev_priv,
2629                              enum dpio_phy phy)
2630 {
2631         enum port port;
2632         uint32_t val;
2633
2634         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2635         val |= GT_DISPLAY_POWER_ON(phy);
2636         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2637
2638         /* Considering 10ms timeout until BSpec is updated */
2639         if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2640                 DRM_ERROR("timeout during PHY%d power on\n", phy);
2641
2642         for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2643              port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2644                 int lane;
2645
2646                 for (lane = 0; lane < 4; lane++) {
2647                         val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2648                         /*
2649                          * Note that on CHV this flag is called UPAR, but has
2650                          * the same function.
2651                          */
2652                         val &= ~LATENCY_OPTIM;
2653                         if (lane != 1)
2654                                 val |= LATENCY_OPTIM;
2655
2656                         I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2657                 }
2658         }
2659
2660         /* Program PLL Rcomp code offset */
2661         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2662         val &= ~IREF0RC_OFFSET_MASK;
2663         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2664         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2665
2666         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2667         val &= ~IREF1RC_OFFSET_MASK;
2668         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2669         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2670
2671         /* Program power gating */
2672         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2673         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2674                 SUS_CLK_CONFIG;
2675         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2676
2677         if (phy == DPIO_PHY0) {
2678                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2679                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2680                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2681         }
2682
2683         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2684         val &= ~OCL2_LDOFUSE_PWR_DIS;
2685         /*
2686          * On PHY1 disable power on the second channel, since no port is
2687          * connected there. On PHY0 both channels have a port, so leave it
2688          * enabled.
2689          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2690          * power down the second channel on PHY0 as well.
2691          */
2692         if (phy == DPIO_PHY1)
2693                 val |= OCL2_LDOFUSE_PWR_DIS;
2694         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2695
2696         if (phy == DPIO_PHY0) {
2697                 uint32_t grc_code;
2698                 /*
2699                  * PHY0 isn't connected to an RCOMP resistor so copy over
2700                  * the corresponding calibrated value from PHY1, and disable
2701                  * the automatic calibration on PHY0.
2702                  */
2703                 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2704                              10))
2705                         DRM_ERROR("timeout waiting for PHY1 GRC\n");
2706
2707                 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2708                 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2709                 grc_code = val << GRC_CODE_FAST_SHIFT |
2710                            val << GRC_CODE_SLOW_SHIFT |
2711                            val;
2712                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2713
2714                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2715                 val |= GRC_DIS | GRC_RDY_OVRD;
2716                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2717         }
2718
2719         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2720         val |= COMMON_RESET_DIS;
2721         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2722 }
2723
2724 void broxton_ddi_phy_init(struct drm_device *dev)
2725 {
2726         /* Enable PHY1 first since it provides Rcomp for PHY0 */
2727         broxton_phy_init(dev->dev_private, DPIO_PHY1);
2728         broxton_phy_init(dev->dev_private, DPIO_PHY0);
2729 }
2730
2731 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2732                                enum dpio_phy phy)
2733 {
2734         uint32_t val;
2735
2736         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2737         val &= ~COMMON_RESET_DIS;
2738         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2739 }
2740
2741 void broxton_ddi_phy_uninit(struct drm_device *dev)
2742 {
2743         struct drm_i915_private *dev_priv = dev->dev_private;
2744
2745         broxton_phy_uninit(dev_priv, DPIO_PHY1);
2746         broxton_phy_uninit(dev_priv, DPIO_PHY0);
2747
2748         /* FIXME: do this in broxton_phy_uninit per phy */
2749         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2750 }
2751
2752 static const char * const bxt_ddi_pll_names[] = {
2753         "PORT PLL A",
2754         "PORT PLL B",
2755         "PORT PLL C",
2756 };
2757
2758 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2759                                 struct intel_shared_dpll *pll)
2760 {
2761         uint32_t temp;
2762         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2763
2764         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2765         temp &= ~PORT_PLL_REF_SEL;
2766         /* Non-SSC reference */
2767         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2768
2769         /* Disable 10 bit clock */
2770         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2771         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2772         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2773
2774         /* Write P1 & P2 */
2775         temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2776         temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2777         temp |= pll->config.hw_state.ebb0;
2778         I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2779
2780         /* Write M2 integer */
2781         temp = I915_READ(BXT_PORT_PLL(port, 0));
2782         temp &= ~PORT_PLL_M2_MASK;
2783         temp |= pll->config.hw_state.pll0;
2784         I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2785
2786         /* Write N */
2787         temp = I915_READ(BXT_PORT_PLL(port, 1));
2788         temp &= ~PORT_PLL_N_MASK;
2789         temp |= pll->config.hw_state.pll1;
2790         I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2791
2792         /* Write M2 fraction */
2793         temp = I915_READ(BXT_PORT_PLL(port, 2));
2794         temp &= ~PORT_PLL_M2_FRAC_MASK;
2795         temp |= pll->config.hw_state.pll2;
2796         I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2797
2798         /* Write M2 fraction enable */
2799         temp = I915_READ(BXT_PORT_PLL(port, 3));
2800         temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2801         temp |= pll->config.hw_state.pll3;
2802         I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2803
2804         /* Write coeff */
2805         temp = I915_READ(BXT_PORT_PLL(port, 6));
2806         temp &= ~PORT_PLL_PROP_COEFF_MASK;
2807         temp &= ~PORT_PLL_INT_COEFF_MASK;
2808         temp &= ~PORT_PLL_GAIN_CTL_MASK;
2809         temp |= pll->config.hw_state.pll6;
2810         I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2811
2812         /* Write calibration val */
2813         temp = I915_READ(BXT_PORT_PLL(port, 8));
2814         temp &= ~PORT_PLL_TARGET_CNT_MASK;
2815         temp |= pll->config.hw_state.pll8;
2816         I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2817
2818         temp = I915_READ(BXT_PORT_PLL(port, 9));
2819         temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2820         temp |= pll->config.hw_state.pll9;
2821         I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2822
2823         temp = I915_READ(BXT_PORT_PLL(port, 10));
2824         temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2825         temp &= ~PORT_PLL_DCO_AMP_MASK;
2826         temp |= pll->config.hw_state.pll10;
2827         I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2828
2829         /* Recalibrate with new settings */
2830         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2831         temp |= PORT_PLL_RECALIBRATE;
2832         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2833         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2834         temp |= pll->config.hw_state.ebb4;
2835         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2836
2837         /* Enable PLL */
2838         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2839         temp |= PORT_PLL_ENABLE;
2840         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2841         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2842
2843         if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2844                         PORT_PLL_LOCK), 200))
2845                 DRM_ERROR("PLL %d not locked\n", port);
2846
2847         /*
2848          * While we write to the group register to program all lanes at once we
2849          * can read only lane registers and we pick lanes 0/1 for that.
2850          */
2851         temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2852         temp &= ~LANE_STAGGER_MASK;
2853         temp &= ~LANESTAGGER_STRAP_OVRD;
2854         temp |= pll->config.hw_state.pcsdw12;
2855         I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2856 }
2857
2858 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2859                                         struct intel_shared_dpll *pll)
2860 {
2861         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2862         uint32_t temp;
2863
2864         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2865         temp &= ~PORT_PLL_ENABLE;
2866         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2867         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2868 }
2869
2870 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2871                                         struct intel_shared_dpll *pll,
2872                                         struct intel_dpll_hw_state *hw_state)
2873 {
2874         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2875         uint32_t val;
2876
2877         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2878                 return false;
2879
2880         val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2881         if (!(val & PORT_PLL_ENABLE))
2882                 return false;
2883
2884         hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2885         hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2886
2887         hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2888         hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2889
2890         hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2891         hw_state->pll0 &= PORT_PLL_M2_MASK;
2892
2893         hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2894         hw_state->pll1 &= PORT_PLL_N_MASK;
2895
2896         hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2897         hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2898
2899         hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2900         hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2901
2902         hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2903         hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2904                           PORT_PLL_INT_COEFF_MASK |
2905                           PORT_PLL_GAIN_CTL_MASK;
2906
2907         hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2908         hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2909
2910         hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2911         hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2912
2913         hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2914         hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2915                            PORT_PLL_DCO_AMP_MASK;
2916
2917         /*
2918          * While we write to the group register to program all lanes at once we
2919          * can read only lane registers. We configure all lanes the same way, so
2920          * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2921          */
2922         hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2923         if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
2924                 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2925                                  hw_state->pcsdw12,
2926                                  I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2927         hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2928
2929         return true;
2930 }
2931
2932 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2933 {
2934         int i;
2935
2936         dev_priv->num_shared_dpll = 3;
2937
2938         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2939                 dev_priv->shared_dplls[i].id = i;
2940                 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2941                 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2942                 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2943                 dev_priv->shared_dplls[i].get_hw_state =
2944                         bxt_ddi_pll_get_hw_state;
2945         }
2946 }
2947
2948 void intel_ddi_pll_init(struct drm_device *dev)
2949 {
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951         uint32_t val = I915_READ(LCPLL_CTL);
2952
2953         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2954                 skl_shared_dplls_init(dev_priv);
2955         else if (IS_BROXTON(dev))
2956                 bxt_shared_dplls_init(dev_priv);
2957         else
2958                 hsw_shared_dplls_init(dev_priv);
2959
2960         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2961                 int cdclk_freq;
2962
2963                 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2964                 dev_priv->skl_boot_cdclk = cdclk_freq;
2965                 if (skl_sanitize_cdclk(dev_priv))
2966                         DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
2967                 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2968                         DRM_ERROR("LCPLL1 is disabled\n");
2969         } else if (IS_BROXTON(dev)) {
2970                 broxton_init_cdclk(dev);
2971                 broxton_ddi_phy_init(dev);
2972         } else {
2973                 /*
2974                  * The LCPLL register should be turned on by the BIOS. For now
2975                  * let's just check its state and print errors in case
2976                  * something is wrong.  Don't even try to turn it on.
2977                  */
2978
2979                 if (val & LCPLL_CD_SOURCE_FCLK)
2980                         DRM_ERROR("CDCLK source is not LCPLL\n");
2981
2982                 if (val & LCPLL_PLL_DISABLE)
2983                         DRM_ERROR("LCPLL is disabled\n");
2984         }
2985 }
2986
2987 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2988 {
2989         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2990         struct drm_i915_private *dev_priv =
2991                 to_i915(intel_dig_port->base.base.dev);
2992         enum port port = intel_dig_port->port;
2993         uint32_t val;
2994         bool wait = false;
2995
2996         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2997                 val = I915_READ(DDI_BUF_CTL(port));
2998                 if (val & DDI_BUF_CTL_ENABLE) {
2999                         val &= ~DDI_BUF_CTL_ENABLE;
3000                         I915_WRITE(DDI_BUF_CTL(port), val);
3001                         wait = true;
3002                 }
3003
3004                 val = I915_READ(DP_TP_CTL(port));
3005                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3006                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3007                 I915_WRITE(DP_TP_CTL(port), val);
3008                 POSTING_READ(DP_TP_CTL(port));
3009
3010                 if (wait)
3011                         intel_wait_ddi_buf_idle(dev_priv, port);
3012         }
3013
3014         val = DP_TP_CTL_ENABLE |
3015               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3016         if (intel_dp->is_mst)
3017                 val |= DP_TP_CTL_MODE_MST;
3018         else {
3019                 val |= DP_TP_CTL_MODE_SST;
3020                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3021                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3022         }
3023         I915_WRITE(DP_TP_CTL(port), val);
3024         POSTING_READ(DP_TP_CTL(port));
3025
3026         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3027         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3028         POSTING_READ(DDI_BUF_CTL(port));
3029
3030         udelay(600);
3031 }
3032
3033 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3034 {
3035         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3036         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3037         uint32_t val;
3038
3039         intel_ddi_post_disable(intel_encoder);
3040
3041         val = I915_READ(FDI_RX_CTL(PIPE_A));
3042         val &= ~FDI_RX_ENABLE;
3043         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3044
3045         val = I915_READ(FDI_RX_MISC(PIPE_A));
3046         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3047         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3048         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3049
3050         val = I915_READ(FDI_RX_CTL(PIPE_A));
3051         val &= ~FDI_PCDCLK;
3052         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3053
3054         val = I915_READ(FDI_RX_CTL(PIPE_A));
3055         val &= ~FDI_RX_PLL_ENABLE;
3056         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3057 }
3058
3059 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3060                                  struct intel_crtc *intel_crtc)
3061 {
3062         u32 temp;
3063
3064         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3065                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3066                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3067                         return true;
3068         }
3069         return false;
3070 }
3071
3072 void intel_ddi_get_config(struct intel_encoder *encoder,
3073                           struct intel_crtc_state *pipe_config)
3074 {
3075         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3076         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
3077         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3078         struct intel_hdmi *intel_hdmi;
3079         u32 temp, flags = 0;
3080
3081         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3082         if (temp & TRANS_DDI_PHSYNC)
3083                 flags |= DRM_MODE_FLAG_PHSYNC;
3084         else
3085                 flags |= DRM_MODE_FLAG_NHSYNC;
3086         if (temp & TRANS_DDI_PVSYNC)
3087                 flags |= DRM_MODE_FLAG_PVSYNC;
3088         else
3089                 flags |= DRM_MODE_FLAG_NVSYNC;
3090
3091         pipe_config->base.adjusted_mode.flags |= flags;
3092
3093         switch (temp & TRANS_DDI_BPC_MASK) {
3094         case TRANS_DDI_BPC_6:
3095                 pipe_config->pipe_bpp = 18;
3096                 break;
3097         case TRANS_DDI_BPC_8:
3098                 pipe_config->pipe_bpp = 24;
3099                 break;
3100         case TRANS_DDI_BPC_10:
3101                 pipe_config->pipe_bpp = 30;
3102                 break;
3103         case TRANS_DDI_BPC_12:
3104                 pipe_config->pipe_bpp = 36;
3105                 break;
3106         default:
3107                 break;
3108         }
3109
3110         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3111         case TRANS_DDI_MODE_SELECT_HDMI:
3112                 pipe_config->has_hdmi_sink = true;
3113                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3114
3115                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
3116                         pipe_config->has_infoframe = true;
3117                 break;
3118         case TRANS_DDI_MODE_SELECT_DVI:
3119         case TRANS_DDI_MODE_SELECT_FDI:
3120                 break;
3121         case TRANS_DDI_MODE_SELECT_DP_SST:
3122         case TRANS_DDI_MODE_SELECT_DP_MST:
3123                 pipe_config->has_dp_encoder = true;
3124                 pipe_config->lane_count =
3125                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3126                 intel_dp_get_m_n(intel_crtc, pipe_config);
3127                 break;
3128         default:
3129                 break;
3130         }
3131
3132         pipe_config->has_audio =
3133                 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
3134
3135         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3136             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3137                 /*
3138                  * This is a big fat ugly hack.
3139                  *
3140                  * Some machines in UEFI boot mode provide us a VBT that has 18
3141                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3142                  * unknown we fail to light up. Yet the same BIOS boots up with
3143                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3144                  * max, not what it tells us to use.
3145                  *
3146                  * Note: This will still be broken if the eDP panel is not lit
3147                  * up by the BIOS, and thus we can't get the mode at module
3148                  * load.
3149                  */
3150                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3151                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3152                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3153         }
3154
3155         intel_ddi_clock_get(encoder, pipe_config);
3156 }
3157
3158 static void intel_ddi_destroy(struct drm_encoder *encoder)
3159 {
3160         /* HDMI has nothing special to destroy, so we can go with this. */
3161         intel_dp_encoder_destroy(encoder);
3162 }
3163
3164 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3165                                      struct intel_crtc_state *pipe_config)
3166 {
3167         int type = encoder->type;
3168         int port = intel_ddi_get_encoder_port(encoder);
3169
3170         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3171
3172         if (port == PORT_A)
3173                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3174
3175         if (type == INTEL_OUTPUT_HDMI)
3176                 return intel_hdmi_compute_config(encoder, pipe_config);
3177         else
3178                 return intel_dp_compute_config(encoder, pipe_config);
3179 }
3180
3181 static const struct drm_encoder_funcs intel_ddi_funcs = {
3182         .destroy = intel_ddi_destroy,
3183 };
3184
3185 static struct intel_connector *
3186 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3187 {
3188         struct intel_connector *connector;
3189         enum port port = intel_dig_port->port;
3190
3191         connector = intel_connector_alloc();
3192         if (!connector)
3193                 return NULL;
3194
3195         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3196         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3197                 kfree(connector);
3198                 return NULL;
3199         }
3200
3201         return connector;
3202 }
3203
3204 static struct intel_connector *
3205 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3206 {
3207         struct intel_connector *connector;
3208         enum port port = intel_dig_port->port;
3209
3210         connector = intel_connector_alloc();
3211         if (!connector)
3212                 return NULL;
3213
3214         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3215         intel_hdmi_init_connector(intel_dig_port, connector);
3216
3217         return connector;
3218 }
3219
3220 void intel_ddi_init(struct drm_device *dev, enum port port)
3221 {
3222         struct drm_i915_private *dev_priv = dev->dev_private;
3223         struct intel_digital_port *intel_dig_port;
3224         struct intel_encoder *intel_encoder;
3225         struct drm_encoder *encoder;
3226         bool init_hdmi, init_dp;
3227         int max_lanes;
3228
3229         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
3230                 switch (port) {
3231                 case PORT_A:
3232                         max_lanes = 4;
3233                         break;
3234                 case PORT_E:
3235                         max_lanes = 0;
3236                         break;
3237                 default:
3238                         max_lanes = 4;
3239                         break;
3240                 }
3241         } else {
3242                 switch (port) {
3243                 case PORT_A:
3244                         max_lanes = 2;
3245                         break;
3246                 case PORT_E:
3247                         max_lanes = 2;
3248                         break;
3249                 default:
3250                         max_lanes = 4;
3251                         break;
3252                 }
3253         }
3254
3255         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3256                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3257         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3258         if (!init_dp && !init_hdmi) {
3259                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3260                               port_name(port));
3261                 return;
3262         }
3263
3264         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3265         if (!intel_dig_port)
3266                 return;
3267
3268         intel_encoder = &intel_dig_port->base;
3269         encoder = &intel_encoder->base;
3270
3271         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3272                          DRM_MODE_ENCODER_TMDS, NULL);
3273
3274         intel_encoder->compute_config = intel_ddi_compute_config;
3275         intel_encoder->enable = intel_enable_ddi;
3276         intel_encoder->pre_enable = intel_ddi_pre_enable;
3277         intel_encoder->disable = intel_disable_ddi;
3278         intel_encoder->post_disable = intel_ddi_post_disable;
3279         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3280         intel_encoder->get_config = intel_ddi_get_config;
3281
3282         intel_dig_port->port = port;
3283         dev_priv->dig_port_map[port] = intel_encoder;
3284         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3285                                           (DDI_BUF_PORT_REVERSAL |
3286                                            DDI_A_4_LANES);
3287
3288         /*
3289          * Bspec says that DDI_A_4_LANES is the only supported configuration
3290          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
3291          * wasn't lit up at boot.  Force this bit on in our internal
3292          * configuration so that we use the proper lane count for our
3293          * calculations.
3294          */
3295         if (IS_BROXTON(dev) && port == PORT_A) {
3296                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3297                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3298                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
3299                         max_lanes = 4;
3300                 }
3301         }
3302
3303         intel_dig_port->max_lanes = max_lanes;
3304
3305         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
3306         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3307         intel_encoder->cloneable = 0;
3308
3309         if (init_dp) {
3310                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3311                         goto err;
3312
3313                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3314                 /*
3315                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3316                  * interrupts to check the external panel connection.
3317                  */
3318                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
3319                         dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3320                 else
3321                         dev_priv->hotplug.irq_port[port] = intel_dig_port;
3322         }
3323
3324         /* In theory we don't need the encoder->type check, but leave it just in
3325          * case we have some really bad VBTs... */
3326         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3327                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3328                         goto err;
3329         }
3330
3331         return;
3332
3333 err:
3334         drm_encoder_cleanup(encoder);
3335         kfree(intel_dig_port);
3336 }