drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,         /* DP parameters */
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45         0x00FFFFFF, 0x00040006          /* HDMI parameters */
  46 };
  47
  48 static const u32 hsw_ddi_translations_fdi[] = {
  49         0x00FFFFFF, 0x0007000E,         /* FDI parameters */
  50         0x00D75FFF, 0x000F000A,
  51         0x00C30FFF, 0x00060006,
  52         0x00AAAFFF, 0x001E0000,
  53         0x00FFFFFF, 0x000F000A,
  54         0x00D75FFF, 0x00160004,
  55         0x00C30FFF, 0x001E0000,
  56         0x00FFFFFF, 0x00060006,
  57         0x00D75FFF, 0x001E0000,
  58         0x00FFFFFF, 0x00040006          /* HDMI parameters */
  59 };
  60
  61 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
  62 {
  63         struct drm_encoder *encoder = &intel_encoder->base;
  64         int type = intel_encoder->type;
  65
  66         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
  67             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
  68                 struct intel_digital_port *intel_dig_port =
  69                         enc_to_dig_port(encoder);
  70                 return intel_dig_port->port;
  71
  72         } else if (type == INTEL_OUTPUT_ANALOG) {
  73                 return PORT_E;
  74
  75         } else {
  76                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
  77                 BUG();
  78         }
  79 }
  80
  81 /* On Haswell, DDI port buffers must be programmed with correct values
  82  * in advance. The buffer values are different for FDI and DP modes,
  83  * but the HDMI/DVI fields are shared among those. So we program the DDI
  84  * in either FDI or DP modes only, as HDMI connections will work with both
  85  * of those
  86  */
  87 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
  88                                       bool use_fdi_mode)
  89 {
  90         struct drm_i915_private *dev_priv = dev->dev_private;
  91         u32 reg;
  92         int i;
  93         const u32 *ddi_translations = ((use_fdi_mode) ?
  94                 hsw_ddi_translations_fdi :
  95                 hsw_ddi_translations_dp);
  96
  97         DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
  98                         port_name(port),
  99                         use_fdi_mode ? "FDI" : "DP");
 100
 101         WARN((use_fdi_mode && (port != PORT_E)),
 102                 "Programming port %c in FDI mode, this probably will not work.\n",
 103                 port_name(port));
 104
 105         for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 106                 I915_WRITE(reg, ddi_translations[i]);
 107                 reg += 4;
 108         }
 109 }
 110
 111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 112  * mode and port E for FDI.
 113  */
 114 void intel_prepare_ddi(struct drm_device *dev)
 115 {
 116         int port;
 117
 118         if (!HAS_DDI(dev))
 119                 return;
 120
 121         for (port = PORT_A; port < PORT_E; port++)
 122                 intel_prepare_ddi_buffers(dev, port, false);
 123
 124         /* DDI E is the suggested one to work in FDI mode, so program is as such
 125          * by default. It will have to be re-programmed in case a digital DP
 126          * output will be detected on it
 127          */
 128         intel_prepare_ddi_buffers(dev, PORT_E, true);
 129 }
 130
 131 static const long hsw_ddi_buf_ctl_values[] = {
 132         DDI_BUF_EMP_400MV_0DB_HSW,
 133         DDI_BUF_EMP_400MV_3_5DB_HSW,
 134         DDI_BUF_EMP_400MV_6DB_HSW,
 135         DDI_BUF_EMP_400MV_9_5DB_HSW,
 136         DDI_BUF_EMP_600MV_0DB_HSW,
 137         DDI_BUF_EMP_600MV_3_5DB_HSW,
 138         DDI_BUF_EMP_600MV_6DB_HSW,
 139         DDI_BUF_EMP_800MV_0DB_HSW,
 140         DDI_BUF_EMP_800MV_3_5DB_HSW
 141 };
 142
 143 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 144                                     enum port port)
 145 {
 146         uint32_t reg = DDI_BUF_CTL(port);
 147         int i;
 148
 149         for (i = 0; i < 8; i++) {
 150                 udelay(1);
 151                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 152                         return;
 153         }
 154         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 155 }
 156
 157 /* Starting with Haswell, different DDI ports can work in FDI mode for
 158  * connection to the PCH-located connectors. For this, it is necessary to train
 159  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 160  *
 161  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 162  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 163  * DDI A (which is used for eDP)
 164  */
 165
 166 void hsw_fdi_link_train(struct drm_crtc *crtc)
 167 {
 168         struct drm_device *dev = crtc->dev;
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 171         u32 temp, i, rx_ctl_val;
 172
 173         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 174          * mode set "sequence for CRT port" document:
 175          * - TP1 to TP2 time with the default value
 176          * - FDI delay to 90h
 177          */
 178         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 179                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 180                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 181
 182         /* Enable the PCH Receiver FDI PLL */
 183         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 184                      FDI_RX_PLL_ENABLE |
 185                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 186         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 187         POSTING_READ(_FDI_RXA_CTL);
 188         udelay(220);
 189
 190         /* Switch from Rawclk to PCDclk */
 191         rx_ctl_val |= FDI_PCDCLK;
 192         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 193
 194         /* Configure Port Clock Select */
 195         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
 196
 197         /* Start the training iterating through available voltages and emphasis,
 198          * testing each value twice. */
 199         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 200                 /* Configure DP_TP_CTL with auto-training */
 201                 I915_WRITE(DP_TP_CTL(PORT_E),
 202                                         DP_TP_CTL_FDI_AUTOTRAIN |
 203                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 204                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 205                                         DP_TP_CTL_ENABLE);
 206
 207                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 208                  * DDI E does not support port reversal, the functionality is
 209                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 210                  * port reversal bit */
 211                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 212                            DDI_BUF_CTL_ENABLE |
 213                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 214                            hsw_ddi_buf_ctl_values[i / 2]);
 215                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 216
 217                 udelay(600);
 218
 219                 /* Program PCH FDI Receiver TU */
 220                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 221
 222                 /* Enable PCH FDI Receiver with auto-training */
 223                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 224                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 225                 POSTING_READ(_FDI_RXA_CTL);
 226
 227                 /* Wait for FDI receiver lane calibration */
 228                 udelay(30);
 229
 230                 /* Unset FDI_RX_MISC pwrdn lanes */
 231                 temp = I915_READ(_FDI_RXA_MISC);
 232                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 233                 I915_WRITE(_FDI_RXA_MISC, temp);
 234                 POSTING_READ(_FDI_RXA_MISC);
 235
 236                 /* Wait for FDI auto training time */
 237                 udelay(5);
 238
 239                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 240                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 241                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 242
 243                         /* Enable normal pixel sending for FDI */
 244                         I915_WRITE(DP_TP_CTL(PORT_E),
 245                                    DP_TP_CTL_FDI_AUTOTRAIN |
 246                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 247                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 248                                    DP_TP_CTL_ENABLE);
 249
 250                         return;
 251                 }
 252
 253                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 254                 temp &= ~DDI_BUF_CTL_ENABLE;
 255                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 256                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 257
 258                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 259                 temp = I915_READ(DP_TP_CTL(PORT_E));
 260                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 261                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 262                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 263                 POSTING_READ(DP_TP_CTL(PORT_E));
 264
 265                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 266
 267                 rx_ctl_val &= ~FDI_RX_ENABLE;
 268                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 269                 POSTING_READ(_FDI_RXA_CTL);
 270
 271                 /* Reset FDI_RX_MISC pwrdn lanes */
 272                 temp = I915_READ(_FDI_RXA_MISC);
 273                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 274                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 275                 I915_WRITE(_FDI_RXA_MISC, temp);
 276                 POSTING_READ(_FDI_RXA_MISC);
 277         }
 278
 279         DRM_ERROR("FDI link training failed!\n");
 280 }
 281
 282 /* WRPLL clock dividers */
 283 struct wrpll_tmds_clock {
 284         u32 clock;
 285         u16 p;          /* Post divider */
 286         u16 n2;         /* Feedback divider */
 287         u16 r2;         /* Reference divider */
 288 };
 289
 290 /* Table of matching values for WRPLL clocks programming for each frequency.
 291  * The code assumes this table is sorted. */
 292 static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
 293         {19750, 38,     25,     18},
 294         {20000, 48,     32,     18},
 295         {21000, 36,     21,     15},
 296         {21912, 42,     29,     17},
 297         {22000, 36,     22,     15},
 298         {23000, 36,     23,     15},
 299         {23500, 40,     40,     23},
 300         {23750, 26,     16,     14},
 301         {24000, 36,     24,     15},
 302         {25000, 36,     25,     15},
 303         {25175, 26,     40,     33},
 304         {25200, 30,     21,     15},
 305         {26000, 36,     26,     15},
 306         {27000, 30,     21,     14},
 307         {27027, 18,     100,    111},
 308         {27500, 30,     29,     19},
 309         {28000, 34,     30,     17},
 310         {28320, 26,     30,     22},
 311         {28322, 32,     42,     25},
 312         {28750, 24,     23,     18},
 313         {29000, 30,     29,     18},
 314         {29750, 32,     30,     17},
 315         {30000, 30,     25,     15},
 316         {30750, 30,     41,     24},
 317         {31000, 30,     31,     18},
 318         {31500, 30,     28,     16},
 319         {32000, 30,     32,     18},
 320         {32500, 28,     32,     19},
 321         {33000, 24,     22,     15},
 322         {34000, 28,     30,     17},
 323         {35000, 26,     32,     19},
 324         {35500, 24,     30,     19},
 325         {36000, 26,     26,     15},
 326         {36750, 26,     46,     26},
 327         {37000, 24,     23,     14},
 328         {37762, 22,     40,     26},
 329         {37800, 20,     21,     15},
 330         {38000, 24,     27,     16},
 331         {38250, 24,     34,     20},
 332         {39000, 24,     26,     15},
 333         {40000, 24,     32,     18},
 334         {40500, 20,     21,     14},
 335         {40541, 22,     147,    89},
 336         {40750, 18,     19,     14},
 337         {41000, 16,     17,     14},
 338         {41500, 22,     44,     26},
 339         {41540, 22,     44,     26},
 340         {42000, 18,     21,     15},
 341         {42500, 22,     45,     26},
 342         {43000, 20,     43,     27},
 343         {43163, 20,     24,     15},
 344         {44000, 18,     22,     15},
 345         {44900, 20,     108,    65},
 346         {45000, 20,     25,     15},
 347         {45250, 20,     52,     31},
 348         {46000, 18,     23,     15},
 349         {46750, 20,     45,     26},
 350         {47000, 20,     40,     23},
 351         {48000, 18,     24,     15},
 352         {49000, 18,     49,     30},
 353         {49500, 16,     22,     15},
 354         {50000, 18,     25,     15},
 355         {50500, 18,     32,     19},
 356         {51000, 18,     34,     20},
 357         {52000, 18,     26,     15},
 358         {52406, 14,     34,     25},
 359         {53000, 16,     22,     14},
 360         {54000, 16,     24,     15},
 361         {54054, 16,     173,    108},
 362         {54500, 14,     24,     17},
 363         {55000, 12,     22,     18},
 364         {56000, 14,     45,     31},
 365         {56250, 16,     25,     15},
 366         {56750, 14,     25,     17},
 367         {57000, 16,     27,     16},
 368         {58000, 16,     43,     25},
 369         {58250, 16,     38,     22},
 370         {58750, 16,     40,     23},
 371         {59000, 14,     26,     17},
 372         {59341, 14,     40,     26},
 373         {59400, 16,     44,     25},
 374         {60000, 16,     32,     18},
 375         {60500, 12,     39,     29},
 376         {61000, 14,     49,     31},
 377         {62000, 14,     37,     23},
 378         {62250, 14,     42,     26},
 379         {63000, 12,     21,     15},
 380         {63500, 14,     28,     17},
 381         {64000, 12,     27,     19},
 382         {65000, 14,     32,     19},
 383         {65250, 12,     29,     20},
 384         {65500, 12,     32,     22},
 385         {66000, 12,     22,     15},
 386         {66667, 14,     38,     22},
 387         {66750, 10,     21,     17},
 388         {67000, 14,     33,     19},
 389         {67750, 14,     58,     33},
 390         {68000, 14,     30,     17},
 391         {68179, 14,     46,     26},
 392         {68250, 14,     46,     26},
 393         {69000, 12,     23,     15},
 394         {70000, 12,     28,     18},
 395         {71000, 12,     30,     19},
 396         {72000, 12,     24,     15},
 397         {73000, 10,     23,     17},
 398         {74000, 12,     23,     14},
 399         {74176, 8,      100,    91},
 400         {74250, 10,     22,     16},
 401         {74481, 12,     43,     26},
 402         {74500, 10,     29,     21},
 403         {75000, 12,     25,     15},
 404         {75250, 10,     39,     28},
 405         {76000, 12,     27,     16},
 406         {77000, 12,     53,     31},
 407         {78000, 12,     26,     15},
 408         {78750, 12,     28,     16},
 409         {79000, 10,     38,     26},
 410         {79500, 10,     28,     19},
 411         {80000, 12,     32,     18},
 412         {81000, 10,     21,     14},
 413         {81081, 6,      100,    111},
 414         {81624, 8,      29,     24},
 415         {82000, 8,      17,     14},
 416         {83000, 10,     40,     26},
 417         {83950, 10,     28,     18},
 418         {84000, 10,     28,     18},
 419         {84750, 6,      16,     17},
 420         {85000, 6,      17,     18},
 421         {85250, 10,     30,     19},
 422         {85750, 10,     27,     17},
 423         {86000, 10,     43,     27},
 424         {87000, 10,     29,     18},
 425         {88000, 10,     44,     27},
 426         {88500, 10,     41,     25},
 427         {89000, 10,     28,     17},
 428         {89012, 6,      90,     91},
 429         {89100, 10,     33,     20},
 430         {90000, 10,     25,     15},
 431         {91000, 10,     32,     19},
 432         {92000, 10,     46,     27},
 433         {93000, 10,     31,     18},
 434         {94000, 10,     40,     23},
 435         {94500, 10,     28,     16},
 436         {95000, 10,     44,     25},
 437         {95654, 10,     39,     22},
 438         {95750, 10,     39,     22},
 439         {96000, 10,     32,     18},
 440         {97000, 8,      23,     16},
 441         {97750, 8,      42,     29},
 442         {98000, 8,      45,     31},
 443         {99000, 8,      22,     15},
 444         {99750, 8,      34,     23},
 445         {100000,        6,      20,     18},
 446         {100500,        6,      19,     17},
 447         {101000,        6,      37,     33},
 448         {101250,        8,      21,     14},
 449         {102000,        6,      17,     15},
 450         {102250,        6,      25,     22},
 451         {103000,        8,      29,     19},
 452         {104000,        8,      37,     24},
 453         {105000,        8,      28,     18},
 454         {106000,        8,      22,     14},
 455         {107000,        8,      46,     29},
 456         {107214,        8,      27,     17},
 457         {108000,        8,      24,     15},
 458         {108108,        8,      173,    108},
 459         {109000,        6,      23,     19},
 460         {110000,        6,      22,     18},
 461         {110013,        6,      22,     18},
 462         {110250,        8,      49,     30},
 463         {110500,        8,      36,     22},
 464         {111000,        8,      23,     14},
 465         {111264,        8,      150,    91},
 466         {111375,        8,      33,     20},
 467         {112000,        8,      63,     38},
 468         {112500,        8,      25,     15},
 469         {113100,        8,      57,     34},
 470         {113309,        8,      42,     25},
 471         {114000,        8,      27,     16},
 472         {115000,        6,      23,     18},
 473         {116000,        8,      43,     25},
 474         {117000,        8,      26,     15},
 475         {117500,        8,      40,     23},
 476         {118000,        6,      38,     29},
 477         {119000,        8,      30,     17},
 478         {119500,        8,      46,     26},
 479         {119651,        8,      39,     22},
 480         {120000,        8,      32,     18},
 481         {121000,        6,      39,     29},
 482         {121250,        6,      31,     23},
 483         {121750,        6,      23,     17},
 484         {122000,        6,      42,     31},
 485         {122614,        6,      30,     22},
 486         {123000,        6,      41,     30},
 487         {123379,        6,      37,     27},
 488         {124000,        6,      51,     37},
 489         {125000,        6,      25,     18},
 490         {125250,        4,      13,     14},
 491         {125750,        4,      27,     29},
 492         {126000,        6,      21,     15},
 493         {127000,        6,      24,     17},
 494         {127250,        6,      41,     29},
 495         {128000,        6,      27,     19},
 496         {129000,        6,      43,     30},
 497         {129859,        4,      25,     26},
 498         {130000,        6,      26,     18},
 499         {130250,        6,      42,     29},
 500         {131000,        6,      32,     22},
 501         {131500,        6,      38,     26},
 502         {131850,        6,      41,     28},
 503         {132000,        6,      22,     15},
 504         {132750,        6,      28,     19},
 505         {133000,        6,      34,     23},
 506         {133330,        6,      37,     25},
 507         {134000,        6,      61,     41},
 508         {135000,        6,      21,     14},
 509         {135250,        6,      167,    111},
 510         {136000,        6,      62,     41},
 511         {137000,        6,      35,     23},
 512         {138000,        6,      23,     15},
 513         {138500,        6,      40,     26},
 514         {138750,        6,      37,     24},
 515         {139000,        6,      34,     22},
 516         {139050,        6,      34,     22},
 517         {139054,        6,      34,     22},
 518         {140000,        6,      28,     18},
 519         {141000,        6,      36,     23},
 520         {141500,        6,      22,     14},
 521         {142000,        6,      30,     19},
 522         {143000,        6,      27,     17},
 523         {143472,        4,      17,     16},
 524         {144000,        6,      24,     15},
 525         {145000,        6,      29,     18},
 526         {146000,        6,      47,     29},
 527         {146250,        6,      26,     16},
 528         {147000,        6,      49,     30},
 529         {147891,        6,      23,     14},
 530         {148000,        6,      23,     14},
 531         {148250,        6,      28,     17},
 532         {148352,        4,      100,    91},
 533         {148500,        6,      33,     20},
 534         {149000,        6,      48,     29},
 535         {150000,        6,      25,     15},
 536         {151000,        4,      19,     17},
 537         {152000,        6,      27,     16},
 538         {152280,        6,      44,     26},
 539         {153000,        6,      34,     20},
 540         {154000,        6,      53,     31},
 541         {155000,        6,      31,     18},
 542         {155250,        6,      50,     29},
 543         {155750,        6,      45,     26},
 544         {156000,        6,      26,     15},
 545         {157000,        6,      61,     35},
 546         {157500,        6,      28,     16},
 547         {158000,        6,      65,     37},
 548         {158250,        6,      44,     25},
 549         {159000,        6,      53,     30},
 550         {159500,        6,      39,     22},
 551         {160000,        6,      32,     18},
 552         {161000,        4,      31,     26},
 553         {162000,        4,      18,     15},
 554         {162162,        4,      131,    109},
 555         {162500,        4,      53,     44},
 556         {163000,        4,      29,     24},
 557         {164000,        4,      17,     14},
 558         {165000,        4,      22,     18},
 559         {166000,        4,      32,     26},
 560         {167000,        4,      26,     21},
 561         {168000,        4,      46,     37},
 562         {169000,        4,      104,    83},
 563         {169128,        4,      64,     51},
 564         {169500,        4,      39,     31},
 565         {170000,        4,      34,     27},
 566         {171000,        4,      19,     15},
 567         {172000,        4,      51,     40},
 568         {172750,        4,      32,     25},
 569         {172800,        4,      32,     25},
 570         {173000,        4,      41,     32},
 571         {174000,        4,      49,     38},
 572         {174787,        4,      22,     17},
 573         {175000,        4,      35,     27},
 574         {176000,        4,      30,     23},
 575         {177000,        4,      38,     29},
 576         {178000,        4,      29,     22},
 577         {178500,        4,      37,     28},
 578         {179000,        4,      53,     40},
 579         {179500,        4,      73,     55},
 580         {180000,        4,      20,     15},
 581         {181000,        4,      55,     41},
 582         {182000,        4,      31,     23},
 583         {183000,        4,      42,     31},
 584         {184000,        4,      30,     22},
 585         {184750,        4,      26,     19},
 586         {185000,        4,      37,     27},
 587         {186000,        4,      51,     37},
 588         {187000,        4,      36,     26},
 589         {188000,        4,      32,     23},
 590         {189000,        4,      21,     15},
 591         {190000,        4,      38,     27},
 592         {190960,        4,      41,     29},
 593         {191000,        4,      41,     29},
 594         {192000,        4,      27,     19},
 595         {192250,        4,      37,     26},
 596         {193000,        4,      20,     14},
 597         {193250,        4,      53,     37},
 598         {194000,        4,      23,     16},
 599         {194208,        4,      23,     16},
 600         {195000,        4,      26,     18},
 601         {196000,        4,      45,     31},
 602         {197000,        4,      35,     24},
 603         {197750,        4,      41,     28},
 604         {198000,        4,      22,     15},
 605         {198500,        4,      25,     17},
 606         {199000,        4,      28,     19},
 607         {200000,        4,      37,     25},
 608         {201000,        4,      61,     41},
 609         {202000,        4,      112,    75},
 610         {202500,        4,      21,     14},
 611         {203000,        4,      146,    97},
 612         {204000,        4,      62,     41},
 613         {204750,        4,      44,     29},
 614         {205000,        4,      38,     25},
 615         {206000,        4,      29,     19},
 616         {207000,        4,      23,     15},
 617         {207500,        4,      40,     26},
 618         {208000,        4,      37,     24},
 619         {208900,        4,      48,     31},
 620         {209000,        4,      48,     31},
 621         {209250,        4,      31,     20},
 622         {210000,        4,      28,     18},
 623         {211000,        4,      25,     16},
 624         {212000,        4,      22,     14},
 625         {213000,        4,      30,     19},
 626         {213750,        4,      38,     24},
 627         {214000,        4,      46,     29},
 628         {214750,        4,      35,     22},
 629         {215000,        4,      43,     27},
 630         {216000,        4,      24,     15},
 631         {217000,        4,      37,     23},
 632         {218000,        4,      42,     26},
 633         {218250,        4,      42,     26},
 634         {218750,        4,      34,     21},
 635         {219000,        4,      47,     29},
 636         {220000,        4,      44,     27},
 637         {220640,        4,      49,     30},
 638         {220750,        4,      36,     22},
 639         {221000,        4,      36,     22},
 640         {222000,        4,      23,     14},
 641         {222525,        4,      28,     17},
 642         {222750,        4,      33,     20},
 643         {227000,        4,      37,     22},
 644         {230250,        4,      29,     17},
 645         {233500,        4,      38,     22},
 646         {235000,        4,      40,     23},
 647         {238000,        4,      30,     17},
 648         {241500,        2,      17,     19},
 649         {245250,        2,      20,     22},
 650         {247750,        2,      22,     24},
 651         {253250,        2,      15,     16},
 652         {256250,        2,      18,     19},
 653         {262500,        2,      31,     32},
 654         {267250,        2,      66,     67},
 655         {268500,        2,      94,     95},
 656         {270000,        2,      14,     14},
 657         {272500,        2,      77,     76},
 658         {273750,        2,      57,     56},
 659         {280750,        2,      24,     23},
 660         {281250,        2,      23,     22},
 661         {286000,        2,      17,     16},
 662         {291750,        2,      26,     24},
 663         {296703,        2,      56,     51},
 664         {297000,        2,      22,     20},
 665         {298000,        2,      21,     19},
 666 };
 667
 668 static void intel_ddi_mode_set(struct drm_encoder *encoder,
 669                                struct drm_display_mode *mode,
 670                                struct drm_display_mode *adjusted_mode)
 671 {
 672         struct drm_crtc *crtc = encoder->crtc;
 673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 674         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 675         int port = intel_ddi_get_encoder_port(intel_encoder);
 676         int pipe = intel_crtc->pipe;
 677         int type = intel_encoder->type;
 678
 679         DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
 680                       port_name(port), pipe_name(pipe));
 681
 682         intel_crtc->eld_vld = false;
 683         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 684                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 685                 struct intel_digital_port *intel_dig_port =
 686                         enc_to_dig_port(encoder);
 687
 688                 intel_dp->DP = intel_dig_port->port_reversal |
 689                                DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
 690                 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 691
 692                 if (intel_dp->has_audio) {
 693                         DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
 694                                          pipe_name(intel_crtc->pipe));
 695
 696                         /* write eld */
 697                         DRM_DEBUG_DRIVER("DP audio: write eld information\n");
 698                         intel_write_eld(encoder, adjusted_mode);
 699                 }
 700
 701                 intel_dp_init_link_config(intel_dp);
 702
 703         } else if (type == INTEL_OUTPUT_HDMI) {
 704                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 705
 706                 if (intel_hdmi->has_audio) {
 707                         /* Proper support for digital audio needs a new logic
 708                          * and a new set of registers, so we leave it for future
 709                          * patch bombing.
 710                          */
 711                         DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
 712                                          pipe_name(intel_crtc->pipe));
 713
 714                         /* write eld */
 715                         DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
 716                         intel_write_eld(encoder, adjusted_mode);
 717                 }
 718
 719                 intel_hdmi->set_infoframes(encoder, adjusted_mode);
 720         }
 721 }
 722
 723 static struct intel_encoder *
 724 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 725 {
 726         struct drm_device *dev = crtc->dev;
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728         struct intel_encoder *intel_encoder, *ret = NULL;
 729         int num_encoders = 0;
 730
 731         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 732                 ret = intel_encoder;
 733                 num_encoders++;
 734         }
 735
 736         if (num_encoders != 1)
 737                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 738                      pipe_name(intel_crtc->pipe));
 739
 740         BUG_ON(ret == NULL);
 741         return ret;
 742 }
 743
 744 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 745 {
 746         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 747         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 749         uint32_t val;
 750
 751         switch (intel_crtc->ddi_pll_sel) {
 752         case PORT_CLK_SEL_SPLL:
 753                 plls->spll_refcount--;
 754                 if (plls->spll_refcount == 0) {
 755                         DRM_DEBUG_KMS("Disabling SPLL\n");
 756                         val = I915_READ(SPLL_CTL);
 757                         WARN_ON(!(val & SPLL_PLL_ENABLE));
 758                         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
 759                         POSTING_READ(SPLL_CTL);
 760                 }
 761                 break;
 762         case PORT_CLK_SEL_WRPLL1:
 763                 plls->wrpll1_refcount--;
 764                 if (plls->wrpll1_refcount == 0) {
 765                         DRM_DEBUG_KMS("Disabling WRPLL 1\n");
 766                         val = I915_READ(WRPLL_CTL1);
 767                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 768                         I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
 769                         POSTING_READ(WRPLL_CTL1);
 770                 }
 771                 break;
 772         case PORT_CLK_SEL_WRPLL2:
 773                 plls->wrpll2_refcount--;
 774                 if (plls->wrpll2_refcount == 0) {
 775                         DRM_DEBUG_KMS("Disabling WRPLL 2\n");
 776                         val = I915_READ(WRPLL_CTL2);
 777                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 778                         I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
 779                         POSTING_READ(WRPLL_CTL2);
 780                 }
 781                 break;
 782         }
 783
 784         WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
 785         WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 786         WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 787
 788         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
 789 }
 790
 791 static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
 792 {
 793         u32 i;
 794
 795         for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
 796                 if (clock <= wrpll_tmds_clock_table[i].clock)
 797                         break;
 798
 799         if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
 800                 i--;
 801
 802         *p = wrpll_tmds_clock_table[i].p;
 803         *n2 = wrpll_tmds_clock_table[i].n2;
 804         *r2 = wrpll_tmds_clock_table[i].r2;
 805
 806         if (wrpll_tmds_clock_table[i].clock != clock)
 807                 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
 808                          wrpll_tmds_clock_table[i].clock, clock);
 809
 810         DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
 811                       clock, *p, *n2, *r2);
 812 }
 813
 814 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
 815 {
 816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 817         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 818         struct drm_encoder *encoder = &intel_encoder->base;
 819         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 820         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 821         int type = intel_encoder->type;
 822         enum pipe pipe = intel_crtc->pipe;
 823         uint32_t reg, val;
 824
 825         /* TODO: reuse PLLs when possible (compare values) */
 826
 827         intel_ddi_put_crtc_pll(crtc);
 828
 829         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 830                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 831
 832                 switch (intel_dp->link_bw) {
 833                 case DP_LINK_BW_1_62:
 834                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 835                         break;
 836                 case DP_LINK_BW_2_7:
 837                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 838                         break;
 839                 case DP_LINK_BW_5_4:
 840                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 841                         break;
 842                 default:
 843                         DRM_ERROR("Link bandwidth %d unsupported\n",
 844                                   intel_dp->link_bw);
 845                         return false;
 846                 }
 847
 848                 /* We don't need to turn any PLL on because we'll use LCPLL. */
 849                 return true;
 850
 851         } else if (type == INTEL_OUTPUT_HDMI) {
 852                 int p, n2, r2;
 853
 854                 if (plls->wrpll1_refcount == 0) {
 855                         DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
 856                                       pipe_name(pipe));
 857                         plls->wrpll1_refcount++;
 858                         reg = WRPLL_CTL1;
 859                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 860                 } else if (plls->wrpll2_refcount == 0) {
 861                         DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
 862                                       pipe_name(pipe));
 863                         plls->wrpll2_refcount++;
 864                         reg = WRPLL_CTL2;
 865                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 866                 } else {
 867                         DRM_ERROR("No WRPLLs available!\n");
 868                         return false;
 869                 }
 870
 871                 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
 872                      "WRPLL already enabled\n");
 873
 874                 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
 875
 876                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
 877                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 878                       WRPLL_DIVIDER_POST(p);
 879
 880         } else if (type == INTEL_OUTPUT_ANALOG) {
 881                 if (plls->spll_refcount == 0) {
 882                         DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
 883                                       pipe_name(pipe));
 884                         plls->spll_refcount++;
 885                         reg = SPLL_CTL;
 886                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 887                 } else {
 888                         DRM_ERROR("SPLL already in use\n");
 889                         return false;
 890                 }
 891
 892                 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
 893                      "SPLL already enabled\n");
 894
 895                 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 896
 897         } else {
 898                 WARN(1, "Invalid DDI encoder type %d\n", type);
 899                 return false;
 900         }
 901
 902         I915_WRITE(reg, val);
 903         udelay(20);
 904
 905         return true;
 906 }
 907
 908 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 909 {
 910         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 912         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 913         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 914         int type = intel_encoder->type;
 915         uint32_t temp;
 916
 917         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 918
 919                 temp = TRANS_MSA_SYNC_CLK;
 920                 switch (intel_crtc->config.pipe_bpp) {
 921                 case 18:
 922                         temp |= TRANS_MSA_6_BPC;
 923                         break;
 924                 case 24:
 925                         temp |= TRANS_MSA_8_BPC;
 926                         break;
 927                 case 30:
 928                         temp |= TRANS_MSA_10_BPC;
 929                         break;
 930                 case 36:
 931                         temp |= TRANS_MSA_12_BPC;
 932                         break;
 933                 default:
 934                         BUG();
 935                 }
 936                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 937         }
 938 }
 939
 940 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 941 {
 942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 943         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 944         struct drm_encoder *encoder = &intel_encoder->base;
 945         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 946         enum pipe pipe = intel_crtc->pipe;
 947         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 948         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 949         int type = intel_encoder->type;
 950         uint32_t temp;
 951
 952         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 953         temp = TRANS_DDI_FUNC_ENABLE;
 954         temp |= TRANS_DDI_SELECT_PORT(port);
 955
 956         switch (intel_crtc->config.pipe_bpp) {
 957         case 18:
 958                 temp |= TRANS_DDI_BPC_6;
 959                 break;
 960         case 24:
 961                 temp |= TRANS_DDI_BPC_8;
 962                 break;
 963         case 30:
 964                 temp |= TRANS_DDI_BPC_10;
 965                 break;
 966         case 36:
 967                 temp |= TRANS_DDI_BPC_12;
 968                 break;
 969         default:
 970                 BUG();
 971         }
 972
 973         if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
 974                 temp |= TRANS_DDI_PVSYNC;
 975         if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
 976                 temp |= TRANS_DDI_PHSYNC;
 977
 978         if (cpu_transcoder == TRANSCODER_EDP) {
 979                 switch (pipe) {
 980                 case PIPE_A:
 981                         /* Can only use the always-on power well for eDP when
 982                          * not using the panel fitter, and when not using motion
 983                           * blur mitigation (which we don't support). */
 984                         if (intel_crtc->config.pch_pfit.size)
 985                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 986                         else
 987                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 988                         break;
 989                 case PIPE_B:
 990                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 991                         break;
 992                 case PIPE_C:
 993                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 994                         break;
 995                 default:
 996                         BUG();
 997                         break;
 998                 }
 999         }
1000
1001         if (type == INTEL_OUTPUT_HDMI) {
1002                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1003
1004                 if (intel_hdmi->has_hdmi_sink)
1005                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1006                 else
1007                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1008
1009         } else if (type == INTEL_OUTPUT_ANALOG) {
1010                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1011                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1012
1013         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1014                    type == INTEL_OUTPUT_EDP) {
1015                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1016
1017                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1018
1019                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1020         } else {
1021                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1022                      intel_encoder->type, pipe_name(pipe));
1023         }
1024
1025         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1026 }
1027
1028 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1029                                        enum transcoder cpu_transcoder)
1030 {
1031         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1032         uint32_t val = I915_READ(reg);
1033
1034         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1035         val |= TRANS_DDI_PORT_NONE;
1036         I915_WRITE(reg, val);
1037 }
1038
1039 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1040 {
1041         struct drm_device *dev = intel_connector->base.dev;
1042         struct drm_i915_private *dev_priv = dev->dev_private;
1043         struct intel_encoder *intel_encoder = intel_connector->encoder;
1044         int type = intel_connector->base.connector_type;
1045         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1046         enum pipe pipe = 0;
1047         enum transcoder cpu_transcoder;
1048         uint32_t tmp;
1049
1050         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1051                 return false;
1052
1053         if (port == PORT_A)
1054                 cpu_transcoder = TRANSCODER_EDP;
1055         else
1056                 cpu_transcoder = (enum transcoder) pipe;
1057
1058         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1059
1060         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1061         case TRANS_DDI_MODE_SELECT_HDMI:
1062         case TRANS_DDI_MODE_SELECT_DVI:
1063                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1064
1065         case TRANS_DDI_MODE_SELECT_DP_SST:
1066                 if (type == DRM_MODE_CONNECTOR_eDP)
1067                         return true;
1068         case TRANS_DDI_MODE_SELECT_DP_MST:
1069                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1070
1071         case TRANS_DDI_MODE_SELECT_FDI:
1072                 return (type == DRM_MODE_CONNECTOR_VGA);
1073
1074         default:
1075                 return false;
1076         }
1077 }
1078
1079 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1080                             enum pipe *pipe)
1081 {
1082         struct drm_device *dev = encoder->base.dev;
1083         struct drm_i915_private *dev_priv = dev->dev_private;
1084         enum port port = intel_ddi_get_encoder_port(encoder);
1085         u32 tmp;
1086         int i;
1087
1088         tmp = I915_READ(DDI_BUF_CTL(port));
1089
1090         if (!(tmp & DDI_BUF_CTL_ENABLE))
1091                 return false;
1092
1093         if (port == PORT_A) {
1094                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1095
1096                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1097                 case TRANS_DDI_EDP_INPUT_A_ON:
1098                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1099                         *pipe = PIPE_A;
1100                         break;
1101                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1102                         *pipe = PIPE_B;
1103                         break;
1104                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1105                         *pipe = PIPE_C;
1106                         break;
1107                 }
1108
1109                 return true;
1110         } else {
1111                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1112                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1113
1114                         if ((tmp & TRANS_DDI_PORT_MASK)
1115                             == TRANS_DDI_SELECT_PORT(port)) {
1116                                 *pipe = i;
1117                                 return true;
1118                         }
1119                 }
1120         }
1121
1122         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1123
1124         return false;
1125 }
1126
1127 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1128                                        enum pipe pipe)
1129 {
1130         uint32_t temp, ret;
1131         enum port port = I915_MAX_PORTS;
1132         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133                                                                       pipe);
1134         int i;
1135
1136         if (cpu_transcoder == TRANSCODER_EDP) {
1137                 port = PORT_A;
1138         } else {
1139                 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1140                 temp &= TRANS_DDI_PORT_MASK;
1141
1142                 for (i = PORT_B; i <= PORT_E; i++)
1143                         if (temp == TRANS_DDI_SELECT_PORT(i))
1144                                 port = i;
1145         }
1146
1147         if (port == I915_MAX_PORTS) {
1148                 WARN(1, "Pipe %c enabled on an unknown port\n",
1149                      pipe_name(pipe));
1150                 ret = PORT_CLK_SEL_NONE;
1151         } else {
1152                 ret = I915_READ(PORT_CLK_SEL(port));
1153                 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1154                               "0x%08x\n", pipe_name(pipe), port_name(port),
1155                               ret);
1156         }
1157
1158         return ret;
1159 }
1160
1161 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1162 {
1163         struct drm_i915_private *dev_priv = dev->dev_private;
1164         enum pipe pipe;
1165         struct intel_crtc *intel_crtc;
1166
1167         for_each_pipe(pipe) {
1168                 intel_crtc =
1169                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1170
1171                 if (!intel_crtc->active)
1172                         continue;
1173
1174                 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1175                                                                  pipe);
1176
1177                 switch (intel_crtc->ddi_pll_sel) {
1178                 case PORT_CLK_SEL_SPLL:
1179                         dev_priv->ddi_plls.spll_refcount++;
1180                         break;
1181                 case PORT_CLK_SEL_WRPLL1:
1182                         dev_priv->ddi_plls.wrpll1_refcount++;
1183                         break;
1184                 case PORT_CLK_SEL_WRPLL2:
1185                         dev_priv->ddi_plls.wrpll2_refcount++;
1186                         break;
1187                 }
1188         }
1189 }
1190
1191 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1192 {
1193         struct drm_crtc *crtc = &intel_crtc->base;
1194         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1195         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1196         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1197         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1198
1199         if (cpu_transcoder != TRANSCODER_EDP)
1200                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1201                            TRANS_CLK_SEL_PORT(port));
1202 }
1203
1204 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1205 {
1206         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1207         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1208
1209         if (cpu_transcoder != TRANSCODER_EDP)
1210                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1211                            TRANS_CLK_SEL_DISABLED);
1212 }
1213
1214 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1215 {
1216         struct drm_encoder *encoder = &intel_encoder->base;
1217         struct drm_crtc *crtc = encoder->crtc;
1218         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1220         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1221         int type = intel_encoder->type;
1222
1223         if (type == INTEL_OUTPUT_EDP) {
1224                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1225                 ironlake_edp_panel_vdd_on(intel_dp);
1226                 ironlake_edp_panel_on(intel_dp);
1227                 ironlake_edp_panel_vdd_off(intel_dp, true);
1228         }
1229
1230         WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1231         I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1232
1233         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1234                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1235
1236                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1237                 intel_dp_start_link_train(intel_dp);
1238                 intel_dp_complete_link_train(intel_dp);
1239         }
1240 }
1241
1242 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1243 {
1244         struct drm_encoder *encoder = &intel_encoder->base;
1245         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1246         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1247         int type = intel_encoder->type;
1248         uint32_t val;
1249         bool wait = false;
1250
1251         val = I915_READ(DDI_BUF_CTL(port));
1252         if (val & DDI_BUF_CTL_ENABLE) {
1253                 val &= ~DDI_BUF_CTL_ENABLE;
1254                 I915_WRITE(DDI_BUF_CTL(port), val);
1255                 wait = true;
1256         }
1257
1258         val = I915_READ(DP_TP_CTL(port));
1259         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1260         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1261         I915_WRITE(DP_TP_CTL(port), val);
1262
1263         if (wait)
1264                 intel_wait_ddi_buf_idle(dev_priv, port);
1265
1266         if (type == INTEL_OUTPUT_EDP) {
1267                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1268                 ironlake_edp_panel_vdd_on(intel_dp);
1269                 ironlake_edp_panel_off(intel_dp);
1270         }
1271
1272         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1273 }
1274
1275 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1276 {
1277         struct drm_encoder *encoder = &intel_encoder->base;
1278         struct drm_crtc *crtc = encoder->crtc;
1279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1280         int pipe = intel_crtc->pipe;
1281         struct drm_device *dev = encoder->dev;
1282         struct drm_i915_private *dev_priv = dev->dev_private;
1283         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1284         int type = intel_encoder->type;
1285         uint32_t tmp;
1286
1287         if (type == INTEL_OUTPUT_HDMI) {
1288                 struct intel_digital_port *intel_dig_port =
1289                         enc_to_dig_port(encoder);
1290
1291                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1292                  * are ignored so nothing special needs to be done besides
1293                  * enabling the port.
1294                  */
1295                 I915_WRITE(DDI_BUF_CTL(port),
1296                            intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
1297         } else if (type == INTEL_OUTPUT_EDP) {
1298                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1299
1300                 ironlake_edp_backlight_on(intel_dp);
1301         }
1302
1303         if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1304                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1305                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1306                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1307         }
1308 }
1309
1310 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1311 {
1312         struct drm_encoder *encoder = &intel_encoder->base;
1313         struct drm_crtc *crtc = encoder->crtc;
1314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1315         int pipe = intel_crtc->pipe;
1316         int type = intel_encoder->type;
1317         struct drm_device *dev = encoder->dev;
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         uint32_t tmp;
1320
1321         if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1322                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1323                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1324                          (pipe * 4));
1325                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1326         }
1327
1328         if (type == INTEL_OUTPUT_EDP) {
1329                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1330
1331                 ironlake_edp_backlight_off(intel_dp);
1332         }
1333 }
1334
1335 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1336 {
1337         if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1338                 return 450;
1339         else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1340                  LCPLL_CLK_FREQ_450)
1341                 return 450;
1342         else if (IS_ULT(dev_priv->dev))
1343                 return 338;
1344         else
1345                 return 540;
1346 }
1347
1348 void intel_ddi_pll_init(struct drm_device *dev)
1349 {
1350         struct drm_i915_private *dev_priv = dev->dev_private;
1351         uint32_t val = I915_READ(LCPLL_CTL);
1352
1353         /* The LCPLL register should be turned on by the BIOS. For now let's
1354          * just check its state and print errors in case something is wrong.
1355          * Don't even try to turn it on.
1356          */
1357
1358         DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1359                       intel_ddi_get_cdclk_freq(dev_priv));
1360
1361         if (val & LCPLL_CD_SOURCE_FCLK)
1362                 DRM_ERROR("CDCLK source is not LCPLL\n");
1363
1364         if (val & LCPLL_PLL_DISABLE)
1365                 DRM_ERROR("LCPLL is disabled\n");
1366 }
1367
1368 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1369 {
1370         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1371         struct intel_dp *intel_dp = &intel_dig_port->dp;
1372         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1373         enum port port = intel_dig_port->port;
1374         uint32_t val;
1375         bool wait = false;
1376
1377         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1378                 val = I915_READ(DDI_BUF_CTL(port));
1379                 if (val & DDI_BUF_CTL_ENABLE) {
1380                         val &= ~DDI_BUF_CTL_ENABLE;
1381                         I915_WRITE(DDI_BUF_CTL(port), val);
1382                         wait = true;
1383                 }
1384
1385                 val = I915_READ(DP_TP_CTL(port));
1386                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1387                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1388                 I915_WRITE(DP_TP_CTL(port), val);
1389                 POSTING_READ(DP_TP_CTL(port));
1390
1391                 if (wait)
1392                         intel_wait_ddi_buf_idle(dev_priv, port);
1393         }
1394
1395         val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1396               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1397         if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1398                 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1399         I915_WRITE(DP_TP_CTL(port), val);
1400         POSTING_READ(DP_TP_CTL(port));
1401
1402         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1403         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1404         POSTING_READ(DDI_BUF_CTL(port));
1405
1406         udelay(600);
1407 }
1408
1409 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1410 {
1411         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1412         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1413         uint32_t val;
1414
1415         intel_ddi_post_disable(intel_encoder);
1416
1417         val = I915_READ(_FDI_RXA_CTL);
1418         val &= ~FDI_RX_ENABLE;
1419         I915_WRITE(_FDI_RXA_CTL, val);
1420
1421         val = I915_READ(_FDI_RXA_MISC);
1422         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1423         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1424         I915_WRITE(_FDI_RXA_MISC, val);
1425
1426         val = I915_READ(_FDI_RXA_CTL);
1427         val &= ~FDI_PCDCLK;
1428         I915_WRITE(_FDI_RXA_CTL, val);
1429
1430         val = I915_READ(_FDI_RXA_CTL);
1431         val &= ~FDI_RX_PLL_ENABLE;
1432         I915_WRITE(_FDI_RXA_CTL, val);
1433 }
1434
1435 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1436 {
1437         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1438         int type = intel_encoder->type;
1439
1440         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1441                 intel_dp_check_link_status(intel_dp);
1442 }
1443
1444 static void intel_ddi_destroy(struct drm_encoder *encoder)
1445 {
1446         /* HDMI has nothing special to destroy, so we can go with this. */
1447         intel_dp_encoder_destroy(encoder);
1448 }
1449
1450 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1451                                      struct intel_crtc_config *pipe_config)
1452 {
1453         int type = encoder->type;
1454
1455         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1456
1457         if (type == INTEL_OUTPUT_HDMI)
1458                 return intel_hdmi_compute_config(encoder, pipe_config);
1459         else
1460                 return intel_dp_compute_config(encoder, pipe_config);
1461 }
1462
1463 static const struct drm_encoder_funcs intel_ddi_funcs = {
1464         .destroy = intel_ddi_destroy,
1465 };
1466
1467 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1468         .mode_set = intel_ddi_mode_set,
1469 };
1470
1471 void intel_ddi_init(struct drm_device *dev, enum port port)
1472 {
1473         struct drm_i915_private *dev_priv = dev->dev_private;
1474         struct intel_digital_port *intel_dig_port;
1475         struct intel_encoder *intel_encoder;
1476         struct drm_encoder *encoder;
1477         struct intel_connector *hdmi_connector = NULL;
1478         struct intel_connector *dp_connector = NULL;
1479
1480         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1481         if (!intel_dig_port)
1482                 return;
1483
1484         dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1485         if (!dp_connector) {
1486                 kfree(intel_dig_port);
1487                 return;
1488         }
1489
1490         intel_encoder = &intel_dig_port->base;
1491         encoder = &intel_encoder->base;
1492
1493         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1494                          DRM_MODE_ENCODER_TMDS);
1495         drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1496
1497         intel_encoder->compute_config = intel_ddi_compute_config;
1498         intel_encoder->enable = intel_enable_ddi;
1499         intel_encoder->pre_enable = intel_ddi_pre_enable;
1500         intel_encoder->disable = intel_disable_ddi;
1501         intel_encoder->post_disable = intel_ddi_post_disable;
1502         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1503
1504         intel_dig_port->port = port;
1505         intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
1506                                         DDI_BUF_PORT_REVERSAL;
1507         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1508
1509         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1510         intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
1511         intel_encoder->cloneable = false;
1512         intel_encoder->hot_plug = intel_ddi_hot_plug;
1513
1514         intel_dp_init_connector(intel_dig_port, dp_connector);
1515
1516         if (intel_encoder->type != INTEL_OUTPUT_EDP) {
1517                 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1518                                          GFP_KERNEL);
1519                 if (!hdmi_connector) {
1520                         return;
1521                 }
1522
1523                 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1524                 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1525         }
1526 }