drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 101                                   struct drm_i915_gem_object *obj,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125
 126 struct intel_limit {
 127         struct {
 128                 int min, max;
 129         } dot, vco, n, m, m1, m2, p, p1;
 130
 131         struct {
 132                 int dot_limit;
 133                 int p2_slow, p2_fast;
 134         } p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 152                       const char *name, u32 reg, int ref_freq)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         mutex_lock(&dev_priv->sb_lock);
 158         val = vlv_cck_read(dev_priv, reg);
 159         mutex_unlock(&dev_priv->sb_lock);
 160
 161         divider = val & CCK_FREQUENCY_VALUES;
 162
 163         WARN((val & CCK_FREQUENCY_STATUS) !=
 164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 165              "%s change in progress\n", name);
 166
 167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 168 }
 169
 170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 171                            const char *name, u32 reg)
 172 {
 173         if (dev_priv->hpll_freq == 0)
 174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 175
 176         return vlv_get_cck_clock(dev_priv, name, reg,
 177                                  dev_priv->hpll_freq);
 178 }
 179
 180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 181 {
 182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 183                 return;
 184
 185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 186                                                       CCK_CZ_CLOCK_CONTROL);
 187
 188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 189 }
 190
 191 static inline u32 /* units of 100MHz */
 192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 193                     const struct intel_crtc_state *pipe_config)
 194 {
 195         if (HAS_DDI(dev_priv))
 196                 return pipe_config->port_clock; /* SPLL */
 197         else if (IS_GEN5(dev_priv))
 198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 199         else
 200                 return 270000;
 201 }
 202
 203 static const struct intel_limit intel_limits_i8xx_dac = {
 204         .dot = { .min = 25000, .max = 350000 },
 205         .vco = { .min = 908000, .max = 1512000 },
 206         .n = { .min = 2, .max = 16 },
 207         .m = { .min = 96, .max = 140 },
 208         .m1 = { .min = 18, .max = 26 },
 209         .m2 = { .min = 6, .max = 16 },
 210         .p = { .min = 4, .max = 128 },
 211         .p1 = { .min = 2, .max = 33 },
 212         .p2 = { .dot_limit = 165000,
 213                 .p2_slow = 4, .p2_fast = 2 },
 214 };
 215
 216 static const struct intel_limit intel_limits_i8xx_dvo = {
 217         .dot = { .min = 25000, .max = 350000 },
 218         .vco = { .min = 908000, .max = 1512000 },
 219         .n = { .min = 2, .max = 16 },
 220         .m = { .min = 96, .max = 140 },
 221         .m1 = { .min = 18, .max = 26 },
 222         .m2 = { .min = 6, .max = 16 },
 223         .p = { .min = 4, .max = 128 },
 224         .p1 = { .min = 2, .max = 33 },
 225         .p2 = { .dot_limit = 165000,
 226                 .p2_slow = 4, .p2_fast = 4 },
 227 };
 228
 229 static const struct intel_limit intel_limits_i8xx_lvds = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 908000, .max = 1512000 },
 232         .n = { .min = 2, .max = 16 },
 233         .m = { .min = 96, .max = 140 },
 234         .m1 = { .min = 18, .max = 26 },
 235         .m2 = { .min = 6, .max = 16 },
 236         .p = { .min = 4, .max = 128 },
 237         .p1 = { .min = 1, .max = 6 },
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 14, .p2_fast = 7 },
 240 };
 241
 242 static const struct intel_limit intel_limits_i9xx_sdvo = {
 243         .dot = { .min = 20000, .max = 400000 },
 244         .vco = { .min = 1400000, .max = 2800000 },
 245         .n = { .min = 1, .max = 6 },
 246         .m = { .min = 70, .max = 120 },
 247         .m1 = { .min = 8, .max = 18 },
 248         .m2 = { .min = 3, .max = 7 },
 249         .p = { .min = 5, .max = 80 },
 250         .p1 = { .min = 1, .max = 8 },
 251         .p2 = { .dot_limit = 200000,
 252                 .p2_slow = 10, .p2_fast = 5 },
 253 };
 254
 255 static const struct intel_limit intel_limits_i9xx_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1400000, .max = 2800000 },
 258         .n = { .min = 1, .max = 6 },
 259         .m = { .min = 70, .max = 120 },
 260         .m1 = { .min = 8, .max = 18 },
 261         .m2 = { .min = 3, .max = 7 },
 262         .p = { .min = 7, .max = 98 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 7 },
 266 };
 267
 268
 269 static const struct intel_limit intel_limits_g4x_sdvo = {
 270         .dot = { .min = 25000, .max = 270000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 17, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 10, .max = 30 },
 277         .p1 = { .min = 1, .max = 3},
 278         .p2 = { .dot_limit = 270000,
 279                 .p2_slow = 10,
 280                 .p2_fast = 10
 281         },
 282 };
 283
 284 static const struct intel_limit intel_limits_g4x_hdmi = {
 285         .dot = { .min = 22000, .max = 400000 },
 286         .vco = { .min = 1750000, .max = 3500000},
 287         .n = { .min = 1, .max = 4 },
 288         .m = { .min = 104, .max = 138 },
 289         .m1 = { .min = 16, .max = 23 },
 290         .m2 = { .min = 5, .max = 11 },
 291         .p = { .min = 5, .max = 80 },
 292         .p1 = { .min = 1, .max = 8},
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 10, .p2_fast = 5 },
 295 };
 296
 297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 298         .dot = { .min = 20000, .max = 115000 },
 299         .vco = { .min = 1750000, .max = 3500000 },
 300         .n = { .min = 1, .max = 3 },
 301         .m = { .min = 104, .max = 138 },
 302         .m1 = { .min = 17, .max = 23 },
 303         .m2 = { .min = 5, .max = 11 },
 304         .p = { .min = 28, .max = 112 },
 305         .p1 = { .min = 2, .max = 8 },
 306         .p2 = { .dot_limit = 0,
 307                 .p2_slow = 14, .p2_fast = 14
 308         },
 309 };
 310
 311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 312         .dot = { .min = 80000, .max = 224000 },
 313         .vco = { .min = 1750000, .max = 3500000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 104, .max = 138 },
 316         .m1 = { .min = 17, .max = 23 },
 317         .m2 = { .min = 5, .max = 11 },
 318         .p = { .min = 14, .max = 42 },
 319         .p1 = { .min = 2, .max = 6 },
 320         .p2 = { .dot_limit = 0,
 321                 .p2_slow = 7, .p2_fast = 7
 322         },
 323 };
 324
 325 static const struct intel_limit intel_limits_pineview_sdvo = {
 326         .dot = { .min = 20000, .max = 400000},
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         /* Pineview's Ncounter is a ring counter */
 329         .n = { .min = 3, .max = 6 },
 330         .m = { .min = 2, .max = 256 },
 331         /* Pineview only has one combined m divider, which we treat as m2. */
 332         .m1 = { .min = 0, .max = 0 },
 333         .m2 = { .min = 0, .max = 254 },
 334         .p = { .min = 5, .max = 80 },
 335         .p1 = { .min = 1, .max = 8 },
 336         .p2 = { .dot_limit = 200000,
 337                 .p2_slow = 10, .p2_fast = 5 },
 338 };
 339
 340 static const struct intel_limit intel_limits_pineview_lvds = {
 341         .dot = { .min = 20000, .max = 400000 },
 342         .vco = { .min = 1700000, .max = 3500000 },
 343         .n = { .min = 3, .max = 6 },
 344         .m = { .min = 2, .max = 256 },
 345         .m1 = { .min = 0, .max = 0 },
 346         .m2 = { .min = 0, .max = 254 },
 347         .p = { .min = 7, .max = 112 },
 348         .p1 = { .min = 1, .max = 8 },
 349         .p2 = { .dot_limit = 112000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 /* Ironlake / Sandybridge
 354  *
 355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 356  * the range value for them is (actual_value - 2).
 357  */
 358 static const struct intel_limit intel_limits_ironlake_dac = {
 359         .dot = { .min = 25000, .max = 350000 },
 360         .vco = { .min = 1760000, .max = 3510000 },
 361         .n = { .min = 1, .max = 5 },
 362         .m = { .min = 79, .max = 127 },
 363         .m1 = { .min = 12, .max = 22 },
 364         .m2 = { .min = 5, .max = 9 },
 365         .p = { .min = 5, .max = 80 },
 366         .p1 = { .min = 1, .max = 8 },
 367         .p2 = { .dot_limit = 225000,
 368                 .p2_slow = 10, .p2_fast = 5 },
 369 };
 370
 371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 372         .dot = { .min = 25000, .max = 350000 },
 373         .vco = { .min = 1760000, .max = 3510000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 79, .max = 118 },
 376         .m1 = { .min = 12, .max = 22 },
 377         .m2 = { .min = 5, .max = 9 },
 378         .p = { .min = 28, .max = 112 },
 379         .p1 = { .min = 2, .max = 8 },
 380         .p2 = { .dot_limit = 225000,
 381                 .p2_slow = 14, .p2_fast = 14 },
 382 };
 383
 384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 385         .dot = { .min = 25000, .max = 350000 },
 386         .vco = { .min = 1760000, .max = 3510000 },
 387         .n = { .min = 1, .max = 3 },
 388         .m = { .min = 79, .max = 127 },
 389         .m1 = { .min = 12, .max = 22 },
 390         .m2 = { .min = 5, .max = 9 },
 391         .p = { .min = 14, .max = 56 },
 392         .p1 = { .min = 2, .max = 8 },
 393         .p2 = { .dot_limit = 225000,
 394                 .p2_slow = 7, .p2_fast = 7 },
 395 };
 396
 397 /* LVDS 100mhz refclk limits. */
 398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 399         .dot = { .min = 25000, .max = 350000 },
 400         .vco = { .min = 1760000, .max = 3510000 },
 401         .n = { .min = 1, .max = 2 },
 402         .m = { .min = 79, .max = 126 },
 403         .m1 = { .min = 12, .max = 22 },
 404         .m2 = { .min = 5, .max = 9 },
 405         .p = { .min = 28, .max = 112 },
 406         .p1 = { .min = 2, .max = 8 },
 407         .p2 = { .dot_limit = 225000,
 408                 .p2_slow = 14, .p2_fast = 14 },
 409 };
 410
 411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 3 },
 415         .m = { .min = 79, .max = 126 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 14, .max = 42 },
 419         .p1 = { .min = 2, .max = 6 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 7, .p2_fast = 7 },
 422 };
 423
 424 static const struct intel_limit intel_limits_vlv = {
 425          /*
 426           * These are the data rate limits (measured in fast clocks)
 427           * since those are the strictest limits we have. The fast
 428           * clock and actual rate limits are more relaxed, so checking
 429           * them would make no difference.
 430           */
 431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 432         .vco = { .min = 4000000, .max = 6000000 },
 433         .n = { .min = 1, .max = 7 },
 434         .m1 = { .min = 2, .max = 3 },
 435         .m2 = { .min = 11, .max = 156 },
 436         .p1 = { .min = 2, .max = 3 },
 437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 438 };
 439
 440 static const struct intel_limit intel_limits_chv = {
 441         /*
 442          * These are the data rate limits (measured in fast clocks)
 443          * since those are the strictest limits we have.  The fast
 444          * clock and actual rate limits are more relaxed, so checking
 445          * them would make no difference.
 446          */
 447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 448         .vco = { .min = 4800000, .max = 6480000 },
 449         .n = { .min = 1, .max = 1 },
 450         .m1 = { .min = 2, .max = 2 },
 451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 452         .p1 = { .min = 2, .max = 4 },
 453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 454 };
 455
 456 static const struct intel_limit intel_limits_bxt = {
 457         /* FIXME: find real dot limits */
 458         .dot = { .min = 0, .max = INT_MAX },
 459         .vco = { .min = 4800000, .max = 6700000 },
 460         .n = { .min = 1, .max = 1 },
 461         .m1 = { .min = 2, .max = 2 },
 462         /* FIXME: find real m2 limits */
 463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 464         .p1 = { .min = 2, .max = 4 },
 465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 466 };
 467
 468 static bool
 469 needs_modeset(struct drm_crtc_state *state)
 470 {
 471         return drm_atomic_crtc_needs_modeset(state);
 472 }
 473
 474 /*
 475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 478  * The helpers' return value is the rate of the clock that is fed to the
 479  * display engine's pipe which can be the above fast dot clock rate or a
 480  * divided-down version of it.
 481  */
 482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 484 {
 485         clock->m = clock->m2 + 2;
 486         clock->p = clock->p1 * clock->p2;
 487         if (WARN_ON(clock->n == 0 || clock->p == 0))
 488                 return 0;
 489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 491
 492         return clock->dot;
 493 }
 494
 495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 496 {
 497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 498 }
 499
 500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 501 {
 502         clock->m = i9xx_dpll_compute_m(clock);
 503         clock->p = clock->p1 * clock->p2;
 504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 505                 return 0;
 506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 508
 509         return clock->dot;
 510 }
 511
 512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 513 {
 514         clock->m = clock->m1 * clock->m2;
 515         clock->p = clock->p1 * clock->p2;
 516         if (WARN_ON(clock->n == 0 || clock->p == 0))
 517                 return 0;
 518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 520
 521         return clock->dot / 5;
 522 }
 523
 524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 525 {
 526         clock->m = clock->m1 * clock->m2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return 0;
 530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 531                         clock->n << 22);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot / 5;
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 544                                const struct intel_limit *limit,
 545                                const struct dpll *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 558                 if (clock->m1 <= clock->m2)
 559                         INTELPllInvalid("m1 <= m2\n");
 560
 561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 562             !IS_GEN9_LP(dev_priv)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static int
 581 i9xx_select_p2_div(const struct intel_limit *limit,
 582                    const struct intel_crtc_state *crtc_state,
 583                    int target)
 584 {
 585         struct drm_device *dev = crtc_state->base.crtc->dev;
 586
 587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         return limit->p2.p2_fast;
 595                 else
 596                         return limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         return limit->p2.p2_slow;
 600                 else
 601                         return limit->p2.p2_fast;
 602         }
 603 }
 604
 605 /*
 606  * Returns a set of divisors for the desired target clock with the given
 607  * refclk, or FALSE.  The returned values represent the clock equation:
 608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 609  *
 610  * Target and reference clocks are specified in kHz.
 611  *
 612  * If match_clock is provided, then best_clock P divider must match the P
 613  * divider from @match_clock used for LVDS downclocking.
 614  */
 615 static bool
 616 i9xx_find_best_dpll(const struct intel_limit *limit,
 617                     struct intel_crtc_state *crtc_state,
 618                     int target, int refclk, struct dpll *match_clock,
 619                     struct dpll *best_clock)
 620 {
 621         struct drm_device *dev = crtc_state->base.crtc->dev;
 622         struct dpll clock;
 623         int err = target;
 624
 625         memset(best_clock, 0, sizeof(*best_clock));
 626
 627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_calc_dpll_params(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(to_i915(dev),
 643                                                                 limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 pnv_find_best_dpll(const struct intel_limit *limit,
 675                    struct intel_crtc_state *crtc_state,
 676                    int target, int refclk, struct dpll *match_clock,
 677                    struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pnv_calc_dpll_params(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(to_i915(dev),
 699                                                                 limit,
 700                                                                 &clock))
 701                                                 continue;
 702                                         if (match_clock &&
 703                                             clock.p != match_clock->p)
 704                                                 continue;
 705
 706                                         this_err = abs(clock.dot - target);
 707                                         if (this_err < err) {
 708                                                 *best_clock = clock;
 709                                                 err = this_err;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715
 716         return (err != target);
 717 }
 718
 719 /*
 720  * Returns a set of divisors for the desired target clock with the given
 721  * refclk, or FALSE.  The returned values represent the clock equation:
 722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 723  *
 724  * Target and reference clocks are specified in kHz.
 725  *
 726  * If match_clock is provided, then best_clock P divider must match the P
 727  * divider from @match_clock used for LVDS downclocking.
 728  */
 729 static bool
 730 g4x_find_best_dpll(const struct intel_limit *limit,
 731                    struct intel_crtc_state *crtc_state,
 732                    int target, int refclk, struct dpll *match_clock,
 733                    struct dpll *best_clock)
 734 {
 735         struct drm_device *dev = crtc_state->base.crtc->dev;
 736         struct dpll clock;
 737         int max_n;
 738         bool found = false;
 739         /* approximately equals target * 0.00585 */
 740         int err_most = (target >> 8) + (target >> 9);
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         max_n = limit->n.max;
 747         /* based on hardware requirement, prefer smaller n to precision */
 748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 749                 /* based on hardware requirement, prefere larger m1,m2 */
 750                 for (clock.m1 = limit->m1.max;
 751                      clock.m1 >= limit->m1.min; clock.m1--) {
 752                         for (clock.m2 = limit->m2.max;
 753                              clock.m2 >= limit->m2.min; clock.m2--) {
 754                                 for (clock.p1 = limit->p1.max;
 755                                      clock.p1 >= limit->p1.min; clock.p1--) {
 756                                         int this_err;
 757
 758                                         i9xx_calc_dpll_params(refclk, &clock);
 759                                         if (!intel_PLL_is_valid(to_i915(dev),
 760                                                                 limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 /*
 779  * Check if the calculated PLL configuration is more optimal compared to the
 780  * best configuration and error found so far. Return the calculated error.
 781  */
 782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 783                                const struct dpll *calculated_clock,
 784                                const struct dpll *best_clock,
 785                                unsigned int best_error_ppm,
 786                                unsigned int *error_ppm)
 787 {
 788         /*
 789          * For CHV ignore the error and consider only the P value.
 790          * Prefer a bigger P value based on HW requirements.
 791          */
 792         if (IS_CHERRYVIEW(to_i915(dev))) {
 793                 *error_ppm = 0;
 794
 795                 return calculated_clock->p > best_clock->p;
 796         }
 797
 798         if (WARN_ON_ONCE(!target_freq))
 799                 return false;
 800
 801         *error_ppm = div_u64(1000000ULL *
 802                                 abs(target_freq - calculated_clock->dot),
 803                              target_freq);
 804         /*
 805          * Prefer a better P value over a better (smaller) error if the error
 806          * is small. Ensure this preference for future configurations too by
 807          * setting the error to 0.
 808          */
 809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 810                 *error_ppm = 0;
 811
 812                 return true;
 813         }
 814
 815         return *error_ppm + 10 < best_error_ppm;
 816 }
 817
 818 /*
 819  * Returns a set of divisors for the desired target clock with the given
 820  * refclk, or FALSE.  The returned values represent the clock equation:
 821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 822  */
 823 static bool
 824 vlv_find_best_dpll(const struct intel_limit *limit,
 825                    struct intel_crtc_state *crtc_state,
 826                    int target, int refclk, struct dpll *match_clock,
 827                    struct dpll *best_clock)
 828 {
 829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 830         struct drm_device *dev = crtc->base.dev;
 831         struct dpll clock;
 832         unsigned int bestppm = 1000000;
 833         /* min update 19.2 MHz */
 834         int max_n = min(limit->n.max, refclk / 19200);
 835         bool found = false;
 836
 837         target *= 5; /* fast clock */
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         /* based on hardware requirement, prefer smaller n to precision */
 842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 846                                 clock.p = clock.p1 * clock.p2;
 847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 849                                         unsigned int ppm;
 850
 851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 852                                                                      refclk * clock.m1);
 853
 854                                         vlv_calc_dpll_params(refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(to_i915(dev),
 857                                                                 limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         if (!vlv_PLL_is_optimal(dev, target,
 862                                                                 &clock,
 863                                                                 best_clock,
 864                                                                 bestppm, &ppm))
 865                                                 continue;
 866
 867                                         *best_clock = clock;
 868                                         bestppm = ppm;
 869                                         found = true;
 870                                 }
 871                         }
 872                 }
 873         }
 874
 875         return found;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 chv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         unsigned int best_error_ppm;
 892         struct dpll clock;
 893         uint64_t m2;
 894         int found = false;
 895
 896         memset(best_clock, 0, sizeof(*best_clock));
 897         best_error_ppm = 1000000;
 898
 899         /*
 900          * Based on hardware doc, the n always set to 1, and m1 always
 901          * set to 2.  If requires to support 200Mhz refclk, we need to
 902          * revisit this because n may not 1 anymore.
 903          */
 904         clock.n = 1, clock.m1 = 2;
 905         target *= 5;    /* fast clock */
 906
 907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 908                 for (clock.p2 = limit->p2.p2_fast;
 909                                 clock.p2 >= limit->p2.p2_slow;
 910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 911                         unsigned int error_ppm;
 912
 913                         clock.p = clock.p1 * clock.p2;
 914
 915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 916                                         clock.n) << 22, refclk * clock.m1);
 917
 918                         if (m2 > INT_MAX/clock.m1)
 919                                 continue;
 920
 921                         clock.m2 = m2;
 922
 923                         chv_calc_dpll_params(refclk, &clock);
 924
 925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 926                                 continue;
 927
 928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 929                                                 best_error_ppm, &error_ppm))
 930                                 continue;
 931
 932                         *best_clock = clock;
 933                         best_error_ppm = error_ppm;
 934                         found = true;
 935                 }
 936         }
 937
 938         return found;
 939 }
 940
 941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 942                         struct dpll *best_clock)
 943 {
 944         int refclk = 100000;
 945         const struct intel_limit *limit = &intel_limits_bxt;
 946
 947         return chv_find_best_dpll(limit, crtc_state,
 948                                   target_clock, refclk, NULL, best_clock);
 949 }
 950
 951 bool intel_crtc_active(struct intel_crtc *crtc)
 952 {
 953         /* Be paranoid as we can arrive here with only partial
 954          * state retrieved from the hardware during setup.
 955          *
 956          * We can ditch the adjusted_mode.crtc_clock check as soon
 957          * as Haswell has gained clock readout/fastboot support.
 958          *
 959          * We can ditch the crtc->primary->fb check as soon as we can
 960          * properly reconstruct framebuffers.
 961          *
 962          * FIXME: The intel_crtc->active here should be switched to
 963          * crtc->state->active once we have proper CRTC states wired up
 964          * for atomic.
 965          */
 966         return crtc->active && crtc->base.primary->state->fb &&
 967                 crtc->config->base.adjusted_mode.crtc_clock;
 968 }
 969
 970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 971                                              enum pipe pipe)
 972 {
 973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 974
 975         return crtc->config->cpu_transcoder;
 976 }
 977
 978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
 979 {
 980         i915_reg_t reg = PIPEDSL(pipe);
 981         u32 line1, line2;
 982         u32 line_mask;
 983
 984         if (IS_GEN2(dev_priv))
 985                 line_mask = DSL_LINEMASK_GEN2;
 986         else
 987                 line_mask = DSL_LINEMASK_GEN3;
 988
 989         line1 = I915_READ(reg) & line_mask;
 990         msleep(5);
 991         line2 = I915_READ(reg) & line_mask;
 992
 993         return line1 == line2;
 994 }
 995
 996 /*
 997  * intel_wait_for_pipe_off - wait for pipe to turn off
 998  * @crtc: crtc whose pipe to wait for
 999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997         unsigned int cpp = fb->format->cpp[plane];
1998
1999         switch (fb->modifier) {
2000         case DRM_FORMAT_MOD_NONE:
2001                 return cpp;
2002         case I915_FORMAT_MOD_X_TILED:
2003                 if (IS_GEN2(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Y_TILED:
2008                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009                         return 128;
2010                 else
2011                         return 512;
2012         case I915_FORMAT_MOD_Yf_TILED:
2013                 switch (cpp) {
2014                 case 1:
2015                         return 64;
2016                 case 2:
2017                 case 4:
2018                         return 128;
2019                 case 8:
2020                 case 16:
2021                         return 256;
2022                 default:
2023                         MISSING_CASE(cpp);
2024                         return cpp;
2025                 }
2026                 break;
2027         default:
2028                 MISSING_CASE(fb->modifier);
2029                 return cpp;
2030         }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036         if (fb->modifier == DRM_FORMAT_MOD_NONE)
2037                 return 1;
2038         else
2039                 return intel_tile_size(to_i915(fb->dev)) /
2040                         intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045                             unsigned int *tile_width,
2046                             unsigned int *tile_height)
2047 {
2048         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049         unsigned int cpp = fb->format->cpp[plane];
2050
2051         *tile_width = tile_width_bytes / cpp;
2052         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057                       int plane, unsigned int height)
2058 {
2059         unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061         return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066         unsigned int size = 0;
2067         int i;
2068
2069         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072         return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077                         const struct drm_framebuffer *fb,
2078                         unsigned int rotation)
2079 {
2080         view->type = I915_GGTT_VIEW_NORMAL;
2081         if (drm_rotation_90_or_270(rotation)) {
2082                 view->type = I915_GGTT_VIEW_ROTATED;
2083                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084         }
2085 }
2086
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089         if (INTEL_INFO(dev_priv)->gen >= 9)
2090                 return 256 * 1024;
2091         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2093                 return 128 * 1024;
2094         else if (INTEL_INFO(dev_priv)->gen >= 4)
2095                 return 4 * 1024;
2096         else
2097                 return 0;
2098 }
2099
2100 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2101                                          int plane)
2102 {
2103         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2104
2105         /* AUX_DIST needs only 4K alignment */
2106         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2107                 return 4096;
2108
2109         switch (fb->modifier) {
2110         case DRM_FORMAT_MOD_NONE:
2111                 return intel_linear_alignment(dev_priv);
2112         case I915_FORMAT_MOD_X_TILED:
2113                 if (INTEL_GEN(dev_priv) >= 9)
2114                         return 256 * 1024;
2115                 return 0;
2116         case I915_FORMAT_MOD_Y_TILED:
2117         case I915_FORMAT_MOD_Yf_TILED:
2118                 return 1 * 1024 * 1024;
2119         default:
2120                 MISSING_CASE(fb->modifier);
2121                 return 0;
2122         }
2123 }
2124
2125 struct i915_vma *
2126 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2127 {
2128         struct drm_device *dev = fb->dev;
2129         struct drm_i915_private *dev_priv = to_i915(dev);
2130         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2131         struct i915_ggtt_view view;
2132         struct i915_vma *vma;
2133         u32 alignment;
2134
2135         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137         alignment = intel_surf_alignment(fb, 0);
2138
2139         intel_fill_fb_ggtt_view(&view, fb, rotation);
2140
2141         /* Note that the w/a also requires 64 PTE of padding following the
2142          * bo. We currently fill all unused PTE with the shadow page and so
2143          * we should always have valid PTE following the scanout preventing
2144          * the VT-d warning.
2145          */
2146         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147                 alignment = 256 * 1024;
2148
2149         /*
2150          * Global gtt pte registers are special registers which actually forward
2151          * writes to a chunk of system memory. Which means that there is no risk
2152          * that the register values disappear as soon as we call
2153          * intel_runtime_pm_put(), so it is correct to wrap only the
2154          * pin/unpin/fence and not more.
2155          */
2156         intel_runtime_pm_get(dev_priv);
2157
2158         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2159         if (IS_ERR(vma))
2160                 goto err;
2161
2162         if (i915_vma_is_map_and_fenceable(vma)) {
2163                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164                  * fence, whereas 965+ only requires a fence if using
2165                  * framebuffer compression.  For simplicity, we always, when
2166                  * possible, install a fence as the cost is not that onerous.
2167                  *
2168                  * If we fail to fence the tiled scanout, then either the
2169                  * modeset will reject the change (which is highly unlikely as
2170                  * the affected systems, all but one, do not have unmappable
2171                  * space) or we will not be able to enable full powersaving
2172                  * techniques (also likely not to apply due to various limits
2173                  * FBC and the like impose on the size of the buffer, which
2174                  * presumably we violated anyway with this unmappable buffer).
2175                  * Anyway, it is presumably better to stumble onwards with
2176                  * something and try to run the system in a "less than optimal"
2177                  * mode that matches the user configuration.
2178                  */
2179                 if (i915_vma_get_fence(vma) == 0)
2180                         i915_vma_pin_fence(vma);
2181         }
2182
2183         i915_vma_get(vma);
2184 err:
2185         intel_runtime_pm_put(dev_priv);
2186         return vma;
2187 }
2188
2189 void intel_unpin_fb_vma(struct i915_vma *vma)
2190 {
2191         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2192
2193         i915_vma_unpin_fence(vma);
2194         i915_gem_object_unpin_from_display_plane(vma);
2195         i915_vma_put(vma);
2196 }
2197
2198 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199                           unsigned int rotation)
2200 {
2201         if (drm_rotation_90_or_270(rotation))
2202                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2203         else
2204                 return fb->pitches[plane];
2205 }
2206
2207 /*
2208  * Convert the x/y offsets into a linear offset.
2209  * Only valid with 0/180 degree rotation, which is fine since linear
2210  * offset is only used with linear buffers on pre-hsw and tiled buffers
2211  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2212  */
2213 u32 intel_fb_xy_to_linear(int x, int y,
2214                           const struct intel_plane_state *state,
2215                           int plane)
2216 {
2217         const struct drm_framebuffer *fb = state->base.fb;
2218         unsigned int cpp = fb->format->cpp[plane];
2219         unsigned int pitch = fb->pitches[plane];
2220
2221         return y * pitch + x * cpp;
2222 }
2223
2224 /*
2225  * Add the x/y offsets derived from fb->offsets[] to the user
2226  * specified plane src x/y offsets. The resulting x/y offsets
2227  * specify the start of scanout from the beginning of the gtt mapping.
2228  */
2229 void intel_add_fb_offsets(int *x, int *y,
2230                           const struct intel_plane_state *state,
2231                           int plane)
2232
2233 {
2234         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235         unsigned int rotation = state->base.rotation;
2236
2237         if (drm_rotation_90_or_270(rotation)) {
2238                 *x += intel_fb->rotated[plane].x;
2239                 *y += intel_fb->rotated[plane].y;
2240         } else {
2241                 *x += intel_fb->normal[plane].x;
2242                 *y += intel_fb->normal[plane].y;
2243         }
2244 }
2245
2246 /*
2247  * Input tile dimensions and pitch must already be
2248  * rotated to match x and y, and in pixel units.
2249  */
2250 static u32 _intel_adjust_tile_offset(int *x, int *y,
2251                                      unsigned int tile_width,
2252                                      unsigned int tile_height,
2253                                      unsigned int tile_size,
2254                                      unsigned int pitch_tiles,
2255                                      u32 old_offset,
2256                                      u32 new_offset)
2257 {
2258         unsigned int pitch_pixels = pitch_tiles * tile_width;
2259         unsigned int tiles;
2260
2261         WARN_ON(old_offset & (tile_size - 1));
2262         WARN_ON(new_offset & (tile_size - 1));
2263         WARN_ON(new_offset > old_offset);
2264
2265         tiles = (old_offset - new_offset) / tile_size;
2266
2267         *y += tiles / pitch_tiles * tile_height;
2268         *x += tiles % pitch_tiles * tile_width;
2269
2270         /* minimize x in case it got needlessly big */
2271         *y += *x / pitch_pixels * tile_height;
2272         *x %= pitch_pixels;
2273
2274         return new_offset;
2275 }
2276
2277 /*
2278  * Adjust the tile offset by moving the difference into
2279  * the x/y offsets.
2280  */
2281 static u32 intel_adjust_tile_offset(int *x, int *y,
2282                                     const struct intel_plane_state *state, int plane,
2283                                     u32 old_offset, u32 new_offset)
2284 {
2285         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286         const struct drm_framebuffer *fb = state->base.fb;
2287         unsigned int cpp = fb->format->cpp[plane];
2288         unsigned int rotation = state->base.rotation;
2289         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2290
2291         WARN_ON(new_offset > old_offset);
2292
2293         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2294                 unsigned int tile_size, tile_width, tile_height;
2295                 unsigned int pitch_tiles;
2296
2297                 tile_size = intel_tile_size(dev_priv);
2298                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2299
2300                 if (drm_rotation_90_or_270(rotation)) {
2301                         pitch_tiles = pitch / tile_height;
2302                         swap(tile_width, tile_height);
2303                 } else {
2304                         pitch_tiles = pitch / (tile_width * cpp);
2305                 }
2306
2307                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308                                           tile_size, pitch_tiles,
2309                                           old_offset, new_offset);
2310         } else {
2311                 old_offset += *y * pitch + *x * cpp;
2312
2313                 *y = (old_offset - new_offset) / pitch;
2314                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2315         }
2316
2317         return new_offset;
2318 }
2319
2320 /*
2321  * Computes the linear offset to the base tile and adjusts
2322  * x, y. bytes per pixel is assumed to be a power-of-two.
2323  *
2324  * In the 90/270 rotated case, x and y are assumed
2325  * to be already rotated to match the rotated GTT view, and
2326  * pitch is the tile_height aligned framebuffer height.
2327  *
2328  * This function is used when computing the derived information
2329  * under intel_framebuffer, so using any of that information
2330  * here is not allowed. Anything under drm_framebuffer can be
2331  * used. This is why the user has to pass in the pitch since it
2332  * is specified in the rotated orientation.
2333  */
2334 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2335                                       int *x, int *y,
2336                                       const struct drm_framebuffer *fb, int plane,
2337                                       unsigned int pitch,
2338                                       unsigned int rotation,
2339                                       u32 alignment)
2340 {
2341         uint64_t fb_modifier = fb->modifier;
2342         unsigned int cpp = fb->format->cpp[plane];
2343         u32 offset, offset_aligned;
2344
2345         if (alignment)
2346                 alignment--;
2347
2348         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2349                 unsigned int tile_size, tile_width, tile_height;
2350                 unsigned int tile_rows, tiles, pitch_tiles;
2351
2352                 tile_size = intel_tile_size(dev_priv);
2353                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2354
2355                 if (drm_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                           tile_size, pitch_tiles,
2373                                           offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386                               const struct intel_plane_state *state,
2387                               int plane)
2388 {
2389         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390         const struct drm_framebuffer *fb = state->base.fb;
2391         unsigned int rotation = state->base.rotation;
2392         int pitch = intel_fb_pitch(fb, plane, rotation);
2393         u32 alignment = intel_surf_alignment(fb, plane);
2394
2395         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396                                           rotation, alignment);
2397 }
2398
2399 /* Convert the fb->offset[] linear offset into x/y offsets */
2400 static void intel_fb_offset_to_xy(int *x, int *y,
2401                                   const struct drm_framebuffer *fb, int plane)
2402 {
2403         unsigned int cpp = fb->format->cpp[plane];
2404         unsigned int pitch = fb->pitches[plane];
2405         u32 linear_offset = fb->offsets[plane];
2406
2407         *y = linear_offset / pitch;
2408         *x = linear_offset % pitch / cpp;
2409 }
2410
2411 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2412 {
2413         switch (fb_modifier) {
2414         case I915_FORMAT_MOD_X_TILED:
2415                 return I915_TILING_X;
2416         case I915_FORMAT_MOD_Y_TILED:
2417                 return I915_TILING_Y;
2418         default:
2419                 return I915_TILING_NONE;
2420         }
2421 }
2422
2423 static int
2424 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425                    struct drm_framebuffer *fb)
2426 {
2427         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429         u32 gtt_offset_rotated = 0;
2430         unsigned int max_size = 0;
2431         int i, num_planes = fb->format->num_planes;
2432         unsigned int tile_size = intel_tile_size(dev_priv);
2433
2434         for (i = 0; i < num_planes; i++) {
2435                 unsigned int width, height;
2436                 unsigned int cpp, size;
2437                 u32 offset;
2438                 int x, y;
2439
2440                 cpp = fb->format->cpp[i];
2441                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2443
2444                 intel_fb_offset_to_xy(&x, &y, fb, i);
2445
2446                 /*
2447                  * The fence (if used) is aligned to the start of the object
2448                  * so having the framebuffer wrap around across the edge of the
2449                  * fenced region doesn't really work. We have no API to configure
2450                  * the fence start offset within the object (nor could we probably
2451                  * on gen2/3). So it's just easier if we just require that the
2452                  * fb layout agrees with the fence layout. We already check that the
2453                  * fb stride matches the fence stride elsewhere.
2454                  */
2455                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456                     (x + width) * cpp > fb->pitches[i]) {
2457                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2458                                       i, fb->offsets[i]);
2459                         return -EINVAL;
2460                 }
2461
2462                 /*
2463                  * First pixel of the framebuffer from
2464                  * the start of the normal gtt mapping.
2465                  */
2466                 intel_fb->normal[i].x = x;
2467                 intel_fb->normal[i].y = y;
2468
2469                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2470                                                     fb, i, fb->pitches[i],
2471                                                     DRM_ROTATE_0, tile_size);
2472                 offset /= tile_size;
2473
2474                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2475                         unsigned int tile_width, tile_height;
2476                         unsigned int pitch_tiles;
2477                         struct drm_rect r;
2478
2479                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2480
2481                         rot_info->plane[i].offset = offset;
2482                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2485
2486                         intel_fb->rotated[i].pitch =
2487                                 rot_info->plane[i].height * tile_height;
2488
2489                         /* how many tiles does this plane need */
2490                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2491                         /*
2492                          * If the plane isn't horizontally tile aligned,
2493                          * we need one more tile.
2494                          */
2495                         if (x != 0)
2496                                 size++;
2497
2498                         /* rotate the x/y offsets to match the GTT view */
2499                         r.x1 = x;
2500                         r.y1 = y;
2501                         r.x2 = x + width;
2502                         r.y2 = y + height;
2503                         drm_rect_rotate(&r,
2504                                         rot_info->plane[i].width * tile_width,
2505                                         rot_info->plane[i].height * tile_height,
2506                                         DRM_ROTATE_270);
2507                         x = r.x1;
2508                         y = r.y1;
2509
2510                         /* rotate the tile dimensions to match the GTT view */
2511                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512                         swap(tile_width, tile_height);
2513
2514                         /*
2515                          * We only keep the x/y offsets, so push all of the
2516                          * gtt offset into the x/y offsets.
2517                          */
2518                         _intel_adjust_tile_offset(&x, &y,
2519                                                   tile_width, tile_height,
2520                                                   tile_size, pitch_tiles,
2521                                                   gtt_offset_rotated * tile_size, 0);
2522
2523                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2524
2525                         /*
2526                          * First pixel of the framebuffer from
2527                          * the start of the rotated gtt mapping.
2528                          */
2529                         intel_fb->rotated[i].x = x;
2530                         intel_fb->rotated[i].y = y;
2531                 } else {
2532                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533                                             x * cpp, tile_size);
2534                 }
2535
2536                 /* how many tiles in total needed in the bo */
2537                 max_size = max(max_size, offset + size);
2538         }
2539
2540         if (max_size * tile_size > intel_fb->obj->base.size) {
2541                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542                               max_size * tile_size, intel_fb->obj->base.size);
2543                 return -EINVAL;
2544         }
2545
2546         return 0;
2547 }
2548
2549 static int i9xx_format_to_fourcc(int format)
2550 {
2551         switch (format) {
2552         case DISPPLANE_8BPP:
2553                 return DRM_FORMAT_C8;
2554         case DISPPLANE_BGRX555:
2555                 return DRM_FORMAT_XRGB1555;
2556         case DISPPLANE_BGRX565:
2557                 return DRM_FORMAT_RGB565;
2558         default:
2559         case DISPPLANE_BGRX888:
2560                 return DRM_FORMAT_XRGB8888;
2561         case DISPPLANE_RGBX888:
2562                 return DRM_FORMAT_XBGR8888;
2563         case DISPPLANE_BGRX101010:
2564                 return DRM_FORMAT_XRGB2101010;
2565         case DISPPLANE_RGBX101010:
2566                 return DRM_FORMAT_XBGR2101010;
2567         }
2568 }
2569
2570 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2571 {
2572         switch (format) {
2573         case PLANE_CTL_FORMAT_RGB_565:
2574                 return DRM_FORMAT_RGB565;
2575         default:
2576         case PLANE_CTL_FORMAT_XRGB_8888:
2577                 if (rgb_order) {
2578                         if (alpha)
2579                                 return DRM_FORMAT_ABGR8888;
2580                         else
2581                                 return DRM_FORMAT_XBGR8888;
2582                 } else {
2583                         if (alpha)
2584                                 return DRM_FORMAT_ARGB8888;
2585                         else
2586                                 return DRM_FORMAT_XRGB8888;
2587                 }
2588         case PLANE_CTL_FORMAT_XRGB_2101010:
2589                 if (rgb_order)
2590                         return DRM_FORMAT_XBGR2101010;
2591                 else
2592                         return DRM_FORMAT_XRGB2101010;
2593         }
2594 }
2595
2596 static bool
2597 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598                               struct intel_initial_plane_config *plane_config)
2599 {
2600         struct drm_device *dev = crtc->base.dev;
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2603         struct drm_i915_gem_object *obj = NULL;
2604         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605         struct drm_framebuffer *fb = &plane_config->fb->base;
2606         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608                                     PAGE_SIZE);
2609
2610         size_aligned -= base_aligned;
2611
2612         if (plane_config->size == 0)
2613                 return false;
2614
2615         /* If the FB is too big, just don't use it since fbdev is not very
2616          * important and we should probably use that space with FBC or other
2617          * features. */
2618         if (size_aligned * 2 > ggtt->stolen_usable_size)
2619                 return false;
2620
2621         mutex_lock(&dev->struct_mutex);
2622         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2623                                                              base_aligned,
2624                                                              base_aligned,
2625                                                              size_aligned);
2626         mutex_unlock(&dev->struct_mutex);
2627         if (!obj)
2628                 return false;
2629
2630         if (plane_config->tiling == I915_TILING_X)
2631                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2632
2633         mode_cmd.pixel_format = fb->format->format;
2634         mode_cmd.width = fb->width;
2635         mode_cmd.height = fb->height;
2636         mode_cmd.pitches[0] = fb->pitches[0];
2637         mode_cmd.modifier[0] = fb->modifier;
2638         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2639
2640         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2641                 DRM_DEBUG_KMS("intel fb init failed\n");
2642                 goto out_unref_obj;
2643         }
2644
2645
2646         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2647         return true;
2648
2649 out_unref_obj:
2650         i915_gem_object_put(obj);
2651         return false;
2652 }
2653
2654 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2655 static void
2656 update_state_fb(struct drm_plane *plane)
2657 {
2658         if (plane->fb == plane->state->fb)
2659                 return;
2660
2661         if (plane->state->fb)
2662                 drm_framebuffer_unreference(plane->state->fb);
2663         plane->state->fb = plane->fb;
2664         if (plane->state->fb)
2665                 drm_framebuffer_reference(plane->state->fb);
2666 }
2667
2668 static void
2669 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670                         struct intel_plane_state *plane_state,
2671                         bool visible)
2672 {
2673         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2674
2675         plane_state->base.visible = visible;
2676
2677         /* FIXME pre-g4x don't work like this */
2678         if (visible) {
2679                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680                 crtc_state->active_planes |= BIT(plane->id);
2681         } else {
2682                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683                 crtc_state->active_planes &= ~BIT(plane->id);
2684         }
2685
2686         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687                       crtc_state->base.crtc->name,
2688                       crtc_state->active_planes);
2689 }
2690
2691 static void
2692 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693                              struct intel_initial_plane_config *plane_config)
2694 {
2695         struct drm_device *dev = intel_crtc->base.dev;
2696         struct drm_i915_private *dev_priv = to_i915(dev);
2697         struct drm_crtc *c;
2698         struct drm_i915_gem_object *obj;
2699         struct drm_plane *primary = intel_crtc->base.primary;
2700         struct drm_plane_state *plane_state = primary->state;
2701         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702         struct intel_plane *intel_plane = to_intel_plane(primary);
2703         struct intel_plane_state *intel_state =
2704                 to_intel_plane_state(plane_state);
2705         struct drm_framebuffer *fb;
2706
2707         if (!plane_config->fb)
2708                 return;
2709
2710         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2711                 fb = &plane_config->fb->base;
2712                 goto valid_fb;
2713         }
2714
2715         kfree(plane_config->fb);
2716
2717         /*
2718          * Failed to alloc the obj, check to see if we should share
2719          * an fb with another CRTC instead
2720          */
2721         for_each_crtc(dev, c) {
2722                 struct intel_plane_state *state;
2723
2724                 if (c == &intel_crtc->base)
2725                         continue;
2726
2727                 if (!to_intel_crtc(c)->active)
2728                         continue;
2729
2730                 state = to_intel_plane_state(c->primary->state);
2731                 if (!state->vma)
2732                         continue;
2733
2734                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735                         fb = c->primary->fb;
2736                         drm_framebuffer_reference(fb);
2737                         goto valid_fb;
2738                 }
2739         }
2740
2741         /*
2742          * We've failed to reconstruct the BIOS FB.  Current display state
2743          * indicates that the primary plane is visible, but has a NULL FB,
2744          * which will lead to problems later if we don't fix it up.  The
2745          * simplest solution is to just disable the primary plane now and
2746          * pretend the BIOS never had it enabled.
2747          */
2748         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749                                 to_intel_plane_state(plane_state),
2750                                 false);
2751         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2752         trace_intel_disable_plane(primary, intel_crtc);
2753         intel_plane->disable_plane(primary, &intel_crtc->base);
2754
2755         return;
2756
2757 valid_fb:
2758         mutex_lock(&dev->struct_mutex);
2759         intel_state->vma =
2760                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761         mutex_unlock(&dev->struct_mutex);
2762         if (IS_ERR(intel_state->vma)) {
2763                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2765
2766                 intel_state->vma = NULL;
2767                 drm_framebuffer_unreference(fb);
2768                 return;
2769         }
2770
2771         plane_state->src_x = 0;
2772         plane_state->src_y = 0;
2773         plane_state->src_w = fb->width << 16;
2774         plane_state->src_h = fb->height << 16;
2775
2776         plane_state->crtc_x = 0;
2777         plane_state->crtc_y = 0;
2778         plane_state->crtc_w = fb->width;
2779         plane_state->crtc_h = fb->height;
2780
2781         intel_state->base.src = drm_plane_state_src(plane_state);
2782         intel_state->base.dst = drm_plane_state_dest(plane_state);
2783
2784         obj = intel_fb_obj(fb);
2785         if (i915_gem_object_is_tiled(obj))
2786                 dev_priv->preserve_bios_swizzle = true;
2787
2788         drm_framebuffer_reference(fb);
2789         primary->fb = primary->state->fb = fb;
2790         primary->crtc = primary->state->crtc = &intel_crtc->base;
2791
2792         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793                                 to_intel_plane_state(plane_state),
2794                                 true);
2795
2796         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797                   &obj->frontbuffer_bits);
2798 }
2799
2800 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801                                unsigned int rotation)
2802 {
2803         int cpp = fb->format->cpp[plane];
2804
2805         switch (fb->modifier) {
2806         case DRM_FORMAT_MOD_NONE:
2807         case I915_FORMAT_MOD_X_TILED:
2808                 switch (cpp) {
2809                 case 8:
2810                         return 4096;
2811                 case 4:
2812                 case 2:
2813                 case 1:
2814                         return 8192;
2815                 default:
2816                         MISSING_CASE(cpp);
2817                         break;
2818                 }
2819                 break;
2820         case I915_FORMAT_MOD_Y_TILED:
2821         case I915_FORMAT_MOD_Yf_TILED:
2822                 switch (cpp) {
2823                 case 8:
2824                         return 2048;
2825                 case 4:
2826                         return 4096;
2827                 case 2:
2828                 case 1:
2829                         return 8192;
2830                 default:
2831                         MISSING_CASE(cpp);
2832                         break;
2833                 }
2834                 break;
2835         default:
2836                 MISSING_CASE(fb->modifier);
2837         }
2838
2839         return 2048;
2840 }
2841
2842 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2843 {
2844         const struct drm_framebuffer *fb = plane_state->base.fb;
2845         unsigned int rotation = plane_state->base.rotation;
2846         int x = plane_state->base.src.x1 >> 16;
2847         int y = plane_state->base.src.y1 >> 16;
2848         int w = drm_rect_width(&plane_state->base.src) >> 16;
2849         int h = drm_rect_height(&plane_state->base.src) >> 16;
2850         int max_width = skl_max_plane_width(fb, 0, rotation);
2851         int max_height = 4096;
2852         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2853
2854         if (w > max_width || h > max_height) {
2855                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856                               w, h, max_width, max_height);
2857                 return -EINVAL;
2858         }
2859
2860         intel_add_fb_offsets(&x, &y, plane_state, 0);
2861         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2862         alignment = intel_surf_alignment(fb, 0);
2863
2864         /*
2865          * AUX surface offset is specified as the distance from the
2866          * main surface offset, and it must be non-negative. Make
2867          * sure that is what we will get.
2868          */
2869         if (offset > aux_offset)
2870                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871                                                   offset, aux_offset & ~(alignment - 1));
2872
2873         /*
2874          * When using an X-tiled surface, the plane blows up
2875          * if the x offset + width exceed the stride.
2876          *
2877          * TODO: linear and Y-tiled seem fine, Yf untested,
2878          */
2879         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2880                 int cpp = fb->format->cpp[0];
2881
2882                 while ((x + w) * cpp > fb->pitches[0]) {
2883                         if (offset == 0) {
2884                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2885                                 return -EINVAL;
2886                         }
2887
2888                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889                                                           offset, offset - alignment);
2890                 }
2891         }
2892
2893         plane_state->main.offset = offset;
2894         plane_state->main.x = x;
2895         plane_state->main.y = y;
2896
2897         return 0;
2898 }
2899
2900 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2901 {
2902         const struct drm_framebuffer *fb = plane_state->base.fb;
2903         unsigned int rotation = plane_state->base.rotation;
2904         int max_width = skl_max_plane_width(fb, 1, rotation);
2905         int max_height = 4096;
2906         int x = plane_state->base.src.x1 >> 17;
2907         int y = plane_state->base.src.y1 >> 17;
2908         int w = drm_rect_width(&plane_state->base.src) >> 17;
2909         int h = drm_rect_height(&plane_state->base.src) >> 17;
2910         u32 offset;
2911
2912         intel_add_fb_offsets(&x, &y, plane_state, 1);
2913         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2914
2915         /* FIXME not quite sure how/if these apply to the chroma plane */
2916         if (w > max_width || h > max_height) {
2917                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918                               w, h, max_width, max_height);
2919                 return -EINVAL;
2920         }
2921
2922         plane_state->aux.offset = offset;
2923         plane_state->aux.x = x;
2924         plane_state->aux.y = y;
2925
2926         return 0;
2927 }
2928
2929 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2930 {
2931         const struct drm_framebuffer *fb = plane_state->base.fb;
2932         unsigned int rotation = plane_state->base.rotation;
2933         int ret;
2934
2935         if (!plane_state->base.visible)
2936                 return 0;
2937
2938         /* Rotate src coordinates to match rotated GTT view */
2939         if (drm_rotation_90_or_270(rotation))
2940                 drm_rect_rotate(&plane_state->base.src,
2941                                 fb->width << 16, fb->height << 16,
2942                                 DRM_ROTATE_270);
2943
2944         /*
2945          * Handle the AUX surface first since
2946          * the main surface setup depends on it.
2947          */
2948         if (fb->format->format == DRM_FORMAT_NV12) {
2949                 ret = skl_check_nv12_aux_surface(plane_state);
2950                 if (ret)
2951                         return ret;
2952         } else {
2953                 plane_state->aux.offset = ~0xfff;
2954                 plane_state->aux.x = 0;
2955                 plane_state->aux.y = 0;
2956         }
2957
2958         ret = skl_check_main_surface(plane_state);
2959         if (ret)
2960                 return ret;
2961
2962         return 0;
2963 }
2964
2965 static void i9xx_update_primary_plane(struct drm_plane *primary,
2966                                       const struct intel_crtc_state *crtc_state,
2967                                       const struct intel_plane_state *plane_state)
2968 {
2969         struct drm_i915_private *dev_priv = to_i915(primary->dev);
2970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2971         struct drm_framebuffer *fb = plane_state->base.fb;
2972         int plane = intel_crtc->plane;
2973         u32 linear_offset;
2974         u32 dspcntr;
2975         i915_reg_t reg = DSPCNTR(plane);
2976         unsigned int rotation = plane_state->base.rotation;
2977         int x = plane_state->base.src.x1 >> 16;
2978         int y = plane_state->base.src.y1 >> 16;
2979         unsigned long irqflags;
2980
2981         dspcntr = DISPPLANE_GAMMA_ENABLE;
2982
2983         dspcntr |= DISPLAY_PLANE_ENABLE;
2984
2985         if (INTEL_GEN(dev_priv) < 4) {
2986                 if (intel_crtc->pipe == PIPE_B)
2987                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2988         }
2989
2990         switch (fb->format->format) {
2991         case DRM_FORMAT_C8:
2992                 dspcntr |= DISPPLANE_8BPP;
2993                 break;
2994         case DRM_FORMAT_XRGB1555:
2995                 dspcntr |= DISPPLANE_BGRX555;
2996                 break;
2997         case DRM_FORMAT_RGB565:
2998                 dspcntr |= DISPPLANE_BGRX565;
2999                 break;
3000         case DRM_FORMAT_XRGB8888:
3001                 dspcntr |= DISPPLANE_BGRX888;
3002                 break;
3003         case DRM_FORMAT_XBGR8888:
3004                 dspcntr |= DISPPLANE_RGBX888;
3005                 break;
3006         case DRM_FORMAT_XRGB2101010:
3007                 dspcntr |= DISPPLANE_BGRX101010;
3008                 break;
3009         case DRM_FORMAT_XBGR2101010:
3010                 dspcntr |= DISPPLANE_RGBX101010;
3011                 break;
3012         default:
3013                 BUG();
3014         }
3015
3016         if (INTEL_GEN(dev_priv) >= 4 &&
3017             fb->modifier == I915_FORMAT_MOD_X_TILED)
3018                 dspcntr |= DISPPLANE_TILED;
3019
3020         if (rotation & DRM_ROTATE_180)
3021                 dspcntr |= DISPPLANE_ROTATE_180;
3022
3023         if (rotation & DRM_REFLECT_X)
3024                 dspcntr |= DISPPLANE_MIRROR;
3025
3026         if (IS_G4X(dev_priv))
3027                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3028
3029         intel_add_fb_offsets(&x, &y, plane_state, 0);
3030
3031         if (INTEL_GEN(dev_priv) >= 4)
3032                 intel_crtc->dspaddr_offset =
3033                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3034
3035         if (rotation & DRM_ROTATE_180) {
3036                 x += crtc_state->pipe_src_w - 1;
3037                 y += crtc_state->pipe_src_h - 1;
3038         } else if (rotation & DRM_REFLECT_X) {
3039                 x += crtc_state->pipe_src_w - 1;
3040         }
3041
3042         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3043
3044         if (INTEL_GEN(dev_priv) < 4)
3045                 intel_crtc->dspaddr_offset = linear_offset;
3046
3047         intel_crtc->adjusted_x = x;
3048         intel_crtc->adjusted_y = y;
3049
3050         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3051
3052         if (INTEL_GEN(dev_priv) < 4) {
3053                 /* pipesrc and dspsize control the size that is scaled from,
3054                  * which should always be the user's requested size.
3055                  */
3056                 I915_WRITE_FW(DSPSIZE(plane),
3057                               ((crtc_state->pipe_src_h - 1) << 16) |
3058                               (crtc_state->pipe_src_w - 1));
3059                 I915_WRITE_FW(DSPPOS(plane), 0);
3060         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3061                 I915_WRITE_FW(PRIMSIZE(plane),
3062                               ((crtc_state->pipe_src_h - 1) << 16) |
3063                               (crtc_state->pipe_src_w - 1));
3064                 I915_WRITE_FW(PRIMPOS(plane), 0);
3065                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3066         }
3067
3068         I915_WRITE_FW(reg, dspcntr);
3069
3070         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3071         if (INTEL_GEN(dev_priv) >= 4) {
3072                 I915_WRITE_FW(DSPSURF(plane),
3073                               intel_plane_ggtt_offset(plane_state) +
3074                               intel_crtc->dspaddr_offset);
3075                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3076                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3077         } else {
3078                 I915_WRITE_FW(DSPADDR(plane),
3079                               intel_plane_ggtt_offset(plane_state) +
3080                               intel_crtc->dspaddr_offset);
3081         }
3082         POSTING_READ_FW(reg);
3083
3084         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3085 }
3086
3087 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3088                                        struct drm_crtc *crtc)
3089 {
3090         struct drm_device *dev = crtc->dev;
3091         struct drm_i915_private *dev_priv = to_i915(dev);
3092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093         int plane = intel_crtc->plane;
3094         unsigned long irqflags;
3095
3096         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3097
3098         I915_WRITE_FW(DSPCNTR(plane), 0);
3099         if (INTEL_INFO(dev_priv)->gen >= 4)
3100                 I915_WRITE_FW(DSPSURF(plane), 0);
3101         else
3102                 I915_WRITE_FW(DSPADDR(plane), 0);
3103         POSTING_READ_FW(DSPCNTR(plane));
3104
3105         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3106 }
3107
3108 static void ironlake_update_primary_plane(struct drm_plane *primary,
3109                                           const struct intel_crtc_state *crtc_state,
3110                                           const struct intel_plane_state *plane_state)
3111 {
3112         struct drm_device *dev = primary->dev;
3113         struct drm_i915_private *dev_priv = to_i915(dev);
3114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3115         struct drm_framebuffer *fb = plane_state->base.fb;
3116         int plane = intel_crtc->plane;
3117         u32 linear_offset;
3118         u32 dspcntr;
3119         i915_reg_t reg = DSPCNTR(plane);
3120         unsigned int rotation = plane_state->base.rotation;
3121         int x = plane_state->base.src.x1 >> 16;
3122         int y = plane_state->base.src.y1 >> 16;
3123         unsigned long irqflags;
3124
3125         dspcntr = DISPPLANE_GAMMA_ENABLE;
3126         dspcntr |= DISPLAY_PLANE_ENABLE;
3127
3128         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3129                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3130
3131         switch (fb->format->format) {
3132         case DRM_FORMAT_C8:
3133                 dspcntr |= DISPPLANE_8BPP;
3134                 break;
3135         case DRM_FORMAT_RGB565:
3136                 dspcntr |= DISPPLANE_BGRX565;
3137                 break;
3138         case DRM_FORMAT_XRGB8888:
3139                 dspcntr |= DISPPLANE_BGRX888;
3140                 break;
3141         case DRM_FORMAT_XBGR8888:
3142                 dspcntr |= DISPPLANE_RGBX888;
3143                 break;
3144         case DRM_FORMAT_XRGB2101010:
3145                 dspcntr |= DISPPLANE_BGRX101010;
3146                 break;
3147         case DRM_FORMAT_XBGR2101010:
3148                 dspcntr |= DISPPLANE_RGBX101010;
3149                 break;
3150         default:
3151                 BUG();
3152         }
3153
3154         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3155                 dspcntr |= DISPPLANE_TILED;
3156
3157         if (rotation & DRM_ROTATE_180)
3158                 dspcntr |= DISPPLANE_ROTATE_180;
3159
3160         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3161                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3162
3163         intel_add_fb_offsets(&x, &y, plane_state, 0);
3164
3165         intel_crtc->dspaddr_offset =
3166                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3167
3168         /* HSW+ does this automagically in hardware */
3169         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3170             rotation & DRM_ROTATE_180) {
3171                 x += crtc_state->pipe_src_w - 1;
3172                 y += crtc_state->pipe_src_h - 1;
3173         }
3174
3175         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3176
3177         intel_crtc->adjusted_x = x;
3178         intel_crtc->adjusted_y = y;
3179
3180         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3181
3182         I915_WRITE_FW(reg, dspcntr);
3183
3184         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3185         I915_WRITE_FW(DSPSURF(plane),
3186                       intel_plane_ggtt_offset(plane_state) +
3187                       intel_crtc->dspaddr_offset);
3188         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3189                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3190         } else {
3191                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3192                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3193         }
3194         POSTING_READ_FW(reg);
3195
3196         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3197 }
3198
3199 static u32
3200 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3201 {
3202         if (fb->modifier == DRM_FORMAT_MOD_NONE)
3203                 return 64;
3204         else
3205                 return intel_tile_width_bytes(fb, plane);
3206 }
3207
3208 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3209 {
3210         struct drm_device *dev = intel_crtc->base.dev;
3211         struct drm_i915_private *dev_priv = to_i915(dev);
3212
3213         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3214         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3215         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3216 }
3217
3218 /*
3219  * This function detaches (aka. unbinds) unused scalers in hardware
3220  */
3221 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3222 {
3223         struct intel_crtc_scaler_state *scaler_state;
3224         int i;
3225
3226         scaler_state = &intel_crtc->config->scaler_state;
3227
3228         /* loop through and disable scalers that aren't in use */
3229         for (i = 0; i < intel_crtc->num_scalers; i++) {
3230                 if (!scaler_state->scalers[i].in_use)
3231                         skl_detach_scaler(intel_crtc, i);
3232         }
3233 }
3234
3235 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3236                      unsigned int rotation)
3237 {
3238         u32 stride;
3239
3240         if (plane >= fb->format->num_planes)
3241                 return 0;
3242
3243         stride = intel_fb_pitch(fb, plane, rotation);
3244
3245         /*
3246          * The stride is either expressed as a multiple of 64 bytes chunks for
3247          * linear buffers or in number of tiles for tiled buffers.
3248          */
3249         if (drm_rotation_90_or_270(rotation))
3250                 stride /= intel_tile_height(fb, plane);
3251         else
3252                 stride /= intel_fb_stride_alignment(fb, plane);
3253
3254         return stride;
3255 }
3256
3257 u32 skl_plane_ctl_format(uint32_t pixel_format)
3258 {
3259         switch (pixel_format) {
3260         case DRM_FORMAT_C8:
3261                 return PLANE_CTL_FORMAT_INDEXED;
3262         case DRM_FORMAT_RGB565:
3263                 return PLANE_CTL_FORMAT_RGB_565;
3264         case DRM_FORMAT_XBGR8888:
3265                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3266         case DRM_FORMAT_XRGB8888:
3267                 return PLANE_CTL_FORMAT_XRGB_8888;
3268         /*
3269          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3270          * to be already pre-multiplied. We need to add a knob (or a different
3271          * DRM_FORMAT) for user-space to configure that.
3272          */
3273         case DRM_FORMAT_ABGR8888:
3274                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3275                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3276         case DRM_FORMAT_ARGB8888:
3277                 return PLANE_CTL_FORMAT_XRGB_8888 |
3278                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3279         case DRM_FORMAT_XRGB2101010:
3280                 return PLANE_CTL_FORMAT_XRGB_2101010;
3281         case DRM_FORMAT_XBGR2101010:
3282                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3283         case DRM_FORMAT_YUYV:
3284                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3285         case DRM_FORMAT_YVYU:
3286                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3287         case DRM_FORMAT_UYVY:
3288                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3289         case DRM_FORMAT_VYUY:
3290                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3291         default:
3292                 MISSING_CASE(pixel_format);
3293         }
3294
3295         return 0;
3296 }
3297
3298 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3299 {
3300         switch (fb_modifier) {
3301         case DRM_FORMAT_MOD_NONE:
3302                 break;
3303         case I915_FORMAT_MOD_X_TILED:
3304                 return PLANE_CTL_TILED_X;
3305         case I915_FORMAT_MOD_Y_TILED:
3306                 return PLANE_CTL_TILED_Y;
3307         case I915_FORMAT_MOD_Yf_TILED:
3308                 return PLANE_CTL_TILED_YF;
3309         default:
3310                 MISSING_CASE(fb_modifier);
3311         }
3312
3313         return 0;
3314 }
3315
3316 u32 skl_plane_ctl_rotation(unsigned int rotation)
3317 {
3318         switch (rotation) {
3319         case DRM_ROTATE_0:
3320                 break;
3321         /*
3322          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3323          * while i915 HW rotation is clockwise, thats why this swapping.
3324          */
3325         case DRM_ROTATE_90:
3326                 return PLANE_CTL_ROTATE_270;
3327         case DRM_ROTATE_180:
3328                 return PLANE_CTL_ROTATE_180;
3329         case DRM_ROTATE_270:
3330                 return PLANE_CTL_ROTATE_90;
3331         default:
3332                 MISSING_CASE(rotation);
3333         }
3334
3335         return 0;
3336 }
3337
3338 static void skylake_update_primary_plane(struct drm_plane *plane,
3339                                          const struct intel_crtc_state *crtc_state,
3340                                          const struct intel_plane_state *plane_state)
3341 {
3342         struct drm_device *dev = plane->dev;
3343         struct drm_i915_private *dev_priv = to_i915(dev);
3344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3345         struct drm_framebuffer *fb = plane_state->base.fb;
3346         enum plane_id plane_id = to_intel_plane(plane)->id;
3347         enum pipe pipe = to_intel_plane(plane)->pipe;
3348         u32 plane_ctl;
3349         unsigned int rotation = plane_state->base.rotation;
3350         u32 stride = skl_plane_stride(fb, 0, rotation);
3351         u32 surf_addr = plane_state->main.offset;
3352         int scaler_id = plane_state->scaler_id;
3353         int src_x = plane_state->main.x;
3354         int src_y = plane_state->main.y;
3355         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3356         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3357         int dst_x = plane_state->base.dst.x1;
3358         int dst_y = plane_state->base.dst.y1;
3359         int dst_w = drm_rect_width(&plane_state->base.dst);
3360         int dst_h = drm_rect_height(&plane_state->base.dst);
3361         unsigned long irqflags;
3362
3363         plane_ctl = PLANE_CTL_ENABLE;
3364
3365         if (!IS_GEMINILAKE(dev_priv)) {
3366                 plane_ctl |=
3367                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3368                         PLANE_CTL_PIPE_CSC_ENABLE |
3369                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3370         }
3371
3372         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3373         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3374         plane_ctl |= skl_plane_ctl_rotation(rotation);
3375
3376         /* Sizes are 0 based */
3377         src_w--;
3378         src_h--;
3379         dst_w--;
3380         dst_h--;
3381
3382         intel_crtc->dspaddr_offset = surf_addr;
3383
3384         intel_crtc->adjusted_x = src_x;
3385         intel_crtc->adjusted_y = src_y;
3386
3387         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3388
3389         if (IS_GEMINILAKE(dev_priv)) {
3390                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3391                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3392                               PLANE_COLOR_PIPE_CSC_ENABLE |
3393                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3394         }
3395
3396         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3397         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3398         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3399         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3400
3401         if (scaler_id >= 0) {
3402                 uint32_t ps_ctrl = 0;
3403
3404                 WARN_ON(!dst_w || !dst_h);
3405                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3406                         crtc_state->scaler_state.scalers[scaler_id].mode;
3407                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3408                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3409                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3410                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3411                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3412         } else {
3413                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3414         }
3415
3416         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3417                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3418
3419         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3420
3421         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3422 }
3423
3424 static void skylake_disable_primary_plane(struct drm_plane *primary,
3425                                           struct drm_crtc *crtc)
3426 {
3427         struct drm_device *dev = crtc->dev;
3428         struct drm_i915_private *dev_priv = to_i915(dev);
3429         enum plane_id plane_id = to_intel_plane(primary)->id;
3430         enum pipe pipe = to_intel_plane(primary)->pipe;
3431         unsigned long irqflags;
3432
3433         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3434
3435         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3436         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3437         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3438
3439         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3440 }
3441
3442 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3443 static int
3444 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3445                            int x, int y, enum mode_set_atomic state)
3446 {
3447         /* Support for kgdboc is disabled, this needs a major rework. */
3448         DRM_ERROR("legacy panic handler not supported any more.\n");
3449
3450         return -ENODEV;
3451 }
3452
3453 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3454 {
3455         struct intel_crtc *crtc;
3456
3457         for_each_intel_crtc(&dev_priv->drm, crtc)
3458                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3459 }
3460
3461 static void intel_update_primary_planes(struct drm_device *dev)
3462 {
3463         struct drm_crtc *crtc;
3464
3465         for_each_crtc(dev, crtc) {
3466                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3467                 struct intel_plane_state *plane_state =
3468                         to_intel_plane_state(plane->base.state);
3469
3470                 if (plane_state->base.visible) {
3471                         trace_intel_update_plane(&plane->base,
3472                                                  to_intel_crtc(crtc));
3473
3474                         plane->update_plane(&plane->base,
3475                                             to_intel_crtc_state(crtc->state),
3476                                             plane_state);
3477                 }
3478         }
3479 }
3480
3481 static int
3482 __intel_display_resume(struct drm_device *dev,
3483                        struct drm_atomic_state *state,
3484                        struct drm_modeset_acquire_ctx *ctx)
3485 {
3486         struct drm_crtc_state *crtc_state;
3487         struct drm_crtc *crtc;
3488         int i, ret;
3489
3490         intel_modeset_setup_hw_state(dev);
3491         i915_redisable_vga(to_i915(dev));
3492
3493         if (!state)
3494                 return 0;
3495
3496         /*
3497          * We've duplicated the state, pointers to the old state are invalid.
3498          *
3499          * Don't attempt to use the old state until we commit the duplicated state.
3500          */
3501         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3502                 /*
3503                  * Force recalculation even if we restore
3504                  * current state. With fast modeset this may not result
3505                  * in a modeset when the state is compatible.
3506                  */
3507                 crtc_state->mode_changed = true;
3508         }
3509
3510         /* ignore any reset values/BIOS leftovers in the WM registers */
3511         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3512                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3513
3514         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3515
3516         WARN_ON(ret == -EDEADLK);
3517         return ret;
3518 }
3519
3520 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3521 {
3522         return intel_has_gpu_reset(dev_priv) &&
3523                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3524 }
3525
3526 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3527 {
3528         struct drm_device *dev = &dev_priv->drm;
3529         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3530         struct drm_atomic_state *state;
3531         int ret;
3532
3533         /*
3534          * Need mode_config.mutex so that we don't
3535          * trample ongoing ->detect() and whatnot.
3536          */
3537         mutex_lock(&dev->mode_config.mutex);
3538         drm_modeset_acquire_init(ctx, 0);
3539         while (1) {
3540                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3541                 if (ret != -EDEADLK)
3542                         break;
3543
3544                 drm_modeset_backoff(ctx);
3545         }
3546
3547         /* reset doesn't touch the display, but flips might get nuked anyway, */
3548         if (!i915.force_reset_modeset_test &&
3549             !gpu_reset_clobbers_display(dev_priv))
3550                 return;
3551
3552         /*
3553          * Disabling the crtcs gracefully seems nicer. Also the
3554          * g33 docs say we should at least disable all the planes.
3555          */
3556         state = drm_atomic_helper_duplicate_state(dev, ctx);
3557         if (IS_ERR(state)) {
3558                 ret = PTR_ERR(state);
3559                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3560                 return;
3561         }
3562
3563         ret = drm_atomic_helper_disable_all(dev, ctx);
3564         if (ret) {
3565                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3566                 drm_atomic_state_put(state);
3567                 return;
3568         }
3569
3570         dev_priv->modeset_restore_state = state;
3571         state->acquire_ctx = ctx;
3572 }
3573
3574 void intel_finish_reset(struct drm_i915_private *dev_priv)
3575 {
3576         struct drm_device *dev = &dev_priv->drm;
3577         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3578         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3579         int ret;
3580
3581         /*
3582          * Flips in the rings will be nuked by the reset,
3583          * so complete all pending flips so that user space
3584          * will get its events and not get stuck.
3585          */
3586         intel_complete_page_flips(dev_priv);
3587
3588         dev_priv->modeset_restore_state = NULL;
3589
3590         /* reset doesn't touch the display */
3591         if (!gpu_reset_clobbers_display(dev_priv)) {
3592                 if (!state) {
3593                         /*
3594                          * Flips in the rings have been nuked by the reset,
3595                          * so update the base address of all primary
3596                          * planes to the the last fb to make sure we're
3597                          * showing the correct fb after a reset.
3598                          *
3599                          * FIXME: Atomic will make this obsolete since we won't schedule
3600                          * CS-based flips (which might get lost in gpu resets) any more.
3601                          */
3602                         intel_update_primary_planes(dev);
3603                 } else {
3604                         ret = __intel_display_resume(dev, state, ctx);
3605                         if (ret)
3606                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3607                 }
3608         } else {
3609                 /*
3610                  * The display has been reset as well,
3611                  * so need a full re-initialization.
3612                  */
3613                 intel_runtime_pm_disable_interrupts(dev_priv);
3614                 intel_runtime_pm_enable_interrupts(dev_priv);
3615
3616                 intel_pps_unlock_regs_wa(dev_priv);
3617                 intel_modeset_init_hw(dev);
3618
3619                 spin_lock_irq(&dev_priv->irq_lock);
3620                 if (dev_priv->display.hpd_irq_setup)
3621                         dev_priv->display.hpd_irq_setup(dev_priv);
3622                 spin_unlock_irq(&dev_priv->irq_lock);
3623
3624                 ret = __intel_display_resume(dev, state, ctx);
3625                 if (ret)
3626                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3627
3628                 intel_hpd_init(dev_priv);
3629         }
3630
3631         if (state)
3632                 drm_atomic_state_put(state);
3633         drm_modeset_drop_locks(ctx);
3634         drm_modeset_acquire_fini(ctx);
3635         mutex_unlock(&dev->mode_config.mutex);
3636 }
3637
3638 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3639 {
3640         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3641
3642         if (i915_reset_backoff(error))
3643                 return true;
3644
3645         if (crtc->reset_count != i915_reset_count(error))
3646                 return true;
3647
3648         return false;
3649 }
3650
3651 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3652 {
3653         struct drm_device *dev = crtc->dev;
3654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655         bool pending;
3656
3657         if (abort_flip_on_reset(intel_crtc))
3658                 return false;
3659
3660         spin_lock_irq(&dev->event_lock);
3661         pending = to_intel_crtc(crtc)->flip_work != NULL;
3662         spin_unlock_irq(&dev->event_lock);
3663
3664         return pending;
3665 }
3666
3667 static void intel_update_pipe_config(struct intel_crtc *crtc,
3668                                      struct intel_crtc_state *old_crtc_state)
3669 {
3670         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3671         struct intel_crtc_state *pipe_config =
3672                 to_intel_crtc_state(crtc->base.state);
3673
3674         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3675         crtc->base.mode = crtc->base.state->mode;
3676
3677         /*
3678          * Update pipe size and adjust fitter if needed: the reason for this is
3679          * that in compute_mode_changes we check the native mode (not the pfit
3680          * mode) to see if we can flip rather than do a full mode set. In the
3681          * fastboot case, we'll flip, but if we don't update the pipesrc and
3682          * pfit state, we'll end up with a big fb scanned out into the wrong
3683          * sized surface.
3684          */
3685
3686         I915_WRITE(PIPESRC(crtc->pipe),
3687                    ((pipe_config->pipe_src_w - 1) << 16) |
3688                    (pipe_config->pipe_src_h - 1));
3689
3690         /* on skylake this is done by detaching scalers */
3691         if (INTEL_GEN(dev_priv) >= 9) {
3692                 skl_detach_scalers(crtc);
3693
3694                 if (pipe_config->pch_pfit.enabled)
3695                         skylake_pfit_enable(crtc);
3696         } else if (HAS_PCH_SPLIT(dev_priv)) {
3697                 if (pipe_config->pch_pfit.enabled)
3698                         ironlake_pfit_enable(crtc);
3699                 else if (old_crtc_state->pch_pfit.enabled)
3700                         ironlake_pfit_disable(crtc, true);
3701         }
3702 }
3703
3704 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3705 {
3706         struct drm_device *dev = crtc->base.dev;
3707         struct drm_i915_private *dev_priv = to_i915(dev);
3708         int pipe = crtc->pipe;
3709         i915_reg_t reg;
3710         u32 temp;
3711
3712         /* enable normal train */
3713         reg = FDI_TX_CTL(pipe);
3714         temp = I915_READ(reg);
3715         if (IS_IVYBRIDGE(dev_priv)) {
3716                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3717                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3718         } else {
3719                 temp &= ~FDI_LINK_TRAIN_NONE;
3720                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3721         }
3722         I915_WRITE(reg, temp);
3723
3724         reg = FDI_RX_CTL(pipe);
3725         temp = I915_READ(reg);
3726         if (HAS_PCH_CPT(dev_priv)) {
3727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3729         } else {
3730                 temp &= ~FDI_LINK_TRAIN_NONE;
3731                 temp |= FDI_LINK_TRAIN_NONE;
3732         }
3733         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3734
3735         /* wait one idle pattern time */
3736         POSTING_READ(reg);
3737         udelay(1000);
3738
3739         /* IVB wants error correction enabled */
3740         if (IS_IVYBRIDGE(dev_priv))
3741                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3742                            FDI_FE_ERRC_ENABLE);
3743 }
3744
3745 /* The FDI link training functions for ILK/Ibexpeak. */
3746 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3747                                     const struct intel_crtc_state *crtc_state)
3748 {
3749         struct drm_device *dev = crtc->base.dev;
3750         struct drm_i915_private *dev_priv = to_i915(dev);
3751         int pipe = crtc->pipe;
3752         i915_reg_t reg;
3753         u32 temp, tries;
3754
3755         /* FDI needs bits from pipe first */
3756         assert_pipe_enabled(dev_priv, pipe);
3757
3758         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3759            for train result */
3760         reg = FDI_RX_IMR(pipe);
3761         temp = I915_READ(reg);
3762         temp &= ~FDI_RX_SYMBOL_LOCK;
3763         temp &= ~FDI_RX_BIT_LOCK;
3764         I915_WRITE(reg, temp);
3765         I915_READ(reg);
3766         udelay(150);
3767
3768         /* enable CPU FDI TX and PCH FDI RX */
3769         reg = FDI_TX_CTL(pipe);
3770         temp = I915_READ(reg);
3771         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3772         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3773         temp &= ~FDI_LINK_TRAIN_NONE;
3774         temp |= FDI_LINK_TRAIN_PATTERN_1;
3775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3776
3777         reg = FDI_RX_CTL(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~FDI_LINK_TRAIN_NONE;
3780         temp |= FDI_LINK_TRAIN_PATTERN_1;
3781         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3782
3783         POSTING_READ(reg);
3784         udelay(150);
3785
3786         /* Ironlake workaround, enable clock pointer after FDI enable*/
3787         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3788         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3789                    FDI_RX_PHASE_SYNC_POINTER_EN);
3790
3791         reg = FDI_RX_IIR(pipe);
3792         for (tries = 0; tries < 5; tries++) {
3793                 temp = I915_READ(reg);
3794                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3795
3796                 if ((temp & FDI_RX_BIT_LOCK)) {
3797                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3798                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3799                         break;
3800                 }
3801         }
3802         if (tries == 5)
3803                 DRM_ERROR("FDI train 1 fail!\n");
3804
3805         /* Train 2 */
3806         reg = FDI_TX_CTL(pipe);
3807         temp = I915_READ(reg);
3808         temp &= ~FDI_LINK_TRAIN_NONE;
3809         temp |= FDI_LINK_TRAIN_PATTERN_2;
3810         I915_WRITE(reg, temp);
3811
3812         reg = FDI_RX_CTL(pipe);
3813         temp = I915_READ(reg);
3814         temp &= ~FDI_LINK_TRAIN_NONE;
3815         temp |= FDI_LINK_TRAIN_PATTERN_2;
3816         I915_WRITE(reg, temp);
3817
3818         POSTING_READ(reg);
3819         udelay(150);
3820
3821         reg = FDI_RX_IIR(pipe);
3822         for (tries = 0; tries < 5; tries++) {
3823                 temp = I915_READ(reg);
3824                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3825
3826                 if (temp & FDI_RX_SYMBOL_LOCK) {
3827                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3828                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3829                         break;
3830                 }
3831         }
3832         if (tries == 5)
3833                 DRM_ERROR("FDI train 2 fail!\n");
3834
3835         DRM_DEBUG_KMS("FDI train done\n");
3836
3837 }
3838
3839 static const int snb_b_fdi_train_param[] = {
3840         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3841         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3842         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3843         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3844 };
3845
3846 /* The FDI link training functions for SNB/Cougarpoint. */
3847 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3848                                 const struct intel_crtc_state *crtc_state)
3849 {
3850         struct drm_device *dev = crtc->base.dev;
3851         struct drm_i915_private *dev_priv = to_i915(dev);
3852         int pipe = crtc->pipe;
3853         i915_reg_t reg;
3854         u32 temp, i, retry;
3855
3856         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3857            for train result */
3858         reg = FDI_RX_IMR(pipe);
3859         temp = I915_READ(reg);
3860         temp &= ~FDI_RX_SYMBOL_LOCK;
3861         temp &= ~FDI_RX_BIT_LOCK;
3862         I915_WRITE(reg, temp);
3863
3864         POSTING_READ(reg);
3865         udelay(150);
3866
3867         /* enable CPU FDI TX and PCH FDI RX */
3868         reg = FDI_TX_CTL(pipe);
3869         temp = I915_READ(reg);
3870         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3871         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3872         temp &= ~FDI_LINK_TRAIN_NONE;
3873         temp |= FDI_LINK_TRAIN_PATTERN_1;
3874         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3875         /* SNB-B */
3876         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3877         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3878
3879         I915_WRITE(FDI_RX_MISC(pipe),
3880                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3881
3882         reg = FDI_RX_CTL(pipe);
3883         temp = I915_READ(reg);
3884         if (HAS_PCH_CPT(dev_priv)) {
3885                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3886                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3887         } else {
3888                 temp &= ~FDI_LINK_TRAIN_NONE;
3889                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3890         }
3891         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3892
3893         POSTING_READ(reg);
3894         udelay(150);
3895
3896         for (i = 0; i < 4; i++) {
3897                 reg = FDI_TX_CTL(pipe);
3898                 temp = I915_READ(reg);
3899                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3900                 temp |= snb_b_fdi_train_param[i];
3901                 I915_WRITE(reg, temp);
3902
3903                 POSTING_READ(reg);
3904                 udelay(500);
3905
3906                 for (retry = 0; retry < 5; retry++) {
3907                         reg = FDI_RX_IIR(pipe);
3908                         temp = I915_READ(reg);
3909                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3910                         if (temp & FDI_RX_BIT_LOCK) {
3911                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3912                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3913                                 break;
3914                         }
3915                         udelay(50);
3916                 }
3917                 if (retry < 5)
3918                         break;
3919         }
3920         if (i == 4)
3921                 DRM_ERROR("FDI train 1 fail!\n");
3922
3923         /* Train 2 */
3924         reg = FDI_TX_CTL(pipe);
3925         temp = I915_READ(reg);
3926         temp &= ~FDI_LINK_TRAIN_NONE;
3927         temp |= FDI_LINK_TRAIN_PATTERN_2;
3928         if (IS_GEN6(dev_priv)) {
3929                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3930                 /* SNB-B */
3931                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3932         }
3933         I915_WRITE(reg, temp);
3934
3935         reg = FDI_RX_CTL(pipe);
3936         temp = I915_READ(reg);
3937         if (HAS_PCH_CPT(dev_priv)) {
3938                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3939                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3940         } else {
3941                 temp &= ~FDI_LINK_TRAIN_NONE;
3942                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3943         }
3944         I915_WRITE(reg, temp);
3945
3946         POSTING_READ(reg);
3947         udelay(150);
3948
3949         for (i = 0; i < 4; i++) {
3950                 reg = FDI_TX_CTL(pipe);
3951                 temp = I915_READ(reg);
3952                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3953                 temp |= snb_b_fdi_train_param[i];
3954                 I915_WRITE(reg, temp);
3955
3956                 POSTING_READ(reg);
3957                 udelay(500);
3958
3959                 for (retry = 0; retry < 5; retry++) {
3960                         reg = FDI_RX_IIR(pipe);
3961                         temp = I915_READ(reg);
3962                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3963                         if (temp & FDI_RX_SYMBOL_LOCK) {
3964                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3965                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3966                                 break;
3967                         }
3968                         udelay(50);
3969                 }
3970                 if (retry < 5)
3971                         break;
3972         }
3973         if (i == 4)
3974                 DRM_ERROR("FDI train 2 fail!\n");
3975
3976         DRM_DEBUG_KMS("FDI train done.\n");
3977 }
3978
3979 /* Manual link training for Ivy Bridge A0 parts */
3980 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3981                                       const struct intel_crtc_state *crtc_state)
3982 {
3983         struct drm_device *dev = crtc->base.dev;
3984         struct drm_i915_private *dev_priv = to_i915(dev);
3985         int pipe = crtc->pipe;
3986         i915_reg_t reg;
3987         u32 temp, i, j;
3988
3989         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3990            for train result */
3991         reg = FDI_RX_IMR(pipe);
3992         temp = I915_READ(reg);
3993         temp &= ~FDI_RX_SYMBOL_LOCK;
3994         temp &= ~FDI_RX_BIT_LOCK;
3995         I915_WRITE(reg, temp);
3996
3997         POSTING_READ(reg);
3998         udelay(150);
3999
4000         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4001                       I915_READ(FDI_RX_IIR(pipe)));
4002
4003         /* Try each vswing and preemphasis setting twice before moving on */
4004         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4005                 /* disable first in case we need to retry */
4006                 reg = FDI_TX_CTL(pipe);
4007                 temp = I915_READ(reg);
4008                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4009                 temp &= ~FDI_TX_ENABLE;
4010                 I915_WRITE(reg, temp);
4011
4012                 reg = FDI_RX_CTL(pipe);
4013                 temp = I915_READ(reg);
4014                 temp &= ~FDI_LINK_TRAIN_AUTO;
4015                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4016                 temp &= ~FDI_RX_ENABLE;
4017                 I915_WRITE(reg, temp);
4018
4019                 /* enable CPU FDI TX and PCH FDI RX */
4020                 reg = FDI_TX_CTL(pipe);
4021                 temp = I915_READ(reg);
4022                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4023                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4024                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4025                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4026                 temp |= snb_b_fdi_train_param[j/2];
4027                 temp |= FDI_COMPOSITE_SYNC;
4028                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4029
4030                 I915_WRITE(FDI_RX_MISC(pipe),
4031                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4032
4033                 reg = FDI_RX_CTL(pipe);
4034                 temp = I915_READ(reg);
4035                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4036                 temp |= FDI_COMPOSITE_SYNC;
4037                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4038
4039                 POSTING_READ(reg);
4040                 udelay(1); /* should be 0.5us */
4041
4042                 for (i = 0; i < 4; i++) {
4043                         reg = FDI_RX_IIR(pipe);
4044                         temp = I915_READ(reg);
4045                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4046
4047                         if (temp & FDI_RX_BIT_LOCK ||
4048                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4049                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4050                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4051                                               i);
4052                                 break;
4053                         }
4054                         udelay(1); /* should be 0.5us */
4055                 }
4056                 if (i == 4) {
4057                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4058                         continue;
4059                 }
4060
4061                 /* Train 2 */
4062                 reg = FDI_TX_CTL(pipe);
4063                 temp = I915_READ(reg);
4064                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4065                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4066                 I915_WRITE(reg, temp);
4067
4068                 reg = FDI_RX_CTL(pipe);
4069                 temp = I915_READ(reg);
4070                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4071                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4072                 I915_WRITE(reg, temp);
4073
4074                 POSTING_READ(reg);
4075                 udelay(2); /* should be 1.5us */
4076
4077                 for (i = 0; i < 4; i++) {
4078                         reg = FDI_RX_IIR(pipe);
4079                         temp = I915_READ(reg);
4080                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4081
4082                         if (temp & FDI_RX_SYMBOL_LOCK ||
4083                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4084                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4085                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4086                                               i);
4087                                 goto train_done;
4088                         }
4089                         udelay(2); /* should be 1.5us */
4090                 }
4091                 if (i == 4)
4092                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4093         }
4094
4095 train_done:
4096         DRM_DEBUG_KMS("FDI train done.\n");
4097 }
4098
4099 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4100 {
4101         struct drm_device *dev = intel_crtc->base.dev;
4102         struct drm_i915_private *dev_priv = to_i915(dev);
4103         int pipe = intel_crtc->pipe;
4104         i915_reg_t reg;
4105         u32 temp;
4106
4107         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4108         reg = FDI_RX_CTL(pipe);
4109         temp = I915_READ(reg);
4110         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4111         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4112         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4113         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4114
4115         POSTING_READ(reg);
4116         udelay(200);
4117
4118         /* Switch from Rawclk to PCDclk */
4119         temp = I915_READ(reg);
4120         I915_WRITE(reg, temp | FDI_PCDCLK);
4121
4122         POSTING_READ(reg);
4123         udelay(200);
4124
4125         /* Enable CPU FDI TX PLL, always on for Ironlake */
4126         reg = FDI_TX_CTL(pipe);
4127         temp = I915_READ(reg);
4128         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4129                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4130
4131                 POSTING_READ(reg);
4132                 udelay(100);
4133         }
4134 }
4135
4136 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4137 {
4138         struct drm_device *dev = intel_crtc->base.dev;
4139         struct drm_i915_private *dev_priv = to_i915(dev);
4140         int pipe = intel_crtc->pipe;
4141         i915_reg_t reg;
4142         u32 temp;
4143
4144         /* Switch from PCDclk to Rawclk */
4145         reg = FDI_RX_CTL(pipe);
4146         temp = I915_READ(reg);
4147         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4148
4149         /* Disable CPU FDI TX PLL */
4150         reg = FDI_TX_CTL(pipe);
4151         temp = I915_READ(reg);
4152         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4153
4154         POSTING_READ(reg);
4155         udelay(100);
4156
4157         reg = FDI_RX_CTL(pipe);
4158         temp = I915_READ(reg);
4159         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4160
4161         /* Wait for the clocks to turn off. */
4162         POSTING_READ(reg);
4163         udelay(100);
4164 }
4165
4166 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4167 {
4168         struct drm_device *dev = crtc->dev;
4169         struct drm_i915_private *dev_priv = to_i915(dev);
4170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4171         int pipe = intel_crtc->pipe;
4172         i915_reg_t reg;
4173         u32 temp;
4174
4175         /* disable CPU FDI tx and PCH FDI rx */
4176         reg = FDI_TX_CTL(pipe);
4177         temp = I915_READ(reg);
4178         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4179         POSTING_READ(reg);
4180
4181         reg = FDI_RX_CTL(pipe);
4182         temp = I915_READ(reg);
4183         temp &= ~(0x7 << 16);
4184         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4185         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4186
4187         POSTING_READ(reg);
4188         udelay(100);
4189
4190         /* Ironlake workaround, disable clock pointer after downing FDI */
4191         if (HAS_PCH_IBX(dev_priv))
4192                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4193
4194         /* still set train pattern 1 */
4195         reg = FDI_TX_CTL(pipe);
4196         temp = I915_READ(reg);
4197         temp &= ~FDI_LINK_TRAIN_NONE;
4198         temp |= FDI_LINK_TRAIN_PATTERN_1;
4199         I915_WRITE(reg, temp);
4200
4201         reg = FDI_RX_CTL(pipe);
4202         temp = I915_READ(reg);
4203         if (HAS_PCH_CPT(dev_priv)) {
4204                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4205                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4206         } else {
4207                 temp &= ~FDI_LINK_TRAIN_NONE;
4208                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4209         }
4210         /* BPC in FDI rx is consistent with that in PIPECONF */
4211         temp &= ~(0x07 << 16);
4212         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4213         I915_WRITE(reg, temp);
4214
4215         POSTING_READ(reg);
4216         udelay(100);
4217 }
4218
4219 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4220 {
4221         struct intel_crtc *crtc;
4222
4223         /* Note that we don't need to be called with mode_config.lock here
4224          * as our list of CRTC objects is static for the lifetime of the
4225          * device and so cannot disappear as we iterate. Similarly, we can
4226          * happily treat the predicates as racy, atomic checks as userspace
4227          * cannot claim and pin a new fb without at least acquring the
4228          * struct_mutex and so serialising with us.
4229          */
4230         for_each_intel_crtc(&dev_priv->drm, crtc) {
4231                 if (atomic_read(&crtc->unpin_work_count) == 0)
4232                         continue;
4233
4234                 if (crtc->flip_work)
4235                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4236
4237                 return true;
4238         }
4239
4240         return false;
4241 }
4242
4243 static void page_flip_completed(struct intel_crtc *intel_crtc)
4244 {
4245         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4246         struct intel_flip_work *work = intel_crtc->flip_work;
4247
4248         intel_crtc->flip_work = NULL;
4249
4250         if (work->event)
4251                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4252
4253         drm_crtc_vblank_put(&intel_crtc->base);
4254
4255         wake_up_all(&dev_priv->pending_flip_queue);
4256         trace_i915_flip_complete(intel_crtc->plane,
4257                                  work->pending_flip_obj);
4258
4259         queue_work(dev_priv->wq, &work->unpin_work);
4260 }
4261
4262 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4263 {
4264         struct drm_device *dev = crtc->dev;
4265         struct drm_i915_private *dev_priv = to_i915(dev);
4266         long ret;
4267
4268         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4269
4270         ret = wait_event_interruptible_timeout(
4271                                         dev_priv->pending_flip_queue,
4272                                         !intel_crtc_has_pending_flip(crtc),
4273                                         60*HZ);
4274
4275         if (ret < 0)
4276                 return ret;
4277
4278         if (ret == 0) {
4279                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4280                 struct intel_flip_work *work;
4281
4282                 spin_lock_irq(&dev->event_lock);
4283                 work = intel_crtc->flip_work;
4284                 if (work && !is_mmio_work(work)) {
4285                         WARN_ONCE(1, "Removing stuck page flip\n");
4286                         page_flip_completed(intel_crtc);
4287                 }
4288                 spin_unlock_irq(&dev->event_lock);
4289         }
4290
4291         return 0;
4292 }
4293
4294 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4295 {
4296         u32 temp;
4297
4298         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4299
4300         mutex_lock(&dev_priv->sb_lock);
4301
4302         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4303         temp |= SBI_SSCCTL_DISABLE;
4304         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4305
4306         mutex_unlock(&dev_priv->sb_lock);
4307 }
4308
4309 /* Program iCLKIP clock to the desired frequency */
4310 static void lpt_program_iclkip(struct intel_crtc *crtc)
4311 {
4312         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4313         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4314         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4315         u32 temp;
4316
4317         lpt_disable_iclkip(dev_priv);
4318
4319         /* The iCLK virtual clock root frequency is in MHz,
4320          * but the adjusted_mode->crtc_clock in in KHz. To get the
4321          * divisors, it is necessary to divide one by another, so we
4322          * convert the virtual clock precision to KHz here for higher
4323          * precision.
4324          */
4325         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4326                 u32 iclk_virtual_root_freq = 172800 * 1000;
4327                 u32 iclk_pi_range = 64;
4328                 u32 desired_divisor;
4329
4330                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4331                                                     clock << auxdiv);
4332                 divsel = (desired_divisor / iclk_pi_range) - 2;
4333                 phaseinc = desired_divisor % iclk_pi_range;
4334
4335                 /*
4336                  * Near 20MHz is a corner case which is
4337                  * out of range for the 7-bit divisor
4338                  */
4339                 if (divsel <= 0x7f)
4340                         break;
4341         }
4342
4343         /* This should not happen with any sane values */
4344         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4345                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4346         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4347                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4348
4349         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4350                         clock,
4351                         auxdiv,
4352                         divsel,
4353                         phasedir,
4354                         phaseinc);
4355
4356         mutex_lock(&dev_priv->sb_lock);
4357
4358         /* Program SSCDIVINTPHASE6 */
4359         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4360         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4361         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4362         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4363         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4364         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4365         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4366         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4367
4368         /* Program SSCAUXDIV */
4369         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4370         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4371         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4372         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4373
4374         /* Enable modulator and associated divider */
4375         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4376         temp &= ~SBI_SSCCTL_DISABLE;
4377         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4378
4379         mutex_unlock(&dev_priv->sb_lock);
4380
4381         /* Wait for initialization time */
4382         udelay(24);
4383
4384         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4385 }
4386
4387 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4388 {
4389         u32 divsel, phaseinc, auxdiv;
4390         u32 iclk_virtual_root_freq = 172800 * 1000;
4391         u32 iclk_pi_range = 64;
4392         u32 desired_divisor;
4393         u32 temp;
4394
4395         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4396                 return 0;
4397
4398         mutex_lock(&dev_priv->sb_lock);
4399
4400         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4401         if (temp & SBI_SSCCTL_DISABLE) {
4402                 mutex_unlock(&dev_priv->sb_lock);
4403                 return 0;
4404         }
4405
4406         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4407         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4408                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4409         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4410                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4411
4412         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4413         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4414                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4415
4416         mutex_unlock(&dev_priv->sb_lock);
4417
4418         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4419
4420         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4421                                  desired_divisor << auxdiv);
4422 }
4423
4424 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4425                                                 enum pipe pch_transcoder)
4426 {
4427         struct drm_device *dev = crtc->base.dev;
4428         struct drm_i915_private *dev_priv = to_i915(dev);
4429         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4430
4431         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4432                    I915_READ(HTOTAL(cpu_transcoder)));
4433         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4434                    I915_READ(HBLANK(cpu_transcoder)));
4435         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4436                    I915_READ(HSYNC(cpu_transcoder)));
4437
4438         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4439                    I915_READ(VTOTAL(cpu_transcoder)));
4440         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4441                    I915_READ(VBLANK(cpu_transcoder)));
4442         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4443                    I915_READ(VSYNC(cpu_transcoder)));
4444         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4445                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4446 }
4447
4448 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4449 {
4450         struct drm_i915_private *dev_priv = to_i915(dev);
4451         uint32_t temp;
4452
4453         temp = I915_READ(SOUTH_CHICKEN1);
4454         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4455                 return;
4456
4457         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4458         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4459
4460         temp &= ~FDI_BC_BIFURCATION_SELECT;
4461         if (enable)
4462                 temp |= FDI_BC_BIFURCATION_SELECT;
4463
4464         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4465         I915_WRITE(SOUTH_CHICKEN1, temp);
4466         POSTING_READ(SOUTH_CHICKEN1);
4467 }
4468
4469 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4470 {
4471         struct drm_device *dev = intel_crtc->base.dev;
4472
4473         switch (intel_crtc->pipe) {
4474         case PIPE_A:
4475                 break;
4476         case PIPE_B:
4477                 if (intel_crtc->config->fdi_lanes > 2)
4478                         cpt_set_fdi_bc_bifurcation(dev, false);
4479                 else
4480                         cpt_set_fdi_bc_bifurcation(dev, true);
4481
4482                 break;
4483         case PIPE_C:
4484                 cpt_set_fdi_bc_bifurcation(dev, true);
4485
4486                 break;
4487         default:
4488                 BUG();
4489         }
4490 }
4491
4492 /* Return which DP Port should be selected for Transcoder DP control */
4493 static enum port
4494 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4495 {
4496         struct drm_device *dev = crtc->base.dev;
4497         struct intel_encoder *encoder;
4498
4499         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4500                 if (encoder->type == INTEL_OUTPUT_DP ||
4501                     encoder->type == INTEL_OUTPUT_EDP)
4502                         return enc_to_dig_port(&encoder->base)->port;
4503         }
4504
4505         return -1;
4506 }
4507
4508 /*
4509  * Enable PCH resources required for PCH ports:
4510  *   - PCH PLLs
4511  *   - FDI training & RX/TX
4512  *   - update transcoder timings
4513  *   - DP transcoding bits
4514  *   - transcoder
4515  */
4516 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4517 {
4518         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4519         struct drm_device *dev = crtc->base.dev;
4520         struct drm_i915_private *dev_priv = to_i915(dev);
4521         int pipe = crtc->pipe;
4522         u32 temp;
4523
4524         assert_pch_transcoder_disabled(dev_priv, pipe);
4525
4526         if (IS_IVYBRIDGE(dev_priv))
4527                 ivybridge_update_fdi_bc_bifurcation(crtc);
4528
4529         /* Write the TU size bits before fdi link training, so that error
4530          * detection works. */
4531         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4532                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4533
4534         /* For PCH output, training FDI link */
4535         dev_priv->display.fdi_link_train(crtc, crtc_state);
4536
4537         /* We need to program the right clock selection before writing the pixel
4538          * mutliplier into the DPLL. */
4539         if (HAS_PCH_CPT(dev_priv)) {
4540                 u32 sel;
4541
4542                 temp = I915_READ(PCH_DPLL_SEL);
4543                 temp |= TRANS_DPLL_ENABLE(pipe);
4544                 sel = TRANS_DPLLB_SEL(pipe);
4545                 if (crtc_state->shared_dpll ==
4546                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4547                         temp |= sel;
4548                 else
4549                         temp &= ~sel;
4550                 I915_WRITE(PCH_DPLL_SEL, temp);
4551         }
4552
4553         /* XXX: pch pll's can be enabled any time before we enable the PCH
4554          * transcoder, and we actually should do this to not upset any PCH
4555          * transcoder that already use the clock when we share it.
4556          *
4557          * Note that enable_shared_dpll tries to do the right thing, but
4558          * get_shared_dpll unconditionally resets the pll - we need that to have
4559          * the right LVDS enable sequence. */
4560         intel_enable_shared_dpll(crtc);
4561
4562         /* set transcoder timing, panel must allow it */
4563         assert_panel_unlocked(dev_priv, pipe);
4564         ironlake_pch_transcoder_set_timings(crtc, pipe);
4565
4566         intel_fdi_normal_train(crtc);
4567
4568         /* For PCH DP, enable TRANS_DP_CTL */
4569         if (HAS_PCH_CPT(dev_priv) &&
4570             intel_crtc_has_dp_encoder(crtc_state)) {
4571                 const struct drm_display_mode *adjusted_mode =
4572                         &crtc_state->base.adjusted_mode;
4573                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4574                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4575                 temp = I915_READ(reg);
4576                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4577                           TRANS_DP_SYNC_MASK |
4578                           TRANS_DP_BPC_MASK);
4579                 temp |= TRANS_DP_OUTPUT_ENABLE;
4580                 temp |= bpc << 9; /* same format but at 11:9 */
4581
4582                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4583                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4584                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4585                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4586
4587                 switch (intel_trans_dp_port_sel(crtc)) {
4588                 case PORT_B:
4589                         temp |= TRANS_DP_PORT_SEL_B;
4590                         break;
4591                 case PORT_C:
4592                         temp |= TRANS_DP_PORT_SEL_C;
4593                         break;
4594                 case PORT_D:
4595                         temp |= TRANS_DP_PORT_SEL_D;
4596                         break;
4597                 default:
4598                         BUG();
4599                 }
4600
4601                 I915_WRITE(reg, temp);
4602         }
4603
4604         ironlake_enable_pch_transcoder(dev_priv, pipe);
4605 }
4606
4607 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4608 {
4609         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4611         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4612
4613         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4614
4615         lpt_program_iclkip(crtc);
4616
4617         /* Set transcoder timing. */
4618         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4619
4620         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4621 }
4622
4623 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4624 {
4625         struct drm_i915_private *dev_priv = to_i915(dev);
4626         i915_reg_t dslreg = PIPEDSL(pipe);
4627         u32 temp;
4628
4629         temp = I915_READ(dslreg);
4630         udelay(500);
4631         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4632                 if (wait_for(I915_READ(dslreg) != temp, 5))
4633                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4634         }
4635 }
4636
4637 static int
4638 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4639                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4640                   int src_w, int src_h, int dst_w, int dst_h)
4641 {
4642         struct intel_crtc_scaler_state *scaler_state =
4643                 &crtc_state->scaler_state;
4644         struct intel_crtc *intel_crtc =
4645                 to_intel_crtc(crtc_state->base.crtc);
4646         int need_scaling;
4647
4648         need_scaling = drm_rotation_90_or_270(rotation) ?
4649                 (src_h != dst_w || src_w != dst_h):
4650                 (src_w != dst_w || src_h != dst_h);
4651
4652         /*
4653          * if plane is being disabled or scaler is no more required or force detach
4654          *  - free scaler binded to this plane/crtc
4655          *  - in order to do this, update crtc->scaler_usage
4656          *
4657          * Here scaler state in crtc_state is set free so that
4658          * scaler can be assigned to other user. Actual register
4659          * update to free the scaler is done in plane/panel-fit programming.
4660          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4661          */
4662         if (force_detach || !need_scaling) {
4663                 if (*scaler_id >= 0) {
4664                         scaler_state->scaler_users &= ~(1 << scaler_user);
4665                         scaler_state->scalers[*scaler_id].in_use = 0;
4666
4667                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4668                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4669                                 intel_crtc->pipe, scaler_user, *scaler_id,
4670                                 scaler_state->scaler_users);
4671                         *scaler_id = -1;
4672                 }
4673                 return 0;
4674         }
4675
4676         /* range checks */
4677         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4678                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4679
4680                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4681                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4682                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4683                         "size is out of scaler range\n",
4684                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4685                 return -EINVAL;
4686         }
4687
4688         /* mark this plane as a scaler user in crtc_state */
4689         scaler_state->scaler_users |= (1 << scaler_user);
4690         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4691                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4692                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4693                 scaler_state->scaler_users);
4694
4695         return 0;
4696 }
4697
4698 /**
4699  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4700  *
4701  * @state: crtc's scaler state
4702  *
4703  * Return
4704  *     0 - scaler_usage updated successfully
4705  *    error - requested scaling cannot be supported or other error condition
4706  */
4707 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4708 {
4709         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4710
4711         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4712                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4713                 state->pipe_src_w, state->pipe_src_h,
4714                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4715 }
4716
4717 /**
4718  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4719  *
4720  * @state: crtc's scaler state
4721  * @plane_state: atomic plane state to update
4722  *
4723  * Return
4724  *     0 - scaler_usage updated successfully
4725  *    error - requested scaling cannot be supported or other error condition
4726  */
4727 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4728                                    struct intel_plane_state *plane_state)
4729 {
4730
4731         struct intel_plane *intel_plane =
4732                 to_intel_plane(plane_state->base.plane);
4733         struct drm_framebuffer *fb = plane_state->base.fb;
4734         int ret;
4735
4736         bool force_detach = !fb || !plane_state->base.visible;
4737
4738         ret = skl_update_scaler(crtc_state, force_detach,
4739                                 drm_plane_index(&intel_plane->base),
4740                                 &plane_state->scaler_id,
4741                                 plane_state->base.rotation,
4742                                 drm_rect_width(&plane_state->base.src) >> 16,
4743                                 drm_rect_height(&plane_state->base.src) >> 16,
4744                                 drm_rect_width(&plane_state->base.dst),
4745                                 drm_rect_height(&plane_state->base.dst));
4746
4747         if (ret || plane_state->scaler_id < 0)
4748                 return ret;
4749
4750         /* check colorkey */
4751         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4752                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4753                               intel_plane->base.base.id,
4754                               intel_plane->base.name);
4755                 return -EINVAL;
4756         }
4757
4758         /* Check src format */
4759         switch (fb->format->format) {
4760         case DRM_FORMAT_RGB565:
4761         case DRM_FORMAT_XBGR8888:
4762         case DRM_FORMAT_XRGB8888:
4763         case DRM_FORMAT_ABGR8888:
4764         case DRM_FORMAT_ARGB8888:
4765         case DRM_FORMAT_XRGB2101010:
4766         case DRM_FORMAT_XBGR2101010:
4767         case DRM_FORMAT_YUYV:
4768         case DRM_FORMAT_YVYU:
4769         case DRM_FORMAT_UYVY:
4770         case DRM_FORMAT_VYUY:
4771                 break;
4772         default:
4773                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4774                               intel_plane->base.base.id, intel_plane->base.name,
4775                               fb->base.id, fb->format->format);
4776                 return -EINVAL;
4777         }
4778
4779         return 0;
4780 }
4781
4782 static void skylake_scaler_disable(struct intel_crtc *crtc)
4783 {
4784         int i;
4785
4786         for (i = 0; i < crtc->num_scalers; i++)
4787                 skl_detach_scaler(crtc, i);
4788 }
4789
4790 static void skylake_pfit_enable(struct intel_crtc *crtc)
4791 {
4792         struct drm_device *dev = crtc->base.dev;
4793         struct drm_i915_private *dev_priv = to_i915(dev);
4794         int pipe = crtc->pipe;
4795         struct intel_crtc_scaler_state *scaler_state =
4796                 &crtc->config->scaler_state;
4797
4798         if (crtc->config->pch_pfit.enabled) {
4799                 int id;
4800
4801                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4802                         return;
4803
4804                 id = scaler_state->scaler_id;
4805                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4806                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4807                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4808                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4809         }
4810 }
4811
4812 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4813 {
4814         struct drm_device *dev = crtc->base.dev;
4815         struct drm_i915_private *dev_priv = to_i915(dev);
4816         int pipe = crtc->pipe;
4817
4818         if (crtc->config->pch_pfit.enabled) {
4819                 /* Force use of hard-coded filter coefficients
4820                  * as some pre-programmed values are broken,
4821                  * e.g. x201.
4822                  */
4823                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4824                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4825                                                  PF_PIPE_SEL_IVB(pipe));
4826                 else
4827                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4828                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4829                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4830         }
4831 }
4832
4833 void hsw_enable_ips(struct intel_crtc *crtc)
4834 {
4835         struct drm_device *dev = crtc->base.dev;
4836         struct drm_i915_private *dev_priv = to_i915(dev);
4837
4838         if (!crtc->config->ips_enabled)
4839                 return;
4840
4841         /*
4842          * We can only enable IPS after we enable a plane and wait for a vblank
4843          * This function is called from post_plane_update, which is run after
4844          * a vblank wait.
4845          */
4846
4847         assert_plane_enabled(dev_priv, crtc->plane);
4848         if (IS_BROADWELL(dev_priv)) {
4849                 mutex_lock(&dev_priv->rps.hw_lock);
4850                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4851                 mutex_unlock(&dev_priv->rps.hw_lock);
4852                 /* Quoting Art Runyan: "its not safe to expect any particular
4853                  * value in IPS_CTL bit 31 after enabling IPS through the
4854                  * mailbox." Moreover, the mailbox may return a bogus state,
4855                  * so we need to just enable it and continue on.
4856                  */
4857         } else {
4858                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4859                 /* The bit only becomes 1 in the next vblank, so this wait here
4860                  * is essentially intel_wait_for_vblank. If we don't have this
4861                  * and don't wait for vblanks until the end of crtc_enable, then
4862                  * the HW state readout code will complain that the expected
4863                  * IPS_CTL value is not the one we read. */
4864                 if (intel_wait_for_register(dev_priv,
4865                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4866                                             50))
4867                         DRM_ERROR("Timed out waiting for IPS enable\n");
4868         }
4869 }
4870
4871 void hsw_disable_ips(struct intel_crtc *crtc)
4872 {
4873         struct drm_device *dev = crtc->base.dev;
4874         struct drm_i915_private *dev_priv = to_i915(dev);
4875
4876         if (!crtc->config->ips_enabled)
4877                 return;
4878
4879         assert_plane_enabled(dev_priv, crtc->plane);
4880         if (IS_BROADWELL(dev_priv)) {
4881                 mutex_lock(&dev_priv->rps.hw_lock);
4882                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4883                 mutex_unlock(&dev_priv->rps.hw_lock);
4884                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4885                 if (intel_wait_for_register(dev_priv,
4886                                             IPS_CTL, IPS_ENABLE, 0,
4887                                             42))
4888                         DRM_ERROR("Timed out waiting for IPS disable\n");
4889         } else {
4890                 I915_WRITE(IPS_CTL, 0);
4891                 POSTING_READ(IPS_CTL);
4892         }
4893
4894         /* We need to wait for a vblank before we can disable the plane. */
4895         intel_wait_for_vblank(dev_priv, crtc->pipe);
4896 }
4897
4898 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4899 {
4900         if (intel_crtc->overlay) {
4901                 struct drm_device *dev = intel_crtc->base.dev;
4902                 struct drm_i915_private *dev_priv = to_i915(dev);
4903
4904                 mutex_lock(&dev->struct_mutex);
4905                 dev_priv->mm.interruptible = false;
4906                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4907                 dev_priv->mm.interruptible = true;
4908                 mutex_unlock(&dev->struct_mutex);
4909         }
4910
4911         /* Let userspace switch the overlay on again. In most cases userspace
4912          * has to recompute where to put it anyway.
4913          */
4914 }
4915
4916 /**
4917  * intel_post_enable_primary - Perform operations after enabling primary plane
4918  * @crtc: the CRTC whose primary plane was just enabled
4919  *
4920  * Performs potentially sleeping operations that must be done after the primary
4921  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4922  * called due to an explicit primary plane update, or due to an implicit
4923  * re-enable that is caused when a sprite plane is updated to no longer
4924  * completely hide the primary plane.
4925  */
4926 static void
4927 intel_post_enable_primary(struct drm_crtc *crtc)
4928 {
4929         struct drm_device *dev = crtc->dev;
4930         struct drm_i915_private *dev_priv = to_i915(dev);
4931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4932         int pipe = intel_crtc->pipe;
4933
4934         /*
4935          * FIXME IPS should be fine as long as one plane is
4936          * enabled, but in practice it seems to have problems
4937          * when going from primary only to sprite only and vice
4938          * versa.
4939          */
4940         hsw_enable_ips(intel_crtc);
4941
4942         /*
4943          * Gen2 reports pipe underruns whenever all planes are disabled.
4944          * So don't enable underrun reporting before at least some planes
4945          * are enabled.
4946          * FIXME: Need to fix the logic to work when we turn off all planes
4947          * but leave the pipe running.
4948          */
4949         if (IS_GEN2(dev_priv))
4950                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4951
4952         /* Underruns don't always raise interrupts, so check manually. */
4953         intel_check_cpu_fifo_underruns(dev_priv);
4954         intel_check_pch_fifo_underruns(dev_priv);
4955 }
4956
4957 /* FIXME move all this to pre_plane_update() with proper state tracking */
4958 static void
4959 intel_pre_disable_primary(struct drm_crtc *crtc)
4960 {
4961         struct drm_device *dev = crtc->dev;
4962         struct drm_i915_private *dev_priv = to_i915(dev);
4963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4964         int pipe = intel_crtc->pipe;
4965
4966         /*
4967          * Gen2 reports pipe underruns whenever all planes are disabled.
4968          * So diasble underrun reporting before all the planes get disabled.
4969          * FIXME: Need to fix the logic to work when we turn off all planes
4970          * but leave the pipe running.
4971          */
4972         if (IS_GEN2(dev_priv))
4973                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4974
4975         /*
4976          * FIXME IPS should be fine as long as one plane is
4977          * enabled, but in practice it seems to have problems
4978          * when going from primary only to sprite only and vice
4979          * versa.
4980          */
4981         hsw_disable_ips(intel_crtc);
4982 }
4983
4984 /* FIXME get rid of this and use pre_plane_update */
4985 static void
4986 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4987 {
4988         struct drm_device *dev = crtc->dev;
4989         struct drm_i915_private *dev_priv = to_i915(dev);
4990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4991         int pipe = intel_crtc->pipe;
4992
4993         intel_pre_disable_primary(crtc);
4994
4995         /*
4996          * Vblank time updates from the shadow to live plane control register
4997          * are blocked if the memory self-refresh mode is active at that
4998          * moment. So to make sure the plane gets truly disabled, disable
4999          * first the self-refresh mode. The self-refresh enable bit in turn
5000          * will be checked/applied by the HW only at the next frame start
5001          * event which is after the vblank start event, so we need to have a
5002          * wait-for-vblank between disabling the plane and the pipe.
5003          */
5004         if (HAS_GMCH_DISPLAY(dev_priv) &&
5005             intel_set_memory_cxsr(dev_priv, false))
5006                 intel_wait_for_vblank(dev_priv, pipe);
5007 }
5008
5009 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5010 {
5011         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5012         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5013         struct intel_crtc_state *pipe_config =
5014                 to_intel_crtc_state(crtc->base.state);
5015         struct drm_plane *primary = crtc->base.primary;
5016         struct drm_plane_state *old_pri_state =
5017                 drm_atomic_get_existing_plane_state(old_state, primary);
5018
5019         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5020
5021         if (pipe_config->update_wm_post && pipe_config->base.active)
5022                 intel_update_watermarks(crtc);
5023
5024         if (old_pri_state) {
5025                 struct intel_plane_state *primary_state =
5026                         to_intel_plane_state(primary->state);
5027                 struct intel_plane_state *old_primary_state =
5028                         to_intel_plane_state(old_pri_state);
5029
5030                 intel_fbc_post_update(crtc);
5031
5032                 if (primary_state->base.visible &&
5033                     (needs_modeset(&pipe_config->base) ||
5034                      !old_primary_state->base.visible))
5035                         intel_post_enable_primary(&crtc->base);
5036         }
5037 }
5038
5039 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5040                                    struct intel_crtc_state *pipe_config)
5041 {
5042         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5043         struct drm_device *dev = crtc->base.dev;
5044         struct drm_i915_private *dev_priv = to_i915(dev);
5045         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5046         struct drm_plane *primary = crtc->base.primary;
5047         struct drm_plane_state *old_pri_state =
5048                 drm_atomic_get_existing_plane_state(old_state, primary);
5049         bool modeset = needs_modeset(&pipe_config->base);
5050         struct intel_atomic_state *old_intel_state =
5051                 to_intel_atomic_state(old_state);
5052
5053         if (old_pri_state) {
5054                 struct intel_plane_state *primary_state =
5055                         to_intel_plane_state(primary->state);
5056                 struct intel_plane_state *old_primary_state =
5057                         to_intel_plane_state(old_pri_state);
5058
5059                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5060
5061                 if (old_primary_state->base.visible &&
5062                     (modeset || !primary_state->base.visible))
5063                         intel_pre_disable_primary(&crtc->base);
5064         }
5065
5066         /*
5067          * Vblank time updates from the shadow to live plane control register
5068          * are blocked if the memory self-refresh mode is active at that
5069          * moment. So to make sure the plane gets truly disabled, disable
5070          * first the self-refresh mode. The self-refresh enable bit in turn
5071          * will be checked/applied by the HW only at the next frame start
5072          * event which is after the vblank start event, so we need to have a
5073          * wait-for-vblank between disabling the plane and the pipe.
5074          */
5075         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5076             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5077                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5078
5079         /*
5080          * IVB workaround: must disable low power watermarks for at least
5081          * one frame before enabling scaling.  LP watermarks can be re-enabled
5082          * when scaling is disabled.
5083          *
5084          * WaCxSRDisabledForSpriteScaling:ivb
5085          */
5086         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5087                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5088
5089         /*
5090          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5091          * watermark programming here.
5092          */
5093         if (needs_modeset(&pipe_config->base))
5094                 return;
5095
5096         /*
5097          * For platforms that support atomic watermarks, program the
5098          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5099          * will be the intermediate values that are safe for both pre- and
5100          * post- vblank; when vblank happens, the 'active' values will be set
5101          * to the final 'target' values and we'll do this again to get the
5102          * optimal watermarks.  For gen9+ platforms, the values we program here
5103          * will be the final target values which will get automatically latched
5104          * at vblank time; no further programming will be necessary.
5105          *
5106          * If a platform hasn't been transitioned to atomic watermarks yet,
5107          * we'll continue to update watermarks the old way, if flags tell
5108          * us to.
5109          */
5110         if (dev_priv->display.initial_watermarks != NULL)
5111                 dev_priv->display.initial_watermarks(old_intel_state,
5112                                                      pipe_config);
5113         else if (pipe_config->update_wm_pre)
5114                 intel_update_watermarks(crtc);
5115 }
5116
5117 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5118 {
5119         struct drm_device *dev = crtc->dev;
5120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5121         struct drm_plane *p;
5122         int pipe = intel_crtc->pipe;
5123
5124         intel_crtc_dpms_overlay_disable(intel_crtc);
5125
5126         drm_for_each_plane_mask(p, dev, plane_mask)
5127                 to_intel_plane(p)->disable_plane(p, crtc);
5128
5129         /*
5130          * FIXME: Once we grow proper nuclear flip support out of this we need
5131          * to compute the mask of flip planes precisely. For the time being
5132          * consider this a flip to a NULL plane.
5133          */
5134         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5135 }
5136
5137 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5138                                           struct intel_crtc_state *crtc_state,
5139                                           struct drm_atomic_state *old_state)
5140 {
5141         struct drm_connector_state *conn_state;
5142         struct drm_connector *conn;
5143         int i;
5144
5145         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5146                 struct intel_encoder *encoder =
5147                         to_intel_encoder(conn_state->best_encoder);
5148
5149                 if (conn_state->crtc != crtc)
5150                         continue;
5151
5152                 if (encoder->pre_pll_enable)
5153                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5154         }
5155 }
5156
5157 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5158                                       struct intel_crtc_state *crtc_state,
5159                                       struct drm_atomic_state *old_state)
5160 {
5161         struct drm_connector_state *conn_state;
5162         struct drm_connector *conn;
5163         int i;
5164
5165         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5166                 struct intel_encoder *encoder =
5167                         to_intel_encoder(conn_state->best_encoder);
5168
5169                 if (conn_state->crtc != crtc)
5170                         continue;
5171
5172                 if (encoder->pre_enable)
5173                         encoder->pre_enable(encoder, crtc_state, conn_state);
5174         }
5175 }
5176
5177 static void intel_encoders_enable(struct drm_crtc *crtc,
5178                                   struct intel_crtc_state *crtc_state,
5179                                   struct drm_atomic_state *old_state)
5180 {
5181         struct drm_connector_state *conn_state;
5182         struct drm_connector *conn;
5183         int i;
5184
5185         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5186                 struct intel_encoder *encoder =
5187                         to_intel_encoder(conn_state->best_encoder);
5188
5189                 if (conn_state->crtc != crtc)
5190                         continue;
5191
5192                 encoder->enable(encoder, crtc_state, conn_state);
5193                 intel_opregion_notify_encoder(encoder, true);
5194         }
5195 }
5196
5197 static void intel_encoders_disable(struct drm_crtc *crtc,
5198                                    struct intel_crtc_state *old_crtc_state,
5199                                    struct drm_atomic_state *old_state)
5200 {
5201         struct drm_connector_state *old_conn_state;
5202         struct drm_connector *conn;
5203         int i;
5204
5205         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5206                 struct intel_encoder *encoder =
5207                         to_intel_encoder(old_conn_state->best_encoder);
5208
5209                 if (old_conn_state->crtc != crtc)
5210                         continue;
5211
5212                 intel_opregion_notify_encoder(encoder, false);
5213                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5214         }
5215 }
5216
5217 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5218                                         struct intel_crtc_state *old_crtc_state,
5219                                         struct drm_atomic_state *old_state)
5220 {
5221         struct drm_connector_state *old_conn_state;
5222         struct drm_connector *conn;
5223         int i;
5224
5225         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5226                 struct intel_encoder *encoder =
5227                         to_intel_encoder(old_conn_state->best_encoder);
5228
5229                 if (old_conn_state->crtc != crtc)
5230                         continue;
5231
5232                 if (encoder->post_disable)
5233                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5234         }
5235 }
5236
5237 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5238                                             struct intel_crtc_state *old_crtc_state,
5239                                             struct drm_atomic_state *old_state)
5240 {
5241         struct drm_connector_state *old_conn_state;
5242         struct drm_connector *conn;
5243         int i;
5244
5245         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5246                 struct intel_encoder *encoder =
5247                         to_intel_encoder(old_conn_state->best_encoder);
5248
5249                 if (old_conn_state->crtc != crtc)
5250                         continue;
5251
5252                 if (encoder->post_pll_disable)
5253                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5254         }
5255 }
5256
5257 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5258                                  struct drm_atomic_state *old_state)
5259 {
5260         struct drm_crtc *crtc = pipe_config->base.crtc;
5261         struct drm_device *dev = crtc->dev;
5262         struct drm_i915_private *dev_priv = to_i915(dev);
5263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5264         int pipe = intel_crtc->pipe;
5265         struct intel_atomic_state *old_intel_state =
5266                 to_intel_atomic_state(old_state);
5267
5268         if (WARN_ON(intel_crtc->active))
5269                 return;
5270
5271         /*
5272          * Sometimes spurious CPU pipe underruns happen during FDI
5273          * training, at least with VGA+HDMI cloning. Suppress them.
5274          *
5275          * On ILK we get an occasional spurious CPU pipe underruns
5276          * between eDP port A enable and vdd enable. Also PCH port
5277          * enable seems to result in the occasional CPU pipe underrun.
5278          *
5279          * Spurious PCH underruns also occur during PCH enabling.
5280          */
5281         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5282                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5283         if (intel_crtc->config->has_pch_encoder)
5284                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5285
5286         if (intel_crtc->config->has_pch_encoder)
5287                 intel_prepare_shared_dpll(intel_crtc);
5288
5289         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5290                 intel_dp_set_m_n(intel_crtc, M1_N1);
5291
5292         intel_set_pipe_timings(intel_crtc);
5293         intel_set_pipe_src_size(intel_crtc);
5294
5295         if (intel_crtc->config->has_pch_encoder) {
5296                 intel_cpu_transcoder_set_m_n(intel_crtc,
5297                                      &intel_crtc->config->fdi_m_n, NULL);
5298         }
5299
5300         ironlake_set_pipeconf(crtc);
5301
5302         intel_crtc->active = true;
5303
5304         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5305
5306         if (intel_crtc->config->has_pch_encoder) {
5307                 /* Note: FDI PLL enabling _must_ be done before we enable the
5308                  * cpu pipes, hence this is separate from all the other fdi/pch
5309                  * enabling. */
5310                 ironlake_fdi_pll_enable(intel_crtc);
5311         } else {
5312                 assert_fdi_tx_disabled(dev_priv, pipe);
5313                 assert_fdi_rx_disabled(dev_priv, pipe);
5314         }
5315
5316         ironlake_pfit_enable(intel_crtc);
5317
5318         /*
5319          * On ILK+ LUT must be loaded before the pipe is running but with
5320          * clocks enabled
5321          */
5322         intel_color_load_luts(&pipe_config->base);
5323
5324         if (dev_priv->display.initial_watermarks != NULL)
5325                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5326         intel_enable_pipe(intel_crtc);
5327
5328         if (intel_crtc->config->has_pch_encoder)
5329                 ironlake_pch_enable(pipe_config);
5330
5331         assert_vblank_disabled(crtc);
5332         drm_crtc_vblank_on(crtc);
5333
5334         intel_encoders_enable(crtc, pipe_config, old_state);
5335
5336         if (HAS_PCH_CPT(dev_priv))
5337                 cpt_verify_modeset(dev, intel_crtc->pipe);
5338
5339         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5340         if (intel_crtc->config->has_pch_encoder)
5341                 intel_wait_for_vblank(dev_priv, pipe);
5342         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5343         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5344 }
5345
5346 /* IPS only exists on ULT machines and is tied to pipe A. */
5347 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5348 {
5349         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5350 }
5351
5352 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5353                                 struct drm_atomic_state *old_state)
5354 {
5355         struct drm_crtc *crtc = pipe_config->base.crtc;
5356         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5358         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5359         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5360         struct intel_atomic_state *old_intel_state =
5361                 to_intel_atomic_state(old_state);
5362
5363         if (WARN_ON(intel_crtc->active))
5364                 return;
5365
5366         if (intel_crtc->config->has_pch_encoder)
5367                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5368                                                       false);
5369
5370         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5371
5372         if (intel_crtc->config->shared_dpll)
5373                 intel_enable_shared_dpll(intel_crtc);
5374
5375         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5376                 intel_dp_set_m_n(intel_crtc, M1_N1);
5377
5378         if (!transcoder_is_dsi(cpu_transcoder))
5379                 intel_set_pipe_timings(intel_crtc);
5380
5381         intel_set_pipe_src_size(intel_crtc);
5382
5383         if (cpu_transcoder != TRANSCODER_EDP &&
5384             !transcoder_is_dsi(cpu_transcoder)) {
5385                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5386                            intel_crtc->config->pixel_multiplier - 1);
5387         }
5388
5389         if (intel_crtc->config->has_pch_encoder) {
5390                 intel_cpu_transcoder_set_m_n(intel_crtc,
5391                                      &intel_crtc->config->fdi_m_n, NULL);
5392         }
5393
5394         if (!transcoder_is_dsi(cpu_transcoder))
5395                 haswell_set_pipeconf(crtc);
5396
5397         haswell_set_pipemisc(crtc);
5398
5399         intel_color_set_csc(&pipe_config->base);
5400
5401         intel_crtc->active = true;
5402
5403         if (intel_crtc->config->has_pch_encoder)
5404                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5405         else
5406                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5407
5408         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5409
5410         if (intel_crtc->config->has_pch_encoder)
5411                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5412
5413         if (!transcoder_is_dsi(cpu_transcoder))
5414                 intel_ddi_enable_pipe_clock(pipe_config);
5415
5416         if (INTEL_GEN(dev_priv) >= 9)
5417                 skylake_pfit_enable(intel_crtc);
5418         else
5419                 ironlake_pfit_enable(intel_crtc);
5420
5421         /*
5422          * On ILK+ LUT must be loaded before the pipe is running but with
5423          * clocks enabled
5424          */
5425         intel_color_load_luts(&pipe_config->base);
5426
5427         intel_ddi_set_pipe_settings(pipe_config);
5428         if (!transcoder_is_dsi(cpu_transcoder))
5429                 intel_ddi_enable_transcoder_func(pipe_config);
5430
5431         if (dev_priv->display.initial_watermarks != NULL)
5432                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5433
5434         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5435         if (!transcoder_is_dsi(cpu_transcoder))
5436                 intel_enable_pipe(intel_crtc);
5437
5438         if (intel_crtc->config->has_pch_encoder)
5439                 lpt_pch_enable(pipe_config);
5440
5441         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5442                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5443
5444         assert_vblank_disabled(crtc);
5445         drm_crtc_vblank_on(crtc);
5446
5447         intel_encoders_enable(crtc, pipe_config, old_state);
5448
5449         if (intel_crtc->config->has_pch_encoder) {
5450                 intel_wait_for_vblank(dev_priv, pipe);
5451                 intel_wait_for_vblank(dev_priv, pipe);
5452                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5453                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5454                                                       true);
5455         }
5456
5457         /* If we change the relative order between pipe/planes enabling, we need
5458          * to change the workaround. */
5459         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5460         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5461                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5462                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5463         }
5464 }
5465
5466 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5467 {
5468         struct drm_device *dev = crtc->base.dev;
5469         struct drm_i915_private *dev_priv = to_i915(dev);
5470         int pipe = crtc->pipe;
5471
5472         /* To avoid upsetting the power well on haswell only disable the pfit if
5473          * it's in use. The hw state code will make sure we get this right. */
5474         if (force || crtc->config->pch_pfit.enabled) {
5475                 I915_WRITE(PF_CTL(pipe), 0);
5476                 I915_WRITE(PF_WIN_POS(pipe), 0);
5477                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5478         }
5479 }
5480
5481 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5482                                   struct drm_atomic_state *old_state)
5483 {
5484         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5485         struct drm_device *dev = crtc->dev;
5486         struct drm_i915_private *dev_priv = to_i915(dev);
5487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5488         int pipe = intel_crtc->pipe;
5489
5490         /*
5491          * Sometimes spurious CPU pipe underruns happen when the
5492          * pipe is already disabled, but FDI RX/TX is still enabled.
5493          * Happens at least with VGA+HDMI cloning. Suppress them.
5494          */
5495         if (intel_crtc->config->has_pch_encoder) {
5496                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5497                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5498         }
5499
5500         intel_encoders_disable(crtc, old_crtc_state, old_state);
5501
5502         drm_crtc_vblank_off(crtc);
5503         assert_vblank_disabled(crtc);
5504
5505         intel_disable_pipe(intel_crtc);
5506
5507         ironlake_pfit_disable(intel_crtc, false);
5508
5509         if (intel_crtc->config->has_pch_encoder)
5510                 ironlake_fdi_disable(crtc);
5511
5512         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5513
5514         if (intel_crtc->config->has_pch_encoder) {
5515                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5516
5517                 if (HAS_PCH_CPT(dev_priv)) {
5518                         i915_reg_t reg;
5519                         u32 temp;
5520
5521                         /* disable TRANS_DP_CTL */
5522                         reg = TRANS_DP_CTL(pipe);
5523                         temp = I915_READ(reg);
5524                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5525                                   TRANS_DP_PORT_SEL_MASK);
5526                         temp |= TRANS_DP_PORT_SEL_NONE;
5527                         I915_WRITE(reg, temp);
5528
5529                         /* disable DPLL_SEL */
5530                         temp = I915_READ(PCH_DPLL_SEL);
5531                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5532                         I915_WRITE(PCH_DPLL_SEL, temp);
5533                 }
5534
5535                 ironlake_fdi_pll_disable(intel_crtc);
5536         }
5537
5538         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5539         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5540 }
5541
5542 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5543                                  struct drm_atomic_state *old_state)
5544 {
5545         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5546         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5548         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5549
5550         if (intel_crtc->config->has_pch_encoder)
5551                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5552                                                       false);
5553
5554         intel_encoders_disable(crtc, old_crtc_state, old_state);
5555
5556         drm_crtc_vblank_off(crtc);
5557         assert_vblank_disabled(crtc);
5558
5559         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5560         if (!transcoder_is_dsi(cpu_transcoder))
5561                 intel_disable_pipe(intel_crtc);
5562
5563         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5564                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5565
5566         if (!transcoder_is_dsi(cpu_transcoder))
5567                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5568
5569         if (INTEL_GEN(dev_priv) >= 9)
5570                 skylake_scaler_disable(intel_crtc);
5571         else
5572                 ironlake_pfit_disable(intel_crtc, false);
5573
5574         if (!transcoder_is_dsi(cpu_transcoder))
5575                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5576
5577         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5578
5579         if (old_crtc_state->has_pch_encoder)
5580                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5581                                                       true);
5582 }
5583
5584 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5585 {
5586         struct drm_device *dev = crtc->base.dev;
5587         struct drm_i915_private *dev_priv = to_i915(dev);
5588         struct intel_crtc_state *pipe_config = crtc->config;
5589
5590         if (!pipe_config->gmch_pfit.control)
5591                 return;
5592
5593         /*
5594          * The panel fitter should only be adjusted whilst the pipe is disabled,
5595          * according to register description and PRM.
5596          */
5597         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5598         assert_pipe_disabled(dev_priv, crtc->pipe);
5599
5600         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5601         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5602
5603         /* Border color in case we don't scale up to the full screen. Black by
5604          * default, change to something else for debugging. */
5605         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5606 }
5607
5608 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5609 {
5610         switch (port) {
5611         case PORT_A:
5612                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5613         case PORT_B:
5614                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5615         case PORT_C:
5616                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5617         case PORT_D:
5618                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5619         case PORT_E:
5620                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5621         default:
5622                 MISSING_CASE(port);
5623                 return POWER_DOMAIN_PORT_OTHER;
5624         }
5625 }
5626
5627 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5628                                   struct intel_crtc_state *crtc_state)
5629 {
5630         struct drm_device *dev = crtc->dev;
5631         struct drm_i915_private *dev_priv = to_i915(dev);
5632         struct drm_encoder *encoder;
5633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5634         enum pipe pipe = intel_crtc->pipe;
5635         u64 mask;
5636         enum transcoder transcoder = crtc_state->cpu_transcoder;
5637
5638         if (!crtc_state->base.active)
5639                 return 0;
5640
5641         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5642         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5643         if (crtc_state->pch_pfit.enabled ||
5644             crtc_state->pch_pfit.force_thru)
5645                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5646
5647         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5648                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5649
5650                 mask |= BIT_ULL(intel_encoder->power_domain);
5651         }
5652
5653         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5654                 mask |= BIT(POWER_DOMAIN_AUDIO);
5655
5656         if (crtc_state->shared_dpll)
5657                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5658
5659         return mask;
5660 }
5661
5662 static u64
5663 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5664                                struct intel_crtc_state *crtc_state)
5665 {
5666         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5668         enum intel_display_power_domain domain;
5669         u64 domains, new_domains, old_domains;
5670
5671         old_domains = intel_crtc->enabled_power_domains;
5672         intel_crtc->enabled_power_domains = new_domains =
5673                 get_crtc_power_domains(crtc, crtc_state);
5674
5675         domains = new_domains & ~old_domains;
5676
5677         for_each_power_domain(domain, domains)
5678                 intel_display_power_get(dev_priv, domain);
5679
5680         return old_domains & ~new_domains;
5681 }
5682
5683 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5684                                       u64 domains)
5685 {
5686         enum intel_display_power_domain domain;
5687
5688         for_each_power_domain(domain, domains)
5689                 intel_display_power_put(dev_priv, domain);
5690 }
5691
5692 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5693                                    struct drm_atomic_state *old_state)
5694 {
5695         struct intel_atomic_state *old_intel_state =
5696                 to_intel_atomic_state(old_state);
5697         struct drm_crtc *crtc = pipe_config->base.crtc;
5698         struct drm_device *dev = crtc->dev;
5699         struct drm_i915_private *dev_priv = to_i915(dev);
5700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5701         int pipe = intel_crtc->pipe;
5702
5703         if (WARN_ON(intel_crtc->active))
5704                 return;
5705
5706         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5707                 intel_dp_set_m_n(intel_crtc, M1_N1);
5708
5709         intel_set_pipe_timings(intel_crtc);
5710         intel_set_pipe_src_size(intel_crtc);
5711
5712         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5713                 struct drm_i915_private *dev_priv = to_i915(dev);
5714
5715                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5716                 I915_WRITE(CHV_CANVAS(pipe), 0);
5717         }
5718
5719         i9xx_set_pipeconf(intel_crtc);
5720
5721         intel_crtc->active = true;
5722
5723         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5724
5725         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5726
5727         if (IS_CHERRYVIEW(dev_priv)) {
5728                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5729                 chv_enable_pll(intel_crtc, intel_crtc->config);
5730         } else {
5731                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5732                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5733         }
5734
5735         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5736
5737         i9xx_pfit_enable(intel_crtc);
5738
5739         intel_color_load_luts(&pipe_config->base);
5740
5741         dev_priv->display.initial_watermarks(old_intel_state,
5742                                              pipe_config);
5743         intel_enable_pipe(intel_crtc);
5744
5745         assert_vblank_disabled(crtc);
5746         drm_crtc_vblank_on(crtc);
5747
5748         intel_encoders_enable(crtc, pipe_config, old_state);
5749 }
5750
5751 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5752 {
5753         struct drm_device *dev = crtc->base.dev;
5754         struct drm_i915_private *dev_priv = to_i915(dev);
5755
5756         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5757         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5758 }
5759
5760 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5761                              struct drm_atomic_state *old_state)
5762 {
5763         struct drm_crtc *crtc = pipe_config->base.crtc;
5764         struct drm_device *dev = crtc->dev;
5765         struct drm_i915_private *dev_priv = to_i915(dev);
5766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767         enum pipe pipe = intel_crtc->pipe;
5768
5769         if (WARN_ON(intel_crtc->active))
5770                 return;
5771
5772         i9xx_set_pll_dividers(intel_crtc);
5773
5774         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5775                 intel_dp_set_m_n(intel_crtc, M1_N1);
5776
5777         intel_set_pipe_timings(intel_crtc);
5778         intel_set_pipe_src_size(intel_crtc);
5779
5780         i9xx_set_pipeconf(intel_crtc);
5781
5782         intel_crtc->active = true;
5783
5784         if (!IS_GEN2(dev_priv))
5785                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5786
5787         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5788
5789         i9xx_enable_pll(intel_crtc);
5790
5791         i9xx_pfit_enable(intel_crtc);
5792
5793         intel_color_load_luts(&pipe_config->base);
5794
5795         intel_update_watermarks(intel_crtc);
5796         intel_enable_pipe(intel_crtc);
5797
5798         assert_vblank_disabled(crtc);
5799         drm_crtc_vblank_on(crtc);
5800
5801         intel_encoders_enable(crtc, pipe_config, old_state);
5802 }
5803
5804 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5805 {
5806         struct drm_device *dev = crtc->base.dev;
5807         struct drm_i915_private *dev_priv = to_i915(dev);
5808
5809         if (!crtc->config->gmch_pfit.control)
5810                 return;
5811
5812         assert_pipe_disabled(dev_priv, crtc->pipe);
5813
5814         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5815                          I915_READ(PFIT_CONTROL));
5816         I915_WRITE(PFIT_CONTROL, 0);
5817 }
5818
5819 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5820                               struct drm_atomic_state *old_state)
5821 {
5822         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5823         struct drm_device *dev = crtc->dev;
5824         struct drm_i915_private *dev_priv = to_i915(dev);
5825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5826         int pipe = intel_crtc->pipe;
5827
5828         /*
5829          * On gen2 planes are double buffered but the pipe isn't, so we must
5830          * wait for planes to fully turn off before disabling the pipe.
5831          */
5832         if (IS_GEN2(dev_priv))
5833                 intel_wait_for_vblank(dev_priv, pipe);
5834
5835         intel_encoders_disable(crtc, old_crtc_state, old_state);
5836
5837         drm_crtc_vblank_off(crtc);
5838         assert_vblank_disabled(crtc);
5839
5840         intel_disable_pipe(intel_crtc);
5841
5842         i9xx_pfit_disable(intel_crtc);
5843
5844         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5845
5846         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5847                 if (IS_CHERRYVIEW(dev_priv))
5848                         chv_disable_pll(dev_priv, pipe);
5849                 else if (IS_VALLEYVIEW(dev_priv))
5850                         vlv_disable_pll(dev_priv, pipe);
5851                 else
5852                         i9xx_disable_pll(intel_crtc);
5853         }
5854
5855         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5856
5857         if (!IS_GEN2(dev_priv))
5858                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5859
5860         if (!dev_priv->display.initial_watermarks)
5861                 intel_update_watermarks(intel_crtc);
5862 }
5863
5864 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5865 {
5866         struct intel_encoder *encoder;
5867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5868         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5869         enum intel_display_power_domain domain;
5870         u64 domains;
5871         struct drm_atomic_state *state;
5872         struct intel_crtc_state *crtc_state;
5873         int ret;
5874
5875         if (!intel_crtc->active)
5876                 return;
5877
5878         if (crtc->primary->state->visible) {
5879                 WARN_ON(intel_crtc->flip_work);
5880
5881                 intel_pre_disable_primary_noatomic(crtc);
5882
5883                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5884                 crtc->primary->state->visible = false;
5885         }
5886
5887         state = drm_atomic_state_alloc(crtc->dev);
5888         if (!state) {
5889                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5890                               crtc->base.id, crtc->name);
5891                 return;
5892         }
5893
5894         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5895
5896         /* Everything's already locked, -EDEADLK can't happen. */
5897         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5898         ret = drm_atomic_add_affected_connectors(state, crtc);
5899
5900         WARN_ON(IS_ERR(crtc_state) || ret);
5901
5902         dev_priv->display.crtc_disable(crtc_state, state);
5903
5904         drm_atomic_state_put(state);
5905
5906         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5907                       crtc->base.id, crtc->name);
5908
5909         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5910         crtc->state->active = false;
5911         intel_crtc->active = false;
5912         crtc->enabled = false;
5913         crtc->state->connector_mask = 0;
5914         crtc->state->encoder_mask = 0;
5915
5916         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5917                 encoder->base.crtc = NULL;
5918
5919         intel_fbc_disable(intel_crtc);
5920         intel_update_watermarks(intel_crtc);
5921         intel_disable_shared_dpll(intel_crtc);
5922
5923         domains = intel_crtc->enabled_power_domains;
5924         for_each_power_domain(domain, domains)
5925                 intel_display_power_put(dev_priv, domain);
5926         intel_crtc->enabled_power_domains = 0;
5927
5928         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5929         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5930 }
5931
5932 /*
5933  * turn all crtc's off, but do not adjust state
5934  * This has to be paired with a call to intel_modeset_setup_hw_state.
5935  */
5936 int intel_display_suspend(struct drm_device *dev)
5937 {
5938         struct drm_i915_private *dev_priv = to_i915(dev);
5939         struct drm_atomic_state *state;
5940         int ret;
5941
5942         state = drm_atomic_helper_suspend(dev);
5943         ret = PTR_ERR_OR_ZERO(state);
5944         if (ret)
5945                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5946         else
5947                 dev_priv->modeset_restore_state = state;
5948         return ret;
5949 }
5950
5951 void intel_encoder_destroy(struct drm_encoder *encoder)
5952 {
5953         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5954
5955         drm_encoder_cleanup(encoder);
5956         kfree(intel_encoder);
5957 }
5958
5959 /* Cross check the actual hw state with our own modeset state tracking (and it's
5960  * internal consistency). */
5961 static void intel_connector_verify_state(struct intel_connector *connector)
5962 {
5963         struct drm_crtc *crtc = connector->base.state->crtc;
5964
5965         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5966                       connector->base.base.id,
5967                       connector->base.name);
5968
5969         if (connector->get_hw_state(connector)) {
5970                 struct intel_encoder *encoder = connector->encoder;
5971                 struct drm_connector_state *conn_state = connector->base.state;
5972
5973                 I915_STATE_WARN(!crtc,
5974                          "connector enabled without attached crtc\n");
5975
5976                 if (!crtc)
5977                         return;
5978
5979                 I915_STATE_WARN(!crtc->state->active,
5980                       "connector is active, but attached crtc isn't\n");
5981
5982                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5983                         return;
5984
5985                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5986                         "atomic encoder doesn't match attached encoder\n");
5987
5988                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5989                         "attached encoder crtc differs from connector crtc\n");
5990         } else {
5991                 I915_STATE_WARN(crtc && crtc->state->active,
5992                         "attached crtc is active, but connector isn't\n");
5993                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5994                         "best encoder set without crtc!\n");
5995         }
5996 }
5997
5998 int intel_connector_init(struct intel_connector *connector)
5999 {
6000         drm_atomic_helper_connector_reset(&connector->base);
6001
6002         if (!connector->base.state)
6003                 return -ENOMEM;
6004
6005         return 0;
6006 }
6007
6008 struct intel_connector *intel_connector_alloc(void)
6009 {
6010         struct intel_connector *connector;
6011
6012         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6013         if (!connector)
6014                 return NULL;
6015
6016         if (intel_connector_init(connector) < 0) {
6017                 kfree(connector);
6018                 return NULL;
6019         }
6020
6021         return connector;
6022 }
6023
6024 /* Simple connector->get_hw_state implementation for encoders that support only
6025  * one connector and no cloning and hence the encoder state determines the state
6026  * of the connector. */
6027 bool intel_connector_get_hw_state(struct intel_connector *connector)
6028 {
6029         enum pipe pipe = 0;
6030         struct intel_encoder *encoder = connector->encoder;
6031
6032         return encoder->get_hw_state(encoder, &pipe);
6033 }
6034
6035 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6036 {
6037         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6038                 return crtc_state->fdi_lanes;
6039
6040         return 0;
6041 }
6042
6043 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6044                                      struct intel_crtc_state *pipe_config)
6045 {
6046         struct drm_i915_private *dev_priv = to_i915(dev);
6047         struct drm_atomic_state *state = pipe_config->base.state;
6048         struct intel_crtc *other_crtc;
6049         struct intel_crtc_state *other_crtc_state;
6050
6051         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6052                       pipe_name(pipe), pipe_config->fdi_lanes);
6053         if (pipe_config->fdi_lanes > 4) {
6054                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6055                               pipe_name(pipe), pipe_config->fdi_lanes);
6056                 return -EINVAL;
6057         }
6058
6059         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6060                 if (pipe_config->fdi_lanes > 2) {
6061                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6062                                       pipe_config->fdi_lanes);
6063                         return -EINVAL;
6064                 } else {
6065                         return 0;
6066                 }
6067         }
6068
6069         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6070                 return 0;
6071
6072         /* Ivybridge 3 pipe is really complicated */
6073         switch (pipe) {
6074         case PIPE_A:
6075                 return 0;
6076         case PIPE_B:
6077                 if (pipe_config->fdi_lanes <= 2)
6078                         return 0;
6079
6080                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6081                 other_crtc_state =
6082                         intel_atomic_get_crtc_state(state, other_crtc);
6083                 if (IS_ERR(other_crtc_state))
6084                         return PTR_ERR(other_crtc_state);
6085
6086                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6087                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6088                                       pipe_name(pipe), pipe_config->fdi_lanes);
6089                         return -EINVAL;
6090                 }
6091                 return 0;
6092         case PIPE_C:
6093                 if (pipe_config->fdi_lanes > 2) {
6094                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6095                                       pipe_name(pipe), pipe_config->fdi_lanes);
6096                         return -EINVAL;
6097                 }
6098
6099                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6100                 other_crtc_state =
6101                         intel_atomic_get_crtc_state(state, other_crtc);
6102                 if (IS_ERR(other_crtc_state))
6103                         return PTR_ERR(other_crtc_state);
6104
6105                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6106                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6107                         return -EINVAL;
6108                 }
6109                 return 0;
6110         default:
6111                 BUG();
6112         }
6113 }
6114
6115 #define RETRY 1
6116 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6117                                        struct intel_crtc_state *pipe_config)
6118 {
6119         struct drm_device *dev = intel_crtc->base.dev;
6120         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6121         int lane, link_bw, fdi_dotclock, ret;
6122         bool needs_recompute = false;
6123
6124 retry:
6125         /* FDI is a binary signal running at ~2.7GHz, encoding
6126          * each output octet as 10 bits. The actual frequency
6127          * is stored as a divider into a 100MHz clock, and the
6128          * mode pixel clock is stored in units of 1KHz.
6129          * Hence the bw of each lane in terms of the mode signal
6130          * is:
6131          */
6132         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6133
6134         fdi_dotclock = adjusted_mode->crtc_clock;
6135
6136         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6137                                            pipe_config->pipe_bpp);
6138
6139         pipe_config->fdi_lanes = lane;
6140
6141         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6142                                link_bw, &pipe_config->fdi_m_n);
6143
6144         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6145         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6146                 pipe_config->pipe_bpp -= 2*3;
6147                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6148                               pipe_config->pipe_bpp);
6149                 needs_recompute = true;
6150                 pipe_config->bw_constrained = true;
6151
6152                 goto retry;
6153         }
6154
6155         if (needs_recompute)
6156                 return RETRY;
6157
6158         return ret;
6159 }
6160
6161 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6162                                      struct intel_crtc_state *pipe_config)
6163 {
6164         if (pipe_config->pipe_bpp > 24)
6165                 return false;
6166
6167         /* HSW can handle pixel rate up to cdclk? */
6168         if (IS_HASWELL(dev_priv))
6169                 return true;
6170
6171         /*
6172          * We compare against max which means we must take
6173          * the increased cdclk requirement into account when
6174          * calculating the new cdclk.
6175          *
6176          * Should measure whether using a lower cdclk w/o IPS
6177          */
6178         return pipe_config->pixel_rate <=
6179                 dev_priv->max_cdclk_freq * 95 / 100;
6180 }
6181
6182 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6183                                    struct intel_crtc_state *pipe_config)
6184 {
6185         struct drm_device *dev = crtc->base.dev;
6186         struct drm_i915_private *dev_priv = to_i915(dev);
6187
6188         pipe_config->ips_enabled = i915.enable_ips &&
6189                 hsw_crtc_supports_ips(crtc) &&
6190                 pipe_config_supports_ips(dev_priv, pipe_config);
6191 }
6192
6193 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6194 {
6195         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6196
6197         /* GDG double wide on either pipe, otherwise pipe A only */
6198         return INTEL_INFO(dev_priv)->gen < 4 &&
6199                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6200 }
6201
6202 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6203 {
6204         uint32_t pixel_rate;
6205
6206         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6207
6208         /*
6209          * We only use IF-ID interlacing. If we ever use
6210          * PF-ID we'll need to adjust the pixel_rate here.
6211          */
6212
6213         if (pipe_config->pch_pfit.enabled) {
6214                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6215                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6216
6217                 pipe_w = pipe_config->pipe_src_w;
6218                 pipe_h = pipe_config->pipe_src_h;
6219
6220                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6221                 pfit_h = pfit_size & 0xFFFF;
6222                 if (pipe_w < pfit_w)
6223                         pipe_w = pfit_w;
6224                 if (pipe_h < pfit_h)
6225                         pipe_h = pfit_h;
6226
6227                 if (WARN_ON(!pfit_w || !pfit_h))
6228                         return pixel_rate;
6229
6230                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6231                                      pfit_w * pfit_h);
6232         }
6233
6234         return pixel_rate;
6235 }
6236
6237 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6238 {
6239         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6240
6241         if (HAS_GMCH_DISPLAY(dev_priv))
6242                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6243                 crtc_state->pixel_rate =
6244                         crtc_state->base.adjusted_mode.crtc_clock;
6245         else
6246                 crtc_state->pixel_rate =
6247                         ilk_pipe_pixel_rate(crtc_state);
6248 }
6249
6250 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6251                                      struct intel_crtc_state *pipe_config)
6252 {
6253         struct drm_device *dev = crtc->base.dev;
6254         struct drm_i915_private *dev_priv = to_i915(dev);
6255         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6256         int clock_limit = dev_priv->max_dotclk_freq;
6257
6258         if (INTEL_GEN(dev_priv) < 4) {
6259                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6260
6261                 /*
6262                  * Enable double wide mode when the dot clock
6263                  * is > 90% of the (display) core speed.
6264                  */
6265                 if (intel_crtc_supports_double_wide(crtc) &&
6266                     adjusted_mode->crtc_clock > clock_limit) {
6267                         clock_limit = dev_priv->max_dotclk_freq;
6268                         pipe_config->double_wide = true;
6269                 }
6270         }
6271
6272         if (adjusted_mode->crtc_clock > clock_limit) {
6273                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6274                               adjusted_mode->crtc_clock, clock_limit,
6275                               yesno(pipe_config->double_wide));
6276                 return -EINVAL;
6277         }
6278
6279         /*
6280          * Pipe horizontal size must be even in:
6281          * - DVO ganged mode
6282          * - LVDS dual channel mode
6283          * - Double wide pipe
6284          */
6285         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6286              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6287                 pipe_config->pipe_src_w &= ~1;
6288
6289         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6290          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6291          */
6292         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6293                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6294                 return -EINVAL;
6295
6296         intel_crtc_compute_pixel_rate(pipe_config);
6297
6298         if (HAS_IPS(dev_priv))
6299                 hsw_compute_ips_config(crtc, pipe_config);
6300
6301         if (pipe_config->has_pch_encoder)
6302                 return ironlake_fdi_compute_config(crtc, pipe_config);
6303
6304         return 0;
6305 }
6306
6307 static void
6308 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6309 {
6310         while (*num > DATA_LINK_M_N_MASK ||
6311                *den > DATA_LINK_M_N_MASK) {
6312                 *num >>= 1;
6313                 *den >>= 1;
6314         }
6315 }
6316
6317 static void compute_m_n(unsigned int m, unsigned int n,
6318                         uint32_t *ret_m, uint32_t *ret_n)
6319 {
6320         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6321         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6322         intel_reduce_m_n_ratio(ret_m, ret_n);
6323 }
6324
6325 void
6326 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6327                        int pixel_clock, int link_clock,
6328                        struct intel_link_m_n *m_n)
6329 {
6330         m_n->tu = 64;
6331
6332         compute_m_n(bits_per_pixel * pixel_clock,
6333                     link_clock * nlanes * 8,
6334                     &m_n->gmch_m, &m_n->gmch_n);
6335
6336         compute_m_n(pixel_clock, link_clock,
6337                     &m_n->link_m, &m_n->link_n);
6338 }
6339
6340 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6341 {
6342         if (i915.panel_use_ssc >= 0)
6343                 return i915.panel_use_ssc != 0;
6344         return dev_priv->vbt.lvds_use_ssc
6345                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6346 }
6347
6348 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6349 {
6350         return (1 << dpll->n) << 16 | dpll->m2;
6351 }
6352
6353 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6354 {
6355         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6356 }
6357
6358 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6359                                      struct intel_crtc_state *crtc_state,
6360                                      struct dpll *reduced_clock)
6361 {
6362         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6363         u32 fp, fp2 = 0;
6364
6365         if (IS_PINEVIEW(dev_priv)) {
6366                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6367                 if (reduced_clock)
6368                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6369         } else {
6370                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6371                 if (reduced_clock)
6372                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6373         }
6374
6375         crtc_state->dpll_hw_state.fp0 = fp;
6376
6377         crtc->lowfreq_avail = false;
6378         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6379             reduced_clock) {
6380                 crtc_state->dpll_hw_state.fp1 = fp2;
6381                 crtc->lowfreq_avail = true;
6382         } else {
6383                 crtc_state->dpll_hw_state.fp1 = fp;
6384         }
6385 }
6386
6387 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6388                 pipe)
6389 {
6390         u32 reg_val;
6391
6392         /*
6393          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6394          * and set it to a reasonable value instead.
6395          */
6396         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6397         reg_val &= 0xffffff00;
6398         reg_val |= 0x00000030;
6399         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6400
6401         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6402         reg_val &= 0x8cffffff;
6403         reg_val = 0x8c000000;
6404         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6405
6406         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6407         reg_val &= 0xffffff00;
6408         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6409
6410         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6411         reg_val &= 0x00ffffff;
6412         reg_val |= 0xb0000000;
6413         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6414 }
6415
6416 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6417                                          struct intel_link_m_n *m_n)
6418 {
6419         struct drm_device *dev = crtc->base.dev;
6420         struct drm_i915_private *dev_priv = to_i915(dev);
6421         int pipe = crtc->pipe;
6422
6423         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6424         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6425         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6426         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6427 }
6428
6429 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6430                                          struct intel_link_m_n *m_n,
6431                                          struct intel_link_m_n *m2_n2)
6432 {
6433         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6434         int pipe = crtc->pipe;
6435         enum transcoder transcoder = crtc->config->cpu_transcoder;
6436
6437         if (INTEL_GEN(dev_priv) >= 5) {
6438                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6439                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6440                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6441                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6442                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6443                  * for gen < 8) and if DRRS is supported (to make sure the
6444                  * registers are not unnecessarily accessed).
6445                  */
6446                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6447                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6448                         I915_WRITE(PIPE_DATA_M2(transcoder),
6449                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6450                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6451                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6452                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6453                 }
6454         } else {
6455                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6456                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6457                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6458                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6459         }
6460 }
6461
6462 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6463 {
6464         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6465
6466         if (m_n == M1_N1) {
6467                 dp_m_n = &crtc->config->dp_m_n;
6468                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6469         } else if (m_n == M2_N2) {
6470
6471                 /*
6472                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6473                  * needs to be programmed into M1_N1.
6474                  */
6475                 dp_m_n = &crtc->config->dp_m2_n2;
6476         } else {
6477                 DRM_ERROR("Unsupported divider value\n");
6478                 return;
6479         }
6480
6481         if (crtc->config->has_pch_encoder)
6482                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6483         else
6484                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6485 }
6486
6487 static void vlv_compute_dpll(struct intel_crtc *crtc,
6488                              struct intel_crtc_state *pipe_config)
6489 {
6490         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6491                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6492         if (crtc->pipe != PIPE_A)
6493                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6494
6495         /* DPLL not used with DSI, but still need the rest set up */
6496         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6497                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6498                         DPLL_EXT_BUFFER_ENABLE_VLV;
6499
6500         pipe_config->dpll_hw_state.dpll_md =
6501                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6502 }
6503
6504 static void chv_compute_dpll(struct intel_crtc *crtc,
6505                              struct intel_crtc_state *pipe_config)
6506 {
6507         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6508                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6509         if (crtc->pipe != PIPE_A)
6510                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6511
6512         /* DPLL not used with DSI, but still need the rest set up */
6513         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6514                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6515
6516         pipe_config->dpll_hw_state.dpll_md =
6517                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6518 }
6519
6520 static void vlv_prepare_pll(struct intel_crtc *crtc,
6521                             const struct intel_crtc_state *pipe_config)
6522 {
6523         struct drm_device *dev = crtc->base.dev;
6524         struct drm_i915_private *dev_priv = to_i915(dev);
6525         enum pipe pipe = crtc->pipe;
6526         u32 mdiv;
6527         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6528         u32 coreclk, reg_val;
6529
6530         /* Enable Refclk */
6531         I915_WRITE(DPLL(pipe),
6532                    pipe_config->dpll_hw_state.dpll &
6533                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6534
6535         /* No need to actually set up the DPLL with DSI */
6536         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6537                 return;
6538
6539         mutex_lock(&dev_priv->sb_lock);
6540
6541         bestn = pipe_config->dpll.n;
6542         bestm1 = pipe_config->dpll.m1;
6543         bestm2 = pipe_config->dpll.m2;
6544         bestp1 = pipe_config->dpll.p1;
6545         bestp2 = pipe_config->dpll.p2;
6546
6547         /* See eDP HDMI DPIO driver vbios notes doc */
6548
6549         /* PLL B needs special handling */
6550         if (pipe == PIPE_B)
6551                 vlv_pllb_recal_opamp(dev_priv, pipe);
6552
6553         /* Set up Tx target for periodic Rcomp update */
6554         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6555
6556         /* Disable target IRef on PLL */
6557         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6558         reg_val &= 0x00ffffff;
6559         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6560
6561         /* Disable fast lock */
6562         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6563
6564         /* Set idtafcrecal before PLL is enabled */
6565         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6566         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6567         mdiv |= ((bestn << DPIO_N_SHIFT));
6568         mdiv |= (1 << DPIO_K_SHIFT);
6569
6570         /*
6571          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6572          * but we don't support that).
6573          * Note: don't use the DAC post divider as it seems unstable.
6574          */
6575         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6576         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6577
6578         mdiv |= DPIO_ENABLE_CALIBRATION;
6579         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6580
6581         /* Set HBR and RBR LPF coefficients */
6582         if (pipe_config->port_clock == 162000 ||
6583             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6584             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6585                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6586                                  0x009f0003);
6587         else
6588                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6589                                  0x00d0000f);
6590
6591         if (intel_crtc_has_dp_encoder(pipe_config)) {
6592                 /* Use SSC source */
6593                 if (pipe == PIPE_A)
6594                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6595                                          0x0df40000);
6596                 else
6597                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6598                                          0x0df70000);
6599         } else { /* HDMI or VGA */
6600                 /* Use bend source */
6601                 if (pipe == PIPE_A)
6602                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6603                                          0x0df70000);
6604                 else
6605                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6606                                          0x0df40000);
6607         }
6608
6609         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6610         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6611         if (intel_crtc_has_dp_encoder(crtc->config))
6612                 coreclk |= 0x01000000;
6613         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6614
6615         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6616         mutex_unlock(&dev_priv->sb_lock);
6617 }
6618
6619 static void chv_prepare_pll(struct intel_crtc *crtc,
6620                             const struct intel_crtc_state *pipe_config)
6621 {
6622         struct drm_device *dev = crtc->base.dev;
6623         struct drm_i915_private *dev_priv = to_i915(dev);
6624         enum pipe pipe = crtc->pipe;
6625         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6626         u32 loopfilter, tribuf_calcntr;
6627         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6628         u32 dpio_val;
6629         int vco;
6630
6631         /* Enable Refclk and SSC */
6632         I915_WRITE(DPLL(pipe),
6633                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6634
6635         /* No need to actually set up the DPLL with DSI */
6636         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6637                 return;
6638
6639         bestn = pipe_config->dpll.n;
6640         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6641         bestm1 = pipe_config->dpll.m1;
6642         bestm2 = pipe_config->dpll.m2 >> 22;
6643         bestp1 = pipe_config->dpll.p1;
6644         bestp2 = pipe_config->dpll.p2;
6645         vco = pipe_config->dpll.vco;
6646         dpio_val = 0;
6647         loopfilter = 0;
6648
6649         mutex_lock(&dev_priv->sb_lock);
6650
6651         /* p1 and p2 divider */
6652         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6653                         5 << DPIO_CHV_S1_DIV_SHIFT |
6654                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6655                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6656                         1 << DPIO_CHV_K_DIV_SHIFT);
6657
6658         /* Feedback post-divider - m2 */
6659         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6660
6661         /* Feedback refclk divider - n and m1 */
6662         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6663                         DPIO_CHV_M1_DIV_BY_2 |
6664                         1 << DPIO_CHV_N_DIV_SHIFT);
6665
6666         /* M2 fraction division */
6667         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6668
6669         /* M2 fraction division enable */
6670         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6671         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6672         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6673         if (bestm2_frac)
6674                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6675         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6676
6677         /* Program digital lock detect threshold */
6678         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6679         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6680                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6681         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6682         if (!bestm2_frac)
6683                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6684         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6685
6686         /* Loop filter */
6687         if (vco == 5400000) {
6688                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6689                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6690                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6691                 tribuf_calcntr = 0x9;
6692         } else if (vco <= 6200000) {
6693                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6694                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6695                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6696                 tribuf_calcntr = 0x9;
6697         } else if (vco <= 6480000) {
6698                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6699                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6700                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6701                 tribuf_calcntr = 0x8;
6702         } else {
6703                 /* Not supported. Apply the same limits as in the max case */
6704                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6705                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6706                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6707                 tribuf_calcntr = 0;
6708         }
6709         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6710
6711         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6712         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6713         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6714         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6715
6716         /* AFC Recal */
6717         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6718                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6719                         DPIO_AFC_RECAL);
6720
6721         mutex_unlock(&dev_priv->sb_lock);
6722 }
6723
6724 /**
6725  * vlv_force_pll_on - forcibly enable just the PLL
6726  * @dev_priv: i915 private structure
6727  * @pipe: pipe PLL to enable
6728  * @dpll: PLL configuration
6729  *
6730  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6731  * in cases where we need the PLL enabled even when @pipe is not going to
6732  * be enabled.
6733  */
6734 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6735                      const struct dpll *dpll)
6736 {
6737         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6738         struct intel_crtc_state *pipe_config;
6739
6740         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6741         if (!pipe_config)
6742                 return -ENOMEM;
6743
6744         pipe_config->base.crtc = &crtc->base;
6745         pipe_config->pixel_multiplier = 1;
6746         pipe_config->dpll = *dpll;
6747
6748         if (IS_CHERRYVIEW(dev_priv)) {
6749                 chv_compute_dpll(crtc, pipe_config);
6750                 chv_prepare_pll(crtc, pipe_config);
6751                 chv_enable_pll(crtc, pipe_config);
6752         } else {
6753                 vlv_compute_dpll(crtc, pipe_config);
6754                 vlv_prepare_pll(crtc, pipe_config);
6755                 vlv_enable_pll(crtc, pipe_config);
6756         }
6757
6758         kfree(pipe_config);
6759
6760         return 0;
6761 }
6762
6763 /**
6764  * vlv_force_pll_off - forcibly disable just the PLL
6765  * @dev_priv: i915 private structure
6766  * @pipe: pipe PLL to disable
6767  *
6768  * Disable the PLL for @pipe. To be used in cases where we need
6769  * the PLL enabled even when @pipe is not going to be enabled.
6770  */
6771 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6772 {
6773         if (IS_CHERRYVIEW(dev_priv))
6774                 chv_disable_pll(dev_priv, pipe);
6775         else
6776                 vlv_disable_pll(dev_priv, pipe);
6777 }
6778
6779 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6780                               struct intel_crtc_state *crtc_state,
6781                               struct dpll *reduced_clock)
6782 {
6783         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6784         u32 dpll;
6785         struct dpll *clock = &crtc_state->dpll;
6786
6787         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6788
6789         dpll = DPLL_VGA_MODE_DIS;
6790
6791         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6792                 dpll |= DPLLB_MODE_LVDS;
6793         else
6794                 dpll |= DPLLB_MODE_DAC_SERIAL;
6795
6796         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6797             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6798                 dpll |= (crtc_state->pixel_multiplier - 1)
6799                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6800         }
6801
6802         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6803             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6804                 dpll |= DPLL_SDVO_HIGH_SPEED;
6805
6806         if (intel_crtc_has_dp_encoder(crtc_state))
6807                 dpll |= DPLL_SDVO_HIGH_SPEED;
6808
6809         /* compute bitmask from p1 value */
6810         if (IS_PINEVIEW(dev_priv))
6811                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6812         else {
6813                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6814                 if (IS_G4X(dev_priv) && reduced_clock)
6815                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6816         }
6817         switch (clock->p2) {
6818         case 5:
6819                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6820                 break;
6821         case 7:
6822                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6823                 break;
6824         case 10:
6825                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6826                 break;
6827         case 14:
6828                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6829                 break;
6830         }
6831         if (INTEL_GEN(dev_priv) >= 4)
6832                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6833
6834         if (crtc_state->sdvo_tv_clock)
6835                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6836         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6837                  intel_panel_use_ssc(dev_priv))
6838                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6839         else
6840                 dpll |= PLL_REF_INPUT_DREFCLK;
6841
6842         dpll |= DPLL_VCO_ENABLE;
6843         crtc_state->dpll_hw_state.dpll = dpll;
6844
6845         if (INTEL_GEN(dev_priv) >= 4) {
6846                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6847                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6848                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6849         }
6850 }
6851
6852 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6853                               struct intel_crtc_state *crtc_state,
6854                               struct dpll *reduced_clock)
6855 {
6856         struct drm_device *dev = crtc->base.dev;
6857         struct drm_i915_private *dev_priv = to_i915(dev);
6858         u32 dpll;
6859         struct dpll *clock = &crtc_state->dpll;
6860
6861         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6862
6863         dpll = DPLL_VGA_MODE_DIS;
6864
6865         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6866                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6867         } else {
6868                 if (clock->p1 == 2)
6869                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6870                 else
6871                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6872                 if (clock->p2 == 4)
6873                         dpll |= PLL_P2_DIVIDE_BY_4;
6874         }
6875
6876         if (!IS_I830(dev_priv) &&
6877             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6878                 dpll |= DPLL_DVO_2X_MODE;
6879
6880         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6881             intel_panel_use_ssc(dev_priv))
6882                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6883         else
6884                 dpll |= PLL_REF_INPUT_DREFCLK;
6885
6886         dpll |= DPLL_VCO_ENABLE;
6887         crtc_state->dpll_hw_state.dpll = dpll;
6888 }
6889
6890 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6891 {
6892         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6893         enum pipe pipe = intel_crtc->pipe;
6894         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6895         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6896         uint32_t crtc_vtotal, crtc_vblank_end;
6897         int vsyncshift = 0;
6898
6899         /* We need to be careful not to changed the adjusted mode, for otherwise
6900          * the hw state checker will get angry at the mismatch. */
6901         crtc_vtotal = adjusted_mode->crtc_vtotal;
6902         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6903
6904         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6905                 /* the chip adds 2 halflines automatically */
6906                 crtc_vtotal -= 1;
6907                 crtc_vblank_end -= 1;
6908
6909                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6910                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6911                 else
6912                         vsyncshift = adjusted_mode->crtc_hsync_start -
6913                                 adjusted_mode->crtc_htotal / 2;
6914                 if (vsyncshift < 0)
6915                         vsyncshift += adjusted_mode->crtc_htotal;
6916         }
6917
6918         if (INTEL_GEN(dev_priv) > 3)
6919                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6920
6921         I915_WRITE(HTOTAL(cpu_transcoder),
6922                    (adjusted_mode->crtc_hdisplay - 1) |
6923                    ((adjusted_mode->crtc_htotal - 1) << 16));
6924         I915_WRITE(HBLANK(cpu_transcoder),
6925                    (adjusted_mode->crtc_hblank_start - 1) |
6926                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6927         I915_WRITE(HSYNC(cpu_transcoder),
6928                    (adjusted_mode->crtc_hsync_start - 1) |
6929                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6930
6931         I915_WRITE(VTOTAL(cpu_transcoder),
6932                    (adjusted_mode->crtc_vdisplay - 1) |
6933                    ((crtc_vtotal - 1) << 16));
6934         I915_WRITE(VBLANK(cpu_transcoder),
6935                    (adjusted_mode->crtc_vblank_start - 1) |
6936                    ((crtc_vblank_end - 1) << 16));
6937         I915_WRITE(VSYNC(cpu_transcoder),
6938                    (adjusted_mode->crtc_vsync_start - 1) |
6939                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6940
6941         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6942          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6943          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6944          * bits. */
6945         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6946             (pipe == PIPE_B || pipe == PIPE_C))
6947                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6948
6949 }
6950
6951 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6952 {
6953         struct drm_device *dev = intel_crtc->base.dev;
6954         struct drm_i915_private *dev_priv = to_i915(dev);
6955         enum pipe pipe = intel_crtc->pipe;
6956
6957         /* pipesrc controls the size that is scaled from, which should
6958          * always be the user's requested size.
6959          */
6960         I915_WRITE(PIPESRC(pipe),
6961                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6962                    (intel_crtc->config->pipe_src_h - 1));
6963 }
6964
6965 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6966                                    struct intel_crtc_state *pipe_config)
6967 {
6968         struct drm_device *dev = crtc->base.dev;
6969         struct drm_i915_private *dev_priv = to_i915(dev);
6970         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6971         uint32_t tmp;
6972
6973         tmp = I915_READ(HTOTAL(cpu_transcoder));
6974         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6975         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6976         tmp = I915_READ(HBLANK(cpu_transcoder));
6977         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6978         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6979         tmp = I915_READ(HSYNC(cpu_transcoder));
6980         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6981         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6982
6983         tmp = I915_READ(VTOTAL(cpu_transcoder));
6984         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6985         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6986         tmp = I915_READ(VBLANK(cpu_transcoder));
6987         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6988         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6989         tmp = I915_READ(VSYNC(cpu_transcoder));
6990         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6991         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6992
6993         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6994                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6995                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6996                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6997         }
6998 }
6999
7000 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7001                                     struct intel_crtc_state *pipe_config)
7002 {
7003         struct drm_device *dev = crtc->base.dev;
7004         struct drm_i915_private *dev_priv = to_i915(dev);
7005         u32 tmp;
7006
7007         tmp = I915_READ(PIPESRC(crtc->pipe));
7008         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7009         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7010
7011         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7012         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7013 }
7014
7015 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7016                                  struct intel_crtc_state *pipe_config)
7017 {
7018         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7019         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7020         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7021         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7022
7023         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7024         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7025         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7026         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7027
7028         mode->flags = pipe_config->base.adjusted_mode.flags;
7029         mode->type = DRM_MODE_TYPE_DRIVER;
7030
7031         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7032
7033         mode->hsync = drm_mode_hsync(mode);
7034         mode->vrefresh = drm_mode_vrefresh(mode);
7035         drm_mode_set_name(mode);
7036 }
7037
7038 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7039 {
7040         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7041         uint32_t pipeconf;
7042
7043         pipeconf = 0;
7044
7045         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7046             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7047                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7048
7049         if (intel_crtc->config->double_wide)
7050                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7051
7052         /* only g4x and later have fancy bpc/dither controls */
7053         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7054             IS_CHERRYVIEW(dev_priv)) {
7055                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7056                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7057                         pipeconf |= PIPECONF_DITHER_EN |
7058                                     PIPECONF_DITHER_TYPE_SP;
7059
7060                 switch (intel_crtc->config->pipe_bpp) {
7061                 case 18:
7062                         pipeconf |= PIPECONF_6BPC;
7063                         break;
7064                 case 24:
7065                         pipeconf |= PIPECONF_8BPC;
7066                         break;
7067                 case 30:
7068                         pipeconf |= PIPECONF_10BPC;
7069                         break;
7070                 default:
7071                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7072                         BUG();
7073                 }
7074         }
7075
7076         if (HAS_PIPE_CXSR(dev_priv)) {
7077                 if (intel_crtc->lowfreq_avail) {
7078                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7079                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7080                 } else {
7081                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7082                 }
7083         }
7084
7085         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7086                 if (INTEL_GEN(dev_priv) < 4 ||
7087                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7088                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7089                 else
7090                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7091         } else
7092                 pipeconf |= PIPECONF_PROGRESSIVE;
7093
7094         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7095              intel_crtc->config->limited_color_range)
7096                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7097
7098         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7099         POSTING_READ(PIPECONF(intel_crtc->pipe));
7100 }
7101
7102 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7103                                    struct intel_crtc_state *crtc_state)
7104 {
7105         struct drm_device *dev = crtc->base.dev;
7106         struct drm_i915_private *dev_priv = to_i915(dev);
7107         const struct intel_limit *limit;
7108         int refclk = 48000;
7109
7110         memset(&crtc_state->dpll_hw_state, 0,
7111                sizeof(crtc_state->dpll_hw_state));
7112
7113         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7114                 if (intel_panel_use_ssc(dev_priv)) {
7115                         refclk = dev_priv->vbt.lvds_ssc_freq;
7116                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7117                 }
7118
7119                 limit = &intel_limits_i8xx_lvds;
7120         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7121                 limit = &intel_limits_i8xx_dvo;
7122         } else {
7123                 limit = &intel_limits_i8xx_dac;
7124         }
7125
7126         if (!crtc_state->clock_set &&
7127             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7128                                  refclk, NULL, &crtc_state->dpll)) {
7129                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7130                 return -EINVAL;
7131         }
7132
7133         i8xx_compute_dpll(crtc, crtc_state, NULL);
7134
7135         return 0;
7136 }
7137
7138 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7139                                   struct intel_crtc_state *crtc_state)
7140 {
7141         struct drm_device *dev = crtc->base.dev;
7142         struct drm_i915_private *dev_priv = to_i915(dev);
7143         const struct intel_limit *limit;
7144         int refclk = 96000;
7145
7146         memset(&crtc_state->dpll_hw_state, 0,
7147                sizeof(crtc_state->dpll_hw_state));
7148
7149         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7150                 if (intel_panel_use_ssc(dev_priv)) {
7151                         refclk = dev_priv->vbt.lvds_ssc_freq;
7152                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7153                 }
7154
7155                 if (intel_is_dual_link_lvds(dev))
7156                         limit = &intel_limits_g4x_dual_channel_lvds;
7157                 else
7158                         limit = &intel_limits_g4x_single_channel_lvds;
7159         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7160                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7161                 limit = &intel_limits_g4x_hdmi;
7162         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7163                 limit = &intel_limits_g4x_sdvo;
7164         } else {
7165                 /* The option is for other outputs */
7166                 limit = &intel_limits_i9xx_sdvo;
7167         }
7168
7169         if (!crtc_state->clock_set &&
7170             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7171                                 refclk, NULL, &crtc_state->dpll)) {
7172                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7173                 return -EINVAL;
7174         }
7175
7176         i9xx_compute_dpll(crtc, crtc_state, NULL);
7177
7178         return 0;
7179 }
7180
7181 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7182                                   struct intel_crtc_state *crtc_state)
7183 {
7184         struct drm_device *dev = crtc->base.dev;
7185         struct drm_i915_private *dev_priv = to_i915(dev);
7186         const struct intel_limit *limit;
7187         int refclk = 96000;
7188
7189         memset(&crtc_state->dpll_hw_state, 0,
7190                sizeof(crtc_state->dpll_hw_state));
7191
7192         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7193                 if (intel_panel_use_ssc(dev_priv)) {
7194                         refclk = dev_priv->vbt.lvds_ssc_freq;
7195                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7196                 }
7197
7198                 limit = &intel_limits_pineview_lvds;
7199         } else {
7200                 limit = &intel_limits_pineview_sdvo;
7201         }
7202
7203         if (!crtc_state->clock_set &&
7204             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7205                                 refclk, NULL, &crtc_state->dpll)) {
7206                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7207                 return -EINVAL;
7208         }
7209
7210         i9xx_compute_dpll(crtc, crtc_state, NULL);
7211
7212         return 0;
7213 }
7214
7215 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7216                                    struct intel_crtc_state *crtc_state)
7217 {
7218         struct drm_device *dev = crtc->base.dev;
7219         struct drm_i915_private *dev_priv = to_i915(dev);
7220         const struct intel_limit *limit;
7221         int refclk = 96000;
7222
7223         memset(&crtc_state->dpll_hw_state, 0,
7224                sizeof(crtc_state->dpll_hw_state));
7225
7226         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7227                 if (intel_panel_use_ssc(dev_priv)) {
7228                         refclk = dev_priv->vbt.lvds_ssc_freq;
7229                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7230                 }
7231
7232                 limit = &intel_limits_i9xx_lvds;
7233         } else {
7234                 limit = &intel_limits_i9xx_sdvo;
7235         }
7236
7237         if (!crtc_state->clock_set &&
7238             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7239                                  refclk, NULL, &crtc_state->dpll)) {
7240                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7241                 return -EINVAL;
7242         }
7243
7244         i9xx_compute_dpll(crtc, crtc_state, NULL);
7245
7246         return 0;
7247 }
7248
7249 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7250                                   struct intel_crtc_state *crtc_state)
7251 {
7252         int refclk = 100000;
7253         const struct intel_limit *limit = &intel_limits_chv;
7254
7255         memset(&crtc_state->dpll_hw_state, 0,
7256                sizeof(crtc_state->dpll_hw_state));
7257
7258         if (!crtc_state->clock_set &&
7259             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7260                                 refclk, NULL, &crtc_state->dpll)) {
7261                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7262                 return -EINVAL;
7263         }
7264
7265         chv_compute_dpll(crtc, crtc_state);
7266
7267         return 0;
7268 }
7269
7270 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7271                                   struct intel_crtc_state *crtc_state)
7272 {
7273         int refclk = 100000;
7274         const struct intel_limit *limit = &intel_limits_vlv;
7275
7276         memset(&crtc_state->dpll_hw_state, 0,
7277                sizeof(crtc_state->dpll_hw_state));
7278
7279         if (!crtc_state->clock_set &&
7280             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7281                                 refclk, NULL, &crtc_state->dpll)) {
7282                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7283                 return -EINVAL;
7284         }
7285
7286         vlv_compute_dpll(crtc, crtc_state);
7287
7288         return 0;
7289 }
7290
7291 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7292                                  struct intel_crtc_state *pipe_config)
7293 {
7294         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7295         uint32_t tmp;
7296
7297         if (INTEL_GEN(dev_priv) <= 3 &&
7298             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7299                 return;
7300
7301         tmp = I915_READ(PFIT_CONTROL);
7302         if (!(tmp & PFIT_ENABLE))
7303                 return;
7304
7305         /* Check whether the pfit is attached to our pipe. */
7306         if (INTEL_GEN(dev_priv) < 4) {
7307                 if (crtc->pipe != PIPE_B)
7308                         return;
7309         } else {
7310                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7311                         return;
7312         }
7313
7314         pipe_config->gmch_pfit.control = tmp;
7315         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7316 }
7317
7318 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7319                                struct intel_crtc_state *pipe_config)
7320 {
7321         struct drm_device *dev = crtc->base.dev;
7322         struct drm_i915_private *dev_priv = to_i915(dev);
7323         int pipe = pipe_config->cpu_transcoder;
7324         struct dpll clock;
7325         u32 mdiv;
7326         int refclk = 100000;
7327
7328         /* In case of DSI, DPLL will not be used */
7329         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7330                 return;
7331
7332         mutex_lock(&dev_priv->sb_lock);
7333         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7334         mutex_unlock(&dev_priv->sb_lock);
7335
7336         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7337         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7338         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7339         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7340         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7341
7342         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7343 }
7344
7345 static void
7346 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7347                               struct intel_initial_plane_config *plane_config)
7348 {
7349         struct drm_device *dev = crtc->base.dev;
7350         struct drm_i915_private *dev_priv = to_i915(dev);
7351         u32 val, base, offset;
7352         int pipe = crtc->pipe, plane = crtc->plane;
7353         int fourcc, pixel_format;
7354         unsigned int aligned_height;
7355         struct drm_framebuffer *fb;
7356         struct intel_framebuffer *intel_fb;
7357
7358         val = I915_READ(DSPCNTR(plane));
7359         if (!(val & DISPLAY_PLANE_ENABLE))
7360                 return;
7361
7362         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7363         if (!intel_fb) {
7364                 DRM_DEBUG_KMS("failed to alloc fb\n");
7365                 return;
7366         }
7367
7368         fb = &intel_fb->base;
7369
7370         fb->dev = dev;
7371
7372         if (INTEL_GEN(dev_priv) >= 4) {
7373                 if (val & DISPPLANE_TILED) {
7374                         plane_config->tiling = I915_TILING_X;
7375                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7376                 }
7377         }
7378
7379         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7380         fourcc = i9xx_format_to_fourcc(pixel_format);
7381         fb->format = drm_format_info(fourcc);
7382
7383         if (INTEL_GEN(dev_priv) >= 4) {
7384                 if (plane_config->tiling)
7385                         offset = I915_READ(DSPTILEOFF(plane));
7386                 else
7387                         offset = I915_READ(DSPLINOFF(plane));
7388                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7389         } else {
7390                 base = I915_READ(DSPADDR(plane));
7391         }
7392         plane_config->base = base;
7393
7394         val = I915_READ(PIPESRC(pipe));
7395         fb->width = ((val >> 16) & 0xfff) + 1;
7396         fb->height = ((val >> 0) & 0xfff) + 1;
7397
7398         val = I915_READ(DSPSTRIDE(pipe));
7399         fb->pitches[0] = val & 0xffffffc0;
7400
7401         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7402
7403         plane_config->size = fb->pitches[0] * aligned_height;
7404
7405         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7406                       pipe_name(pipe), plane, fb->width, fb->height,
7407                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7408                       plane_config->size);
7409
7410         plane_config->fb = intel_fb;
7411 }
7412
7413 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7414                                struct intel_crtc_state *pipe_config)
7415 {
7416         struct drm_device *dev = crtc->base.dev;
7417         struct drm_i915_private *dev_priv = to_i915(dev);
7418         int pipe = pipe_config->cpu_transcoder;
7419         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7420         struct dpll clock;
7421         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7422         int refclk = 100000;
7423
7424         /* In case of DSI, DPLL will not be used */
7425         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7426                 return;
7427
7428         mutex_lock(&dev_priv->sb_lock);
7429         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7430         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7431         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7432         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7433         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7434         mutex_unlock(&dev_priv->sb_lock);
7435
7436         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7437         clock.m2 = (pll_dw0 & 0xff) << 22;
7438         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7439                 clock.m2 |= pll_dw2 & 0x3fffff;
7440         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7441         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7442         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7443
7444         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7445 }
7446
7447 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7448                                  struct intel_crtc_state *pipe_config)
7449 {
7450         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7451         enum intel_display_power_domain power_domain;
7452         uint32_t tmp;
7453         bool ret;
7454
7455         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7456         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7457                 return false;
7458
7459         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7460         pipe_config->shared_dpll = NULL;
7461
7462         ret = false;
7463
7464         tmp = I915_READ(PIPECONF(crtc->pipe));
7465         if (!(tmp & PIPECONF_ENABLE))
7466                 goto out;
7467
7468         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7469             IS_CHERRYVIEW(dev_priv)) {
7470                 switch (tmp & PIPECONF_BPC_MASK) {
7471                 case PIPECONF_6BPC:
7472                         pipe_config->pipe_bpp = 18;
7473                         break;
7474                 case PIPECONF_8BPC:
7475                         pipe_config->pipe_bpp = 24;
7476                         break;
7477                 case PIPECONF_10BPC:
7478                         pipe_config->pipe_bpp = 30;
7479                         break;
7480                 default:
7481                         break;
7482                 }
7483         }
7484
7485         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7486             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7487                 pipe_config->limited_color_range = true;
7488
7489         if (INTEL_GEN(dev_priv) < 4)
7490                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7491
7492         intel_get_pipe_timings(crtc, pipe_config);
7493         intel_get_pipe_src_size(crtc, pipe_config);
7494
7495         i9xx_get_pfit_config(crtc, pipe_config);
7496
7497         if (INTEL_GEN(dev_priv) >= 4) {
7498                 /* No way to read it out on pipes B and C */
7499                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7500                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7501                 else
7502                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7503                 pipe_config->pixel_multiplier =
7504                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7505                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7506                 pipe_config->dpll_hw_state.dpll_md = tmp;
7507         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7508                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7509                 tmp = I915_READ(DPLL(crtc->pipe));
7510                 pipe_config->pixel_multiplier =
7511                         ((tmp & SDVO_MULTIPLIER_MASK)
7512                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7513         } else {
7514                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7515                  * port and will be fixed up in the encoder->get_config
7516                  * function. */
7517                 pipe_config->pixel_multiplier = 1;
7518         }
7519         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7520         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7521                 /*
7522                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7523                  * on 830. Filter it out here so that we don't
7524                  * report errors due to that.
7525                  */
7526                 if (IS_I830(dev_priv))
7527                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7528
7529                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7530                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7531         } else {
7532                 /* Mask out read-only status bits. */
7533                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7534                                                      DPLL_PORTC_READY_MASK |
7535                                                      DPLL_PORTB_READY_MASK);
7536         }
7537
7538         if (IS_CHERRYVIEW(dev_priv))
7539                 chv_crtc_clock_get(crtc, pipe_config);
7540         else if (IS_VALLEYVIEW(dev_priv))
7541                 vlv_crtc_clock_get(crtc, pipe_config);
7542         else
7543                 i9xx_crtc_clock_get(crtc, pipe_config);
7544
7545         /*
7546          * Normally the dotclock is filled in by the encoder .get_config()
7547          * but in case the pipe is enabled w/o any ports we need a sane
7548          * default.
7549          */
7550         pipe_config->base.adjusted_mode.crtc_clock =
7551                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7552
7553         ret = true;
7554
7555 out:
7556         intel_display_power_put(dev_priv, power_domain);
7557
7558         return ret;
7559 }
7560
7561 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7562 {
7563         struct intel_encoder *encoder;
7564         int i;
7565         u32 val, final;
7566         bool has_lvds = false;
7567         bool has_cpu_edp = false;
7568         bool has_panel = false;
7569         bool has_ck505 = false;
7570         bool can_ssc = false;
7571         bool using_ssc_source = false;
7572
7573         /* We need to take the global config into account */
7574         for_each_intel_encoder(&dev_priv->drm, encoder) {
7575                 switch (encoder->type) {
7576                 case INTEL_OUTPUT_LVDS:
7577                         has_panel = true;
7578                         has_lvds = true;
7579                         break;
7580                 case INTEL_OUTPUT_EDP:
7581                         has_panel = true;
7582                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7583                                 has_cpu_edp = true;
7584                         break;
7585                 default:
7586                         break;
7587                 }
7588         }
7589
7590         if (HAS_PCH_IBX(dev_priv)) {
7591                 has_ck505 = dev_priv->vbt.display_clock_mode;
7592                 can_ssc = has_ck505;
7593         } else {
7594                 has_ck505 = false;
7595                 can_ssc = true;
7596         }
7597
7598         /* Check if any DPLLs are using the SSC source */
7599         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7600                 u32 temp = I915_READ(PCH_DPLL(i));
7601
7602                 if (!(temp & DPLL_VCO_ENABLE))
7603                         continue;
7604
7605                 if ((temp & PLL_REF_INPUT_MASK) ==
7606                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7607                         using_ssc_source = true;
7608                         break;
7609                 }
7610         }
7611
7612         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7613                       has_panel, has_lvds, has_ck505, using_ssc_source);
7614
7615         /* Ironlake: try to setup display ref clock before DPLL
7616          * enabling. This is only under driver's control after
7617          * PCH B stepping, previous chipset stepping should be
7618          * ignoring this setting.
7619          */
7620         val = I915_READ(PCH_DREF_CONTROL);
7621
7622         /* As we must carefully and slowly disable/enable each source in turn,
7623          * compute the final state we want first and check if we need to
7624          * make any changes at all.
7625          */
7626         final = val;
7627         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7628         if (has_ck505)
7629                 final |= DREF_NONSPREAD_CK505_ENABLE;
7630         else
7631                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7632
7633         final &= ~DREF_SSC_SOURCE_MASK;
7634         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7635         final &= ~DREF_SSC1_ENABLE;
7636
7637         if (has_panel) {
7638                 final |= DREF_SSC_SOURCE_ENABLE;
7639
7640                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7641                         final |= DREF_SSC1_ENABLE;
7642
7643                 if (has_cpu_edp) {
7644                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7645                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7646                         else
7647                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7648                 } else
7649                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7650         } else if (using_ssc_source) {
7651                 final |= DREF_SSC_SOURCE_ENABLE;
7652                 final |= DREF_SSC1_ENABLE;
7653         }
7654
7655         if (final == val)
7656                 return;
7657
7658         /* Always enable nonspread source */
7659         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7660
7661         if (has_ck505)
7662                 val |= DREF_NONSPREAD_CK505_ENABLE;
7663         else
7664                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7665
7666         if (has_panel) {
7667                 val &= ~DREF_SSC_SOURCE_MASK;
7668                 val |= DREF_SSC_SOURCE_ENABLE;
7669
7670                 /* SSC must be turned on before enabling the CPU output  */
7671                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7672                         DRM_DEBUG_KMS("Using SSC on panel\n");
7673                         val |= DREF_SSC1_ENABLE;
7674                 } else
7675                         val &= ~DREF_SSC1_ENABLE;
7676
7677                 /* Get SSC going before enabling the outputs */
7678                 I915_WRITE(PCH_DREF_CONTROL, val);
7679                 POSTING_READ(PCH_DREF_CONTROL);
7680                 udelay(200);
7681
7682                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7683
7684                 /* Enable CPU source on CPU attached eDP */
7685                 if (has_cpu_edp) {
7686                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7687                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7688                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7689                         } else
7690                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7691                 } else
7692                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7693
7694                 I915_WRITE(PCH_DREF_CONTROL, val);
7695                 POSTING_READ(PCH_DREF_CONTROL);
7696                 udelay(200);
7697         } else {
7698                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7699
7700                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7701
7702                 /* Turn off CPU output */
7703                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7704
7705                 I915_WRITE(PCH_DREF_CONTROL, val);
7706                 POSTING_READ(PCH_DREF_CONTROL);
7707                 udelay(200);
7708
7709                 if (!using_ssc_source) {
7710                         DRM_DEBUG_KMS("Disabling SSC source\n");
7711
7712                         /* Turn off the SSC source */
7713                         val &= ~DREF_SSC_SOURCE_MASK;
7714                         val |= DREF_SSC_SOURCE_DISABLE;
7715
7716                         /* Turn off SSC1 */
7717                         val &= ~DREF_SSC1_ENABLE;
7718
7719                         I915_WRITE(PCH_DREF_CONTROL, val);
7720                         POSTING_READ(PCH_DREF_CONTROL);
7721                         udelay(200);
7722                 }
7723         }
7724
7725         BUG_ON(val != final);
7726 }
7727
7728 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7729 {
7730         uint32_t tmp;
7731
7732         tmp = I915_READ(SOUTH_CHICKEN2);
7733         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7734         I915_WRITE(SOUTH_CHICKEN2, tmp);
7735
7736         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7737                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7738                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7739
7740         tmp = I915_READ(SOUTH_CHICKEN2);
7741         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7742         I915_WRITE(SOUTH_CHICKEN2, tmp);
7743
7744         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7745                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7746                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7747 }
7748
7749 /* WaMPhyProgramming:hsw */
7750 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7751 {
7752         uint32_t tmp;
7753
7754         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7755         tmp &= ~(0xFF << 24);
7756         tmp |= (0x12 << 24);
7757         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7758
7759         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7760         tmp |= (1 << 11);
7761         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7762
7763         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7764         tmp |= (1 << 11);
7765         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7766
7767         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7768         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7769         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7770
7771         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7772         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7773         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7774
7775         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7776         tmp &= ~(7 << 13);
7777         tmp |= (5 << 13);
7778         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7779
7780         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7781         tmp &= ~(7 << 13);
7782         tmp |= (5 << 13);
7783         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7784
7785         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7786         tmp &= ~0xFF;
7787         tmp |= 0x1C;
7788         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7789
7790         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7791         tmp &= ~0xFF;
7792         tmp |= 0x1C;
7793         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7794
7795         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7796         tmp &= ~(0xFF << 16);
7797         tmp |= (0x1C << 16);
7798         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7799
7800         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7801         tmp &= ~(0xFF << 16);
7802         tmp |= (0x1C << 16);
7803         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7804
7805         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7806         tmp |= (1 << 27);
7807         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7808
7809         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7810         tmp |= (1 << 27);
7811         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7812
7813         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7814         tmp &= ~(0xF << 28);
7815         tmp |= (4 << 28);
7816         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7817
7818         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7819         tmp &= ~(0xF << 28);
7820         tmp |= (4 << 28);
7821         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7822 }
7823
7824 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7825  * Programming" based on the parameters passed:
7826  * - Sequence to enable CLKOUT_DP
7827  * - Sequence to enable CLKOUT_DP without spread
7828  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7829  */
7830 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7831                                  bool with_spread, bool with_fdi)
7832 {
7833         uint32_t reg, tmp;
7834
7835         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7836                 with_spread = true;
7837         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7838             with_fdi, "LP PCH doesn't have FDI\n"))
7839                 with_fdi = false;
7840
7841         mutex_lock(&dev_priv->sb_lock);
7842
7843         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7844         tmp &= ~SBI_SSCCTL_DISABLE;
7845         tmp |= SBI_SSCCTL_PATHALT;
7846         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7847
7848         udelay(24);
7849
7850         if (with_spread) {
7851                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7852                 tmp &= ~SBI_SSCCTL_PATHALT;
7853                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7854
7855                 if (with_fdi) {
7856                         lpt_reset_fdi_mphy(dev_priv);
7857                         lpt_program_fdi_mphy(dev_priv);
7858                 }
7859         }
7860
7861         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7862         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7863         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7864         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7865
7866         mutex_unlock(&dev_priv->sb_lock);
7867 }
7868
7869 /* Sequence to disable CLKOUT_DP */
7870 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7871 {
7872         uint32_t reg, tmp;
7873
7874         mutex_lock(&dev_priv->sb_lock);
7875
7876         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7877         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7878         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7879         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7880
7881         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7882         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7883                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7884                         tmp |= SBI_SSCCTL_PATHALT;
7885                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7886                         udelay(32);
7887                 }
7888                 tmp |= SBI_SSCCTL_DISABLE;
7889                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7890         }
7891
7892         mutex_unlock(&dev_priv->sb_lock);
7893 }
7894
7895 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7896
7897 static const uint16_t sscdivintphase[] = {
7898         [BEND_IDX( 50)] = 0x3B23,
7899         [BEND_IDX( 45)] = 0x3B23,
7900         [BEND_IDX( 40)] = 0x3C23,
7901         [BEND_IDX( 35)] = 0x3C23,
7902         [BEND_IDX( 30)] = 0x3D23,
7903         [BEND_IDX( 25)] = 0x3D23,
7904         [BEND_IDX( 20)] = 0x3E23,
7905         [BEND_IDX( 15)] = 0x3E23,
7906         [BEND_IDX( 10)] = 0x3F23,
7907         [BEND_IDX(  5)] = 0x3F23,
7908         [BEND_IDX(  0)] = 0x0025,
7909         [BEND_IDX( -5)] = 0x0025,
7910         [BEND_IDX(-10)] = 0x0125,
7911         [BEND_IDX(-15)] = 0x0125,
7912         [BEND_IDX(-20)] = 0x0225,
7913         [BEND_IDX(-25)] = 0x0225,
7914         [BEND_IDX(-30)] = 0x0325,
7915         [BEND_IDX(-35)] = 0x0325,
7916         [BEND_IDX(-40)] = 0x0425,
7917         [BEND_IDX(-45)] = 0x0425,
7918         [BEND_IDX(-50)] = 0x0525,
7919 };
7920
7921 /*
7922  * Bend CLKOUT_DP
7923  * steps -50 to 50 inclusive, in steps of 5
7924  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7925  * change in clock period = -(steps / 10) * 5.787 ps
7926  */
7927 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7928 {
7929         uint32_t tmp;
7930         int idx = BEND_IDX(steps);
7931
7932         if (WARN_ON(steps % 5 != 0))
7933                 return;
7934
7935         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7936                 return;
7937
7938         mutex_lock(&dev_priv->sb_lock);
7939
7940         if (steps % 10 != 0)
7941                 tmp = 0xAAAAAAAB;
7942         else
7943                 tmp = 0x00000000;
7944         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7945
7946         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7947         tmp &= 0xffff0000;
7948         tmp |= sscdivintphase[idx];
7949         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7950
7951         mutex_unlock(&dev_priv->sb_lock);
7952 }
7953
7954 #undef BEND_IDX
7955
7956 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7957 {
7958         struct intel_encoder *encoder;
7959         bool has_vga = false;
7960
7961         for_each_intel_encoder(&dev_priv->drm, encoder) {
7962                 switch (encoder->type) {
7963                 case INTEL_OUTPUT_ANALOG:
7964                         has_vga = true;
7965                         break;
7966                 default:
7967                         break;
7968                 }
7969         }
7970
7971         if (has_vga) {
7972                 lpt_bend_clkout_dp(dev_priv, 0);
7973                 lpt_enable_clkout_dp(dev_priv, true, true);
7974         } else {
7975                 lpt_disable_clkout_dp(dev_priv);
7976         }
7977 }
7978
7979 /*
7980  * Initialize reference clocks when the driver loads
7981  */
7982 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7983 {
7984         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7985                 ironlake_init_pch_refclk(dev_priv);
7986         else if (HAS_PCH_LPT(dev_priv))
7987                 lpt_init_pch_refclk(dev_priv);
7988 }
7989
7990 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7991 {
7992         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7994         int pipe = intel_crtc->pipe;
7995         uint32_t val;
7996
7997         val = 0;
7998
7999         switch (intel_crtc->config->pipe_bpp) {
8000         case 18:
8001                 val |= PIPECONF_6BPC;
8002                 break;
8003         case 24:
8004                 val |= PIPECONF_8BPC;
8005                 break;
8006         case 30:
8007                 val |= PIPECONF_10BPC;
8008                 break;
8009         case 36:
8010                 val |= PIPECONF_12BPC;
8011                 break;
8012         default:
8013                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8014                 BUG();
8015         }
8016
8017         if (intel_crtc->config->dither)
8018                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8019
8020         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8021                 val |= PIPECONF_INTERLACED_ILK;
8022         else
8023                 val |= PIPECONF_PROGRESSIVE;
8024
8025         if (intel_crtc->config->limited_color_range)
8026                 val |= PIPECONF_COLOR_RANGE_SELECT;
8027
8028         I915_WRITE(PIPECONF(pipe), val);
8029         POSTING_READ(PIPECONF(pipe));
8030 }
8031
8032 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8033 {
8034         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8036         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8037         u32 val = 0;
8038
8039         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8040                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8041
8042         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8043                 val |= PIPECONF_INTERLACED_ILK;
8044         else
8045                 val |= PIPECONF_PROGRESSIVE;
8046
8047         I915_WRITE(PIPECONF(cpu_transcoder), val);
8048         POSTING_READ(PIPECONF(cpu_transcoder));
8049 }
8050
8051 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8052 {
8053         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8055
8056         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8057                 u32 val = 0;
8058
8059                 switch (intel_crtc->config->pipe_bpp) {
8060                 case 18:
8061                         val |= PIPEMISC_DITHER_6_BPC;
8062                         break;
8063                 case 24:
8064                         val |= PIPEMISC_DITHER_8_BPC;
8065                         break;
8066                 case 30:
8067                         val |= PIPEMISC_DITHER_10_BPC;
8068                         break;
8069                 case 36:
8070                         val |= PIPEMISC_DITHER_12_BPC;
8071                         break;
8072                 default:
8073                         /* Case prevented by pipe_config_set_bpp. */
8074                         BUG();
8075                 }
8076
8077                 if (intel_crtc->config->dither)
8078                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8079
8080                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8081         }
8082 }
8083
8084 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8085 {
8086         /*
8087          * Account for spread spectrum to avoid
8088          * oversubscribing the link. Max center spread
8089          * is 2.5%; use 5% for safety's sake.
8090          */
8091         u32 bps = target_clock * bpp * 21 / 20;
8092         return DIV_ROUND_UP(bps, link_bw * 8);
8093 }
8094
8095 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8096 {
8097         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8098 }
8099
8100 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8101                                   struct intel_crtc_state *crtc_state,
8102                                   struct dpll *reduced_clock)
8103 {
8104         struct drm_crtc *crtc = &intel_crtc->base;
8105         struct drm_device *dev = crtc->dev;
8106         struct drm_i915_private *dev_priv = to_i915(dev);
8107         u32 dpll, fp, fp2;
8108         int factor;
8109
8110         /* Enable autotuning of the PLL clock (if permissible) */
8111         factor = 21;
8112         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8113                 if ((intel_panel_use_ssc(dev_priv) &&
8114                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8115                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8116                         factor = 25;
8117         } else if (crtc_state->sdvo_tv_clock)
8118                 factor = 20;
8119
8120         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8121
8122         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8123                 fp |= FP_CB_TUNE;
8124
8125         if (reduced_clock) {
8126                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8127
8128                 if (reduced_clock->m < factor * reduced_clock->n)
8129                         fp2 |= FP_CB_TUNE;
8130         } else {
8131                 fp2 = fp;
8132         }
8133
8134         dpll = 0;
8135
8136         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8137                 dpll |= DPLLB_MODE_LVDS;
8138         else
8139                 dpll |= DPLLB_MODE_DAC_SERIAL;
8140
8141         dpll |= (crtc_state->pixel_multiplier - 1)
8142                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8143
8144         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8145             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8146                 dpll |= DPLL_SDVO_HIGH_SPEED;
8147
8148         if (intel_crtc_has_dp_encoder(crtc_state))
8149                 dpll |= DPLL_SDVO_HIGH_SPEED;
8150
8151         /*
8152          * The high speed IO clock is only really required for
8153          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8154          * possible to share the DPLL between CRT and HDMI. Enabling
8155          * the clock needlessly does no real harm, except use up a
8156          * bit of power potentially.
8157          *
8158          * We'll limit this to IVB with 3 pipes, since it has only two
8159          * DPLLs and so DPLL sharing is the only way to get three pipes
8160          * driving PCH ports at the same time. On SNB we could do this,
8161          * and potentially avoid enabling the second DPLL, but it's not
8162          * clear if it''s a win or loss power wise. No point in doing
8163          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8164          */
8165         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8166             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8167                 dpll |= DPLL_SDVO_HIGH_SPEED;
8168
8169         /* compute bitmask from p1 value */
8170         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8171         /* also FPA1 */
8172         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8173
8174         switch (crtc_state->dpll.p2) {
8175         case 5:
8176                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8177                 break;
8178         case 7:
8179                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8180                 break;
8181         case 10:
8182                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8183                 break;
8184         case 14:
8185                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8186                 break;
8187         }
8188
8189         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8190             intel_panel_use_ssc(dev_priv))
8191                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8192         else
8193                 dpll |= PLL_REF_INPUT_DREFCLK;
8194
8195         dpll |= DPLL_VCO_ENABLE;
8196
8197         crtc_state->dpll_hw_state.dpll = dpll;
8198         crtc_state->dpll_hw_state.fp0 = fp;
8199         crtc_state->dpll_hw_state.fp1 = fp2;
8200 }
8201
8202 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8203                                        struct intel_crtc_state *crtc_state)
8204 {
8205         struct drm_device *dev = crtc->base.dev;
8206         struct drm_i915_private *dev_priv = to_i915(dev);
8207         struct dpll reduced_clock;
8208         bool has_reduced_clock = false;
8209         struct intel_shared_dpll *pll;
8210         const struct intel_limit *limit;
8211         int refclk = 120000;
8212
8213         memset(&crtc_state->dpll_hw_state, 0,
8214                sizeof(crtc_state->dpll_hw_state));
8215
8216         crtc->lowfreq_avail = false;
8217
8218         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8219         if (!crtc_state->has_pch_encoder)
8220                 return 0;
8221
8222         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8223                 if (intel_panel_use_ssc(dev_priv)) {
8224                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8225                                       dev_priv->vbt.lvds_ssc_freq);
8226                         refclk = dev_priv->vbt.lvds_ssc_freq;
8227                 }
8228
8229                 if (intel_is_dual_link_lvds(dev)) {
8230                         if (refclk == 100000)
8231                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8232                         else
8233                                 limit = &intel_limits_ironlake_dual_lvds;
8234                 } else {
8235                         if (refclk == 100000)
8236                                 limit = &intel_limits_ironlake_single_lvds_100m;
8237                         else
8238                                 limit = &intel_limits_ironlake_single_lvds;
8239                 }
8240         } else {
8241                 limit = &intel_limits_ironlake_dac;
8242         }
8243
8244         if (!crtc_state->clock_set &&
8245             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8246                                 refclk, NULL, &crtc_state->dpll)) {
8247                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8248                 return -EINVAL;
8249         }
8250
8251         ironlake_compute_dpll(crtc, crtc_state,
8252                               has_reduced_clock ? &reduced_clock : NULL);
8253
8254         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8255         if (pll == NULL) {
8256                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8257                                  pipe_name(crtc->pipe));
8258                 return -EINVAL;
8259         }
8260
8261         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8262             has_reduced_clock)
8263                 crtc->lowfreq_avail = true;
8264
8265         return 0;
8266 }
8267
8268 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8269                                          struct intel_link_m_n *m_n)
8270 {
8271         struct drm_device *dev = crtc->base.dev;
8272         struct drm_i915_private *dev_priv = to_i915(dev);
8273         enum pipe pipe = crtc->pipe;
8274
8275         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8276         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8277         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8278                 & ~TU_SIZE_MASK;
8279         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8280         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8281                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8282 }
8283
8284 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8285                                          enum transcoder transcoder,
8286                                          struct intel_link_m_n *m_n,
8287                                          struct intel_link_m_n *m2_n2)
8288 {
8289         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8290         enum pipe pipe = crtc->pipe;
8291
8292         if (INTEL_GEN(dev_priv) >= 5) {
8293                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8294                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8295                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8296                         & ~TU_SIZE_MASK;
8297                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8298                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8299                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8300                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8301                  * gen < 8) and if DRRS is supported (to make sure the
8302                  * registers are not unnecessarily read).
8303                  */
8304                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8305                         crtc->config->has_drrs) {
8306                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8307                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8308                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8309                                         & ~TU_SIZE_MASK;
8310                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8311                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8312                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8313                 }
8314         } else {
8315                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8316                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8317                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8318                         & ~TU_SIZE_MASK;
8319                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8320                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8321                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8322         }
8323 }
8324
8325 void intel_dp_get_m_n(struct intel_crtc *crtc,
8326                       struct intel_crtc_state *pipe_config)
8327 {
8328         if (pipe_config->has_pch_encoder)
8329                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8330         else
8331                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8332                                              &pipe_config->dp_m_n,
8333                                              &pipe_config->dp_m2_n2);
8334 }
8335
8336 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8337                                         struct intel_crtc_state *pipe_config)
8338 {
8339         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8340                                      &pipe_config->fdi_m_n, NULL);
8341 }
8342
8343 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8344                                     struct intel_crtc_state *pipe_config)
8345 {
8346         struct drm_device *dev = crtc->base.dev;
8347         struct drm_i915_private *dev_priv = to_i915(dev);
8348         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8349         uint32_t ps_ctrl = 0;
8350         int id = -1;
8351         int i;
8352
8353         /* find scaler attached to this pipe */
8354         for (i = 0; i < crtc->num_scalers; i++) {
8355                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8356                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8357                         id = i;
8358                         pipe_config->pch_pfit.enabled = true;
8359                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8360                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8361                         break;
8362                 }
8363         }
8364
8365         scaler_state->scaler_id = id;
8366         if (id >= 0) {
8367                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8368         } else {
8369                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8370         }
8371 }
8372
8373 static void
8374 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8375                                  struct intel_initial_plane_config *plane_config)
8376 {
8377         struct drm_device *dev = crtc->base.dev;
8378         struct drm_i915_private *dev_priv = to_i915(dev);
8379         u32 val, base, offset, stride_mult, tiling;
8380         int pipe = crtc->pipe;
8381         int fourcc, pixel_format;
8382         unsigned int aligned_height;
8383         struct drm_framebuffer *fb;
8384         struct intel_framebuffer *intel_fb;
8385
8386         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8387         if (!intel_fb) {
8388                 DRM_DEBUG_KMS("failed to alloc fb\n");
8389                 return;
8390         }
8391
8392         fb = &intel_fb->base;
8393
8394         fb->dev = dev;
8395
8396         val = I915_READ(PLANE_CTL(pipe, 0));
8397         if (!(val & PLANE_CTL_ENABLE))
8398                 goto error;
8399
8400         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8401         fourcc = skl_format_to_fourcc(pixel_format,
8402                                       val & PLANE_CTL_ORDER_RGBX,
8403                                       val & PLANE_CTL_ALPHA_MASK);
8404         fb->format = drm_format_info(fourcc);
8405
8406         tiling = val & PLANE_CTL_TILED_MASK;
8407         switch (tiling) {
8408         case PLANE_CTL_TILED_LINEAR:
8409                 fb->modifier = DRM_FORMAT_MOD_NONE;
8410                 break;
8411         case PLANE_CTL_TILED_X:
8412                 plane_config->tiling = I915_TILING_X;
8413                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8414                 break;
8415         case PLANE_CTL_TILED_Y:
8416                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8417                 break;
8418         case PLANE_CTL_TILED_YF:
8419                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8420                 break;
8421         default:
8422                 MISSING_CASE(tiling);
8423                 goto error;
8424         }
8425
8426         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8427         plane_config->base = base;
8428
8429         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8430
8431         val = I915_READ(PLANE_SIZE(pipe, 0));
8432         fb->height = ((val >> 16) & 0xfff) + 1;
8433         fb->width = ((val >> 0) & 0x1fff) + 1;
8434
8435         val = I915_READ(PLANE_STRIDE(pipe, 0));
8436         stride_mult = intel_fb_stride_alignment(fb, 0);
8437         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8438
8439         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8440
8441         plane_config->size = fb->pitches[0] * aligned_height;
8442
8443         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8444                       pipe_name(pipe), fb->width, fb->height,
8445                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8446                       plane_config->size);
8447
8448         plane_config->fb = intel_fb;
8449         return;
8450
8451 error:
8452         kfree(intel_fb);
8453 }
8454
8455 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8456                                      struct intel_crtc_state *pipe_config)
8457 {
8458         struct drm_device *dev = crtc->base.dev;
8459         struct drm_i915_private *dev_priv = to_i915(dev);
8460         uint32_t tmp;
8461
8462         tmp = I915_READ(PF_CTL(crtc->pipe));
8463
8464         if (tmp & PF_ENABLE) {
8465                 pipe_config->pch_pfit.enabled = true;
8466                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8467                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8468
8469                 /* We currently do not free assignements of panel fitters on
8470                  * ivb/hsw (since we don't use the higher upscaling modes which
8471                  * differentiates them) so just WARN about this case for now. */
8472                 if (IS_GEN7(dev_priv)) {
8473                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8474                                 PF_PIPE_SEL_IVB(crtc->pipe));
8475                 }
8476         }
8477 }
8478
8479 static void
8480 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8481                                   struct intel_initial_plane_config *plane_config)
8482 {
8483         struct drm_device *dev = crtc->base.dev;
8484         struct drm_i915_private *dev_priv = to_i915(dev);
8485         u32 val, base, offset;
8486         int pipe = crtc->pipe;
8487         int fourcc, pixel_format;
8488         unsigned int aligned_height;
8489         struct drm_framebuffer *fb;
8490         struct intel_framebuffer *intel_fb;
8491
8492         val = I915_READ(DSPCNTR(pipe));
8493         if (!(val & DISPLAY_PLANE_ENABLE))
8494                 return;
8495
8496         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8497         if (!intel_fb) {
8498                 DRM_DEBUG_KMS("failed to alloc fb\n");
8499                 return;
8500         }
8501
8502         fb = &intel_fb->base;
8503
8504         fb->dev = dev;
8505
8506         if (INTEL_GEN(dev_priv) >= 4) {
8507                 if (val & DISPPLANE_TILED) {
8508                         plane_config->tiling = I915_TILING_X;
8509                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8510                 }
8511         }
8512
8513         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8514         fourcc = i9xx_format_to_fourcc(pixel_format);
8515         fb->format = drm_format_info(fourcc);
8516
8517         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8518         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8519                 offset = I915_READ(DSPOFFSET(pipe));
8520         } else {
8521                 if (plane_config->tiling)
8522                         offset = I915_READ(DSPTILEOFF(pipe));
8523                 else
8524                         offset = I915_READ(DSPLINOFF(pipe));
8525         }
8526         plane_config->base = base;
8527
8528         val = I915_READ(PIPESRC(pipe));
8529         fb->width = ((val >> 16) & 0xfff) + 1;
8530         fb->height = ((val >> 0) & 0xfff) + 1;
8531
8532         val = I915_READ(DSPSTRIDE(pipe));
8533         fb->pitches[0] = val & 0xffffffc0;
8534
8535         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8536
8537         plane_config->size = fb->pitches[0] * aligned_height;
8538
8539         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8540                       pipe_name(pipe), fb->width, fb->height,
8541                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8542                       plane_config->size);
8543
8544         plane_config->fb = intel_fb;
8545 }
8546
8547 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8548                                      struct intel_crtc_state *pipe_config)
8549 {
8550         struct drm_device *dev = crtc->base.dev;
8551         struct drm_i915_private *dev_priv = to_i915(dev);
8552         enum intel_display_power_domain power_domain;
8553         uint32_t tmp;
8554         bool ret;
8555
8556         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8557         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8558                 return false;
8559
8560         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8561         pipe_config->shared_dpll = NULL;
8562
8563         ret = false;
8564         tmp = I915_READ(PIPECONF(crtc->pipe));
8565         if (!(tmp & PIPECONF_ENABLE))
8566                 goto out;
8567
8568         switch (tmp & PIPECONF_BPC_MASK) {
8569         case PIPECONF_6BPC:
8570                 pipe_config->pipe_bpp = 18;
8571                 break;
8572         case PIPECONF_8BPC:
8573                 pipe_config->pipe_bpp = 24;
8574                 break;
8575         case PIPECONF_10BPC:
8576                 pipe_config->pipe_bpp = 30;
8577                 break;
8578         case PIPECONF_12BPC:
8579                 pipe_config->pipe_bpp = 36;
8580                 break;
8581         default:
8582                 break;
8583         }
8584
8585         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8586                 pipe_config->limited_color_range = true;
8587
8588         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8589                 struct intel_shared_dpll *pll;
8590                 enum intel_dpll_id pll_id;
8591
8592                 pipe_config->has_pch_encoder = true;
8593
8594                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8595                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8596                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8597
8598                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8599
8600                 if (HAS_PCH_IBX(dev_priv)) {
8601                         /*
8602                          * The pipe->pch transcoder and pch transcoder->pll
8603                          * mapping is fixed.
8604                          */
8605                         pll_id = (enum intel_dpll_id) crtc->pipe;
8606                 } else {
8607                         tmp = I915_READ(PCH_DPLL_SEL);
8608                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8609                                 pll_id = DPLL_ID_PCH_PLL_B;
8610                         else
8611                                 pll_id= DPLL_ID_PCH_PLL_A;
8612                 }
8613
8614                 pipe_config->shared_dpll =
8615                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8616                 pll = pipe_config->shared_dpll;
8617
8618                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8619                                                  &pipe_config->dpll_hw_state));
8620
8621                 tmp = pipe_config->dpll_hw_state.dpll;
8622                 pipe_config->pixel_multiplier =
8623                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8624                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8625
8626                 ironlake_pch_clock_get(crtc, pipe_config);
8627         } else {
8628                 pipe_config->pixel_multiplier = 1;
8629         }
8630
8631         intel_get_pipe_timings(crtc, pipe_config);
8632         intel_get_pipe_src_size(crtc, pipe_config);
8633
8634         ironlake_get_pfit_config(crtc, pipe_config);
8635
8636         ret = true;
8637
8638 out:
8639         intel_display_power_put(dev_priv, power_domain);
8640
8641         return ret;
8642 }
8643
8644 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8645 {
8646         struct drm_device *dev = &dev_priv->drm;
8647         struct intel_crtc *crtc;
8648
8649         for_each_intel_crtc(dev, crtc)
8650                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8651                      pipe_name(crtc->pipe));
8652
8653         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8654         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8655         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8656         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8657         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8658         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8659              "CPU PWM1 enabled\n");
8660         if (IS_HASWELL(dev_priv))
8661                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8662                      "CPU PWM2 enabled\n");
8663         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8664              "PCH PWM1 enabled\n");
8665         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8666              "Utility pin enabled\n");
8667         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8668
8669         /*
8670          * In theory we can still leave IRQs enabled, as long as only the HPD
8671          * interrupts remain enabled. We used to check for that, but since it's
8672          * gen-specific and since we only disable LCPLL after we fully disable
8673          * the interrupts, the check below should be enough.
8674          */
8675         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8676 }
8677
8678 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8679 {
8680         if (IS_HASWELL(dev_priv))
8681                 return I915_READ(D_COMP_HSW);
8682         else
8683                 return I915_READ(D_COMP_BDW);
8684 }
8685
8686 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8687 {
8688         if (IS_HASWELL(dev_priv)) {
8689                 mutex_lock(&dev_priv->rps.hw_lock);
8690                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8691                                             val))
8692                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8693                 mutex_unlock(&dev_priv->rps.hw_lock);
8694         } else {
8695                 I915_WRITE(D_COMP_BDW, val);
8696                 POSTING_READ(D_COMP_BDW);
8697         }
8698 }
8699
8700 /*
8701  * This function implements pieces of two sequences from BSpec:
8702  * - Sequence for display software to disable LCPLL
8703  * - Sequence for display software to allow package C8+
8704  * The steps implemented here are just the steps that actually touch the LCPLL
8705  * register. Callers should take care of disabling all the display engine
8706  * functions, doing the mode unset, fixing interrupts, etc.
8707  */
8708 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8709                               bool switch_to_fclk, bool allow_power_down)
8710 {
8711         uint32_t val;
8712
8713         assert_can_disable_lcpll(dev_priv);
8714
8715         val = I915_READ(LCPLL_CTL);
8716
8717         if (switch_to_fclk) {
8718                 val |= LCPLL_CD_SOURCE_FCLK;
8719                 I915_WRITE(LCPLL_CTL, val);
8720
8721                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8722                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8723                         DRM_ERROR("Switching to FCLK failed\n");
8724
8725                 val = I915_READ(LCPLL_CTL);
8726         }
8727
8728         val |= LCPLL_PLL_DISABLE;
8729         I915_WRITE(LCPLL_CTL, val);
8730         POSTING_READ(LCPLL_CTL);
8731
8732         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8733                 DRM_ERROR("LCPLL still locked\n");
8734
8735         val = hsw_read_dcomp(dev_priv);
8736         val |= D_COMP_COMP_DISABLE;
8737         hsw_write_dcomp(dev_priv, val);
8738         ndelay(100);
8739
8740         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8741                      1))
8742                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8743
8744         if (allow_power_down) {
8745                 val = I915_READ(LCPLL_CTL);
8746                 val |= LCPLL_POWER_DOWN_ALLOW;
8747                 I915_WRITE(LCPLL_CTL, val);
8748                 POSTING_READ(LCPLL_CTL);
8749         }
8750 }
8751
8752 /*
8753  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8754  * source.
8755  */
8756 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8757 {
8758         uint32_t val;
8759
8760         val = I915_READ(LCPLL_CTL);
8761
8762         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8763                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8764                 return;
8765
8766         /*
8767          * Make sure we're not on PC8 state before disabling PC8, otherwise
8768          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8769          */
8770         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8771
8772         if (val & LCPLL_POWER_DOWN_ALLOW) {
8773                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8774                 I915_WRITE(LCPLL_CTL, val);
8775                 POSTING_READ(LCPLL_CTL);
8776         }
8777
8778         val = hsw_read_dcomp(dev_priv);
8779         val |= D_COMP_COMP_FORCE;
8780         val &= ~D_COMP_COMP_DISABLE;
8781         hsw_write_dcomp(dev_priv, val);
8782
8783         val = I915_READ(LCPLL_CTL);
8784         val &= ~LCPLL_PLL_DISABLE;
8785         I915_WRITE(LCPLL_CTL, val);
8786
8787         if (intel_wait_for_register(dev_priv,
8788                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8789                                     5))
8790                 DRM_ERROR("LCPLL not locked yet\n");
8791
8792         if (val & LCPLL_CD_SOURCE_FCLK) {
8793                 val = I915_READ(LCPLL_CTL);
8794                 val &= ~LCPLL_CD_SOURCE_FCLK;
8795                 I915_WRITE(LCPLL_CTL, val);
8796
8797                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8798                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8799                         DRM_ERROR("Switching back to LCPLL failed\n");
8800         }
8801
8802         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8803         intel_update_cdclk(dev_priv);
8804 }
8805
8806 /*
8807  * Package states C8 and deeper are really deep PC states that can only be
8808  * reached when all the devices on the system allow it, so even if the graphics
8809  * device allows PC8+, it doesn't mean the system will actually get to these
8810  * states. Our driver only allows PC8+ when going into runtime PM.
8811  *
8812  * The requirements for PC8+ are that all the outputs are disabled, the power
8813  * well is disabled and most interrupts are disabled, and these are also
8814  * requirements for runtime PM. When these conditions are met, we manually do
8815  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8816  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8817  * hang the machine.
8818  *
8819  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8820  * the state of some registers, so when we come back from PC8+ we need to
8821  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8822  * need to take care of the registers kept by RC6. Notice that this happens even
8823  * if we don't put the device in PCI D3 state (which is what currently happens
8824  * because of the runtime PM support).
8825  *
8826  * For more, read "Display Sequences for Package C8" on the hardware
8827  * documentation.
8828  */
8829 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8830 {
8831         uint32_t val;
8832
8833         DRM_DEBUG_KMS("Enabling package C8+\n");
8834
8835         if (HAS_PCH_LPT_LP(dev_priv)) {
8836                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8837                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8838                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8839         }
8840
8841         lpt_disable_clkout_dp(dev_priv);
8842         hsw_disable_lcpll(dev_priv, true, true);
8843 }
8844
8845 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8846 {
8847         uint32_t val;
8848
8849         DRM_DEBUG_KMS("Disabling package C8+\n");
8850
8851         hsw_restore_lcpll(dev_priv);
8852         lpt_init_pch_refclk(dev_priv);
8853
8854         if (HAS_PCH_LPT_LP(dev_priv)) {
8855                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8856                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8857                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8858         }
8859 }
8860
8861 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8862                                       struct intel_crtc_state *crtc_state)
8863 {
8864         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8865                 if (!intel_ddi_pll_select(crtc, crtc_state))
8866                         return -EINVAL;
8867         }
8868
8869         crtc->lowfreq_avail = false;
8870
8871         return 0;
8872 }
8873
8874 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8875                                 enum port port,
8876                                 struct intel_crtc_state *pipe_config)
8877 {
8878         enum intel_dpll_id id;
8879
8880         switch (port) {
8881         case PORT_A:
8882                 id = DPLL_ID_SKL_DPLL0;
8883                 break;
8884         case PORT_B:
8885                 id = DPLL_ID_SKL_DPLL1;
8886                 break;
8887         case PORT_C:
8888                 id = DPLL_ID_SKL_DPLL2;
8889                 break;
8890         default:
8891                 DRM_ERROR("Incorrect port type\n");
8892                 return;
8893         }
8894
8895         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8896 }
8897
8898 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8899                                 enum port port,
8900                                 struct intel_crtc_state *pipe_config)
8901 {
8902         enum intel_dpll_id id;
8903         u32 temp;
8904
8905         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8906         id = temp >> (port * 3 + 1);
8907
8908         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8909                 return;
8910
8911         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8912 }
8913
8914 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8915                                 enum port port,
8916                                 struct intel_crtc_state *pipe_config)
8917 {
8918         enum intel_dpll_id id;
8919         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8920
8921         switch (ddi_pll_sel) {
8922         case PORT_CLK_SEL_WRPLL1:
8923                 id = DPLL_ID_WRPLL1;
8924                 break;
8925         case PORT_CLK_SEL_WRPLL2:
8926                 id = DPLL_ID_WRPLL2;
8927                 break;
8928         case PORT_CLK_SEL_SPLL:
8929                 id = DPLL_ID_SPLL;
8930                 break;
8931         case PORT_CLK_SEL_LCPLL_810:
8932                 id = DPLL_ID_LCPLL_810;
8933                 break;
8934         case PORT_CLK_SEL_LCPLL_1350:
8935                 id = DPLL_ID_LCPLL_1350;
8936                 break;
8937         case PORT_CLK_SEL_LCPLL_2700:
8938                 id = DPLL_ID_LCPLL_2700;
8939                 break;
8940         default:
8941                 MISSING_CASE(ddi_pll_sel);
8942                 /* fall through */
8943         case PORT_CLK_SEL_NONE:
8944                 return;
8945         }
8946
8947         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8948 }
8949
8950 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8951                                      struct intel_crtc_state *pipe_config,
8952                                      u64 *power_domain_mask)
8953 {
8954         struct drm_device *dev = crtc->base.dev;
8955         struct drm_i915_private *dev_priv = to_i915(dev);
8956         enum intel_display_power_domain power_domain;
8957         u32 tmp;
8958
8959         /*
8960          * The pipe->transcoder mapping is fixed with the exception of the eDP
8961          * transcoder handled below.
8962          */
8963         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8964
8965         /*
8966          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8967          * consistency and less surprising code; it's in always on power).
8968          */
8969         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8970         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8971                 enum pipe trans_edp_pipe;
8972                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8973                 default:
8974                         WARN(1, "unknown pipe linked to edp transcoder\n");
8975                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8976                 case TRANS_DDI_EDP_INPUT_A_ON:
8977                         trans_edp_pipe = PIPE_A;
8978                         break;
8979                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8980                         trans_edp_pipe = PIPE_B;
8981                         break;
8982                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8983                         trans_edp_pipe = PIPE_C;
8984                         break;
8985                 }
8986
8987                 if (trans_edp_pipe == crtc->pipe)
8988                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8989         }
8990
8991         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8992         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8993                 return false;
8994         *power_domain_mask |= BIT_ULL(power_domain);
8995
8996         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8997
8998         return tmp & PIPECONF_ENABLE;
8999 }
9000
9001 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9002                                          struct intel_crtc_state *pipe_config,
9003                                          u64 *power_domain_mask)
9004 {
9005         struct drm_device *dev = crtc->base.dev;
9006         struct drm_i915_private *dev_priv = to_i915(dev);
9007         enum intel_display_power_domain power_domain;
9008         enum port port;
9009         enum transcoder cpu_transcoder;
9010         u32 tmp;
9011
9012         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9013                 if (port == PORT_A)
9014                         cpu_transcoder = TRANSCODER_DSI_A;
9015                 else
9016                         cpu_transcoder = TRANSCODER_DSI_C;
9017
9018                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9019                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9020                         continue;
9021                 *power_domain_mask |= BIT_ULL(power_domain);
9022
9023                 /*
9024                  * The PLL needs to be enabled with a valid divider
9025                  * configuration, otherwise accessing DSI registers will hang
9026                  * the machine. See BSpec North Display Engine
9027                  * registers/MIPI[BXT]. We can break out here early, since we
9028                  * need the same DSI PLL to be enabled for both DSI ports.
9029                  */
9030                 if (!intel_dsi_pll_is_enabled(dev_priv))
9031                         break;
9032
9033                 /* XXX: this works for video mode only */
9034                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9035                 if (!(tmp & DPI_ENABLE))
9036                         continue;
9037
9038                 tmp = I915_READ(MIPI_CTRL(port));
9039                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9040                         continue;
9041
9042                 pipe_config->cpu_transcoder = cpu_transcoder;
9043                 break;
9044         }
9045
9046         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9047 }
9048
9049 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9050                                        struct intel_crtc_state *pipe_config)
9051 {
9052         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9053         struct intel_shared_dpll *pll;
9054         enum port port;
9055         uint32_t tmp;
9056
9057         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9058
9059         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9060
9061         if (IS_GEN9_BC(dev_priv))
9062                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9063         else if (IS_GEN9_LP(dev_priv))
9064                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9065         else
9066                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9067
9068         pll = pipe_config->shared_dpll;
9069         if (pll) {
9070                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9071                                                  &pipe_config->dpll_hw_state));
9072         }
9073
9074         /*
9075          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9076          * DDI E. So just check whether this pipe is wired to DDI E and whether
9077          * the PCH transcoder is on.
9078          */
9079         if (INTEL_GEN(dev_priv) < 9 &&
9080             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9081                 pipe_config->has_pch_encoder = true;
9082
9083                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9084                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9085                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9086
9087                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9088         }
9089 }
9090
9091 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9092                                     struct intel_crtc_state *pipe_config)
9093 {
9094         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9095         enum intel_display_power_domain power_domain;
9096         u64 power_domain_mask;
9097         bool active;
9098
9099         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9100         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9101                 return false;
9102         power_domain_mask = BIT_ULL(power_domain);
9103
9104         pipe_config->shared_dpll = NULL;
9105
9106         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9107
9108         if (IS_GEN9_LP(dev_priv) &&
9109             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9110                 WARN_ON(active);
9111                 active = true;
9112         }
9113
9114         if (!active)
9115                 goto out;
9116
9117         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9118                 haswell_get_ddi_port_state(crtc, pipe_config);
9119                 intel_get_pipe_timings(crtc, pipe_config);
9120         }
9121
9122         intel_get_pipe_src_size(crtc, pipe_config);
9123
9124         pipe_config->gamma_mode =
9125                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9126
9127         if (INTEL_GEN(dev_priv) >= 9) {
9128                 intel_crtc_init_scalers(crtc, pipe_config);
9129
9130                 pipe_config->scaler_state.scaler_id = -1;
9131                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9132         }
9133
9134         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9135         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9136                 power_domain_mask |= BIT_ULL(power_domain);
9137                 if (INTEL_GEN(dev_priv) >= 9)
9138                         skylake_get_pfit_config(crtc, pipe_config);
9139                 else
9140                         ironlake_get_pfit_config(crtc, pipe_config);
9141         }
9142
9143         if (IS_HASWELL(dev_priv))
9144                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9145                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9146
9147         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9148             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9149                 pipe_config->pixel_multiplier =
9150                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9151         } else {
9152                 pipe_config->pixel_multiplier = 1;
9153         }
9154
9155 out:
9156         for_each_power_domain(power_domain, power_domain_mask)
9157                 intel_display_power_put(dev_priv, power_domain);
9158
9159         return active;
9160 }
9161
9162 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9163                                const struct intel_plane_state *plane_state)
9164 {
9165         struct drm_device *dev = crtc->dev;
9166         struct drm_i915_private *dev_priv = to_i915(dev);
9167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9168         uint32_t cntl = 0, size = 0;
9169
9170         if (plane_state && plane_state->base.visible) {
9171                 unsigned int width = plane_state->base.crtc_w;
9172                 unsigned int height = plane_state->base.crtc_h;
9173                 unsigned int stride = roundup_pow_of_two(width) * 4;
9174
9175                 switch (stride) {
9176                 default:
9177                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9178                                   width, stride);
9179                         stride = 256;
9180                         /* fallthrough */
9181                 case 256:
9182                 case 512:
9183                 case 1024:
9184                 case 2048:
9185                         break;
9186                 }
9187
9188                 cntl |= CURSOR_ENABLE |
9189                         CURSOR_GAMMA_ENABLE |
9190                         CURSOR_FORMAT_ARGB |
9191                         CURSOR_STRIDE(stride);
9192
9193                 size = (height << 12) | width;
9194         }
9195
9196         if (intel_crtc->cursor_cntl != 0 &&
9197             (intel_crtc->cursor_base != base ||
9198              intel_crtc->cursor_size != size ||
9199              intel_crtc->cursor_cntl != cntl)) {
9200                 /* On these chipsets we can only modify the base/size/stride
9201                  * whilst the cursor is disabled.
9202                  */
9203                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9204                 POSTING_READ_FW(CURCNTR(PIPE_A));
9205                 intel_crtc->cursor_cntl = 0;
9206         }
9207
9208         if (intel_crtc->cursor_base != base) {
9209                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9210                 intel_crtc->cursor_base = base;
9211         }
9212
9213         if (intel_crtc->cursor_size != size) {
9214                 I915_WRITE_FW(CURSIZE, size);
9215                 intel_crtc->cursor_size = size;
9216         }
9217
9218         if (intel_crtc->cursor_cntl != cntl) {
9219                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9220                 POSTING_READ_FW(CURCNTR(PIPE_A));
9221                 intel_crtc->cursor_cntl = cntl;
9222         }
9223 }
9224
9225 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9226                                const struct intel_plane_state *plane_state)
9227 {
9228         struct drm_device *dev = crtc->dev;
9229         struct drm_i915_private *dev_priv = to_i915(dev);
9230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9231         int pipe = intel_crtc->pipe;
9232         uint32_t cntl = 0;
9233
9234         if (plane_state && plane_state->base.visible) {
9235                 cntl = MCURSOR_GAMMA_ENABLE;
9236                 switch (plane_state->base.crtc_w) {
9237                         case 64:
9238                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9239                                 break;
9240                         case 128:
9241                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9242                                 break;
9243                         case 256:
9244                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9245                                 break;
9246                         default:
9247                                 MISSING_CASE(plane_state->base.crtc_w);
9248                                 return;
9249                 }
9250                 cntl |= pipe << 28; /* Connect to correct pipe */
9251
9252                 if (HAS_DDI(dev_priv))
9253                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9254
9255                 if (plane_state->base.rotation & DRM_ROTATE_180)
9256                         cntl |= CURSOR_ROTATE_180;
9257         }
9258
9259         if (intel_crtc->cursor_cntl != cntl) {
9260                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9261                 POSTING_READ_FW(CURCNTR(pipe));
9262                 intel_crtc->cursor_cntl = cntl;
9263         }
9264
9265         /* and commit changes on next vblank */
9266         I915_WRITE_FW(CURBASE(pipe), base);
9267         POSTING_READ_FW(CURBASE(pipe));
9268
9269         intel_crtc->cursor_base = base;
9270 }
9271
9272 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9273 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9274                                      const struct intel_plane_state *plane_state)
9275 {
9276         struct drm_device *dev = crtc->dev;
9277         struct drm_i915_private *dev_priv = to_i915(dev);
9278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9279         int pipe = intel_crtc->pipe;
9280         u32 base = intel_crtc->cursor_addr;
9281         unsigned long irqflags;
9282         u32 pos = 0;
9283
9284         if (plane_state) {
9285                 int x = plane_state->base.crtc_x;
9286                 int y = plane_state->base.crtc_y;
9287
9288                 if (x < 0) {
9289                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9290                         x = -x;
9291                 }
9292                 pos |= x << CURSOR_X_SHIFT;
9293
9294                 if (y < 0) {
9295                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9296                         y = -y;
9297                 }
9298                 pos |= y << CURSOR_Y_SHIFT;
9299
9300                 /* ILK+ do this automagically */
9301                 if (HAS_GMCH_DISPLAY(dev_priv) &&
9302                     plane_state->base.rotation & DRM_ROTATE_180) {
9303                         base += (plane_state->base.crtc_h *
9304                                  plane_state->base.crtc_w - 1) * 4;
9305                 }
9306         }
9307
9308         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9309
9310         I915_WRITE_FW(CURPOS(pipe), pos);
9311
9312         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9313                 i845_update_cursor(crtc, base, plane_state);
9314         else
9315                 i9xx_update_cursor(crtc, base, plane_state);
9316
9317         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9318 }
9319
9320 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9321                            uint32_t width, uint32_t height)
9322 {
9323         if (width == 0 || height == 0)
9324                 return false;
9325
9326         /*
9327          * 845g/865g are special in that they are only limited by
9328          * the width of their cursors, the height is arbitrary up to
9329          * the precision of the register. Everything else requires
9330          * square cursors, limited to a few power-of-two sizes.
9331          */
9332         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9333                 if ((width & 63) != 0)
9334                         return false;
9335
9336                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9337                         return false;
9338
9339                 if (height > 1023)
9340                         return false;
9341         } else {
9342                 switch (width | height) {
9343                 case 256:
9344                 case 128:
9345                         if (IS_GEN2(dev_priv))
9346                                 return false;
9347                 case 64:
9348                         break;
9349                 default:
9350                         return false;
9351                 }
9352         }
9353
9354         return true;
9355 }
9356
9357 /* VESA 640x480x72Hz mode to set on the pipe */
9358 static struct drm_display_mode load_detect_mode = {
9359         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9360                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9361 };
9362
9363 struct drm_framebuffer *
9364 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9365                          struct drm_mode_fb_cmd2 *mode_cmd)
9366 {
9367         struct intel_framebuffer *intel_fb;
9368         int ret;
9369
9370         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9371         if (!intel_fb)
9372                 return ERR_PTR(-ENOMEM);
9373
9374         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9375         if (ret)
9376                 goto err;
9377
9378         return &intel_fb->base;
9379
9380 err:
9381         kfree(intel_fb);
9382         return ERR_PTR(ret);
9383 }
9384
9385 static u32
9386 intel_framebuffer_pitch_for_width(int width, int bpp)
9387 {
9388         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9389         return ALIGN(pitch, 64);
9390 }
9391
9392 static u32
9393 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9394 {
9395         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9396         return PAGE_ALIGN(pitch * mode->vdisplay);
9397 }
9398
9399 static struct drm_framebuffer *
9400 intel_framebuffer_create_for_mode(struct drm_device *dev,
9401                                   struct drm_display_mode *mode,
9402                                   int depth, int bpp)
9403 {
9404         struct drm_framebuffer *fb;
9405         struct drm_i915_gem_object *obj;
9406         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9407
9408         obj = i915_gem_object_create(to_i915(dev),
9409                                     intel_framebuffer_size_for_mode(mode, bpp));
9410         if (IS_ERR(obj))
9411                 return ERR_CAST(obj);
9412
9413         mode_cmd.width = mode->hdisplay;
9414         mode_cmd.height = mode->vdisplay;
9415         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9416                                                                 bpp);
9417         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9418
9419         fb = intel_framebuffer_create(obj, &mode_cmd);
9420         if (IS_ERR(fb))
9421                 i915_gem_object_put(obj);
9422
9423         return fb;
9424 }
9425
9426 static struct drm_framebuffer *
9427 mode_fits_in_fbdev(struct drm_device *dev,
9428                    struct drm_display_mode *mode)
9429 {
9430 #ifdef CONFIG_DRM_FBDEV_EMULATION
9431         struct drm_i915_private *dev_priv = to_i915(dev);
9432         struct drm_i915_gem_object *obj;
9433         struct drm_framebuffer *fb;
9434
9435         if (!dev_priv->fbdev)
9436                 return NULL;
9437
9438         if (!dev_priv->fbdev->fb)
9439                 return NULL;
9440
9441         obj = dev_priv->fbdev->fb->obj;
9442         BUG_ON(!obj);
9443
9444         fb = &dev_priv->fbdev->fb->base;
9445         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9446                                                                fb->format->cpp[0] * 8))
9447                 return NULL;
9448
9449         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9450                 return NULL;
9451
9452         drm_framebuffer_reference(fb);
9453         return fb;
9454 #else
9455         return NULL;
9456 #endif
9457 }
9458
9459 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9460                                            struct drm_crtc *crtc,
9461                                            struct drm_display_mode *mode,
9462                                            struct drm_framebuffer *fb,
9463                                            int x, int y)
9464 {
9465         struct drm_plane_state *plane_state;
9466         int hdisplay, vdisplay;
9467         int ret;
9468
9469         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9470         if (IS_ERR(plane_state))
9471                 return PTR_ERR(plane_state);
9472
9473         if (mode)
9474                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9475         else
9476                 hdisplay = vdisplay = 0;
9477
9478         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9479         if (ret)
9480                 return ret;
9481         drm_atomic_set_fb_for_plane(plane_state, fb);
9482         plane_state->crtc_x = 0;
9483         plane_state->crtc_y = 0;
9484         plane_state->crtc_w = hdisplay;
9485         plane_state->crtc_h = vdisplay;
9486         plane_state->src_x = x << 16;
9487         plane_state->src_y = y << 16;
9488         plane_state->src_w = hdisplay << 16;
9489         plane_state->src_h = vdisplay << 16;
9490
9491         return 0;
9492 }
9493
9494 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9495                                 struct drm_display_mode *mode,
9496                                 struct intel_load_detect_pipe *old,
9497                                 struct drm_modeset_acquire_ctx *ctx)
9498 {
9499         struct intel_crtc *intel_crtc;
9500         struct intel_encoder *intel_encoder =
9501                 intel_attached_encoder(connector);
9502         struct drm_crtc *possible_crtc;
9503         struct drm_encoder *encoder = &intel_encoder->base;
9504         struct drm_crtc *crtc = NULL;
9505         struct drm_device *dev = encoder->dev;
9506         struct drm_i915_private *dev_priv = to_i915(dev);
9507         struct drm_framebuffer *fb;
9508         struct drm_mode_config *config = &dev->mode_config;
9509         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9510         struct drm_connector_state *connector_state;
9511         struct intel_crtc_state *crtc_state;
9512         int ret, i = -1;
9513
9514         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9515                       connector->base.id, connector->name,
9516                       encoder->base.id, encoder->name);
9517
9518         old->restore_state = NULL;
9519
9520 retry:
9521         ret = drm_modeset_lock(&config->connection_mutex, ctx);
9522         if (ret)
9523                 goto fail;
9524
9525         /*
9526          * Algorithm gets a little messy:
9527          *
9528          *   - if the connector already has an assigned crtc, use it (but make
9529          *     sure it's on first)
9530          *
9531          *   - try to find the first unused crtc that can drive this connector,
9532          *     and use that if we find one
9533          */
9534
9535         /* See if we already have a CRTC for this connector */
9536         if (connector->state->crtc) {
9537                 crtc = connector->state->crtc;
9538
9539                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9540                 if (ret)
9541                         goto fail;
9542
9543                 /* Make sure the crtc and connector are running */
9544                 goto found;
9545         }
9546
9547         /* Find an unused one (if possible) */
9548         for_each_crtc(dev, possible_crtc) {
9549                 i++;
9550                 if (!(encoder->possible_crtcs & (1 << i)))
9551                         continue;
9552
9553                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9554                 if (ret)
9555                         goto fail;
9556
9557                 if (possible_crtc->state->enable) {
9558                         drm_modeset_unlock(&possible_crtc->mutex);
9559                         continue;
9560                 }
9561
9562                 crtc = possible_crtc;
9563                 break;
9564         }
9565
9566         /*
9567          * If we didn't find an unused CRTC, don't use any.
9568          */
9569         if (!crtc) {
9570                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9571                 goto fail;
9572         }
9573
9574 found:
9575         intel_crtc = to_intel_crtc(crtc);
9576
9577         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9578         if (ret)
9579                 goto fail;
9580
9581         state = drm_atomic_state_alloc(dev);
9582         restore_state = drm_atomic_state_alloc(dev);
9583         if (!state || !restore_state) {
9584                 ret = -ENOMEM;
9585                 goto fail;
9586         }
9587
9588         state->acquire_ctx = ctx;
9589         restore_state->acquire_ctx = ctx;
9590
9591         connector_state = drm_atomic_get_connector_state(state, connector);
9592         if (IS_ERR(connector_state)) {
9593                 ret = PTR_ERR(connector_state);
9594                 goto fail;
9595         }
9596
9597         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9598         if (ret)
9599                 goto fail;
9600
9601         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9602         if (IS_ERR(crtc_state)) {
9603                 ret = PTR_ERR(crtc_state);
9604                 goto fail;
9605         }
9606
9607         crtc_state->base.active = crtc_state->base.enable = true;
9608
9609         if (!mode)
9610                 mode = &load_detect_mode;
9611
9612         /* We need a framebuffer large enough to accommodate all accesses
9613          * that the plane may generate whilst we perform load detection.
9614          * We can not rely on the fbcon either being present (we get called
9615          * during its initialisation to detect all boot displays, or it may
9616          * not even exist) or that it is large enough to satisfy the
9617          * requested mode.
9618          */
9619         fb = mode_fits_in_fbdev(dev, mode);
9620         if (fb == NULL) {
9621                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9622                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9623         } else
9624                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9625         if (IS_ERR(fb)) {
9626                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9627                 goto fail;
9628         }
9629
9630         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9631         if (ret)
9632                 goto fail;
9633
9634         drm_framebuffer_unreference(fb);
9635
9636         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9637         if (ret)
9638                 goto fail;
9639
9640         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9641         if (!ret)
9642                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9643         if (!ret)
9644                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9645         if (ret) {
9646                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9647                 goto fail;
9648         }
9649
9650         ret = drm_atomic_commit(state);
9651         if (ret) {
9652                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9653                 goto fail;
9654         }
9655
9656         old->restore_state = restore_state;
9657         drm_atomic_state_put(state);
9658
9659         /* let the connector get through one full cycle before testing */
9660         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9661         return true;
9662
9663 fail:
9664         if (state) {
9665                 drm_atomic_state_put(state);
9666                 state = NULL;
9667         }
9668         if (restore_state) {
9669                 drm_atomic_state_put(restore_state);
9670                 restore_state = NULL;
9671         }
9672
9673         if (ret == -EDEADLK) {
9674                 drm_modeset_backoff(ctx);
9675                 goto retry;
9676         }
9677
9678         return false;
9679 }
9680
9681 void intel_release_load_detect_pipe(struct drm_connector *connector,
9682                                     struct intel_load_detect_pipe *old,
9683                                     struct drm_modeset_acquire_ctx *ctx)
9684 {
9685         struct intel_encoder *intel_encoder =
9686                 intel_attached_encoder(connector);
9687         struct drm_encoder *encoder = &intel_encoder->base;
9688         struct drm_atomic_state *state = old->restore_state;
9689         int ret;
9690
9691         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9692                       connector->base.id, connector->name,
9693                       encoder->base.id, encoder->name);
9694
9695         if (!state)
9696                 return;
9697
9698         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9699         if (ret)
9700                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9701         drm_atomic_state_put(state);
9702 }
9703
9704 static int i9xx_pll_refclk(struct drm_device *dev,
9705                            const struct intel_crtc_state *pipe_config)
9706 {
9707         struct drm_i915_private *dev_priv = to_i915(dev);
9708         u32 dpll = pipe_config->dpll_hw_state.dpll;
9709
9710         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9711                 return dev_priv->vbt.lvds_ssc_freq;
9712         else if (HAS_PCH_SPLIT(dev_priv))
9713                 return 120000;
9714         else if (!IS_GEN2(dev_priv))
9715                 return 96000;
9716         else
9717                 return 48000;
9718 }
9719
9720 /* Returns the clock of the currently programmed mode of the given pipe. */
9721 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9722                                 struct intel_crtc_state *pipe_config)
9723 {
9724         struct drm_device *dev = crtc->base.dev;
9725         struct drm_i915_private *dev_priv = to_i915(dev);
9726         int pipe = pipe_config->cpu_transcoder;
9727         u32 dpll = pipe_config->dpll_hw_state.dpll;
9728         u32 fp;
9729         struct dpll clock;
9730         int port_clock;
9731         int refclk = i9xx_pll_refclk(dev, pipe_config);
9732
9733         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9734                 fp = pipe_config->dpll_hw_state.fp0;
9735         else
9736                 fp = pipe_config->dpll_hw_state.fp1;
9737
9738         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9739         if (IS_PINEVIEW(dev_priv)) {
9740                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9741                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9742         } else {
9743                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9744                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9745         }
9746
9747         if (!IS_GEN2(dev_priv)) {
9748                 if (IS_PINEVIEW(dev_priv))
9749                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9750                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9751                 else
9752                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9753                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9754
9755                 switch (dpll & DPLL_MODE_MASK) {
9756                 case DPLLB_MODE_DAC_SERIAL:
9757                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9758                                 5 : 10;
9759                         break;
9760                 case DPLLB_MODE_LVDS:
9761                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9762                                 7 : 14;
9763                         break;
9764                 default:
9765                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9766                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9767                         return;
9768                 }
9769
9770                 if (IS_PINEVIEW(dev_priv))
9771                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9772                 else
9773                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9774         } else {
9775                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9776                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9777
9778                 if (is_lvds) {
9779                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9780                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9781
9782                         if (lvds & LVDS_CLKB_POWER_UP)
9783                                 clock.p2 = 7;
9784                         else
9785                                 clock.p2 = 14;
9786                 } else {
9787                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9788                                 clock.p1 = 2;
9789                         else {
9790                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9791                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9792                         }
9793                         if (dpll & PLL_P2_DIVIDE_BY_4)
9794                                 clock.p2 = 4;
9795                         else
9796                                 clock.p2 = 2;
9797                 }
9798
9799                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9800         }
9801
9802         /*
9803          * This value includes pixel_multiplier. We will use
9804          * port_clock to compute adjusted_mode.crtc_clock in the
9805          * encoder's get_config() function.
9806          */
9807         pipe_config->port_clock = port_clock;
9808 }
9809
9810 int intel_dotclock_calculate(int link_freq,
9811                              const struct intel_link_m_n *m_n)
9812 {
9813         /*
9814          * The calculation for the data clock is:
9815          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9816          * But we want to avoid losing precison if possible, so:
9817          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9818          *
9819          * and the link clock is simpler:
9820          * link_clock = (m * link_clock) / n
9821          */
9822
9823         if (!m_n->link_n)
9824                 return 0;
9825
9826         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9827 }
9828
9829 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9830                                    struct intel_crtc_state *pipe_config)
9831 {
9832         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9833
9834         /* read out port_clock from the DPLL */
9835         i9xx_crtc_clock_get(crtc, pipe_config);
9836
9837         /*
9838          * In case there is an active pipe without active ports,
9839          * we may need some idea for the dotclock anyway.
9840          * Calculate one based on the FDI configuration.
9841          */
9842         pipe_config->base.adjusted_mode.crtc_clock =
9843                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9844                                          &pipe_config->fdi_m_n);
9845 }
9846
9847 /** Returns the currently programmed mode of the given pipe. */
9848 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9849                                              struct drm_crtc *crtc)
9850 {
9851         struct drm_i915_private *dev_priv = to_i915(dev);
9852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9853         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9854         struct drm_display_mode *mode;
9855         struct intel_crtc_state *pipe_config;
9856         int htot = I915_READ(HTOTAL(cpu_transcoder));
9857         int hsync = I915_READ(HSYNC(cpu_transcoder));
9858         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9859         int vsync = I915_READ(VSYNC(cpu_transcoder));
9860         enum pipe pipe = intel_crtc->pipe;
9861
9862         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9863         if (!mode)
9864                 return NULL;
9865
9866         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9867         if (!pipe_config) {
9868                 kfree(mode);
9869                 return NULL;
9870         }
9871
9872         /*
9873          * Construct a pipe_config sufficient for getting the clock info
9874          * back out of crtc_clock_get.
9875          *
9876          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9877          * to use a real value here instead.
9878          */
9879         pipe_config->cpu_transcoder = (enum transcoder) pipe;
9880         pipe_config->pixel_multiplier = 1;
9881         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9882         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9883         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9884         i9xx_crtc_clock_get(intel_crtc, pipe_config);
9885
9886         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9887         mode->hdisplay = (htot & 0xffff) + 1;
9888         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9889         mode->hsync_start = (hsync & 0xffff) + 1;
9890         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9891         mode->vdisplay = (vtot & 0xffff) + 1;
9892         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9893         mode->vsync_start = (vsync & 0xffff) + 1;
9894         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9895
9896         drm_mode_set_name(mode);
9897
9898         kfree(pipe_config);
9899
9900         return mode;
9901 }
9902
9903 static void intel_crtc_destroy(struct drm_crtc *crtc)
9904 {
9905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9906         struct drm_device *dev = crtc->dev;
9907         struct intel_flip_work *work;
9908
9909         spin_lock_irq(&dev->event_lock);
9910         work = intel_crtc->flip_work;
9911         intel_crtc->flip_work = NULL;
9912         spin_unlock_irq(&dev->event_lock);
9913
9914         if (work) {
9915                 cancel_work_sync(&work->mmio_work);
9916                 cancel_work_sync(&work->unpin_work);
9917                 kfree(work);
9918         }
9919
9920         drm_crtc_cleanup(crtc);
9921
9922         kfree(intel_crtc);
9923 }
9924
9925 static void intel_unpin_work_fn(struct work_struct *__work)
9926 {
9927         struct intel_flip_work *work =
9928                 container_of(__work, struct intel_flip_work, unpin_work);
9929         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9930         struct drm_device *dev = crtc->base.dev;
9931         struct drm_plane *primary = crtc->base.primary;
9932
9933         if (is_mmio_work(work))
9934                 flush_work(&work->mmio_work);
9935
9936         mutex_lock(&dev->struct_mutex);
9937         intel_unpin_fb_vma(work->old_vma);
9938         i915_gem_object_put(work->pending_flip_obj);
9939         mutex_unlock(&dev->struct_mutex);
9940
9941         i915_gem_request_put(work->flip_queued_req);
9942
9943         intel_frontbuffer_flip_complete(to_i915(dev),
9944                                         to_intel_plane(primary)->frontbuffer_bit);
9945         intel_fbc_post_update(crtc);
9946         drm_framebuffer_unreference(work->old_fb);
9947
9948         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9949         atomic_dec(&crtc->unpin_work_count);
9950
9951         kfree(work);
9952 }
9953
9954 /* Is 'a' after or equal to 'b'? */
9955 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9956 {
9957         return !((a - b) & 0x80000000);
9958 }
9959
9960 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9961                                    struct intel_flip_work *work)
9962 {
9963         struct drm_device *dev = crtc->base.dev;
9964         struct drm_i915_private *dev_priv = to_i915(dev);
9965
9966         if (abort_flip_on_reset(crtc))
9967                 return true;
9968
9969         /*
9970          * The relevant registers doen't exist on pre-ctg.
9971          * As the flip done interrupt doesn't trigger for mmio
9972          * flips on gmch platforms, a flip count check isn't
9973          * really needed there. But since ctg has the registers,
9974          * include it in the check anyway.
9975          */
9976         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9977                 return true;
9978
9979         /*
9980          * BDW signals flip done immediately if the plane
9981          * is disabled, even if the plane enable is already
9982          * armed to occur at the next vblank :(
9983          */
9984
9985         /*
9986          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9987          * used the same base address. In that case the mmio flip might
9988          * have completed, but the CS hasn't even executed the flip yet.
9989          *
9990          * A flip count check isn't enough as the CS might have updated
9991          * the base address just after start of vblank, but before we
9992          * managed to process the interrupt. This means we'd complete the
9993          * CS flip too soon.
9994          *
9995          * Combining both checks should get us a good enough result. It may
9996          * still happen that the CS flip has been executed, but has not
9997          * yet actually completed. But in case the base address is the same
9998          * anyway, we don't really care.
9999          */
10000         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10001                 crtc->flip_work->gtt_offset &&
10002                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10003                                     crtc->flip_work->flip_count);
10004 }
10005
10006 static bool
10007 __pageflip_finished_mmio(struct intel_crtc *crtc,
10008                                struct intel_flip_work *work)
10009 {
10010         /*
10011          * MMIO work completes when vblank is different from
10012          * flip_queued_vblank.
10013          *
10014          * Reset counter value doesn't matter, this is handled by
10015          * i915_wait_request finishing early, so no need to handle
10016          * reset here.
10017          */
10018         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10019 }
10020
10021
10022 static bool pageflip_finished(struct intel_crtc *crtc,
10023                               struct intel_flip_work *work)
10024 {
10025         if (!atomic_read(&work->pending))
10026                 return false;
10027
10028         smp_rmb();
10029
10030         if (is_mmio_work(work))
10031                 return __pageflip_finished_mmio(crtc, work);
10032         else
10033                 return __pageflip_finished_cs(crtc, work);
10034 }
10035
10036 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10037 {
10038         struct drm_device *dev = &dev_priv->drm;
10039         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10040         struct intel_flip_work *work;
10041         unsigned long flags;
10042
10043         /* Ignore early vblank irqs */
10044         if (!crtc)
10045                 return;
10046
10047         /*
10048          * This is called both by irq handlers and the reset code (to complete
10049          * lost pageflips) so needs the full irqsave spinlocks.
10050          */
10051         spin_lock_irqsave(&dev->event_lock, flags);
10052         work = crtc->flip_work;
10053
10054         if (work != NULL &&
10055             !is_mmio_work(work) &&
10056             pageflip_finished(crtc, work))
10057                 page_flip_completed(crtc);
10058
10059         spin_unlock_irqrestore(&dev->event_lock, flags);
10060 }
10061
10062 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10063 {
10064         struct drm_device *dev = &dev_priv->drm;
10065         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10066         struct intel_flip_work *work;
10067         unsigned long flags;
10068
10069         /* Ignore early vblank irqs */
10070         if (!crtc)
10071                 return;
10072
10073         /*
10074          * This is called both by irq handlers and the reset code (to complete
10075          * lost pageflips) so needs the full irqsave spinlocks.
10076          */
10077         spin_lock_irqsave(&dev->event_lock, flags);
10078         work = crtc->flip_work;
10079
10080         if (work != NULL &&
10081             is_mmio_work(work) &&
10082             pageflip_finished(crtc, work))
10083                 page_flip_completed(crtc);
10084
10085         spin_unlock_irqrestore(&dev->event_lock, flags);
10086 }
10087
10088 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10089                                                struct intel_flip_work *work)
10090 {
10091         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10092
10093         /* Ensure that the work item is consistent when activating it ... */
10094         smp_mb__before_atomic();
10095         atomic_set(&work->pending, 1);
10096 }
10097
10098 static int intel_gen2_queue_flip(struct drm_device *dev,
10099                                  struct drm_crtc *crtc,
10100                                  struct drm_framebuffer *fb,
10101                                  struct drm_i915_gem_object *obj,
10102                                  struct drm_i915_gem_request *req,
10103                                  uint32_t flags)
10104 {
10105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10106         u32 flip_mask, *cs;
10107
10108         cs = intel_ring_begin(req, 6);
10109         if (IS_ERR(cs))
10110                 return PTR_ERR(cs);
10111
10112         /* Can't queue multiple flips, so wait for the previous
10113          * one to finish before executing the next.
10114          */
10115         if (intel_crtc->plane)
10116                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10117         else
10118                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10119         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10120         *cs++ = MI_NOOP;
10121         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10122         *cs++ = fb->pitches[0];
10123         *cs++ = intel_crtc->flip_work->gtt_offset;
10124         *cs++ = 0; /* aux display base address, unused */
10125
10126         return 0;
10127 }
10128
10129 static int intel_gen3_queue_flip(struct drm_device *dev,
10130                                  struct drm_crtc *crtc,
10131                                  struct drm_framebuffer *fb,
10132                                  struct drm_i915_gem_object *obj,
10133                                  struct drm_i915_gem_request *req,
10134                                  uint32_t flags)
10135 {
10136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10137         u32 flip_mask, *cs;
10138
10139         cs = intel_ring_begin(req, 6);
10140         if (IS_ERR(cs))
10141                 return PTR_ERR(cs);
10142
10143         if (intel_crtc->plane)
10144                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10145         else
10146                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10147         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10148         *cs++ = MI_NOOP;
10149         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10150         *cs++ = fb->pitches[0];
10151         *cs++ = intel_crtc->flip_work->gtt_offset;
10152         *cs++ = MI_NOOP;
10153
10154         return 0;
10155 }
10156
10157 static int intel_gen4_queue_flip(struct drm_device *dev,
10158                                  struct drm_crtc *crtc,
10159                                  struct drm_framebuffer *fb,
10160                                  struct drm_i915_gem_object *obj,
10161                                  struct drm_i915_gem_request *req,
10162                                  uint32_t flags)
10163 {
10164         struct drm_i915_private *dev_priv = to_i915(dev);
10165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10166         u32 pf, pipesrc, *cs;
10167
10168         cs = intel_ring_begin(req, 4);
10169         if (IS_ERR(cs))
10170                 return PTR_ERR(cs);
10171
10172         /* i965+ uses the linear or tiled offsets from the
10173          * Display Registers (which do not change across a page-flip)
10174          * so we need only reprogram the base address.
10175          */
10176         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10177         *cs++ = fb->pitches[0];
10178         *cs++ = intel_crtc->flip_work->gtt_offset |
10179                 intel_fb_modifier_to_tiling(fb->modifier);
10180
10181         /* XXX Enabling the panel-fitter across page-flip is so far
10182          * untested on non-native modes, so ignore it for now.
10183          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10184          */
10185         pf = 0;
10186         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10187         *cs++ = pf | pipesrc;
10188
10189         return 0;
10190 }
10191
10192 static int intel_gen6_queue_flip(struct drm_device *dev,
10193                                  struct drm_crtc *crtc,
10194                                  struct drm_framebuffer *fb,
10195                                  struct drm_i915_gem_object *obj,
10196                                  struct drm_i915_gem_request *req,
10197                                  uint32_t flags)
10198 {
10199         struct drm_i915_private *dev_priv = to_i915(dev);
10200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10201         u32 pf, pipesrc, *cs;
10202
10203         cs = intel_ring_begin(req, 4);
10204         if (IS_ERR(cs))
10205                 return PTR_ERR(cs);
10206
10207         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10208         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10209         *cs++ = intel_crtc->flip_work->gtt_offset;
10210
10211         /* Contrary to the suggestions in the documentation,
10212          * "Enable Panel Fitter" does not seem to be required when page
10213          * flipping with a non-native mode, and worse causes a normal
10214          * modeset to fail.
10215          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10216          */
10217         pf = 0;
10218         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10219         *cs++ = pf | pipesrc;
10220
10221         return 0;
10222 }
10223
10224 static int intel_gen7_queue_flip(struct drm_device *dev,
10225                                  struct drm_crtc *crtc,
10226                                  struct drm_framebuffer *fb,
10227                                  struct drm_i915_gem_object *obj,
10228                                  struct drm_i915_gem_request *req,
10229                                  uint32_t flags)
10230 {
10231         struct drm_i915_private *dev_priv = to_i915(dev);
10232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10233         u32 *cs, plane_bit = 0;
10234         int len, ret;
10235
10236         switch (intel_crtc->plane) {
10237         case PLANE_A:
10238                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10239                 break;
10240         case PLANE_B:
10241                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10242                 break;
10243         case PLANE_C:
10244                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10245                 break;
10246         default:
10247                 WARN_ONCE(1, "unknown plane in flip command\n");
10248                 return -ENODEV;
10249         }
10250
10251         len = 4;
10252         if (req->engine->id == RCS) {
10253                 len += 6;
10254                 /*
10255                  * On Gen 8, SRM is now taking an extra dword to accommodate
10256                  * 48bits addresses, and we need a NOOP for the batch size to
10257                  * stay even.
10258                  */
10259                 if (IS_GEN8(dev_priv))
10260                         len += 2;
10261         }
10262
10263         /*
10264          * BSpec MI_DISPLAY_FLIP for IVB:
10265          * "The full packet must be contained within the same cache line."
10266          *
10267          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10268          * cacheline, if we ever start emitting more commands before
10269          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10270          * then do the cacheline alignment, and finally emit the
10271          * MI_DISPLAY_FLIP.
10272          */
10273         ret = intel_ring_cacheline_align(req);
10274         if (ret)
10275                 return ret;
10276
10277         cs = intel_ring_begin(req, len);
10278         if (IS_ERR(cs))
10279                 return PTR_ERR(cs);
10280
10281         /* Unmask the flip-done completion message. Note that the bspec says that
10282          * we should do this for both the BCS and RCS, and that we must not unmask
10283          * more than one flip event at any time (or ensure that one flip message
10284          * can be sent by waiting for flip-done prior to queueing new flips).
10285          * Experimentation says that BCS works despite DERRMR masking all
10286          * flip-done completion events and that unmasking all planes at once
10287          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10288          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10289          */
10290         if (req->engine->id == RCS) {
10291                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10292                 *cs++ = i915_mmio_reg_offset(DERRMR);
10293                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10294                           DERRMR_PIPEB_PRI_FLIP_DONE |
10295                           DERRMR_PIPEC_PRI_FLIP_DONE);
10296                 if (IS_GEN8(dev_priv))
10297                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10298                                 MI_SRM_LRM_GLOBAL_GTT;
10299                 else
10300                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10301                 *cs++ = i915_mmio_reg_offset(DERRMR);
10302                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10303                 if (IS_GEN8(dev_priv)) {
10304                         *cs++ = 0;
10305                         *cs++ = MI_NOOP;
10306                 }
10307         }
10308
10309         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10310         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10311         *cs++ = intel_crtc->flip_work->gtt_offset;
10312         *cs++ = MI_NOOP;
10313
10314         return 0;
10315 }
10316
10317 static bool use_mmio_flip(struct intel_engine_cs *engine,
10318                           struct drm_i915_gem_object *obj)
10319 {
10320         /*
10321          * This is not being used for older platforms, because
10322          * non-availability of flip done interrupt forces us to use
10323          * CS flips. Older platforms derive flip done using some clever
10324          * tricks involving the flip_pending status bits and vblank irqs.
10325          * So using MMIO flips there would disrupt this mechanism.
10326          */
10327
10328         if (engine == NULL)
10329                 return true;
10330
10331         if (INTEL_GEN(engine->i915) < 5)
10332                 return false;
10333
10334         if (i915.use_mmio_flip < 0)
10335                 return false;
10336         else if (i915.use_mmio_flip > 0)
10337                 return true;
10338         else if (i915.enable_execlists)
10339                 return true;
10340
10341         return engine != i915_gem_object_last_write_engine(obj);
10342 }
10343
10344 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10345                              unsigned int rotation,
10346                              struct intel_flip_work *work)
10347 {
10348         struct drm_device *dev = intel_crtc->base.dev;
10349         struct drm_i915_private *dev_priv = to_i915(dev);
10350         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10351         const enum pipe pipe = intel_crtc->pipe;
10352         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10353
10354         ctl = I915_READ(PLANE_CTL(pipe, 0));
10355         ctl &= ~PLANE_CTL_TILED_MASK;
10356         switch (fb->modifier) {
10357         case DRM_FORMAT_MOD_NONE:
10358                 break;
10359         case I915_FORMAT_MOD_X_TILED:
10360                 ctl |= PLANE_CTL_TILED_X;
10361                 break;
10362         case I915_FORMAT_MOD_Y_TILED:
10363                 ctl |= PLANE_CTL_TILED_Y;
10364                 break;
10365         case I915_FORMAT_MOD_Yf_TILED:
10366                 ctl |= PLANE_CTL_TILED_YF;
10367                 break;
10368         default:
10369                 MISSING_CASE(fb->modifier);
10370         }
10371
10372         /*
10373          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10374          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10375          */
10376         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10377         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10378
10379         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10380         POSTING_READ(PLANE_SURF(pipe, 0));
10381 }
10382
10383 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10384                              struct intel_flip_work *work)
10385 {
10386         struct drm_device *dev = intel_crtc->base.dev;
10387         struct drm_i915_private *dev_priv = to_i915(dev);
10388         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10389         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10390         u32 dspcntr;
10391
10392         dspcntr = I915_READ(reg);
10393
10394         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10395                 dspcntr |= DISPPLANE_TILED;
10396         else
10397                 dspcntr &= ~DISPPLANE_TILED;
10398
10399         I915_WRITE(reg, dspcntr);
10400
10401         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10402         POSTING_READ(DSPSURF(intel_crtc->plane));
10403 }
10404
10405 static void intel_mmio_flip_work_func(struct work_struct *w)
10406 {
10407         struct intel_flip_work *work =
10408                 container_of(w, struct intel_flip_work, mmio_work);
10409         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10410         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10411         struct intel_framebuffer *intel_fb =
10412                 to_intel_framebuffer(crtc->base.primary->fb);
10413         struct drm_i915_gem_object *obj = intel_fb->obj;
10414
10415         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10416
10417         intel_pipe_update_start(crtc);
10418
10419         if (INTEL_GEN(dev_priv) >= 9)
10420                 skl_do_mmio_flip(crtc, work->rotation, work);
10421         else
10422                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10423                 ilk_do_mmio_flip(crtc, work);
10424
10425         intel_pipe_update_end(crtc, work);
10426 }
10427
10428 static int intel_default_queue_flip(struct drm_device *dev,
10429                                     struct drm_crtc *crtc,
10430                                     struct drm_framebuffer *fb,
10431                                     struct drm_i915_gem_object *obj,
10432                                     struct drm_i915_gem_request *req,
10433                                     uint32_t flags)
10434 {
10435         return -ENODEV;
10436 }
10437
10438 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10439                                       struct intel_crtc *intel_crtc,
10440                                       struct intel_flip_work *work)
10441 {
10442         u32 addr, vblank;
10443
10444         if (!atomic_read(&work->pending))
10445                 return false;
10446
10447         smp_rmb();
10448
10449         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10450         if (work->flip_ready_vblank == 0) {
10451                 if (work->flip_queued_req &&
10452                     !i915_gem_request_completed(work->flip_queued_req))
10453                         return false;
10454
10455                 work->flip_ready_vblank = vblank;
10456         }
10457
10458         if (vblank - work->flip_ready_vblank < 3)
10459                 return false;
10460
10461         /* Potential stall - if we see that the flip has happened,
10462          * assume a missed interrupt. */
10463         if (INTEL_GEN(dev_priv) >= 4)
10464                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10465         else
10466                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10467
10468         /* There is a potential issue here with a false positive after a flip
10469          * to the same address. We could address this by checking for a
10470          * non-incrementing frame counter.
10471          */
10472         return addr == work->gtt_offset;
10473 }
10474
10475 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10476 {
10477         struct drm_device *dev = &dev_priv->drm;
10478         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10479         struct intel_flip_work *work;
10480
10481         WARN_ON(!in_interrupt());
10482
10483         if (crtc == NULL)
10484                 return;
10485
10486         spin_lock(&dev->event_lock);
10487         work = crtc->flip_work;
10488
10489         if (work != NULL && !is_mmio_work(work) &&
10490             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10491                 WARN_ONCE(1,
10492                           "Kicking stuck page flip: queued at %d, now %d\n",
10493                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10494                 page_flip_completed(crtc);
10495                 work = NULL;
10496         }
10497
10498         if (work != NULL && !is_mmio_work(work) &&
10499             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10500                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10501         spin_unlock(&dev->event_lock);
10502 }
10503
10504 __maybe_unused
10505 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10506                                 struct drm_framebuffer *fb,
10507                                 struct drm_pending_vblank_event *event,
10508                                 uint32_t page_flip_flags)
10509 {
10510         struct drm_device *dev = crtc->dev;
10511         struct drm_i915_private *dev_priv = to_i915(dev);
10512         struct drm_framebuffer *old_fb = crtc->primary->fb;
10513         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10515         struct drm_plane *primary = crtc->primary;
10516         enum pipe pipe = intel_crtc->pipe;
10517         struct intel_flip_work *work;
10518         struct intel_engine_cs *engine;
10519         bool mmio_flip;
10520         struct drm_i915_gem_request *request;
10521         struct i915_vma *vma;
10522         int ret;
10523
10524         /*
10525          * drm_mode_page_flip_ioctl() should already catch this, but double
10526          * check to be safe.  In the future we may enable pageflipping from
10527          * a disabled primary plane.
10528          */
10529         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10530                 return -EBUSY;
10531
10532         /* Can't change pixel format via MI display flips. */
10533         if (fb->format != crtc->primary->fb->format)
10534                 return -EINVAL;
10535
10536         /*
10537          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10538          * Note that pitch changes could also affect these register.
10539          */
10540         if (INTEL_GEN(dev_priv) > 3 &&
10541             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10542              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10543                 return -EINVAL;
10544
10545         if (i915_terminally_wedged(&dev_priv->gpu_error))
10546                 goto out_hang;
10547
10548         work = kzalloc(sizeof(*work), GFP_KERNEL);
10549         if (work == NULL)
10550                 return -ENOMEM;
10551
10552         work->event = event;
10553         work->crtc = crtc;
10554         work->old_fb = old_fb;
10555         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10556
10557         ret = drm_crtc_vblank_get(crtc);
10558         if (ret)
10559                 goto free_work;
10560
10561         /* We borrow the event spin lock for protecting flip_work */
10562         spin_lock_irq(&dev->event_lock);
10563         if (intel_crtc->flip_work) {
10564                 /* Before declaring the flip queue wedged, check if
10565                  * the hardware completed the operation behind our backs.
10566                  */
10567                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10568                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10569                         page_flip_completed(intel_crtc);
10570                 } else {
10571                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10572                         spin_unlock_irq(&dev->event_lock);
10573
10574                         drm_crtc_vblank_put(crtc);
10575                         kfree(work);
10576                         return -EBUSY;
10577                 }
10578         }
10579         intel_crtc->flip_work = work;
10580         spin_unlock_irq(&dev->event_lock);
10581
10582         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10583                 flush_workqueue(dev_priv->wq);
10584
10585         /* Reference the objects for the scheduled work. */
10586         drm_framebuffer_reference(work->old_fb);
10587
10588         crtc->primary->fb = fb;
10589         update_state_fb(crtc->primary);
10590
10591         work->pending_flip_obj = i915_gem_object_get(obj);
10592
10593         ret = i915_mutex_lock_interruptible(dev);
10594         if (ret)
10595                 goto cleanup;
10596
10597         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10598         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10599                 ret = -EIO;
10600                 goto unlock;
10601         }
10602
10603         atomic_inc(&intel_crtc->unpin_work_count);
10604
10605         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10606                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10607
10608         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10609                 engine = dev_priv->engine[BCS];
10610                 if (fb->modifier != old_fb->modifier)
10611                         /* vlv: DISPLAY_FLIP fails to change tiling */
10612                         engine = NULL;
10613         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10614                 engine = dev_priv->engine[BCS];
10615         } else if (INTEL_GEN(dev_priv) >= 7) {
10616                 engine = i915_gem_object_last_write_engine(obj);
10617                 if (engine == NULL || engine->id != RCS)
10618                         engine = dev_priv->engine[BCS];
10619         } else {
10620                 engine = dev_priv->engine[RCS];
10621         }
10622
10623         mmio_flip = use_mmio_flip(engine, obj);
10624
10625         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10626         if (IS_ERR(vma)) {
10627                 ret = PTR_ERR(vma);
10628                 goto cleanup_pending;
10629         }
10630
10631         work->old_vma = to_intel_plane_state(primary->state)->vma;
10632         to_intel_plane_state(primary->state)->vma = vma;
10633
10634         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10635         work->rotation = crtc->primary->state->rotation;
10636
10637         /*
10638          * There's the potential that the next frame will not be compatible with
10639          * FBC, so we want to call pre_update() before the actual page flip.
10640          * The problem is that pre_update() caches some information about the fb
10641          * object, so we want to do this only after the object is pinned. Let's
10642          * be on the safe side and do this immediately before scheduling the
10643          * flip.
10644          */
10645         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10646                              to_intel_plane_state(primary->state));
10647
10648         if (mmio_flip) {
10649                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10650                 queue_work(system_unbound_wq, &work->mmio_work);
10651         } else {
10652                 request = i915_gem_request_alloc(engine,
10653                                                  dev_priv->kernel_context);
10654                 if (IS_ERR(request)) {
10655                         ret = PTR_ERR(request);
10656                         goto cleanup_unpin;
10657                 }
10658
10659                 ret = i915_gem_request_await_object(request, obj, false);
10660                 if (ret)
10661                         goto cleanup_request;
10662
10663                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10664                                                    page_flip_flags);
10665                 if (ret)
10666                         goto cleanup_request;
10667
10668                 intel_mark_page_flip_active(intel_crtc, work);
10669
10670                 work->flip_queued_req = i915_gem_request_get(request);
10671                 i915_add_request(request);
10672         }
10673
10674         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10675         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10676                           to_intel_plane(primary)->frontbuffer_bit);
10677         mutex_unlock(&dev->struct_mutex);
10678
10679         intel_frontbuffer_flip_prepare(to_i915(dev),
10680                                        to_intel_plane(primary)->frontbuffer_bit);
10681
10682         trace_i915_flip_request(intel_crtc->plane, obj);
10683
10684         return 0;
10685
10686 cleanup_request:
10687         i915_add_request(request);
10688 cleanup_unpin:
10689         to_intel_plane_state(primary->state)->vma = work->old_vma;
10690         intel_unpin_fb_vma(vma);
10691 cleanup_pending:
10692         atomic_dec(&intel_crtc->unpin_work_count);
10693 unlock:
10694         mutex_unlock(&dev->struct_mutex);
10695 cleanup:
10696         crtc->primary->fb = old_fb;
10697         update_state_fb(crtc->primary);
10698
10699         i915_gem_object_put(obj);
10700         drm_framebuffer_unreference(work->old_fb);
10701
10702         spin_lock_irq(&dev->event_lock);
10703         intel_crtc->flip_work = NULL;
10704         spin_unlock_irq(&dev->event_lock);
10705
10706         drm_crtc_vblank_put(crtc);
10707 free_work:
10708         kfree(work);
10709
10710         if (ret == -EIO) {
10711                 struct drm_atomic_state *state;
10712                 struct drm_plane_state *plane_state;
10713
10714 out_hang:
10715                 state = drm_atomic_state_alloc(dev);
10716                 if (!state)
10717                         return -ENOMEM;
10718                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10719
10720 retry:
10721                 plane_state = drm_atomic_get_plane_state(state, primary);
10722                 ret = PTR_ERR_OR_ZERO(plane_state);
10723                 if (!ret) {
10724                         drm_atomic_set_fb_for_plane(plane_state, fb);
10725
10726                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10727                         if (!ret)
10728                                 ret = drm_atomic_commit(state);
10729                 }
10730
10731                 if (ret == -EDEADLK) {
10732                         drm_modeset_backoff(state->acquire_ctx);
10733                         drm_atomic_state_clear(state);
10734                         goto retry;
10735                 }
10736
10737                 drm_atomic_state_put(state);
10738
10739                 if (ret == 0 && event) {
10740                         spin_lock_irq(&dev->event_lock);
10741                         drm_crtc_send_vblank_event(crtc, event);
10742                         spin_unlock_irq(&dev->event_lock);
10743                 }
10744         }
10745         return ret;
10746 }
10747
10748
10749 /**
10750  * intel_wm_need_update - Check whether watermarks need updating
10751  * @plane: drm plane
10752  * @state: new plane state
10753  *
10754  * Check current plane state versus the new one to determine whether
10755  * watermarks need to be recalculated.
10756  *
10757  * Returns true or false.
10758  */
10759 static bool intel_wm_need_update(struct drm_plane *plane,
10760                                  struct drm_plane_state *state)
10761 {
10762         struct intel_plane_state *new = to_intel_plane_state(state);
10763         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10764
10765         /* Update watermarks on tiling or size changes. */
10766         if (new->base.visible != cur->base.visible)
10767                 return true;
10768
10769         if (!cur->base.fb || !new->base.fb)
10770                 return false;
10771
10772         if (cur->base.fb->modifier != new->base.fb->modifier ||
10773             cur->base.rotation != new->base.rotation ||
10774             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10775             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10776             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10777             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10778                 return true;
10779
10780         return false;
10781 }
10782
10783 static bool needs_scaling(struct intel_plane_state *state)
10784 {
10785         int src_w = drm_rect_width(&state->base.src) >> 16;
10786         int src_h = drm_rect_height(&state->base.src) >> 16;
10787         int dst_w = drm_rect_width(&state->base.dst);
10788         int dst_h = drm_rect_height(&state->base.dst);
10789
10790         return (src_w != dst_w || src_h != dst_h);
10791 }
10792
10793 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10794                                     struct drm_plane_state *plane_state)
10795 {
10796         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10797         struct drm_crtc *crtc = crtc_state->crtc;
10798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10799         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10800         struct drm_device *dev = crtc->dev;
10801         struct drm_i915_private *dev_priv = to_i915(dev);
10802         struct intel_plane_state *old_plane_state =
10803                 to_intel_plane_state(plane->base.state);
10804         bool mode_changed = needs_modeset(crtc_state);
10805         bool was_crtc_enabled = crtc->state->active;
10806         bool is_crtc_enabled = crtc_state->active;
10807         bool turn_off, turn_on, visible, was_visible;
10808         struct drm_framebuffer *fb = plane_state->fb;
10809         int ret;
10810
10811         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10812                 ret = skl_update_scaler_plane(
10813                         to_intel_crtc_state(crtc_state),
10814                         to_intel_plane_state(plane_state));
10815                 if (ret)
10816                         return ret;
10817         }
10818
10819         was_visible = old_plane_state->base.visible;
10820         visible = plane_state->visible;
10821
10822         if (!was_crtc_enabled && WARN_ON(was_visible))
10823                 was_visible = false;
10824
10825         /*
10826          * Visibility is calculated as if the crtc was on, but
10827          * after scaler setup everything depends on it being off
10828          * when the crtc isn't active.
10829          *
10830          * FIXME this is wrong for watermarks. Watermarks should also
10831          * be computed as if the pipe would be active. Perhaps move
10832          * per-plane wm computation to the .check_plane() hook, and
10833          * only combine the results from all planes in the current place?
10834          */
10835         if (!is_crtc_enabled) {
10836                 plane_state->visible = visible = false;
10837                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10838         }
10839
10840         if (!was_visible && !visible)
10841                 return 0;
10842
10843         if (fb != old_plane_state->base.fb)
10844                 pipe_config->fb_changed = true;
10845
10846         turn_off = was_visible && (!visible || mode_changed);
10847         turn_on = visible && (!was_visible || mode_changed);
10848
10849         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10850                          intel_crtc->base.base.id, intel_crtc->base.name,
10851                          plane->base.base.id, plane->base.name,
10852                          fb ? fb->base.id : -1);
10853
10854         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10855                          plane->base.base.id, plane->base.name,
10856                          was_visible, visible,
10857                          turn_off, turn_on, mode_changed);
10858
10859         if (turn_on) {
10860                 if (INTEL_GEN(dev_priv) < 5)
10861                         pipe_config->update_wm_pre = true;
10862
10863                 /* must disable cxsr around plane enable/disable */
10864                 if (plane->id != PLANE_CURSOR)
10865                         pipe_config->disable_cxsr = true;
10866         } else if (turn_off) {
10867                 if (INTEL_GEN(dev_priv) < 5)
10868                         pipe_config->update_wm_post = true;
10869
10870                 /* must disable cxsr around plane enable/disable */
10871                 if (plane->id != PLANE_CURSOR)
10872                         pipe_config->disable_cxsr = true;
10873         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10874                 if (INTEL_GEN(dev_priv) < 5) {
10875                         /* FIXME bollocks */
10876                         pipe_config->update_wm_pre = true;
10877                         pipe_config->update_wm_post = true;
10878                 }
10879         }
10880
10881         if (visible || was_visible)
10882                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10883
10884         /*
10885          * WaCxSRDisabledForSpriteScaling:ivb
10886          *
10887          * cstate->update_wm was already set above, so this flag will
10888          * take effect when we commit and program watermarks.
10889          */
10890         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10891             needs_scaling(to_intel_plane_state(plane_state)) &&
10892             !needs_scaling(old_plane_state))
10893                 pipe_config->disable_lp_wm = true;
10894
10895         return 0;
10896 }
10897
10898 static bool encoders_cloneable(const struct intel_encoder *a,
10899                                const struct intel_encoder *b)
10900 {
10901         /* masks could be asymmetric, so check both ways */
10902         return a == b || (a->cloneable & (1 << b->type) &&
10903                           b->cloneable & (1 << a->type));
10904 }
10905
10906 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10907                                          struct intel_crtc *crtc,
10908                                          struct intel_encoder *encoder)
10909 {
10910         struct intel_encoder *source_encoder;
10911         struct drm_connector *connector;
10912         struct drm_connector_state *connector_state;
10913         int i;
10914
10915         for_each_new_connector_in_state(state, connector, connector_state, i) {
10916                 if (connector_state->crtc != &crtc->base)
10917                         continue;
10918
10919                 source_encoder =
10920                         to_intel_encoder(connector_state->best_encoder);
10921                 if (!encoders_cloneable(encoder, source_encoder))
10922                         return false;
10923         }
10924
10925         return true;
10926 }
10927
10928 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10929                                    struct drm_crtc_state *crtc_state)
10930 {
10931         struct drm_device *dev = crtc->dev;
10932         struct drm_i915_private *dev_priv = to_i915(dev);
10933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10934         struct intel_crtc_state *pipe_config =
10935                 to_intel_crtc_state(crtc_state);
10936         struct drm_atomic_state *state = crtc_state->state;
10937         int ret;
10938         bool mode_changed = needs_modeset(crtc_state);
10939
10940         if (mode_changed && !crtc_state->active)
10941                 pipe_config->update_wm_post = true;
10942
10943         if (mode_changed && crtc_state->enable &&
10944             dev_priv->display.crtc_compute_clock &&
10945             !WARN_ON(pipe_config->shared_dpll)) {
10946                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10947                                                            pipe_config);
10948                 if (ret)
10949                         return ret;
10950         }
10951
10952         if (crtc_state->color_mgmt_changed) {
10953                 ret = intel_color_check(crtc, crtc_state);
10954                 if (ret)
10955                         return ret;
10956
10957                 /*
10958                  * Changing color management on Intel hardware is
10959                  * handled as part of planes update.
10960                  */
10961                 crtc_state->planes_changed = true;
10962         }
10963
10964         ret = 0;
10965         if (dev_priv->display.compute_pipe_wm) {
10966                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10967                 if (ret) {
10968                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10969                         return ret;
10970                 }
10971         }
10972
10973         if (dev_priv->display.compute_intermediate_wm &&
10974             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10975                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10976                         return 0;
10977
10978                 /*
10979                  * Calculate 'intermediate' watermarks that satisfy both the
10980                  * old state and the new state.  We can program these
10981                  * immediately.
10982                  */
10983                 ret = dev_priv->display.compute_intermediate_wm(dev,
10984                                                                 intel_crtc,
10985                                                                 pipe_config);
10986                 if (ret) {
10987                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10988                         return ret;
10989                 }
10990         } else if (dev_priv->display.compute_intermediate_wm) {
10991                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10992                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10993         }
10994
10995         if (INTEL_GEN(dev_priv) >= 9) {
10996                 if (mode_changed)
10997                         ret = skl_update_scaler_crtc(pipe_config);
10998
10999                 if (!ret)
11000                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11001                                                          pipe_config);
11002         }
11003
11004         return ret;
11005 }
11006
11007 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11008         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11009         .atomic_begin = intel_begin_crtc_commit,
11010         .atomic_flush = intel_finish_crtc_commit,
11011         .atomic_check = intel_crtc_atomic_check,
11012 };
11013
11014 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11015 {
11016         struct intel_connector *connector;
11017         struct drm_connector_list_iter conn_iter;
11018
11019         drm_connector_list_iter_begin(dev, &conn_iter);
11020         for_each_intel_connector_iter(connector, &conn_iter) {
11021                 if (connector->base.state->crtc)
11022                         drm_connector_unreference(&connector->base);
11023
11024                 if (connector->base.encoder) {
11025                         connector->base.state->best_encoder =
11026                                 connector->base.encoder;
11027                         connector->base.state->crtc =
11028                                 connector->base.encoder->crtc;
11029
11030                         drm_connector_reference(&connector->base);
11031                 } else {
11032                         connector->base.state->best_encoder = NULL;
11033                         connector->base.state->crtc = NULL;
11034                 }
11035         }
11036         drm_connector_list_iter_end(&conn_iter);
11037 }
11038
11039 static void
11040 connected_sink_compute_bpp(struct intel_connector *connector,
11041                            struct intel_crtc_state *pipe_config)
11042 {
11043         const struct drm_display_info *info = &connector->base.display_info;
11044         int bpp = pipe_config->pipe_bpp;
11045
11046         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11047                       connector->base.base.id,
11048                       connector->base.name);
11049
11050         /* Don't use an invalid EDID bpc value */
11051         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11052                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11053                               bpp, info->bpc * 3);
11054                 pipe_config->pipe_bpp = info->bpc * 3;
11055         }
11056
11057         /* Clamp bpp to 8 on screens without EDID 1.4 */
11058         if (info->bpc == 0 && bpp > 24) {
11059                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11060                               bpp);
11061                 pipe_config->pipe_bpp = 24;
11062         }
11063 }
11064
11065 static int
11066 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11067                           struct intel_crtc_state *pipe_config)
11068 {
11069         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11070         struct drm_atomic_state *state;
11071         struct drm_connector *connector;
11072         struct drm_connector_state *connector_state;
11073         int bpp, i;
11074
11075         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11076             IS_CHERRYVIEW(dev_priv)))
11077                 bpp = 10*3;
11078         else if (INTEL_GEN(dev_priv) >= 5)
11079                 bpp = 12*3;
11080         else
11081                 bpp = 8*3;
11082
11083
11084         pipe_config->pipe_bpp = bpp;
11085
11086         state = pipe_config->base.state;
11087
11088         /* Clamp display bpp to EDID value */
11089         for_each_new_connector_in_state(state, connector, connector_state, i) {
11090                 if (connector_state->crtc != &crtc->base)
11091                         continue;
11092
11093                 connected_sink_compute_bpp(to_intel_connector(connector),
11094                                            pipe_config);
11095         }
11096
11097         return bpp;
11098 }
11099
11100 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11101 {
11102         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11103                         "type: 0x%x flags: 0x%x\n",
11104                 mode->crtc_clock,
11105                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11106                 mode->crtc_hsync_end, mode->crtc_htotal,
11107                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11108                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11109 }
11110
11111 static inline void
11112 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11113                       unsigned int lane_count, struct intel_link_m_n *m_n)
11114 {
11115         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11116                       id, lane_count,
11117                       m_n->gmch_m, m_n->gmch_n,
11118                       m_n->link_m, m_n->link_n, m_n->tu);
11119 }
11120
11121 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11122                                    struct intel_crtc_state *pipe_config,
11123                                    const char *context)
11124 {
11125         struct drm_device *dev = crtc->base.dev;
11126         struct drm_i915_private *dev_priv = to_i915(dev);
11127         struct drm_plane *plane;
11128         struct intel_plane *intel_plane;
11129         struct intel_plane_state *state;
11130         struct drm_framebuffer *fb;
11131
11132         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11133                       crtc->base.base.id, crtc->base.name, context);
11134
11135         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11136                       transcoder_name(pipe_config->cpu_transcoder),
11137                       pipe_config->pipe_bpp, pipe_config->dither);
11138
11139         if (pipe_config->has_pch_encoder)
11140                 intel_dump_m_n_config(pipe_config, "fdi",
11141                                       pipe_config->fdi_lanes,
11142                                       &pipe_config->fdi_m_n);
11143
11144         if (intel_crtc_has_dp_encoder(pipe_config)) {
11145                 intel_dump_m_n_config(pipe_config, "dp m_n",
11146                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11147                 if (pipe_config->has_drrs)
11148                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11149                                               pipe_config->lane_count,
11150                                               &pipe_config->dp_m2_n2);
11151         }
11152
11153         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11154                       pipe_config->has_audio, pipe_config->has_infoframe);
11155
11156         DRM_DEBUG_KMS("requested mode:\n");
11157         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11158         DRM_DEBUG_KMS("adjusted mode:\n");
11159         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11160         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11161         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11162                       pipe_config->port_clock,
11163                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11164                       pipe_config->pixel_rate);
11165
11166         if (INTEL_GEN(dev_priv) >= 9)
11167                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11168                               crtc->num_scalers,
11169                               pipe_config->scaler_state.scaler_users,
11170                               pipe_config->scaler_state.scaler_id);
11171
11172         if (HAS_GMCH_DISPLAY(dev_priv))
11173                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11174                               pipe_config->gmch_pfit.control,
11175                               pipe_config->gmch_pfit.pgm_ratios,
11176                               pipe_config->gmch_pfit.lvds_border_bits);
11177         else
11178                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11179                               pipe_config->pch_pfit.pos,
11180                               pipe_config->pch_pfit.size,
11181                               enableddisabled(pipe_config->pch_pfit.enabled));
11182
11183         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11184                       pipe_config->ips_enabled, pipe_config->double_wide);
11185
11186         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11187
11188         DRM_DEBUG_KMS("planes on this crtc\n");
11189         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11190                 struct drm_format_name_buf format_name;
11191                 intel_plane = to_intel_plane(plane);
11192                 if (intel_plane->pipe != crtc->pipe)
11193                         continue;
11194
11195                 state = to_intel_plane_state(plane->state);
11196                 fb = state->base.fb;
11197                 if (!fb) {
11198                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11199                                       plane->base.id, plane->name, state->scaler_id);
11200                         continue;
11201                 }
11202
11203                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11204                               plane->base.id, plane->name,
11205                               fb->base.id, fb->width, fb->height,
11206                               drm_get_format_name(fb->format->format, &format_name));
11207                 if (INTEL_GEN(dev_priv) >= 9)
11208                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11209                                       state->scaler_id,
11210                                       state->base.src.x1 >> 16,
11211                                       state->base.src.y1 >> 16,
11212                                       drm_rect_width(&state->base.src) >> 16,
11213                                       drm_rect_height(&state->base.src) >> 16,
11214                                       state->base.dst.x1, state->base.dst.y1,
11215                                       drm_rect_width(&state->base.dst),
11216                                       drm_rect_height(&state->base.dst));
11217         }
11218 }
11219
11220 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11221 {
11222         struct drm_device *dev = state->dev;
11223         struct drm_connector *connector;
11224         unsigned int used_ports = 0;
11225         unsigned int used_mst_ports = 0;
11226
11227         /*
11228          * Walk the connector list instead of the encoder
11229          * list to detect the problem on ddi platforms
11230          * where there's just one encoder per digital port.
11231          */
11232         drm_for_each_connector(connector, dev) {
11233                 struct drm_connector_state *connector_state;
11234                 struct intel_encoder *encoder;
11235
11236                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11237                 if (!connector_state)
11238                         connector_state = connector->state;
11239
11240                 if (!connector_state->best_encoder)
11241                         continue;
11242
11243                 encoder = to_intel_encoder(connector_state->best_encoder);
11244
11245                 WARN_ON(!connector_state->crtc);
11246
11247                 switch (encoder->type) {
11248                         unsigned int port_mask;
11249                 case INTEL_OUTPUT_UNKNOWN:
11250                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11251                                 break;
11252                 case INTEL_OUTPUT_DP:
11253                 case INTEL_OUTPUT_HDMI:
11254                 case INTEL_OUTPUT_EDP:
11255                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11256
11257                         /* the same port mustn't appear more than once */
11258                         if (used_ports & port_mask)
11259                                 return false;
11260
11261                         used_ports |= port_mask;
11262                         break;
11263                 case INTEL_OUTPUT_DP_MST:
11264                         used_mst_ports |=
11265                                 1 << enc_to_mst(&encoder->base)->primary->port;
11266                         break;
11267                 default:
11268                         break;
11269                 }
11270         }
11271
11272         /* can't mix MST and SST/HDMI on the same port */
11273         if (used_ports & used_mst_ports)
11274                 return false;
11275
11276         return true;
11277 }
11278
11279 static void
11280 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11281 {
11282         struct drm_i915_private *dev_priv =
11283                 to_i915(crtc_state->base.crtc->dev);
11284         struct intel_crtc_scaler_state scaler_state;
11285         struct intel_dpll_hw_state dpll_hw_state;
11286         struct intel_shared_dpll *shared_dpll;
11287         struct intel_crtc_wm_state wm_state;
11288         bool force_thru;
11289
11290         /* FIXME: before the switch to atomic started, a new pipe_config was
11291          * kzalloc'd. Code that depends on any field being zero should be
11292          * fixed, so that the crtc_state can be safely duplicated. For now,
11293          * only fields that are know to not cause problems are preserved. */
11294
11295         scaler_state = crtc_state->scaler_state;
11296         shared_dpll = crtc_state->shared_dpll;
11297         dpll_hw_state = crtc_state->dpll_hw_state;
11298         force_thru = crtc_state->pch_pfit.force_thru;
11299         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11300                 wm_state = crtc_state->wm;
11301
11302         /* Keep base drm_crtc_state intact, only clear our extended struct */
11303         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11304         memset(&crtc_state->base + 1, 0,
11305                sizeof(*crtc_state) - sizeof(crtc_state->base));
11306
11307         crtc_state->scaler_state = scaler_state;
11308         crtc_state->shared_dpll = shared_dpll;
11309         crtc_state->dpll_hw_state = dpll_hw_state;
11310         crtc_state->pch_pfit.force_thru = force_thru;
11311         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11312                 crtc_state->wm = wm_state;
11313 }
11314
11315 static int
11316 intel_modeset_pipe_config(struct drm_crtc *crtc,
11317                           struct intel_crtc_state *pipe_config)
11318 {
11319         struct drm_atomic_state *state = pipe_config->base.state;
11320         struct intel_encoder *encoder;
11321         struct drm_connector *connector;
11322         struct drm_connector_state *connector_state;
11323         int base_bpp, ret = -EINVAL;
11324         int i;
11325         bool retry = true;
11326
11327         clear_intel_crtc_state(pipe_config);
11328
11329         pipe_config->cpu_transcoder =
11330                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11331
11332         /*
11333          * Sanitize sync polarity flags based on requested ones. If neither
11334          * positive or negative polarity is requested, treat this as meaning
11335          * negative polarity.
11336          */
11337         if (!(pipe_config->base.adjusted_mode.flags &
11338               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11339                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11340
11341         if (!(pipe_config->base.adjusted_mode.flags &
11342               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11343                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11344
11345         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11346                                              pipe_config);
11347         if (base_bpp < 0)
11348                 goto fail;
11349
11350         /*
11351          * Determine the real pipe dimensions. Note that stereo modes can
11352          * increase the actual pipe size due to the frame doubling and
11353          * insertion of additional space for blanks between the frame. This
11354          * is stored in the crtc timings. We use the requested mode to do this
11355          * computation to clearly distinguish it from the adjusted mode, which
11356          * can be changed by the connectors in the below retry loop.
11357          */
11358         drm_mode_get_hv_timing(&pipe_config->base.mode,
11359                                &pipe_config->pipe_src_w,
11360                                &pipe_config->pipe_src_h);
11361
11362         for_each_new_connector_in_state(state, connector, connector_state, i) {
11363                 if (connector_state->crtc != crtc)
11364                         continue;
11365
11366                 encoder = to_intel_encoder(connector_state->best_encoder);
11367
11368                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11369                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11370                         goto fail;
11371                 }
11372
11373                 /*
11374                  * Determine output_types before calling the .compute_config()
11375                  * hooks so that the hooks can use this information safely.
11376                  */
11377                 pipe_config->output_types |= 1 << encoder->type;
11378         }
11379
11380 encoder_retry:
11381         /* Ensure the port clock defaults are reset when retrying. */
11382         pipe_config->port_clock = 0;
11383         pipe_config->pixel_multiplier = 1;
11384
11385         /* Fill in default crtc timings, allow encoders to overwrite them. */
11386         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11387                               CRTC_STEREO_DOUBLE);
11388
11389         /* Pass our mode to the connectors and the CRTC to give them a chance to
11390          * adjust it according to limitations or connector properties, and also
11391          * a chance to reject the mode entirely.
11392          */
11393         for_each_new_connector_in_state(state, connector, connector_state, i) {
11394                 if (connector_state->crtc != crtc)
11395                         continue;
11396
11397                 encoder = to_intel_encoder(connector_state->best_encoder);
11398
11399                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11400                         DRM_DEBUG_KMS("Encoder config failure\n");
11401                         goto fail;
11402                 }
11403         }
11404
11405         /* Set default port clock if not overwritten by the encoder. Needs to be
11406          * done afterwards in case the encoder adjusts the mode. */
11407         if (!pipe_config->port_clock)
11408                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11409                         * pipe_config->pixel_multiplier;
11410
11411         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11412         if (ret < 0) {
11413                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11414                 goto fail;
11415         }
11416
11417         if (ret == RETRY) {
11418                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11419                         ret = -EINVAL;
11420                         goto fail;
11421                 }
11422
11423                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11424                 retry = false;
11425                 goto encoder_retry;
11426         }
11427
11428         /* Dithering seems to not pass-through bits correctly when it should, so
11429          * only enable it on 6bpc panels and when its not a compliance
11430          * test requesting 6bpc video pattern.
11431          */
11432         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11433                 !pipe_config->dither_force_disable;
11434         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11435                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11436
11437 fail:
11438         return ret;
11439 }
11440
11441 static void
11442 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11443 {
11444         struct drm_crtc *crtc;
11445         struct drm_crtc_state *new_crtc_state;
11446         int i;
11447
11448         /* Double check state. */
11449         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11450                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11451
11452                 /* Update hwmode for vblank functions */
11453                 if (new_crtc_state->active)
11454                         crtc->hwmode = new_crtc_state->adjusted_mode;
11455                 else
11456                         crtc->hwmode.crtc_clock = 0;
11457
11458                 /*
11459                  * Update legacy state to satisfy fbc code. This can
11460                  * be removed when fbc uses the atomic state.
11461                  */
11462                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11463                         struct drm_plane_state *plane_state = crtc->primary->state;
11464
11465                         crtc->primary->fb = plane_state->fb;
11466                         crtc->x = plane_state->src_x >> 16;
11467                         crtc->y = plane_state->src_y >> 16;
11468                 }
11469         }
11470 }
11471
11472 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11473 {
11474         int diff;
11475
11476         if (clock1 == clock2)
11477                 return true;
11478
11479         if (!clock1 || !clock2)
11480                 return false;
11481
11482         diff = abs(clock1 - clock2);
11483
11484         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11485                 return true;
11486
11487         return false;
11488 }
11489
11490 static bool
11491 intel_compare_m_n(unsigned int m, unsigned int n,
11492                   unsigned int m2, unsigned int n2,
11493                   bool exact)
11494 {
11495         if (m == m2 && n == n2)
11496                 return true;
11497
11498         if (exact || !m || !n || !m2 || !n2)
11499                 return false;
11500
11501         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11502
11503         if (n > n2) {
11504                 while (n > n2) {
11505                         m2 <<= 1;
11506                         n2 <<= 1;
11507                 }
11508         } else if (n < n2) {
11509                 while (n < n2) {
11510                         m <<= 1;
11511                         n <<= 1;
11512                 }
11513         }
11514
11515         if (n != n2)
11516                 return false;
11517
11518         return intel_fuzzy_clock_check(m, m2);
11519 }
11520
11521 static bool
11522 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11523                        struct intel_link_m_n *m2_n2,
11524                        bool adjust)
11525 {
11526         if (m_n->tu == m2_n2->tu &&
11527             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11528                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11529             intel_compare_m_n(m_n->link_m, m_n->link_n,
11530                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11531                 if (adjust)
11532                         *m2_n2 = *m_n;
11533
11534                 return true;
11535         }
11536
11537         return false;
11538 }
11539
11540 static void __printf(3, 4)
11541 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11542 {
11543         char *level;
11544         unsigned int category;
11545         struct va_format vaf;
11546         va_list args;
11547
11548         if (adjust) {
11549                 level = KERN_DEBUG;
11550                 category = DRM_UT_KMS;
11551         } else {
11552                 level = KERN_ERR;
11553                 category = DRM_UT_NONE;
11554         }
11555
11556         va_start(args, format);
11557         vaf.fmt = format;
11558         vaf.va = &args;
11559
11560         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11561
11562         va_end(args);
11563 }
11564
11565 static bool
11566 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11567                           struct intel_crtc_state *current_config,
11568                           struct intel_crtc_state *pipe_config,
11569                           bool adjust)
11570 {
11571         bool ret = true;
11572
11573 #define PIPE_CONF_CHECK_X(name) \
11574         if (current_config->name != pipe_config->name) { \
11575                 pipe_config_err(adjust, __stringify(name), \
11576                           "(expected 0x%08x, found 0x%08x)\n", \
11577                           current_config->name, \
11578                           pipe_config->name); \
11579                 ret = false; \
11580         }
11581
11582 #define PIPE_CONF_CHECK_I(name) \
11583         if (current_config->name != pipe_config->name) { \
11584                 pipe_config_err(adjust, __stringify(name), \
11585                           "(expected %i, found %i)\n", \
11586                           current_config->name, \
11587                           pipe_config->name); \
11588                 ret = false; \
11589         }
11590
11591 #define PIPE_CONF_CHECK_P(name) \
11592         if (current_config->name != pipe_config->name) { \
11593                 pipe_config_err(adjust, __stringify(name), \
11594                           "(expected %p, found %p)\n", \
11595                           current_config->name, \
11596                           pipe_config->name); \
11597                 ret = false; \
11598         }
11599
11600 #define PIPE_CONF_CHECK_M_N(name) \
11601         if (!intel_compare_link_m_n(&current_config->name, \
11602                                     &pipe_config->name,\
11603                                     adjust)) { \
11604                 pipe_config_err(adjust, __stringify(name), \
11605                           "(expected tu %i gmch %i/%i link %i/%i, " \
11606                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11607                           current_config->name.tu, \
11608                           current_config->name.gmch_m, \
11609                           current_config->name.gmch_n, \
11610                           current_config->name.link_m, \
11611                           current_config->name.link_n, \
11612                           pipe_config->name.tu, \
11613                           pipe_config->name.gmch_m, \
11614                           pipe_config->name.gmch_n, \
11615                           pipe_config->name.link_m, \
11616                           pipe_config->name.link_n); \
11617                 ret = false; \
11618         }
11619
11620 /* This is required for BDW+ where there is only one set of registers for
11621  * switching between high and low RR.
11622  * This macro can be used whenever a comparison has to be made between one
11623  * hw state and multiple sw state variables.
11624  */
11625 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11626         if (!intel_compare_link_m_n(&current_config->name, \
11627                                     &pipe_config->name, adjust) && \
11628             !intel_compare_link_m_n(&current_config->alt_name, \
11629                                     &pipe_config->name, adjust)) { \
11630                 pipe_config_err(adjust, __stringify(name), \
11631                           "(expected tu %i gmch %i/%i link %i/%i, " \
11632                           "or tu %i gmch %i/%i link %i/%i, " \
11633                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11634                           current_config->name.tu, \
11635                           current_config->name.gmch_m, \
11636                           current_config->name.gmch_n, \
11637                           current_config->name.link_m, \
11638                           current_config->name.link_n, \
11639                           current_config->alt_name.tu, \
11640                           current_config->alt_name.gmch_m, \
11641                           current_config->alt_name.gmch_n, \
11642                           current_config->alt_name.link_m, \
11643                           current_config->alt_name.link_n, \
11644                           pipe_config->name.tu, \
11645                           pipe_config->name.gmch_m, \
11646                           pipe_config->name.gmch_n, \
11647                           pipe_config->name.link_m, \
11648                           pipe_config->name.link_n); \
11649                 ret = false; \
11650         }
11651
11652 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11653         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11654                 pipe_config_err(adjust, __stringify(name), \
11655                           "(%x) (expected %i, found %i)\n", \
11656                           (mask), \
11657                           current_config->name & (mask), \
11658                           pipe_config->name & (mask)); \
11659                 ret = false; \
11660         }
11661
11662 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11663         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11664                 pipe_config_err(adjust, __stringify(name), \
11665                           "(expected %i, found %i)\n", \
11666                           current_config->name, \
11667                           pipe_config->name); \
11668                 ret = false; \
11669         }
11670
11671 #define PIPE_CONF_QUIRK(quirk)  \
11672         ((current_config->quirks | pipe_config->quirks) & (quirk))
11673
11674         PIPE_CONF_CHECK_I(cpu_transcoder);
11675
11676         PIPE_CONF_CHECK_I(has_pch_encoder);
11677         PIPE_CONF_CHECK_I(fdi_lanes);
11678         PIPE_CONF_CHECK_M_N(fdi_m_n);
11679
11680         PIPE_CONF_CHECK_I(lane_count);
11681         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11682
11683         if (INTEL_GEN(dev_priv) < 8) {
11684                 PIPE_CONF_CHECK_M_N(dp_m_n);
11685
11686                 if (current_config->has_drrs)
11687                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11688         } else
11689                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11690
11691         PIPE_CONF_CHECK_X(output_types);
11692
11693         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11694         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11695         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11696         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11697         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11698         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11699
11700         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11701         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11702         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11703         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11704         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11705         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11706
11707         PIPE_CONF_CHECK_I(pixel_multiplier);
11708         PIPE_CONF_CHECK_I(has_hdmi_sink);
11709         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11710             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11711                 PIPE_CONF_CHECK_I(limited_color_range);
11712         PIPE_CONF_CHECK_I(has_infoframe);
11713
11714         PIPE_CONF_CHECK_I(has_audio);
11715
11716         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11717                               DRM_MODE_FLAG_INTERLACE);
11718
11719         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11720                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11721                                       DRM_MODE_FLAG_PHSYNC);
11722                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11723                                       DRM_MODE_FLAG_NHSYNC);
11724                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11725                                       DRM_MODE_FLAG_PVSYNC);
11726                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11727                                       DRM_MODE_FLAG_NVSYNC);
11728         }
11729
11730         PIPE_CONF_CHECK_X(gmch_pfit.control);
11731         /* pfit ratios are autocomputed by the hw on gen4+ */
11732         if (INTEL_GEN(dev_priv) < 4)
11733                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11734         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11735
11736         if (!adjust) {
11737                 PIPE_CONF_CHECK_I(pipe_src_w);
11738                 PIPE_CONF_CHECK_I(pipe_src_h);
11739
11740                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11741                 if (current_config->pch_pfit.enabled) {
11742                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11743                         PIPE_CONF_CHECK_X(pch_pfit.size);
11744                 }
11745
11746                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11747                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11748         }
11749
11750         /* BDW+ don't expose a synchronous way to read the state */
11751         if (IS_HASWELL(dev_priv))
11752                 PIPE_CONF_CHECK_I(ips_enabled);
11753
11754         PIPE_CONF_CHECK_I(double_wide);
11755
11756         PIPE_CONF_CHECK_P(shared_dpll);
11757         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11758         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11759         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11760         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11761         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11762         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11763         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11764         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11765         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11766
11767         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11768         PIPE_CONF_CHECK_X(dsi_pll.div);
11769
11770         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11771                 PIPE_CONF_CHECK_I(pipe_bpp);
11772
11773         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11774         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11775
11776 #undef PIPE_CONF_CHECK_X
11777 #undef PIPE_CONF_CHECK_I
11778 #undef PIPE_CONF_CHECK_P
11779 #undef PIPE_CONF_CHECK_FLAGS
11780 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11781 #undef PIPE_CONF_QUIRK
11782
11783         return ret;
11784 }
11785
11786 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11787                                            const struct intel_crtc_state *pipe_config)
11788 {
11789         if (pipe_config->has_pch_encoder) {
11790                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11791                                                             &pipe_config->fdi_m_n);
11792                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11793
11794                 /*
11795                  * FDI already provided one idea for the dotclock.
11796                  * Yell if the encoder disagrees.
11797                  */
11798                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11799                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11800                      fdi_dotclock, dotclock);
11801         }
11802 }
11803
11804 static void verify_wm_state(struct drm_crtc *crtc,
11805                             struct drm_crtc_state *new_state)
11806 {
11807         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11808         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11809         struct skl_pipe_wm hw_wm, *sw_wm;
11810         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11811         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11813         const enum pipe pipe = intel_crtc->pipe;
11814         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11815
11816         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11817                 return;
11818
11819         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11820         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11821
11822         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11823         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11824
11825         /* planes */
11826         for_each_universal_plane(dev_priv, pipe, plane) {
11827                 hw_plane_wm = &hw_wm.planes[plane];
11828                 sw_plane_wm = &sw_wm->planes[plane];
11829
11830                 /* Watermarks */
11831                 for (level = 0; level <= max_level; level++) {
11832                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11833                                                 &sw_plane_wm->wm[level]))
11834                                 continue;
11835
11836                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11837                                   pipe_name(pipe), plane + 1, level,
11838                                   sw_plane_wm->wm[level].plane_en,
11839                                   sw_plane_wm->wm[level].plane_res_b,
11840                                   sw_plane_wm->wm[level].plane_res_l,
11841                                   hw_plane_wm->wm[level].plane_en,
11842                                   hw_plane_wm->wm[level].plane_res_b,
11843                                   hw_plane_wm->wm[level].plane_res_l);
11844                 }
11845
11846                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11847                                          &sw_plane_wm->trans_wm)) {
11848                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11849                                   pipe_name(pipe), plane + 1,
11850                                   sw_plane_wm->trans_wm.plane_en,
11851                                   sw_plane_wm->trans_wm.plane_res_b,
11852                                   sw_plane_wm->trans_wm.plane_res_l,
11853                                   hw_plane_wm->trans_wm.plane_en,
11854                                   hw_plane_wm->trans_wm.plane_res_b,
11855                                   hw_plane_wm->trans_wm.plane_res_l);
11856                 }
11857
11858                 /* DDB */
11859                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11860                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11861
11862                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11863                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11864                                   pipe_name(pipe), plane + 1,
11865                                   sw_ddb_entry->start, sw_ddb_entry->end,
11866                                   hw_ddb_entry->start, hw_ddb_entry->end);
11867                 }
11868         }
11869
11870         /*
11871          * cursor
11872          * If the cursor plane isn't active, we may not have updated it's ddb
11873          * allocation. In that case since the ddb allocation will be updated
11874          * once the plane becomes visible, we can skip this check
11875          */
11876         if (intel_crtc->cursor_addr) {
11877                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11878                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11879
11880                 /* Watermarks */
11881                 for (level = 0; level <= max_level; level++) {
11882                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11883                                                 &sw_plane_wm->wm[level]))
11884                                 continue;
11885
11886                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11887                                   pipe_name(pipe), level,
11888                                   sw_plane_wm->wm[level].plane_en,
11889                                   sw_plane_wm->wm[level].plane_res_b,
11890                                   sw_plane_wm->wm[level].plane_res_l,
11891                                   hw_plane_wm->wm[level].plane_en,
11892                                   hw_plane_wm->wm[level].plane_res_b,
11893                                   hw_plane_wm->wm[level].plane_res_l);
11894                 }
11895
11896                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11897                                          &sw_plane_wm->trans_wm)) {
11898                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11899                                   pipe_name(pipe),
11900                                   sw_plane_wm->trans_wm.plane_en,
11901                                   sw_plane_wm->trans_wm.plane_res_b,
11902                                   sw_plane_wm->trans_wm.plane_res_l,
11903                                   hw_plane_wm->trans_wm.plane_en,
11904                                   hw_plane_wm->trans_wm.plane_res_b,
11905                                   hw_plane_wm->trans_wm.plane_res_l);
11906                 }
11907
11908                 /* DDB */
11909                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11910                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11911
11912                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11913                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11914                                   pipe_name(pipe),
11915                                   sw_ddb_entry->start, sw_ddb_entry->end,
11916                                   hw_ddb_entry->start, hw_ddb_entry->end);
11917                 }
11918         }
11919 }
11920
11921 static void
11922 verify_connector_state(struct drm_device *dev,
11923                        struct drm_atomic_state *state,
11924                        struct drm_crtc *crtc)
11925 {
11926         struct drm_connector *connector;
11927         struct drm_connector_state *new_conn_state;
11928         int i;
11929
11930         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11931                 struct drm_encoder *encoder = connector->encoder;
11932
11933                 if (new_conn_state->crtc != crtc)
11934                         continue;
11935
11936                 intel_connector_verify_state(to_intel_connector(connector));
11937
11938                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11939                      "connector's atomic encoder doesn't match legacy encoder\n");
11940         }
11941 }
11942
11943 static void
11944 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11945 {
11946         struct intel_encoder *encoder;
11947         struct drm_connector *connector;
11948         struct drm_connector_state *old_conn_state, *new_conn_state;
11949         int i;
11950
11951         for_each_intel_encoder(dev, encoder) {
11952                 bool enabled = false, found = false;
11953                 enum pipe pipe;
11954
11955                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11956                               encoder->base.base.id,
11957                               encoder->base.name);
11958
11959                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11960                                                    new_conn_state, i) {
11961                         if (old_conn_state->best_encoder == &encoder->base)
11962                                 found = true;
11963
11964                         if (new_conn_state->best_encoder != &encoder->base)
11965                                 continue;
11966                         found = enabled = true;
11967
11968                         I915_STATE_WARN(new_conn_state->crtc !=
11969                                         encoder->base.crtc,
11970                              "connector's crtc doesn't match encoder crtc\n");
11971                 }
11972
11973                 if (!found)
11974                         continue;
11975
11976                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11977                      "encoder's enabled state mismatch "
11978                      "(expected %i, found %i)\n",
11979                      !!encoder->base.crtc, enabled);
11980
11981                 if (!encoder->base.crtc) {
11982                         bool active;
11983
11984                         active = encoder->get_hw_state(encoder, &pipe);
11985                         I915_STATE_WARN(active,
11986                              "encoder detached but still enabled on pipe %c.\n",
11987                              pipe_name(pipe));
11988                 }
11989         }
11990 }
11991
11992 static void
11993 verify_crtc_state(struct drm_crtc *crtc,
11994                   struct drm_crtc_state *old_crtc_state,
11995                   struct drm_crtc_state *new_crtc_state)
11996 {
11997         struct drm_device *dev = crtc->dev;
11998         struct drm_i915_private *dev_priv = to_i915(dev);
11999         struct intel_encoder *encoder;
12000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12001         struct intel_crtc_state *pipe_config, *sw_config;
12002         struct drm_atomic_state *old_state;
12003         bool active;
12004
12005         old_state = old_crtc_state->state;
12006         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12007         pipe_config = to_intel_crtc_state(old_crtc_state);
12008         memset(pipe_config, 0, sizeof(*pipe_config));
12009         pipe_config->base.crtc = crtc;
12010         pipe_config->base.state = old_state;
12011
12012         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12013
12014         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12015
12016         /* hw state is inconsistent with the pipe quirk */
12017         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12018             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12019                 active = new_crtc_state->active;
12020
12021         I915_STATE_WARN(new_crtc_state->active != active,
12022              "crtc active state doesn't match with hw state "
12023              "(expected %i, found %i)\n", new_crtc_state->active, active);
12024
12025         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12026              "transitional active state does not match atomic hw state "
12027              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12028
12029         for_each_encoder_on_crtc(dev, crtc, encoder) {
12030                 enum pipe pipe;
12031
12032                 active = encoder->get_hw_state(encoder, &pipe);
12033                 I915_STATE_WARN(active != new_crtc_state->active,
12034                         "[ENCODER:%i] active %i with crtc active %i\n",
12035                         encoder->base.base.id, active, new_crtc_state->active);
12036
12037                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12038                                 "Encoder connected to wrong pipe %c\n",
12039                                 pipe_name(pipe));
12040
12041                 if (active) {
12042                         pipe_config->output_types |= 1 << encoder->type;
12043                         encoder->get_config(encoder, pipe_config);
12044                 }
12045         }
12046
12047         intel_crtc_compute_pixel_rate(pipe_config);
12048
12049         if (!new_crtc_state->active)
12050                 return;
12051
12052         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12053
12054         sw_config = to_intel_crtc_state(crtc->state);
12055         if (!intel_pipe_config_compare(dev_priv, sw_config,
12056                                        pipe_config, false)) {
12057                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12058                 intel_dump_pipe_config(intel_crtc, pipe_config,
12059                                        "[hw state]");
12060                 intel_dump_pipe_config(intel_crtc, sw_config,
12061                                        "[sw state]");
12062         }
12063 }
12064
12065 static void
12066 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12067                          struct intel_shared_dpll *pll,
12068                          struct drm_crtc *crtc,
12069                          struct drm_crtc_state *new_state)
12070 {
12071         struct intel_dpll_hw_state dpll_hw_state;
12072         unsigned crtc_mask;
12073         bool active;
12074
12075         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12076
12077         DRM_DEBUG_KMS("%s\n", pll->name);
12078
12079         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12080
12081         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12082                 I915_STATE_WARN(!pll->on && pll->active_mask,
12083                      "pll in active use but not on in sw tracking\n");
12084                 I915_STATE_WARN(pll->on && !pll->active_mask,
12085                      "pll is on but not used by any active crtc\n");
12086                 I915_STATE_WARN(pll->on != active,
12087                      "pll on state mismatch (expected %i, found %i)\n",
12088                      pll->on, active);
12089         }
12090
12091         if (!crtc) {
12092                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12093                                 "more active pll users than references: %x vs %x\n",
12094                                 pll->active_mask, pll->state.crtc_mask);
12095
12096                 return;
12097         }
12098
12099         crtc_mask = 1 << drm_crtc_index(crtc);
12100
12101         if (new_state->active)
12102                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12103                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12104                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12105         else
12106                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12107                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12108                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12109
12110         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12111                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12112                         crtc_mask, pll->state.crtc_mask);
12113
12114         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12115                                           &dpll_hw_state,
12116                                           sizeof(dpll_hw_state)),
12117                         "pll hw state mismatch\n");
12118 }
12119
12120 static void
12121 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12122                          struct drm_crtc_state *old_crtc_state,
12123                          struct drm_crtc_state *new_crtc_state)
12124 {
12125         struct drm_i915_private *dev_priv = to_i915(dev);
12126         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12127         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12128
12129         if (new_state->shared_dpll)
12130                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12131
12132         if (old_state->shared_dpll &&
12133             old_state->shared_dpll != new_state->shared_dpll) {
12134                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12135                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12136
12137                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12138                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12139                                 pipe_name(drm_crtc_index(crtc)));
12140                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12141                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12142                                 pipe_name(drm_crtc_index(crtc)));
12143         }
12144 }
12145
12146 static void
12147 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12148                           struct drm_atomic_state *state,
12149                           struct drm_crtc_state *old_state,
12150                           struct drm_crtc_state *new_state)
12151 {
12152         if (!needs_modeset(new_state) &&
12153             !to_intel_crtc_state(new_state)->update_pipe)
12154                 return;
12155
12156         verify_wm_state(crtc, new_state);
12157         verify_connector_state(crtc->dev, state, crtc);
12158         verify_crtc_state(crtc, old_state, new_state);
12159         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12160 }
12161
12162 static void
12163 verify_disabled_dpll_state(struct drm_device *dev)
12164 {
12165         struct drm_i915_private *dev_priv = to_i915(dev);
12166         int i;
12167
12168         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12169                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12170 }
12171
12172 static void
12173 intel_modeset_verify_disabled(struct drm_device *dev,
12174                               struct drm_atomic_state *state)
12175 {
12176         verify_encoder_state(dev, state);
12177         verify_connector_state(dev, state, NULL);
12178         verify_disabled_dpll_state(dev);
12179 }
12180
12181 static void update_scanline_offset(struct intel_crtc *crtc)
12182 {
12183         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12184
12185         /*
12186          * The scanline counter increments at the leading edge of hsync.
12187          *
12188          * On most platforms it starts counting from vtotal-1 on the
12189          * first active line. That means the scanline counter value is
12190          * always one less than what we would expect. Ie. just after
12191          * start of vblank, which also occurs at start of hsync (on the
12192          * last active line), the scanline counter will read vblank_start-1.
12193          *
12194          * On gen2 the scanline counter starts counting from 1 instead
12195          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12196          * to keep the value positive), instead of adding one.
12197          *
12198          * On HSW+ the behaviour of the scanline counter depends on the output
12199          * type. For DP ports it behaves like most other platforms, but on HDMI
12200          * there's an extra 1 line difference. So we need to add two instead of
12201          * one to the value.
12202          */
12203         if (IS_GEN2(dev_priv)) {
12204                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12205                 int vtotal;
12206
12207                 vtotal = adjusted_mode->crtc_vtotal;
12208                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12209                         vtotal /= 2;
12210
12211                 crtc->scanline_offset = vtotal - 1;
12212         } else if (HAS_DDI(dev_priv) &&
12213                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12214                 crtc->scanline_offset = 2;
12215         } else
12216                 crtc->scanline_offset = 1;
12217 }
12218
12219 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12220 {
12221         struct drm_device *dev = state->dev;
12222         struct drm_i915_private *dev_priv = to_i915(dev);
12223         struct drm_crtc *crtc;
12224         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12225         int i;
12226
12227         if (!dev_priv->display.crtc_compute_clock)
12228                 return;
12229
12230         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12231                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12232                 struct intel_shared_dpll *old_dpll =
12233                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12234
12235                 if (!needs_modeset(new_crtc_state))
12236                         continue;
12237
12238                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12239
12240                 if (!old_dpll)
12241                         continue;
12242
12243                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12244         }
12245 }
12246
12247 /*
12248  * This implements the workaround described in the "notes" section of the mode
12249  * set sequence documentation. When going from no pipes or single pipe to
12250  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12251  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12252  */
12253 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12254 {
12255         struct drm_crtc_state *crtc_state;
12256         struct intel_crtc *intel_crtc;
12257         struct drm_crtc *crtc;
12258         struct intel_crtc_state *first_crtc_state = NULL;
12259         struct intel_crtc_state *other_crtc_state = NULL;
12260         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12261         int i;
12262
12263         /* look at all crtc's that are going to be enabled in during modeset */
12264         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12265                 intel_crtc = to_intel_crtc(crtc);
12266
12267                 if (!crtc_state->active || !needs_modeset(crtc_state))
12268                         continue;
12269
12270                 if (first_crtc_state) {
12271                         other_crtc_state = to_intel_crtc_state(crtc_state);
12272                         break;
12273                 } else {
12274                         first_crtc_state = to_intel_crtc_state(crtc_state);
12275                         first_pipe = intel_crtc->pipe;
12276                 }
12277         }
12278
12279         /* No workaround needed? */
12280         if (!first_crtc_state)
12281                 return 0;
12282
12283         /* w/a possibly needed, check how many crtc's are already enabled. */
12284         for_each_intel_crtc(state->dev, intel_crtc) {
12285                 struct intel_crtc_state *pipe_config;
12286
12287                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12288                 if (IS_ERR(pipe_config))
12289                         return PTR_ERR(pipe_config);
12290
12291                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12292
12293                 if (!pipe_config->base.active ||
12294                     needs_modeset(&pipe_config->base))
12295                         continue;
12296
12297                 /* 2 or more enabled crtcs means no need for w/a */
12298                 if (enabled_pipe != INVALID_PIPE)
12299                         return 0;
12300
12301                 enabled_pipe = intel_crtc->pipe;
12302         }
12303
12304         if (enabled_pipe != INVALID_PIPE)
12305                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12306         else if (other_crtc_state)
12307                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12308
12309         return 0;
12310 }
12311
12312 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12313 {
12314         struct drm_crtc *crtc;
12315
12316         /* Add all pipes to the state */
12317         for_each_crtc(state->dev, crtc) {
12318                 struct drm_crtc_state *crtc_state;
12319
12320                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12321                 if (IS_ERR(crtc_state))
12322                         return PTR_ERR(crtc_state);
12323         }
12324
12325         return 0;
12326 }
12327
12328 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12329 {
12330         struct drm_crtc *crtc;
12331
12332         /*
12333          * Add all pipes to the state, and force
12334          * a modeset on all the active ones.
12335          */
12336         for_each_crtc(state->dev, crtc) {
12337                 struct drm_crtc_state *crtc_state;
12338                 int ret;
12339
12340                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12341                 if (IS_ERR(crtc_state))
12342                         return PTR_ERR(crtc_state);
12343
12344                 if (!crtc_state->active || needs_modeset(crtc_state))
12345                         continue;
12346
12347                 crtc_state->mode_changed = true;
12348
12349                 ret = drm_atomic_add_affected_connectors(state, crtc);
12350                 if (ret)
12351                         return ret;
12352
12353                 ret = drm_atomic_add_affected_planes(state, crtc);
12354                 if (ret)
12355                         return ret;
12356         }
12357
12358         return 0;
12359 }
12360
12361 static int intel_modeset_checks(struct drm_atomic_state *state)
12362 {
12363         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12364         struct drm_i915_private *dev_priv = to_i915(state->dev);
12365         struct drm_crtc *crtc;
12366         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12367         int ret = 0, i;
12368
12369         if (!check_digital_port_conflicts(state)) {
12370                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12371                 return -EINVAL;
12372         }
12373
12374         intel_state->modeset = true;
12375         intel_state->active_crtcs = dev_priv->active_crtcs;
12376         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12377         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12378
12379         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12380                 if (new_crtc_state->active)
12381                         intel_state->active_crtcs |= 1 << i;
12382                 else
12383                         intel_state->active_crtcs &= ~(1 << i);
12384
12385                 if (old_crtc_state->active != new_crtc_state->active)
12386                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12387         }
12388
12389         /*
12390          * See if the config requires any additional preparation, e.g.
12391          * to adjust global state with pipes off.  We need to do this
12392          * here so we can get the modeset_pipe updated config for the new
12393          * mode set on this crtc.  For other crtcs we need to use the
12394          * adjusted_mode bits in the crtc directly.
12395          */
12396         if (dev_priv->display.modeset_calc_cdclk) {
12397                 ret = dev_priv->display.modeset_calc_cdclk(state);
12398                 if (ret < 0)
12399                         return ret;
12400
12401                 /*
12402                  * Writes to dev_priv->cdclk.logical must protected by
12403                  * holding all the crtc locks, even if we don't end up
12404                  * touching the hardware
12405                  */
12406                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12407                                                &intel_state->cdclk.logical)) {
12408                         ret = intel_lock_all_pipes(state);
12409                         if (ret < 0)
12410                                 return ret;
12411                 }
12412
12413                 /* All pipes must be switched off while we change the cdclk. */
12414                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12415                                                &intel_state->cdclk.actual)) {
12416                         ret = intel_modeset_all_pipes(state);
12417                         if (ret < 0)
12418                                 return ret;
12419                 }
12420
12421                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12422                               intel_state->cdclk.logical.cdclk,
12423                               intel_state->cdclk.actual.cdclk);
12424         } else {
12425                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12426         }
12427
12428         intel_modeset_clear_plls(state);
12429
12430         if (IS_HASWELL(dev_priv))
12431                 return haswell_mode_set_planes_workaround(state);
12432
12433         return 0;
12434 }
12435
12436 /*
12437  * Handle calculation of various watermark data at the end of the atomic check
12438  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12439  * handlers to ensure that all derived state has been updated.
12440  */
12441 static int calc_watermark_data(struct drm_atomic_state *state)
12442 {
12443         struct drm_device *dev = state->dev;
12444         struct drm_i915_private *dev_priv = to_i915(dev);
12445
12446         /* Is there platform-specific watermark information to calculate? */
12447         if (dev_priv->display.compute_global_watermarks)
12448                 return dev_priv->display.compute_global_watermarks(state);
12449
12450         return 0;
12451 }
12452
12453 /**
12454  * intel_atomic_check - validate state object
12455  * @dev: drm device
12456  * @state: state to validate
12457  */
12458 static int intel_atomic_check(struct drm_device *dev,
12459                               struct drm_atomic_state *state)
12460 {
12461         struct drm_i915_private *dev_priv = to_i915(dev);
12462         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12463         struct drm_crtc *crtc;
12464         struct drm_crtc_state *old_crtc_state, *crtc_state;
12465         int ret, i;
12466         bool any_ms = false;
12467
12468         ret = drm_atomic_helper_check_modeset(dev, state);
12469         if (ret)
12470                 return ret;
12471
12472         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12473                 struct intel_crtc_state *pipe_config =
12474                         to_intel_crtc_state(crtc_state);
12475
12476                 /* Catch I915_MODE_FLAG_INHERITED */
12477                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12478                         crtc_state->mode_changed = true;
12479
12480                 if (!needs_modeset(crtc_state))
12481                         continue;
12482
12483                 if (!crtc_state->enable) {
12484                         any_ms = true;
12485                         continue;
12486                 }
12487
12488                 /* FIXME: For only active_changed we shouldn't need to do any
12489                  * state recomputation at all. */
12490
12491                 ret = drm_atomic_add_affected_connectors(state, crtc);
12492                 if (ret)
12493                         return ret;
12494
12495                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12496                 if (ret) {
12497                         intel_dump_pipe_config(to_intel_crtc(crtc),
12498                                                pipe_config, "[failed]");
12499                         return ret;
12500                 }
12501
12502                 if (i915.fastboot &&
12503                     intel_pipe_config_compare(dev_priv,
12504                                         to_intel_crtc_state(old_crtc_state),
12505                                         pipe_config, true)) {
12506                         crtc_state->mode_changed = false;
12507                         pipe_config->update_pipe = true;
12508                 }
12509
12510                 if (needs_modeset(crtc_state))
12511                         any_ms = true;
12512
12513                 ret = drm_atomic_add_affected_planes(state, crtc);
12514                 if (ret)
12515                         return ret;
12516
12517                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12518                                        needs_modeset(crtc_state) ?
12519                                        "[modeset]" : "[fastset]");
12520         }
12521
12522         if (any_ms) {
12523                 ret = intel_modeset_checks(state);
12524
12525                 if (ret)
12526                         return ret;
12527         } else {
12528                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12529         }
12530
12531         ret = drm_atomic_helper_check_planes(dev, state);
12532         if (ret)
12533                 return ret;
12534
12535         intel_fbc_choose_crtc(dev_priv, state);
12536         return calc_watermark_data(state);
12537 }
12538
12539 static int intel_atomic_prepare_commit(struct drm_device *dev,
12540                                        struct drm_atomic_state *state)
12541 {
12542         struct drm_i915_private *dev_priv = to_i915(dev);
12543         struct drm_crtc_state *crtc_state;
12544         struct drm_crtc *crtc;
12545         int i, ret;
12546
12547         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12548                 if (state->legacy_cursor_update)
12549                         continue;
12550
12551                 ret = intel_crtc_wait_for_pending_flips(crtc);
12552                 if (ret)
12553                         return ret;
12554
12555                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12556                         flush_workqueue(dev_priv->wq);
12557         }
12558
12559         ret = mutex_lock_interruptible(&dev->struct_mutex);
12560         if (ret)
12561                 return ret;
12562
12563         ret = drm_atomic_helper_prepare_planes(dev, state);
12564         mutex_unlock(&dev->struct_mutex);
12565
12566         return ret;
12567 }
12568
12569 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12570 {
12571         struct drm_device *dev = crtc->base.dev;
12572
12573         if (!dev->max_vblank_count)
12574                 return drm_accurate_vblank_count(&crtc->base);
12575
12576         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12577 }
12578
12579 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12580                                           struct drm_i915_private *dev_priv,
12581                                           unsigned crtc_mask)
12582 {
12583         unsigned last_vblank_count[I915_MAX_PIPES];
12584         enum pipe pipe;
12585         int ret;
12586
12587         if (!crtc_mask)
12588                 return;
12589
12590         for_each_pipe(dev_priv, pipe) {
12591                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12592                                                                   pipe);
12593
12594                 if (!((1 << pipe) & crtc_mask))
12595                         continue;
12596
12597                 ret = drm_crtc_vblank_get(&crtc->base);
12598                 if (WARN_ON(ret != 0)) {
12599                         crtc_mask &= ~(1 << pipe);
12600                         continue;
12601                 }
12602
12603                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12604         }
12605
12606         for_each_pipe(dev_priv, pipe) {
12607                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12608                                                                   pipe);
12609                 long lret;
12610
12611                 if (!((1 << pipe) & crtc_mask))
12612                         continue;
12613
12614                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12615                                 last_vblank_count[pipe] !=
12616                                         drm_crtc_vblank_count(&crtc->base),
12617                                 msecs_to_jiffies(50));
12618
12619                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12620
12621                 drm_crtc_vblank_put(&crtc->base);
12622         }
12623 }
12624
12625 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12626 {
12627         /* fb updated, need to unpin old fb */
12628         if (crtc_state->fb_changed)
12629                 return true;
12630
12631         /* wm changes, need vblank before final wm's */
12632         if (crtc_state->update_wm_post)
12633                 return true;
12634
12635         if (crtc_state->wm.need_postvbl_update)
12636                 return true;
12637
12638         return false;
12639 }
12640
12641 static void intel_update_crtc(struct drm_crtc *crtc,
12642                               struct drm_atomic_state *state,
12643                               struct drm_crtc_state *old_crtc_state,
12644                               struct drm_crtc_state *new_crtc_state,
12645                               unsigned int *crtc_vblank_mask)
12646 {
12647         struct drm_device *dev = crtc->dev;
12648         struct drm_i915_private *dev_priv = to_i915(dev);
12649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12650         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12651         bool modeset = needs_modeset(new_crtc_state);
12652
12653         if (modeset) {
12654                 update_scanline_offset(intel_crtc);
12655                 dev_priv->display.crtc_enable(pipe_config, state);
12656         } else {
12657                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12658                                        pipe_config);
12659         }
12660
12661         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12662                 intel_fbc_enable(
12663                     intel_crtc, pipe_config,
12664                     to_intel_plane_state(crtc->primary->state));
12665         }
12666
12667         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12668
12669         if (needs_vblank_wait(pipe_config))
12670                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12671 }
12672
12673 static void intel_update_crtcs(struct drm_atomic_state *state,
12674                                unsigned int *crtc_vblank_mask)
12675 {
12676         struct drm_crtc *crtc;
12677         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12678         int i;
12679
12680         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12681                 if (!new_crtc_state->active)
12682                         continue;
12683
12684                 intel_update_crtc(crtc, state, old_crtc_state,
12685                                   new_crtc_state, crtc_vblank_mask);
12686         }
12687 }
12688
12689 static void skl_update_crtcs(struct drm_atomic_state *state,
12690                              unsigned int *crtc_vblank_mask)
12691 {
12692         struct drm_i915_private *dev_priv = to_i915(state->dev);
12693         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12694         struct drm_crtc *crtc;
12695         struct intel_crtc *intel_crtc;
12696         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12697         struct intel_crtc_state *cstate;
12698         unsigned int updated = 0;
12699         bool progress;
12700         enum pipe pipe;
12701         int i;
12702
12703         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12704
12705         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12706                 /* ignore allocations for crtc's that have been turned off. */
12707                 if (new_crtc_state->active)
12708                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12709
12710         /*
12711          * Whenever the number of active pipes changes, we need to make sure we
12712          * update the pipes in the right order so that their ddb allocations
12713          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12714          * cause pipe underruns and other bad stuff.
12715          */
12716         do {
12717                 progress = false;
12718
12719                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12720                         bool vbl_wait = false;
12721                         unsigned int cmask = drm_crtc_mask(crtc);
12722
12723                         intel_crtc = to_intel_crtc(crtc);
12724                         cstate = to_intel_crtc_state(crtc->state);
12725                         pipe = intel_crtc->pipe;
12726
12727                         if (updated & cmask || !cstate->base.active)
12728                                 continue;
12729
12730                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12731                                 continue;
12732
12733                         updated |= cmask;
12734                         entries[i] = &cstate->wm.skl.ddb;
12735
12736                         /*
12737                          * If this is an already active pipe, it's DDB changed,
12738                          * and this isn't the last pipe that needs updating
12739                          * then we need to wait for a vblank to pass for the
12740                          * new ddb allocation to take effect.
12741                          */
12742                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12743                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12744                             !new_crtc_state->active_changed &&
12745                             intel_state->wm_results.dirty_pipes != updated)
12746                                 vbl_wait = true;
12747
12748                         intel_update_crtc(crtc, state, old_crtc_state,
12749                                           new_crtc_state, crtc_vblank_mask);
12750
12751                         if (vbl_wait)
12752                                 intel_wait_for_vblank(dev_priv, pipe);
12753
12754                         progress = true;
12755                 }
12756         } while (progress);
12757 }
12758
12759 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12760 {
12761         struct intel_atomic_state *state, *next;
12762         struct llist_node *freed;
12763
12764         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12765         llist_for_each_entry_safe(state, next, freed, freed)
12766                 drm_atomic_state_put(&state->base);
12767 }
12768
12769 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12770 {
12771         struct drm_i915_private *dev_priv =
12772                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12773
12774         intel_atomic_helper_free_state(dev_priv);
12775 }
12776
12777 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12778 {
12779         struct drm_device *dev = state->dev;
12780         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12781         struct drm_i915_private *dev_priv = to_i915(dev);
12782         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12783         struct drm_crtc *crtc;
12784         struct intel_crtc_state *intel_cstate;
12785         bool hw_check = intel_state->modeset;
12786         u64 put_domains[I915_MAX_PIPES] = {};
12787         unsigned crtc_vblank_mask = 0;
12788         int i;
12789
12790         drm_atomic_helper_wait_for_dependencies(state);
12791
12792         if (intel_state->modeset)
12793                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12794
12795         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12796                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12797
12798                 if (needs_modeset(new_crtc_state) ||
12799                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12800                         hw_check = true;
12801
12802                         put_domains[to_intel_crtc(crtc)->pipe] =
12803                                 modeset_get_crtc_power_domains(crtc,
12804                                         to_intel_crtc_state(new_crtc_state));
12805                 }
12806
12807                 if (!needs_modeset(new_crtc_state))
12808                         continue;
12809
12810                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12811                                        to_intel_crtc_state(new_crtc_state));
12812
12813                 if (old_crtc_state->active) {
12814                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12815                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12816                         intel_crtc->active = false;
12817                         intel_fbc_disable(intel_crtc);
12818                         intel_disable_shared_dpll(intel_crtc);
12819
12820                         /*
12821                          * Underruns don't always raise
12822                          * interrupts, so check manually.
12823                          */
12824                         intel_check_cpu_fifo_underruns(dev_priv);
12825                         intel_check_pch_fifo_underruns(dev_priv);
12826
12827                         if (!crtc->state->active) {
12828                                 /*
12829                                  * Make sure we don't call initial_watermarks
12830                                  * for ILK-style watermark updates.
12831                                  *
12832                                  * No clue what this is supposed to achieve.
12833                                  */
12834                                 if (INTEL_GEN(dev_priv) >= 9)
12835                                         dev_priv->display.initial_watermarks(intel_state,
12836                                                                              to_intel_crtc_state(crtc->state));
12837                         }
12838                 }
12839         }
12840
12841         /* Only after disabling all output pipelines that will be changed can we
12842          * update the the output configuration. */
12843         intel_modeset_update_crtc_state(state);
12844
12845         if (intel_state->modeset) {
12846                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12847
12848                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12849
12850                 /*
12851                  * SKL workaround: bspec recommends we disable the SAGV when we
12852                  * have more then one pipe enabled
12853                  */
12854                 if (!intel_can_enable_sagv(state))
12855                         intel_disable_sagv(dev_priv);
12856
12857                 intel_modeset_verify_disabled(dev, state);
12858         }
12859
12860         /* Complete the events for pipes that have now been disabled */
12861         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12862                 bool modeset = needs_modeset(new_crtc_state);
12863
12864                 /* Complete events for now disable pipes here. */
12865                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12866                         spin_lock_irq(&dev->event_lock);
12867                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12868                         spin_unlock_irq(&dev->event_lock);
12869
12870                         new_crtc_state->event = NULL;
12871                 }
12872         }
12873
12874         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12875         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12876
12877         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12878          * already, but still need the state for the delayed optimization. To
12879          * fix this:
12880          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12881          * - schedule that vblank worker _before_ calling hw_done
12882          * - at the start of commit_tail, cancel it _synchrously
12883          * - switch over to the vblank wait helper in the core after that since
12884          *   we don't need out special handling any more.
12885          */
12886         if (!state->legacy_cursor_update)
12887                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12888
12889         /*
12890          * Now that the vblank has passed, we can go ahead and program the
12891          * optimal watermarks on platforms that need two-step watermark
12892          * programming.
12893          *
12894          * TODO: Move this (and other cleanup) to an async worker eventually.
12895          */
12896         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12897                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12898
12899                 if (dev_priv->display.optimize_watermarks)
12900                         dev_priv->display.optimize_watermarks(intel_state,
12901                                                               intel_cstate);
12902         }
12903
12904         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12905                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12906
12907                 if (put_domains[i])
12908                         modeset_put_power_domains(dev_priv, put_domains[i]);
12909
12910                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12911         }
12912
12913         if (intel_state->modeset && intel_can_enable_sagv(state))
12914                 intel_enable_sagv(dev_priv);
12915
12916         drm_atomic_helper_commit_hw_done(state);
12917
12918         if (intel_state->modeset)
12919                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12920
12921         mutex_lock(&dev->struct_mutex);
12922         drm_atomic_helper_cleanup_planes(dev, state);
12923         mutex_unlock(&dev->struct_mutex);
12924
12925         drm_atomic_helper_commit_cleanup_done(state);
12926
12927         drm_atomic_state_put(state);
12928
12929         /* As one of the primary mmio accessors, KMS has a high likelihood
12930          * of triggering bugs in unclaimed access. After we finish
12931          * modesetting, see if an error has been flagged, and if so
12932          * enable debugging for the next modeset - and hope we catch
12933          * the culprit.
12934          *
12935          * XXX note that we assume display power is on at this point.
12936          * This might hold true now but we need to add pm helper to check
12937          * unclaimed only when the hardware is on, as atomic commits
12938          * can happen also when the device is completely off.
12939          */
12940         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12941
12942         intel_atomic_helper_free_state(dev_priv);
12943 }
12944
12945 static void intel_atomic_commit_work(struct work_struct *work)
12946 {
12947         struct drm_atomic_state *state =
12948                 container_of(work, struct drm_atomic_state, commit_work);
12949
12950         intel_atomic_commit_tail(state);
12951 }
12952
12953 static int __i915_sw_fence_call
12954 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12955                           enum i915_sw_fence_notify notify)
12956 {
12957         struct intel_atomic_state *state =
12958                 container_of(fence, struct intel_atomic_state, commit_ready);
12959
12960         switch (notify) {
12961         case FENCE_COMPLETE:
12962                 if (state->base.commit_work.func)
12963                         queue_work(system_unbound_wq, &state->base.commit_work);
12964                 break;
12965
12966         case FENCE_FREE:
12967                 {
12968                         struct intel_atomic_helper *helper =
12969                                 &to_i915(state->base.dev)->atomic_helper;
12970
12971                         if (llist_add(&state->freed, &helper->free_list))
12972                                 schedule_work(&helper->free_work);
12973                         break;
12974                 }
12975         }
12976
12977         return NOTIFY_DONE;
12978 }
12979
12980 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12981 {
12982         struct drm_plane_state *old_plane_state, *new_plane_state;
12983         struct drm_plane *plane;
12984         int i;
12985
12986         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12987                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12988                                   intel_fb_obj(new_plane_state->fb),
12989                                   to_intel_plane(plane)->frontbuffer_bit);
12990 }
12991
12992 /**
12993  * intel_atomic_commit - commit validated state object
12994  * @dev: DRM device
12995  * @state: the top-level driver state object
12996  * @nonblock: nonblocking commit
12997  *
12998  * This function commits a top-level state object that has been validated
12999  * with drm_atomic_helper_check().
13000  *
13001  * RETURNS
13002  * Zero for success or -errno.
13003  */
13004 static int intel_atomic_commit(struct drm_device *dev,
13005                                struct drm_atomic_state *state,
13006                                bool nonblock)
13007 {
13008         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13009         struct drm_i915_private *dev_priv = to_i915(dev);
13010         int ret = 0;
13011
13012         /*
13013          * The intel_legacy_cursor_update() fast path takes care
13014          * of avoiding the vblank waits for simple cursor
13015          * movement and flips. For cursor on/off and size changes,
13016          * we want to perform the vblank waits so that watermark
13017          * updates happen during the correct frames. Gen9+ have
13018          * double buffered watermarks and so shouldn't need this.
13019          */
13020         if (INTEL_GEN(dev_priv) < 9)
13021                 state->legacy_cursor_update = false;
13022
13023         ret = drm_atomic_helper_setup_commit(state, nonblock);
13024         if (ret)
13025                 return ret;
13026
13027         drm_atomic_state_get(state);
13028         i915_sw_fence_init(&intel_state->commit_ready,
13029                            intel_atomic_commit_ready);
13030
13031         ret = intel_atomic_prepare_commit(dev, state);
13032         if (ret) {
13033                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13034                 i915_sw_fence_commit(&intel_state->commit_ready);
13035                 return ret;
13036         }
13037
13038         drm_atomic_helper_swap_state(state, true);
13039         dev_priv->wm.distrust_bios_wm = false;
13040         intel_shared_dpll_swap_state(state);
13041         intel_atomic_track_fbs(state);
13042
13043         if (intel_state->modeset) {
13044                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13045                        sizeof(intel_state->min_pixclk));
13046                 dev_priv->active_crtcs = intel_state->active_crtcs;
13047                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13048                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13049         }
13050
13051         drm_atomic_state_get(state);
13052         INIT_WORK(&state->commit_work,
13053                   nonblock ? intel_atomic_commit_work : NULL);
13054
13055         i915_sw_fence_commit(&intel_state->commit_ready);
13056         if (!nonblock) {
13057                 i915_sw_fence_wait(&intel_state->commit_ready);
13058                 intel_atomic_commit_tail(state);
13059         }
13060
13061         return 0;
13062 }
13063
13064 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13065 {
13066         struct drm_device *dev = crtc->dev;
13067         struct drm_atomic_state *state;
13068         struct drm_crtc_state *crtc_state;
13069         int ret;
13070
13071         state = drm_atomic_state_alloc(dev);
13072         if (!state) {
13073                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13074                               crtc->base.id, crtc->name);
13075                 return;
13076         }
13077
13078         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13079
13080 retry:
13081         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13082         ret = PTR_ERR_OR_ZERO(crtc_state);
13083         if (!ret) {
13084                 if (!crtc_state->active)
13085                         goto out;
13086
13087                 crtc_state->mode_changed = true;
13088                 ret = drm_atomic_commit(state);
13089         }
13090
13091         if (ret == -EDEADLK) {
13092                 drm_atomic_state_clear(state);
13093                 drm_modeset_backoff(state->acquire_ctx);
13094                 goto retry;
13095         }
13096
13097 out:
13098         drm_atomic_state_put(state);
13099 }
13100
13101 /*
13102  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13103  *        drm_atomic_helper_legacy_gamma_set() directly.
13104  */
13105 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13106                                          u16 *red, u16 *green, u16 *blue,
13107                                          uint32_t size)
13108 {
13109         struct drm_device *dev = crtc->dev;
13110         struct drm_mode_config *config = &dev->mode_config;
13111         struct drm_crtc_state *state;
13112         int ret;
13113
13114         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13115         if (ret)
13116                 return ret;
13117
13118         /*
13119          * Make sure we update the legacy properties so this works when
13120          * atomic is not enabled.
13121          */
13122
13123         state = crtc->state;
13124
13125         drm_object_property_set_value(&crtc->base,
13126                                       config->degamma_lut_property,
13127                                       (state->degamma_lut) ?
13128                                       state->degamma_lut->base.id : 0);
13129
13130         drm_object_property_set_value(&crtc->base,
13131                                       config->ctm_property,
13132                                       (state->ctm) ?
13133                                       state->ctm->base.id : 0);
13134
13135         drm_object_property_set_value(&crtc->base,
13136                                       config->gamma_lut_property,
13137                                       (state->gamma_lut) ?
13138                                       state->gamma_lut->base.id : 0);
13139
13140         return 0;
13141 }
13142
13143 static const struct drm_crtc_funcs intel_crtc_funcs = {
13144         .gamma_set = intel_atomic_legacy_gamma_set,
13145         .set_config = drm_atomic_helper_set_config,
13146         .set_property = drm_atomic_helper_crtc_set_property,
13147         .destroy = intel_crtc_destroy,
13148         .page_flip = drm_atomic_helper_page_flip,
13149         .atomic_duplicate_state = intel_crtc_duplicate_state,
13150         .atomic_destroy_state = intel_crtc_destroy_state,
13151         .set_crc_source = intel_crtc_set_crc_source,
13152 };
13153
13154 /**
13155  * intel_prepare_plane_fb - Prepare fb for usage on plane
13156  * @plane: drm plane to prepare for
13157  * @fb: framebuffer to prepare for presentation
13158  *
13159  * Prepares a framebuffer for usage on a display plane.  Generally this
13160  * involves pinning the underlying object and updating the frontbuffer tracking
13161  * bits.  Some older platforms need special physical address handling for
13162  * cursor planes.
13163  *
13164  * Must be called with struct_mutex held.
13165  *
13166  * Returns 0 on success, negative error code on failure.
13167  */
13168 int
13169 intel_prepare_plane_fb(struct drm_plane *plane,
13170                        struct drm_plane_state *new_state)
13171 {
13172         struct intel_atomic_state *intel_state =
13173                 to_intel_atomic_state(new_state->state);
13174         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13175         struct drm_framebuffer *fb = new_state->fb;
13176         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13177         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13178         int ret;
13179
13180         if (obj) {
13181                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13182                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13183                         const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13184
13185                         ret = i915_gem_object_attach_phys(obj, align);
13186                         if (ret) {
13187                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13188                                 return ret;
13189                         }
13190                 } else {
13191                         struct i915_vma *vma;
13192
13193                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13194                         if (IS_ERR(vma)) {
13195                                 DRM_DEBUG_KMS("failed to pin object\n");
13196                                 return PTR_ERR(vma);
13197                         }
13198
13199                         to_intel_plane_state(new_state)->vma = vma;
13200                 }
13201         }
13202
13203         if (!obj && !old_obj)
13204                 return 0;
13205
13206         if (old_obj) {
13207                 struct drm_crtc_state *crtc_state =
13208                         drm_atomic_get_existing_crtc_state(new_state->state,
13209                                                            plane->state->crtc);
13210
13211                 /* Big Hammer, we also need to ensure that any pending
13212                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13213                  * current scanout is retired before unpinning the old
13214                  * framebuffer. Note that we rely on userspace rendering
13215                  * into the buffer attached to the pipe they are waiting
13216                  * on. If not, userspace generates a GPU hang with IPEHR
13217                  * point to the MI_WAIT_FOR_EVENT.
13218                  *
13219                  * This should only fail upon a hung GPU, in which case we
13220                  * can safely continue.
13221                  */
13222                 if (needs_modeset(crtc_state)) {
13223                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13224                                                               old_obj->resv, NULL,
13225                                                               false, 0,
13226                                                               GFP_KERNEL);
13227                         if (ret < 0)
13228                                 return ret;
13229                 }
13230         }
13231
13232         if (new_state->fence) { /* explicit fencing */
13233                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13234                                                     new_state->fence,
13235                                                     I915_FENCE_TIMEOUT,
13236                                                     GFP_KERNEL);
13237                 if (ret < 0)
13238                         return ret;
13239         }
13240
13241         if (!obj)
13242                 return 0;
13243
13244         if (!new_state->fence) { /* implicit fencing */
13245                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13246                                                       obj->resv, NULL,
13247                                                       false, I915_FENCE_TIMEOUT,
13248                                                       GFP_KERNEL);
13249                 if (ret < 0)
13250                         return ret;
13251
13252                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13253         }
13254
13255         return 0;
13256 }
13257
13258 /**
13259  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13260  * @plane: drm plane to clean up for
13261  * @fb: old framebuffer that was on plane
13262  *
13263  * Cleans up a framebuffer that has just been removed from a plane.
13264  *
13265  * Must be called with struct_mutex held.
13266  */
13267 void
13268 intel_cleanup_plane_fb(struct drm_plane *plane,
13269                        struct drm_plane_state *old_state)
13270 {
13271         struct i915_vma *vma;
13272
13273         /* Should only be called after a successful intel_prepare_plane_fb()! */
13274         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13275         if (vma)
13276                 intel_unpin_fb_vma(vma);
13277 }
13278
13279 int
13280 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13281 {
13282         struct drm_i915_private *dev_priv;
13283         int max_scale;
13284         int crtc_clock, max_dotclk;
13285
13286         if (!intel_crtc || !crtc_state->base.enable)
13287                 return DRM_PLANE_HELPER_NO_SCALING;
13288
13289         dev_priv = to_i915(intel_crtc->base.dev);
13290
13291         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13292         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13293
13294         if (IS_GEMINILAKE(dev_priv))
13295                 max_dotclk *= 2;
13296
13297         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13298                 return DRM_PLANE_HELPER_NO_SCALING;
13299
13300         /*
13301          * skl max scale is lower of:
13302          *    close to 3 but not 3, -1 is for that purpose
13303          *            or
13304          *    cdclk/crtc_clock
13305          */
13306         max_scale = min((1 << 16) * 3 - 1,
13307                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13308
13309         return max_scale;
13310 }
13311
13312 static int
13313 intel_check_primary_plane(struct drm_plane *plane,
13314                           struct intel_crtc_state *crtc_state,
13315                           struct intel_plane_state *state)
13316 {
13317         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13318         struct drm_crtc *crtc = state->base.crtc;
13319         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13320         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13321         bool can_position = false;
13322         int ret;
13323
13324         if (INTEL_GEN(dev_priv) >= 9) {
13325                 /* use scaler when colorkey is not required */
13326                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13327                         min_scale = 1;
13328                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13329                 }
13330                 can_position = true;
13331         }
13332
13333         ret = drm_plane_helper_check_state(&state->base,
13334                                            &state->clip,
13335                                            min_scale, max_scale,
13336                                            can_position, true);
13337         if (ret)
13338                 return ret;
13339
13340         if (!state->base.fb)
13341                 return 0;
13342
13343         if (INTEL_GEN(dev_priv) >= 9) {
13344                 ret = skl_check_plane_surface(state);
13345                 if (ret)
13346                         return ret;
13347         }
13348
13349         return 0;
13350 }
13351
13352 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13353                                     struct drm_crtc_state *old_crtc_state)
13354 {
13355         struct drm_device *dev = crtc->dev;
13356         struct drm_i915_private *dev_priv = to_i915(dev);
13357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13358         struct intel_crtc_state *intel_cstate =
13359                 to_intel_crtc_state(crtc->state);
13360         struct intel_crtc_state *old_intel_cstate =
13361                 to_intel_crtc_state(old_crtc_state);
13362         struct intel_atomic_state *old_intel_state =
13363                 to_intel_atomic_state(old_crtc_state->state);
13364         bool modeset = needs_modeset(crtc->state);
13365
13366         if (!modeset &&
13367             (intel_cstate->base.color_mgmt_changed ||
13368              intel_cstate->update_pipe)) {
13369                 intel_color_set_csc(crtc->state);
13370                 intel_color_load_luts(crtc->state);
13371         }
13372
13373         /* Perform vblank evasion around commit operation */
13374         intel_pipe_update_start(intel_crtc);
13375
13376         if (modeset)
13377                 goto out;
13378
13379         if (intel_cstate->update_pipe)
13380                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13381         else if (INTEL_GEN(dev_priv) >= 9)
13382                 skl_detach_scalers(intel_crtc);
13383
13384 out:
13385         if (dev_priv->display.atomic_update_watermarks)
13386                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13387                                                            intel_cstate);
13388 }
13389
13390 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13391                                      struct drm_crtc_state *old_crtc_state)
13392 {
13393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13394
13395         intel_pipe_update_end(intel_crtc, NULL);
13396 }
13397
13398 /**
13399  * intel_plane_destroy - destroy a plane
13400  * @plane: plane to destroy
13401  *
13402  * Common destruction function for all types of planes (primary, cursor,
13403  * sprite).
13404  */
13405 void intel_plane_destroy(struct drm_plane *plane)
13406 {
13407         drm_plane_cleanup(plane);
13408         kfree(to_intel_plane(plane));
13409 }
13410
13411 const struct drm_plane_funcs intel_plane_funcs = {
13412         .update_plane = drm_atomic_helper_update_plane,
13413         .disable_plane = drm_atomic_helper_disable_plane,
13414         .destroy = intel_plane_destroy,
13415         .set_property = drm_atomic_helper_plane_set_property,
13416         .atomic_get_property = intel_plane_atomic_get_property,
13417         .atomic_set_property = intel_plane_atomic_set_property,
13418         .atomic_duplicate_state = intel_plane_duplicate_state,
13419         .atomic_destroy_state = intel_plane_destroy_state,
13420 };
13421
13422 static int
13423 intel_legacy_cursor_update(struct drm_plane *plane,
13424                            struct drm_crtc *crtc,
13425                            struct drm_framebuffer *fb,
13426                            int crtc_x, int crtc_y,
13427                            unsigned int crtc_w, unsigned int crtc_h,
13428                            uint32_t src_x, uint32_t src_y,
13429                            uint32_t src_w, uint32_t src_h)
13430 {
13431         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13432         int ret;
13433         struct drm_plane_state *old_plane_state, *new_plane_state;
13434         struct intel_plane *intel_plane = to_intel_plane(plane);
13435         struct drm_framebuffer *old_fb;
13436         struct drm_crtc_state *crtc_state = crtc->state;
13437         struct i915_vma *old_vma;
13438
13439         /*
13440          * When crtc is inactive or there is a modeset pending,
13441          * wait for it to complete in the slowpath
13442          */
13443         if (!crtc_state->active || needs_modeset(crtc_state) ||
13444             to_intel_crtc_state(crtc_state)->update_pipe)
13445                 goto slow;
13446
13447         old_plane_state = plane->state;
13448
13449         /*
13450          * If any parameters change that may affect watermarks,
13451          * take the slowpath. Only changing fb or position should be
13452          * in the fastpath.
13453          */
13454         if (old_plane_state->crtc != crtc ||
13455             old_plane_state->src_w != src_w ||
13456             old_plane_state->src_h != src_h ||
13457             old_plane_state->crtc_w != crtc_w ||
13458             old_plane_state->crtc_h != crtc_h ||
13459             !old_plane_state->fb != !fb)
13460                 goto slow;
13461
13462         new_plane_state = intel_plane_duplicate_state(plane);
13463         if (!new_plane_state)
13464                 return -ENOMEM;
13465
13466         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13467
13468         new_plane_state->src_x = src_x;
13469         new_plane_state->src_y = src_y;
13470         new_plane_state->src_w = src_w;
13471         new_plane_state->src_h = src_h;
13472         new_plane_state->crtc_x = crtc_x;
13473         new_plane_state->crtc_y = crtc_y;
13474         new_plane_state->crtc_w = crtc_w;
13475         new_plane_state->crtc_h = crtc_h;
13476
13477         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13478                                                   to_intel_plane_state(new_plane_state));
13479         if (ret)
13480                 goto out_free;
13481
13482         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13483         if (ret)
13484                 goto out_free;
13485
13486         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13487                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13488
13489                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13490                 if (ret) {
13491                         DRM_DEBUG_KMS("failed to attach phys object\n");
13492                         goto out_unlock;
13493                 }
13494         } else {
13495                 struct i915_vma *vma;
13496
13497                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13498                 if (IS_ERR(vma)) {
13499                         DRM_DEBUG_KMS("failed to pin object\n");
13500
13501                         ret = PTR_ERR(vma);
13502                         goto out_unlock;
13503                 }
13504
13505                 to_intel_plane_state(new_plane_state)->vma = vma;
13506         }
13507
13508         old_fb = old_plane_state->fb;
13509         old_vma = to_intel_plane_state(old_plane_state)->vma;
13510
13511         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13512                           intel_plane->frontbuffer_bit);
13513
13514         /* Swap plane state */
13515         new_plane_state->fence = old_plane_state->fence;
13516         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13517         new_plane_state->fence = NULL;
13518         new_plane_state->fb = old_fb;
13519         to_intel_plane_state(new_plane_state)->vma = old_vma;
13520
13521         if (plane->state->visible) {
13522                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13523                 intel_plane->update_plane(plane,
13524                                           to_intel_crtc_state(crtc->state),
13525                                           to_intel_plane_state(plane->state));
13526         } else {
13527                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13528                 intel_plane->disable_plane(plane, crtc);
13529         }
13530
13531         intel_cleanup_plane_fb(plane, new_plane_state);
13532
13533 out_unlock:
13534         mutex_unlock(&dev_priv->drm.struct_mutex);
13535 out_free:
13536         intel_plane_destroy_state(plane, new_plane_state);
13537         return ret;
13538
13539 slow:
13540         return drm_atomic_helper_update_plane(plane, crtc, fb,
13541                                               crtc_x, crtc_y, crtc_w, crtc_h,
13542                                               src_x, src_y, src_w, src_h);
13543 }
13544
13545 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13546         .update_plane = intel_legacy_cursor_update,
13547         .disable_plane = drm_atomic_helper_disable_plane,
13548         .destroy = intel_plane_destroy,
13549         .set_property = drm_atomic_helper_plane_set_property,
13550         .atomic_get_property = intel_plane_atomic_get_property,
13551         .atomic_set_property = intel_plane_atomic_set_property,
13552         .atomic_duplicate_state = intel_plane_duplicate_state,
13553         .atomic_destroy_state = intel_plane_destroy_state,
13554 };
13555
13556 static struct intel_plane *
13557 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13558 {
13559         struct intel_plane *primary = NULL;
13560         struct intel_plane_state *state = NULL;
13561         const uint32_t *intel_primary_formats;
13562         unsigned int supported_rotations;
13563         unsigned int num_formats;
13564         int ret;
13565
13566         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13567         if (!primary) {
13568                 ret = -ENOMEM;
13569                 goto fail;
13570         }
13571
13572         state = intel_create_plane_state(&primary->base);
13573         if (!state) {
13574                 ret = -ENOMEM;
13575                 goto fail;
13576         }
13577
13578         primary->base.state = &state->base;
13579
13580         primary->can_scale = false;
13581         primary->max_downscale = 1;
13582         if (INTEL_GEN(dev_priv) >= 9) {
13583                 primary->can_scale = true;
13584                 state->scaler_id = -1;
13585         }
13586         primary->pipe = pipe;
13587         /*
13588          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13589          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13590          */
13591         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13592                 primary->plane = (enum plane) !pipe;
13593         else
13594                 primary->plane = (enum plane) pipe;
13595         primary->id = PLANE_PRIMARY;
13596         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13597         primary->check_plane = intel_check_primary_plane;
13598
13599         if (INTEL_GEN(dev_priv) >= 9) {
13600                 intel_primary_formats = skl_primary_formats;
13601                 num_formats = ARRAY_SIZE(skl_primary_formats);
13602
13603                 primary->update_plane = skylake_update_primary_plane;
13604                 primary->disable_plane = skylake_disable_primary_plane;
13605         } else if (HAS_PCH_SPLIT(dev_priv)) {
13606                 intel_primary_formats = i965_primary_formats;
13607                 num_formats = ARRAY_SIZE(i965_primary_formats);
13608
13609                 primary->update_plane = ironlake_update_primary_plane;
13610                 primary->disable_plane = i9xx_disable_primary_plane;
13611         } else if (INTEL_GEN(dev_priv) >= 4) {
13612                 intel_primary_formats = i965_primary_formats;
13613                 num_formats = ARRAY_SIZE(i965_primary_formats);
13614
13615                 primary->update_plane = i9xx_update_primary_plane;
13616                 primary->disable_plane = i9xx_disable_primary_plane;
13617         } else {
13618                 intel_primary_formats = i8xx_primary_formats;
13619                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13620
13621                 primary->update_plane = i9xx_update_primary_plane;
13622                 primary->disable_plane = i9xx_disable_primary_plane;
13623         }
13624
13625         if (INTEL_GEN(dev_priv) >= 9)
13626                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13627                                                0, &intel_plane_funcs,
13628                                                intel_primary_formats, num_formats,
13629                                                DRM_PLANE_TYPE_PRIMARY,
13630                                                "plane 1%c", pipe_name(pipe));
13631         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13632                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13633                                                0, &intel_plane_funcs,
13634                                                intel_primary_formats, num_formats,
13635                                                DRM_PLANE_TYPE_PRIMARY,
13636                                                "primary %c", pipe_name(pipe));
13637         else
13638                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13639                                                0, &intel_plane_funcs,
13640                                                intel_primary_formats, num_formats,
13641                                                DRM_PLANE_TYPE_PRIMARY,
13642                                                "plane %c", plane_name(primary->plane));
13643         if (ret)
13644                 goto fail;
13645
13646         if (INTEL_GEN(dev_priv) >= 9) {
13647                 supported_rotations =
13648                         DRM_ROTATE_0 | DRM_ROTATE_90 |
13649                         DRM_ROTATE_180 | DRM_ROTATE_270;
13650         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13651                 supported_rotations =
13652                         DRM_ROTATE_0 | DRM_ROTATE_180 |
13653                         DRM_REFLECT_X;
13654         } else if (INTEL_GEN(dev_priv) >= 4) {
13655                 supported_rotations =
13656                         DRM_ROTATE_0 | DRM_ROTATE_180;
13657         } else {
13658                 supported_rotations = DRM_ROTATE_0;
13659         }
13660
13661         if (INTEL_GEN(dev_priv) >= 4)
13662                 drm_plane_create_rotation_property(&primary->base,
13663                                                    DRM_ROTATE_0,
13664                                                    supported_rotations);
13665
13666         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13667
13668         return primary;
13669
13670 fail:
13671         kfree(state);
13672         kfree(primary);
13673
13674         return ERR_PTR(ret);
13675 }
13676
13677 static int
13678 intel_check_cursor_plane(struct drm_plane *plane,
13679                          struct intel_crtc_state *crtc_state,
13680                          struct intel_plane_state *state)
13681 {
13682         struct drm_framebuffer *fb = state->base.fb;
13683         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13684         enum pipe pipe = to_intel_plane(plane)->pipe;
13685         unsigned stride;
13686         int ret;
13687
13688         ret = drm_plane_helper_check_state(&state->base,
13689                                            &state->clip,
13690                                            DRM_PLANE_HELPER_NO_SCALING,
13691                                            DRM_PLANE_HELPER_NO_SCALING,
13692                                            true, true);
13693         if (ret)
13694                 return ret;
13695
13696         /* if we want to turn off the cursor ignore width and height */
13697         if (!obj)
13698                 return 0;
13699
13700         /* Check for which cursor types we support */
13701         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
13702                             state->base.crtc_h)) {
13703                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13704                           state->base.crtc_w, state->base.crtc_h);
13705                 return -EINVAL;
13706         }
13707
13708         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13709         if (obj->base.size < stride * state->base.crtc_h) {
13710                 DRM_DEBUG_KMS("buffer is too small\n");
13711                 return -ENOMEM;
13712         }
13713
13714         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
13715                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13716                 return -EINVAL;
13717         }
13718
13719         /*
13720          * There's something wrong with the cursor on CHV pipe C.
13721          * If it straddles the left edge of the screen then
13722          * moving it away from the edge or disabling it often
13723          * results in a pipe underrun, and often that can lead to
13724          * dead pipe (constant underrun reported, and it scans
13725          * out just a solid color). To recover from that, the
13726          * display power well must be turned off and on again.
13727          * Refuse the put the cursor into that compromised position.
13728          */
13729         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
13730             state->base.visible && state->base.crtc_x < 0) {
13731                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13732                 return -EINVAL;
13733         }
13734
13735         return 0;
13736 }
13737
13738 static void
13739 intel_disable_cursor_plane(struct drm_plane *plane,
13740                            struct drm_crtc *crtc)
13741 {
13742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13743
13744         intel_crtc->cursor_addr = 0;
13745         intel_crtc_update_cursor(crtc, NULL);
13746 }
13747
13748 static void
13749 intel_update_cursor_plane(struct drm_plane *plane,
13750                           const struct intel_crtc_state *crtc_state,
13751                           const struct intel_plane_state *state)
13752 {
13753         struct drm_crtc *crtc = crtc_state->base.crtc;
13754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13755         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13756         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13757         uint32_t addr;
13758
13759         if (!obj)
13760                 addr = 0;
13761         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13762                 addr = intel_plane_ggtt_offset(state);
13763         else
13764                 addr = obj->phys_handle->busaddr;
13765
13766         intel_crtc->cursor_addr = addr;
13767         intel_crtc_update_cursor(crtc, state);
13768 }
13769
13770 static struct intel_plane *
13771 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13772 {
13773         struct intel_plane *cursor = NULL;
13774         struct intel_plane_state *state = NULL;
13775         int ret;
13776
13777         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13778         if (!cursor) {
13779                 ret = -ENOMEM;
13780                 goto fail;
13781         }
13782
13783         state = intel_create_plane_state(&cursor->base);
13784         if (!state) {
13785                 ret = -ENOMEM;
13786                 goto fail;
13787         }
13788
13789         cursor->base.state = &state->base;
13790
13791         cursor->can_scale = false;
13792         cursor->max_downscale = 1;
13793         cursor->pipe = pipe;
13794         cursor->plane = pipe;
13795         cursor->id = PLANE_CURSOR;
13796         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13797         cursor->check_plane = intel_check_cursor_plane;
13798         cursor->update_plane = intel_update_cursor_plane;
13799         cursor->disable_plane = intel_disable_cursor_plane;
13800
13801         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13802                                        0, &intel_cursor_plane_funcs,
13803                                        intel_cursor_formats,
13804                                        ARRAY_SIZE(intel_cursor_formats),
13805                                        DRM_PLANE_TYPE_CURSOR,
13806                                        "cursor %c", pipe_name(pipe));
13807         if (ret)
13808                 goto fail;
13809
13810         if (INTEL_GEN(dev_priv) >= 4)
13811                 drm_plane_create_rotation_property(&cursor->base,
13812                                                    DRM_ROTATE_0,
13813                                                    DRM_ROTATE_0 |
13814                                                    DRM_ROTATE_180);
13815
13816         if (INTEL_GEN(dev_priv) >= 9)
13817                 state->scaler_id = -1;
13818
13819         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13820
13821         return cursor;
13822
13823 fail:
13824         kfree(state);
13825         kfree(cursor);
13826
13827         return ERR_PTR(ret);
13828 }
13829
13830 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13831                                     struct intel_crtc_state *crtc_state)
13832 {
13833         struct intel_crtc_scaler_state *scaler_state =
13834                 &crtc_state->scaler_state;
13835         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13836         int i;
13837
13838         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13839         if (!crtc->num_scalers)
13840                 return;
13841
13842         for (i = 0; i < crtc->num_scalers; i++) {
13843                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13844
13845                 scaler->in_use = 0;
13846                 scaler->mode = PS_SCALER_MODE_DYN;
13847         }
13848
13849         scaler_state->scaler_id = -1;
13850 }
13851
13852 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13853 {
13854         struct intel_crtc *intel_crtc;
13855         struct intel_crtc_state *crtc_state = NULL;
13856         struct intel_plane *primary = NULL;
13857         struct intel_plane *cursor = NULL;
13858         int sprite, ret;
13859
13860         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13861         if (!intel_crtc)
13862                 return -ENOMEM;
13863
13864         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13865         if (!crtc_state) {
13866                 ret = -ENOMEM;
13867                 goto fail;
13868         }
13869         intel_crtc->config = crtc_state;
13870         intel_crtc->base.state = &crtc_state->base;
13871         crtc_state->base.crtc = &intel_crtc->base;
13872
13873         primary = intel_primary_plane_create(dev_priv, pipe);
13874         if (IS_ERR(primary)) {
13875                 ret = PTR_ERR(primary);
13876                 goto fail;
13877         }
13878         intel_crtc->plane_ids_mask |= BIT(primary->id);
13879
13880         for_each_sprite(dev_priv, pipe, sprite) {
13881                 struct intel_plane *plane;
13882
13883                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13884                 if (IS_ERR(plane)) {
13885                         ret = PTR_ERR(plane);
13886                         goto fail;
13887                 }
13888                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13889         }
13890
13891         cursor = intel_cursor_plane_create(dev_priv, pipe);
13892         if (IS_ERR(cursor)) {
13893                 ret = PTR_ERR(cursor);
13894                 goto fail;
13895         }
13896         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13897
13898         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13899                                         &primary->base, &cursor->base,
13900                                         &intel_crtc_funcs,
13901                                         "pipe %c", pipe_name(pipe));
13902         if (ret)
13903                 goto fail;
13904
13905         intel_crtc->pipe = pipe;
13906         intel_crtc->plane = primary->plane;
13907
13908         intel_crtc->cursor_base = ~0;
13909         intel_crtc->cursor_cntl = ~0;
13910         intel_crtc->cursor_size = ~0;
13911
13912         /* initialize shared scalers */
13913         intel_crtc_init_scalers(intel_crtc, crtc_state);
13914
13915         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13916                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13917         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13918         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13919
13920         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13921
13922         intel_color_init(&intel_crtc->base);
13923
13924         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13925
13926         return 0;
13927
13928 fail:
13929         /*
13930          * drm_mode_config_cleanup() will free up any
13931          * crtcs/planes already initialized.
13932          */
13933         kfree(crtc_state);
13934         kfree(intel_crtc);
13935
13936         return ret;
13937 }
13938
13939 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13940 {
13941         struct drm_device *dev = connector->base.dev;
13942
13943         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13944
13945         if (!connector->base.state->crtc)
13946                 return INVALID_PIPE;
13947
13948         return to_intel_crtc(connector->base.state->crtc)->pipe;
13949 }
13950
13951 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13952                                 struct drm_file *file)
13953 {
13954         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13955         struct drm_crtc *drmmode_crtc;
13956         struct intel_crtc *crtc;
13957
13958         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13959         if (!drmmode_crtc)
13960                 return -ENOENT;
13961
13962         crtc = to_intel_crtc(drmmode_crtc);
13963         pipe_from_crtc_id->pipe = crtc->pipe;
13964
13965         return 0;
13966 }
13967
13968 static int intel_encoder_clones(struct intel_encoder *encoder)
13969 {
13970         struct drm_device *dev = encoder->base.dev;
13971         struct intel_encoder *source_encoder;
13972         int index_mask = 0;
13973         int entry = 0;
13974
13975         for_each_intel_encoder(dev, source_encoder) {
13976                 if (encoders_cloneable(encoder, source_encoder))
13977                         index_mask |= (1 << entry);
13978
13979                 entry++;
13980         }
13981
13982         return index_mask;
13983 }
13984
13985 static bool has_edp_a(struct drm_i915_private *dev_priv)
13986 {
13987         if (!IS_MOBILE(dev_priv))
13988                 return false;
13989
13990         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13991                 return false;
13992
13993         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13994                 return false;
13995
13996         return true;
13997 }
13998
13999 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14000 {
14001         if (INTEL_GEN(dev_priv) >= 9)
14002                 return false;
14003
14004         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14005                 return false;
14006
14007         if (IS_CHERRYVIEW(dev_priv))
14008                 return false;
14009
14010         if (HAS_PCH_LPT_H(dev_priv) &&
14011             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14012                 return false;
14013
14014         /* DDI E can't be used if DDI A requires 4 lanes */
14015         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14016                 return false;
14017
14018         if (!dev_priv->vbt.int_crt_support)
14019                 return false;
14020
14021         return true;
14022 }
14023
14024 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14025 {
14026         int pps_num;
14027         int pps_idx;
14028
14029         if (HAS_DDI(dev_priv))
14030                 return;
14031         /*
14032          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14033          * everywhere where registers can be write protected.
14034          */
14035         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14036                 pps_num = 2;
14037         else
14038                 pps_num = 1;
14039
14040         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14041                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14042
14043                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14044                 I915_WRITE(PP_CONTROL(pps_idx), val);
14045         }
14046 }
14047
14048 static void intel_pps_init(struct drm_i915_private *dev_priv)
14049 {
14050         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14051                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14052         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14053                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14054         else
14055                 dev_priv->pps_mmio_base = PPS_BASE;
14056
14057         intel_pps_unlock_regs_wa(dev_priv);
14058 }
14059
14060 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14061 {
14062         struct intel_encoder *encoder;
14063         bool dpd_is_edp = false;
14064
14065         intel_pps_init(dev_priv);
14066
14067         /*
14068          * intel_edp_init_connector() depends on this completing first, to
14069          * prevent the registeration of both eDP and LVDS and the incorrect
14070          * sharing of the PPS.
14071          */
14072         intel_lvds_init(dev_priv);
14073
14074         if (intel_crt_present(dev_priv))
14075                 intel_crt_init(dev_priv);
14076
14077         if (IS_GEN9_LP(dev_priv)) {
14078                 /*
14079                  * FIXME: Broxton doesn't support port detection via the
14080                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14081                  * detect the ports.
14082                  */
14083                 intel_ddi_init(dev_priv, PORT_A);
14084                 intel_ddi_init(dev_priv, PORT_B);
14085                 intel_ddi_init(dev_priv, PORT_C);
14086
14087                 intel_dsi_init(dev_priv);
14088         } else if (HAS_DDI(dev_priv)) {
14089                 int found;
14090
14091                 /*
14092                  * Haswell uses DDI functions to detect digital outputs.
14093                  * On SKL pre-D0 the strap isn't connected, so we assume
14094                  * it's there.
14095                  */
14096                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14097                 /* WaIgnoreDDIAStrap: skl */
14098                 if (found || IS_GEN9_BC(dev_priv))
14099                         intel_ddi_init(dev_priv, PORT_A);
14100
14101                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14102                  * register */
14103                 found = I915_READ(SFUSE_STRAP);
14104
14105                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14106                         intel_ddi_init(dev_priv, PORT_B);
14107                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14108                         intel_ddi_init(dev_priv, PORT_C);
14109                 if (found & SFUSE_STRAP_DDID_DETECTED)
14110                         intel_ddi_init(dev_priv, PORT_D);
14111                 /*
14112                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14113                  */
14114                 if (IS_GEN9_BC(dev_priv) &&
14115                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14116                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14117                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14118                         intel_ddi_init(dev_priv, PORT_E);
14119
14120         } else if (HAS_PCH_SPLIT(dev_priv)) {
14121                 int found;
14122                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14123
14124                 if (has_edp_a(dev_priv))
14125                         intel_dp_init(dev_priv, DP_A, PORT_A);
14126
14127                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14128                         /* PCH SDVOB multiplex with HDMIB */
14129                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14130                         if (!found)
14131                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14132                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14133                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14134                 }
14135
14136                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14137                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14138
14139                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14140                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14141
14142                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14143                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14144
14145                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14146                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14147         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14148                 bool has_edp, has_port;
14149
14150                 /*
14151                  * The DP_DETECTED bit is the latched state of the DDC
14152                  * SDA pin at boot. However since eDP doesn't require DDC
14153                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14154                  * eDP ports may have been muxed to an alternate function.
14155                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14156                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14157                  * detect eDP ports.
14158                  *
14159                  * Sadly the straps seem to be missing sometimes even for HDMI
14160                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14161                  * and VBT for the presence of the port. Additionally we can't
14162                  * trust the port type the VBT declares as we've seen at least
14163                  * HDMI ports that the VBT claim are DP or eDP.
14164                  */
14165                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14166                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14167                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14168                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14169                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14170                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14171
14172                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14173                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14174                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14175                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14176                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14177                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14178
14179                 if (IS_CHERRYVIEW(dev_priv)) {
14180                         /*
14181                          * eDP not supported on port D,
14182                          * so no need to worry about it
14183                          */
14184                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14185                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14186                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14187                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14188                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14189                 }
14190
14191                 intel_dsi_init(dev_priv);
14192         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14193                 bool found = false;
14194
14195                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14196                         DRM_DEBUG_KMS("probing SDVOB\n");
14197                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14198                         if (!found && IS_G4X(dev_priv)) {
14199                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14200                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14201                         }
14202
14203                         if (!found && IS_G4X(dev_priv))
14204                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14205                 }
14206
14207                 /* Before G4X SDVOC doesn't have its own detect register */
14208
14209                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14210                         DRM_DEBUG_KMS("probing SDVOC\n");
14211                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14212                 }
14213
14214                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14215
14216                         if (IS_G4X(dev_priv)) {
14217                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14218                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14219                         }
14220                         if (IS_G4X(dev_priv))
14221                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14222                 }
14223
14224                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14225                         intel_dp_init(dev_priv, DP_D, PORT_D);
14226         } else if (IS_GEN2(dev_priv))
14227                 intel_dvo_init(dev_priv);
14228
14229         if (SUPPORTS_TV(dev_priv))
14230                 intel_tv_init(dev_priv);
14231
14232         intel_psr_init(dev_priv);
14233
14234         for_each_intel_encoder(&dev_priv->drm, encoder) {
14235                 encoder->base.possible_crtcs = encoder->crtc_mask;
14236                 encoder->base.possible_clones =
14237                         intel_encoder_clones(encoder);
14238         }
14239
14240         intel_init_pch_refclk(dev_priv);
14241
14242         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14243 }
14244
14245 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14246 {
14247         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14248
14249         drm_framebuffer_cleanup(fb);
14250
14251         i915_gem_object_lock(intel_fb->obj);
14252         WARN_ON(!intel_fb->obj->framebuffer_references--);
14253         i915_gem_object_unlock(intel_fb->obj);
14254
14255         i915_gem_object_put(intel_fb->obj);
14256
14257         kfree(intel_fb);
14258 }
14259
14260 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14261                                                 struct drm_file *file,
14262                                                 unsigned int *handle)
14263 {
14264         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14265         struct drm_i915_gem_object *obj = intel_fb->obj;
14266
14267         if (obj->userptr.mm) {
14268                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14269                 return -EINVAL;
14270         }
14271
14272         return drm_gem_handle_create(file, &obj->base, handle);
14273 }
14274
14275 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14276                                         struct drm_file *file,
14277                                         unsigned flags, unsigned color,
14278                                         struct drm_clip_rect *clips,
14279                                         unsigned num_clips)
14280 {
14281         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14282
14283         i915_gem_object_flush_if_display(obj);
14284         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14285
14286         return 0;
14287 }
14288
14289 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14290         .destroy = intel_user_framebuffer_destroy,
14291         .create_handle = intel_user_framebuffer_create_handle,
14292         .dirty = intel_user_framebuffer_dirty,
14293 };
14294
14295 static
14296 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14297                          uint64_t fb_modifier, uint32_t pixel_format)
14298 {
14299         u32 gen = INTEL_GEN(dev_priv);
14300
14301         if (gen >= 9) {
14302                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14303
14304                 /* "The stride in bytes must not exceed the of the size of 8K
14305                  *  pixels and 32K bytes."
14306                  */
14307                 return min(8192 * cpp, 32768);
14308         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14309                 return 32*1024;
14310         } else if (gen >= 4) {
14311                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14312                         return 16*1024;
14313                 else
14314                         return 32*1024;
14315         } else if (gen >= 3) {
14316                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14317                         return 8*1024;
14318                 else
14319                         return 16*1024;
14320         } else {
14321                 /* XXX DSPC is limited to 4k tiled */
14322                 return 8*1024;
14323         }
14324 }
14325
14326 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14327                                   struct drm_i915_gem_object *obj,
14328                                   struct drm_mode_fb_cmd2 *mode_cmd)
14329 {
14330         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14331         struct drm_format_name_buf format_name;
14332         u32 pitch_limit, stride_alignment;
14333         unsigned int tiling, stride;
14334         int ret = -EINVAL;
14335
14336         i915_gem_object_lock(obj);
14337         obj->framebuffer_references++;
14338         tiling = i915_gem_object_get_tiling(obj);
14339         stride = i915_gem_object_get_stride(obj);
14340         i915_gem_object_unlock(obj);
14341
14342         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14343                 /*
14344                  * If there's a fence, enforce that
14345                  * the fb modifier and tiling mode match.
14346                  */
14347                 if (tiling != I915_TILING_NONE &&
14348                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14349                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14350                         goto err;
14351                 }
14352         } else {
14353                 if (tiling == I915_TILING_X) {
14354                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14355                 } else if (tiling == I915_TILING_Y) {
14356                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14357                         goto err;
14358                 }
14359         }
14360
14361         /* Passed in modifier sanity checking. */
14362         switch (mode_cmd->modifier[0]) {
14363         case I915_FORMAT_MOD_Y_TILED:
14364         case I915_FORMAT_MOD_Yf_TILED:
14365                 if (INTEL_GEN(dev_priv) < 9) {
14366                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14367                                       mode_cmd->modifier[0]);
14368                         goto err;
14369                 }
14370         case DRM_FORMAT_MOD_NONE:
14371         case I915_FORMAT_MOD_X_TILED:
14372                 break;
14373         default:
14374                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14375                               mode_cmd->modifier[0]);
14376                 goto err;
14377         }
14378
14379         /*
14380          * gen2/3 display engine uses the fence if present,
14381          * so the tiling mode must match the fb modifier exactly.
14382          */
14383         if (INTEL_INFO(dev_priv)->gen < 4 &&
14384             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14385                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14386                 goto err;
14387         }
14388
14389         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14390                                            mode_cmd->pixel_format);
14391         if (mode_cmd->pitches[0] > pitch_limit) {
14392                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14393                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14394                               "tiled" : "linear",
14395                               mode_cmd->pitches[0], pitch_limit);
14396                 goto err;
14397         }
14398
14399         /*
14400          * If there's a fence, enforce that
14401          * the fb pitch and fence stride match.
14402          */
14403         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14404                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14405                               mode_cmd->pitches[0], stride);
14406                 goto err;
14407         }
14408
14409         /* Reject formats not supported by any plane early. */
14410         switch (mode_cmd->pixel_format) {
14411         case DRM_FORMAT_C8:
14412         case DRM_FORMAT_RGB565:
14413         case DRM_FORMAT_XRGB8888:
14414         case DRM_FORMAT_ARGB8888:
14415                 break;
14416         case DRM_FORMAT_XRGB1555:
14417                 if (INTEL_GEN(dev_priv) > 3) {
14418                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14419                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14420                         goto err;
14421                 }
14422                 break;
14423         case DRM_FORMAT_ABGR8888:
14424                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14425                     INTEL_GEN(dev_priv) < 9) {
14426                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14427                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14428                         goto err;
14429                 }
14430                 break;
14431         case DRM_FORMAT_XBGR8888:
14432         case DRM_FORMAT_XRGB2101010:
14433         case DRM_FORMAT_XBGR2101010:
14434                 if (INTEL_GEN(dev_priv) < 4) {
14435                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14436                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14437                         goto err;
14438                 }
14439                 break;
14440         case DRM_FORMAT_ABGR2101010:
14441                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14442                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14443                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14444                         goto err;
14445                 }
14446                 break;
14447         case DRM_FORMAT_YUYV:
14448         case DRM_FORMAT_UYVY:
14449         case DRM_FORMAT_YVYU:
14450         case DRM_FORMAT_VYUY:
14451                 if (INTEL_GEN(dev_priv) < 5) {
14452                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14453                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14454                         goto err;
14455                 }
14456                 break;
14457         default:
14458                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14459                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14460                 goto err;
14461         }
14462
14463         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14464         if (mode_cmd->offsets[0] != 0)
14465                 goto err;
14466
14467         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14468                                        &intel_fb->base, mode_cmd);
14469
14470         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14471         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14472                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14473                               mode_cmd->pitches[0], stride_alignment);
14474                 goto err;
14475         }
14476
14477         intel_fb->obj = obj;
14478
14479         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14480         if (ret)
14481                 goto err;
14482
14483         ret = drm_framebuffer_init(obj->base.dev,
14484                                    &intel_fb->base,
14485                                    &intel_fb_funcs);
14486         if (ret) {
14487                 DRM_ERROR("framebuffer init failed %d\n", ret);
14488                 goto err;
14489         }
14490
14491         return 0;
14492
14493 err:
14494         i915_gem_object_lock(obj);
14495         obj->framebuffer_references--;
14496         i915_gem_object_unlock(obj);
14497         return ret;
14498 }
14499
14500 static struct drm_framebuffer *
14501 intel_user_framebuffer_create(struct drm_device *dev,
14502                               struct drm_file *filp,
14503                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14504 {
14505         struct drm_framebuffer *fb;
14506         struct drm_i915_gem_object *obj;
14507         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14508
14509         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14510         if (!obj)
14511                 return ERR_PTR(-ENOENT);
14512
14513         fb = intel_framebuffer_create(obj, &mode_cmd);
14514         if (IS_ERR(fb))
14515                 i915_gem_object_put(obj);
14516
14517         return fb;
14518 }
14519
14520 static void intel_atomic_state_free(struct drm_atomic_state *state)
14521 {
14522         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14523
14524         drm_atomic_state_default_release(state);
14525
14526         i915_sw_fence_fini(&intel_state->commit_ready);
14527
14528         kfree(state);
14529 }
14530
14531 static const struct drm_mode_config_funcs intel_mode_funcs = {
14532         .fb_create = intel_user_framebuffer_create,
14533         .output_poll_changed = intel_fbdev_output_poll_changed,
14534         .atomic_check = intel_atomic_check,
14535         .atomic_commit = intel_atomic_commit,
14536         .atomic_state_alloc = intel_atomic_state_alloc,
14537         .atomic_state_clear = intel_atomic_state_clear,
14538         .atomic_state_free = intel_atomic_state_free,
14539 };
14540
14541 /**
14542  * intel_init_display_hooks - initialize the display modesetting hooks
14543  * @dev_priv: device private
14544  */
14545 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14546 {
14547         intel_init_cdclk_hooks(dev_priv);
14548
14549         if (INTEL_INFO(dev_priv)->gen >= 9) {
14550                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14551                 dev_priv->display.get_initial_plane_config =
14552                         skylake_get_initial_plane_config;
14553                 dev_priv->display.crtc_compute_clock =
14554                         haswell_crtc_compute_clock;
14555                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14556                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14557         } else if (HAS_DDI(dev_priv)) {
14558                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14559                 dev_priv->display.get_initial_plane_config =
14560                         ironlake_get_initial_plane_config;
14561                 dev_priv->display.crtc_compute_clock =
14562                         haswell_crtc_compute_clock;
14563                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14564                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14565         } else if (HAS_PCH_SPLIT(dev_priv)) {
14566                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14567                 dev_priv->display.get_initial_plane_config =
14568                         ironlake_get_initial_plane_config;
14569                 dev_priv->display.crtc_compute_clock =
14570                         ironlake_crtc_compute_clock;
14571                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14572                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14573         } else if (IS_CHERRYVIEW(dev_priv)) {
14574                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14575                 dev_priv->display.get_initial_plane_config =
14576                         i9xx_get_initial_plane_config;
14577                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14578                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14579                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14580         } else if (IS_VALLEYVIEW(dev_priv)) {
14581                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14582                 dev_priv->display.get_initial_plane_config =
14583                         i9xx_get_initial_plane_config;
14584                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14585                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14586                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14587         } else if (IS_G4X(dev_priv)) {
14588                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14589                 dev_priv->display.get_initial_plane_config =
14590                         i9xx_get_initial_plane_config;
14591                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14592                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14593                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14594         } else if (IS_PINEVIEW(dev_priv)) {
14595                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14596                 dev_priv->display.get_initial_plane_config =
14597                         i9xx_get_initial_plane_config;
14598                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14599                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14600                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14601         } else if (!IS_GEN2(dev_priv)) {
14602                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14603                 dev_priv->display.get_initial_plane_config =
14604                         i9xx_get_initial_plane_config;
14605                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14606                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14607                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14608         } else {
14609                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14610                 dev_priv->display.get_initial_plane_config =
14611                         i9xx_get_initial_plane_config;
14612                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14613                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14614                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14615         }
14616
14617         if (IS_GEN5(dev_priv)) {
14618                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14619         } else if (IS_GEN6(dev_priv)) {
14620                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14621         } else if (IS_IVYBRIDGE(dev_priv)) {
14622                 /* FIXME: detect B0+ stepping and use auto training */
14623                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14624         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14625                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14626         }
14627
14628         if (dev_priv->info.gen >= 9)
14629                 dev_priv->display.update_crtcs = skl_update_crtcs;
14630         else
14631                 dev_priv->display.update_crtcs = intel_update_crtcs;
14632
14633         switch (INTEL_INFO(dev_priv)->gen) {
14634         case 2:
14635                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14636                 break;
14637
14638         case 3:
14639                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14640                 break;
14641
14642         case 4:
14643         case 5:
14644                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14645                 break;
14646
14647         case 6:
14648                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14649                 break;
14650         case 7:
14651         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14652                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14653                 break;
14654         case 9:
14655                 /* Drop through - unsupported since execlist only. */
14656         default:
14657                 /* Default just returns -ENODEV to indicate unsupported */
14658                 dev_priv->display.queue_flip = intel_default_queue_flip;
14659         }
14660 }
14661
14662 /*
14663  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14664  * resume, or other times.  This quirk makes sure that's the case for
14665  * affected systems.
14666  */
14667 static void quirk_pipea_force(struct drm_device *dev)
14668 {
14669         struct drm_i915_private *dev_priv = to_i915(dev);
14670
14671         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14672         DRM_INFO("applying pipe a force quirk\n");
14673 }
14674
14675 static void quirk_pipeb_force(struct drm_device *dev)
14676 {
14677         struct drm_i915_private *dev_priv = to_i915(dev);
14678
14679         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14680         DRM_INFO("applying pipe b force quirk\n");
14681 }
14682
14683 /*
14684  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14685  */
14686 static void quirk_ssc_force_disable(struct drm_device *dev)
14687 {
14688         struct drm_i915_private *dev_priv = to_i915(dev);
14689         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14690         DRM_INFO("applying lvds SSC disable quirk\n");
14691 }
14692
14693 /*
14694  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14695  * brightness value
14696  */
14697 static void quirk_invert_brightness(struct drm_device *dev)
14698 {
14699         struct drm_i915_private *dev_priv = to_i915(dev);
14700         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14701         DRM_INFO("applying inverted panel brightness quirk\n");
14702 }
14703
14704 /* Some VBT's incorrectly indicate no backlight is present */
14705 static void quirk_backlight_present(struct drm_device *dev)
14706 {
14707         struct drm_i915_private *dev_priv = to_i915(dev);
14708         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14709         DRM_INFO("applying backlight present quirk\n");
14710 }
14711
14712 struct intel_quirk {
14713         int device;
14714         int subsystem_vendor;
14715         int subsystem_device;
14716         void (*hook)(struct drm_device *dev);
14717 };
14718
14719 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14720 struct intel_dmi_quirk {
14721         void (*hook)(struct drm_device *dev);
14722         const struct dmi_system_id (*dmi_id_list)[];
14723 };
14724
14725 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14726 {
14727         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14728         return 1;
14729 }
14730
14731 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14732         {
14733                 .dmi_id_list = &(const struct dmi_system_id[]) {
14734                         {
14735                                 .callback = intel_dmi_reverse_brightness,
14736                                 .ident = "NCR Corporation",
14737                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14738                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14739                                 },
14740                         },
14741                         { }  /* terminating entry */
14742                 },
14743                 .hook = quirk_invert_brightness,
14744         },
14745 };
14746
14747 static struct intel_quirk intel_quirks[] = {
14748         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14749         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14750
14751         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14752         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14753
14754         /* 830 needs to leave pipe A & dpll A up */
14755         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14756
14757         /* 830 needs to leave pipe B & dpll B up */
14758         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14759
14760         /* Lenovo U160 cannot use SSC on LVDS */
14761         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14762
14763         /* Sony Vaio Y cannot use SSC on LVDS */
14764         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14765
14766         /* Acer Aspire 5734Z must invert backlight brightness */
14767         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14768
14769         /* Acer/eMachines G725 */
14770         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14771
14772         /* Acer/eMachines e725 */
14773         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14774
14775         /* Acer/Packard Bell NCL20 */
14776         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14777
14778         /* Acer Aspire 4736Z */
14779         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14780
14781         /* Acer Aspire 5336 */
14782         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14783
14784         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14785         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14786
14787         /* Acer C720 Chromebook (Core i3 4005U) */
14788         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14789
14790         /* Apple Macbook 2,1 (Core 2 T7400) */
14791         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14792
14793         /* Apple Macbook 4,1 */
14794         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14795
14796         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14797         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14798
14799         /* HP Chromebook 14 (Celeron 2955U) */
14800         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14801
14802         /* Dell Chromebook 11 */
14803         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14804
14805         /* Dell Chromebook 11 (2015 version) */
14806         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14807 };
14808
14809 static void intel_init_quirks(struct drm_device *dev)
14810 {
14811         struct pci_dev *d = dev->pdev;
14812         int i;
14813
14814         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14815                 struct intel_quirk *q = &intel_quirks[i];
14816
14817                 if (d->device == q->device &&
14818                     (d->subsystem_vendor == q->subsystem_vendor ||
14819                      q->subsystem_vendor == PCI_ANY_ID) &&
14820                     (d->subsystem_device == q->subsystem_device ||
14821                      q->subsystem_device == PCI_ANY_ID))
14822                         q->hook(dev);
14823         }
14824         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14825                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14826                         intel_dmi_quirks[i].hook(dev);
14827         }
14828 }
14829
14830 /* Disable the VGA plane that we never use */
14831 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14832 {
14833         struct pci_dev *pdev = dev_priv->drm.pdev;
14834         u8 sr1;
14835         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14836
14837         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14838         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14839         outb(SR01, VGA_SR_INDEX);
14840         sr1 = inb(VGA_SR_DATA);
14841         outb(sr1 | 1<<5, VGA_SR_DATA);
14842         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14843         udelay(300);
14844
14845         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14846         POSTING_READ(vga_reg);
14847 }
14848
14849 void intel_modeset_init_hw(struct drm_device *dev)
14850 {
14851         struct drm_i915_private *dev_priv = to_i915(dev);
14852
14853         intel_update_cdclk(dev_priv);
14854         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14855
14856         intel_init_clock_gating(dev_priv);
14857 }
14858
14859 /*
14860  * Calculate what we think the watermarks should be for the state we've read
14861  * out of the hardware and then immediately program those watermarks so that
14862  * we ensure the hardware settings match our internal state.
14863  *
14864  * We can calculate what we think WM's should be by creating a duplicate of the
14865  * current state (which was constructed during hardware readout) and running it
14866  * through the atomic check code to calculate new watermark values in the
14867  * state object.
14868  */
14869 static void sanitize_watermarks(struct drm_device *dev)
14870 {
14871         struct drm_i915_private *dev_priv = to_i915(dev);
14872         struct drm_atomic_state *state;
14873         struct intel_atomic_state *intel_state;
14874         struct drm_crtc *crtc;
14875         struct drm_crtc_state *cstate;
14876         struct drm_modeset_acquire_ctx ctx;
14877         int ret;
14878         int i;
14879
14880         /* Only supported on platforms that use atomic watermark design */
14881         if (!dev_priv->display.optimize_watermarks)
14882                 return;
14883
14884         /*
14885          * We need to hold connection_mutex before calling duplicate_state so
14886          * that the connector loop is protected.
14887          */
14888         drm_modeset_acquire_init(&ctx, 0);
14889 retry:
14890         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14891         if (ret == -EDEADLK) {
14892                 drm_modeset_backoff(&ctx);
14893                 goto retry;
14894         } else if (WARN_ON(ret)) {
14895                 goto fail;
14896         }
14897
14898         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14899         if (WARN_ON(IS_ERR(state)))
14900                 goto fail;
14901
14902         intel_state = to_intel_atomic_state(state);
14903
14904         /*
14905          * Hardware readout is the only time we don't want to calculate
14906          * intermediate watermarks (since we don't trust the current
14907          * watermarks).
14908          */
14909         if (!HAS_GMCH_DISPLAY(dev_priv))
14910                 intel_state->skip_intermediate_wm = true;
14911
14912         ret = intel_atomic_check(dev, state);
14913         if (ret) {
14914                 /*
14915                  * If we fail here, it means that the hardware appears to be
14916                  * programmed in a way that shouldn't be possible, given our
14917                  * understanding of watermark requirements.  This might mean a
14918                  * mistake in the hardware readout code or a mistake in the
14919                  * watermark calculations for a given platform.  Raise a WARN
14920                  * so that this is noticeable.
14921                  *
14922                  * If this actually happens, we'll have to just leave the
14923                  * BIOS-programmed watermarks untouched and hope for the best.
14924                  */
14925                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14926                 goto put_state;
14927         }
14928
14929         /* Write calculated watermark values back */
14930         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14931                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14932
14933                 cs->wm.need_postvbl_update = true;
14934                 dev_priv->display.optimize_watermarks(intel_state, cs);
14935         }
14936
14937 put_state:
14938         drm_atomic_state_put(state);
14939 fail:
14940         drm_modeset_drop_locks(&ctx);
14941         drm_modeset_acquire_fini(&ctx);
14942 }
14943
14944 int intel_modeset_init(struct drm_device *dev)
14945 {
14946         struct drm_i915_private *dev_priv = to_i915(dev);
14947         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14948         enum pipe pipe;
14949         struct intel_crtc *crtc;
14950
14951         drm_mode_config_init(dev);
14952
14953         dev->mode_config.min_width = 0;
14954         dev->mode_config.min_height = 0;
14955
14956         dev->mode_config.preferred_depth = 24;
14957         dev->mode_config.prefer_shadow = 1;
14958
14959         dev->mode_config.allow_fb_modifiers = true;
14960
14961         dev->mode_config.funcs = &intel_mode_funcs;
14962
14963         INIT_WORK(&dev_priv->atomic_helper.free_work,
14964                   intel_atomic_helper_free_state_worker);
14965
14966         intel_init_quirks(dev);
14967
14968         intel_init_pm(dev_priv);
14969
14970         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14971                 return 0;
14972
14973         /*
14974          * There may be no VBT; and if the BIOS enabled SSC we can
14975          * just keep using it to avoid unnecessary flicker.  Whereas if the
14976          * BIOS isn't using it, don't assume it will work even if the VBT
14977          * indicates as much.
14978          */
14979         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14980                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14981                                             DREF_SSC1_ENABLE);
14982
14983                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14984                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14985                                      bios_lvds_use_ssc ? "en" : "dis",
14986                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14987                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14988                 }
14989         }
14990
14991         if (IS_GEN2(dev_priv)) {
14992                 dev->mode_config.max_width = 2048;
14993                 dev->mode_config.max_height = 2048;
14994         } else if (IS_GEN3(dev_priv)) {
14995                 dev->mode_config.max_width = 4096;
14996                 dev->mode_config.max_height = 4096;
14997         } else {
14998                 dev->mode_config.max_width = 8192;
14999                 dev->mode_config.max_height = 8192;
15000         }
15001
15002         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15003                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15004                 dev->mode_config.cursor_height = 1023;
15005         } else if (IS_GEN2(dev_priv)) {
15006                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15007                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15008         } else {
15009                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15010                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15011         }
15012
15013         dev->mode_config.fb_base = ggtt->mappable_base;
15014
15015         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15016                       INTEL_INFO(dev_priv)->num_pipes,
15017                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15018
15019         for_each_pipe(dev_priv, pipe) {
15020                 int ret;
15021
15022                 ret = intel_crtc_init(dev_priv, pipe);
15023                 if (ret) {
15024                         drm_mode_config_cleanup(dev);
15025                         return ret;
15026                 }
15027         }
15028
15029         intel_shared_dpll_init(dev);
15030
15031         intel_update_czclk(dev_priv);
15032         intel_modeset_init_hw(dev);
15033
15034         if (dev_priv->max_cdclk_freq == 0)
15035                 intel_update_max_cdclk(dev_priv);
15036
15037         /* Just disable it once at startup */
15038         i915_disable_vga(dev_priv);
15039         intel_setup_outputs(dev_priv);
15040
15041         drm_modeset_lock_all(dev);
15042         intel_modeset_setup_hw_state(dev);
15043         drm_modeset_unlock_all(dev);
15044
15045         for_each_intel_crtc(dev, crtc) {
15046                 struct intel_initial_plane_config plane_config = {};
15047
15048                 if (!crtc->active)
15049                         continue;
15050
15051                 /*
15052                  * Note that reserving the BIOS fb up front prevents us
15053                  * from stuffing other stolen allocations like the ring
15054                  * on top.  This prevents some ugliness at boot time, and
15055                  * can even allow for smooth boot transitions if the BIOS
15056                  * fb is large enough for the active pipe configuration.
15057                  */
15058                 dev_priv->display.get_initial_plane_config(crtc,
15059                                                            &plane_config);
15060
15061                 /*
15062                  * If the fb is shared between multiple heads, we'll
15063                  * just get the first one.
15064                  */
15065                 intel_find_initial_plane_obj(crtc, &plane_config);
15066         }
15067
15068         /*
15069          * Make sure hardware watermarks really match the state we read out.
15070          * Note that we need to do this after reconstructing the BIOS fb's
15071          * since the watermark calculation done here will use pstate->fb.
15072          */
15073         if (!HAS_GMCH_DISPLAY(dev_priv))
15074                 sanitize_watermarks(dev);
15075
15076         return 0;
15077 }
15078
15079 static void intel_enable_pipe_a(struct drm_device *dev)
15080 {
15081         struct intel_connector *connector;
15082         struct drm_connector_list_iter conn_iter;
15083         struct drm_connector *crt = NULL;
15084         struct intel_load_detect_pipe load_detect_temp;
15085         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15086
15087         /* We can't just switch on the pipe A, we need to set things up with a
15088          * proper mode and output configuration. As a gross hack, enable pipe A
15089          * by enabling the load detect pipe once. */
15090         drm_connector_list_iter_begin(dev, &conn_iter);
15091         for_each_intel_connector_iter(connector, &conn_iter) {
15092                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15093                         crt = &connector->base;
15094                         break;
15095                 }
15096         }
15097         drm_connector_list_iter_end(&conn_iter);
15098
15099         if (!crt)
15100                 return;
15101
15102         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15103                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15104 }
15105
15106 static bool
15107 intel_check_plane_mapping(struct intel_crtc *crtc)
15108 {
15109         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15110         u32 val;
15111
15112         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15113                 return true;
15114
15115         val = I915_READ(DSPCNTR(!crtc->plane));
15116
15117         if ((val & DISPLAY_PLANE_ENABLE) &&
15118             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15119                 return false;
15120
15121         return true;
15122 }
15123
15124 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15125 {
15126         struct drm_device *dev = crtc->base.dev;
15127         struct intel_encoder *encoder;
15128
15129         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15130                 return true;
15131
15132         return false;
15133 }
15134
15135 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15136 {
15137         struct drm_device *dev = encoder->base.dev;
15138         struct intel_connector *connector;
15139
15140         for_each_connector_on_encoder(dev, &encoder->base, connector)
15141                 return connector;
15142
15143         return NULL;
15144 }
15145
15146 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15147                               enum transcoder pch_transcoder)
15148 {
15149         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15150                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15151 }
15152
15153 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15154 {
15155         struct drm_device *dev = crtc->base.dev;
15156         struct drm_i915_private *dev_priv = to_i915(dev);
15157         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15158
15159         /* Clear any frame start delays used for debugging left by the BIOS */
15160         if (!transcoder_is_dsi(cpu_transcoder)) {
15161                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15162
15163                 I915_WRITE(reg,
15164                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15165         }
15166
15167         /* restore vblank interrupts to correct state */
15168         drm_crtc_vblank_reset(&crtc->base);
15169         if (crtc->active) {
15170                 struct intel_plane *plane;
15171
15172                 drm_crtc_vblank_on(&crtc->base);
15173
15174                 /* Disable everything but the primary plane */
15175                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15176                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15177                                 continue;
15178
15179                         trace_intel_disable_plane(&plane->base, crtc);
15180                         plane->disable_plane(&plane->base, &crtc->base);
15181                 }
15182         }
15183
15184         /* We need to sanitize the plane -> pipe mapping first because this will
15185          * disable the crtc (and hence change the state) if it is wrong. Note
15186          * that gen4+ has a fixed plane -> pipe mapping.  */
15187         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15188                 bool plane;
15189
15190                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15191                               crtc->base.base.id, crtc->base.name);
15192
15193                 /* Pipe has the wrong plane attached and the plane is active.
15194                  * Temporarily change the plane mapping and disable everything
15195                  * ...  */
15196                 plane = crtc->plane;
15197                 crtc->base.primary->state->visible = true;
15198                 crtc->plane = !plane;
15199                 intel_crtc_disable_noatomic(&crtc->base);
15200                 crtc->plane = plane;
15201         }
15202
15203         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15204             crtc->pipe == PIPE_A && !crtc->active) {
15205                 /* BIOS forgot to enable pipe A, this mostly happens after
15206                  * resume. Force-enable the pipe to fix this, the update_dpms
15207                  * call below we restore the pipe to the right state, but leave
15208                  * the required bits on. */
15209                 intel_enable_pipe_a(dev);
15210         }
15211
15212         /* Adjust the state of the output pipe according to whether we
15213          * have active connectors/encoders. */
15214         if (crtc->active && !intel_crtc_has_encoders(crtc))
15215                 intel_crtc_disable_noatomic(&crtc->base);
15216
15217         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15218                 /*
15219                  * We start out with underrun reporting disabled to avoid races.
15220                  * For correct bookkeeping mark this on active crtcs.
15221                  *
15222                  * Also on gmch platforms we dont have any hardware bits to
15223                  * disable the underrun reporting. Which means we need to start
15224                  * out with underrun reporting disabled also on inactive pipes,
15225                  * since otherwise we'll complain about the garbage we read when
15226                  * e.g. coming up after runtime pm.
15227                  *
15228                  * No protection against concurrent access is required - at
15229                  * worst a fifo underrun happens which also sets this to false.
15230                  */
15231                 crtc->cpu_fifo_underrun_disabled = true;
15232                 /*
15233                  * We track the PCH trancoder underrun reporting state
15234                  * within the crtc. With crtc for pipe A housing the underrun
15235                  * reporting state for PCH transcoder A, crtc for pipe B housing
15236                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15237                  * and marking underrun reporting as disabled for the non-existing
15238                  * PCH transcoders B and C would prevent enabling the south
15239                  * error interrupt (see cpt_can_enable_serr_int()).
15240                  */
15241                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15242                         crtc->pch_fifo_underrun_disabled = true;
15243         }
15244 }
15245
15246 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15247 {
15248         struct intel_connector *connector;
15249
15250         /* We need to check both for a crtc link (meaning that the
15251          * encoder is active and trying to read from a pipe) and the
15252          * pipe itself being active. */
15253         bool has_active_crtc = encoder->base.crtc &&
15254                 to_intel_crtc(encoder->base.crtc)->active;
15255
15256         connector = intel_encoder_find_connector(encoder);
15257         if (connector && !has_active_crtc) {
15258                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15259                               encoder->base.base.id,
15260                               encoder->base.name);
15261
15262                 /* Connector is active, but has no active pipe. This is
15263                  * fallout from our resume register restoring. Disable
15264                  * the encoder manually again. */
15265                 if (encoder->base.crtc) {
15266                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15267
15268                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15269                                       encoder->base.base.id,
15270                                       encoder->base.name);
15271                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15272                         if (encoder->post_disable)
15273                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15274                 }
15275                 encoder->base.crtc = NULL;
15276
15277                 /* Inconsistent output/port/pipe state happens presumably due to
15278                  * a bug in one of the get_hw_state functions. Or someplace else
15279                  * in our code, like the register restore mess on resume. Clamp
15280                  * things to off as a safer default. */
15281
15282                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15283                 connector->base.encoder = NULL;
15284         }
15285         /* Enabled encoders without active connectors will be fixed in
15286          * the crtc fixup. */
15287 }
15288
15289 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15290 {
15291         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15292
15293         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15294                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15295                 i915_disable_vga(dev_priv);
15296         }
15297 }
15298
15299 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15300 {
15301         /* This function can be called both from intel_modeset_setup_hw_state or
15302          * at a very early point in our resume sequence, where the power well
15303          * structures are not yet restored. Since this function is at a very
15304          * paranoid "someone might have enabled VGA while we were not looking"
15305          * level, just check if the power well is enabled instead of trying to
15306          * follow the "don't touch the power well if we don't need it" policy
15307          * the rest of the driver uses. */
15308         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15309                 return;
15310
15311         i915_redisable_vga_power_on(dev_priv);
15312
15313         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15314 }
15315
15316 static bool primary_get_hw_state(struct intel_plane *plane)
15317 {
15318         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15319
15320         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15321 }
15322
15323 /* FIXME read out full plane state for all planes */
15324 static void readout_plane_state(struct intel_crtc *crtc)
15325 {
15326         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15327         bool visible;
15328
15329         visible = crtc->active && primary_get_hw_state(primary);
15330
15331         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15332                                 to_intel_plane_state(primary->base.state),
15333                                 visible);
15334 }
15335
15336 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15337 {
15338         struct drm_i915_private *dev_priv = to_i915(dev);
15339         enum pipe pipe;
15340         struct intel_crtc *crtc;
15341         struct intel_encoder *encoder;
15342         struct intel_connector *connector;
15343         struct drm_connector_list_iter conn_iter;
15344         int i;
15345
15346         dev_priv->active_crtcs = 0;
15347
15348         for_each_intel_crtc(dev, crtc) {
15349                 struct intel_crtc_state *crtc_state =
15350                         to_intel_crtc_state(crtc->base.state);
15351
15352                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15353                 memset(crtc_state, 0, sizeof(*crtc_state));
15354                 crtc_state->base.crtc = &crtc->base;
15355
15356                 crtc_state->base.active = crtc_state->base.enable =
15357                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15358
15359                 crtc->base.enabled = crtc_state->base.enable;
15360                 crtc->active = crtc_state->base.active;
15361
15362                 if (crtc_state->base.active)
15363                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15364
15365                 readout_plane_state(crtc);
15366
15367                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15368                               crtc->base.base.id, crtc->base.name,
15369                               enableddisabled(crtc_state->base.active));
15370         }
15371
15372         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15373                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15374
15375                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15376                                                   &pll->state.hw_state);
15377                 pll->state.crtc_mask = 0;
15378                 for_each_intel_crtc(dev, crtc) {
15379                         struct intel_crtc_state *crtc_state =
15380                                 to_intel_crtc_state(crtc->base.state);
15381
15382                         if (crtc_state->base.active &&
15383                             crtc_state->shared_dpll == pll)
15384                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15385                 }
15386                 pll->active_mask = pll->state.crtc_mask;
15387
15388                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15389                               pll->name, pll->state.crtc_mask, pll->on);
15390         }
15391
15392         for_each_intel_encoder(dev, encoder) {
15393                 pipe = 0;
15394
15395                 if (encoder->get_hw_state(encoder, &pipe)) {
15396                         struct intel_crtc_state *crtc_state;
15397
15398                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15399                         crtc_state = to_intel_crtc_state(crtc->base.state);
15400
15401                         encoder->base.crtc = &crtc->base;
15402                         crtc_state->output_types |= 1 << encoder->type;
15403                         encoder->get_config(encoder, crtc_state);
15404                 } else {
15405                         encoder->base.crtc = NULL;
15406                 }
15407
15408                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15409                               encoder->base.base.id, encoder->base.name,
15410                               enableddisabled(encoder->base.crtc),
15411                               pipe_name(pipe));
15412         }
15413
15414         drm_connector_list_iter_begin(dev, &conn_iter);
15415         for_each_intel_connector_iter(connector, &conn_iter) {
15416                 if (connector->get_hw_state(connector)) {
15417                         connector->base.dpms = DRM_MODE_DPMS_ON;
15418
15419                         encoder = connector->encoder;
15420                         connector->base.encoder = &encoder->base;
15421
15422                         if (encoder->base.crtc &&
15423                             encoder->base.crtc->state->active) {
15424                                 /*
15425                                  * This has to be done during hardware readout
15426                                  * because anything calling .crtc_disable may
15427                                  * rely on the connector_mask being accurate.
15428                                  */
15429                                 encoder->base.crtc->state->connector_mask |=
15430                                         1 << drm_connector_index(&connector->base);
15431                                 encoder->base.crtc->state->encoder_mask |=
15432                                         1 << drm_encoder_index(&encoder->base);
15433                         }
15434
15435                 } else {
15436                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15437                         connector->base.encoder = NULL;
15438                 }
15439                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15440                               connector->base.base.id, connector->base.name,
15441                               enableddisabled(connector->base.encoder));
15442         }
15443         drm_connector_list_iter_end(&conn_iter);
15444
15445         for_each_intel_crtc(dev, crtc) {
15446                 struct intel_crtc_state *crtc_state =
15447                         to_intel_crtc_state(crtc->base.state);
15448                 int pixclk = 0;
15449
15450                 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15451
15452                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15453                 if (crtc_state->base.active) {
15454                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15455                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15456                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15457
15458                         /*
15459                          * The initial mode needs to be set in order to keep
15460                          * the atomic core happy. It wants a valid mode if the
15461                          * crtc's enabled, so we do the above call.
15462                          *
15463                          * But we don't set all the derived state fully, hence
15464                          * set a flag to indicate that a full recalculation is
15465                          * needed on the next commit.
15466                          */
15467                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15468
15469                         intel_crtc_compute_pixel_rate(crtc_state);
15470
15471                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15472                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15473                                 pixclk = crtc_state->pixel_rate;
15474                         else
15475                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15476
15477                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15478                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15479                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15480
15481                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15482                         update_scanline_offset(crtc);
15483                 }
15484
15485                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15486
15487                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15488         }
15489 }
15490
15491 static void
15492 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15493 {
15494         struct intel_encoder *encoder;
15495
15496         for_each_intel_encoder(&dev_priv->drm, encoder) {
15497                 u64 get_domains;
15498                 enum intel_display_power_domain domain;
15499
15500                 if (!encoder->get_power_domains)
15501                         continue;
15502
15503                 get_domains = encoder->get_power_domains(encoder);
15504                 for_each_power_domain(domain, get_domains)
15505                         intel_display_power_get(dev_priv, domain);
15506         }
15507 }
15508
15509 /* Scan out the current hw modeset state,
15510  * and sanitizes it to the current state
15511  */
15512 static void
15513 intel_modeset_setup_hw_state(struct drm_device *dev)
15514 {
15515         struct drm_i915_private *dev_priv = to_i915(dev);
15516         enum pipe pipe;
15517         struct intel_crtc *crtc;
15518         struct intel_encoder *encoder;
15519         int i;
15520
15521         intel_modeset_readout_hw_state(dev);
15522
15523         /* HW state is read out, now we need to sanitize this mess. */
15524         get_encoder_power_domains(dev_priv);
15525
15526         for_each_intel_encoder(dev, encoder) {
15527                 intel_sanitize_encoder(encoder);
15528         }
15529
15530         for_each_pipe(dev_priv, pipe) {
15531                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15532
15533                 intel_sanitize_crtc(crtc);
15534                 intel_dump_pipe_config(crtc, crtc->config,
15535                                        "[setup_hw_state]");
15536         }
15537
15538         intel_modeset_update_connector_atomic_state(dev);
15539
15540         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15541                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15542
15543                 if (!pll->on || pll->active_mask)
15544                         continue;
15545
15546                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15547
15548                 pll->funcs.disable(dev_priv, pll);
15549                 pll->on = false;
15550         }
15551
15552         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15553                 vlv_wm_get_hw_state(dev);
15554                 vlv_wm_sanitize(dev_priv);
15555         } else if (IS_GEN9(dev_priv)) {
15556                 skl_wm_get_hw_state(dev);
15557         } else if (HAS_PCH_SPLIT(dev_priv)) {
15558                 ilk_wm_get_hw_state(dev);
15559         }
15560
15561         for_each_intel_crtc(dev, crtc) {
15562                 u64 put_domains;
15563
15564                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15565                 if (WARN_ON(put_domains))
15566                         modeset_put_power_domains(dev_priv, put_domains);
15567         }
15568         intel_display_set_init_power(dev_priv, false);
15569
15570         intel_power_domains_verify_state(dev_priv);
15571
15572         intel_fbc_init_pipe_state(dev_priv);
15573 }
15574
15575 void intel_display_resume(struct drm_device *dev)
15576 {
15577         struct drm_i915_private *dev_priv = to_i915(dev);
15578         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15579         struct drm_modeset_acquire_ctx ctx;
15580         int ret;
15581
15582         dev_priv->modeset_restore_state = NULL;
15583         if (state)
15584                 state->acquire_ctx = &ctx;
15585
15586         /*
15587          * This is a cludge because with real atomic modeset mode_config.mutex
15588          * won't be taken. Unfortunately some probed state like
15589          * audio_codec_enable is still protected by mode_config.mutex, so lock
15590          * it here for now.
15591          */
15592         mutex_lock(&dev->mode_config.mutex);
15593         drm_modeset_acquire_init(&ctx, 0);
15594
15595         while (1) {
15596                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15597                 if (ret != -EDEADLK)
15598                         break;
15599
15600                 drm_modeset_backoff(&ctx);
15601         }
15602
15603         if (!ret)
15604                 ret = __intel_display_resume(dev, state, &ctx);
15605
15606         drm_modeset_drop_locks(&ctx);
15607         drm_modeset_acquire_fini(&ctx);
15608         mutex_unlock(&dev->mode_config.mutex);
15609
15610         if (ret)
15611                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15612         if (state)
15613                 drm_atomic_state_put(state);
15614 }
15615
15616 void intel_modeset_gem_init(struct drm_device *dev)
15617 {
15618         struct drm_i915_private *dev_priv = to_i915(dev);
15619
15620         intel_init_gt_powersave(dev_priv);
15621
15622         intel_setup_overlay(dev_priv);
15623 }
15624
15625 int intel_connector_register(struct drm_connector *connector)
15626 {
15627         struct intel_connector *intel_connector = to_intel_connector(connector);
15628         int ret;
15629
15630         ret = intel_backlight_device_register(intel_connector);
15631         if (ret)
15632                 goto err;
15633
15634         return 0;
15635
15636 err:
15637         return ret;
15638 }
15639
15640 void intel_connector_unregister(struct drm_connector *connector)
15641 {
15642         struct intel_connector *intel_connector = to_intel_connector(connector);
15643
15644         intel_backlight_device_unregister(intel_connector);
15645         intel_panel_destroy_backlight(connector);
15646 }
15647
15648 void intel_modeset_cleanup(struct drm_device *dev)
15649 {
15650         struct drm_i915_private *dev_priv = to_i915(dev);
15651
15652         flush_work(&dev_priv->atomic_helper.free_work);
15653         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15654
15655         intel_disable_gt_powersave(dev_priv);
15656
15657         /*
15658          * Interrupts and polling as the first thing to avoid creating havoc.
15659          * Too much stuff here (turning of connectors, ...) would
15660          * experience fancy races otherwise.
15661          */
15662         intel_irq_uninstall(dev_priv);
15663
15664         /*
15665          * Due to the hpd irq storm handling the hotplug work can re-arm the
15666          * poll handlers. Hence disable polling after hpd handling is shut down.
15667          */
15668         drm_kms_helper_poll_fini(dev);
15669
15670         intel_unregister_dsm_handler();
15671
15672         intel_fbc_global_disable(dev_priv);
15673
15674         /* flush any delayed tasks or pending work */
15675         flush_scheduled_work();
15676
15677         drm_mode_config_cleanup(dev);
15678
15679         intel_cleanup_overlay(dev_priv);
15680
15681         intel_cleanup_gt_powersave(dev_priv);
15682
15683         intel_teardown_gmbus(dev_priv);
15684 }
15685
15686 void intel_connector_attach_encoder(struct intel_connector *connector,
15687                                     struct intel_encoder *encoder)
15688 {
15689         connector->encoder = encoder;
15690         drm_mode_connector_attach_encoder(&connector->base,
15691                                           &encoder->base);
15692 }
15693
15694 /*
15695  * set vga decode state - true == enable VGA decode
15696  */
15697 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15698 {
15699         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15700         u16 gmch_ctrl;
15701
15702         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15703                 DRM_ERROR("failed to read control word\n");
15704                 return -EIO;
15705         }
15706
15707         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15708                 return 0;
15709
15710         if (state)
15711                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15712         else
15713                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15714
15715         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15716                 DRM_ERROR("failed to write control word\n");
15717                 return -EIO;
15718         }
15719
15720         return 0;
15721 }
15722
15723 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15724
15725 struct intel_display_error_state {
15726
15727         u32 power_well_driver;
15728
15729         int num_transcoders;
15730
15731         struct intel_cursor_error_state {
15732                 u32 control;
15733                 u32 position;
15734                 u32 base;
15735                 u32 size;
15736         } cursor[I915_MAX_PIPES];
15737
15738         struct intel_pipe_error_state {
15739                 bool power_domain_on;
15740                 u32 source;
15741                 u32 stat;
15742         } pipe[I915_MAX_PIPES];
15743
15744         struct intel_plane_error_state {
15745                 u32 control;
15746                 u32 stride;
15747                 u32 size;
15748                 u32 pos;
15749                 u32 addr;
15750                 u32 surface;
15751                 u32 tile_offset;
15752         } plane[I915_MAX_PIPES];
15753
15754         struct intel_transcoder_error_state {
15755                 bool power_domain_on;
15756                 enum transcoder cpu_transcoder;
15757
15758                 u32 conf;
15759
15760                 u32 htotal;
15761                 u32 hblank;
15762                 u32 hsync;
15763                 u32 vtotal;
15764                 u32 vblank;
15765                 u32 vsync;
15766         } transcoder[4];
15767 };
15768
15769 struct intel_display_error_state *
15770 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15771 {
15772         struct intel_display_error_state *error;
15773         int transcoders[] = {
15774                 TRANSCODER_A,
15775                 TRANSCODER_B,
15776                 TRANSCODER_C,
15777                 TRANSCODER_EDP,
15778         };
15779         int i;
15780
15781         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15782                 return NULL;
15783
15784         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15785         if (error == NULL)
15786                 return NULL;
15787
15788         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15789                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15790
15791         for_each_pipe(dev_priv, i) {
15792                 error->pipe[i].power_domain_on =
15793                         __intel_display_power_is_enabled(dev_priv,
15794                                                          POWER_DOMAIN_PIPE(i));
15795                 if (!error->pipe[i].power_domain_on)
15796                         continue;
15797
15798                 error->cursor[i].control = I915_READ(CURCNTR(i));
15799                 error->cursor[i].position = I915_READ(CURPOS(i));
15800                 error->cursor[i].base = I915_READ(CURBASE(i));
15801
15802                 error->plane[i].control = I915_READ(DSPCNTR(i));
15803                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15804                 if (INTEL_GEN(dev_priv) <= 3) {
15805                         error->plane[i].size = I915_READ(DSPSIZE(i));
15806                         error->plane[i].pos = I915_READ(DSPPOS(i));
15807                 }
15808                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15809                         error->plane[i].addr = I915_READ(DSPADDR(i));
15810                 if (INTEL_GEN(dev_priv) >= 4) {
15811                         error->plane[i].surface = I915_READ(DSPSURF(i));
15812                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15813                 }
15814
15815                 error->pipe[i].source = I915_READ(PIPESRC(i));
15816
15817                 if (HAS_GMCH_DISPLAY(dev_priv))
15818                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15819         }
15820
15821         /* Note: this does not include DSI transcoders. */
15822         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15823         if (HAS_DDI(dev_priv))
15824                 error->num_transcoders++; /* Account for eDP. */
15825
15826         for (i = 0; i < error->num_transcoders; i++) {
15827                 enum transcoder cpu_transcoder = transcoders[i];
15828
15829                 error->transcoder[i].power_domain_on =
15830                         __intel_display_power_is_enabled(dev_priv,
15831                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15832                 if (!error->transcoder[i].power_domain_on)
15833                         continue;
15834
15835                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15836
15837                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15838                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15839                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15840                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15841                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15842                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15843                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15844         }
15845
15846         return error;
15847 }
15848
15849 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15850
15851 void
15852 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15853                                 struct intel_display_error_state *error)
15854 {
15855         struct drm_i915_private *dev_priv = m->i915;
15856         int i;
15857
15858         if (!error)
15859                 return;
15860
15861         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15862         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15863                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15864                            error->power_well_driver);
15865         for_each_pipe(dev_priv, i) {
15866                 err_printf(m, "Pipe [%d]:\n", i);
15867                 err_printf(m, "  Power: %s\n",
15868                            onoff(error->pipe[i].power_domain_on));
15869                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15870                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15871
15872                 err_printf(m, "Plane [%d]:\n", i);
15873                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15874                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15875                 if (INTEL_GEN(dev_priv) <= 3) {
15876                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15877                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15878                 }
15879                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15880                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15881                 if (INTEL_GEN(dev_priv) >= 4) {
15882                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15883                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15884                 }
15885
15886                 err_printf(m, "Cursor [%d]:\n", i);
15887                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15888                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15889                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15890         }
15891
15892         for (i = 0; i < error->num_transcoders; i++) {
15893                 err_printf(m, "CPU transcoder: %s\n",
15894                            transcoder_name(error->transcoder[i].cpu_transcoder));
15895                 err_printf(m, "  Power: %s\n",
15896                            onoff(error->transcoder[i].power_domain_on));
15897                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15898                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15899                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15900                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15901                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15902                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15903                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15904         }
15905 }
15906
15907 #endif