drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 908000, .max = 1512000 },
  94         .n = { .min = 2, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 908000, .max = 1512000 },
 107         .n = { .min = 2, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 908000, .max = 1512000 },
 120         .n = { .min = 2, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         if (WARN_ON(clock->n == 0 || clock->p == 0))
 333                 return;
 334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 336 }
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 limit = &intel_limits_vlv;
 414         } else if (!IS_GEN2(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 416                         limit = &intel_limits_i9xx_lvds;
 417                 else
 418                         limit = &intel_limits_i9xx_sdvo;
 419         } else {
 420                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 421                         limit = &intel_limits_i8xx_lvds;
 422                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 423                         limit = &intel_limits_i8xx_dvo;
 424                 else
 425                         limit = &intel_limits_i8xx_dac;
 426         }
 427         return limit;
 428 }
 429
 430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 431 static void pineview_clock(int refclk, intel_clock_t *clock)
 432 {
 433         clock->m = clock->m2 + 2;
 434         clock->p = clock->p1 * clock->p2;
 435         if (WARN_ON(clock->n == 0 || clock->p == 0))
 436                 return;
 437         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 438         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 439 }
 440
 441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 442 {
 443         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 444 }
 445
 446 static void i9xx_clock(int refclk, intel_clock_t *clock)
 447 {
 448         clock->m = i9xx_dpll_compute_m(clock);
 449         clock->p = clock->p1 * clock->p2;
 450         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 451                 return;
 452         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 453         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 467                 INTELPllInvalid("n out of range\n");
 468         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 469                 INTELPllInvalid("p1 out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474
 475         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 476                 if (clock->m1 <= clock->m2)
 477                         INTELPllInvalid("m1 <= m2\n");
 478
 479         if (!IS_VALLEYVIEW(dev)) {
 480                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 481                         INTELPllInvalid("p out of range\n");
 482                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 483                         INTELPllInvalid("m out of range\n");
 484         }
 485
 486         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 487                 INTELPllInvalid("vco out of range\n");
 488         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 489          * connector, etc., rather than just a single range.
 490          */
 491         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 492                 INTELPllInvalid("dot out of range\n");
 493
 494         return true;
 495 }
 496
 497 static bool
 498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 499                     int target, int refclk, intel_clock_t *match_clock,
 500                     intel_clock_t *best_clock)
 501 {
 502         struct drm_device *dev = crtc->dev;
 503         intel_clock_t clock;
 504         int err = target;
 505
 506         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 507                 /*
 508                  * For LVDS just rely on its current settings for dual-channel.
 509                  * We haven't figured out how to reliably set up different
 510                  * single/dual channel state, if we even can.
 511                  */
 512                 if (intel_is_dual_link_lvds(dev))
 513                         clock.p2 = limit->p2.p2_fast;
 514                 else
 515                         clock.p2 = limit->p2.p2_slow;
 516         } else {
 517                 if (target < limit->p2.dot_limit)
 518                         clock.p2 = limit->p2.p2_slow;
 519                 else
 520                         clock.p2 = limit->p2.p2_fast;
 521         }
 522
 523         memset(best_clock, 0, sizeof(*best_clock));
 524
 525         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 526              clock.m1++) {
 527                 for (clock.m2 = limit->m2.min;
 528                      clock.m2 <= limit->m2.max; clock.m2++) {
 529                         if (clock.m2 >= clock.m1)
 530                                 break;
 531                         for (clock.n = limit->n.min;
 532                              clock.n <= limit->n.max; clock.n++) {
 533                                 for (clock.p1 = limit->p1.min;
 534                                         clock.p1 <= limit->p1.max; clock.p1++) {
 535                                         int this_err;
 536
 537                                         i9xx_clock(refclk, &clock);
 538                                         if (!intel_PLL_is_valid(dev, limit,
 539                                                                 &clock))
 540                                                 continue;
 541                                         if (match_clock &&
 542                                             clock.p != match_clock->p)
 543                                                 continue;
 544
 545                                         this_err = abs(clock.dot - target);
 546                                         if (this_err < err) {
 547                                                 *best_clock = clock;
 548                                                 err = this_err;
 549                                         }
 550                                 }
 551                         }
 552                 }
 553         }
 554
 555         return (err != target);
 556 }
 557
 558 static bool
 559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 560                    int target, int refclk, intel_clock_t *match_clock,
 561                    intel_clock_t *best_clock)
 562 {
 563         struct drm_device *dev = crtc->dev;
 564         intel_clock_t clock;
 565         int err = target;
 566
 567         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 568                 /*
 569                  * For LVDS just rely on its current settings for dual-channel.
 570                  * We haven't figured out how to reliably set up different
 571                  * single/dual channel state, if we even can.
 572                  */
 573                 if (intel_is_dual_link_lvds(dev))
 574                         clock.p2 = limit->p2.p2_fast;
 575                 else
 576                         clock.p2 = limit->p2.p2_slow;
 577         } else {
 578                 if (target < limit->p2.dot_limit)
 579                         clock.p2 = limit->p2.p2_slow;
 580                 else
 581                         clock.p2 = limit->p2.p2_fast;
 582         }
 583
 584         memset(best_clock, 0, sizeof(*best_clock));
 585
 586         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 587              clock.m1++) {
 588                 for (clock.m2 = limit->m2.min;
 589                      clock.m2 <= limit->m2.max; clock.m2++) {
 590                         for (clock.n = limit->n.min;
 591                              clock.n <= limit->n.max; clock.n++) {
 592                                 for (clock.p1 = limit->p1.min;
 593                                         clock.p1 <= limit->p1.max; clock.p1++) {
 594                                         int this_err;
 595
 596                                         pineview_clock(refclk, &clock);
 597                                         if (!intel_PLL_is_valid(dev, limit,
 598                                                                 &clock))
 599                                                 continue;
 600                                         if (match_clock &&
 601                                             clock.p != match_clock->p)
 602                                                 continue;
 603
 604                                         this_err = abs(clock.dot - target);
 605                                         if (this_err < err) {
 606                                                 *best_clock = clock;
 607                                                 err = this_err;
 608                                         }
 609                                 }
 610                         }
 611                 }
 612         }
 613
 614         return (err != target);
 615 }
 616
 617 static bool
 618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                    int target, int refclk, intel_clock_t *match_clock,
 620                    intel_clock_t *best_clock)
 621 {
 622         struct drm_device *dev = crtc->dev;
 623         intel_clock_t clock;
 624         int max_n;
 625         bool found;
 626         /* approximately equals target * 0.00585 */
 627         int err_most = (target >> 8) + (target >> 9);
 628         found = false;
 629
 630         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 631                 if (intel_is_dual_link_lvds(dev))
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         i9xx_clock(refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659
 660                                         this_err = abs(clock.dot - target);
 661                                         if (this_err < err_most) {
 662                                                 *best_clock = clock;
 663                                                 err_most = this_err;
 664                                                 max_n = clock.n;
 665                                                 found = true;
 666                                         }
 667                                 }
 668                         }
 669                 }
 670         }
 671         return found;
 672 }
 673
 674 static bool
 675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                    int target, int refclk, intel_clock_t *match_clock,
 677                    intel_clock_t *best_clock)
 678 {
 679         struct drm_device *dev = crtc->dev;
 680         intel_clock_t clock;
 681         unsigned int bestppm = 1000000;
 682         /* min update 19.2 MHz */
 683         int max_n = min(limit->n.max, refclk / 19200);
 684         bool found = false;
 685
 686         target *= 5; /* fast clock */
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         /* based on hardware requirement, prefer smaller n to precision */
 691         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 692                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 693                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 694                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 695                                 clock.p = clock.p1 * clock.p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 698                                         unsigned int ppm, diff;
 699
 700                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 701                                                                      refclk * clock.m1);
 702
 703                                         vlv_clock(refclk, &clock);
 704
 705                                         if (!intel_PLL_is_valid(dev, limit,
 706                                                                 &clock))
 707                                                 continue;
 708
 709                                         diff = abs(clock.dot - target);
 710                                         ppm = div_u64(1000000ULL * diff, target);
 711
 712                                         if (ppm < 100 && clock.p > best_clock->p) {
 713                                                 bestppm = 0;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717
 718                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 719                                                 bestppm = ppm;
 720                                                 *best_clock = clock;
 721                                                 found = true;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727
 728         return found;
 729 }
 730
 731 bool intel_crtc_active(struct drm_crtc *crtc)
 732 {
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         /* Be paranoid as we can arrive here with only partial
 736          * state retrieved from the hardware during setup.
 737          *
 738          * We can ditch the adjusted_mode.crtc_clock check as soon
 739          * as Haswell has gained clock readout/fastboot support.
 740          *
 741          * We can ditch the crtc->fb check as soon as we can
 742          * properly reconstruct framebuffers.
 743          */
 744         return intel_crtc->active && crtc->fb &&
 745                 intel_crtc->config.adjusted_mode.crtc_clock;
 746 }
 747
 748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 749                                              enum pipe pipe)
 750 {
 751         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 753
 754         return intel_crtc->config.cpu_transcoder;
 755 }
 756
 757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 761
 762         frame = I915_READ(frame_reg);
 763
 764         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 765                 DRM_DEBUG_KMS("vblank wait timed out\n");
 766 }
 767
 768 /**
 769  * intel_wait_for_vblank - wait for vblank on a given pipe
 770  * @dev: drm device
 771  * @pipe: pipe to wait for
 772  *
 773  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 774  * mode setting code.
 775  */
 776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         int pipestat_reg = PIPESTAT(pipe);
 780
 781         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 782                 g4x_wait_for_vblank(dev, pipe);
 783                 return;
 784         }
 785
 786         /* Clear existing vblank status. Note this will clear any other
 787          * sticky status fields as well.
 788          *
 789          * This races with i915_driver_irq_handler() with the result
 790          * that either function could miss a vblank event.  Here it is not
 791          * fatal, as we will either wait upon the next vblank interrupt or
 792          * timeout.  Generally speaking intel_wait_for_vblank() is only
 793          * called during modeset at which time the GPU should be idle and
 794          * should *not* be performing page flips and thus not waiting on
 795          * vblanks...
 796          * Currently, the result of us stealing a vblank from the irq
 797          * handler is that a single frame will be skipped during swapbuffers.
 798          */
 799         I915_WRITE(pipestat_reg,
 800                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 801
 802         /* Wait for vblank interrupt bit to set */
 803         if (wait_for(I915_READ(pipestat_reg) &
 804                      PIPE_VBLANK_INTERRUPT_STATUS,
 805                      50))
 806                 DRM_DEBUG_KMS("vblank wait timed out\n");
 807 }
 808
 809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         u32 reg = PIPEDSL(pipe);
 813         u32 line1, line2;
 814         u32 line_mask;
 815
 816         if (IS_GEN2(dev))
 817                 line_mask = DSL_LINEMASK_GEN2;
 818         else
 819                 line_mask = DSL_LINEMASK_GEN3;
 820
 821         line1 = I915_READ(reg) & line_mask;
 822         mdelay(5);
 823         line2 = I915_READ(reg) & line_mask;
 824
 825         return line1 == line2;
 826 }
 827
 828 /*
 829  * intel_wait_for_pipe_off - wait for pipe to turn off
 830  * @dev: drm device
 831  * @pipe: pipe to wait for
 832  *
 833  * After disabling a pipe, we can't wait for vblank in the usual way,
 834  * spinning on the vblank interrupt status bit, since we won't actually
 835  * see an interrupt when the pipe is disabled.
 836  *
 837  * On Gen4 and above:
 838  *   wait for the pipe register state bit to turn off
 839  *
 840  * Otherwise:
 841  *   wait for the display line value to settle (it usually
 842  *   ends up stopping at the start of the next frame).
 843  *
 844  */
 845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 849                                                                       pipe);
 850
 851         if (INTEL_INFO(dev)->gen >= 4) {
 852                 int reg = PIPECONF(cpu_transcoder);
 853
 854                 /* Wait for the Pipe State to go off */
 855                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 856                              100))
 857                         WARN(1, "pipe_off wait timed out\n");
 858         } else {
 859                 /* Wait for the display line to settle */
 860                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1220
1221         val = I915_READ(PCH_DREF_CONTROL);
1222         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1223                             DREF_SUPERSPREAD_SOURCE_MASK));
1224         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1225 }
1226
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228                                            enum pipe pipe)
1229 {
1230         int reg;
1231         u32 val;
1232         bool enabled;
1233
1234         reg = PCH_TRANSCONF(pipe);
1235         val = I915_READ(reg);
1236         enabled = !!(val & TRANS_ENABLE);
1237         WARN(enabled,
1238              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239              pipe_name(pipe));
1240 }
1241
1242 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1243                             enum pipe pipe, u32 port_sel, u32 val)
1244 {
1245         if ((val & DP_PORT_EN) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1250                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1251                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1252                         return false;
1253         } else {
1254                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1255                         return false;
1256         }
1257         return true;
1258 }
1259
1260 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1261                               enum pipe pipe, u32 val)
1262 {
1263         if ((val & SDVO_ENABLE) == 0)
1264                 return false;
1265
1266         if (HAS_PCH_CPT(dev_priv->dev)) {
1267                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1268                         return false;
1269         } else {
1270                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1271                         return false;
1272         }
1273         return true;
1274 }
1275
1276 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1277                               enum pipe pipe, u32 val)
1278 {
1279         if ((val & LVDS_PORT_EN) == 0)
1280                 return false;
1281
1282         if (HAS_PCH_CPT(dev_priv->dev)) {
1283                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284                         return false;
1285         } else {
1286                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1287                         return false;
1288         }
1289         return true;
1290 }
1291
1292 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1293                               enum pipe pipe, u32 val)
1294 {
1295         if ((val & ADPA_DAC_ENABLE) == 0)
1296                 return false;
1297         if (HAS_PCH_CPT(dev_priv->dev)) {
1298                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1299                         return false;
1300         } else {
1301                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1302                         return false;
1303         }
1304         return true;
1305 }
1306
1307 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1308                                    enum pipe pipe, int reg, u32 port_sel)
1309 {
1310         u32 val = I915_READ(reg);
1311         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1312              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313              reg, pipe_name(pipe));
1314
1315         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1316              && (val & DP_PIPEB_SELECT),
1317              "IBX PCH dp port still using transcoder B\n");
1318 }
1319
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1321                                      enum pipe pipe, int reg)
1322 {
1323         u32 val = I915_READ(reg);
1324         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1325              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326              reg, pipe_name(pipe));
1327
1328         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1329              && (val & SDVO_PIPE_B_SELECT),
1330              "IBX PCH hdmi port still using transcoder B\n");
1331 }
1332
1333 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1334                                       enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val;
1338
1339         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1340         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1341         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1342
1343         reg = PCH_ADPA;
1344         val = I915_READ(reg);
1345         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1346              "PCH VGA enabled on transcoder %c, should be disabled\n",
1347              pipe_name(pipe));
1348
1349         reg = PCH_LVDS;
1350         val = I915_READ(reg);
1351         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1352              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1353              pipe_name(pipe));
1354
1355         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1356         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1357         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1358 }
1359
1360 static void intel_init_dpio(struct drm_device *dev)
1361 {
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363
1364         if (!IS_VALLEYVIEW(dev))
1365                 return;
1366
1367         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1368 }
1369
1370 static void intel_reset_dpio(struct drm_device *dev)
1371 {
1372         struct drm_i915_private *dev_priv = dev->dev_private;
1373
1374         if (!IS_VALLEYVIEW(dev))
1375                 return;
1376
1377         /*
1378          * Enable the CRI clock source so we can get at the display and the
1379          * reference clock for VGA hotplug / manual detection.
1380          */
1381         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1382                    DPLL_REFA_CLK_ENABLE_VLV |
1383                    DPLL_INTEGRATED_CRI_CLK_VLV);
1384
1385         /*
1386          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1388          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389          *   b. The other bits such as sfr settings / modesel may all be set
1390          *      to 0.
1391          *
1392          * This should only be done on init and resume from S3 with both
1393          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1394          */
1395         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1396 }
1397
1398 static void vlv_enable_pll(struct intel_crtc *crtc)
1399 {
1400         struct drm_device *dev = crtc->base.dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402         int reg = DPLL(crtc->pipe);
1403         u32 dpll = crtc->config.dpll_hw_state.dpll;
1404
1405         assert_pipe_disabled(dev_priv, crtc->pipe);
1406
1407         /* No really, not for ILK+ */
1408         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1409
1410         /* PLL is protected by panel, make sure we can write it */
1411         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1412                 assert_panel_unlocked(dev_priv, crtc->pipe);
1413
1414         I915_WRITE(reg, dpll);
1415         POSTING_READ(reg);
1416         udelay(150);
1417
1418         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1419                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1420
1421         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1422         POSTING_READ(DPLL_MD(crtc->pipe));
1423
1424         /* We do this three times for luck */
1425         I915_WRITE(reg, dpll);
1426         POSTING_READ(reg);
1427         udelay(150); /* wait for warmup */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434 }
1435
1436 static void i9xx_enable_pll(struct intel_crtc *crtc)
1437 {
1438         struct drm_device *dev = crtc->base.dev;
1439         struct drm_i915_private *dev_priv = dev->dev_private;
1440         int reg = DPLL(crtc->pipe);
1441         u32 dpll = crtc->config.dpll_hw_state.dpll;
1442
1443         assert_pipe_disabled(dev_priv, crtc->pipe);
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(dev_priv->info->gen >= 5);
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev) && !IS_I830(dev))
1450                 assert_panel_unlocked(dev_priv, crtc->pipe);
1451
1452         I915_WRITE(reg, dpll);
1453
1454         /* Wait for the clocks to stabilize. */
1455         POSTING_READ(reg);
1456         udelay(150);
1457
1458         if (INTEL_INFO(dev)->gen >= 4) {
1459                 I915_WRITE(DPLL_MD(crtc->pipe),
1460                            crtc->config.dpll_hw_state.dpll_md);
1461         } else {
1462                 /* The pixel multiplier can only be updated once the
1463                  * DPLL is enabled and the clocks are stable.
1464                  *
1465                  * So write it again.
1466                  */
1467                 I915_WRITE(reg, dpll);
1468         }
1469
1470         /* We do this three times for luck */
1471         I915_WRITE(reg, dpll);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480 }
1481
1482 /**
1483  * i9xx_disable_pll - disable a PLL
1484  * @dev_priv: i915 private structure
1485  * @pipe: pipe PLL to disable
1486  *
1487  * Disable the PLL for @pipe, making sure the pipe is off first.
1488  *
1489  * Note!  This is for pre-ILK only.
1490  */
1491 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1492 {
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499
1500         I915_WRITE(DPLL(pipe), 0);
1501         POSTING_READ(DPLL(pipe));
1502 }
1503
1504 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505 {
1506         u32 val = 0;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         /*
1512          * Leave integrated clock source and reference clock enabled for pipe B.
1513          * The latter is needed for VGA hotplug / manual detection.
1514          */
1515         if (pipe == PIPE_B)
1516                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1517         I915_WRITE(DPLL(pipe), val);
1518         POSTING_READ(DPLL(pipe));
1519 }
1520
1521 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1522                 struct intel_digital_port *dport)
1523 {
1524         u32 port_mask;
1525
1526         switch (dport->port) {
1527         case PORT_B:
1528                 port_mask = DPLL_PORTB_READY_MASK;
1529                 break;
1530         case PORT_C:
1531                 port_mask = DPLL_PORTC_READY_MASK;
1532                 break;
1533         default:
1534                 BUG();
1535         }
1536
1537         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1538                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1539                      port_name(dport->port), I915_READ(DPLL(0)));
1540 }
1541
1542 /**
1543  * ironlake_enable_shared_dpll - enable PCH PLL
1544  * @dev_priv: i915 private structure
1545  * @pipe: pipe PLL to enable
1546  *
1547  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548  * drives the transcoder clock.
1549  */
1550 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1551 {
1552         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1553         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1554
1555         /* PCH PLLs only available on ILK, SNB and IVB */
1556         BUG_ON(dev_priv->info->gen < 5);
1557         if (WARN_ON(pll == NULL))
1558                 return;
1559
1560         if (WARN_ON(pll->refcount == 0))
1561                 return;
1562
1563         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1564                       pll->name, pll->active, pll->on,
1565                       crtc->base.base.id);
1566
1567         if (pll->active++) {
1568                 WARN_ON(!pll->on);
1569                 assert_shared_dpll_enabled(dev_priv, pll);
1570                 return;
1571         }
1572         WARN_ON(pll->on);
1573
1574         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1575         pll->enable(dev_priv, pll);
1576         pll->on = true;
1577 }
1578
1579 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1580 {
1581         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1582         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1583
1584         /* PCH only available on ILK+ */
1585         BUG_ON(dev_priv->info->gen < 5);
1586         if (WARN_ON(pll == NULL))
1587                return;
1588
1589         if (WARN_ON(pll->refcount == 0))
1590                 return;
1591
1592         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1593                       pll->name, pll->active, pll->on,
1594                       crtc->base.base.id);
1595
1596         if (WARN_ON(pll->active == 0)) {
1597                 assert_shared_dpll_disabled(dev_priv, pll);
1598                 return;
1599         }
1600
1601         assert_shared_dpll_enabled(dev_priv, pll);
1602         WARN_ON(!pll->on);
1603         if (--pll->active)
1604                 return;
1605
1606         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1607         pll->disable(dev_priv, pll);
1608         pll->on = false;
1609 }
1610
1611 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1612                                            enum pipe pipe)
1613 {
1614         struct drm_device *dev = dev_priv->dev;
1615         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1617         uint32_t reg, val, pipeconf_val;
1618
1619         /* PCH only available on ILK+ */
1620         BUG_ON(dev_priv->info->gen < 5);
1621
1622         /* Make sure PCH DPLL is enabled */
1623         assert_shared_dpll_enabled(dev_priv,
1624                                    intel_crtc_to_shared_dpll(intel_crtc));
1625
1626         /* FDI must be feeding us bits for PCH ports */
1627         assert_fdi_tx_enabled(dev_priv, pipe);
1628         assert_fdi_rx_enabled(dev_priv, pipe);
1629
1630         if (HAS_PCH_CPT(dev)) {
1631                 /* Workaround: Set the timing override bit before enabling the
1632                  * pch transcoder. */
1633                 reg = TRANS_CHICKEN2(pipe);
1634                 val = I915_READ(reg);
1635                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1636                 I915_WRITE(reg, val);
1637         }
1638
1639         reg = PCH_TRANSCONF(pipe);
1640         val = I915_READ(reg);
1641         pipeconf_val = I915_READ(PIPECONF(pipe));
1642
1643         if (HAS_PCH_IBX(dev_priv->dev)) {
1644                 /*
1645                  * make the BPC in transcoder be consistent with
1646                  * that in pipeconf reg.
1647                  */
1648                 val &= ~PIPECONF_BPC_MASK;
1649                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1650         }
1651
1652         val &= ~TRANS_INTERLACE_MASK;
1653         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1654                 if (HAS_PCH_IBX(dev_priv->dev) &&
1655                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1656                         val |= TRANS_LEGACY_INTERLACED_ILK;
1657                 else
1658                         val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(reg, val | TRANS_ENABLE);
1663         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1665 }
1666
1667 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                       enum transcoder cpu_transcoder)
1669 {
1670         u32 val, pipeconf_val;
1671
1672         /* PCH only available on ILK+ */
1673         BUG_ON(dev_priv->info->gen < 5);
1674
1675         /* FDI must be feeding us bits for PCH ports */
1676         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1677         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1678
1679         /* Workaround: set timing override bit. */
1680         val = I915_READ(_TRANSA_CHICKEN2);
1681         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1682         I915_WRITE(_TRANSA_CHICKEN2, val);
1683
1684         val = TRANS_ENABLE;
1685         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1686
1687         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1688             PIPECONF_INTERLACED_ILK)
1689                 val |= TRANS_INTERLACED;
1690         else
1691                 val |= TRANS_PROGRESSIVE;
1692
1693         I915_WRITE(LPT_TRANSCONF, val);
1694         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1695                 DRM_ERROR("Failed to enable PCH transcoder\n");
1696 }
1697
1698 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1699                                             enum pipe pipe)
1700 {
1701         struct drm_device *dev = dev_priv->dev;
1702         uint32_t reg, val;
1703
1704         /* FDI relies on the transcoder */
1705         assert_fdi_tx_disabled(dev_priv, pipe);
1706         assert_fdi_rx_disabled(dev_priv, pipe);
1707
1708         /* Ports must be off as well */
1709         assert_pch_ports_disabled(dev_priv, pipe);
1710
1711         reg = PCH_TRANSCONF(pipe);
1712         val = I915_READ(reg);
1713         val &= ~TRANS_ENABLE;
1714         I915_WRITE(reg, val);
1715         /* wait for PCH transcoder off, transcoder state */
1716         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1717                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1718
1719         if (!HAS_PCH_IBX(dev)) {
1720                 /* Workaround: Clear the timing override chicken bit again. */
1721                 reg = TRANS_CHICKEN2(pipe);
1722                 val = I915_READ(reg);
1723                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1724                 I915_WRITE(reg, val);
1725         }
1726 }
1727
1728 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1729 {
1730         u32 val;
1731
1732         val = I915_READ(LPT_TRANSCONF);
1733         val &= ~TRANS_ENABLE;
1734         I915_WRITE(LPT_TRANSCONF, val);
1735         /* wait for PCH transcoder off, transcoder state */
1736         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1737                 DRM_ERROR("Failed to disable PCH transcoder\n");
1738
1739         /* Workaround: clear timing override bit. */
1740         val = I915_READ(_TRANSA_CHICKEN2);
1741         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1742         I915_WRITE(_TRANSA_CHICKEN2, val);
1743 }
1744
1745 /**
1746  * intel_enable_pipe - enable a pipe, asserting requirements
1747  * @dev_priv: i915 private structure
1748  * @pipe: pipe to enable
1749  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1750  *
1751  * Enable @pipe, making sure that various hardware specific requirements
1752  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1753  *
1754  * @pipe should be %PIPE_A or %PIPE_B.
1755  *
1756  * Will wait until the pipe is actually running (i.e. first vblank) before
1757  * returning.
1758  */
1759 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1760                               bool pch_port, bool dsi)
1761 {
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (dsi)
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (pch_port) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE)
1800                 return;
1801
1802         I915_WRITE(reg, val | PIPECONF_ENABLE);
1803         intel_wait_for_vblank(dev_priv->dev, pipe);
1804 }
1805
1806 /**
1807  * intel_disable_pipe - disable a pipe, asserting requirements
1808  * @dev_priv: i915 private structure
1809  * @pipe: pipe to disable
1810  *
1811  * Disable @pipe, making sure that various hardware specific requirements
1812  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1813  *
1814  * @pipe should be %PIPE_A or %PIPE_B.
1815  *
1816  * Will wait until the pipe has shut down before returning.
1817  */
1818 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1819                                enum pipe pipe)
1820 {
1821         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1822                                                                       pipe);
1823         int reg;
1824         u32 val;
1825
1826         /*
1827          * Make sure planes won't keep trying to pump pixels to us,
1828          * or we might hang the display.
1829          */
1830         assert_planes_disabled(dev_priv, pipe);
1831         assert_cursor_disabled(dev_priv, pipe);
1832         assert_sprites_disabled(dev_priv, pipe);
1833
1834         /* Don't disable pipe A or pipe A PLLs if needed */
1835         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1836                 return;
1837
1838         reg = PIPECONF(cpu_transcoder);
1839         val = I915_READ(reg);
1840         if ((val & PIPECONF_ENABLE) == 0)
1841                 return;
1842
1843         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1844         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1845 }
1846
1847 /*
1848  * Plane regs are double buffered, going from enabled->disabled needs a
1849  * trigger in order to latch.  The display address reg provides this.
1850  */
1851 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1852                                enum plane plane)
1853 {
1854         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1855
1856         I915_WRITE(reg, I915_READ(reg));
1857         POSTING_READ(reg);
1858 }
1859
1860 /**
1861  * intel_enable_primary_plane - enable the primary plane on a given pipe
1862  * @dev_priv: i915 private structure
1863  * @plane: plane to enable
1864  * @pipe: pipe being fed
1865  *
1866  * Enable @plane on @pipe, making sure that @pipe is running first.
1867  */
1868 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1869                                        enum plane plane, enum pipe pipe)
1870 {
1871         struct intel_crtc *intel_crtc =
1872                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1873         int reg;
1874         u32 val;
1875
1876         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1877         assert_pipe_enabled(dev_priv, pipe);
1878
1879         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1880
1881         intel_crtc->primary_enabled = true;
1882
1883         reg = DSPCNTR(plane);
1884         val = I915_READ(reg);
1885         if (val & DISPLAY_PLANE_ENABLE)
1886                 return;
1887
1888         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1889         intel_flush_primary_plane(dev_priv, plane);
1890         intel_wait_for_vblank(dev_priv->dev, pipe);
1891 }
1892
1893 /**
1894  * intel_disable_primary_plane - disable the primary plane
1895  * @dev_priv: i915 private structure
1896  * @plane: plane to disable
1897  * @pipe: pipe consuming the data
1898  *
1899  * Disable @plane; should be an independent operation.
1900  */
1901 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1902                                         enum plane plane, enum pipe pipe)
1903 {
1904         struct intel_crtc *intel_crtc =
1905                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1906         int reg;
1907         u32 val;
1908
1909         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1910
1911         intel_crtc->primary_enabled = false;
1912
1913         reg = DSPCNTR(plane);
1914         val = I915_READ(reg);
1915         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1916                 return;
1917
1918         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1919         intel_flush_primary_plane(dev_priv, plane);
1920         intel_wait_for_vblank(dev_priv->dev, pipe);
1921 }
1922
1923 static bool need_vtd_wa(struct drm_device *dev)
1924 {
1925 #ifdef CONFIG_INTEL_IOMMU
1926         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1927                 return true;
1928 #endif
1929         return false;
1930 }
1931
1932 int
1933 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1934                            struct drm_i915_gem_object *obj,
1935                            struct intel_ring_buffer *pipelined)
1936 {
1937         struct drm_i915_private *dev_priv = dev->dev_private;
1938         u32 alignment;
1939         int ret;
1940
1941         switch (obj->tiling_mode) {
1942         case I915_TILING_NONE:
1943                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1944                         alignment = 128 * 1024;
1945                 else if (INTEL_INFO(dev)->gen >= 4)
1946                         alignment = 4 * 1024;
1947                 else
1948                         alignment = 64 * 1024;
1949                 break;
1950         case I915_TILING_X:
1951                 /* pin() will align the object as required by fence */
1952                 alignment = 0;
1953                 break;
1954         case I915_TILING_Y:
1955                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1956                 return -EINVAL;
1957         default:
1958                 BUG();
1959         }
1960
1961         /* Note that the w/a also requires 64 PTE of padding following the
1962          * bo. We currently fill all unused PTE with the shadow page and so
1963          * we should always have valid PTE following the scanout preventing
1964          * the VT-d warning.
1965          */
1966         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1967                 alignment = 256 * 1024;
1968
1969         dev_priv->mm.interruptible = false;
1970         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1971         if (ret)
1972                 goto err_interruptible;
1973
1974         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1975          * fence, whereas 965+ only requires a fence if using
1976          * framebuffer compression.  For simplicity, we always install
1977          * a fence as the cost is not that onerous.
1978          */
1979         ret = i915_gem_object_get_fence(obj);
1980         if (ret)
1981                 goto err_unpin;
1982
1983         i915_gem_object_pin_fence(obj);
1984
1985         dev_priv->mm.interruptible = true;
1986         return 0;
1987
1988 err_unpin:
1989         i915_gem_object_unpin_from_display_plane(obj);
1990 err_interruptible:
1991         dev_priv->mm.interruptible = true;
1992         return ret;
1993 }
1994
1995 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1996 {
1997         i915_gem_object_unpin_fence(obj);
1998         i915_gem_object_unpin_from_display_plane(obj);
1999 }
2000
2001 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2002  * is assumed to be a power-of-two. */
2003 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2004                                              unsigned int tiling_mode,
2005                                              unsigned int cpp,
2006                                              unsigned int pitch)
2007 {
2008         if (tiling_mode != I915_TILING_NONE) {
2009                 unsigned int tile_rows, tiles;
2010
2011                 tile_rows = *y / 8;
2012                 *y %= 8;
2013
2014                 tiles = *x / (512/cpp);
2015                 *x %= 512/cpp;
2016
2017                 return tile_rows * pitch * 8 + tiles * 4096;
2018         } else {
2019                 unsigned int offset;
2020
2021                 offset = *y * pitch + *x * cpp;
2022                 *y = 0;
2023                 *x = (offset & 4095) / cpp;
2024                 return offset & -4096;
2025         }
2026 }
2027
2028 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2029                              int x, int y)
2030 {
2031         struct drm_device *dev = crtc->dev;
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2034         struct intel_framebuffer *intel_fb;
2035         struct drm_i915_gem_object *obj;
2036         int plane = intel_crtc->plane;
2037         unsigned long linear_offset;
2038         u32 dspcntr;
2039         u32 reg;
2040
2041         switch (plane) {
2042         case 0:
2043         case 1:
2044                 break;
2045         default:
2046                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2047                 return -EINVAL;
2048         }
2049
2050         intel_fb = to_intel_framebuffer(fb);
2051         obj = intel_fb->obj;
2052
2053         reg = DSPCNTR(plane);
2054         dspcntr = I915_READ(reg);
2055         /* Mask out pixel format bits in case we change it */
2056         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2057         switch (fb->pixel_format) {
2058         case DRM_FORMAT_C8:
2059                 dspcntr |= DISPPLANE_8BPP;
2060                 break;
2061         case DRM_FORMAT_XRGB1555:
2062         case DRM_FORMAT_ARGB1555:
2063                 dspcntr |= DISPPLANE_BGRX555;
2064                 break;
2065         case DRM_FORMAT_RGB565:
2066                 dspcntr |= DISPPLANE_BGRX565;
2067                 break;
2068         case DRM_FORMAT_XRGB8888:
2069         case DRM_FORMAT_ARGB8888:
2070                 dspcntr |= DISPPLANE_BGRX888;
2071                 break;
2072         case DRM_FORMAT_XBGR8888:
2073         case DRM_FORMAT_ABGR8888:
2074                 dspcntr |= DISPPLANE_RGBX888;
2075                 break;
2076         case DRM_FORMAT_XRGB2101010:
2077         case DRM_FORMAT_ARGB2101010:
2078                 dspcntr |= DISPPLANE_BGRX101010;
2079                 break;
2080         case DRM_FORMAT_XBGR2101010:
2081         case DRM_FORMAT_ABGR2101010:
2082                 dspcntr |= DISPPLANE_RGBX101010;
2083                 break;
2084         default:
2085                 BUG();
2086         }
2087
2088         if (INTEL_INFO(dev)->gen >= 4) {
2089                 if (obj->tiling_mode != I915_TILING_NONE)
2090                         dspcntr |= DISPPLANE_TILED;
2091                 else
2092                         dspcntr &= ~DISPPLANE_TILED;
2093         }
2094
2095         if (IS_G4X(dev))
2096                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101
2102         if (INTEL_INFO(dev)->gen >= 4) {
2103                 intel_crtc->dspaddr_offset =
2104                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2105                                                        fb->bits_per_pixel / 8,
2106                                                        fb->pitches[0]);
2107                 linear_offset -= intel_crtc->dspaddr_offset;
2108         } else {
2109                 intel_crtc->dspaddr_offset = linear_offset;
2110         }
2111
2112         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2113                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2114                       fb->pitches[0]);
2115         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2116         if (INTEL_INFO(dev)->gen >= 4) {
2117                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2118                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2119                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2120                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2121         } else
2122                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2123         POSTING_READ(reg);
2124
2125         return 0;
2126 }
2127
2128 static int ironlake_update_plane(struct drm_crtc *crtc,
2129                                  struct drm_framebuffer *fb, int x, int y)
2130 {
2131         struct drm_device *dev = crtc->dev;
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134         struct intel_framebuffer *intel_fb;
2135         struct drm_i915_gem_object *obj;
2136         int plane = intel_crtc->plane;
2137         unsigned long linear_offset;
2138         u32 dspcntr;
2139         u32 reg;
2140
2141         switch (plane) {
2142         case 0:
2143         case 1:
2144         case 2:
2145                 break;
2146         default:
2147                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2148                 return -EINVAL;
2149         }
2150
2151         intel_fb = to_intel_framebuffer(fb);
2152         obj = intel_fb->obj;
2153
2154         reg = DSPCNTR(plane);
2155         dspcntr = I915_READ(reg);
2156         /* Mask out pixel format bits in case we change it */
2157         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2158         switch (fb->pixel_format) {
2159         case DRM_FORMAT_C8:
2160                 dspcntr |= DISPPLANE_8BPP;
2161                 break;
2162         case DRM_FORMAT_RGB565:
2163                 dspcntr |= DISPPLANE_BGRX565;
2164                 break;
2165         case DRM_FORMAT_XRGB8888:
2166         case DRM_FORMAT_ARGB8888:
2167                 dspcntr |= DISPPLANE_BGRX888;
2168                 break;
2169         case DRM_FORMAT_XBGR8888:
2170         case DRM_FORMAT_ABGR8888:
2171                 dspcntr |= DISPPLANE_RGBX888;
2172                 break;
2173         case DRM_FORMAT_XRGB2101010:
2174         case DRM_FORMAT_ARGB2101010:
2175                 dspcntr |= DISPPLANE_BGRX101010;
2176                 break;
2177         case DRM_FORMAT_XBGR2101010:
2178         case DRM_FORMAT_ABGR2101010:
2179                 dspcntr |= DISPPLANE_RGBX101010;
2180                 break;
2181         default:
2182                 BUG();
2183         }
2184
2185         if (obj->tiling_mode != I915_TILING_NONE)
2186                 dspcntr |= DISPPLANE_TILED;
2187         else
2188                 dspcntr &= ~DISPPLANE_TILED;
2189
2190         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2191                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2192         else
2193                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2194
2195         I915_WRITE(reg, dspcntr);
2196
2197         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2198         intel_crtc->dspaddr_offset =
2199                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2200                                                fb->bits_per_pixel / 8,
2201                                                fb->pitches[0]);
2202         linear_offset -= intel_crtc->dspaddr_offset;
2203
2204         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2206                       fb->pitches[0]);
2207         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2208         I915_MODIFY_DISPBASE(DSPSURF(plane),
2209                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2210         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2211                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2212         } else {
2213                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2215         }
2216         POSTING_READ(reg);
2217
2218         return 0;
2219 }
2220
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2222 static int
2223 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224                            int x, int y, enum mode_set_atomic state)
2225 {
2226         struct drm_device *dev = crtc->dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229         if (dev_priv->display.disable_fbc)
2230                 dev_priv->display.disable_fbc(dev);
2231         intel_increase_pllclock(crtc);
2232
2233         return dev_priv->display.update_plane(crtc, fb, x, y);
2234 }
2235
2236 void intel_display_handle_reset(struct drm_device *dev)
2237 {
2238         struct drm_i915_private *dev_priv = dev->dev_private;
2239         struct drm_crtc *crtc;
2240
2241         /*
2242          * Flips in the rings have been nuked by the reset,
2243          * so complete all pending flips so that user space
2244          * will get its events and not get stuck.
2245          *
2246          * Also update the base address of all primary
2247          * planes to the the last fb to make sure we're
2248          * showing the correct fb after a reset.
2249          *
2250          * Need to make two loops over the crtcs so that we
2251          * don't try to grab a crtc mutex before the
2252          * pending_flip_queue really got woken up.
2253          */
2254
2255         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2256                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257                 enum plane plane = intel_crtc->plane;
2258
2259                 intel_prepare_page_flip(dev, plane);
2260                 intel_finish_page_flip_plane(dev, plane);
2261         }
2262
2263         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2264                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266                 mutex_lock(&crtc->mutex);
2267                 /*
2268                  * FIXME: Once we have proper support for primary planes (and
2269                  * disabling them without disabling the entire crtc) allow again
2270                  * a NULL crtc->fb.
2271                  */
2272                 if (intel_crtc->active && crtc->fb)
2273                         dev_priv->display.update_plane(crtc, crtc->fb,
2274                                                        crtc->x, crtc->y);
2275                 mutex_unlock(&crtc->mutex);
2276         }
2277 }
2278
2279 static int
2280 intel_finish_fb(struct drm_framebuffer *old_fb)
2281 {
2282         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2283         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2284         bool was_interruptible = dev_priv->mm.interruptible;
2285         int ret;
2286
2287         /* Big Hammer, we also need to ensure that any pending
2288          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2289          * current scanout is retired before unpinning the old
2290          * framebuffer.
2291          *
2292          * This should only fail upon a hung GPU, in which case we
2293          * can safely continue.
2294          */
2295         dev_priv->mm.interruptible = false;
2296         ret = i915_gem_object_finish_gpu(obj);
2297         dev_priv->mm.interruptible = was_interruptible;
2298
2299         return ret;
2300 }
2301
2302 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2303 {
2304         struct drm_device *dev = crtc->dev;
2305         struct drm_i915_master_private *master_priv;
2306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307
2308         if (!dev->primary->master)
2309                 return;
2310
2311         master_priv = dev->primary->master->driver_priv;
2312         if (!master_priv->sarea_priv)
2313                 return;
2314
2315         switch (intel_crtc->pipe) {
2316         case 0:
2317                 master_priv->sarea_priv->pipeA_x = x;
2318                 master_priv->sarea_priv->pipeA_y = y;
2319                 break;
2320         case 1:
2321                 master_priv->sarea_priv->pipeB_x = x;
2322                 master_priv->sarea_priv->pipeB_y = y;
2323                 break;
2324         default:
2325                 break;
2326         }
2327 }
2328
2329 static int
2330 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2331                     struct drm_framebuffer *fb)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         struct drm_framebuffer *old_fb;
2337         int ret;
2338
2339         /* no fb bound */
2340         if (!fb) {
2341                 DRM_ERROR("No FB bound\n");
2342                 return 0;
2343         }
2344
2345         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2346                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2347                           plane_name(intel_crtc->plane),
2348                           INTEL_INFO(dev)->num_pipes);
2349                 return -EINVAL;
2350         }
2351
2352         mutex_lock(&dev->struct_mutex);
2353         ret = intel_pin_and_fence_fb_obj(dev,
2354                                          to_intel_framebuffer(fb)->obj,
2355                                          NULL);
2356         if (ret != 0) {
2357                 mutex_unlock(&dev->struct_mutex);
2358                 DRM_ERROR("pin & fence failed\n");
2359                 return ret;
2360         }
2361
2362         /*
2363          * Update pipe size and adjust fitter if needed: the reason for this is
2364          * that in compute_mode_changes we check the native mode (not the pfit
2365          * mode) to see if we can flip rather than do a full mode set. In the
2366          * fastboot case, we'll flip, but if we don't update the pipesrc and
2367          * pfit state, we'll end up with a big fb scanned out into the wrong
2368          * sized surface.
2369          *
2370          * To fix this properly, we need to hoist the checks up into
2371          * compute_mode_changes (or above), check the actual pfit state and
2372          * whether the platform allows pfit disable with pipe active, and only
2373          * then update the pipesrc and pfit state, even on the flip path.
2374          */
2375         if (i915_fastboot) {
2376                 const struct drm_display_mode *adjusted_mode =
2377                         &intel_crtc->config.adjusted_mode;
2378
2379                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2380                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2381                            (adjusted_mode->crtc_vdisplay - 1));
2382                 if (!intel_crtc->config.pch_pfit.enabled &&
2383                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2384                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2385                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2386                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2387                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2388                 }
2389                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2390                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2391         }
2392
2393         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2394         if (ret) {
2395                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2396                 mutex_unlock(&dev->struct_mutex);
2397                 DRM_ERROR("failed to update base address\n");
2398                 return ret;
2399         }
2400
2401         old_fb = crtc->fb;
2402         crtc->fb = fb;
2403         crtc->x = x;
2404         crtc->y = y;
2405
2406         if (old_fb) {
2407                 if (intel_crtc->active && old_fb != fb)
2408                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2409                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2410         }
2411
2412         intel_update_fbc(dev);
2413         intel_edp_psr_update(dev);
2414         mutex_unlock(&dev->struct_mutex);
2415
2416         intel_crtc_update_sarea_pos(crtc, x, y);
2417
2418         return 0;
2419 }
2420
2421 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         int pipe = intel_crtc->pipe;
2427         u32 reg, temp;
2428
2429         /* enable normal train */
2430         reg = FDI_TX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         if (IS_IVYBRIDGE(dev)) {
2433                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2434                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2435         } else {
2436                 temp &= ~FDI_LINK_TRAIN_NONE;
2437                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2438         }
2439         I915_WRITE(reg, temp);
2440
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         if (HAS_PCH_CPT(dev)) {
2444                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2446         } else {
2447                 temp &= ~FDI_LINK_TRAIN_NONE;
2448                 temp |= FDI_LINK_TRAIN_NONE;
2449         }
2450         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2451
2452         /* wait one idle pattern time */
2453         POSTING_READ(reg);
2454         udelay(1000);
2455
2456         /* IVB wants error correction enabled */
2457         if (IS_IVYBRIDGE(dev))
2458                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2459                            FDI_FE_ERRC_ENABLE);
2460 }
2461
2462 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2463 {
2464         return crtc->base.enabled && crtc->active &&
2465                 crtc->config.has_pch_encoder;
2466 }
2467
2468 static void ivb_modeset_global_resources(struct drm_device *dev)
2469 {
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *pipe_B_crtc =
2472                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473         struct intel_crtc *pipe_C_crtc =
2474                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475         uint32_t temp;
2476
2477         /*
2478          * When everything is off disable fdi C so that we could enable fdi B
2479          * with all lanes. Note that we don't care about enabled pipes without
2480          * an enabled pch encoder.
2481          */
2482         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2483             !pipe_has_enabled_pch(pipe_C_crtc)) {
2484                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2485                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2486
2487                 temp = I915_READ(SOUTH_CHICKEN1);
2488                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2489                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2490                 I915_WRITE(SOUTH_CHICKEN1, temp);
2491         }
2492 }
2493
2494 /* The FDI link training functions for ILK/Ibexpeak. */
2495 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2496 {
2497         struct drm_device *dev = crtc->dev;
2498         struct drm_i915_private *dev_priv = dev->dev_private;
2499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500         int pipe = intel_crtc->pipe;
2501         int plane = intel_crtc->plane;
2502         u32 reg, temp, tries;
2503
2504         /* FDI needs bits from pipe & plane first */
2505         assert_pipe_enabled(dev_priv, pipe);
2506         assert_plane_enabled(dev_priv, plane);
2507
2508         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509            for train result */
2510         reg = FDI_RX_IMR(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_RX_SYMBOL_LOCK;
2513         temp &= ~FDI_RX_BIT_LOCK;
2514         I915_WRITE(reg, temp);
2515         I915_READ(reg);
2516         udelay(150);
2517
2518         /* enable CPU FDI TX and PCH FDI RX */
2519         reg = FDI_TX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2522         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_1;
2525         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2526
2527         reg = FDI_RX_CTL(pipe);
2528         temp = I915_READ(reg);
2529         temp &= ~FDI_LINK_TRAIN_NONE;
2530         temp |= FDI_LINK_TRAIN_PATTERN_1;
2531         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2532
2533         POSTING_READ(reg);
2534         udelay(150);
2535
2536         /* Ironlake workaround, enable clock pointer after FDI enable*/
2537         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2538         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2539                    FDI_RX_PHASE_SYNC_POINTER_EN);
2540
2541         reg = FDI_RX_IIR(pipe);
2542         for (tries = 0; tries < 5; tries++) {
2543                 temp = I915_READ(reg);
2544                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546                 if ((temp & FDI_RX_BIT_LOCK)) {
2547                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2548                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549                         break;
2550                 }
2551         }
2552         if (tries == 5)
2553                 DRM_ERROR("FDI train 1 fail!\n");
2554
2555         /* Train 2 */
2556         reg = FDI_TX_CTL(pipe);
2557         temp = I915_READ(reg);
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_2;
2560         I915_WRITE(reg, temp);
2561
2562         reg = FDI_RX_CTL(pipe);
2563         temp = I915_READ(reg);
2564         temp &= ~FDI_LINK_TRAIN_NONE;
2565         temp |= FDI_LINK_TRAIN_PATTERN_2;
2566         I915_WRITE(reg, temp);
2567
2568         POSTING_READ(reg);
2569         udelay(150);
2570
2571         reg = FDI_RX_IIR(pipe);
2572         for (tries = 0; tries < 5; tries++) {
2573                 temp = I915_READ(reg);
2574                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575
2576                 if (temp & FDI_RX_SYMBOL_LOCK) {
2577                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2578                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2579                         break;
2580                 }
2581         }
2582         if (tries == 5)
2583                 DRM_ERROR("FDI train 2 fail!\n");
2584
2585         DRM_DEBUG_KMS("FDI train done\n");
2586
2587 }
2588
2589 static const int snb_b_fdi_train_param[] = {
2590         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2591         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2592         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2593         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2594 };
2595
2596 /* The FDI link training functions for SNB/Cougarpoint. */
2597 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2598 {
2599         struct drm_device *dev = crtc->dev;
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602         int pipe = intel_crtc->pipe;
2603         u32 reg, temp, i, retry;
2604
2605         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606            for train result */
2607         reg = FDI_RX_IMR(pipe);
2608         temp = I915_READ(reg);
2609         temp &= ~FDI_RX_SYMBOL_LOCK;
2610         temp &= ~FDI_RX_BIT_LOCK;
2611         I915_WRITE(reg, temp);
2612
2613         POSTING_READ(reg);
2614         udelay(150);
2615
2616         /* enable CPU FDI TX and PCH FDI RX */
2617         reg = FDI_TX_CTL(pipe);
2618         temp = I915_READ(reg);
2619         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2620         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2621         temp &= ~FDI_LINK_TRAIN_NONE;
2622         temp |= FDI_LINK_TRAIN_PATTERN_1;
2623         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624         /* SNB-B */
2625         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2626         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628         I915_WRITE(FDI_RX_MISC(pipe),
2629                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2630
2631         reg = FDI_RX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         if (HAS_PCH_CPT(dev)) {
2634                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636         } else {
2637                 temp &= ~FDI_LINK_TRAIN_NONE;
2638                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2639         }
2640         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642         POSTING_READ(reg);
2643         udelay(150);
2644
2645         for (i = 0; i < 4; i++) {
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 temp |= snb_b_fdi_train_param[i];
2650                 I915_WRITE(reg, temp);
2651
2652                 POSTING_READ(reg);
2653                 udelay(500);
2654
2655                 for (retry = 0; retry < 5; retry++) {
2656                         reg = FDI_RX_IIR(pipe);
2657                         temp = I915_READ(reg);
2658                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2659                         if (temp & FDI_RX_BIT_LOCK) {
2660                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662                                 break;
2663                         }
2664                         udelay(50);
2665                 }
2666                 if (retry < 5)
2667                         break;
2668         }
2669         if (i == 4)
2670                 DRM_ERROR("FDI train 1 fail!\n");
2671
2672         /* Train 2 */
2673         reg = FDI_TX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_NONE;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2;
2677         if (IS_GEN6(dev)) {
2678                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679                 /* SNB-B */
2680                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2681         }
2682         I915_WRITE(reg, temp);
2683
2684         reg = FDI_RX_CTL(pipe);
2685         temp = I915_READ(reg);
2686         if (HAS_PCH_CPT(dev)) {
2687                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2688                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2689         } else {
2690                 temp &= ~FDI_LINK_TRAIN_NONE;
2691                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2692         }
2693         I915_WRITE(reg, temp);
2694
2695         POSTING_READ(reg);
2696         udelay(150);
2697
2698         for (i = 0; i < 4; i++) {
2699                 reg = FDI_TX_CTL(pipe);
2700                 temp = I915_READ(reg);
2701                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2702                 temp |= snb_b_fdi_train_param[i];
2703                 I915_WRITE(reg, temp);
2704
2705                 POSTING_READ(reg);
2706                 udelay(500);
2707
2708                 for (retry = 0; retry < 5; retry++) {
2709                         reg = FDI_RX_IIR(pipe);
2710                         temp = I915_READ(reg);
2711                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2712                         if (temp & FDI_RX_SYMBOL_LOCK) {
2713                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2714                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2715                                 break;
2716                         }
2717                         udelay(50);
2718                 }
2719                 if (retry < 5)
2720                         break;
2721         }
2722         if (i == 4)
2723                 DRM_ERROR("FDI train 2 fail!\n");
2724
2725         DRM_DEBUG_KMS("FDI train done.\n");
2726 }
2727
2728 /* Manual link training for Ivy Bridge A0 parts */
2729 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2730 {
2731         struct drm_device *dev = crtc->dev;
2732         struct drm_i915_private *dev_priv = dev->dev_private;
2733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2734         int pipe = intel_crtc->pipe;
2735         u32 reg, temp, i, j;
2736
2737         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2738            for train result */
2739         reg = FDI_RX_IMR(pipe);
2740         temp = I915_READ(reg);
2741         temp &= ~FDI_RX_SYMBOL_LOCK;
2742         temp &= ~FDI_RX_BIT_LOCK;
2743         I915_WRITE(reg, temp);
2744
2745         POSTING_READ(reg);
2746         udelay(150);
2747
2748         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2749                       I915_READ(FDI_RX_IIR(pipe)));
2750
2751         /* Try each vswing and preemphasis setting twice before moving on */
2752         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2753                 /* disable first in case we need to retry */
2754                 reg = FDI_TX_CTL(pipe);
2755                 temp = I915_READ(reg);
2756                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2757                 temp &= ~FDI_TX_ENABLE;
2758                 I915_WRITE(reg, temp);
2759
2760                 reg = FDI_RX_CTL(pipe);
2761                 temp = I915_READ(reg);
2762                 temp &= ~FDI_LINK_TRAIN_AUTO;
2763                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2764                 temp &= ~FDI_RX_ENABLE;
2765                 I915_WRITE(reg, temp);
2766
2767                 /* enable CPU FDI TX and PCH FDI RX */
2768                 reg = FDI_TX_CTL(pipe);
2769                 temp = I915_READ(reg);
2770                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2771                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2772                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2773                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2774                 temp |= snb_b_fdi_train_param[j/2];
2775                 temp |= FDI_COMPOSITE_SYNC;
2776                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2777
2778                 I915_WRITE(FDI_RX_MISC(pipe),
2779                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2780
2781                 reg = FDI_RX_CTL(pipe);
2782                 temp = I915_READ(reg);
2783                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2784                 temp |= FDI_COMPOSITE_SYNC;
2785                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2786
2787                 POSTING_READ(reg);
2788                 udelay(1); /* should be 0.5us */
2789
2790                 for (i = 0; i < 4; i++) {
2791                         reg = FDI_RX_IIR(pipe);
2792                         temp = I915_READ(reg);
2793                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795                         if (temp & FDI_RX_BIT_LOCK ||
2796                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2797                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2798                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2799                                               i);
2800                                 break;
2801                         }
2802                         udelay(1); /* should be 0.5us */
2803                 }
2804                 if (i == 4) {
2805                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2806                         continue;
2807                 }
2808
2809                 /* Train 2 */
2810                 reg = FDI_TX_CTL(pipe);
2811                 temp = I915_READ(reg);
2812                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2813                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2814                 I915_WRITE(reg, temp);
2815
2816                 reg = FDI_RX_CTL(pipe);
2817                 temp = I915_READ(reg);
2818                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2820                 I915_WRITE(reg, temp);
2821
2822                 POSTING_READ(reg);
2823                 udelay(2); /* should be 1.5us */
2824
2825                 for (i = 0; i < 4; i++) {
2826                         reg = FDI_RX_IIR(pipe);
2827                         temp = I915_READ(reg);
2828                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830                         if (temp & FDI_RX_SYMBOL_LOCK ||
2831                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2832                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2833                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2834                                               i);
2835                                 goto train_done;
2836                         }
2837                         udelay(2); /* should be 1.5us */
2838                 }
2839                 if (i == 4)
2840                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2841         }
2842
2843 train_done:
2844         DRM_DEBUG_KMS("FDI train done.\n");
2845 }
2846
2847 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2848 {
2849         struct drm_device *dev = intel_crtc->base.dev;
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         int pipe = intel_crtc->pipe;
2852         u32 reg, temp;
2853
2854
2855         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2856         reg = FDI_RX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2859         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2860         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2862
2863         POSTING_READ(reg);
2864         udelay(200);
2865
2866         /* Switch from Rawclk to PCDclk */
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp | FDI_PCDCLK);
2869
2870         POSTING_READ(reg);
2871         udelay(200);
2872
2873         /* Enable CPU FDI TX PLL, always on for Ironlake */
2874         reg = FDI_TX_CTL(pipe);
2875         temp = I915_READ(reg);
2876         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2877                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2878
2879                 POSTING_READ(reg);
2880                 udelay(100);
2881         }
2882 }
2883
2884 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2885 {
2886         struct drm_device *dev = intel_crtc->base.dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         int pipe = intel_crtc->pipe;
2889         u32 reg, temp;
2890
2891         /* Switch from PCDclk to Rawclk */
2892         reg = FDI_RX_CTL(pipe);
2893         temp = I915_READ(reg);
2894         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2895
2896         /* Disable CPU FDI TX PLL */
2897         reg = FDI_TX_CTL(pipe);
2898         temp = I915_READ(reg);
2899         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2900
2901         POSTING_READ(reg);
2902         udelay(100);
2903
2904         reg = FDI_RX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2907
2908         /* Wait for the clocks to turn off. */
2909         POSTING_READ(reg);
2910         udelay(100);
2911 }
2912
2913 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2914 {
2915         struct drm_device *dev = crtc->dev;
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918         int pipe = intel_crtc->pipe;
2919         u32 reg, temp;
2920
2921         /* disable CPU FDI tx and PCH FDI rx */
2922         reg = FDI_TX_CTL(pipe);
2923         temp = I915_READ(reg);
2924         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2925         POSTING_READ(reg);
2926
2927         reg = FDI_RX_CTL(pipe);
2928         temp = I915_READ(reg);
2929         temp &= ~(0x7 << 16);
2930         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2931         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2932
2933         POSTING_READ(reg);
2934         udelay(100);
2935
2936         /* Ironlake workaround, disable clock pointer after downing FDI */
2937         if (HAS_PCH_IBX(dev)) {
2938                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2939         }
2940
2941         /* still set train pattern 1 */
2942         reg = FDI_TX_CTL(pipe);
2943         temp = I915_READ(reg);
2944         temp &= ~FDI_LINK_TRAIN_NONE;
2945         temp |= FDI_LINK_TRAIN_PATTERN_1;
2946         I915_WRITE(reg, temp);
2947
2948         reg = FDI_RX_CTL(pipe);
2949         temp = I915_READ(reg);
2950         if (HAS_PCH_CPT(dev)) {
2951                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2952                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2953         } else {
2954                 temp &= ~FDI_LINK_TRAIN_NONE;
2955                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2956         }
2957         /* BPC in FDI rx is consistent with that in PIPECONF */
2958         temp &= ~(0x07 << 16);
2959         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2960         I915_WRITE(reg, temp);
2961
2962         POSTING_READ(reg);
2963         udelay(100);
2964 }
2965
2966 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971         unsigned long flags;
2972         bool pending;
2973
2974         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2975             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2976                 return false;
2977
2978         spin_lock_irqsave(&dev->event_lock, flags);
2979         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2980         spin_unlock_irqrestore(&dev->event_lock, flags);
2981
2982         return pending;
2983 }
2984
2985 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2986 {
2987         struct drm_device *dev = crtc->dev;
2988         struct drm_i915_private *dev_priv = dev->dev_private;
2989
2990         if (crtc->fb == NULL)
2991                 return;
2992
2993         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2994
2995         wait_event(dev_priv->pending_flip_queue,
2996                    !intel_crtc_has_pending_flip(crtc));
2997
2998         mutex_lock(&dev->struct_mutex);
2999         intel_finish_fb(crtc->fb);
3000         mutex_unlock(&dev->struct_mutex);
3001 }
3002
3003 /* Program iCLKIP clock to the desired frequency */
3004 static void lpt_program_iclkip(struct drm_crtc *crtc)
3005 {
3006         struct drm_device *dev = crtc->dev;
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3009         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3010         u32 temp;
3011
3012         mutex_lock(&dev_priv->dpio_lock);
3013
3014         /* It is necessary to ungate the pixclk gate prior to programming
3015          * the divisors, and gate it back when it is done.
3016          */
3017         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3018
3019         /* Disable SSCCTL */
3020         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3021                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3022                                 SBI_SSCCTL_DISABLE,
3023                         SBI_ICLK);
3024
3025         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3026         if (clock == 20000) {
3027                 auxdiv = 1;
3028                 divsel = 0x41;
3029                 phaseinc = 0x20;
3030         } else {
3031                 /* The iCLK virtual clock root frequency is in MHz,
3032                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3033                  * divisors, it is necessary to divide one by another, so we
3034                  * convert the virtual clock precision to KHz here for higher
3035                  * precision.
3036                  */
3037                 u32 iclk_virtual_root_freq = 172800 * 1000;
3038                 u32 iclk_pi_range = 64;
3039                 u32 desired_divisor, msb_divisor_value, pi_value;
3040
3041                 desired_divisor = (iclk_virtual_root_freq / clock);
3042                 msb_divisor_value = desired_divisor / iclk_pi_range;
3043                 pi_value = desired_divisor % iclk_pi_range;
3044
3045                 auxdiv = 0;
3046                 divsel = msb_divisor_value - 2;
3047                 phaseinc = pi_value;
3048         }
3049
3050         /* This should not happen with any sane values */
3051         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3052                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3053         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3054                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3055
3056         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3057                         clock,
3058                         auxdiv,
3059                         divsel,
3060                         phasedir,
3061                         phaseinc);
3062
3063         /* Program SSCDIVINTPHASE6 */
3064         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3065         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3066         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3067         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3068         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3069         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3070         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3071         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3072
3073         /* Program SSCAUXDIV */
3074         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3075         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3076         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3077         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3078
3079         /* Enable modulator and associated divider */
3080         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3081         temp &= ~SBI_SSCCTL_DISABLE;
3082         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3083
3084         /* Wait for initialization time */
3085         udelay(24);
3086
3087         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3088
3089         mutex_unlock(&dev_priv->dpio_lock);
3090 }
3091
3092 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3093                                                 enum pipe pch_transcoder)
3094 {
3095         struct drm_device *dev = crtc->base.dev;
3096         struct drm_i915_private *dev_priv = dev->dev_private;
3097         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3098
3099         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3100                    I915_READ(HTOTAL(cpu_transcoder)));
3101         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3102                    I915_READ(HBLANK(cpu_transcoder)));
3103         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3104                    I915_READ(HSYNC(cpu_transcoder)));
3105
3106         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3107                    I915_READ(VTOTAL(cpu_transcoder)));
3108         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3109                    I915_READ(VBLANK(cpu_transcoder)));
3110         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3111                    I915_READ(VSYNC(cpu_transcoder)));
3112         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3113                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3114 }
3115
3116 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3117 {
3118         struct drm_i915_private *dev_priv = dev->dev_private;
3119         uint32_t temp;
3120
3121         temp = I915_READ(SOUTH_CHICKEN1);
3122         if (temp & FDI_BC_BIFURCATION_SELECT)
3123                 return;
3124
3125         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3126         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3127
3128         temp |= FDI_BC_BIFURCATION_SELECT;
3129         DRM_DEBUG_KMS("enabling fdi C rx\n");
3130         I915_WRITE(SOUTH_CHICKEN1, temp);
3131         POSTING_READ(SOUTH_CHICKEN1);
3132 }
3133
3134 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3135 {
3136         struct drm_device *dev = intel_crtc->base.dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138
3139         switch (intel_crtc->pipe) {
3140         case PIPE_A:
3141                 break;
3142         case PIPE_B:
3143                 if (intel_crtc->config.fdi_lanes > 2)
3144                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3145                 else
3146                         cpt_enable_fdi_bc_bifurcation(dev);
3147
3148                 break;
3149         case PIPE_C:
3150                 cpt_enable_fdi_bc_bifurcation(dev);
3151
3152                 break;
3153         default:
3154                 BUG();
3155         }
3156 }
3157
3158 /*
3159  * Enable PCH resources required for PCH ports:
3160  *   - PCH PLLs
3161  *   - FDI training & RX/TX
3162  *   - update transcoder timings
3163  *   - DP transcoding bits
3164  *   - transcoder
3165  */
3166 static void ironlake_pch_enable(struct drm_crtc *crtc)
3167 {
3168         struct drm_device *dev = crtc->dev;
3169         struct drm_i915_private *dev_priv = dev->dev_private;
3170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3171         int pipe = intel_crtc->pipe;
3172         u32 reg, temp;
3173
3174         assert_pch_transcoder_disabled(dev_priv, pipe);
3175
3176         if (IS_IVYBRIDGE(dev))
3177                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3178
3179         /* Write the TU size bits before fdi link training, so that error
3180          * detection works. */
3181         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3182                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3183
3184         /* For PCH output, training FDI link */
3185         dev_priv->display.fdi_link_train(crtc);
3186
3187         /* We need to program the right clock selection before writing the pixel
3188          * mutliplier into the DPLL. */
3189         if (HAS_PCH_CPT(dev)) {
3190                 u32 sel;
3191
3192                 temp = I915_READ(PCH_DPLL_SEL);
3193                 temp |= TRANS_DPLL_ENABLE(pipe);
3194                 sel = TRANS_DPLLB_SEL(pipe);
3195                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3196                         temp |= sel;
3197                 else
3198                         temp &= ~sel;
3199                 I915_WRITE(PCH_DPLL_SEL, temp);
3200         }
3201
3202         /* XXX: pch pll's can be enabled any time before we enable the PCH
3203          * transcoder, and we actually should do this to not upset any PCH
3204          * transcoder that already use the clock when we share it.
3205          *
3206          * Note that enable_shared_dpll tries to do the right thing, but
3207          * get_shared_dpll unconditionally resets the pll - we need that to have
3208          * the right LVDS enable sequence. */
3209         ironlake_enable_shared_dpll(intel_crtc);
3210
3211         /* set transcoder timing, panel must allow it */
3212         assert_panel_unlocked(dev_priv, pipe);
3213         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3214
3215         intel_fdi_normal_train(crtc);
3216
3217         /* For PCH DP, enable TRANS_DP_CTL */
3218         if (HAS_PCH_CPT(dev) &&
3219             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3220              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3221                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3222                 reg = TRANS_DP_CTL(pipe);
3223                 temp = I915_READ(reg);
3224                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3225                           TRANS_DP_SYNC_MASK |
3226                           TRANS_DP_BPC_MASK);
3227                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3228                          TRANS_DP_ENH_FRAMING);
3229                 temp |= bpc << 9; /* same format but at 11:9 */
3230
3231                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3232                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3233                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3234                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3235
3236                 switch (intel_trans_dp_port_sel(crtc)) {
3237                 case PCH_DP_B:
3238                         temp |= TRANS_DP_PORT_SEL_B;
3239                         break;
3240                 case PCH_DP_C:
3241                         temp |= TRANS_DP_PORT_SEL_C;
3242                         break;
3243                 case PCH_DP_D:
3244                         temp |= TRANS_DP_PORT_SEL_D;
3245                         break;
3246                 default:
3247                         BUG();
3248                 }
3249
3250                 I915_WRITE(reg, temp);
3251         }
3252
3253         ironlake_enable_pch_transcoder(dev_priv, pipe);
3254 }
3255
3256 static void lpt_pch_enable(struct drm_crtc *crtc)
3257 {
3258         struct drm_device *dev = crtc->dev;
3259         struct drm_i915_private *dev_priv = dev->dev_private;
3260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3261         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3262
3263         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3264
3265         lpt_program_iclkip(crtc);
3266
3267         /* Set transcoder timing. */
3268         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3269
3270         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3271 }
3272
3273 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3274 {
3275         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3276
3277         if (pll == NULL)
3278                 return;
3279
3280         if (pll->refcount == 0) {
3281                 WARN(1, "bad %s refcount\n", pll->name);
3282                 return;
3283         }
3284
3285         if (--pll->refcount == 0) {
3286                 WARN_ON(pll->on);
3287                 WARN_ON(pll->active);
3288         }
3289
3290         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3291 }
3292
3293 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3294 {
3295         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3296         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3297         enum intel_dpll_id i;
3298
3299         if (pll) {
3300                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3301                               crtc->base.base.id, pll->name);
3302                 intel_put_shared_dpll(crtc);
3303         }
3304
3305         if (HAS_PCH_IBX(dev_priv->dev)) {
3306                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3307                 i = (enum intel_dpll_id) crtc->pipe;
3308                 pll = &dev_priv->shared_dplls[i];
3309
3310                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3311                               crtc->base.base.id, pll->name);
3312
3313                 goto found;
3314         }
3315
3316         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3317                 pll = &dev_priv->shared_dplls[i];
3318
3319                 /* Only want to check enabled timings first */
3320                 if (pll->refcount == 0)
3321                         continue;
3322
3323                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3324                            sizeof(pll->hw_state)) == 0) {
3325                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3326                                       crtc->base.base.id,
3327                                       pll->name, pll->refcount, pll->active);
3328
3329                         goto found;
3330                 }
3331         }
3332
3333         /* Ok no matching timings, maybe there's a free one? */
3334         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3335                 pll = &dev_priv->shared_dplls[i];
3336                 if (pll->refcount == 0) {
3337                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3338                                       crtc->base.base.id, pll->name);
3339                         goto found;
3340                 }
3341         }
3342
3343         return NULL;
3344
3345 found:
3346         crtc->config.shared_dpll = i;
3347         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3348                          pipe_name(crtc->pipe));
3349
3350         if (pll->active == 0) {
3351                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3352                        sizeof(pll->hw_state));
3353
3354                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3355                 WARN_ON(pll->on);
3356                 assert_shared_dpll_disabled(dev_priv, pll);
3357
3358                 pll->mode_set(dev_priv, pll);
3359         }
3360         pll->refcount++;
3361
3362         return pll;
3363 }
3364
3365 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3366 {
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         int dslreg = PIPEDSL(pipe);
3369         u32 temp;
3370
3371         temp = I915_READ(dslreg);
3372         udelay(500);
3373         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3374                 if (wait_for(I915_READ(dslreg) != temp, 5))
3375                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3376         }
3377 }
3378
3379 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3380 {
3381         struct drm_device *dev = crtc->base.dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         int pipe = crtc->pipe;
3384
3385         if (crtc->config.pch_pfit.enabled) {
3386                 /* Force use of hard-coded filter coefficients
3387                  * as some pre-programmed values are broken,
3388                  * e.g. x201.
3389                  */
3390                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3391                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3392                                                  PF_PIPE_SEL_IVB(pipe));
3393                 else
3394                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3395                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3396                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3397         }
3398 }
3399
3400 static void intel_enable_planes(struct drm_crtc *crtc)
3401 {
3402         struct drm_device *dev = crtc->dev;
3403         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3404         struct intel_plane *intel_plane;
3405
3406         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3407                 if (intel_plane->pipe == pipe)
3408                         intel_plane_restore(&intel_plane->base);
3409 }
3410
3411 static void intel_disable_planes(struct drm_crtc *crtc)
3412 {
3413         struct drm_device *dev = crtc->dev;
3414         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3415         struct intel_plane *intel_plane;
3416
3417         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3418                 if (intel_plane->pipe == pipe)
3419                         intel_plane_disable(&intel_plane->base);
3420 }
3421
3422 void hsw_enable_ips(struct intel_crtc *crtc)
3423 {
3424         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3425
3426         if (!crtc->config.ips_enabled)
3427                 return;
3428
3429         /* We can only enable IPS after we enable a plane and wait for a vblank.
3430          * We guarantee that the plane is enabled by calling intel_enable_ips
3431          * only after intel_enable_plane. And intel_enable_plane already waits
3432          * for a vblank, so all we need to do here is to enable the IPS bit. */
3433         assert_plane_enabled(dev_priv, crtc->plane);
3434         if (IS_BROADWELL(crtc->base.dev)) {
3435                 mutex_lock(&dev_priv->rps.hw_lock);
3436                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3437                 mutex_unlock(&dev_priv->rps.hw_lock);
3438                 /* Quoting Art Runyan: "its not safe to expect any particular
3439                  * value in IPS_CTL bit 31 after enabling IPS through the
3440                  * mailbox." Moreover, the mailbox may return a bogus state,
3441                  * so we need to just enable it and continue on.
3442                  */
3443         } else {
3444                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3445                 /* The bit only becomes 1 in the next vblank, so this wait here
3446                  * is essentially intel_wait_for_vblank. If we don't have this
3447                  * and don't wait for vblanks until the end of crtc_enable, then
3448                  * the HW state readout code will complain that the expected
3449                  * IPS_CTL value is not the one we read. */
3450                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3451                         DRM_ERROR("Timed out waiting for IPS enable\n");
3452         }
3453 }
3454
3455 void hsw_disable_ips(struct intel_crtc *crtc)
3456 {
3457         struct drm_device *dev = crtc->base.dev;
3458         struct drm_i915_private *dev_priv = dev->dev_private;
3459
3460         if (!crtc->config.ips_enabled)
3461                 return;
3462
3463         assert_plane_enabled(dev_priv, crtc->plane);
3464         if (IS_BROADWELL(crtc->base.dev)) {
3465                 mutex_lock(&dev_priv->rps.hw_lock);
3466                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3467                 mutex_unlock(&dev_priv->rps.hw_lock);
3468         } else {
3469                 I915_WRITE(IPS_CTL, 0);
3470                 POSTING_READ(IPS_CTL);
3471         }
3472
3473         /* We need to wait for a vblank before we can disable the plane. */
3474         intel_wait_for_vblank(dev, crtc->pipe);
3475 }
3476
3477 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3478 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3479 {
3480         struct drm_device *dev = crtc->dev;
3481         struct drm_i915_private *dev_priv = dev->dev_private;
3482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483         enum pipe pipe = intel_crtc->pipe;
3484         int palreg = PALETTE(pipe);
3485         int i;
3486         bool reenable_ips = false;
3487
3488         /* The clocks have to be on to load the palette. */
3489         if (!crtc->enabled || !intel_crtc->active)
3490                 return;
3491
3492         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3493                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3494                         assert_dsi_pll_enabled(dev_priv);
3495                 else
3496                         assert_pll_enabled(dev_priv, pipe);
3497         }
3498
3499         /* use legacy palette for Ironlake */
3500         if (HAS_PCH_SPLIT(dev))
3501                 palreg = LGC_PALETTE(pipe);
3502
3503         /* Workaround : Do not read or write the pipe palette/gamma data while
3504          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3505          */
3506         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3507             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3508              GAMMA_MODE_MODE_SPLIT)) {
3509                 hsw_disable_ips(intel_crtc);
3510                 reenable_ips = true;
3511         }
3512
3513         for (i = 0; i < 256; i++) {
3514                 I915_WRITE(palreg + 4 * i,
3515                            (intel_crtc->lut_r[i] << 16) |
3516                            (intel_crtc->lut_g[i] << 8) |
3517                            intel_crtc->lut_b[i]);
3518         }
3519
3520         if (reenable_ips)
3521                 hsw_enable_ips(intel_crtc);
3522 }
3523
3524 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3525 {
3526         struct drm_device *dev = crtc->dev;
3527         struct drm_i915_private *dev_priv = dev->dev_private;
3528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3529         struct intel_encoder *encoder;
3530         int pipe = intel_crtc->pipe;
3531         int plane = intel_crtc->plane;
3532
3533         WARN_ON(!crtc->enabled);
3534
3535         if (intel_crtc->active)
3536                 return;
3537
3538         intel_crtc->active = true;
3539
3540         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3541         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->pre_enable)
3545                         encoder->pre_enable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 /* Note: FDI PLL enabling _must_ be done before we enable the
3549                  * cpu pipes, hence this is separate from all the other fdi/pch
3550                  * enabling. */
3551                 ironlake_fdi_pll_enable(intel_crtc);
3552         } else {
3553                 assert_fdi_tx_disabled(dev_priv, pipe);
3554                 assert_fdi_rx_disabled(dev_priv, pipe);
3555         }
3556
3557         ironlake_pfit_enable(intel_crtc);
3558
3559         /*
3560          * On ILK+ LUT must be loaded before the pipe is running but with
3561          * clocks enabled
3562          */
3563         intel_crtc_load_lut(crtc);
3564
3565         intel_update_watermarks(crtc);
3566         intel_enable_pipe(dev_priv, pipe,
3567                           intel_crtc->config.has_pch_encoder, false);
3568         intel_enable_primary_plane(dev_priv, plane, pipe);
3569         intel_enable_planes(crtc);
3570         intel_crtc_update_cursor(crtc, true);
3571
3572         if (intel_crtc->config.has_pch_encoder)
3573                 ironlake_pch_enable(crtc);
3574
3575         mutex_lock(&dev->struct_mutex);
3576         intel_update_fbc(dev);
3577         mutex_unlock(&dev->struct_mutex);
3578
3579         for_each_encoder_on_crtc(dev, crtc, encoder)
3580                 encoder->enable(encoder);
3581
3582         if (HAS_PCH_CPT(dev))
3583                 cpt_verify_modeset(dev, intel_crtc->pipe);
3584
3585         /*
3586          * There seems to be a race in PCH platform hw (at least on some
3587          * outputs) where an enabled pipe still completes any pageflip right
3588          * away (as if the pipe is off) instead of waiting for vblank. As soon
3589          * as the first vblank happend, everything works as expected. Hence just
3590          * wait for one vblank before returning to avoid strange things
3591          * happening.
3592          */
3593         intel_wait_for_vblank(dev, intel_crtc->pipe);
3594 }
3595
3596 /* IPS only exists on ULT machines and is tied to pipe A. */
3597 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3598 {
3599         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3600 }
3601
3602 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3603 {
3604         struct drm_device *dev = crtc->dev;
3605         struct drm_i915_private *dev_priv = dev->dev_private;
3606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607         int pipe = intel_crtc->pipe;
3608         int plane = intel_crtc->plane;
3609
3610         intel_enable_primary_plane(dev_priv, plane, pipe);
3611         intel_enable_planes(crtc);
3612         intel_crtc_update_cursor(crtc, true);
3613
3614         hsw_enable_ips(intel_crtc);
3615
3616         mutex_lock(&dev->struct_mutex);
3617         intel_update_fbc(dev);
3618         mutex_unlock(&dev->struct_mutex);
3619 }
3620
3621 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626         int pipe = intel_crtc->pipe;
3627         int plane = intel_crtc->plane;
3628
3629         intel_crtc_wait_for_pending_flips(crtc);
3630         drm_vblank_off(dev, pipe);
3631
3632         /* FBC must be disabled before disabling the plane on HSW. */
3633         if (dev_priv->fbc.plane == plane)
3634                 intel_disable_fbc(dev);
3635
3636         hsw_disable_ips(intel_crtc);
3637
3638         intel_crtc_update_cursor(crtc, false);
3639         intel_disable_planes(crtc);
3640         intel_disable_primary_plane(dev_priv, plane, pipe);
3641 }
3642
3643 /*
3644  * This implements the workaround described in the "notes" section of the mode
3645  * set sequence documentation. When going from no pipes or single pipe to
3646  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3647  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3648  */
3649 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3650 {
3651         struct drm_device *dev = crtc->base.dev;
3652         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3653
3654         /* We want to get the other_active_crtc only if there's only 1 other
3655          * active crtc. */
3656         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3657                 if (!crtc_it->active || crtc_it == crtc)
3658                         continue;
3659
3660                 if (other_active_crtc)
3661                         return;
3662
3663                 other_active_crtc = crtc_it;
3664         }
3665         if (!other_active_crtc)
3666                 return;
3667
3668         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3669         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3670 }
3671
3672 static void haswell_crtc_enable(struct drm_crtc *crtc)
3673 {
3674         struct drm_device *dev = crtc->dev;
3675         struct drm_i915_private *dev_priv = dev->dev_private;
3676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677         struct intel_encoder *encoder;
3678         int pipe = intel_crtc->pipe;
3679
3680         WARN_ON(!crtc->enabled);
3681
3682         if (intel_crtc->active)
3683                 return;
3684
3685         intel_crtc->active = true;
3686
3687         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3688         if (intel_crtc->config.has_pch_encoder)
3689                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3690
3691         if (intel_crtc->config.has_pch_encoder)
3692                 dev_priv->display.fdi_link_train(crtc);
3693
3694         for_each_encoder_on_crtc(dev, crtc, encoder)
3695                 if (encoder->pre_enable)
3696                         encoder->pre_enable(encoder);
3697
3698         intel_ddi_enable_pipe_clock(intel_crtc);
3699
3700         ironlake_pfit_enable(intel_crtc);
3701
3702         /*
3703          * On ILK+ LUT must be loaded before the pipe is running but with
3704          * clocks enabled
3705          */
3706         intel_crtc_load_lut(crtc);
3707
3708         intel_ddi_set_pipe_settings(crtc);
3709         intel_ddi_enable_transcoder_func(crtc);
3710
3711         intel_update_watermarks(crtc);
3712         intel_enable_pipe(dev_priv, pipe,
3713                           intel_crtc->config.has_pch_encoder, false);
3714
3715         if (intel_crtc->config.has_pch_encoder)
3716                 lpt_pch_enable(crtc);
3717
3718         for_each_encoder_on_crtc(dev, crtc, encoder) {
3719                 encoder->enable(encoder);
3720                 intel_opregion_notify_encoder(encoder, true);
3721         }
3722
3723         /* If we change the relative order between pipe/planes enabling, we need
3724          * to change the workaround. */
3725         haswell_mode_set_planes_workaround(intel_crtc);
3726         haswell_crtc_enable_planes(crtc);
3727
3728         /*
3729          * There seems to be a race in PCH platform hw (at least on some
3730          * outputs) where an enabled pipe still completes any pageflip right
3731          * away (as if the pipe is off) instead of waiting for vblank. As soon
3732          * as the first vblank happend, everything works as expected. Hence just
3733          * wait for one vblank before returning to avoid strange things
3734          * happening.
3735          */
3736         intel_wait_for_vblank(dev, intel_crtc->pipe);
3737 }
3738
3739 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3740 {
3741         struct drm_device *dev = crtc->base.dev;
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743         int pipe = crtc->pipe;
3744
3745         /* To avoid upsetting the power well on haswell only disable the pfit if
3746          * it's in use. The hw state code will make sure we get this right. */
3747         if (crtc->config.pch_pfit.enabled) {
3748                 I915_WRITE(PF_CTL(pipe), 0);
3749                 I915_WRITE(PF_WIN_POS(pipe), 0);
3750                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3751         }
3752 }
3753
3754 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3755 {
3756         struct drm_device *dev = crtc->dev;
3757         struct drm_i915_private *dev_priv = dev->dev_private;
3758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759         struct intel_encoder *encoder;
3760         int pipe = intel_crtc->pipe;
3761         int plane = intel_crtc->plane;
3762         u32 reg, temp;
3763
3764
3765         if (!intel_crtc->active)
3766                 return;
3767
3768         for_each_encoder_on_crtc(dev, crtc, encoder)
3769                 encoder->disable(encoder);
3770
3771         intel_crtc_wait_for_pending_flips(crtc);
3772         drm_vblank_off(dev, pipe);
3773
3774         if (dev_priv->fbc.plane == plane)
3775                 intel_disable_fbc(dev);
3776
3777         intel_crtc_update_cursor(crtc, false);
3778         intel_disable_planes(crtc);
3779         intel_disable_primary_plane(dev_priv, plane, pipe);
3780
3781         if (intel_crtc->config.has_pch_encoder)
3782                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3783
3784         intel_disable_pipe(dev_priv, pipe);
3785
3786         ironlake_pfit_disable(intel_crtc);
3787
3788         for_each_encoder_on_crtc(dev, crtc, encoder)
3789                 if (encoder->post_disable)
3790                         encoder->post_disable(encoder);
3791
3792         if (intel_crtc->config.has_pch_encoder) {
3793                 ironlake_fdi_disable(crtc);
3794
3795                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3796                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3797
3798                 if (HAS_PCH_CPT(dev)) {
3799                         /* disable TRANS_DP_CTL */
3800                         reg = TRANS_DP_CTL(pipe);
3801                         temp = I915_READ(reg);
3802                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3803                                   TRANS_DP_PORT_SEL_MASK);
3804                         temp |= TRANS_DP_PORT_SEL_NONE;
3805                         I915_WRITE(reg, temp);
3806
3807                         /* disable DPLL_SEL */
3808                         temp = I915_READ(PCH_DPLL_SEL);
3809                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3810                         I915_WRITE(PCH_DPLL_SEL, temp);
3811                 }
3812
3813                 /* disable PCH DPLL */
3814                 intel_disable_shared_dpll(intel_crtc);
3815
3816                 ironlake_fdi_pll_disable(intel_crtc);
3817         }
3818
3819         intel_crtc->active = false;
3820         intel_update_watermarks(crtc);
3821
3822         mutex_lock(&dev->struct_mutex);
3823         intel_update_fbc(dev);
3824         mutex_unlock(&dev->struct_mutex);
3825 }
3826
3827 static void haswell_crtc_disable(struct drm_crtc *crtc)
3828 {
3829         struct drm_device *dev = crtc->dev;
3830         struct drm_i915_private *dev_priv = dev->dev_private;
3831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3832         struct intel_encoder *encoder;
3833         int pipe = intel_crtc->pipe;
3834         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3835
3836         if (!intel_crtc->active)
3837                 return;
3838
3839         haswell_crtc_disable_planes(crtc);
3840
3841         for_each_encoder_on_crtc(dev, crtc, encoder) {
3842                 intel_opregion_notify_encoder(encoder, false);
3843                 encoder->disable(encoder);
3844         }
3845
3846         if (intel_crtc->config.has_pch_encoder)
3847                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3848         intel_disable_pipe(dev_priv, pipe);
3849
3850         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3851
3852         ironlake_pfit_disable(intel_crtc);
3853
3854         intel_ddi_disable_pipe_clock(intel_crtc);
3855
3856         for_each_encoder_on_crtc(dev, crtc, encoder)
3857                 if (encoder->post_disable)
3858                         encoder->post_disable(encoder);
3859
3860         if (intel_crtc->config.has_pch_encoder) {
3861                 lpt_disable_pch_transcoder(dev_priv);
3862                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3863                 intel_ddi_fdi_disable(crtc);
3864         }
3865
3866         intel_crtc->active = false;
3867         intel_update_watermarks(crtc);
3868
3869         mutex_lock(&dev->struct_mutex);
3870         intel_update_fbc(dev);
3871         mutex_unlock(&dev->struct_mutex);
3872 }
3873
3874 static void ironlake_crtc_off(struct drm_crtc *crtc)
3875 {
3876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3877         intel_put_shared_dpll(intel_crtc);
3878 }
3879
3880 static void haswell_crtc_off(struct drm_crtc *crtc)
3881 {
3882         intel_ddi_put_crtc_pll(crtc);
3883 }
3884
3885 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3886 {
3887         if (!enable && intel_crtc->overlay) {
3888                 struct drm_device *dev = intel_crtc->base.dev;
3889                 struct drm_i915_private *dev_priv = dev->dev_private;
3890
3891                 mutex_lock(&dev->struct_mutex);
3892                 dev_priv->mm.interruptible = false;
3893                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3894                 dev_priv->mm.interruptible = true;
3895                 mutex_unlock(&dev->struct_mutex);
3896         }
3897
3898         /* Let userspace switch the overlay on again. In most cases userspace
3899          * has to recompute where to put it anyway.
3900          */
3901 }
3902
3903 /**
3904  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3905  * cursor plane briefly if not already running after enabling the display
3906  * plane.
3907  * This workaround avoids occasional blank screens when self refresh is
3908  * enabled.
3909  */
3910 static void
3911 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3912 {
3913         u32 cntl = I915_READ(CURCNTR(pipe));
3914
3915         if ((cntl & CURSOR_MODE) == 0) {
3916                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3917
3918                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3919                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3920                 intel_wait_for_vblank(dev_priv->dev, pipe);
3921                 I915_WRITE(CURCNTR(pipe), cntl);
3922                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3923                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3924         }
3925 }
3926
3927 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3928 {
3929         struct drm_device *dev = crtc->base.dev;
3930         struct drm_i915_private *dev_priv = dev->dev_private;
3931         struct intel_crtc_config *pipe_config = &crtc->config;
3932
3933         if (!crtc->config.gmch_pfit.control)
3934                 return;
3935
3936         /*
3937          * The panel fitter should only be adjusted whilst the pipe is disabled,
3938          * according to register description and PRM.
3939          */
3940         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3941         assert_pipe_disabled(dev_priv, crtc->pipe);
3942
3943         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3944         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3945
3946         /* Border color in case we don't scale up to the full screen. Black by
3947          * default, change to something else for debugging. */
3948         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3949 }
3950
3951 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3952 {
3953         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3954
3955         /* Obtain SKU information */
3956         mutex_lock(&dev_priv->dpio_lock);
3957         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3958                 CCK_FUSE_HPLL_FREQ_MASK;
3959         mutex_unlock(&dev_priv->dpio_lock);
3960
3961         return vco_freq[hpll_freq];
3962 }
3963
3964 /* Adjust CDclk dividers to allow high res or save power if possible */
3965 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3966 {
3967         struct drm_i915_private *dev_priv = dev->dev_private;
3968         u32 val, cmd;
3969
3970         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3971                 cmd = 2;
3972         else if (cdclk == 266)
3973                 cmd = 1;
3974         else
3975                 cmd = 0;
3976
3977         mutex_lock(&dev_priv->rps.hw_lock);
3978         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3979         val &= ~DSPFREQGUAR_MASK;
3980         val |= (cmd << DSPFREQGUAR_SHIFT);
3981         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3982         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3983                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3984                      50)) {
3985                 DRM_ERROR("timed out waiting for CDclk change\n");
3986         }
3987         mutex_unlock(&dev_priv->rps.hw_lock);
3988
3989         if (cdclk == 400) {
3990                 u32 divider, vco;
3991
3992                 vco = valleyview_get_vco(dev_priv);
3993                 divider = ((vco << 1) / cdclk) - 1;
3994
3995                 mutex_lock(&dev_priv->dpio_lock);
3996                 /* adjust cdclk divider */
3997                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3998                 val &= ~0xf;
3999                 val |= divider;
4000                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4001                 mutex_unlock(&dev_priv->dpio_lock);
4002         }
4003
4004         mutex_lock(&dev_priv->dpio_lock);
4005         /* adjust self-refresh exit latency value */
4006         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4007         val &= ~0x7f;
4008
4009         /*
4010          * For high bandwidth configs, we set a higher latency in the bunit
4011          * so that the core display fetch happens in time to avoid underruns.
4012          */
4013         if (cdclk == 400)
4014                 val |= 4500 / 250; /* 4.5 usec */
4015         else
4016                 val |= 3000 / 250; /* 3.0 usec */
4017         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4018         mutex_unlock(&dev_priv->dpio_lock);
4019
4020         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4021         intel_i2c_reset(dev);
4022 }
4023
4024 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4025 {
4026         int cur_cdclk, vco;
4027         int divider;
4028
4029         vco = valleyview_get_vco(dev_priv);
4030
4031         mutex_lock(&dev_priv->dpio_lock);
4032         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4033         mutex_unlock(&dev_priv->dpio_lock);
4034
4035         divider &= 0xf;
4036
4037         cur_cdclk = (vco << 1) / (divider + 1);
4038
4039         return cur_cdclk;
4040 }
4041
4042 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4043                                  int max_pixclk)
4044 {
4045         int cur_cdclk;
4046
4047         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4048
4049         /*
4050          * Really only a few cases to deal with, as only 4 CDclks are supported:
4051          *   200MHz
4052          *   267MHz
4053          *   320MHz
4054          *   400MHz
4055          * So we check to see whether we're above 90% of the lower bin and
4056          * adjust if needed.
4057          */
4058         if (max_pixclk > 288000) {
4059                 return 400;
4060         } else if (max_pixclk > 240000) {
4061                 return 320;
4062         } else
4063                 return 266;
4064         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4065 }
4066
4067 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4068                                  unsigned modeset_pipes,
4069                                  struct intel_crtc_config *pipe_config)
4070 {
4071         struct drm_device *dev = dev_priv->dev;
4072         struct intel_crtc *intel_crtc;
4073         int max_pixclk = 0;
4074
4075         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4076                             base.head) {
4077                 if (modeset_pipes & (1 << intel_crtc->pipe))
4078                         max_pixclk = max(max_pixclk,
4079                                          pipe_config->adjusted_mode.crtc_clock);
4080                 else if (intel_crtc->base.enabled)
4081                         max_pixclk = max(max_pixclk,
4082                                          intel_crtc->config.adjusted_mode.crtc_clock);
4083         }
4084
4085         return max_pixclk;
4086 }
4087
4088 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4089                                             unsigned *prepare_pipes,
4090                                             unsigned modeset_pipes,
4091                                             struct intel_crtc_config *pipe_config)
4092 {
4093         struct drm_i915_private *dev_priv = dev->dev_private;
4094         struct intel_crtc *intel_crtc;
4095         int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4096                                                pipe_config);
4097         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4098
4099         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4100                 return;
4101
4102         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4103                             base.head)
4104                 if (intel_crtc->base.enabled)
4105                         *prepare_pipes |= (1 << intel_crtc->pipe);
4106 }
4107
4108 static void valleyview_modeset_global_resources(struct drm_device *dev)
4109 {
4110         struct drm_i915_private *dev_priv = dev->dev_private;
4111         int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4112         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4113         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4114
4115         if (req_cdclk != cur_cdclk)
4116                 valleyview_set_cdclk(dev, req_cdclk);
4117 }
4118
4119 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4120 {
4121         struct drm_device *dev = crtc->dev;
4122         struct drm_i915_private *dev_priv = dev->dev_private;
4123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4124         struct intel_encoder *encoder;
4125         int pipe = intel_crtc->pipe;
4126         int plane = intel_crtc->plane;
4127         bool is_dsi;
4128
4129         WARN_ON(!crtc->enabled);
4130
4131         if (intel_crtc->active)
4132                 return;
4133
4134         intel_crtc->active = true;
4135
4136         for_each_encoder_on_crtc(dev, crtc, encoder)
4137                 if (encoder->pre_pll_enable)
4138                         encoder->pre_pll_enable(encoder);
4139
4140         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4141
4142         if (!is_dsi)
4143                 vlv_enable_pll(intel_crtc);
4144
4145         for_each_encoder_on_crtc(dev, crtc, encoder)
4146                 if (encoder->pre_enable)
4147                         encoder->pre_enable(encoder);
4148
4149         i9xx_pfit_enable(intel_crtc);
4150
4151         intel_crtc_load_lut(crtc);
4152
4153         intel_update_watermarks(crtc);
4154         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4155         intel_enable_primary_plane(dev_priv, plane, pipe);
4156         intel_enable_planes(crtc);
4157         intel_crtc_update_cursor(crtc, true);
4158
4159         intel_update_fbc(dev);
4160
4161         for_each_encoder_on_crtc(dev, crtc, encoder)
4162                 encoder->enable(encoder);
4163 }
4164
4165 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4166 {
4167         struct drm_device *dev = crtc->dev;
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4170         struct intel_encoder *encoder;
4171         int pipe = intel_crtc->pipe;
4172         int plane = intel_crtc->plane;
4173
4174         WARN_ON(!crtc->enabled);
4175
4176         if (intel_crtc->active)
4177                 return;
4178
4179         intel_crtc->active = true;
4180
4181         for_each_encoder_on_crtc(dev, crtc, encoder)
4182                 if (encoder->pre_enable)
4183                         encoder->pre_enable(encoder);
4184
4185         i9xx_enable_pll(intel_crtc);
4186
4187         i9xx_pfit_enable(intel_crtc);
4188
4189         intel_crtc_load_lut(crtc);
4190
4191         intel_update_watermarks(crtc);
4192         intel_enable_pipe(dev_priv, pipe, false, false);
4193         intel_enable_primary_plane(dev_priv, plane, pipe);
4194         intel_enable_planes(crtc);
4195         /* The fixup needs to happen before cursor is enabled */
4196         if (IS_G4X(dev))
4197                 g4x_fixup_plane(dev_priv, pipe);
4198         intel_crtc_update_cursor(crtc, true);
4199
4200         /* Give the overlay scaler a chance to enable if it's on this pipe */
4201         intel_crtc_dpms_overlay(intel_crtc, true);
4202
4203         intel_update_fbc(dev);
4204
4205         for_each_encoder_on_crtc(dev, crtc, encoder)
4206                 encoder->enable(encoder);
4207 }
4208
4209 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4210 {
4211         struct drm_device *dev = crtc->base.dev;
4212         struct drm_i915_private *dev_priv = dev->dev_private;
4213
4214         if (!crtc->config.gmch_pfit.control)
4215                 return;
4216
4217         assert_pipe_disabled(dev_priv, crtc->pipe);
4218
4219         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4220                          I915_READ(PFIT_CONTROL));
4221         I915_WRITE(PFIT_CONTROL, 0);
4222 }
4223
4224 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4225 {
4226         struct drm_device *dev = crtc->dev;
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229         struct intel_encoder *encoder;
4230         int pipe = intel_crtc->pipe;
4231         int plane = intel_crtc->plane;
4232
4233         if (!intel_crtc->active)
4234                 return;
4235
4236         for_each_encoder_on_crtc(dev, crtc, encoder)
4237                 encoder->disable(encoder);
4238
4239         /* Give the overlay scaler a chance to disable if it's on this pipe */
4240         intel_crtc_wait_for_pending_flips(crtc);
4241         drm_vblank_off(dev, pipe);
4242
4243         if (dev_priv->fbc.plane == plane)
4244                 intel_disable_fbc(dev);
4245
4246         intel_crtc_dpms_overlay(intel_crtc, false);
4247         intel_crtc_update_cursor(crtc, false);
4248         intel_disable_planes(crtc);
4249         intel_disable_primary_plane(dev_priv, plane, pipe);
4250
4251         intel_disable_pipe(dev_priv, pipe);
4252
4253         i9xx_pfit_disable(intel_crtc);
4254
4255         for_each_encoder_on_crtc(dev, crtc, encoder)
4256                 if (encoder->post_disable)
4257                         encoder->post_disable(encoder);
4258
4259         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4260                 vlv_disable_pll(dev_priv, pipe);
4261         else if (!IS_VALLEYVIEW(dev))
4262                 i9xx_disable_pll(dev_priv, pipe);
4263
4264         intel_crtc->active = false;
4265         intel_update_watermarks(crtc);
4266
4267         intel_update_fbc(dev);
4268 }
4269
4270 static void i9xx_crtc_off(struct drm_crtc *crtc)
4271 {
4272 }
4273
4274 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4275                                     bool enabled)
4276 {
4277         struct drm_device *dev = crtc->dev;
4278         struct drm_i915_master_private *master_priv;
4279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4280         int pipe = intel_crtc->pipe;
4281
4282         if (!dev->primary->master)
4283                 return;
4284
4285         master_priv = dev->primary->master->driver_priv;
4286         if (!master_priv->sarea_priv)
4287                 return;
4288
4289         switch (pipe) {
4290         case 0:
4291                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4292                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4293                 break;
4294         case 1:
4295                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4296                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4297                 break;
4298         default:
4299                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4300                 break;
4301         }
4302 }
4303
4304 /**
4305  * Sets the power management mode of the pipe and plane.
4306  */
4307 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4308 {
4309         struct drm_device *dev = crtc->dev;
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         struct intel_encoder *intel_encoder;
4312         bool enable = false;
4313
4314         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4315                 enable |= intel_encoder->connectors_active;
4316
4317         if (enable)
4318                 dev_priv->display.crtc_enable(crtc);
4319         else
4320                 dev_priv->display.crtc_disable(crtc);
4321
4322         intel_crtc_update_sarea(crtc, enable);
4323 }
4324
4325 static void intel_crtc_disable(struct drm_crtc *crtc)
4326 {
4327         struct drm_device *dev = crtc->dev;
4328         struct drm_connector *connector;
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4331
4332         /* crtc should still be enabled when we disable it. */
4333         WARN_ON(!crtc->enabled);
4334
4335         dev_priv->display.crtc_disable(crtc);
4336         intel_crtc->eld_vld = false;
4337         intel_crtc_update_sarea(crtc, false);
4338         dev_priv->display.off(crtc);
4339
4340         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4341         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4342         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4343
4344         if (crtc->fb) {
4345                 mutex_lock(&dev->struct_mutex);
4346                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4347                 mutex_unlock(&dev->struct_mutex);
4348                 crtc->fb = NULL;
4349         }
4350
4351         /* Update computed state. */
4352         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4353                 if (!connector->encoder || !connector->encoder->crtc)
4354                         continue;
4355
4356                 if (connector->encoder->crtc != crtc)
4357                         continue;
4358
4359                 connector->dpms = DRM_MODE_DPMS_OFF;
4360                 to_intel_encoder(connector->encoder)->connectors_active = false;
4361         }
4362 }
4363
4364 void intel_encoder_destroy(struct drm_encoder *encoder)
4365 {
4366         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4367
4368         drm_encoder_cleanup(encoder);
4369         kfree(intel_encoder);
4370 }
4371
4372 /* Simple dpms helper for encoders with just one connector, no cloning and only
4373  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4374  * state of the entire output pipe. */
4375 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4376 {
4377         if (mode == DRM_MODE_DPMS_ON) {
4378                 encoder->connectors_active = true;
4379
4380                 intel_crtc_update_dpms(encoder->base.crtc);
4381         } else {
4382                 encoder->connectors_active = false;
4383
4384                 intel_crtc_update_dpms(encoder->base.crtc);
4385         }
4386 }
4387
4388 /* Cross check the actual hw state with our own modeset state tracking (and it's
4389  * internal consistency). */
4390 static void intel_connector_check_state(struct intel_connector *connector)
4391 {
4392         if (connector->get_hw_state(connector)) {
4393                 struct intel_encoder *encoder = connector->encoder;
4394                 struct drm_crtc *crtc;
4395                 bool encoder_enabled;
4396                 enum pipe pipe;
4397
4398                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4399                               connector->base.base.id,
4400                               drm_get_connector_name(&connector->base));
4401
4402                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4403                      "wrong connector dpms state\n");
4404                 WARN(connector->base.encoder != &encoder->base,
4405                      "active connector not linked to encoder\n");
4406                 WARN(!encoder->connectors_active,
4407                      "encoder->connectors_active not set\n");
4408
4409                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4410                 WARN(!encoder_enabled, "encoder not enabled\n");
4411                 if (WARN_ON(!encoder->base.crtc))
4412                         return;
4413
4414                 crtc = encoder->base.crtc;
4415
4416                 WARN(!crtc->enabled, "crtc not enabled\n");
4417                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4418                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4419                      "encoder active on the wrong pipe\n");
4420         }
4421 }
4422
4423 /* Even simpler default implementation, if there's really no special case to
4424  * consider. */
4425 void intel_connector_dpms(struct drm_connector *connector, int mode)
4426 {
4427         /* All the simple cases only support two dpms states. */
4428         if (mode != DRM_MODE_DPMS_ON)
4429                 mode = DRM_MODE_DPMS_OFF;
4430
4431         if (mode == connector->dpms)
4432                 return;
4433
4434         connector->dpms = mode;
4435
4436         /* Only need to change hw state when actually enabled */
4437         if (connector->encoder)
4438                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4439
4440         intel_modeset_check_state(connector->dev);
4441 }
4442
4443 /* Simple connector->get_hw_state implementation for encoders that support only
4444  * one connector and no cloning and hence the encoder state determines the state
4445  * of the connector. */
4446 bool intel_connector_get_hw_state(struct intel_connector *connector)
4447 {
4448         enum pipe pipe = 0;
4449         struct intel_encoder *encoder = connector->encoder;
4450
4451         return encoder->get_hw_state(encoder, &pipe);
4452 }
4453
4454 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4455                                      struct intel_crtc_config *pipe_config)
4456 {
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458         struct intel_crtc *pipe_B_crtc =
4459                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4460
4461         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4462                       pipe_name(pipe), pipe_config->fdi_lanes);
4463         if (pipe_config->fdi_lanes > 4) {
4464                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4465                               pipe_name(pipe), pipe_config->fdi_lanes);
4466                 return false;
4467         }
4468
4469         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4470                 if (pipe_config->fdi_lanes > 2) {
4471                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4472                                       pipe_config->fdi_lanes);
4473                         return false;
4474                 } else {
4475                         return true;
4476                 }
4477         }
4478
4479         if (INTEL_INFO(dev)->num_pipes == 2)
4480                 return true;
4481
4482         /* Ivybridge 3 pipe is really complicated */
4483         switch (pipe) {
4484         case PIPE_A:
4485                 return true;
4486         case PIPE_B:
4487                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4488                     pipe_config->fdi_lanes > 2) {
4489                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4490                                       pipe_name(pipe), pipe_config->fdi_lanes);
4491                         return false;
4492                 }
4493                 return true;
4494         case PIPE_C:
4495                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4496                     pipe_B_crtc->config.fdi_lanes <= 2) {
4497                         if (pipe_config->fdi_lanes > 2) {
4498                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4499                                               pipe_name(pipe), pipe_config->fdi_lanes);
4500                                 return false;
4501                         }
4502                 } else {
4503                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4504                         return false;
4505                 }
4506                 return true;
4507         default:
4508                 BUG();
4509         }
4510 }
4511
4512 #define RETRY 1
4513 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4514                                        struct intel_crtc_config *pipe_config)
4515 {
4516         struct drm_device *dev = intel_crtc->base.dev;
4517         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4518         int lane, link_bw, fdi_dotclock;
4519         bool setup_ok, needs_recompute = false;
4520
4521 retry:
4522         /* FDI is a binary signal running at ~2.7GHz, encoding
4523          * each output octet as 10 bits. The actual frequency
4524          * is stored as a divider into a 100MHz clock, and the
4525          * mode pixel clock is stored in units of 1KHz.
4526          * Hence the bw of each lane in terms of the mode signal
4527          * is:
4528          */
4529         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4530
4531         fdi_dotclock = adjusted_mode->crtc_clock;
4532
4533         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4534                                            pipe_config->pipe_bpp);
4535
4536         pipe_config->fdi_lanes = lane;
4537
4538         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4539                                link_bw, &pipe_config->fdi_m_n);
4540
4541         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4542                                             intel_crtc->pipe, pipe_config);
4543         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4544                 pipe_config->pipe_bpp -= 2*3;
4545                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4546                               pipe_config->pipe_bpp);
4547                 needs_recompute = true;
4548                 pipe_config->bw_constrained = true;
4549
4550                 goto retry;
4551         }
4552
4553         if (needs_recompute)
4554                 return RETRY;
4555
4556         return setup_ok ? 0 : -EINVAL;
4557 }
4558
4559 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4560                                    struct intel_crtc_config *pipe_config)
4561 {
4562         pipe_config->ips_enabled = i915_enable_ips &&
4563                                    hsw_crtc_supports_ips(crtc) &&
4564                                    pipe_config->pipe_bpp <= 24;
4565 }
4566
4567 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4568                                      struct intel_crtc_config *pipe_config)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4572
4573         /* FIXME should check pixel clock limits on all platforms */
4574         if (INTEL_INFO(dev)->gen < 4) {
4575                 struct drm_i915_private *dev_priv = dev->dev_private;
4576                 int clock_limit =
4577                         dev_priv->display.get_display_clock_speed(dev);
4578
4579                 /*
4580                  * Enable pixel doubling when the dot clock
4581                  * is > 90% of the (display) core speed.
4582                  *
4583                  * GDG double wide on either pipe,
4584                  * otherwise pipe A only.
4585                  */
4586                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4587                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4588                         clock_limit *= 2;
4589                         pipe_config->double_wide = true;
4590                 }
4591
4592                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4593                         return -EINVAL;
4594         }
4595
4596         /*
4597          * Pipe horizontal size must be even in:
4598          * - DVO ganged mode
4599          * - LVDS dual channel mode
4600          * - Double wide pipe
4601          */
4602         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4603              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4604                 pipe_config->pipe_src_w &= ~1;
4605
4606         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4607          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4608          */
4609         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4610                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4611                 return -EINVAL;
4612
4613         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4614                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4615         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4616                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4617                  * for lvds. */
4618                 pipe_config->pipe_bpp = 8*3;
4619         }
4620
4621         if (HAS_IPS(dev))
4622                 hsw_compute_ips_config(crtc, pipe_config);
4623
4624         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4625          * clock survives for now. */
4626         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4627                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4628
4629         if (pipe_config->has_pch_encoder)
4630                 return ironlake_fdi_compute_config(crtc, pipe_config);
4631
4632         return 0;
4633 }
4634
4635 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4636 {
4637         return 400000; /* FIXME */
4638 }
4639
4640 static int i945_get_display_clock_speed(struct drm_device *dev)
4641 {
4642         return 400000;
4643 }
4644
4645 static int i915_get_display_clock_speed(struct drm_device *dev)
4646 {
4647         return 333000;
4648 }
4649
4650 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4651 {
4652         return 200000;
4653 }
4654
4655 static int pnv_get_display_clock_speed(struct drm_device *dev)
4656 {
4657         u16 gcfgc = 0;
4658
4659         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4660
4661         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4662         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4663                 return 267000;
4664         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4665                 return 333000;
4666         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4667                 return 444000;
4668         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4669                 return 200000;
4670         default:
4671                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4672         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4673                 return 133000;
4674         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4675                 return 167000;
4676         }
4677 }
4678
4679 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4680 {
4681         u16 gcfgc = 0;
4682
4683         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4684
4685         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4686                 return 133000;
4687         else {
4688                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4689                 case GC_DISPLAY_CLOCK_333_MHZ:
4690                         return 333000;
4691                 default:
4692                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4693                         return 190000;
4694                 }
4695         }
4696 }
4697
4698 static int i865_get_display_clock_speed(struct drm_device *dev)
4699 {
4700         return 266000;
4701 }
4702
4703 static int i855_get_display_clock_speed(struct drm_device *dev)
4704 {
4705         u16 hpllcc = 0;
4706         /* Assume that the hardware is in the high speed state.  This
4707          * should be the default.
4708          */
4709         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4710         case GC_CLOCK_133_200:
4711         case GC_CLOCK_100_200:
4712                 return 200000;
4713         case GC_CLOCK_166_250:
4714                 return 250000;
4715         case GC_CLOCK_100_133:
4716                 return 133000;
4717         }
4718
4719         /* Shouldn't happen */
4720         return 0;
4721 }
4722
4723 static int i830_get_display_clock_speed(struct drm_device *dev)
4724 {
4725         return 133000;
4726 }
4727
4728 static void
4729 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4730 {
4731         while (*num > DATA_LINK_M_N_MASK ||
4732                *den > DATA_LINK_M_N_MASK) {
4733                 *num >>= 1;
4734                 *den >>= 1;
4735         }
4736 }
4737
4738 static void compute_m_n(unsigned int m, unsigned int n,
4739                         uint32_t *ret_m, uint32_t *ret_n)
4740 {
4741         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4742         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4743         intel_reduce_m_n_ratio(ret_m, ret_n);
4744 }
4745
4746 void
4747 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4748                        int pixel_clock, int link_clock,
4749                        struct intel_link_m_n *m_n)
4750 {
4751         m_n->tu = 64;
4752
4753         compute_m_n(bits_per_pixel * pixel_clock,
4754                     link_clock * nlanes * 8,
4755                     &m_n->gmch_m, &m_n->gmch_n);
4756
4757         compute_m_n(pixel_clock, link_clock,
4758                     &m_n->link_m, &m_n->link_n);
4759 }
4760
4761 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4762 {
4763         if (i915_panel_use_ssc >= 0)
4764                 return i915_panel_use_ssc != 0;
4765         return dev_priv->vbt.lvds_use_ssc
4766                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4767 }
4768
4769 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4770 {
4771         struct drm_device *dev = crtc->dev;
4772         struct drm_i915_private *dev_priv = dev->dev_private;
4773         int refclk;
4774
4775         if (IS_VALLEYVIEW(dev)) {
4776                 refclk = 100000;
4777         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4778             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4779                 refclk = dev_priv->vbt.lvds_ssc_freq;
4780                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4781         } else if (!IS_GEN2(dev)) {
4782                 refclk = 96000;
4783         } else {
4784                 refclk = 48000;
4785         }
4786
4787         return refclk;
4788 }
4789
4790 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4791 {
4792         return (1 << dpll->n) << 16 | dpll->m2;
4793 }
4794
4795 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4796 {
4797         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4798 }
4799
4800 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4801                                      intel_clock_t *reduced_clock)
4802 {
4803         struct drm_device *dev = crtc->base.dev;
4804         struct drm_i915_private *dev_priv = dev->dev_private;
4805         int pipe = crtc->pipe;
4806         u32 fp, fp2 = 0;
4807
4808         if (IS_PINEVIEW(dev)) {
4809                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4810                 if (reduced_clock)
4811                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4812         } else {
4813                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4814                 if (reduced_clock)
4815                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4816         }
4817
4818         I915_WRITE(FP0(pipe), fp);
4819         crtc->config.dpll_hw_state.fp0 = fp;
4820
4821         crtc->lowfreq_avail = false;
4822         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4823             reduced_clock && i915_powersave) {
4824                 I915_WRITE(FP1(pipe), fp2);
4825                 crtc->config.dpll_hw_state.fp1 = fp2;
4826                 crtc->lowfreq_avail = true;
4827         } else {
4828                 I915_WRITE(FP1(pipe), fp);
4829                 crtc->config.dpll_hw_state.fp1 = fp;
4830         }
4831 }
4832
4833 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4834                 pipe)
4835 {
4836         u32 reg_val;
4837
4838         /*
4839          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4840          * and set it to a reasonable value instead.
4841          */
4842         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4843         reg_val &= 0xffffff00;
4844         reg_val |= 0x00000030;
4845         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4846
4847         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4848         reg_val &= 0x8cffffff;
4849         reg_val = 0x8c000000;
4850         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4851
4852         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4853         reg_val &= 0xffffff00;
4854         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4855
4856         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4857         reg_val &= 0x00ffffff;
4858         reg_val |= 0xb0000000;
4859         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4860 }
4861
4862 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4863                                          struct intel_link_m_n *m_n)
4864 {
4865         struct drm_device *dev = crtc->base.dev;
4866         struct drm_i915_private *dev_priv = dev->dev_private;
4867         int pipe = crtc->pipe;
4868
4869         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4870         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4871         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4872         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4873 }
4874
4875 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4876                                          struct intel_link_m_n *m_n)
4877 {
4878         struct drm_device *dev = crtc->base.dev;
4879         struct drm_i915_private *dev_priv = dev->dev_private;
4880         int pipe = crtc->pipe;
4881         enum transcoder transcoder = crtc->config.cpu_transcoder;
4882
4883         if (INTEL_INFO(dev)->gen >= 5) {
4884                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4885                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4886                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4887                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4888         } else {
4889                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4890                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4891                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4892                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4893         }
4894 }
4895
4896 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4897 {
4898         if (crtc->config.has_pch_encoder)
4899                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4900         else
4901                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4902 }
4903
4904 static void vlv_update_pll(struct intel_crtc *crtc)
4905 {
4906         struct drm_device *dev = crtc->base.dev;
4907         struct drm_i915_private *dev_priv = dev->dev_private;
4908         int pipe = crtc->pipe;
4909         u32 dpll, mdiv;
4910         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4911         u32 coreclk, reg_val, dpll_md;
4912
4913         mutex_lock(&dev_priv->dpio_lock);
4914
4915         bestn = crtc->config.dpll.n;
4916         bestm1 = crtc->config.dpll.m1;
4917         bestm2 = crtc->config.dpll.m2;
4918         bestp1 = crtc->config.dpll.p1;
4919         bestp2 = crtc->config.dpll.p2;
4920
4921         /* See eDP HDMI DPIO driver vbios notes doc */
4922
4923         /* PLL B needs special handling */
4924         if (pipe)
4925                 vlv_pllb_recal_opamp(dev_priv, pipe);
4926
4927         /* Set up Tx target for periodic Rcomp update */
4928         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4929
4930         /* Disable target IRef on PLL */
4931         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4932         reg_val &= 0x00ffffff;
4933         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4934
4935         /* Disable fast lock */
4936         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4937
4938         /* Set idtafcrecal before PLL is enabled */
4939         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4940         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4941         mdiv |= ((bestn << DPIO_N_SHIFT));
4942         mdiv |= (1 << DPIO_K_SHIFT);
4943
4944         /*
4945          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4946          * but we don't support that).
4947          * Note: don't use the DAC post divider as it seems unstable.
4948          */
4949         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4950         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4951
4952         mdiv |= DPIO_ENABLE_CALIBRATION;
4953         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4954
4955         /* Set HBR and RBR LPF coefficients */
4956         if (crtc->config.port_clock == 162000 ||
4957             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4958             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4959                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4960                                  0x009f0003);
4961         else
4962                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4963                                  0x00d0000f);
4964
4965         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4966             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4967                 /* Use SSC source */
4968                 if (!pipe)
4969                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4970                                          0x0df40000);
4971                 else
4972                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4973                                          0x0df70000);
4974         } else { /* HDMI or VGA */
4975                 /* Use bend source */
4976                 if (!pipe)
4977                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4978                                          0x0df70000);
4979                 else
4980                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4981                                          0x0df40000);
4982         }
4983
4984         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4985         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4986         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4987             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4988                 coreclk |= 0x01000000;
4989         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4990
4991         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4992
4993         /*
4994          * Enable DPIO clock input. We should never disable the reference
4995          * clock for pipe B, since VGA hotplug / manual detection depends
4996          * on it.
4997          */
4998         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4999                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5000         /* We should never disable this, set it here for state tracking */
5001         if (pipe == PIPE_B)
5002                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5003         dpll |= DPLL_VCO_ENABLE;
5004         crtc->config.dpll_hw_state.dpll = dpll;
5005
5006         dpll_md = (crtc->config.pixel_multiplier - 1)
5007                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5008         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5009
5010         if (crtc->config.has_dp_encoder)
5011                 intel_dp_set_m_n(crtc);
5012
5013         mutex_unlock(&dev_priv->dpio_lock);
5014 }
5015
5016 static void i9xx_update_pll(struct intel_crtc *crtc,
5017                             intel_clock_t *reduced_clock,
5018                             int num_connectors)
5019 {
5020         struct drm_device *dev = crtc->base.dev;
5021         struct drm_i915_private *dev_priv = dev->dev_private;
5022         u32 dpll;
5023         bool is_sdvo;
5024         struct dpll *clock = &crtc->config.dpll;
5025
5026         i9xx_update_pll_dividers(crtc, reduced_clock);
5027
5028         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5029                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5030
5031         dpll = DPLL_VGA_MODE_DIS;
5032
5033         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5034                 dpll |= DPLLB_MODE_LVDS;
5035         else
5036                 dpll |= DPLLB_MODE_DAC_SERIAL;
5037
5038         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5039                 dpll |= (crtc->config.pixel_multiplier - 1)
5040                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5041         }
5042
5043         if (is_sdvo)
5044                 dpll |= DPLL_SDVO_HIGH_SPEED;
5045
5046         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5047                 dpll |= DPLL_SDVO_HIGH_SPEED;
5048
5049         /* compute bitmask from p1 value */
5050         if (IS_PINEVIEW(dev))
5051                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5052         else {
5053                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5054                 if (IS_G4X(dev) && reduced_clock)
5055                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5056         }
5057         switch (clock->p2) {
5058         case 5:
5059                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5060                 break;
5061         case 7:
5062                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5063                 break;
5064         case 10:
5065                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5066                 break;
5067         case 14:
5068                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5069                 break;
5070         }
5071         if (INTEL_INFO(dev)->gen >= 4)
5072                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5073
5074         if (crtc->config.sdvo_tv_clock)
5075                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5076         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5077                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5078                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5079         else
5080                 dpll |= PLL_REF_INPUT_DREFCLK;
5081
5082         dpll |= DPLL_VCO_ENABLE;
5083         crtc->config.dpll_hw_state.dpll = dpll;
5084
5085         if (INTEL_INFO(dev)->gen >= 4) {
5086                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5087                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5088                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5089         }
5090
5091         if (crtc->config.has_dp_encoder)
5092                 intel_dp_set_m_n(crtc);
5093 }
5094
5095 static void i8xx_update_pll(struct intel_crtc *crtc,
5096                             intel_clock_t *reduced_clock,
5097                             int num_connectors)
5098 {
5099         struct drm_device *dev = crtc->base.dev;
5100         struct drm_i915_private *dev_priv = dev->dev_private;
5101         u32 dpll;
5102         struct dpll *clock = &crtc->config.dpll;
5103
5104         i9xx_update_pll_dividers(crtc, reduced_clock);
5105
5106         dpll = DPLL_VGA_MODE_DIS;
5107
5108         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5109                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5110         } else {
5111                 if (clock->p1 == 2)
5112                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5113                 else
5114                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5115                 if (clock->p2 == 4)
5116                         dpll |= PLL_P2_DIVIDE_BY_4;
5117         }
5118
5119         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5120                 dpll |= DPLL_DVO_2X_MODE;
5121
5122         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5123                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5124                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5125         else
5126                 dpll |= PLL_REF_INPUT_DREFCLK;
5127
5128         dpll |= DPLL_VCO_ENABLE;
5129         crtc->config.dpll_hw_state.dpll = dpll;
5130 }
5131
5132 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5133 {
5134         struct drm_device *dev = intel_crtc->base.dev;
5135         struct drm_i915_private *dev_priv = dev->dev_private;
5136         enum pipe pipe = intel_crtc->pipe;
5137         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5138         struct drm_display_mode *adjusted_mode =
5139                 &intel_crtc->config.adjusted_mode;
5140         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5141
5142         /* We need to be careful not to changed the adjusted mode, for otherwise
5143          * the hw state checker will get angry at the mismatch. */
5144         crtc_vtotal = adjusted_mode->crtc_vtotal;
5145         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5146
5147         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5148                 /* the chip adds 2 halflines automatically */
5149                 crtc_vtotal -= 1;
5150                 crtc_vblank_end -= 1;
5151                 vsyncshift = adjusted_mode->crtc_hsync_start
5152                              - adjusted_mode->crtc_htotal / 2;
5153         } else {
5154                 vsyncshift = 0;
5155         }
5156
5157         if (INTEL_INFO(dev)->gen > 3)
5158                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5159
5160         I915_WRITE(HTOTAL(cpu_transcoder),
5161                    (adjusted_mode->crtc_hdisplay - 1) |
5162                    ((adjusted_mode->crtc_htotal - 1) << 16));
5163         I915_WRITE(HBLANK(cpu_transcoder),
5164                    (adjusted_mode->crtc_hblank_start - 1) |
5165                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5166         I915_WRITE(HSYNC(cpu_transcoder),
5167                    (adjusted_mode->crtc_hsync_start - 1) |
5168                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5169
5170         I915_WRITE(VTOTAL(cpu_transcoder),
5171                    (adjusted_mode->crtc_vdisplay - 1) |
5172                    ((crtc_vtotal - 1) << 16));
5173         I915_WRITE(VBLANK(cpu_transcoder),
5174                    (adjusted_mode->crtc_vblank_start - 1) |
5175                    ((crtc_vblank_end - 1) << 16));
5176         I915_WRITE(VSYNC(cpu_transcoder),
5177                    (adjusted_mode->crtc_vsync_start - 1) |
5178                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5179
5180         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5181          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5182          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5183          * bits. */
5184         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5185             (pipe == PIPE_B || pipe == PIPE_C))
5186                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5187
5188         /* pipesrc controls the size that is scaled from, which should
5189          * always be the user's requested size.
5190          */
5191         I915_WRITE(PIPESRC(pipe),
5192                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5193                    (intel_crtc->config.pipe_src_h - 1));
5194 }
5195
5196 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5197                                    struct intel_crtc_config *pipe_config)
5198 {
5199         struct drm_device *dev = crtc->base.dev;
5200         struct drm_i915_private *dev_priv = dev->dev_private;
5201         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5202         uint32_t tmp;
5203
5204         tmp = I915_READ(HTOTAL(cpu_transcoder));
5205         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5206         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5207         tmp = I915_READ(HBLANK(cpu_transcoder));
5208         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5209         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5210         tmp = I915_READ(HSYNC(cpu_transcoder));
5211         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5212         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5213
5214         tmp = I915_READ(VTOTAL(cpu_transcoder));
5215         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5216         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5217         tmp = I915_READ(VBLANK(cpu_transcoder));
5218         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5219         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5220         tmp = I915_READ(VSYNC(cpu_transcoder));
5221         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5222         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5223
5224         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5225                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5226                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5227                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5228         }
5229
5230         tmp = I915_READ(PIPESRC(crtc->pipe));
5231         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5232         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5233
5234         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5235         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5236 }
5237
5238 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5239                                              struct intel_crtc_config *pipe_config)
5240 {
5241         struct drm_crtc *crtc = &intel_crtc->base;
5242
5243         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5244         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5245         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5246         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5247
5248         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5249         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5250         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5251         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5252
5253         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5254
5255         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5256         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5257 }
5258
5259 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5260 {
5261         struct drm_device *dev = intel_crtc->base.dev;
5262         struct drm_i915_private *dev_priv = dev->dev_private;
5263         uint32_t pipeconf;
5264
5265         pipeconf = 0;
5266
5267         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5268             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5269                 pipeconf |= PIPECONF_ENABLE;
5270
5271         if (intel_crtc->config.double_wide)
5272                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5273
5274         /* only g4x and later have fancy bpc/dither controls */
5275         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5276                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5277                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5278                         pipeconf |= PIPECONF_DITHER_EN |
5279                                     PIPECONF_DITHER_TYPE_SP;
5280
5281                 switch (intel_crtc->config.pipe_bpp) {
5282                 case 18:
5283                         pipeconf |= PIPECONF_6BPC;
5284                         break;
5285                 case 24:
5286                         pipeconf |= PIPECONF_8BPC;
5287                         break;
5288                 case 30:
5289                         pipeconf |= PIPECONF_10BPC;
5290                         break;
5291                 default:
5292                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5293                         BUG();
5294                 }
5295         }
5296
5297         if (HAS_PIPE_CXSR(dev)) {
5298                 if (intel_crtc->lowfreq_avail) {
5299                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5300                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5301                 } else {
5302                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5303                 }
5304         }
5305
5306         if (!IS_GEN2(dev) &&
5307             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5308                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5309         else
5310                 pipeconf |= PIPECONF_PROGRESSIVE;
5311
5312         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5313                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5314
5315         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5316         POSTING_READ(PIPECONF(intel_crtc->pipe));
5317 }
5318
5319 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5320                               int x, int y,
5321                               struct drm_framebuffer *fb)
5322 {
5323         struct drm_device *dev = crtc->dev;
5324         struct drm_i915_private *dev_priv = dev->dev_private;
5325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5326         int pipe = intel_crtc->pipe;
5327         int plane = intel_crtc->plane;
5328         int refclk, num_connectors = 0;
5329         intel_clock_t clock, reduced_clock;
5330         u32 dspcntr;
5331         bool ok, has_reduced_clock = false;
5332         bool is_lvds = false, is_dsi = false;
5333         struct intel_encoder *encoder;
5334         const intel_limit_t *limit;
5335         int ret;
5336
5337         for_each_encoder_on_crtc(dev, crtc, encoder) {
5338                 switch (encoder->type) {
5339                 case INTEL_OUTPUT_LVDS:
5340                         is_lvds = true;
5341                         break;
5342                 case INTEL_OUTPUT_DSI:
5343                         is_dsi = true;
5344                         break;
5345                 }
5346
5347                 num_connectors++;
5348         }
5349
5350         if (is_dsi)
5351                 goto skip_dpll;
5352
5353         if (!intel_crtc->config.clock_set) {
5354                 refclk = i9xx_get_refclk(crtc, num_connectors);
5355
5356                 /*
5357                  * Returns a set of divisors for the desired target clock with
5358                  * the given refclk, or FALSE.  The returned values represent
5359                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5360                  * 2) / p1 / p2.
5361                  */
5362                 limit = intel_limit(crtc, refclk);
5363                 ok = dev_priv->display.find_dpll(limit, crtc,
5364                                                  intel_crtc->config.port_clock,
5365                                                  refclk, NULL, &clock);
5366                 if (!ok) {
5367                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5368                         return -EINVAL;
5369                 }
5370
5371                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5372                         /*
5373                          * Ensure we match the reduced clock's P to the target
5374                          * clock.  If the clocks don't match, we can't switch
5375                          * the display clock by using the FP0/FP1. In such case
5376                          * we will disable the LVDS downclock feature.
5377                          */
5378                         has_reduced_clock =
5379                                 dev_priv->display.find_dpll(limit, crtc,
5380                                                             dev_priv->lvds_downclock,
5381                                                             refclk, &clock,
5382                                                             &reduced_clock);
5383                 }
5384                 /* Compat-code for transition, will disappear. */
5385                 intel_crtc->config.dpll.n = clock.n;
5386                 intel_crtc->config.dpll.m1 = clock.m1;
5387                 intel_crtc->config.dpll.m2 = clock.m2;
5388                 intel_crtc->config.dpll.p1 = clock.p1;
5389                 intel_crtc->config.dpll.p2 = clock.p2;
5390         }
5391
5392         if (IS_GEN2(dev)) {
5393                 i8xx_update_pll(intel_crtc,
5394                                 has_reduced_clock ? &reduced_clock : NULL,
5395                                 num_connectors);
5396         } else if (IS_VALLEYVIEW(dev)) {
5397                 vlv_update_pll(intel_crtc);
5398         } else {
5399                 i9xx_update_pll(intel_crtc,
5400                                 has_reduced_clock ? &reduced_clock : NULL,
5401                                 num_connectors);
5402         }
5403
5404 skip_dpll:
5405         /* Set up the display plane register */
5406         dspcntr = DISPPLANE_GAMMA_ENABLE;
5407
5408         if (!IS_VALLEYVIEW(dev)) {
5409                 if (pipe == 0)
5410                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5411                 else
5412                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5413         }
5414
5415         intel_set_pipe_timings(intel_crtc);
5416
5417         /* pipesrc and dspsize control the size that is scaled from,
5418          * which should always be the user's requested size.
5419          */
5420         I915_WRITE(DSPSIZE(plane),
5421                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5422                    (intel_crtc->config.pipe_src_w - 1));
5423         I915_WRITE(DSPPOS(plane), 0);
5424
5425         i9xx_set_pipeconf(intel_crtc);
5426
5427         I915_WRITE(DSPCNTR(plane), dspcntr);
5428         POSTING_READ(DSPCNTR(plane));
5429
5430         ret = intel_pipe_set_base(crtc, x, y, fb);
5431
5432         return ret;
5433 }
5434
5435 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5436                                  struct intel_crtc_config *pipe_config)
5437 {
5438         struct drm_device *dev = crtc->base.dev;
5439         struct drm_i915_private *dev_priv = dev->dev_private;
5440         uint32_t tmp;
5441
5442         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5443                 return;
5444
5445         tmp = I915_READ(PFIT_CONTROL);
5446         if (!(tmp & PFIT_ENABLE))
5447                 return;
5448
5449         /* Check whether the pfit is attached to our pipe. */
5450         if (INTEL_INFO(dev)->gen < 4) {
5451                 if (crtc->pipe != PIPE_B)
5452                         return;
5453         } else {
5454                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5455                         return;
5456         }
5457
5458         pipe_config->gmch_pfit.control = tmp;
5459         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5460         if (INTEL_INFO(dev)->gen < 5)
5461                 pipe_config->gmch_pfit.lvds_border_bits =
5462                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5463 }
5464
5465 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5466                                struct intel_crtc_config *pipe_config)
5467 {
5468         struct drm_device *dev = crtc->base.dev;
5469         struct drm_i915_private *dev_priv = dev->dev_private;
5470         int pipe = pipe_config->cpu_transcoder;
5471         intel_clock_t clock;
5472         u32 mdiv;
5473         int refclk = 100000;
5474
5475         mutex_lock(&dev_priv->dpio_lock);
5476         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5477         mutex_unlock(&dev_priv->dpio_lock);
5478
5479         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5480         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5481         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5482         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5483         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5484
5485         vlv_clock(refclk, &clock);
5486
5487         /* clock.dot is the fast clock */
5488         pipe_config->port_clock = clock.dot / 5;
5489 }
5490
5491 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5492                                  struct intel_crtc_config *pipe_config)
5493 {
5494         struct drm_device *dev = crtc->base.dev;
5495         struct drm_i915_private *dev_priv = dev->dev_private;
5496         uint32_t tmp;
5497
5498         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5499         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5500
5501         tmp = I915_READ(PIPECONF(crtc->pipe));
5502         if (!(tmp & PIPECONF_ENABLE))
5503                 return false;
5504
5505         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5506                 switch (tmp & PIPECONF_BPC_MASK) {
5507                 case PIPECONF_6BPC:
5508                         pipe_config->pipe_bpp = 18;
5509                         break;
5510                 case PIPECONF_8BPC:
5511                         pipe_config->pipe_bpp = 24;
5512                         break;
5513                 case PIPECONF_10BPC:
5514                         pipe_config->pipe_bpp = 30;
5515                         break;
5516                 default:
5517                         break;
5518                 }
5519         }
5520
5521         if (INTEL_INFO(dev)->gen < 4)
5522                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5523
5524         intel_get_pipe_timings(crtc, pipe_config);
5525
5526         i9xx_get_pfit_config(crtc, pipe_config);
5527
5528         if (INTEL_INFO(dev)->gen >= 4) {
5529                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5530                 pipe_config->pixel_multiplier =
5531                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5532                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5533                 pipe_config->dpll_hw_state.dpll_md = tmp;
5534         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5535                 tmp = I915_READ(DPLL(crtc->pipe));
5536                 pipe_config->pixel_multiplier =
5537                         ((tmp & SDVO_MULTIPLIER_MASK)
5538                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5539         } else {
5540                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5541                  * port and will be fixed up in the encoder->get_config
5542                  * function. */
5543                 pipe_config->pixel_multiplier = 1;
5544         }
5545         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5546         if (!IS_VALLEYVIEW(dev)) {
5547                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5548                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5549         } else {
5550                 /* Mask out read-only status bits. */
5551                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5552                                                      DPLL_PORTC_READY_MASK |
5553                                                      DPLL_PORTB_READY_MASK);
5554         }
5555
5556         if (IS_VALLEYVIEW(dev))
5557                 vlv_crtc_clock_get(crtc, pipe_config);
5558         else
5559                 i9xx_crtc_clock_get(crtc, pipe_config);
5560
5561         return true;
5562 }
5563
5564 static void ironlake_init_pch_refclk(struct drm_device *dev)
5565 {
5566         struct drm_i915_private *dev_priv = dev->dev_private;
5567         struct drm_mode_config *mode_config = &dev->mode_config;
5568         struct intel_encoder *encoder;
5569         u32 val, final;
5570         bool has_lvds = false;
5571         bool has_cpu_edp = false;
5572         bool has_panel = false;
5573         bool has_ck505 = false;
5574         bool can_ssc = false;
5575
5576         /* We need to take the global config into account */
5577         list_for_each_entry(encoder, &mode_config->encoder_list,
5578                             base.head) {
5579                 switch (encoder->type) {
5580                 case INTEL_OUTPUT_LVDS:
5581                         has_panel = true;
5582                         has_lvds = true;
5583                         break;
5584                 case INTEL_OUTPUT_EDP:
5585                         has_panel = true;
5586                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5587                                 has_cpu_edp = true;
5588                         break;
5589                 }
5590         }
5591
5592         if (HAS_PCH_IBX(dev)) {
5593                 has_ck505 = dev_priv->vbt.display_clock_mode;
5594                 can_ssc = has_ck505;
5595         } else {
5596                 has_ck505 = false;
5597                 can_ssc = true;
5598         }
5599
5600         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5601                       has_panel, has_lvds, has_ck505);
5602
5603         /* Ironlake: try to setup display ref clock before DPLL
5604          * enabling. This is only under driver's control after
5605          * PCH B stepping, previous chipset stepping should be
5606          * ignoring this setting.
5607          */
5608         val = I915_READ(PCH_DREF_CONTROL);
5609
5610         /* As we must carefully and slowly disable/enable each source in turn,
5611          * compute the final state we want first and check if we need to
5612          * make any changes at all.
5613          */
5614         final = val;
5615         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5616         if (has_ck505)
5617                 final |= DREF_NONSPREAD_CK505_ENABLE;
5618         else
5619                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5620
5621         final &= ~DREF_SSC_SOURCE_MASK;
5622         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5623         final &= ~DREF_SSC1_ENABLE;
5624
5625         if (has_panel) {
5626                 final |= DREF_SSC_SOURCE_ENABLE;
5627
5628                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5629                         final |= DREF_SSC1_ENABLE;
5630
5631                 if (has_cpu_edp) {
5632                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5633                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5634                         else
5635                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5636                 } else
5637                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5638         } else {
5639                 final |= DREF_SSC_SOURCE_DISABLE;
5640                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5641         }
5642
5643         if (final == val)
5644                 return;
5645
5646         /* Always enable nonspread source */
5647         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5648
5649         if (has_ck505)
5650                 val |= DREF_NONSPREAD_CK505_ENABLE;
5651         else
5652                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5653
5654         if (has_panel) {
5655                 val &= ~DREF_SSC_SOURCE_MASK;
5656                 val |= DREF_SSC_SOURCE_ENABLE;
5657
5658                 /* SSC must be turned on before enabling the CPU output  */
5659                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5660                         DRM_DEBUG_KMS("Using SSC on panel\n");
5661                         val |= DREF_SSC1_ENABLE;
5662                 } else
5663                         val &= ~DREF_SSC1_ENABLE;
5664
5665                 /* Get SSC going before enabling the outputs */
5666                 I915_WRITE(PCH_DREF_CONTROL, val);
5667                 POSTING_READ(PCH_DREF_CONTROL);
5668                 udelay(200);
5669
5670                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5671
5672                 /* Enable CPU source on CPU attached eDP */
5673                 if (has_cpu_edp) {
5674                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5675                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5676                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5677                         }
5678                         else
5679                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5680                 } else
5681                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5682
5683                 I915_WRITE(PCH_DREF_CONTROL, val);
5684                 POSTING_READ(PCH_DREF_CONTROL);
5685                 udelay(200);
5686         } else {
5687                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5688
5689                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5690
5691                 /* Turn off CPU output */
5692                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5693
5694                 I915_WRITE(PCH_DREF_CONTROL, val);
5695                 POSTING_READ(PCH_DREF_CONTROL);
5696                 udelay(200);
5697
5698                 /* Turn off the SSC source */
5699                 val &= ~DREF_SSC_SOURCE_MASK;
5700                 val |= DREF_SSC_SOURCE_DISABLE;
5701
5702                 /* Turn off SSC1 */
5703                 val &= ~DREF_SSC1_ENABLE;
5704
5705                 I915_WRITE(PCH_DREF_CONTROL, val);
5706                 POSTING_READ(PCH_DREF_CONTROL);
5707                 udelay(200);
5708         }
5709
5710         BUG_ON(val != final);
5711 }
5712
5713 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5714 {
5715         uint32_t tmp;
5716
5717         tmp = I915_READ(SOUTH_CHICKEN2);
5718         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5719         I915_WRITE(SOUTH_CHICKEN2, tmp);
5720
5721         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5722                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5723                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5724
5725         tmp = I915_READ(SOUTH_CHICKEN2);
5726         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5727         I915_WRITE(SOUTH_CHICKEN2, tmp);
5728
5729         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5730                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5731                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5732 }
5733
5734 /* WaMPhyProgramming:hsw */
5735 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5736 {
5737         uint32_t tmp;
5738
5739         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5740         tmp &= ~(0xFF << 24);
5741         tmp |= (0x12 << 24);
5742         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5743
5744         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5745         tmp |= (1 << 11);
5746         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5747
5748         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5749         tmp |= (1 << 11);
5750         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5751
5752         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5753         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5754         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5755
5756         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5757         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5758         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5759
5760         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5761         tmp &= ~(7 << 13);
5762         tmp |= (5 << 13);
5763         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5764
5765         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5766         tmp &= ~(7 << 13);
5767         tmp |= (5 << 13);
5768         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5769
5770         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5771         tmp &= ~0xFF;
5772         tmp |= 0x1C;
5773         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5774
5775         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5776         tmp &= ~0xFF;
5777         tmp |= 0x1C;
5778         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5779
5780         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5781         tmp &= ~(0xFF << 16);
5782         tmp |= (0x1C << 16);
5783         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5784
5785         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5786         tmp &= ~(0xFF << 16);
5787         tmp |= (0x1C << 16);
5788         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5789
5790         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5791         tmp |= (1 << 27);
5792         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5793
5794         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5795         tmp |= (1 << 27);
5796         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5797
5798         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5799         tmp &= ~(0xF << 28);
5800         tmp |= (4 << 28);
5801         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5802
5803         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5804         tmp &= ~(0xF << 28);
5805         tmp |= (4 << 28);
5806         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5807 }
5808
5809 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5810  * Programming" based on the parameters passed:
5811  * - Sequence to enable CLKOUT_DP
5812  * - Sequence to enable CLKOUT_DP without spread
5813  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5814  */
5815 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5816                                  bool with_fdi)
5817 {
5818         struct drm_i915_private *dev_priv = dev->dev_private;
5819         uint32_t reg, tmp;
5820
5821         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5822                 with_spread = true;
5823         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5824                  with_fdi, "LP PCH doesn't have FDI\n"))
5825                 with_fdi = false;
5826
5827         mutex_lock(&dev_priv->dpio_lock);
5828
5829         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5830         tmp &= ~SBI_SSCCTL_DISABLE;
5831         tmp |= SBI_SSCCTL_PATHALT;
5832         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5833
5834         udelay(24);
5835
5836         if (with_spread) {
5837                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5838                 tmp &= ~SBI_SSCCTL_PATHALT;
5839                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5840
5841                 if (with_fdi) {
5842                         lpt_reset_fdi_mphy(dev_priv);
5843                         lpt_program_fdi_mphy(dev_priv);
5844                 }
5845         }
5846
5847         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5848                SBI_GEN0 : SBI_DBUFF0;
5849         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5850         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5851         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5852
5853         mutex_unlock(&dev_priv->dpio_lock);
5854 }
5855
5856 /* Sequence to disable CLKOUT_DP */
5857 static void lpt_disable_clkout_dp(struct drm_device *dev)
5858 {
5859         struct drm_i915_private *dev_priv = dev->dev_private;
5860         uint32_t reg, tmp;
5861
5862         mutex_lock(&dev_priv->dpio_lock);
5863
5864         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5865                SBI_GEN0 : SBI_DBUFF0;
5866         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5867         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5868         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5869
5870         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5871         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5872                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5873                         tmp |= SBI_SSCCTL_PATHALT;
5874                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5875                         udelay(32);
5876                 }
5877                 tmp |= SBI_SSCCTL_DISABLE;
5878                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5879         }
5880
5881         mutex_unlock(&dev_priv->dpio_lock);
5882 }
5883
5884 static void lpt_init_pch_refclk(struct drm_device *dev)
5885 {
5886         struct drm_mode_config *mode_config = &dev->mode_config;
5887         struct intel_encoder *encoder;
5888         bool has_vga = false;
5889
5890         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5891                 switch (encoder->type) {
5892                 case INTEL_OUTPUT_ANALOG:
5893                         has_vga = true;
5894                         break;
5895                 }
5896         }
5897
5898         if (has_vga)
5899                 lpt_enable_clkout_dp(dev, true, true);
5900         else
5901                 lpt_disable_clkout_dp(dev);
5902 }
5903
5904 /*
5905  * Initialize reference clocks when the driver loads
5906  */
5907 void intel_init_pch_refclk(struct drm_device *dev)
5908 {
5909         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5910                 ironlake_init_pch_refclk(dev);
5911         else if (HAS_PCH_LPT(dev))
5912                 lpt_init_pch_refclk(dev);
5913 }
5914
5915 static int ironlake_get_refclk(struct drm_crtc *crtc)
5916 {
5917         struct drm_device *dev = crtc->dev;
5918         struct drm_i915_private *dev_priv = dev->dev_private;
5919         struct intel_encoder *encoder;
5920         int num_connectors = 0;
5921         bool is_lvds = false;
5922
5923         for_each_encoder_on_crtc(dev, crtc, encoder) {
5924                 switch (encoder->type) {
5925                 case INTEL_OUTPUT_LVDS:
5926                         is_lvds = true;
5927                         break;
5928                 }
5929                 num_connectors++;
5930         }
5931
5932         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5933                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5934                               dev_priv->vbt.lvds_ssc_freq);
5935                 return dev_priv->vbt.lvds_ssc_freq;
5936         }
5937
5938         return 120000;
5939 }
5940
5941 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5942 {
5943         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5945         int pipe = intel_crtc->pipe;
5946         uint32_t val;
5947
5948         val = 0;
5949
5950         switch (intel_crtc->config.pipe_bpp) {
5951         case 18:
5952                 val |= PIPECONF_6BPC;
5953                 break;
5954         case 24:
5955                 val |= PIPECONF_8BPC;
5956                 break;
5957         case 30:
5958                 val |= PIPECONF_10BPC;
5959                 break;
5960         case 36:
5961                 val |= PIPECONF_12BPC;
5962                 break;
5963         default:
5964                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5965                 BUG();
5966         }
5967
5968         if (intel_crtc->config.dither)
5969                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5970
5971         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5972                 val |= PIPECONF_INTERLACED_ILK;
5973         else
5974                 val |= PIPECONF_PROGRESSIVE;
5975
5976         if (intel_crtc->config.limited_color_range)
5977                 val |= PIPECONF_COLOR_RANGE_SELECT;
5978
5979         I915_WRITE(PIPECONF(pipe), val);
5980         POSTING_READ(PIPECONF(pipe));
5981 }
5982
5983 /*
5984  * Set up the pipe CSC unit.
5985  *
5986  * Currently only full range RGB to limited range RGB conversion
5987  * is supported, but eventually this should handle various
5988  * RGB<->YCbCr scenarios as well.
5989  */
5990 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5991 {
5992         struct drm_device *dev = crtc->dev;
5993         struct drm_i915_private *dev_priv = dev->dev_private;
5994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5995         int pipe = intel_crtc->pipe;
5996         uint16_t coeff = 0x7800; /* 1.0 */
5997
5998         /*
5999          * TODO: Check what kind of values actually come out of the pipe
6000          * with these coeff/postoff values and adjust to get the best
6001          * accuracy. Perhaps we even need to take the bpc value into
6002          * consideration.
6003          */
6004
6005         if (intel_crtc->config.limited_color_range)
6006                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6007
6008         /*
6009          * GY/GU and RY/RU should be the other way around according
6010          * to BSpec, but reality doesn't agree. Just set them up in
6011          * a way that results in the correct picture.
6012          */
6013         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6014         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6015
6016         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6017         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6018
6019         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6020         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6021
6022         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6023         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6024         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6025
6026         if (INTEL_INFO(dev)->gen > 6) {
6027                 uint16_t postoff = 0;
6028
6029                 if (intel_crtc->config.limited_color_range)
6030                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6031
6032                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6033                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6034                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6035
6036                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6037         } else {
6038                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6039
6040                 if (intel_crtc->config.limited_color_range)
6041                         mode |= CSC_BLACK_SCREEN_OFFSET;
6042
6043                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6044         }
6045 }
6046
6047 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6048 {
6049         struct drm_device *dev = crtc->dev;
6050         struct drm_i915_private *dev_priv = dev->dev_private;
6051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052         enum pipe pipe = intel_crtc->pipe;
6053         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6054         uint32_t val;
6055
6056         val = 0;
6057
6058         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6059                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6060
6061         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6062                 val |= PIPECONF_INTERLACED_ILK;
6063         else
6064                 val |= PIPECONF_PROGRESSIVE;
6065
6066         I915_WRITE(PIPECONF(cpu_transcoder), val);
6067         POSTING_READ(PIPECONF(cpu_transcoder));
6068
6069         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6070         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6071
6072         if (IS_BROADWELL(dev)) {
6073                 val = 0;
6074
6075                 switch (intel_crtc->config.pipe_bpp) {
6076                 case 18:
6077                         val |= PIPEMISC_DITHER_6_BPC;
6078                         break;
6079                 case 24:
6080                         val |= PIPEMISC_DITHER_8_BPC;
6081                         break;
6082                 case 30:
6083                         val |= PIPEMISC_DITHER_10_BPC;
6084                         break;
6085                 case 36:
6086                         val |= PIPEMISC_DITHER_12_BPC;
6087                         break;
6088                 default:
6089                         /* Case prevented by pipe_config_set_bpp. */
6090                         BUG();
6091                 }
6092
6093                 if (intel_crtc->config.dither)
6094                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6095
6096                 I915_WRITE(PIPEMISC(pipe), val);
6097         }
6098 }
6099
6100 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6101                                     intel_clock_t *clock,
6102                                     bool *has_reduced_clock,
6103                                     intel_clock_t *reduced_clock)
6104 {
6105         struct drm_device *dev = crtc->dev;
6106         struct drm_i915_private *dev_priv = dev->dev_private;
6107         struct intel_encoder *intel_encoder;
6108         int refclk;
6109         const intel_limit_t *limit;
6110         bool ret, is_lvds = false;
6111
6112         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6113                 switch (intel_encoder->type) {
6114                 case INTEL_OUTPUT_LVDS:
6115                         is_lvds = true;
6116                         break;
6117                 }
6118         }
6119
6120         refclk = ironlake_get_refclk(crtc);
6121
6122         /*
6123          * Returns a set of divisors for the desired target clock with the given
6124          * refclk, or FALSE.  The returned values represent the clock equation:
6125          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6126          */
6127         limit = intel_limit(crtc, refclk);
6128         ret = dev_priv->display.find_dpll(limit, crtc,
6129                                           to_intel_crtc(crtc)->config.port_clock,
6130                                           refclk, NULL, clock);
6131         if (!ret)
6132                 return false;
6133
6134         if (is_lvds && dev_priv->lvds_downclock_avail) {
6135                 /*
6136                  * Ensure we match the reduced clock's P to the target clock.
6137                  * If the clocks don't match, we can't switch the display clock
6138                  * by using the FP0/FP1. In such case we will disable the LVDS
6139                  * downclock feature.
6140                 */
6141                 *has_reduced_clock =
6142                         dev_priv->display.find_dpll(limit, crtc,
6143                                                     dev_priv->lvds_downclock,
6144                                                     refclk, clock,
6145                                                     reduced_clock);
6146         }
6147
6148         return true;
6149 }
6150
6151 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6152 {
6153         /*
6154          * Account for spread spectrum to avoid
6155          * oversubscribing the link. Max center spread
6156          * is 2.5%; use 5% for safety's sake.
6157          */
6158         u32 bps = target_clock * bpp * 21 / 20;
6159         return bps / (link_bw * 8) + 1;
6160 }
6161
6162 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6163 {
6164         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6165 }
6166
6167 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6168                                       u32 *fp,
6169                                       intel_clock_t *reduced_clock, u32 *fp2)
6170 {
6171         struct drm_crtc *crtc = &intel_crtc->base;
6172         struct drm_device *dev = crtc->dev;
6173         struct drm_i915_private *dev_priv = dev->dev_private;
6174         struct intel_encoder *intel_encoder;
6175         uint32_t dpll;
6176         int factor, num_connectors = 0;
6177         bool is_lvds = false, is_sdvo = false;
6178
6179         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6180                 switch (intel_encoder->type) {
6181                 case INTEL_OUTPUT_LVDS:
6182                         is_lvds = true;
6183                         break;
6184                 case INTEL_OUTPUT_SDVO:
6185                 case INTEL_OUTPUT_HDMI:
6186                         is_sdvo = true;
6187                         break;
6188                 }
6189
6190                 num_connectors++;
6191         }
6192
6193         /* Enable autotuning of the PLL clock (if permissible) */
6194         factor = 21;
6195         if (is_lvds) {
6196                 if ((intel_panel_use_ssc(dev_priv) &&
6197                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6198                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6199                         factor = 25;
6200         } else if (intel_crtc->config.sdvo_tv_clock)
6201                 factor = 20;
6202
6203         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6204                 *fp |= FP_CB_TUNE;
6205
6206         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6207                 *fp2 |= FP_CB_TUNE;
6208
6209         dpll = 0;
6210
6211         if (is_lvds)
6212                 dpll |= DPLLB_MODE_LVDS;
6213         else
6214                 dpll |= DPLLB_MODE_DAC_SERIAL;
6215
6216         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6217                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6218
6219         if (is_sdvo)
6220                 dpll |= DPLL_SDVO_HIGH_SPEED;
6221         if (intel_crtc->config.has_dp_encoder)
6222                 dpll |= DPLL_SDVO_HIGH_SPEED;
6223
6224         /* compute bitmask from p1 value */
6225         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6226         /* also FPA1 */
6227         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6228
6229         switch (intel_crtc->config.dpll.p2) {
6230         case 5:
6231                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6232                 break;
6233         case 7:
6234                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6235                 break;
6236         case 10:
6237                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6238                 break;
6239         case 14:
6240                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6241                 break;
6242         }
6243
6244         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6245                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6246         else
6247                 dpll |= PLL_REF_INPUT_DREFCLK;
6248
6249         return dpll | DPLL_VCO_ENABLE;
6250 }
6251
6252 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6253                                   int x, int y,
6254                                   struct drm_framebuffer *fb)
6255 {
6256         struct drm_device *dev = crtc->dev;
6257         struct drm_i915_private *dev_priv = dev->dev_private;
6258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6259         int pipe = intel_crtc->pipe;
6260         int plane = intel_crtc->plane;
6261         int num_connectors = 0;
6262         intel_clock_t clock, reduced_clock;
6263         u32 dpll = 0, fp = 0, fp2 = 0;
6264         bool ok, has_reduced_clock = false;
6265         bool is_lvds = false;
6266         struct intel_encoder *encoder;
6267         struct intel_shared_dpll *pll;
6268         int ret;
6269
6270         for_each_encoder_on_crtc(dev, crtc, encoder) {
6271                 switch (encoder->type) {
6272                 case INTEL_OUTPUT_LVDS:
6273                         is_lvds = true;
6274                         break;
6275                 }
6276
6277                 num_connectors++;
6278         }
6279
6280         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6281              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6282
6283         ok = ironlake_compute_clocks(crtc, &clock,
6284                                      &has_reduced_clock, &reduced_clock);
6285         if (!ok && !intel_crtc->config.clock_set) {
6286                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6287                 return -EINVAL;
6288         }
6289         /* Compat-code for transition, will disappear. */
6290         if (!intel_crtc->config.clock_set) {
6291                 intel_crtc->config.dpll.n = clock.n;
6292                 intel_crtc->config.dpll.m1 = clock.m1;
6293                 intel_crtc->config.dpll.m2 = clock.m2;
6294                 intel_crtc->config.dpll.p1 = clock.p1;
6295                 intel_crtc->config.dpll.p2 = clock.p2;
6296         }
6297
6298         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6299         if (intel_crtc->config.has_pch_encoder) {
6300                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6301                 if (has_reduced_clock)
6302                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6303
6304                 dpll = ironlake_compute_dpll(intel_crtc,
6305                                              &fp, &reduced_clock,
6306                                              has_reduced_clock ? &fp2 : NULL);
6307
6308                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6309                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6310                 if (has_reduced_clock)
6311                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6312                 else
6313                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6314
6315                 pll = intel_get_shared_dpll(intel_crtc);
6316                 if (pll == NULL) {
6317                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6318                                          pipe_name(pipe));
6319                         return -EINVAL;
6320                 }
6321         } else
6322                 intel_put_shared_dpll(intel_crtc);
6323
6324         if (intel_crtc->config.has_dp_encoder)
6325                 intel_dp_set_m_n(intel_crtc);
6326
6327         if (is_lvds && has_reduced_clock && i915_powersave)
6328                 intel_crtc->lowfreq_avail = true;
6329         else
6330                 intel_crtc->lowfreq_avail = false;
6331
6332         intel_set_pipe_timings(intel_crtc);
6333
6334         if (intel_crtc->config.has_pch_encoder) {
6335                 intel_cpu_transcoder_set_m_n(intel_crtc,
6336                                              &intel_crtc->config.fdi_m_n);
6337         }
6338
6339         ironlake_set_pipeconf(crtc);
6340
6341         /* Set up the display plane register */
6342         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6343         POSTING_READ(DSPCNTR(plane));
6344
6345         ret = intel_pipe_set_base(crtc, x, y, fb);
6346
6347         return ret;
6348 }
6349
6350 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6351                                          struct intel_link_m_n *m_n)
6352 {
6353         struct drm_device *dev = crtc->base.dev;
6354         struct drm_i915_private *dev_priv = dev->dev_private;
6355         enum pipe pipe = crtc->pipe;
6356
6357         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6358         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6359         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6360                 & ~TU_SIZE_MASK;
6361         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6362         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6363                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6364 }
6365
6366 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6367                                          enum transcoder transcoder,
6368                                          struct intel_link_m_n *m_n)
6369 {
6370         struct drm_device *dev = crtc->base.dev;
6371         struct drm_i915_private *dev_priv = dev->dev_private;
6372         enum pipe pipe = crtc->pipe;
6373
6374         if (INTEL_INFO(dev)->gen >= 5) {
6375                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6376                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6377                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6378                         & ~TU_SIZE_MASK;
6379                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6380                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6381                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6382         } else {
6383                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6384                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6385                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6386                         & ~TU_SIZE_MASK;
6387                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6388                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6389                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6390         }
6391 }
6392
6393 void intel_dp_get_m_n(struct intel_crtc *crtc,
6394                       struct intel_crtc_config *pipe_config)
6395 {
6396         if (crtc->config.has_pch_encoder)
6397                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6398         else
6399                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6400                                              &pipe_config->dp_m_n);
6401 }
6402
6403 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6404                                         struct intel_crtc_config *pipe_config)
6405 {
6406         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6407                                      &pipe_config->fdi_m_n);
6408 }
6409
6410 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6411                                      struct intel_crtc_config *pipe_config)
6412 {
6413         struct drm_device *dev = crtc->base.dev;
6414         struct drm_i915_private *dev_priv = dev->dev_private;
6415         uint32_t tmp;
6416
6417         tmp = I915_READ(PF_CTL(crtc->pipe));
6418
6419         if (tmp & PF_ENABLE) {
6420                 pipe_config->pch_pfit.enabled = true;
6421                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6422                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6423
6424                 /* We currently do not free assignements of panel fitters on
6425                  * ivb/hsw (since we don't use the higher upscaling modes which
6426                  * differentiates them) so just WARN about this case for now. */
6427                 if (IS_GEN7(dev)) {
6428                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6429                                 PF_PIPE_SEL_IVB(crtc->pipe));
6430                 }
6431         }
6432 }
6433
6434 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6435                                      struct intel_crtc_config *pipe_config)
6436 {
6437         struct drm_device *dev = crtc->base.dev;
6438         struct drm_i915_private *dev_priv = dev->dev_private;
6439         uint32_t tmp;
6440
6441         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6442         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6443
6444         tmp = I915_READ(PIPECONF(crtc->pipe));
6445         if (!(tmp & PIPECONF_ENABLE))
6446                 return false;
6447
6448         switch (tmp & PIPECONF_BPC_MASK) {
6449         case PIPECONF_6BPC:
6450                 pipe_config->pipe_bpp = 18;
6451                 break;
6452         case PIPECONF_8BPC:
6453                 pipe_config->pipe_bpp = 24;
6454                 break;
6455         case PIPECONF_10BPC:
6456                 pipe_config->pipe_bpp = 30;
6457                 break;
6458         case PIPECONF_12BPC:
6459                 pipe_config->pipe_bpp = 36;
6460                 break;
6461         default:
6462                 break;
6463         }
6464
6465         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6466                 struct intel_shared_dpll *pll;
6467
6468                 pipe_config->has_pch_encoder = true;
6469
6470                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6471                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6472                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6473
6474                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6475
6476                 if (HAS_PCH_IBX(dev_priv->dev)) {
6477                         pipe_config->shared_dpll =
6478                                 (enum intel_dpll_id) crtc->pipe;
6479                 } else {
6480                         tmp = I915_READ(PCH_DPLL_SEL);
6481                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6482                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6483                         else
6484                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6485                 }
6486
6487                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6488
6489                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6490                                            &pipe_config->dpll_hw_state));
6491
6492                 tmp = pipe_config->dpll_hw_state.dpll;
6493                 pipe_config->pixel_multiplier =
6494                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6495                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6496
6497                 ironlake_pch_clock_get(crtc, pipe_config);
6498         } else {
6499                 pipe_config->pixel_multiplier = 1;
6500         }
6501
6502         intel_get_pipe_timings(crtc, pipe_config);
6503
6504         ironlake_get_pfit_config(crtc, pipe_config);
6505
6506         return true;
6507 }
6508
6509 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6510 {
6511         struct drm_device *dev = dev_priv->dev;
6512         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6513         struct intel_crtc *crtc;
6514         unsigned long irqflags;
6515         uint32_t val;
6516
6517         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6518                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6519                      pipe_name(crtc->pipe));
6520
6521         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6522         WARN(plls->spll_refcount, "SPLL enabled\n");
6523         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6524         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6525         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6526         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6527              "CPU PWM1 enabled\n");
6528         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6529              "CPU PWM2 enabled\n");
6530         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6531              "PCH PWM1 enabled\n");
6532         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6533              "Utility pin enabled\n");
6534         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6535
6536         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6537         val = I915_READ(DEIMR);
6538         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6539              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6540         val = I915_READ(SDEIMR);
6541         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6542              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6543         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6544 }
6545
6546 /*
6547  * This function implements pieces of two sequences from BSpec:
6548  * - Sequence for display software to disable LCPLL
6549  * - Sequence for display software to allow package C8+
6550  * The steps implemented here are just the steps that actually touch the LCPLL
6551  * register. Callers should take care of disabling all the display engine
6552  * functions, doing the mode unset, fixing interrupts, etc.
6553  */
6554 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6555                               bool switch_to_fclk, bool allow_power_down)
6556 {
6557         uint32_t val;
6558
6559         assert_can_disable_lcpll(dev_priv);
6560
6561         val = I915_READ(LCPLL_CTL);
6562
6563         if (switch_to_fclk) {
6564                 val |= LCPLL_CD_SOURCE_FCLK;
6565                 I915_WRITE(LCPLL_CTL, val);
6566
6567                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6568                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6569                         DRM_ERROR("Switching to FCLK failed\n");
6570
6571                 val = I915_READ(LCPLL_CTL);
6572         }
6573
6574         val |= LCPLL_PLL_DISABLE;
6575         I915_WRITE(LCPLL_CTL, val);
6576         POSTING_READ(LCPLL_CTL);
6577
6578         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6579                 DRM_ERROR("LCPLL still locked\n");
6580
6581         val = I915_READ(D_COMP);
6582         val |= D_COMP_COMP_DISABLE;
6583         mutex_lock(&dev_priv->rps.hw_lock);
6584         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6585                 DRM_ERROR("Failed to disable D_COMP\n");
6586         mutex_unlock(&dev_priv->rps.hw_lock);
6587         POSTING_READ(D_COMP);
6588         ndelay(100);
6589
6590         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6591                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6592
6593         if (allow_power_down) {
6594                 val = I915_READ(LCPLL_CTL);
6595                 val |= LCPLL_POWER_DOWN_ALLOW;
6596                 I915_WRITE(LCPLL_CTL, val);
6597                 POSTING_READ(LCPLL_CTL);
6598         }
6599 }
6600
6601 /*
6602  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6603  * source.
6604  */
6605 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6606 {
6607         uint32_t val;
6608
6609         val = I915_READ(LCPLL_CTL);
6610
6611         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6612                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6613                 return;
6614
6615         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6616          * we'll hang the machine! */
6617         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6618
6619         if (val & LCPLL_POWER_DOWN_ALLOW) {
6620                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6621                 I915_WRITE(LCPLL_CTL, val);
6622                 POSTING_READ(LCPLL_CTL);
6623         }
6624
6625         val = I915_READ(D_COMP);
6626         val |= D_COMP_COMP_FORCE;
6627         val &= ~D_COMP_COMP_DISABLE;
6628         mutex_lock(&dev_priv->rps.hw_lock);
6629         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6630                 DRM_ERROR("Failed to enable D_COMP\n");
6631         mutex_unlock(&dev_priv->rps.hw_lock);
6632         POSTING_READ(D_COMP);
6633
6634         val = I915_READ(LCPLL_CTL);
6635         val &= ~LCPLL_PLL_DISABLE;
6636         I915_WRITE(LCPLL_CTL, val);
6637
6638         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6639                 DRM_ERROR("LCPLL not locked yet\n");
6640
6641         if (val & LCPLL_CD_SOURCE_FCLK) {
6642                 val = I915_READ(LCPLL_CTL);
6643                 val &= ~LCPLL_CD_SOURCE_FCLK;
6644                 I915_WRITE(LCPLL_CTL, val);
6645
6646                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6647                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6648                         DRM_ERROR("Switching back to LCPLL failed\n");
6649         }
6650
6651         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6652 }
6653
6654 void hsw_enable_pc8_work(struct work_struct *__work)
6655 {
6656         struct drm_i915_private *dev_priv =
6657                 container_of(to_delayed_work(__work), struct drm_i915_private,
6658                              pc8.enable_work);
6659         struct drm_device *dev = dev_priv->dev;
6660         uint32_t val;
6661
6662         WARN_ON(!HAS_PC8(dev));
6663
6664         if (dev_priv->pc8.enabled)
6665                 return;
6666
6667         DRM_DEBUG_KMS("Enabling package C8+\n");
6668
6669         dev_priv->pc8.enabled = true;
6670
6671         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6672                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6673                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6674                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6675         }
6676
6677         lpt_disable_clkout_dp(dev);
6678         hsw_pc8_disable_interrupts(dev);
6679         hsw_disable_lcpll(dev_priv, true, true);
6680
6681         intel_runtime_pm_put(dev_priv);
6682 }
6683
6684 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6685 {
6686         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6687         WARN(dev_priv->pc8.disable_count < 1,
6688              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6689
6690         dev_priv->pc8.disable_count--;
6691         if (dev_priv->pc8.disable_count != 0)
6692                 return;
6693
6694         schedule_delayed_work(&dev_priv->pc8.enable_work,
6695                               msecs_to_jiffies(i915_pc8_timeout));
6696 }
6697
6698 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6699 {
6700         struct drm_device *dev = dev_priv->dev;
6701         uint32_t val;
6702
6703         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6704         WARN(dev_priv->pc8.disable_count < 0,
6705              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6706
6707         dev_priv->pc8.disable_count++;
6708         if (dev_priv->pc8.disable_count != 1)
6709                 return;
6710
6711         WARN_ON(!HAS_PC8(dev));
6712
6713         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6714         if (!dev_priv->pc8.enabled)
6715                 return;
6716
6717         DRM_DEBUG_KMS("Disabling package C8+\n");
6718
6719         intel_runtime_pm_get(dev_priv);
6720
6721         hsw_restore_lcpll(dev_priv);
6722         hsw_pc8_restore_interrupts(dev);
6723         lpt_init_pch_refclk(dev);
6724
6725         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6726                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6727                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6728                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6729         }
6730
6731         intel_prepare_ddi(dev);
6732         i915_gem_init_swizzling(dev);
6733         mutex_lock(&dev_priv->rps.hw_lock);
6734         gen6_update_ring_freq(dev);
6735         mutex_unlock(&dev_priv->rps.hw_lock);
6736         dev_priv->pc8.enabled = false;
6737 }
6738
6739 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6740 {
6741         if (!HAS_PC8(dev_priv->dev))
6742                 return;
6743
6744         mutex_lock(&dev_priv->pc8.lock);
6745         __hsw_enable_package_c8(dev_priv);
6746         mutex_unlock(&dev_priv->pc8.lock);
6747 }
6748
6749 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6750 {
6751         if (!HAS_PC8(dev_priv->dev))
6752                 return;
6753
6754         mutex_lock(&dev_priv->pc8.lock);
6755         __hsw_disable_package_c8(dev_priv);
6756         mutex_unlock(&dev_priv->pc8.lock);
6757 }
6758
6759 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6760 {
6761         struct drm_device *dev = dev_priv->dev;
6762         struct intel_crtc *crtc;
6763         uint32_t val;
6764
6765         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6766                 if (crtc->base.enabled)
6767                         return false;
6768
6769         /* This case is still possible since we have the i915.disable_power_well
6770          * parameter and also the KVMr or something else might be requesting the
6771          * power well. */
6772         val = I915_READ(HSW_PWR_WELL_DRIVER);
6773         if (val != 0) {
6774                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6775                 return false;
6776         }
6777
6778         return true;
6779 }
6780
6781 /* Since we're called from modeset_global_resources there's no way to
6782  * symmetrically increase and decrease the refcount, so we use
6783  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6784  * or not.
6785  */
6786 static void hsw_update_package_c8(struct drm_device *dev)
6787 {
6788         struct drm_i915_private *dev_priv = dev->dev_private;
6789         bool allow;
6790
6791         if (!HAS_PC8(dev_priv->dev))
6792                 return;
6793
6794         if (!i915_enable_pc8)
6795                 return;
6796
6797         mutex_lock(&dev_priv->pc8.lock);
6798
6799         allow = hsw_can_enable_package_c8(dev_priv);
6800
6801         if (allow == dev_priv->pc8.requirements_met)
6802                 goto done;
6803
6804         dev_priv->pc8.requirements_met = allow;
6805
6806         if (allow)
6807                 __hsw_enable_package_c8(dev_priv);
6808         else
6809                 __hsw_disable_package_c8(dev_priv);
6810
6811 done:
6812         mutex_unlock(&dev_priv->pc8.lock);
6813 }
6814
6815 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6816 {
6817         if (!HAS_PC8(dev_priv->dev))
6818                 return;
6819
6820         mutex_lock(&dev_priv->pc8.lock);
6821         if (!dev_priv->pc8.gpu_idle) {
6822                 dev_priv->pc8.gpu_idle = true;
6823                 __hsw_enable_package_c8(dev_priv);
6824         }
6825         mutex_unlock(&dev_priv->pc8.lock);
6826 }
6827
6828 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6829 {
6830         if (!HAS_PC8(dev_priv->dev))
6831                 return;
6832
6833         mutex_lock(&dev_priv->pc8.lock);
6834         if (dev_priv->pc8.gpu_idle) {
6835                 dev_priv->pc8.gpu_idle = false;
6836                 __hsw_disable_package_c8(dev_priv);
6837         }
6838         mutex_unlock(&dev_priv->pc8.lock);
6839 }
6840
6841 #define for_each_power_domain(domain, mask)                             \
6842         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6843                 if ((1 << (domain)) & (mask))
6844
6845 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6846                                             enum pipe pipe, bool pfit_enabled)
6847 {
6848         unsigned long mask;
6849         enum transcoder transcoder;
6850
6851         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6852
6853         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6854         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6855         if (pfit_enabled)
6856                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6857
6858         return mask;
6859 }
6860
6861 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6862 {
6863         struct drm_i915_private *dev_priv = dev->dev_private;
6864
6865         if (dev_priv->power_domains.init_power_on == enable)
6866                 return;
6867
6868         if (enable)
6869                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6870         else
6871                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6872
6873         dev_priv->power_domains.init_power_on = enable;
6874 }
6875
6876 static void modeset_update_power_wells(struct drm_device *dev)
6877 {
6878         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6879         struct intel_crtc *crtc;
6880
6881         /*
6882          * First get all needed power domains, then put all unneeded, to avoid
6883          * any unnecessary toggling of the power wells.
6884          */
6885         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6886                 enum intel_display_power_domain domain;
6887
6888                 if (!crtc->base.enabled)
6889                         continue;
6890
6891                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6892                                                 crtc->pipe,
6893                                                 crtc->config.pch_pfit.enabled);
6894
6895                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6896                         intel_display_power_get(dev, domain);
6897         }
6898
6899         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6900                 enum intel_display_power_domain domain;
6901
6902                 for_each_power_domain(domain, crtc->enabled_power_domains)
6903                         intel_display_power_put(dev, domain);
6904
6905                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6906         }
6907
6908         intel_display_set_init_power(dev, false);
6909 }
6910
6911 static void haswell_modeset_global_resources(struct drm_device *dev)
6912 {
6913         modeset_update_power_wells(dev);
6914         hsw_update_package_c8(dev);
6915 }
6916
6917 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6918                                  int x, int y,
6919                                  struct drm_framebuffer *fb)
6920 {
6921         struct drm_device *dev = crtc->dev;
6922         struct drm_i915_private *dev_priv = dev->dev_private;
6923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924         int plane = intel_crtc->plane;
6925         int ret;
6926
6927         if (!intel_ddi_pll_select(intel_crtc))
6928                 return -EINVAL;
6929         intel_ddi_pll_enable(intel_crtc);
6930
6931         if (intel_crtc->config.has_dp_encoder)
6932                 intel_dp_set_m_n(intel_crtc);
6933
6934         intel_crtc->lowfreq_avail = false;
6935
6936         intel_set_pipe_timings(intel_crtc);
6937
6938         if (intel_crtc->config.has_pch_encoder) {
6939                 intel_cpu_transcoder_set_m_n(intel_crtc,
6940                                              &intel_crtc->config.fdi_m_n);
6941         }
6942
6943         haswell_set_pipeconf(crtc);
6944
6945         intel_set_pipe_csc(crtc);
6946
6947         /* Set up the display plane register */
6948         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6949         POSTING_READ(DSPCNTR(plane));
6950
6951         ret = intel_pipe_set_base(crtc, x, y, fb);
6952
6953         return ret;
6954 }
6955
6956 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6957                                     struct intel_crtc_config *pipe_config)
6958 {
6959         struct drm_device *dev = crtc->base.dev;
6960         struct drm_i915_private *dev_priv = dev->dev_private;
6961         enum intel_display_power_domain pfit_domain;
6962         uint32_t tmp;
6963
6964         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6965         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6966
6967         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6968         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6969                 enum pipe trans_edp_pipe;
6970                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6971                 default:
6972                         WARN(1, "unknown pipe linked to edp transcoder\n");
6973                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6974                 case TRANS_DDI_EDP_INPUT_A_ON:
6975                         trans_edp_pipe = PIPE_A;
6976                         break;
6977                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6978                         trans_edp_pipe = PIPE_B;
6979                         break;
6980                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6981                         trans_edp_pipe = PIPE_C;
6982                         break;
6983                 }
6984
6985                 if (trans_edp_pipe == crtc->pipe)
6986                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6987         }
6988
6989         if (!intel_display_power_enabled(dev,
6990                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6991                 return false;
6992
6993         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6994         if (!(tmp & PIPECONF_ENABLE))
6995                 return false;
6996
6997         /*
6998          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6999          * DDI E. So just check whether this pipe is wired to DDI E and whether
7000          * the PCH transcoder is on.
7001          */
7002         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7003         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7004             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7005                 pipe_config->has_pch_encoder = true;
7006
7007                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7008                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7009                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7010
7011                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7012         }
7013
7014         intel_get_pipe_timings(crtc, pipe_config);
7015
7016         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7017         if (intel_display_power_enabled(dev, pfit_domain))
7018                 ironlake_get_pfit_config(crtc, pipe_config);
7019
7020         if (IS_HASWELL(dev))
7021                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7022                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7023
7024         pipe_config->pixel_multiplier = 1;
7025
7026         return true;
7027 }
7028
7029 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7030                                int x, int y,
7031                                struct drm_framebuffer *fb)
7032 {
7033         struct drm_device *dev = crtc->dev;
7034         struct drm_i915_private *dev_priv = dev->dev_private;
7035         struct intel_encoder *encoder;
7036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7038         int pipe = intel_crtc->pipe;
7039         int ret;
7040
7041         drm_vblank_pre_modeset(dev, pipe);
7042
7043         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7044
7045         drm_vblank_post_modeset(dev, pipe);
7046
7047         if (ret != 0)
7048                 return ret;
7049
7050         for_each_encoder_on_crtc(dev, crtc, encoder) {
7051                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7052                         encoder->base.base.id,
7053                         drm_get_encoder_name(&encoder->base),
7054                         mode->base.id, mode->name);
7055                 encoder->mode_set(encoder);
7056         }
7057
7058         return 0;
7059 }
7060
7061 static struct {
7062         int clock;
7063         u32 config;
7064 } hdmi_audio_clock[] = {
7065         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7066         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7067         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7068         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7069         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7070         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7071         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7072         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7073         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7074         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7075 };
7076
7077 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7078 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7079 {
7080         int i;
7081
7082         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7083                 if (mode->clock == hdmi_audio_clock[i].clock)
7084                         break;
7085         }
7086
7087         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7088                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7089                 i = 1;
7090         }
7091
7092         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7093                       hdmi_audio_clock[i].clock,
7094                       hdmi_audio_clock[i].config);
7095
7096         return hdmi_audio_clock[i].config;
7097 }
7098
7099 static bool intel_eld_uptodate(struct drm_connector *connector,
7100                                int reg_eldv, uint32_t bits_eldv,
7101                                int reg_elda, uint32_t bits_elda,
7102                                int reg_edid)
7103 {
7104         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7105         uint8_t *eld = connector->eld;
7106         uint32_t i;
7107
7108         i = I915_READ(reg_eldv);
7109         i &= bits_eldv;
7110
7111         if (!eld[0])
7112                 return !i;
7113
7114         if (!i)
7115                 return false;
7116
7117         i = I915_READ(reg_elda);
7118         i &= ~bits_elda;
7119         I915_WRITE(reg_elda, i);
7120
7121         for (i = 0; i < eld[2]; i++)
7122                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7123                         return false;
7124
7125         return true;
7126 }
7127
7128 static void g4x_write_eld(struct drm_connector *connector,
7129                           struct drm_crtc *crtc,
7130                           struct drm_display_mode *mode)
7131 {
7132         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7133         uint8_t *eld = connector->eld;
7134         uint32_t eldv;
7135         uint32_t len;
7136         uint32_t i;
7137
7138         i = I915_READ(G4X_AUD_VID_DID);
7139
7140         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7141                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7142         else
7143                 eldv = G4X_ELDV_DEVCTG;
7144
7145         if (intel_eld_uptodate(connector,
7146                                G4X_AUD_CNTL_ST, eldv,
7147                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7148                                G4X_HDMIW_HDMIEDID))
7149                 return;
7150
7151         i = I915_READ(G4X_AUD_CNTL_ST);
7152         i &= ~(eldv | G4X_ELD_ADDR);
7153         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7154         I915_WRITE(G4X_AUD_CNTL_ST, i);
7155
7156         if (!eld[0])
7157                 return;
7158
7159         len = min_t(uint8_t, eld[2], len);
7160         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7161         for (i = 0; i < len; i++)
7162                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7163
7164         i = I915_READ(G4X_AUD_CNTL_ST);
7165         i |= eldv;
7166         I915_WRITE(G4X_AUD_CNTL_ST, i);
7167 }
7168
7169 static void haswell_write_eld(struct drm_connector *connector,
7170                               struct drm_crtc *crtc,
7171                               struct drm_display_mode *mode)
7172 {
7173         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7174         uint8_t *eld = connector->eld;
7175         struct drm_device *dev = crtc->dev;
7176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177         uint32_t eldv;
7178         uint32_t i;
7179         int len;
7180         int pipe = to_intel_crtc(crtc)->pipe;
7181         int tmp;
7182
7183         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7184         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7185         int aud_config = HSW_AUD_CFG(pipe);
7186         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7187
7188
7189         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7190
7191         /* Audio output enable */
7192         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7193         tmp = I915_READ(aud_cntrl_st2);
7194         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7195         I915_WRITE(aud_cntrl_st2, tmp);
7196
7197         /* Wait for 1 vertical blank */
7198         intel_wait_for_vblank(dev, pipe);
7199
7200         /* Set ELD valid state */
7201         tmp = I915_READ(aud_cntrl_st2);
7202         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7203         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7204         I915_WRITE(aud_cntrl_st2, tmp);
7205         tmp = I915_READ(aud_cntrl_st2);
7206         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7207
7208         /* Enable HDMI mode */
7209         tmp = I915_READ(aud_config);
7210         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7211         /* clear N_programing_enable and N_value_index */
7212         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7213         I915_WRITE(aud_config, tmp);
7214
7215         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7216
7217         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7218         intel_crtc->eld_vld = true;
7219
7220         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7221                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7222                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7223                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7224         } else {
7225                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7226         }
7227
7228         if (intel_eld_uptodate(connector,
7229                                aud_cntrl_st2, eldv,
7230                                aud_cntl_st, IBX_ELD_ADDRESS,
7231                                hdmiw_hdmiedid))
7232                 return;
7233
7234         i = I915_READ(aud_cntrl_st2);
7235         i &= ~eldv;
7236         I915_WRITE(aud_cntrl_st2, i);
7237
7238         if (!eld[0])
7239                 return;
7240
7241         i = I915_READ(aud_cntl_st);
7242         i &= ~IBX_ELD_ADDRESS;
7243         I915_WRITE(aud_cntl_st, i);
7244         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7245         DRM_DEBUG_DRIVER("port num:%d\n", i);
7246
7247         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7248         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7249         for (i = 0; i < len; i++)
7250                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7251
7252         i = I915_READ(aud_cntrl_st2);
7253         i |= eldv;
7254         I915_WRITE(aud_cntrl_st2, i);
7255
7256 }
7257
7258 static void ironlake_write_eld(struct drm_connector *connector,
7259                                struct drm_crtc *crtc,
7260                                struct drm_display_mode *mode)
7261 {
7262         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7263         uint8_t *eld = connector->eld;
7264         uint32_t eldv;
7265         uint32_t i;
7266         int len;
7267         int hdmiw_hdmiedid;
7268         int aud_config;
7269         int aud_cntl_st;
7270         int aud_cntrl_st2;
7271         int pipe = to_intel_crtc(crtc)->pipe;
7272
7273         if (HAS_PCH_IBX(connector->dev)) {
7274                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7275                 aud_config = IBX_AUD_CFG(pipe);
7276                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7277                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7278         } else if (IS_VALLEYVIEW(connector->dev)) {
7279                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7280                 aud_config = VLV_AUD_CFG(pipe);
7281                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7282                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7283         } else {
7284                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7285                 aud_config = CPT_AUD_CFG(pipe);
7286                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7287                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7288         }
7289
7290         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7291
7292         if (IS_VALLEYVIEW(connector->dev))  {
7293                 struct intel_encoder *intel_encoder;
7294                 struct intel_digital_port *intel_dig_port;
7295
7296                 intel_encoder = intel_attached_encoder(connector);
7297                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7298                 i = intel_dig_port->port;
7299         } else {
7300                 i = I915_READ(aud_cntl_st);
7301                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7302                 /* DIP_Port_Select, 0x1 = PortB */
7303         }
7304
7305         if (!i) {
7306                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7307                 /* operate blindly on all ports */
7308                 eldv = IBX_ELD_VALIDB;
7309                 eldv |= IBX_ELD_VALIDB << 4;
7310                 eldv |= IBX_ELD_VALIDB << 8;
7311         } else {
7312                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7313                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7314         }
7315
7316         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7317                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7318                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7319                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7320         } else {
7321                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7322         }
7323
7324         if (intel_eld_uptodate(connector,
7325                                aud_cntrl_st2, eldv,
7326                                aud_cntl_st, IBX_ELD_ADDRESS,
7327                                hdmiw_hdmiedid))
7328                 return;
7329
7330         i = I915_READ(aud_cntrl_st2);
7331         i &= ~eldv;
7332         I915_WRITE(aud_cntrl_st2, i);
7333
7334         if (!eld[0])
7335                 return;
7336
7337         i = I915_READ(aud_cntl_st);
7338         i &= ~IBX_ELD_ADDRESS;
7339         I915_WRITE(aud_cntl_st, i);
7340
7341         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7342         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7343         for (i = 0; i < len; i++)
7344                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7345
7346         i = I915_READ(aud_cntrl_st2);
7347         i |= eldv;
7348         I915_WRITE(aud_cntrl_st2, i);
7349 }
7350
7351 void intel_write_eld(struct drm_encoder *encoder,
7352                      struct drm_display_mode *mode)
7353 {
7354         struct drm_crtc *crtc = encoder->crtc;
7355         struct drm_connector *connector;
7356         struct drm_device *dev = encoder->dev;
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358
7359         connector = drm_select_eld(encoder, mode);
7360         if (!connector)
7361                 return;
7362
7363         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7364                          connector->base.id,
7365                          drm_get_connector_name(connector),
7366                          connector->encoder->base.id,
7367                          drm_get_encoder_name(connector->encoder));
7368
7369         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7370
7371         if (dev_priv->display.write_eld)
7372                 dev_priv->display.write_eld(connector, crtc, mode);
7373 }
7374
7375 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7376 {
7377         struct drm_device *dev = crtc->dev;
7378         struct drm_i915_private *dev_priv = dev->dev_private;
7379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7380         bool visible = base != 0;
7381         u32 cntl;
7382
7383         if (intel_crtc->cursor_visible == visible)
7384                 return;
7385
7386         cntl = I915_READ(_CURACNTR);
7387         if (visible) {
7388                 /* On these chipsets we can only modify the base whilst
7389                  * the cursor is disabled.
7390                  */
7391                 I915_WRITE(_CURABASE, base);
7392
7393                 cntl &= ~(CURSOR_FORMAT_MASK);
7394                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7395                 cntl |= CURSOR_ENABLE |
7396                         CURSOR_GAMMA_ENABLE |
7397                         CURSOR_FORMAT_ARGB;
7398         } else
7399                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7400         I915_WRITE(_CURACNTR, cntl);
7401
7402         intel_crtc->cursor_visible = visible;
7403 }
7404
7405 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7406 {
7407         struct drm_device *dev = crtc->dev;
7408         struct drm_i915_private *dev_priv = dev->dev_private;
7409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7410         int pipe = intel_crtc->pipe;
7411         bool visible = base != 0;
7412
7413         if (intel_crtc->cursor_visible != visible) {
7414                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7415                 if (base) {
7416                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7417                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7418                         cntl |= pipe << 28; /* Connect to correct pipe */
7419                 } else {
7420                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7421                         cntl |= CURSOR_MODE_DISABLE;
7422                 }
7423                 I915_WRITE(CURCNTR(pipe), cntl);
7424
7425                 intel_crtc->cursor_visible = visible;
7426         }
7427         /* and commit changes on next vblank */
7428         POSTING_READ(CURCNTR(pipe));
7429         I915_WRITE(CURBASE(pipe), base);
7430         POSTING_READ(CURBASE(pipe));
7431 }
7432
7433 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7434 {
7435         struct drm_device *dev = crtc->dev;
7436         struct drm_i915_private *dev_priv = dev->dev_private;
7437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7438         int pipe = intel_crtc->pipe;
7439         bool visible = base != 0;
7440
7441         if (intel_crtc->cursor_visible != visible) {
7442                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7443                 if (base) {
7444                         cntl &= ~CURSOR_MODE;
7445                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7446                 } else {
7447                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7448                         cntl |= CURSOR_MODE_DISABLE;
7449                 }
7450                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7451                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7452                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7453                 }
7454                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7455
7456                 intel_crtc->cursor_visible = visible;
7457         }
7458         /* and commit changes on next vblank */
7459         POSTING_READ(CURCNTR_IVB(pipe));
7460         I915_WRITE(CURBASE_IVB(pipe), base);
7461         POSTING_READ(CURBASE_IVB(pipe));
7462 }
7463
7464 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7465 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7466                                      bool on)
7467 {
7468         struct drm_device *dev = crtc->dev;
7469         struct drm_i915_private *dev_priv = dev->dev_private;
7470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7471         int pipe = intel_crtc->pipe;
7472         int x = intel_crtc->cursor_x;
7473         int y = intel_crtc->cursor_y;
7474         u32 base = 0, pos = 0;
7475         bool visible;
7476
7477         if (on)
7478                 base = intel_crtc->cursor_addr;
7479
7480         if (x >= intel_crtc->config.pipe_src_w)
7481                 base = 0;
7482
7483         if (y >= intel_crtc->config.pipe_src_h)
7484                 base = 0;
7485
7486         if (x < 0) {
7487                 if (x + intel_crtc->cursor_width <= 0)
7488                         base = 0;
7489
7490                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7491                 x = -x;
7492         }
7493         pos |= x << CURSOR_X_SHIFT;
7494
7495         if (y < 0) {
7496                 if (y + intel_crtc->cursor_height <= 0)
7497                         base = 0;
7498
7499                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7500                 y = -y;
7501         }
7502         pos |= y << CURSOR_Y_SHIFT;
7503
7504         visible = base != 0;
7505         if (!visible && !intel_crtc->cursor_visible)
7506                 return;
7507
7508         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7509                 I915_WRITE(CURPOS_IVB(pipe), pos);
7510                 ivb_update_cursor(crtc, base);
7511         } else {
7512                 I915_WRITE(CURPOS(pipe), pos);
7513                 if (IS_845G(dev) || IS_I865G(dev))
7514                         i845_update_cursor(crtc, base);
7515                 else
7516                         i9xx_update_cursor(crtc, base);
7517         }
7518 }
7519
7520 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7521                                  struct drm_file *file,
7522                                  uint32_t handle,
7523                                  uint32_t width, uint32_t height)
7524 {
7525         struct drm_device *dev = crtc->dev;
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7528         struct drm_i915_gem_object *obj;
7529         uint32_t addr;
7530         int ret;
7531
7532         /* if we want to turn off the cursor ignore width and height */
7533         if (!handle) {
7534                 DRM_DEBUG_KMS("cursor off\n");
7535                 addr = 0;
7536                 obj = NULL;
7537                 mutex_lock(&dev->struct_mutex);
7538                 goto finish;
7539         }
7540
7541         /* Currently we only support 64x64 cursors */
7542         if (width != 64 || height != 64) {
7543                 DRM_ERROR("we currently only support 64x64 cursors\n");
7544                 return -EINVAL;
7545         }
7546
7547         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7548         if (&obj->base == NULL)
7549                 return -ENOENT;
7550
7551         if (obj->base.size < width * height * 4) {
7552                 DRM_ERROR("buffer is to small\n");
7553                 ret = -ENOMEM;
7554                 goto fail;
7555         }
7556
7557         /* we only need to pin inside GTT if cursor is non-phy */
7558         mutex_lock(&dev->struct_mutex);
7559         if (!dev_priv->info->cursor_needs_physical) {
7560                 unsigned alignment;
7561
7562                 if (obj->tiling_mode) {
7563                         DRM_ERROR("cursor cannot be tiled\n");
7564                         ret = -EINVAL;
7565                         goto fail_locked;
7566                 }
7567
7568                 /* Note that the w/a also requires 2 PTE of padding following
7569                  * the bo. We currently fill all unused PTE with the shadow
7570                  * page and so we should always have valid PTE following the
7571                  * cursor preventing the VT-d warning.
7572                  */
7573                 alignment = 0;
7574                 if (need_vtd_wa(dev))
7575                         alignment = 64*1024;
7576
7577                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7578                 if (ret) {
7579                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7580                         goto fail_locked;
7581                 }
7582
7583                 ret = i915_gem_object_put_fence(obj);
7584                 if (ret) {
7585                         DRM_ERROR("failed to release fence for cursor");
7586                         goto fail_unpin;
7587                 }
7588
7589                 addr = i915_gem_obj_ggtt_offset(obj);
7590         } else {
7591                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7592                 ret = i915_gem_attach_phys_object(dev, obj,
7593                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7594                                                   align);
7595                 if (ret) {
7596                         DRM_ERROR("failed to attach phys object\n");
7597                         goto fail_locked;
7598                 }
7599                 addr = obj->phys_obj->handle->busaddr;
7600         }
7601
7602         if (IS_GEN2(dev))
7603                 I915_WRITE(CURSIZE, (height << 12) | width);
7604
7605  finish:
7606         if (intel_crtc->cursor_bo) {
7607                 if (dev_priv->info->cursor_needs_physical) {
7608                         if (intel_crtc->cursor_bo != obj)
7609                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7610                 } else
7611                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7612                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7613         }
7614
7615         mutex_unlock(&dev->struct_mutex);
7616
7617         intel_crtc->cursor_addr = addr;
7618         intel_crtc->cursor_bo = obj;
7619         intel_crtc->cursor_width = width;
7620         intel_crtc->cursor_height = height;
7621
7622         if (intel_crtc->active)
7623                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7624
7625         return 0;
7626 fail_unpin:
7627         i915_gem_object_unpin_from_display_plane(obj);
7628 fail_locked:
7629         mutex_unlock(&dev->struct_mutex);
7630 fail:
7631         drm_gem_object_unreference_unlocked(&obj->base);
7632         return ret;
7633 }
7634
7635 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7636 {
7637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7638
7639         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7640         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7641
7642         if (intel_crtc->active)
7643                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7644
7645         return 0;
7646 }
7647
7648 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7649                                  u16 *blue, uint32_t start, uint32_t size)
7650 {
7651         int end = (start + size > 256) ? 256 : start + size, i;
7652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7653
7654         for (i = start; i < end; i++) {
7655                 intel_crtc->lut_r[i] = red[i] >> 8;
7656                 intel_crtc->lut_g[i] = green[i] >> 8;
7657                 intel_crtc->lut_b[i] = blue[i] >> 8;
7658         }
7659
7660         intel_crtc_load_lut(crtc);
7661 }
7662
7663 /* VESA 640x480x72Hz mode to set on the pipe */
7664 static struct drm_display_mode load_detect_mode = {
7665         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7666                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7667 };
7668
7669 static struct drm_framebuffer *
7670 intel_framebuffer_create(struct drm_device *dev,
7671                          struct drm_mode_fb_cmd2 *mode_cmd,
7672                          struct drm_i915_gem_object *obj)
7673 {
7674         struct intel_framebuffer *intel_fb;
7675         int ret;
7676
7677         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7678         if (!intel_fb) {
7679                 drm_gem_object_unreference_unlocked(&obj->base);
7680                 return ERR_PTR(-ENOMEM);
7681         }
7682
7683         ret = i915_mutex_lock_interruptible(dev);
7684         if (ret)
7685                 goto err;
7686
7687         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7688         mutex_unlock(&dev->struct_mutex);
7689         if (ret)
7690                 goto err;
7691
7692         return &intel_fb->base;
7693 err:
7694         drm_gem_object_unreference_unlocked(&obj->base);
7695         kfree(intel_fb);
7696
7697         return ERR_PTR(ret);
7698 }
7699
7700 static u32
7701 intel_framebuffer_pitch_for_width(int width, int bpp)
7702 {
7703         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7704         return ALIGN(pitch, 64);
7705 }
7706
7707 static u32
7708 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7709 {
7710         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7711         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7712 }
7713
7714 static struct drm_framebuffer *
7715 intel_framebuffer_create_for_mode(struct drm_device *dev,
7716                                   struct drm_display_mode *mode,
7717                                   int depth, int bpp)
7718 {
7719         struct drm_i915_gem_object *obj;
7720         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7721
7722         obj = i915_gem_alloc_object(dev,
7723                                     intel_framebuffer_size_for_mode(mode, bpp));
7724         if (obj == NULL)
7725                 return ERR_PTR(-ENOMEM);
7726
7727         mode_cmd.width = mode->hdisplay;
7728         mode_cmd.height = mode->vdisplay;
7729         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7730                                                                 bpp);
7731         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7732
7733         return intel_framebuffer_create(dev, &mode_cmd, obj);
7734 }
7735
7736 static struct drm_framebuffer *
7737 mode_fits_in_fbdev(struct drm_device *dev,
7738                    struct drm_display_mode *mode)
7739 {
7740 #ifdef CONFIG_DRM_I915_FBDEV
7741         struct drm_i915_private *dev_priv = dev->dev_private;
7742         struct drm_i915_gem_object *obj;
7743         struct drm_framebuffer *fb;
7744
7745         if (dev_priv->fbdev == NULL)
7746                 return NULL;
7747
7748         obj = dev_priv->fbdev->ifb.obj;
7749         if (obj == NULL)
7750                 return NULL;
7751
7752         fb = &dev_priv->fbdev->ifb.base;
7753         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7754                                                                fb->bits_per_pixel))
7755                 return NULL;
7756
7757         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7758                 return NULL;
7759
7760         return fb;
7761 #else
7762         return NULL;
7763 #endif
7764 }
7765
7766 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7767                                 struct drm_display_mode *mode,
7768                                 struct intel_load_detect_pipe *old)
7769 {
7770         struct intel_crtc *intel_crtc;
7771         struct intel_encoder *intel_encoder =
7772                 intel_attached_encoder(connector);
7773         struct drm_crtc *possible_crtc;
7774         struct drm_encoder *encoder = &intel_encoder->base;
7775         struct drm_crtc *crtc = NULL;
7776         struct drm_device *dev = encoder->dev;
7777         struct drm_framebuffer *fb;
7778         int i = -1;
7779
7780         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7781                       connector->base.id, drm_get_connector_name(connector),
7782                       encoder->base.id, drm_get_encoder_name(encoder));
7783
7784         /*
7785          * Algorithm gets a little messy:
7786          *
7787          *   - if the connector already has an assigned crtc, use it (but make
7788          *     sure it's on first)
7789          *
7790          *   - try to find the first unused crtc that can drive this connector,
7791          *     and use that if we find one
7792          */
7793
7794         /* See if we already have a CRTC for this connector */
7795         if (encoder->crtc) {
7796                 crtc = encoder->crtc;
7797
7798                 mutex_lock(&crtc->mutex);
7799
7800                 old->dpms_mode = connector->dpms;
7801                 old->load_detect_temp = false;
7802
7803                 /* Make sure the crtc and connector are running */
7804                 if (connector->dpms != DRM_MODE_DPMS_ON)
7805                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7806
7807                 return true;
7808         }
7809
7810         /* Find an unused one (if possible) */
7811         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7812                 i++;
7813                 if (!(encoder->possible_crtcs & (1 << i)))
7814                         continue;
7815                 if (!possible_crtc->enabled) {
7816                         crtc = possible_crtc;
7817                         break;
7818                 }
7819         }
7820
7821         /*
7822          * If we didn't find an unused CRTC, don't use any.
7823          */
7824         if (!crtc) {
7825                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7826                 return false;
7827         }
7828
7829         mutex_lock(&crtc->mutex);
7830         intel_encoder->new_crtc = to_intel_crtc(crtc);
7831         to_intel_connector(connector)->new_encoder = intel_encoder;
7832
7833         intel_crtc = to_intel_crtc(crtc);
7834         old->dpms_mode = connector->dpms;
7835         old->load_detect_temp = true;
7836         old->release_fb = NULL;
7837
7838         if (!mode)
7839                 mode = &load_detect_mode;
7840
7841         /* We need a framebuffer large enough to accommodate all accesses
7842          * that the plane may generate whilst we perform load detection.
7843          * We can not rely on the fbcon either being present (we get called
7844          * during its initialisation to detect all boot displays, or it may
7845          * not even exist) or that it is large enough to satisfy the
7846          * requested mode.
7847          */
7848         fb = mode_fits_in_fbdev(dev, mode);
7849         if (fb == NULL) {
7850                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7851                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7852                 old->release_fb = fb;
7853         } else
7854                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7855         if (IS_ERR(fb)) {
7856                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7857                 mutex_unlock(&crtc->mutex);
7858                 return false;
7859         }
7860
7861         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7862                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7863                 if (old->release_fb)
7864                         old->release_fb->funcs->destroy(old->release_fb);
7865                 mutex_unlock(&crtc->mutex);
7866                 return false;
7867         }
7868
7869         /* let the connector get through one full cycle before testing */
7870         intel_wait_for_vblank(dev, intel_crtc->pipe);
7871         return true;
7872 }
7873
7874 void intel_release_load_detect_pipe(struct drm_connector *connector,
7875                                     struct intel_load_detect_pipe *old)
7876 {
7877         struct intel_encoder *intel_encoder =
7878                 intel_attached_encoder(connector);
7879         struct drm_encoder *encoder = &intel_encoder->base;
7880         struct drm_crtc *crtc = encoder->crtc;
7881
7882         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7883                       connector->base.id, drm_get_connector_name(connector),
7884                       encoder->base.id, drm_get_encoder_name(encoder));
7885
7886         if (old->load_detect_temp) {
7887                 to_intel_connector(connector)->new_encoder = NULL;
7888                 intel_encoder->new_crtc = NULL;
7889                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7890
7891                 if (old->release_fb) {
7892                         drm_framebuffer_unregister_private(old->release_fb);
7893                         drm_framebuffer_unreference(old->release_fb);
7894                 }
7895
7896                 mutex_unlock(&crtc->mutex);
7897                 return;
7898         }
7899
7900         /* Switch crtc and encoder back off if necessary */
7901         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7902                 connector->funcs->dpms(connector, old->dpms_mode);
7903
7904         mutex_unlock(&crtc->mutex);
7905 }
7906
7907 static int i9xx_pll_refclk(struct drm_device *dev,
7908                            const struct intel_crtc_config *pipe_config)
7909 {
7910         struct drm_i915_private *dev_priv = dev->dev_private;
7911         u32 dpll = pipe_config->dpll_hw_state.dpll;
7912
7913         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7914                 return dev_priv->vbt.lvds_ssc_freq;
7915         else if (HAS_PCH_SPLIT(dev))
7916                 return 120000;
7917         else if (!IS_GEN2(dev))
7918                 return 96000;
7919         else
7920                 return 48000;
7921 }
7922
7923 /* Returns the clock of the currently programmed mode of the given pipe. */
7924 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7925                                 struct intel_crtc_config *pipe_config)
7926 {
7927         struct drm_device *dev = crtc->base.dev;
7928         struct drm_i915_private *dev_priv = dev->dev_private;
7929         int pipe = pipe_config->cpu_transcoder;
7930         u32 dpll = pipe_config->dpll_hw_state.dpll;
7931         u32 fp;
7932         intel_clock_t clock;
7933         int refclk = i9xx_pll_refclk(dev, pipe_config);
7934
7935         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7936                 fp = pipe_config->dpll_hw_state.fp0;
7937         else
7938                 fp = pipe_config->dpll_hw_state.fp1;
7939
7940         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7941         if (IS_PINEVIEW(dev)) {
7942                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7943                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7944         } else {
7945                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7946                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7947         }
7948
7949         if (!IS_GEN2(dev)) {
7950                 if (IS_PINEVIEW(dev))
7951                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7952                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7953                 else
7954                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7955                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7956
7957                 switch (dpll & DPLL_MODE_MASK) {
7958                 case DPLLB_MODE_DAC_SERIAL:
7959                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7960                                 5 : 10;
7961                         break;
7962                 case DPLLB_MODE_LVDS:
7963                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7964                                 7 : 14;
7965                         break;
7966                 default:
7967                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7968                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7969                         return;
7970                 }
7971
7972                 if (IS_PINEVIEW(dev))
7973                         pineview_clock(refclk, &clock);
7974                 else
7975                         i9xx_clock(refclk, &clock);
7976         } else {
7977                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
7978                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7979
7980                 if (is_lvds) {
7981                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7982                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7983
7984                         if (lvds & LVDS_CLKB_POWER_UP)
7985                                 clock.p2 = 7;
7986                         else
7987                                 clock.p2 = 14;
7988                 } else {
7989                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7990                                 clock.p1 = 2;
7991                         else {
7992                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7993                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7994                         }
7995                         if (dpll & PLL_P2_DIVIDE_BY_4)
7996                                 clock.p2 = 4;
7997                         else
7998                                 clock.p2 = 2;
7999                 }
8000
8001                 i9xx_clock(refclk, &clock);
8002         }
8003
8004         /*
8005          * This value includes pixel_multiplier. We will use
8006          * port_clock to compute adjusted_mode.crtc_clock in the
8007          * encoder's get_config() function.
8008          */
8009         pipe_config->port_clock = clock.dot;
8010 }
8011
8012 int intel_dotclock_calculate(int link_freq,
8013                              const struct intel_link_m_n *m_n)
8014 {
8015         /*
8016          * The calculation for the data clock is:
8017          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8018          * But we want to avoid losing precison if possible, so:
8019          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8020          *
8021          * and the link clock is simpler:
8022          * link_clock = (m * link_clock) / n
8023          */
8024
8025         if (!m_n->link_n)
8026                 return 0;
8027
8028         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8029 }
8030
8031 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8032                                    struct intel_crtc_config *pipe_config)
8033 {
8034         struct drm_device *dev = crtc->base.dev;
8035
8036         /* read out port_clock from the DPLL */
8037         i9xx_crtc_clock_get(crtc, pipe_config);
8038
8039         /*
8040          * This value does not include pixel_multiplier.
8041          * We will check that port_clock and adjusted_mode.crtc_clock
8042          * agree once we know their relationship in the encoder's
8043          * get_config() function.
8044          */
8045         pipe_config->adjusted_mode.crtc_clock =
8046                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8047                                          &pipe_config->fdi_m_n);
8048 }
8049
8050 /** Returns the currently programmed mode of the given pipe. */
8051 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8052                                              struct drm_crtc *crtc)
8053 {
8054         struct drm_i915_private *dev_priv = dev->dev_private;
8055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8056         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8057         struct drm_display_mode *mode;
8058         struct intel_crtc_config pipe_config;
8059         int htot = I915_READ(HTOTAL(cpu_transcoder));
8060         int hsync = I915_READ(HSYNC(cpu_transcoder));
8061         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8062         int vsync = I915_READ(VSYNC(cpu_transcoder));
8063         enum pipe pipe = intel_crtc->pipe;
8064
8065         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8066         if (!mode)
8067                 return NULL;
8068
8069         /*
8070          * Construct a pipe_config sufficient for getting the clock info
8071          * back out of crtc_clock_get.
8072          *
8073          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8074          * to use a real value here instead.
8075          */
8076         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8077         pipe_config.pixel_multiplier = 1;
8078         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8079         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8080         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8081         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8082
8083         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8084         mode->hdisplay = (htot & 0xffff) + 1;
8085         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8086         mode->hsync_start = (hsync & 0xffff) + 1;
8087         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8088         mode->vdisplay = (vtot & 0xffff) + 1;
8089         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8090         mode->vsync_start = (vsync & 0xffff) + 1;
8091         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8092
8093         drm_mode_set_name(mode);
8094
8095         return mode;
8096 }
8097
8098 static void intel_increase_pllclock(struct drm_crtc *crtc)
8099 {
8100         struct drm_device *dev = crtc->dev;
8101         drm_i915_private_t *dev_priv = dev->dev_private;
8102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8103         int pipe = intel_crtc->pipe;
8104         int dpll_reg = DPLL(pipe);
8105         int dpll;
8106
8107         if (HAS_PCH_SPLIT(dev))
8108                 return;
8109
8110         if (!dev_priv->lvds_downclock_avail)
8111                 return;
8112
8113         dpll = I915_READ(dpll_reg);
8114         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8115                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8116
8117                 assert_panel_unlocked(dev_priv, pipe);
8118
8119                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8120                 I915_WRITE(dpll_reg, dpll);
8121                 intel_wait_for_vblank(dev, pipe);
8122
8123                 dpll = I915_READ(dpll_reg);
8124                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8125                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8126         }
8127 }
8128
8129 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8130 {
8131         struct drm_device *dev = crtc->dev;
8132         drm_i915_private_t *dev_priv = dev->dev_private;
8133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8134
8135         if (HAS_PCH_SPLIT(dev))
8136                 return;
8137
8138         if (!dev_priv->lvds_downclock_avail)
8139                 return;
8140
8141         /*
8142          * Since this is called by a timer, we should never get here in
8143          * the manual case.
8144          */
8145         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8146                 int pipe = intel_crtc->pipe;
8147                 int dpll_reg = DPLL(pipe);
8148                 int dpll;
8149
8150                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8151
8152                 assert_panel_unlocked(dev_priv, pipe);
8153
8154                 dpll = I915_READ(dpll_reg);
8155                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8156                 I915_WRITE(dpll_reg, dpll);
8157                 intel_wait_for_vblank(dev, pipe);
8158                 dpll = I915_READ(dpll_reg);
8159                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8160                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8161         }
8162
8163 }
8164
8165 void intel_mark_busy(struct drm_device *dev)
8166 {
8167         struct drm_i915_private *dev_priv = dev->dev_private;
8168
8169         hsw_package_c8_gpu_busy(dev_priv);
8170         i915_update_gfx_val(dev_priv);
8171 }
8172
8173 void intel_mark_idle(struct drm_device *dev)
8174 {
8175         struct drm_i915_private *dev_priv = dev->dev_private;
8176         struct drm_crtc *crtc;
8177
8178         hsw_package_c8_gpu_idle(dev_priv);
8179
8180         if (!i915_powersave)
8181                 return;
8182
8183         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8184                 if (!crtc->fb)
8185                         continue;
8186
8187                 intel_decrease_pllclock(crtc);
8188         }
8189
8190         if (dev_priv->info->gen >= 6)
8191                 gen6_rps_idle(dev->dev_private);
8192 }
8193
8194 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8195                         struct intel_ring_buffer *ring)
8196 {
8197         struct drm_device *dev = obj->base.dev;
8198         struct drm_crtc *crtc;
8199
8200         if (!i915_powersave)
8201                 return;
8202
8203         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8204                 if (!crtc->fb)
8205                         continue;
8206
8207                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8208                         continue;
8209
8210                 intel_increase_pllclock(crtc);
8211                 if (ring && intel_fbc_enabled(dev))
8212                         ring->fbc_dirty = true;
8213         }
8214 }
8215
8216 static void intel_crtc_destroy(struct drm_crtc *crtc)
8217 {
8218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8219         struct drm_device *dev = crtc->dev;
8220         struct intel_unpin_work *work;
8221         unsigned long flags;
8222
8223         spin_lock_irqsave(&dev->event_lock, flags);
8224         work = intel_crtc->unpin_work;
8225         intel_crtc->unpin_work = NULL;
8226         spin_unlock_irqrestore(&dev->event_lock, flags);
8227
8228         if (work) {
8229                 cancel_work_sync(&work->work);
8230                 kfree(work);
8231         }
8232
8233         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8234
8235         drm_crtc_cleanup(crtc);
8236
8237         kfree(intel_crtc);
8238 }
8239
8240 static void intel_unpin_work_fn(struct work_struct *__work)
8241 {
8242         struct intel_unpin_work *work =
8243                 container_of(__work, struct intel_unpin_work, work);
8244         struct drm_device *dev = work->crtc->dev;
8245
8246         mutex_lock(&dev->struct_mutex);
8247         intel_unpin_fb_obj(work->old_fb_obj);
8248         drm_gem_object_unreference(&work->pending_flip_obj->base);
8249         drm_gem_object_unreference(&work->old_fb_obj->base);
8250
8251         intel_update_fbc(dev);
8252         mutex_unlock(&dev->struct_mutex);
8253
8254         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8255         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8256
8257         kfree(work);
8258 }
8259
8260 static void do_intel_finish_page_flip(struct drm_device *dev,
8261                                       struct drm_crtc *crtc)
8262 {
8263         drm_i915_private_t *dev_priv = dev->dev_private;
8264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8265         struct intel_unpin_work *work;
8266         unsigned long flags;
8267
8268         /* Ignore early vblank irqs */
8269         if (intel_crtc == NULL)
8270                 return;
8271
8272         spin_lock_irqsave(&dev->event_lock, flags);
8273         work = intel_crtc->unpin_work;
8274
8275         /* Ensure we don't miss a work->pending update ... */
8276         smp_rmb();
8277
8278         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8279                 spin_unlock_irqrestore(&dev->event_lock, flags);
8280                 return;
8281         }
8282
8283         /* and that the unpin work is consistent wrt ->pending. */
8284         smp_rmb();
8285
8286         intel_crtc->unpin_work = NULL;
8287
8288         if (work->event)
8289                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8290
8291         drm_vblank_put(dev, intel_crtc->pipe);
8292
8293         spin_unlock_irqrestore(&dev->event_lock, flags);
8294
8295         wake_up_all(&dev_priv->pending_flip_queue);
8296
8297         queue_work(dev_priv->wq, &work->work);
8298
8299         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8300 }
8301
8302 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8303 {
8304         drm_i915_private_t *dev_priv = dev->dev_private;
8305         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8306
8307         do_intel_finish_page_flip(dev, crtc);
8308 }
8309
8310 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8311 {
8312         drm_i915_private_t *dev_priv = dev->dev_private;
8313         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8314
8315         do_intel_finish_page_flip(dev, crtc);
8316 }
8317
8318 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8319 {
8320         drm_i915_private_t *dev_priv = dev->dev_private;
8321         struct intel_crtc *intel_crtc =
8322                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8323         unsigned long flags;
8324
8325         /* NB: An MMIO update of the plane base pointer will also
8326          * generate a page-flip completion irq, i.e. every modeset
8327          * is also accompanied by a spurious intel_prepare_page_flip().
8328          */
8329         spin_lock_irqsave(&dev->event_lock, flags);
8330         if (intel_crtc->unpin_work)
8331                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8332         spin_unlock_irqrestore(&dev->event_lock, flags);
8333 }
8334
8335 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8336 {
8337         /* Ensure that the work item is consistent when activating it ... */
8338         smp_wmb();
8339         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8340         /* and that it is marked active as soon as the irq could fire. */
8341         smp_wmb();
8342 }
8343
8344 static int intel_gen2_queue_flip(struct drm_device *dev,
8345                                  struct drm_crtc *crtc,
8346                                  struct drm_framebuffer *fb,
8347                                  struct drm_i915_gem_object *obj,
8348                                  uint32_t flags)
8349 {
8350         struct drm_i915_private *dev_priv = dev->dev_private;
8351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8352         u32 flip_mask;
8353         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8354         int ret;
8355
8356         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8357         if (ret)
8358                 goto err;
8359
8360         ret = intel_ring_begin(ring, 6);
8361         if (ret)
8362                 goto err_unpin;
8363
8364         /* Can't queue multiple flips, so wait for the previous
8365          * one to finish before executing the next.
8366          */
8367         if (intel_crtc->plane)
8368                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8369         else
8370                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8371         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8372         intel_ring_emit(ring, MI_NOOP);
8373         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8374                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8375         intel_ring_emit(ring, fb->pitches[0]);
8376         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8377         intel_ring_emit(ring, 0); /* aux display base address, unused */
8378
8379         intel_mark_page_flip_active(intel_crtc);
8380         __intel_ring_advance(ring);
8381         return 0;
8382
8383 err_unpin:
8384         intel_unpin_fb_obj(obj);
8385 err:
8386         return ret;
8387 }
8388
8389 static int intel_gen3_queue_flip(struct drm_device *dev,
8390                                  struct drm_crtc *crtc,
8391                                  struct drm_framebuffer *fb,
8392                                  struct drm_i915_gem_object *obj,
8393                                  uint32_t flags)
8394 {
8395         struct drm_i915_private *dev_priv = dev->dev_private;
8396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8397         u32 flip_mask;
8398         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8399         int ret;
8400
8401         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8402         if (ret)
8403                 goto err;
8404
8405         ret = intel_ring_begin(ring, 6);
8406         if (ret)
8407                 goto err_unpin;
8408
8409         if (intel_crtc->plane)
8410                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8411         else
8412                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8413         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8414         intel_ring_emit(ring, MI_NOOP);
8415         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8416                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8417         intel_ring_emit(ring, fb->pitches[0]);
8418         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8419         intel_ring_emit(ring, MI_NOOP);
8420
8421         intel_mark_page_flip_active(intel_crtc);
8422         __intel_ring_advance(ring);
8423         return 0;
8424
8425 err_unpin:
8426         intel_unpin_fb_obj(obj);
8427 err:
8428         return ret;
8429 }
8430
8431 static int intel_gen4_queue_flip(struct drm_device *dev,
8432                                  struct drm_crtc *crtc,
8433                                  struct drm_framebuffer *fb,
8434                                  struct drm_i915_gem_object *obj,
8435                                  uint32_t flags)
8436 {
8437         struct drm_i915_private *dev_priv = dev->dev_private;
8438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8439         uint32_t pf, pipesrc;
8440         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8441         int ret;
8442
8443         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8444         if (ret)
8445                 goto err;
8446
8447         ret = intel_ring_begin(ring, 4);
8448         if (ret)
8449                 goto err_unpin;
8450
8451         /* i965+ uses the linear or tiled offsets from the
8452          * Display Registers (which do not change across a page-flip)
8453          * so we need only reprogram the base address.
8454          */
8455         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8456                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8457         intel_ring_emit(ring, fb->pitches[0]);
8458         intel_ring_emit(ring,
8459                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8460                         obj->tiling_mode);
8461
8462         /* XXX Enabling the panel-fitter across page-flip is so far
8463          * untested on non-native modes, so ignore it for now.
8464          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8465          */
8466         pf = 0;
8467         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8468         intel_ring_emit(ring, pf | pipesrc);
8469
8470         intel_mark_page_flip_active(intel_crtc);
8471         __intel_ring_advance(ring);
8472         return 0;
8473
8474 err_unpin:
8475         intel_unpin_fb_obj(obj);
8476 err:
8477         return ret;
8478 }
8479
8480 static int intel_gen6_queue_flip(struct drm_device *dev,
8481                                  struct drm_crtc *crtc,
8482                                  struct drm_framebuffer *fb,
8483                                  struct drm_i915_gem_object *obj,
8484                                  uint32_t flags)
8485 {
8486         struct drm_i915_private *dev_priv = dev->dev_private;
8487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8488         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8489         uint32_t pf, pipesrc;
8490         int ret;
8491
8492         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8493         if (ret)
8494                 goto err;
8495
8496         ret = intel_ring_begin(ring, 4);
8497         if (ret)
8498                 goto err_unpin;
8499
8500         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8501                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8502         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8503         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8504
8505         /* Contrary to the suggestions in the documentation,
8506          * "Enable Panel Fitter" does not seem to be required when page
8507          * flipping with a non-native mode, and worse causes a normal
8508          * modeset to fail.
8509          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8510          */
8511         pf = 0;
8512         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8513         intel_ring_emit(ring, pf | pipesrc);
8514
8515         intel_mark_page_flip_active(intel_crtc);
8516         __intel_ring_advance(ring);
8517         return 0;
8518
8519 err_unpin:
8520         intel_unpin_fb_obj(obj);
8521 err:
8522         return ret;
8523 }
8524
8525 static int intel_gen7_queue_flip(struct drm_device *dev,
8526                                  struct drm_crtc *crtc,
8527                                  struct drm_framebuffer *fb,
8528                                  struct drm_i915_gem_object *obj,
8529                                  uint32_t flags)
8530 {
8531         struct drm_i915_private *dev_priv = dev->dev_private;
8532         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8533         struct intel_ring_buffer *ring;
8534         uint32_t plane_bit = 0;
8535         int len, ret;
8536
8537         ring = obj->ring;
8538         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8539                 ring = &dev_priv->ring[BCS];
8540
8541         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8542         if (ret)
8543                 goto err;
8544
8545         switch(intel_crtc->plane) {
8546         case PLANE_A:
8547                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8548                 break;
8549         case PLANE_B:
8550                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8551                 break;
8552         case PLANE_C:
8553                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8554                 break;
8555         default:
8556                 WARN_ONCE(1, "unknown plane in flip command\n");
8557                 ret = -ENODEV;
8558                 goto err_unpin;
8559         }
8560
8561         len = 4;
8562         if (ring->id == RCS)
8563                 len += 6;
8564
8565         ret = intel_ring_begin(ring, len);
8566         if (ret)
8567                 goto err_unpin;
8568
8569         /* Unmask the flip-done completion message. Note that the bspec says that
8570          * we should do this for both the BCS and RCS, and that we must not unmask
8571          * more than one flip event at any time (or ensure that one flip message
8572          * can be sent by waiting for flip-done prior to queueing new flips).
8573          * Experimentation says that BCS works despite DERRMR masking all
8574          * flip-done completion events and that unmasking all planes at once
8575          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8576          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8577          */
8578         if (ring->id == RCS) {
8579                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8580                 intel_ring_emit(ring, DERRMR);
8581                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8582                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8583                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8584                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8585                                 MI_SRM_LRM_GLOBAL_GTT);
8586                 intel_ring_emit(ring, DERRMR);
8587                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8588         }
8589
8590         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8591         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8592         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8593         intel_ring_emit(ring, (MI_NOOP));
8594
8595         intel_mark_page_flip_active(intel_crtc);
8596         __intel_ring_advance(ring);
8597         return 0;
8598
8599 err_unpin:
8600         intel_unpin_fb_obj(obj);
8601 err:
8602         return ret;
8603 }
8604
8605 static int intel_default_queue_flip(struct drm_device *dev,
8606                                     struct drm_crtc *crtc,
8607                                     struct drm_framebuffer *fb,
8608                                     struct drm_i915_gem_object *obj,
8609                                     uint32_t flags)
8610 {
8611         return -ENODEV;
8612 }
8613
8614 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8615                                 struct drm_framebuffer *fb,
8616                                 struct drm_pending_vblank_event *event,
8617                                 uint32_t page_flip_flags)
8618 {
8619         struct drm_device *dev = crtc->dev;
8620         struct drm_i915_private *dev_priv = dev->dev_private;
8621         struct drm_framebuffer *old_fb = crtc->fb;
8622         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8624         struct intel_unpin_work *work;
8625         unsigned long flags;
8626         int ret;
8627
8628         /* Can't change pixel format via MI display flips. */
8629         if (fb->pixel_format != crtc->fb->pixel_format)
8630                 return -EINVAL;
8631
8632         /*
8633          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8634          * Note that pitch changes could also affect these register.
8635          */
8636         if (INTEL_INFO(dev)->gen > 3 &&
8637             (fb->offsets[0] != crtc->fb->offsets[0] ||
8638              fb->pitches[0] != crtc->fb->pitches[0]))
8639                 return -EINVAL;
8640
8641         work = kzalloc(sizeof(*work), GFP_KERNEL);
8642         if (work == NULL)
8643                 return -ENOMEM;
8644
8645         work->event = event;
8646         work->crtc = crtc;
8647         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8648         INIT_WORK(&work->work, intel_unpin_work_fn);
8649
8650         ret = drm_vblank_get(dev, intel_crtc->pipe);
8651         if (ret)
8652                 goto free_work;
8653
8654         /* We borrow the event spin lock for protecting unpin_work */
8655         spin_lock_irqsave(&dev->event_lock, flags);
8656         if (intel_crtc->unpin_work) {
8657                 spin_unlock_irqrestore(&dev->event_lock, flags);
8658                 kfree(work);
8659                 drm_vblank_put(dev, intel_crtc->pipe);
8660
8661                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8662                 return -EBUSY;
8663         }
8664         intel_crtc->unpin_work = work;
8665         spin_unlock_irqrestore(&dev->event_lock, flags);
8666
8667         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8668                 flush_workqueue(dev_priv->wq);
8669
8670         ret = i915_mutex_lock_interruptible(dev);
8671         if (ret)
8672                 goto cleanup;
8673
8674         /* Reference the objects for the scheduled work. */
8675         drm_gem_object_reference(&work->old_fb_obj->base);
8676         drm_gem_object_reference(&obj->base);
8677
8678         crtc->fb = fb;
8679
8680         work->pending_flip_obj = obj;
8681
8682         work->enable_stall_check = true;
8683
8684         atomic_inc(&intel_crtc->unpin_work_count);
8685         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8686
8687         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8688         if (ret)
8689                 goto cleanup_pending;
8690
8691         intel_disable_fbc(dev);
8692         intel_mark_fb_busy(obj, NULL);
8693         mutex_unlock(&dev->struct_mutex);
8694
8695         trace_i915_flip_request(intel_crtc->plane, obj);
8696
8697         return 0;
8698
8699 cleanup_pending:
8700         atomic_dec(&intel_crtc->unpin_work_count);
8701         crtc->fb = old_fb;
8702         drm_gem_object_unreference(&work->old_fb_obj->base);
8703         drm_gem_object_unreference(&obj->base);
8704         mutex_unlock(&dev->struct_mutex);
8705
8706 cleanup:
8707         spin_lock_irqsave(&dev->event_lock, flags);
8708         intel_crtc->unpin_work = NULL;
8709         spin_unlock_irqrestore(&dev->event_lock, flags);
8710
8711         drm_vblank_put(dev, intel_crtc->pipe);
8712 free_work:
8713         kfree(work);
8714
8715         return ret;
8716 }
8717
8718 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8719         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8720         .load_lut = intel_crtc_load_lut,
8721 };
8722
8723 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8724                                   struct drm_crtc *crtc)
8725 {
8726         struct drm_device *dev;
8727         struct drm_crtc *tmp;
8728         int crtc_mask = 1;
8729
8730         WARN(!crtc, "checking null crtc?\n");
8731
8732         dev = crtc->dev;
8733
8734         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8735                 if (tmp == crtc)
8736                         break;
8737                 crtc_mask <<= 1;
8738         }
8739
8740         if (encoder->possible_crtcs & crtc_mask)
8741                 return true;
8742         return false;
8743 }
8744
8745 /**
8746  * intel_modeset_update_staged_output_state
8747  *
8748  * Updates the staged output configuration state, e.g. after we've read out the
8749  * current hw state.
8750  */
8751 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8752 {
8753         struct intel_encoder *encoder;
8754         struct intel_connector *connector;
8755
8756         list_for_each_entry(connector, &dev->mode_config.connector_list,
8757                             base.head) {
8758                 connector->new_encoder =
8759                         to_intel_encoder(connector->base.encoder);
8760         }
8761
8762         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8763                             base.head) {
8764                 encoder->new_crtc =
8765                         to_intel_crtc(encoder->base.crtc);
8766         }
8767 }
8768
8769 /**
8770  * intel_modeset_commit_output_state
8771  *
8772  * This function copies the stage display pipe configuration to the real one.
8773  */
8774 static void intel_modeset_commit_output_state(struct drm_device *dev)
8775 {
8776         struct intel_encoder *encoder;
8777         struct intel_connector *connector;
8778
8779         list_for_each_entry(connector, &dev->mode_config.connector_list,
8780                             base.head) {
8781                 connector->base.encoder = &connector->new_encoder->base;
8782         }
8783
8784         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8785                             base.head) {
8786                 encoder->base.crtc = &encoder->new_crtc->base;
8787         }
8788 }
8789
8790 static void
8791 connected_sink_compute_bpp(struct intel_connector * connector,
8792                            struct intel_crtc_config *pipe_config)
8793 {
8794         int bpp = pipe_config->pipe_bpp;
8795
8796         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8797                 connector->base.base.id,
8798                 drm_get_connector_name(&connector->base));
8799
8800         /* Don't use an invalid EDID bpc value */
8801         if (connector->base.display_info.bpc &&
8802             connector->base.display_info.bpc * 3 < bpp) {
8803                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8804                               bpp, connector->base.display_info.bpc*3);
8805                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8806         }
8807
8808         /* Clamp bpp to 8 on screens without EDID 1.4 */
8809         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8810                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8811                               bpp);
8812                 pipe_config->pipe_bpp = 24;
8813         }
8814 }
8815
8816 static int
8817 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8818                           struct drm_framebuffer *fb,
8819                           struct intel_crtc_config *pipe_config)
8820 {
8821         struct drm_device *dev = crtc->base.dev;
8822         struct intel_connector *connector;
8823         int bpp;
8824
8825         switch (fb->pixel_format) {
8826         case DRM_FORMAT_C8:
8827                 bpp = 8*3; /* since we go through a colormap */
8828                 break;
8829         case DRM_FORMAT_XRGB1555:
8830         case DRM_FORMAT_ARGB1555:
8831                 /* checked in intel_framebuffer_init already */
8832                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8833                         return -EINVAL;
8834         case DRM_FORMAT_RGB565:
8835                 bpp = 6*3; /* min is 18bpp */
8836                 break;
8837         case DRM_FORMAT_XBGR8888:
8838         case DRM_FORMAT_ABGR8888:
8839                 /* checked in intel_framebuffer_init already */
8840                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8841                         return -EINVAL;
8842         case DRM_FORMAT_XRGB8888:
8843         case DRM_FORMAT_ARGB8888:
8844                 bpp = 8*3;
8845                 break;
8846         case DRM_FORMAT_XRGB2101010:
8847         case DRM_FORMAT_ARGB2101010:
8848         case DRM_FORMAT_XBGR2101010:
8849         case DRM_FORMAT_ABGR2101010:
8850                 /* checked in intel_framebuffer_init already */
8851                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8852                         return -EINVAL;
8853                 bpp = 10*3;
8854                 break;
8855         /* TODO: gen4+ supports 16 bpc floating point, too. */
8856         default:
8857                 DRM_DEBUG_KMS("unsupported depth\n");
8858                 return -EINVAL;
8859         }
8860
8861         pipe_config->pipe_bpp = bpp;
8862
8863         /* Clamp display bpp to EDID value */
8864         list_for_each_entry(connector, &dev->mode_config.connector_list,
8865                             base.head) {
8866                 if (!connector->new_encoder ||
8867                     connector->new_encoder->new_crtc != crtc)
8868                         continue;
8869
8870                 connected_sink_compute_bpp(connector, pipe_config);
8871         }
8872
8873         return bpp;
8874 }
8875
8876 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8877 {
8878         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8879                         "type: 0x%x flags: 0x%x\n",
8880                 mode->crtc_clock,
8881                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8882                 mode->crtc_hsync_end, mode->crtc_htotal,
8883                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8884                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8885 }
8886
8887 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8888                                    struct intel_crtc_config *pipe_config,
8889                                    const char *context)
8890 {
8891         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8892                       context, pipe_name(crtc->pipe));
8893
8894         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8895         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8896                       pipe_config->pipe_bpp, pipe_config->dither);
8897         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8898                       pipe_config->has_pch_encoder,
8899                       pipe_config->fdi_lanes,
8900                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8901                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8902                       pipe_config->fdi_m_n.tu);
8903         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8904                       pipe_config->has_dp_encoder,
8905                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8906                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8907                       pipe_config->dp_m_n.tu);
8908         DRM_DEBUG_KMS("requested mode:\n");
8909         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8910         DRM_DEBUG_KMS("adjusted mode:\n");
8911         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8912         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8913         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8914         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8915                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8916         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8917                       pipe_config->gmch_pfit.control,
8918                       pipe_config->gmch_pfit.pgm_ratios,
8919                       pipe_config->gmch_pfit.lvds_border_bits);
8920         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8921                       pipe_config->pch_pfit.pos,
8922                       pipe_config->pch_pfit.size,
8923                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8924         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8925         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8926 }
8927
8928 static bool check_encoder_cloning(struct drm_crtc *crtc)
8929 {
8930         int num_encoders = 0;
8931         bool uncloneable_encoders = false;
8932         struct intel_encoder *encoder;
8933
8934         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8935                             base.head) {
8936                 if (&encoder->new_crtc->base != crtc)
8937                         continue;
8938
8939                 num_encoders++;
8940                 if (!encoder->cloneable)
8941                         uncloneable_encoders = true;
8942         }
8943
8944         return !(num_encoders > 1 && uncloneable_encoders);
8945 }
8946
8947 static struct intel_crtc_config *
8948 intel_modeset_pipe_config(struct drm_crtc *crtc,
8949                           struct drm_framebuffer *fb,
8950                           struct drm_display_mode *mode)
8951 {
8952         struct drm_device *dev = crtc->dev;
8953         struct intel_encoder *encoder;
8954         struct intel_crtc_config *pipe_config;
8955         int plane_bpp, ret = -EINVAL;
8956         bool retry = true;
8957
8958         if (!check_encoder_cloning(crtc)) {
8959                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8960                 return ERR_PTR(-EINVAL);
8961         }
8962
8963         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8964         if (!pipe_config)
8965                 return ERR_PTR(-ENOMEM);
8966
8967         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8968         drm_mode_copy(&pipe_config->requested_mode, mode);
8969
8970         pipe_config->cpu_transcoder =
8971                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8972         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8973
8974         /*
8975          * Sanitize sync polarity flags based on requested ones. If neither
8976          * positive or negative polarity is requested, treat this as meaning
8977          * negative polarity.
8978          */
8979         if (!(pipe_config->adjusted_mode.flags &
8980               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8981                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8982
8983         if (!(pipe_config->adjusted_mode.flags &
8984               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8985                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8986
8987         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8988          * plane pixel format and any sink constraints into account. Returns the
8989          * source plane bpp so that dithering can be selected on mismatches
8990          * after encoders and crtc also have had their say. */
8991         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8992                                               fb, pipe_config);
8993         if (plane_bpp < 0)
8994                 goto fail;
8995
8996         /*
8997          * Determine the real pipe dimensions. Note that stereo modes can
8998          * increase the actual pipe size due to the frame doubling and
8999          * insertion of additional space for blanks between the frame. This
9000          * is stored in the crtc timings. We use the requested mode to do this
9001          * computation to clearly distinguish it from the adjusted mode, which
9002          * can be changed by the connectors in the below retry loop.
9003          */
9004         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9005         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9006         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9007
9008 encoder_retry:
9009         /* Ensure the port clock defaults are reset when retrying. */
9010         pipe_config->port_clock = 0;
9011         pipe_config->pixel_multiplier = 1;
9012
9013         /* Fill in default crtc timings, allow encoders to overwrite them. */
9014         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9015
9016         /* Pass our mode to the connectors and the CRTC to give them a chance to
9017          * adjust it according to limitations or connector properties, and also
9018          * a chance to reject the mode entirely.
9019          */
9020         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9021                             base.head) {
9022
9023                 if (&encoder->new_crtc->base != crtc)
9024                         continue;
9025
9026                 if (!(encoder->compute_config(encoder, pipe_config))) {
9027                         DRM_DEBUG_KMS("Encoder config failure\n");
9028                         goto fail;
9029                 }
9030         }
9031
9032         /* Set default port clock if not overwritten by the encoder. Needs to be
9033          * done afterwards in case the encoder adjusts the mode. */
9034         if (!pipe_config->port_clock)
9035                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9036                         * pipe_config->pixel_multiplier;
9037
9038         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9039         if (ret < 0) {
9040                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9041                 goto fail;
9042         }
9043
9044         if (ret == RETRY) {
9045                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9046                         ret = -EINVAL;
9047                         goto fail;
9048                 }
9049
9050                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9051                 retry = false;
9052                 goto encoder_retry;
9053         }
9054
9055         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9056         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9057                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9058
9059         return pipe_config;
9060 fail:
9061         kfree(pipe_config);
9062         return ERR_PTR(ret);
9063 }
9064
9065 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9066  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9067 static void
9068 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9069                              unsigned *prepare_pipes, unsigned *disable_pipes)
9070 {
9071         struct intel_crtc *intel_crtc;
9072         struct drm_device *dev = crtc->dev;
9073         struct intel_encoder *encoder;
9074         struct intel_connector *connector;
9075         struct drm_crtc *tmp_crtc;
9076
9077         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9078
9079         /* Check which crtcs have changed outputs connected to them, these need
9080          * to be part of the prepare_pipes mask. We don't (yet) support global
9081          * modeset across multiple crtcs, so modeset_pipes will only have one
9082          * bit set at most. */
9083         list_for_each_entry(connector, &dev->mode_config.connector_list,
9084                             base.head) {
9085                 if (connector->base.encoder == &connector->new_encoder->base)
9086                         continue;
9087
9088                 if (connector->base.encoder) {
9089                         tmp_crtc = connector->base.encoder->crtc;
9090
9091                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9092                 }
9093
9094                 if (connector->new_encoder)
9095                         *prepare_pipes |=
9096                                 1 << connector->new_encoder->new_crtc->pipe;
9097         }
9098
9099         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9100                             base.head) {
9101                 if (encoder->base.crtc == &encoder->new_crtc->base)
9102                         continue;
9103
9104                 if (encoder->base.crtc) {
9105                         tmp_crtc = encoder->base.crtc;
9106
9107                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9108                 }
9109
9110                 if (encoder->new_crtc)
9111                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9112         }
9113
9114         /* Check for any pipes that will be fully disabled ... */
9115         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9116                             base.head) {
9117                 bool used = false;
9118
9119                 /* Don't try to disable disabled crtcs. */
9120                 if (!intel_crtc->base.enabled)
9121                         continue;
9122
9123                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9124                                     base.head) {
9125                         if (encoder->new_crtc == intel_crtc)
9126                                 used = true;
9127                 }
9128
9129                 if (!used)
9130                         *disable_pipes |= 1 << intel_crtc->pipe;
9131         }
9132
9133
9134         /* set_mode is also used to update properties on life display pipes. */
9135         intel_crtc = to_intel_crtc(crtc);
9136         if (crtc->enabled)
9137                 *prepare_pipes |= 1 << intel_crtc->pipe;
9138
9139         /*
9140          * For simplicity do a full modeset on any pipe where the output routing
9141          * changed. We could be more clever, but that would require us to be
9142          * more careful with calling the relevant encoder->mode_set functions.
9143          */
9144         if (*prepare_pipes)
9145                 *modeset_pipes = *prepare_pipes;
9146
9147         /* ... and mask these out. */
9148         *modeset_pipes &= ~(*disable_pipes);
9149         *prepare_pipes &= ~(*disable_pipes);
9150
9151         /*
9152          * HACK: We don't (yet) fully support global modesets. intel_set_config
9153          * obies this rule, but the modeset restore mode of
9154          * intel_modeset_setup_hw_state does not.
9155          */
9156         *modeset_pipes &= 1 << intel_crtc->pipe;
9157         *prepare_pipes &= 1 << intel_crtc->pipe;
9158
9159         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9160                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9161 }
9162
9163 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9164 {
9165         struct drm_encoder *encoder;
9166         struct drm_device *dev = crtc->dev;
9167
9168         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9169                 if (encoder->crtc == crtc)
9170                         return true;
9171
9172         return false;
9173 }
9174
9175 static void
9176 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9177 {
9178         struct intel_encoder *intel_encoder;
9179         struct intel_crtc *intel_crtc;
9180         struct drm_connector *connector;
9181
9182         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9183                             base.head) {
9184                 if (!intel_encoder->base.crtc)
9185                         continue;
9186
9187                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9188
9189                 if (prepare_pipes & (1 << intel_crtc->pipe))
9190                         intel_encoder->connectors_active = false;
9191         }
9192
9193         intel_modeset_commit_output_state(dev);
9194
9195         /* Update computed state. */
9196         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9197                             base.head) {
9198                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9199         }
9200
9201         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9202                 if (!connector->encoder || !connector->encoder->crtc)
9203                         continue;
9204
9205                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9206
9207                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9208                         struct drm_property *dpms_property =
9209                                 dev->mode_config.dpms_property;
9210
9211                         connector->dpms = DRM_MODE_DPMS_ON;
9212                         drm_object_property_set_value(&connector->base,
9213                                                          dpms_property,
9214                                                          DRM_MODE_DPMS_ON);
9215
9216                         intel_encoder = to_intel_encoder(connector->encoder);
9217                         intel_encoder->connectors_active = true;
9218                 }
9219         }
9220
9221 }
9222
9223 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9224 {
9225         int diff;
9226
9227         if (clock1 == clock2)
9228                 return true;
9229
9230         if (!clock1 || !clock2)
9231                 return false;
9232
9233         diff = abs(clock1 - clock2);
9234
9235         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9236                 return true;
9237
9238         return false;
9239 }
9240
9241 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9242         list_for_each_entry((intel_crtc), \
9243                             &(dev)->mode_config.crtc_list, \
9244                             base.head) \
9245                 if (mask & (1 <<(intel_crtc)->pipe))
9246
9247 static bool
9248 intel_pipe_config_compare(struct drm_device *dev,
9249                           struct intel_crtc_config *current_config,
9250                           struct intel_crtc_config *pipe_config)
9251 {
9252 #define PIPE_CONF_CHECK_X(name) \
9253         if (current_config->name != pipe_config->name) { \
9254                 DRM_ERROR("mismatch in " #name " " \
9255                           "(expected 0x%08x, found 0x%08x)\n", \
9256                           current_config->name, \
9257                           pipe_config->name); \
9258                 return false; \
9259         }
9260
9261 #define PIPE_CONF_CHECK_I(name) \
9262         if (current_config->name != pipe_config->name) { \
9263                 DRM_ERROR("mismatch in " #name " " \
9264                           "(expected %i, found %i)\n", \
9265                           current_config->name, \
9266                           pipe_config->name); \
9267                 return false; \
9268         }
9269
9270 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9271         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9272                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9273                           "(expected %i, found %i)\n", \
9274                           current_config->name & (mask), \
9275                           pipe_config->name & (mask)); \
9276                 return false; \
9277         }
9278
9279 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9280         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9281                 DRM_ERROR("mismatch in " #name " " \
9282                           "(expected %i, found %i)\n", \
9283                           current_config->name, \
9284                           pipe_config->name); \
9285                 return false; \
9286         }
9287
9288 #define PIPE_CONF_QUIRK(quirk)  \
9289         ((current_config->quirks | pipe_config->quirks) & (quirk))
9290
9291         PIPE_CONF_CHECK_I(cpu_transcoder);
9292
9293         PIPE_CONF_CHECK_I(has_pch_encoder);
9294         PIPE_CONF_CHECK_I(fdi_lanes);
9295         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9296         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9297         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9298         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9299         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9300
9301         PIPE_CONF_CHECK_I(has_dp_encoder);
9302         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9303         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9304         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9305         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9306         PIPE_CONF_CHECK_I(dp_m_n.tu);
9307
9308         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9309         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9310         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9311         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9312         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9313         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9314
9315         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9316         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9317         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9318         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9319         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9320         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9321
9322         PIPE_CONF_CHECK_I(pixel_multiplier);
9323
9324         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9325                               DRM_MODE_FLAG_INTERLACE);
9326
9327         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9328                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9329                                       DRM_MODE_FLAG_PHSYNC);
9330                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9331                                       DRM_MODE_FLAG_NHSYNC);
9332                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9333                                       DRM_MODE_FLAG_PVSYNC);
9334                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9335                                       DRM_MODE_FLAG_NVSYNC);
9336         }
9337
9338         PIPE_CONF_CHECK_I(pipe_src_w);
9339         PIPE_CONF_CHECK_I(pipe_src_h);
9340
9341         PIPE_CONF_CHECK_I(gmch_pfit.control);
9342         /* pfit ratios are autocomputed by the hw on gen4+ */
9343         if (INTEL_INFO(dev)->gen < 4)
9344                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9345         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9346         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9347         if (current_config->pch_pfit.enabled) {
9348                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9349                 PIPE_CONF_CHECK_I(pch_pfit.size);
9350         }
9351
9352         /* BDW+ don't expose a synchronous way to read the state */
9353         if (IS_HASWELL(dev))
9354                 PIPE_CONF_CHECK_I(ips_enabled);
9355
9356         PIPE_CONF_CHECK_I(double_wide);
9357
9358         PIPE_CONF_CHECK_I(shared_dpll);
9359         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9360         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9361         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9362         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9363
9364         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9365                 PIPE_CONF_CHECK_I(pipe_bpp);
9366
9367         if (!HAS_DDI(dev)) {
9368                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9369                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9370         }
9371
9372 #undef PIPE_CONF_CHECK_X
9373 #undef PIPE_CONF_CHECK_I
9374 #undef PIPE_CONF_CHECK_FLAGS
9375 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9376 #undef PIPE_CONF_QUIRK
9377
9378         return true;
9379 }
9380
9381 static void
9382 check_connector_state(struct drm_device *dev)
9383 {
9384         struct intel_connector *connector;
9385
9386         list_for_each_entry(connector, &dev->mode_config.connector_list,
9387                             base.head) {
9388                 /* This also checks the encoder/connector hw state with the
9389                  * ->get_hw_state callbacks. */
9390                 intel_connector_check_state(connector);
9391
9392                 WARN(&connector->new_encoder->base != connector->base.encoder,
9393                      "connector's staged encoder doesn't match current encoder\n");
9394         }
9395 }
9396
9397 static void
9398 check_encoder_state(struct drm_device *dev)
9399 {
9400         struct intel_encoder *encoder;
9401         struct intel_connector *connector;
9402
9403         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9404                             base.head) {
9405                 bool enabled = false;
9406                 bool active = false;
9407                 enum pipe pipe, tracked_pipe;
9408
9409                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9410                               encoder->base.base.id,
9411                               drm_get_encoder_name(&encoder->base));
9412
9413                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9414                      "encoder's stage crtc doesn't match current crtc\n");
9415                 WARN(encoder->connectors_active && !encoder->base.crtc,
9416                      "encoder's active_connectors set, but no crtc\n");
9417
9418                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9419                                     base.head) {
9420                         if (connector->base.encoder != &encoder->base)
9421                                 continue;
9422                         enabled = true;
9423                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9424                                 active = true;
9425                 }
9426                 WARN(!!encoder->base.crtc != enabled,
9427                      "encoder's enabled state mismatch "
9428                      "(expected %i, found %i)\n",
9429                      !!encoder->base.crtc, enabled);
9430                 WARN(active && !encoder->base.crtc,
9431                      "active encoder with no crtc\n");
9432
9433                 WARN(encoder->connectors_active != active,
9434                      "encoder's computed active state doesn't match tracked active state "
9435                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9436
9437                 active = encoder->get_hw_state(encoder, &pipe);
9438                 WARN(active != encoder->connectors_active,
9439                      "encoder's hw state doesn't match sw tracking "
9440                      "(expected %i, found %i)\n",
9441                      encoder->connectors_active, active);
9442
9443                 if (!encoder->base.crtc)
9444                         continue;
9445
9446                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9447                 WARN(active && pipe != tracked_pipe,
9448                      "active encoder's pipe doesn't match"
9449                      "(expected %i, found %i)\n",
9450                      tracked_pipe, pipe);
9451
9452         }
9453 }
9454
9455 static void
9456 check_crtc_state(struct drm_device *dev)
9457 {
9458         drm_i915_private_t *dev_priv = dev->dev_private;
9459         struct intel_crtc *crtc;
9460         struct intel_encoder *encoder;
9461         struct intel_crtc_config pipe_config;
9462
9463         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9464                             base.head) {
9465                 bool enabled = false;
9466                 bool active = false;
9467
9468                 memset(&pipe_config, 0, sizeof(pipe_config));
9469
9470                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9471                               crtc->base.base.id);
9472
9473                 WARN(crtc->active && !crtc->base.enabled,
9474                      "active crtc, but not enabled in sw tracking\n");
9475
9476                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9477                                     base.head) {
9478                         if (encoder->base.crtc != &crtc->base)
9479                                 continue;
9480                         enabled = true;
9481                         if (encoder->connectors_active)
9482                                 active = true;
9483                 }
9484
9485                 WARN(active != crtc->active,
9486                      "crtc's computed active state doesn't match tracked active state "
9487                      "(expected %i, found %i)\n", active, crtc->active);
9488                 WARN(enabled != crtc->base.enabled,
9489                      "crtc's computed enabled state doesn't match tracked enabled state "
9490                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9491
9492                 active = dev_priv->display.get_pipe_config(crtc,
9493                                                            &pipe_config);
9494
9495                 /* hw state is inconsistent with the pipe A quirk */
9496                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9497                         active = crtc->active;
9498
9499                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9500                                     base.head) {
9501                         enum pipe pipe;
9502                         if (encoder->base.crtc != &crtc->base)
9503                                 continue;
9504                         if (encoder->get_hw_state(encoder, &pipe))
9505                                 encoder->get_config(encoder, &pipe_config);
9506                 }
9507
9508                 WARN(crtc->active != active,
9509                      "crtc active state doesn't match with hw state "
9510                      "(expected %i, found %i)\n", crtc->active, active);
9511
9512                 if (active &&
9513                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9514                         WARN(1, "pipe state doesn't match!\n");
9515                         intel_dump_pipe_config(crtc, &pipe_config,
9516                                                "[hw state]");
9517                         intel_dump_pipe_config(crtc, &crtc->config,
9518                                                "[sw state]");
9519                 }
9520         }
9521 }
9522
9523 static void
9524 check_shared_dpll_state(struct drm_device *dev)
9525 {
9526         drm_i915_private_t *dev_priv = dev->dev_private;
9527         struct intel_crtc *crtc;
9528         struct intel_dpll_hw_state dpll_hw_state;
9529         int i;
9530
9531         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9532                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9533                 int enabled_crtcs = 0, active_crtcs = 0;
9534                 bool active;
9535
9536                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9537
9538                 DRM_DEBUG_KMS("%s\n", pll->name);
9539
9540                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9541
9542                 WARN(pll->active > pll->refcount,
9543                      "more active pll users than references: %i vs %i\n",
9544                      pll->active, pll->refcount);
9545                 WARN(pll->active && !pll->on,
9546                      "pll in active use but not on in sw tracking\n");
9547                 WARN(pll->on && !pll->active,
9548                      "pll in on but not on in use in sw tracking\n");
9549                 WARN(pll->on != active,
9550                      "pll on state mismatch (expected %i, found %i)\n",
9551                      pll->on, active);
9552
9553                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9554                                     base.head) {
9555                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9556                                 enabled_crtcs++;
9557                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9558                                 active_crtcs++;
9559                 }
9560                 WARN(pll->active != active_crtcs,
9561                      "pll active crtcs mismatch (expected %i, found %i)\n",
9562                      pll->active, active_crtcs);
9563                 WARN(pll->refcount != enabled_crtcs,
9564                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9565                      pll->refcount, enabled_crtcs);
9566
9567                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9568                                        sizeof(dpll_hw_state)),
9569                      "pll hw state mismatch\n");
9570         }
9571 }
9572
9573 void
9574 intel_modeset_check_state(struct drm_device *dev)
9575 {
9576         check_connector_state(dev);
9577         check_encoder_state(dev);
9578         check_crtc_state(dev);
9579         check_shared_dpll_state(dev);
9580 }
9581
9582 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9583                                      int dotclock)
9584 {
9585         /*
9586          * FDI already provided one idea for the dotclock.
9587          * Yell if the encoder disagrees.
9588          */
9589         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9590              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9591              pipe_config->adjusted_mode.crtc_clock, dotclock);
9592 }
9593
9594 static int __intel_set_mode(struct drm_crtc *crtc,
9595                             struct drm_display_mode *mode,
9596                             int x, int y, struct drm_framebuffer *fb)
9597 {
9598         struct drm_device *dev = crtc->dev;
9599         drm_i915_private_t *dev_priv = dev->dev_private;
9600         struct drm_display_mode *saved_mode;
9601         struct intel_crtc_config *pipe_config = NULL;
9602         struct intel_crtc *intel_crtc;
9603         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9604         int ret = 0;
9605
9606         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9607         if (!saved_mode)
9608                 return -ENOMEM;
9609
9610         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9611                                      &prepare_pipes, &disable_pipes);
9612
9613         *saved_mode = crtc->mode;
9614
9615         /* Hack: Because we don't (yet) support global modeset on multiple
9616          * crtcs, we don't keep track of the new mode for more than one crtc.
9617          * Hence simply check whether any bit is set in modeset_pipes in all the
9618          * pieces of code that are not yet converted to deal with mutliple crtcs
9619          * changing their mode at the same time. */
9620         if (modeset_pipes) {
9621                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9622                 if (IS_ERR(pipe_config)) {
9623                         ret = PTR_ERR(pipe_config);
9624                         pipe_config = NULL;
9625
9626                         goto out;
9627                 }
9628                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9629                                        "[modeset]");
9630         }
9631
9632         /*
9633          * See if the config requires any additional preparation, e.g.
9634          * to adjust global state with pipes off.  We need to do this
9635          * here so we can get the modeset_pipe updated config for the new
9636          * mode set on this crtc.  For other crtcs we need to use the
9637          * adjusted_mode bits in the crtc directly.
9638          */
9639         if (IS_VALLEYVIEW(dev)) {
9640                 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9641                                                 modeset_pipes, pipe_config);
9642
9643                 /* may have added more to prepare_pipes than we should */
9644                 prepare_pipes &= ~disable_pipes;
9645         }
9646
9647         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9648                 intel_crtc_disable(&intel_crtc->base);
9649
9650         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9651                 if (intel_crtc->base.enabled)
9652                         dev_priv->display.crtc_disable(&intel_crtc->base);
9653         }
9654
9655         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9656          * to set it here already despite that we pass it down the callchain.
9657          */
9658         if (modeset_pipes) {
9659                 crtc->mode = *mode;
9660                 /* mode_set/enable/disable functions rely on a correct pipe
9661                  * config. */
9662                 to_intel_crtc(crtc)->config = *pipe_config;
9663
9664                 /*
9665                  * Calculate and store various constants which
9666                  * are later needed by vblank and swap-completion
9667                  * timestamping. They are derived from true hwmode.
9668                  */
9669                 drm_calc_timestamping_constants(crtc,
9670                                                 &pipe_config->adjusted_mode);
9671         }
9672
9673         /* Only after disabling all output pipelines that will be changed can we
9674          * update the the output configuration. */
9675         intel_modeset_update_state(dev, prepare_pipes);
9676
9677         if (dev_priv->display.modeset_global_resources)
9678                 dev_priv->display.modeset_global_resources(dev);
9679
9680         /* Set up the DPLL and any encoders state that needs to adjust or depend
9681          * on the DPLL.
9682          */
9683         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9684                 ret = intel_crtc_mode_set(&intel_crtc->base,
9685                                           x, y, fb);
9686                 if (ret)
9687                         goto done;
9688         }
9689
9690         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9691         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9692                 dev_priv->display.crtc_enable(&intel_crtc->base);
9693
9694         /* FIXME: add subpixel order */
9695 done:
9696         if (ret && crtc->enabled)
9697                 crtc->mode = *saved_mode;
9698
9699 out:
9700         kfree(pipe_config);
9701         kfree(saved_mode);
9702         return ret;
9703 }
9704
9705 static int intel_set_mode(struct drm_crtc *crtc,
9706                           struct drm_display_mode *mode,
9707                           int x, int y, struct drm_framebuffer *fb)
9708 {
9709         int ret;
9710
9711         ret = __intel_set_mode(crtc, mode, x, y, fb);
9712
9713         if (ret == 0)
9714                 intel_modeset_check_state(crtc->dev);
9715
9716         return ret;
9717 }
9718
9719 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9720 {
9721         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9722 }
9723
9724 #undef for_each_intel_crtc_masked
9725
9726 static void intel_set_config_free(struct intel_set_config *config)
9727 {
9728         if (!config)
9729                 return;
9730
9731         kfree(config->save_connector_encoders);
9732         kfree(config->save_encoder_crtcs);
9733         kfree(config);
9734 }
9735
9736 static int intel_set_config_save_state(struct drm_device *dev,
9737                                        struct intel_set_config *config)
9738 {
9739         struct drm_encoder *encoder;
9740         struct drm_connector *connector;
9741         int count;
9742
9743         config->save_encoder_crtcs =
9744                 kcalloc(dev->mode_config.num_encoder,
9745                         sizeof(struct drm_crtc *), GFP_KERNEL);
9746         if (!config->save_encoder_crtcs)
9747                 return -ENOMEM;
9748
9749         config->save_connector_encoders =
9750                 kcalloc(dev->mode_config.num_connector,
9751                         sizeof(struct drm_encoder *), GFP_KERNEL);
9752         if (!config->save_connector_encoders)
9753                 return -ENOMEM;
9754
9755         /* Copy data. Note that driver private data is not affected.
9756          * Should anything bad happen only the expected state is
9757          * restored, not the drivers personal bookkeeping.
9758          */
9759         count = 0;
9760         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9761                 config->save_encoder_crtcs[count++] = encoder->crtc;
9762         }
9763
9764         count = 0;
9765         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9766                 config->save_connector_encoders[count++] = connector->encoder;
9767         }
9768
9769         return 0;
9770 }
9771
9772 static void intel_set_config_restore_state(struct drm_device *dev,
9773                                            struct intel_set_config *config)
9774 {
9775         struct intel_encoder *encoder;
9776         struct intel_connector *connector;
9777         int count;
9778
9779         count = 0;
9780         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9781                 encoder->new_crtc =
9782                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9783         }
9784
9785         count = 0;
9786         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9787                 connector->new_encoder =
9788                         to_intel_encoder(config->save_connector_encoders[count++]);
9789         }
9790 }
9791
9792 static bool
9793 is_crtc_connector_off(struct drm_mode_set *set)
9794 {
9795         int i;
9796
9797         if (set->num_connectors == 0)
9798                 return false;
9799
9800         if (WARN_ON(set->connectors == NULL))
9801                 return false;
9802
9803         for (i = 0; i < set->num_connectors; i++)
9804                 if (set->connectors[i]->encoder &&
9805                     set->connectors[i]->encoder->crtc == set->crtc &&
9806                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9807                         return true;
9808
9809         return false;
9810 }
9811
9812 static void
9813 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9814                                       struct intel_set_config *config)
9815 {
9816
9817         /* We should be able to check here if the fb has the same properties
9818          * and then just flip_or_move it */
9819         if (is_crtc_connector_off(set)) {
9820                 config->mode_changed = true;
9821         } else if (set->crtc->fb != set->fb) {
9822                 /* If we have no fb then treat it as a full mode set */
9823                 if (set->crtc->fb == NULL) {
9824                         struct intel_crtc *intel_crtc =
9825                                 to_intel_crtc(set->crtc);
9826
9827                         if (intel_crtc->active && i915_fastboot) {
9828                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9829                                 config->fb_changed = true;
9830                         } else {
9831                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9832                                 config->mode_changed = true;
9833                         }
9834                 } else if (set->fb == NULL) {
9835                         config->mode_changed = true;
9836                 } else if (set->fb->pixel_format !=
9837                            set->crtc->fb->pixel_format) {
9838                         config->mode_changed = true;
9839                 } else {
9840                         config->fb_changed = true;
9841                 }
9842         }
9843
9844         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9845                 config->fb_changed = true;
9846
9847         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9848                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9849                 drm_mode_debug_printmodeline(&set->crtc->mode);
9850                 drm_mode_debug_printmodeline(set->mode);
9851                 config->mode_changed = true;
9852         }
9853
9854         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9855                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9856 }
9857
9858 static int
9859 intel_modeset_stage_output_state(struct drm_device *dev,
9860                                  struct drm_mode_set *set,
9861                                  struct intel_set_config *config)
9862 {
9863         struct drm_crtc *new_crtc;
9864         struct intel_connector *connector;
9865         struct intel_encoder *encoder;
9866         int ro;
9867
9868         /* The upper layers ensure that we either disable a crtc or have a list
9869          * of connectors. For paranoia, double-check this. */
9870         WARN_ON(!set->fb && (set->num_connectors != 0));
9871         WARN_ON(set->fb && (set->num_connectors == 0));
9872
9873         list_for_each_entry(connector, &dev->mode_config.connector_list,
9874                             base.head) {
9875                 /* Otherwise traverse passed in connector list and get encoders
9876                  * for them. */
9877                 for (ro = 0; ro < set->num_connectors; ro++) {
9878                         if (set->connectors[ro] == &connector->base) {
9879                                 connector->new_encoder = connector->encoder;
9880                                 break;
9881                         }
9882                 }
9883
9884                 /* If we disable the crtc, disable all its connectors. Also, if
9885                  * the connector is on the changing crtc but not on the new
9886                  * connector list, disable it. */
9887                 if ((!set->fb || ro == set->num_connectors) &&
9888                     connector->base.encoder &&
9889                     connector->base.encoder->crtc == set->crtc) {
9890                         connector->new_encoder = NULL;
9891
9892                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9893                                 connector->base.base.id,
9894                                 drm_get_connector_name(&connector->base));
9895                 }
9896
9897
9898                 if (&connector->new_encoder->base != connector->base.encoder) {
9899                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9900                         config->mode_changed = true;
9901                 }
9902         }
9903         /* connector->new_encoder is now updated for all connectors. */
9904
9905         /* Update crtc of enabled connectors. */
9906         list_for_each_entry(connector, &dev->mode_config.connector_list,
9907                             base.head) {
9908                 if (!connector->new_encoder)
9909                         continue;
9910
9911                 new_crtc = connector->new_encoder->base.crtc;
9912
9913                 for (ro = 0; ro < set->num_connectors; ro++) {
9914                         if (set->connectors[ro] == &connector->base)
9915                                 new_crtc = set->crtc;
9916                 }
9917
9918                 /* Make sure the new CRTC will work with the encoder */
9919                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9920                                            new_crtc)) {
9921                         return -EINVAL;
9922                 }
9923                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9924
9925                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9926                         connector->base.base.id,
9927                         drm_get_connector_name(&connector->base),
9928                         new_crtc->base.id);
9929         }
9930
9931         /* Check for any encoders that needs to be disabled. */
9932         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9933                             base.head) {
9934                 int num_connectors = 0;
9935                 list_for_each_entry(connector,
9936                                     &dev->mode_config.connector_list,
9937                                     base.head) {
9938                         if (connector->new_encoder == encoder) {
9939                                 WARN_ON(!connector->new_encoder->new_crtc);
9940                                 num_connectors++;
9941                         }
9942                 }
9943
9944                 if (num_connectors == 0)
9945                         encoder->new_crtc = NULL;
9946                 else if (num_connectors > 1)
9947                         return -EINVAL;
9948
9949                 /* Only now check for crtc changes so we don't miss encoders
9950                  * that will be disabled. */
9951                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9952                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9953                         config->mode_changed = true;
9954                 }
9955         }
9956         /* Now we've also updated encoder->new_crtc for all encoders. */
9957
9958         return 0;
9959 }
9960
9961 static int intel_crtc_set_config(struct drm_mode_set *set)
9962 {
9963         struct drm_device *dev;
9964         struct drm_mode_set save_set;
9965         struct intel_set_config *config;
9966         int ret;
9967
9968         BUG_ON(!set);
9969         BUG_ON(!set->crtc);
9970         BUG_ON(!set->crtc->helper_private);
9971
9972         /* Enforce sane interface api - has been abused by the fb helper. */
9973         BUG_ON(!set->mode && set->fb);
9974         BUG_ON(set->fb && set->num_connectors == 0);
9975
9976         if (set->fb) {
9977                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9978                                 set->crtc->base.id, set->fb->base.id,
9979                                 (int)set->num_connectors, set->x, set->y);
9980         } else {
9981                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9982         }
9983
9984         dev = set->crtc->dev;
9985
9986         ret = -ENOMEM;
9987         config = kzalloc(sizeof(*config), GFP_KERNEL);
9988         if (!config)
9989                 goto out_config;
9990
9991         ret = intel_set_config_save_state(dev, config);
9992         if (ret)
9993                 goto out_config;
9994
9995         save_set.crtc = set->crtc;
9996         save_set.mode = &set->crtc->mode;
9997         save_set.x = set->crtc->x;
9998         save_set.y = set->crtc->y;
9999         save_set.fb = set->crtc->fb;
10000
10001         /* Compute whether we need a full modeset, only an fb base update or no
10002          * change at all. In the future we might also check whether only the
10003          * mode changed, e.g. for LVDS where we only change the panel fitter in
10004          * such cases. */
10005         intel_set_config_compute_mode_changes(set, config);
10006
10007         ret = intel_modeset_stage_output_state(dev, set, config);
10008         if (ret)
10009                 goto fail;
10010
10011         if (config->mode_changed) {
10012                 ret = intel_set_mode(set->crtc, set->mode,
10013                                      set->x, set->y, set->fb);
10014         } else if (config->fb_changed) {
10015                 intel_crtc_wait_for_pending_flips(set->crtc);
10016
10017                 ret = intel_pipe_set_base(set->crtc,
10018                                           set->x, set->y, set->fb);
10019                 /*
10020                  * In the fastboot case this may be our only check of the
10021                  * state after boot.  It would be better to only do it on
10022                  * the first update, but we don't have a nice way of doing that
10023                  * (and really, set_config isn't used much for high freq page
10024                  * flipping, so increasing its cost here shouldn't be a big
10025                  * deal).
10026                  */
10027                 if (i915_fastboot && ret == 0)
10028                         intel_modeset_check_state(set->crtc->dev);
10029         }
10030
10031         if (ret) {
10032                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10033                               set->crtc->base.id, ret);
10034 fail:
10035                 intel_set_config_restore_state(dev, config);
10036
10037                 /* Try to restore the config */
10038                 if (config->mode_changed &&
10039                     intel_set_mode(save_set.crtc, save_set.mode,
10040                                    save_set.x, save_set.y, save_set.fb))
10041                         DRM_ERROR("failed to restore config after modeset failure\n");
10042         }
10043
10044 out_config:
10045         intel_set_config_free(config);
10046         return ret;
10047 }
10048
10049 static const struct drm_crtc_funcs intel_crtc_funcs = {
10050         .cursor_set = intel_crtc_cursor_set,
10051         .cursor_move = intel_crtc_cursor_move,
10052         .gamma_set = intel_crtc_gamma_set,
10053         .set_config = intel_crtc_set_config,
10054         .destroy = intel_crtc_destroy,
10055         .page_flip = intel_crtc_page_flip,
10056 };
10057
10058 static void intel_cpu_pll_init(struct drm_device *dev)
10059 {
10060         if (HAS_DDI(dev))
10061                 intel_ddi_pll_init(dev);
10062 }
10063
10064 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10065                                       struct intel_shared_dpll *pll,
10066                                       struct intel_dpll_hw_state *hw_state)
10067 {
10068         uint32_t val;
10069
10070         val = I915_READ(PCH_DPLL(pll->id));
10071         hw_state->dpll = val;
10072         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10073         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10074
10075         return val & DPLL_VCO_ENABLE;
10076 }
10077
10078 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10079                                   struct intel_shared_dpll *pll)
10080 {
10081         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10082         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10083 }
10084
10085 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10086                                 struct intel_shared_dpll *pll)
10087 {
10088         /* PCH refclock must be enabled first */
10089         ibx_assert_pch_refclk_enabled(dev_priv);
10090
10091         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10092
10093         /* Wait for the clocks to stabilize. */
10094         POSTING_READ(PCH_DPLL(pll->id));
10095         udelay(150);
10096
10097         /* The pixel multiplier can only be updated once the
10098          * DPLL is enabled and the clocks are stable.
10099          *
10100          * So write it again.
10101          */
10102         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10103         POSTING_READ(PCH_DPLL(pll->id));
10104         udelay(200);
10105 }
10106
10107 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10108                                  struct intel_shared_dpll *pll)
10109 {
10110         struct drm_device *dev = dev_priv->dev;
10111         struct intel_crtc *crtc;
10112
10113         /* Make sure no transcoder isn't still depending on us. */
10114         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10115                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10116                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10117         }
10118
10119         I915_WRITE(PCH_DPLL(pll->id), 0);
10120         POSTING_READ(PCH_DPLL(pll->id));
10121         udelay(200);
10122 }
10123
10124 static char *ibx_pch_dpll_names[] = {
10125         "PCH DPLL A",
10126         "PCH DPLL B",
10127 };
10128
10129 static void ibx_pch_dpll_init(struct drm_device *dev)
10130 {
10131         struct drm_i915_private *dev_priv = dev->dev_private;
10132         int i;
10133
10134         dev_priv->num_shared_dpll = 2;
10135
10136         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10137                 dev_priv->shared_dplls[i].id = i;
10138                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10139                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10140                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10141                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10142                 dev_priv->shared_dplls[i].get_hw_state =
10143                         ibx_pch_dpll_get_hw_state;
10144         }
10145 }
10146
10147 static void intel_shared_dpll_init(struct drm_device *dev)
10148 {
10149         struct drm_i915_private *dev_priv = dev->dev_private;
10150
10151         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10152                 ibx_pch_dpll_init(dev);
10153         else
10154                 dev_priv->num_shared_dpll = 0;
10155
10156         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10157 }
10158
10159 static void intel_crtc_init(struct drm_device *dev, int pipe)
10160 {
10161         drm_i915_private_t *dev_priv = dev->dev_private;
10162         struct intel_crtc *intel_crtc;
10163         int i;
10164
10165         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10166         if (intel_crtc == NULL)
10167                 return;
10168
10169         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10170
10171         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10172         for (i = 0; i < 256; i++) {
10173                 intel_crtc->lut_r[i] = i;
10174                 intel_crtc->lut_g[i] = i;
10175                 intel_crtc->lut_b[i] = i;
10176         }
10177
10178         /*
10179          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10180          * is hooked to plane B. Hence we want plane A feeding pipe B.
10181          */
10182         intel_crtc->pipe = pipe;
10183         intel_crtc->plane = pipe;
10184         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10185                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10186                 intel_crtc->plane = !pipe;
10187         }
10188
10189         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10190                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10191         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10192         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10193
10194         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10195 }
10196
10197 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10198 {
10199         struct drm_encoder *encoder = connector->base.encoder;
10200
10201         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10202
10203         if (!encoder)
10204                 return INVALID_PIPE;
10205
10206         return to_intel_crtc(encoder->crtc)->pipe;
10207 }
10208
10209 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10210                                 struct drm_file *file)
10211 {
10212         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10213         struct drm_mode_object *drmmode_obj;
10214         struct intel_crtc *crtc;
10215
10216         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10217                 return -ENODEV;
10218
10219         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10220                         DRM_MODE_OBJECT_CRTC);
10221
10222         if (!drmmode_obj) {
10223                 DRM_ERROR("no such CRTC id\n");
10224                 return -ENOENT;
10225         }
10226
10227         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10228         pipe_from_crtc_id->pipe = crtc->pipe;
10229
10230         return 0;
10231 }
10232
10233 static int intel_encoder_clones(struct intel_encoder *encoder)
10234 {
10235         struct drm_device *dev = encoder->base.dev;
10236         struct intel_encoder *source_encoder;
10237         int index_mask = 0;
10238         int entry = 0;
10239
10240         list_for_each_entry(source_encoder,
10241                             &dev->mode_config.encoder_list, base.head) {
10242
10243                 if (encoder == source_encoder)
10244                         index_mask |= (1 << entry);
10245
10246                 /* Intel hw has only one MUX where enocoders could be cloned. */
10247                 if (encoder->cloneable && source_encoder->cloneable)
10248                         index_mask |= (1 << entry);
10249
10250                 entry++;
10251         }
10252
10253         return index_mask;
10254 }
10255
10256 static bool has_edp_a(struct drm_device *dev)
10257 {
10258         struct drm_i915_private *dev_priv = dev->dev_private;
10259
10260         if (!IS_MOBILE(dev))
10261                 return false;
10262
10263         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10264                 return false;
10265
10266         if (IS_GEN5(dev) &&
10267             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10268                 return false;
10269
10270         return true;
10271 }
10272
10273 const char *intel_output_name(int output)
10274 {
10275         static const char *names[] = {
10276                 [INTEL_OUTPUT_UNUSED] = "Unused",
10277                 [INTEL_OUTPUT_ANALOG] = "Analog",
10278                 [INTEL_OUTPUT_DVO] = "DVO",
10279                 [INTEL_OUTPUT_SDVO] = "SDVO",
10280                 [INTEL_OUTPUT_LVDS] = "LVDS",
10281                 [INTEL_OUTPUT_TVOUT] = "TV",
10282                 [INTEL_OUTPUT_HDMI] = "HDMI",
10283                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10284                 [INTEL_OUTPUT_EDP] = "eDP",
10285                 [INTEL_OUTPUT_DSI] = "DSI",
10286                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10287         };
10288
10289         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10290                 return "Invalid";
10291
10292         return names[output];
10293 }
10294
10295 static void intel_setup_outputs(struct drm_device *dev)
10296 {
10297         struct drm_i915_private *dev_priv = dev->dev_private;
10298         struct intel_encoder *encoder;
10299         bool dpd_is_edp = false;
10300
10301         intel_lvds_init(dev);
10302
10303         if (!IS_ULT(dev))
10304                 intel_crt_init(dev);
10305
10306         if (HAS_DDI(dev)) {
10307                 int found;
10308
10309                 /* Haswell uses DDI functions to detect digital outputs */
10310                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10311                 /* DDI A only supports eDP */
10312                 if (found)
10313                         intel_ddi_init(dev, PORT_A);
10314
10315                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10316                  * register */
10317                 found = I915_READ(SFUSE_STRAP);
10318
10319                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10320                         intel_ddi_init(dev, PORT_B);
10321                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10322                         intel_ddi_init(dev, PORT_C);
10323                 if (found & SFUSE_STRAP_DDID_DETECTED)
10324                         intel_ddi_init(dev, PORT_D);
10325         } else if (HAS_PCH_SPLIT(dev)) {
10326                 int found;
10327                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10328
10329                 if (has_edp_a(dev))
10330                         intel_dp_init(dev, DP_A, PORT_A);
10331
10332                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10333                         /* PCH SDVOB multiplex with HDMIB */
10334                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10335                         if (!found)
10336                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10337                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10338                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10339                 }
10340
10341                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10342                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10343
10344                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10345                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10346
10347                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10348                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10349
10350                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10351                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10352         } else if (IS_VALLEYVIEW(dev)) {
10353                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10354                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10355                                         PORT_B);
10356                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10357                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10358                 }
10359
10360                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10361                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10362                                         PORT_C);
10363                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10364                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10365                 }
10366
10367                 intel_dsi_init(dev);
10368         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10369                 bool found = false;
10370
10371                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10372                         DRM_DEBUG_KMS("probing SDVOB\n");
10373                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10374                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10375                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10376                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10377                         }
10378
10379                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10380                                 intel_dp_init(dev, DP_B, PORT_B);
10381                 }
10382
10383                 /* Before G4X SDVOC doesn't have its own detect register */
10384
10385                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10386                         DRM_DEBUG_KMS("probing SDVOC\n");
10387                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10388                 }
10389
10390                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10391
10392                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10393                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10394                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10395                         }
10396                         if (SUPPORTS_INTEGRATED_DP(dev))
10397                                 intel_dp_init(dev, DP_C, PORT_C);
10398                 }
10399
10400                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10401                     (I915_READ(DP_D) & DP_DETECTED))
10402                         intel_dp_init(dev, DP_D, PORT_D);
10403         } else if (IS_GEN2(dev))
10404                 intel_dvo_init(dev);
10405
10406         if (SUPPORTS_TV(dev))
10407                 intel_tv_init(dev);
10408
10409         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10410                 encoder->base.possible_crtcs = encoder->crtc_mask;
10411                 encoder->base.possible_clones =
10412                         intel_encoder_clones(encoder);
10413         }
10414
10415         intel_init_pch_refclk(dev);
10416
10417         drm_helper_move_panel_connectors_to_head(dev);
10418 }
10419
10420 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10421 {
10422         drm_framebuffer_cleanup(&fb->base);
10423         WARN_ON(!fb->obj->framebuffer_references--);
10424         drm_gem_object_unreference_unlocked(&fb->obj->base);
10425 }
10426
10427 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10428 {
10429         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10430
10431         intel_framebuffer_fini(intel_fb);
10432         kfree(intel_fb);
10433 }
10434
10435 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10436                                                 struct drm_file *file,
10437                                                 unsigned int *handle)
10438 {
10439         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10440         struct drm_i915_gem_object *obj = intel_fb->obj;
10441
10442         return drm_gem_handle_create(file, &obj->base, handle);
10443 }
10444
10445 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10446         .destroy = intel_user_framebuffer_destroy,
10447         .create_handle = intel_user_framebuffer_create_handle,
10448 };
10449
10450 int intel_framebuffer_init(struct drm_device *dev,
10451                            struct intel_framebuffer *intel_fb,
10452                            struct drm_mode_fb_cmd2 *mode_cmd,
10453                            struct drm_i915_gem_object *obj)
10454 {
10455         int aligned_height, tile_height;
10456         int pitch_limit;
10457         int ret;
10458
10459         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10460
10461         if (obj->tiling_mode == I915_TILING_Y) {
10462                 DRM_DEBUG("hardware does not support tiling Y\n");
10463                 return -EINVAL;
10464         }
10465
10466         if (mode_cmd->pitches[0] & 63) {
10467                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10468                           mode_cmd->pitches[0]);
10469                 return -EINVAL;
10470         }
10471
10472         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10473                 pitch_limit = 32*1024;
10474         } else if (INTEL_INFO(dev)->gen >= 4) {
10475                 if (obj->tiling_mode)
10476                         pitch_limit = 16*1024;
10477                 else
10478                         pitch_limit = 32*1024;
10479         } else if (INTEL_INFO(dev)->gen >= 3) {
10480                 if (obj->tiling_mode)
10481                         pitch_limit = 8*1024;
10482                 else
10483                         pitch_limit = 16*1024;
10484         } else
10485                 /* XXX DSPC is limited to 4k tiled */
10486                 pitch_limit = 8*1024;
10487
10488         if (mode_cmd->pitches[0] > pitch_limit) {
10489                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10490                           obj->tiling_mode ? "tiled" : "linear",
10491                           mode_cmd->pitches[0], pitch_limit);
10492                 return -EINVAL;
10493         }
10494
10495         if (obj->tiling_mode != I915_TILING_NONE &&
10496             mode_cmd->pitches[0] != obj->stride) {
10497                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10498                           mode_cmd->pitches[0], obj->stride);
10499                 return -EINVAL;
10500         }
10501
10502         /* Reject formats not supported by any plane early. */
10503         switch (mode_cmd->pixel_format) {
10504         case DRM_FORMAT_C8:
10505         case DRM_FORMAT_RGB565:
10506         case DRM_FORMAT_XRGB8888:
10507         case DRM_FORMAT_ARGB8888:
10508                 break;
10509         case DRM_FORMAT_XRGB1555:
10510         case DRM_FORMAT_ARGB1555:
10511                 if (INTEL_INFO(dev)->gen > 3) {
10512                         DRM_DEBUG("unsupported pixel format: %s\n",
10513                                   drm_get_format_name(mode_cmd->pixel_format));
10514                         return -EINVAL;
10515                 }
10516                 break;
10517         case DRM_FORMAT_XBGR8888:
10518         case DRM_FORMAT_ABGR8888:
10519         case DRM_FORMAT_XRGB2101010:
10520         case DRM_FORMAT_ARGB2101010:
10521         case DRM_FORMAT_XBGR2101010:
10522         case DRM_FORMAT_ABGR2101010:
10523                 if (INTEL_INFO(dev)->gen < 4) {
10524                         DRM_DEBUG("unsupported pixel format: %s\n",
10525                                   drm_get_format_name(mode_cmd->pixel_format));
10526                         return -EINVAL;
10527                 }
10528                 break;
10529         case DRM_FORMAT_YUYV:
10530         case DRM_FORMAT_UYVY:
10531         case DRM_FORMAT_YVYU:
10532         case DRM_FORMAT_VYUY:
10533                 if (INTEL_INFO(dev)->gen < 5) {
10534                         DRM_DEBUG("unsupported pixel format: %s\n",
10535                                   drm_get_format_name(mode_cmd->pixel_format));
10536                         return -EINVAL;
10537                 }
10538                 break;
10539         default:
10540                 DRM_DEBUG("unsupported pixel format: %s\n",
10541                           drm_get_format_name(mode_cmd->pixel_format));
10542                 return -EINVAL;
10543         }
10544
10545         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10546         if (mode_cmd->offsets[0] != 0)
10547                 return -EINVAL;
10548
10549         tile_height = IS_GEN2(dev) ? 16 : 8;
10550         aligned_height = ALIGN(mode_cmd->height,
10551                                obj->tiling_mode ? tile_height : 1);
10552         /* FIXME drm helper for size checks (especially planar formats)? */
10553         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10554                 return -EINVAL;
10555
10556         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10557         intel_fb->obj = obj;
10558         intel_fb->obj->framebuffer_references++;
10559
10560         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10561         if (ret) {
10562                 DRM_ERROR("framebuffer init failed %d\n", ret);
10563                 return ret;
10564         }
10565
10566         return 0;
10567 }
10568
10569 static struct drm_framebuffer *
10570 intel_user_framebuffer_create(struct drm_device *dev,
10571                               struct drm_file *filp,
10572                               struct drm_mode_fb_cmd2 *mode_cmd)
10573 {
10574         struct drm_i915_gem_object *obj;
10575
10576         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10577                                                 mode_cmd->handles[0]));
10578         if (&obj->base == NULL)
10579                 return ERR_PTR(-ENOENT);
10580
10581         return intel_framebuffer_create(dev, mode_cmd, obj);
10582 }
10583
10584 #ifndef CONFIG_DRM_I915_FBDEV
10585 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10586 {
10587 }
10588 #endif
10589
10590 static const struct drm_mode_config_funcs intel_mode_funcs = {
10591         .fb_create = intel_user_framebuffer_create,
10592         .output_poll_changed = intel_fbdev_output_poll_changed,
10593 };
10594
10595 /* Set up chip specific display functions */
10596 static void intel_init_display(struct drm_device *dev)
10597 {
10598         struct drm_i915_private *dev_priv = dev->dev_private;
10599
10600         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10601                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10602         else if (IS_VALLEYVIEW(dev))
10603                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10604         else if (IS_PINEVIEW(dev))
10605                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10606         else
10607                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10608
10609         if (HAS_DDI(dev)) {
10610                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10611                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10612                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10613                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10614                 dev_priv->display.off = haswell_crtc_off;
10615                 dev_priv->display.update_plane = ironlake_update_plane;
10616         } else if (HAS_PCH_SPLIT(dev)) {
10617                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10618                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10619                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10620                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10621                 dev_priv->display.off = ironlake_crtc_off;
10622                 dev_priv->display.update_plane = ironlake_update_plane;
10623         } else if (IS_VALLEYVIEW(dev)) {
10624                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10625                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10626                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10627                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10628                 dev_priv->display.off = i9xx_crtc_off;
10629                 dev_priv->display.update_plane = i9xx_update_plane;
10630         } else {
10631                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10632                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10633                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10634                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10635                 dev_priv->display.off = i9xx_crtc_off;
10636                 dev_priv->display.update_plane = i9xx_update_plane;
10637         }
10638
10639         /* Returns the core display clock speed */
10640         if (IS_VALLEYVIEW(dev))
10641                 dev_priv->display.get_display_clock_speed =
10642                         valleyview_get_display_clock_speed;
10643         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10644                 dev_priv->display.get_display_clock_speed =
10645                         i945_get_display_clock_speed;
10646         else if (IS_I915G(dev))
10647                 dev_priv->display.get_display_clock_speed =
10648                         i915_get_display_clock_speed;
10649         else if (IS_I945GM(dev) || IS_845G(dev))
10650                 dev_priv->display.get_display_clock_speed =
10651                         i9xx_misc_get_display_clock_speed;
10652         else if (IS_PINEVIEW(dev))
10653                 dev_priv->display.get_display_clock_speed =
10654                         pnv_get_display_clock_speed;
10655         else if (IS_I915GM(dev))
10656                 dev_priv->display.get_display_clock_speed =
10657                         i915gm_get_display_clock_speed;
10658         else if (IS_I865G(dev))
10659                 dev_priv->display.get_display_clock_speed =
10660                         i865_get_display_clock_speed;
10661         else if (IS_I85X(dev))
10662                 dev_priv->display.get_display_clock_speed =
10663                         i855_get_display_clock_speed;
10664         else /* 852, 830 */
10665                 dev_priv->display.get_display_clock_speed =
10666                         i830_get_display_clock_speed;
10667
10668         if (HAS_PCH_SPLIT(dev)) {
10669                 if (IS_GEN5(dev)) {
10670                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10671                         dev_priv->display.write_eld = ironlake_write_eld;
10672                 } else if (IS_GEN6(dev)) {
10673                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10674                         dev_priv->display.write_eld = ironlake_write_eld;
10675                 } else if (IS_IVYBRIDGE(dev)) {
10676                         /* FIXME: detect B0+ stepping and use auto training */
10677                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10678                         dev_priv->display.write_eld = ironlake_write_eld;
10679                         dev_priv->display.modeset_global_resources =
10680                                 ivb_modeset_global_resources;
10681                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10682                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10683                         dev_priv->display.write_eld = haswell_write_eld;
10684                         dev_priv->display.modeset_global_resources =
10685                                 haswell_modeset_global_resources;
10686                 }
10687         } else if (IS_G4X(dev)) {
10688                 dev_priv->display.write_eld = g4x_write_eld;
10689         } else if (IS_VALLEYVIEW(dev)) {
10690                 dev_priv->display.modeset_global_resources =
10691                         valleyview_modeset_global_resources;
10692                 dev_priv->display.write_eld = ironlake_write_eld;
10693         }
10694
10695         /* Default just returns -ENODEV to indicate unsupported */
10696         dev_priv->display.queue_flip = intel_default_queue_flip;
10697
10698         switch (INTEL_INFO(dev)->gen) {
10699         case 2:
10700                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10701                 break;
10702
10703         case 3:
10704                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10705                 break;
10706
10707         case 4:
10708         case 5:
10709                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10710                 break;
10711
10712         case 6:
10713                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10714                 break;
10715         case 7:
10716         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10717                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10718                 break;
10719         }
10720
10721         intel_panel_init_backlight_funcs(dev);
10722 }
10723
10724 /*
10725  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10726  * resume, or other times.  This quirk makes sure that's the case for
10727  * affected systems.
10728  */
10729 static void quirk_pipea_force(struct drm_device *dev)
10730 {
10731         struct drm_i915_private *dev_priv = dev->dev_private;
10732
10733         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10734         DRM_INFO("applying pipe a force quirk\n");
10735 }
10736
10737 /*
10738  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10739  */
10740 static void quirk_ssc_force_disable(struct drm_device *dev)
10741 {
10742         struct drm_i915_private *dev_priv = dev->dev_private;
10743         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10744         DRM_INFO("applying lvds SSC disable quirk\n");
10745 }
10746
10747 /*
10748  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10749  * brightness value
10750  */
10751 static void quirk_invert_brightness(struct drm_device *dev)
10752 {
10753         struct drm_i915_private *dev_priv = dev->dev_private;
10754         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10755         DRM_INFO("applying inverted panel brightness quirk\n");
10756 }
10757
10758 struct intel_quirk {
10759         int device;
10760         int subsystem_vendor;
10761         int subsystem_device;
10762         void (*hook)(struct drm_device *dev);
10763 };
10764
10765 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10766 struct intel_dmi_quirk {
10767         void (*hook)(struct drm_device *dev);
10768         const struct dmi_system_id (*dmi_id_list)[];
10769 };
10770
10771 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10772 {
10773         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10774         return 1;
10775 }
10776
10777 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10778         {
10779                 .dmi_id_list = &(const struct dmi_system_id[]) {
10780                         {
10781                                 .callback = intel_dmi_reverse_brightness,
10782                                 .ident = "NCR Corporation",
10783                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10784                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10785                                 },
10786                         },
10787                         { }  /* terminating entry */
10788                 },
10789                 .hook = quirk_invert_brightness,
10790         },
10791 };
10792
10793 static struct intel_quirk intel_quirks[] = {
10794         /* HP Mini needs pipe A force quirk (LP: #322104) */
10795         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10796
10797         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10798         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10799
10800         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10801         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10802
10803         /* 830 needs to leave pipe A & dpll A up */
10804         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10805
10806         /* Lenovo U160 cannot use SSC on LVDS */
10807         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10808
10809         /* Sony Vaio Y cannot use SSC on LVDS */
10810         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10811
10812         /* Acer Aspire 5734Z must invert backlight brightness */
10813         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10814
10815         /* Acer/eMachines G725 */
10816         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10817
10818         /* Acer/eMachines e725 */
10819         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10820
10821         /* Acer/Packard Bell NCL20 */
10822         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10823
10824         /* Acer Aspire 4736Z */
10825         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10826 };
10827
10828 static void intel_init_quirks(struct drm_device *dev)
10829 {
10830         struct pci_dev *d = dev->pdev;
10831         int i;
10832
10833         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10834                 struct intel_quirk *q = &intel_quirks[i];
10835
10836                 if (d->device == q->device &&
10837                     (d->subsystem_vendor == q->subsystem_vendor ||
10838                      q->subsystem_vendor == PCI_ANY_ID) &&
10839                     (d->subsystem_device == q->subsystem_device ||
10840                      q->subsystem_device == PCI_ANY_ID))
10841                         q->hook(dev);
10842         }
10843         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10844                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10845                         intel_dmi_quirks[i].hook(dev);
10846         }
10847 }
10848
10849 /* Disable the VGA plane that we never use */
10850 static void i915_disable_vga(struct drm_device *dev)
10851 {
10852         struct drm_i915_private *dev_priv = dev->dev_private;
10853         u8 sr1;
10854         u32 vga_reg = i915_vgacntrl_reg(dev);
10855
10856         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10857         outb(SR01, VGA_SR_INDEX);
10858         sr1 = inb(VGA_SR_DATA);
10859         outb(sr1 | 1<<5, VGA_SR_DATA);
10860         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10861         udelay(300);
10862
10863         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10864         POSTING_READ(vga_reg);
10865 }
10866
10867 void intel_modeset_init_hw(struct drm_device *dev)
10868 {
10869         intel_prepare_ddi(dev);
10870
10871         intel_init_clock_gating(dev);
10872
10873         intel_reset_dpio(dev);
10874
10875         mutex_lock(&dev->struct_mutex);
10876         intel_enable_gt_powersave(dev);
10877         mutex_unlock(&dev->struct_mutex);
10878 }
10879
10880 void intel_modeset_suspend_hw(struct drm_device *dev)
10881 {
10882         intel_suspend_hw(dev);
10883 }
10884
10885 void intel_modeset_init(struct drm_device *dev)
10886 {
10887         struct drm_i915_private *dev_priv = dev->dev_private;
10888         int i, j, ret;
10889
10890         drm_mode_config_init(dev);
10891
10892         dev->mode_config.min_width = 0;
10893         dev->mode_config.min_height = 0;
10894
10895         dev->mode_config.preferred_depth = 24;
10896         dev->mode_config.prefer_shadow = 1;
10897
10898         dev->mode_config.funcs = &intel_mode_funcs;
10899
10900         intel_init_quirks(dev);
10901
10902         intel_init_pm(dev);
10903
10904         if (INTEL_INFO(dev)->num_pipes == 0)
10905                 return;
10906
10907         intel_init_display(dev);
10908
10909         if (IS_GEN2(dev)) {
10910                 dev->mode_config.max_width = 2048;
10911                 dev->mode_config.max_height = 2048;
10912         } else if (IS_GEN3(dev)) {
10913                 dev->mode_config.max_width = 4096;
10914                 dev->mode_config.max_height = 4096;
10915         } else {
10916                 dev->mode_config.max_width = 8192;
10917                 dev->mode_config.max_height = 8192;
10918         }
10919         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10920
10921         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10922                       INTEL_INFO(dev)->num_pipes,
10923                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10924
10925         for_each_pipe(i) {
10926                 intel_crtc_init(dev, i);
10927                 for (j = 0; j < dev_priv->num_plane; j++) {
10928                         ret = intel_plane_init(dev, i, j);
10929                         if (ret)
10930                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10931                                               pipe_name(i), sprite_name(i, j), ret);
10932                 }
10933         }
10934
10935         intel_init_dpio(dev);
10936         intel_reset_dpio(dev);
10937
10938         intel_cpu_pll_init(dev);
10939         intel_shared_dpll_init(dev);
10940
10941         /* Just disable it once at startup */
10942         i915_disable_vga(dev);
10943         intel_setup_outputs(dev);
10944
10945         /* Just in case the BIOS is doing something questionable. */
10946         intel_disable_fbc(dev);
10947 }
10948
10949 static void
10950 intel_connector_break_all_links(struct intel_connector *connector)
10951 {
10952         connector->base.dpms = DRM_MODE_DPMS_OFF;
10953         connector->base.encoder = NULL;
10954         connector->encoder->connectors_active = false;
10955         connector->encoder->base.crtc = NULL;
10956 }
10957
10958 static void intel_enable_pipe_a(struct drm_device *dev)
10959 {
10960         struct intel_connector *connector;
10961         struct drm_connector *crt = NULL;
10962         struct intel_load_detect_pipe load_detect_temp;
10963
10964         /* We can't just switch on the pipe A, we need to set things up with a
10965          * proper mode and output configuration. As a gross hack, enable pipe A
10966          * by enabling the load detect pipe once. */
10967         list_for_each_entry(connector,
10968                             &dev->mode_config.connector_list,
10969                             base.head) {
10970                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10971                         crt = &connector->base;
10972                         break;
10973                 }
10974         }
10975
10976         if (!crt)
10977                 return;
10978
10979         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10980                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10981
10982
10983 }
10984
10985 static bool
10986 intel_check_plane_mapping(struct intel_crtc *crtc)
10987 {
10988         struct drm_device *dev = crtc->base.dev;
10989         struct drm_i915_private *dev_priv = dev->dev_private;
10990         u32 reg, val;
10991
10992         if (INTEL_INFO(dev)->num_pipes == 1)
10993                 return true;
10994
10995         reg = DSPCNTR(!crtc->plane);
10996         val = I915_READ(reg);
10997
10998         if ((val & DISPLAY_PLANE_ENABLE) &&
10999             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11000                 return false;
11001
11002         return true;
11003 }
11004
11005 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11006 {
11007         struct drm_device *dev = crtc->base.dev;
11008         struct drm_i915_private *dev_priv = dev->dev_private;
11009         u32 reg;
11010
11011         /* Clear any frame start delays used for debugging left by the BIOS */
11012         reg = PIPECONF(crtc->config.cpu_transcoder);
11013         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11014
11015         /* We need to sanitize the plane -> pipe mapping first because this will
11016          * disable the crtc (and hence change the state) if it is wrong. Note
11017          * that gen4+ has a fixed plane -> pipe mapping.  */
11018         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11019                 struct intel_connector *connector;
11020                 bool plane;
11021
11022                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11023                               crtc->base.base.id);
11024
11025                 /* Pipe has the wrong plane attached and the plane is active.
11026                  * Temporarily change the plane mapping and disable everything
11027                  * ...  */
11028                 plane = crtc->plane;
11029                 crtc->plane = !plane;
11030                 dev_priv->display.crtc_disable(&crtc->base);
11031                 crtc->plane = plane;
11032
11033                 /* ... and break all links. */
11034                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11035                                     base.head) {
11036                         if (connector->encoder->base.crtc != &crtc->base)
11037                                 continue;
11038
11039                         intel_connector_break_all_links(connector);
11040                 }
11041
11042                 WARN_ON(crtc->active);
11043                 crtc->base.enabled = false;
11044         }
11045
11046         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11047             crtc->pipe == PIPE_A && !crtc->active) {
11048                 /* BIOS forgot to enable pipe A, this mostly happens after
11049                  * resume. Force-enable the pipe to fix this, the update_dpms
11050                  * call below we restore the pipe to the right state, but leave
11051                  * the required bits on. */
11052                 intel_enable_pipe_a(dev);
11053         }
11054
11055         /* Adjust the state of the output pipe according to whether we
11056          * have active connectors/encoders. */
11057         intel_crtc_update_dpms(&crtc->base);
11058
11059         if (crtc->active != crtc->base.enabled) {
11060                 struct intel_encoder *encoder;
11061
11062                 /* This can happen either due to bugs in the get_hw_state
11063                  * functions or because the pipe is force-enabled due to the
11064                  * pipe A quirk. */
11065                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11066                               crtc->base.base.id,
11067                               crtc->base.enabled ? "enabled" : "disabled",
11068                               crtc->active ? "enabled" : "disabled");
11069
11070                 crtc->base.enabled = crtc->active;
11071
11072                 /* Because we only establish the connector -> encoder ->
11073                  * crtc links if something is active, this means the
11074                  * crtc is now deactivated. Break the links. connector
11075                  * -> encoder links are only establish when things are
11076                  *  actually up, hence no need to break them. */
11077                 WARN_ON(crtc->active);
11078
11079                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11080                         WARN_ON(encoder->connectors_active);
11081                         encoder->base.crtc = NULL;
11082                 }
11083         }
11084 }
11085
11086 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11087 {
11088         struct intel_connector *connector;
11089         struct drm_device *dev = encoder->base.dev;
11090
11091         /* We need to check both for a crtc link (meaning that the
11092          * encoder is active and trying to read from a pipe) and the
11093          * pipe itself being active. */
11094         bool has_active_crtc = encoder->base.crtc &&
11095                 to_intel_crtc(encoder->base.crtc)->active;
11096
11097         if (encoder->connectors_active && !has_active_crtc) {
11098                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11099                               encoder->base.base.id,
11100                               drm_get_encoder_name(&encoder->base));
11101
11102                 /* Connector is active, but has no active pipe. This is
11103                  * fallout from our resume register restoring. Disable
11104                  * the encoder manually again. */
11105                 if (encoder->base.crtc) {
11106                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11107                                       encoder->base.base.id,
11108                                       drm_get_encoder_name(&encoder->base));
11109                         encoder->disable(encoder);
11110                 }
11111
11112                 /* Inconsistent output/port/pipe state happens presumably due to
11113                  * a bug in one of the get_hw_state functions. Or someplace else
11114                  * in our code, like the register restore mess on resume. Clamp
11115                  * things to off as a safer default. */
11116                 list_for_each_entry(connector,
11117                                     &dev->mode_config.connector_list,
11118                                     base.head) {
11119                         if (connector->encoder != encoder)
11120                                 continue;
11121
11122                         intel_connector_break_all_links(connector);
11123                 }
11124         }
11125         /* Enabled encoders without active connectors will be fixed in
11126          * the crtc fixup. */
11127 }
11128
11129 void i915_redisable_vga(struct drm_device *dev)
11130 {
11131         struct drm_i915_private *dev_priv = dev->dev_private;
11132         u32 vga_reg = i915_vgacntrl_reg(dev);
11133
11134         /* This function can be called both from intel_modeset_setup_hw_state or
11135          * at a very early point in our resume sequence, where the power well
11136          * structures are not yet restored. Since this function is at a very
11137          * paranoid "someone might have enabled VGA while we were not looking"
11138          * level, just check if the power well is enabled instead of trying to
11139          * follow the "don't touch the power well if we don't need it" policy
11140          * the rest of the driver uses. */
11141         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11142             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11143                 return;
11144
11145         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11146                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11147                 i915_disable_vga(dev);
11148         }
11149 }
11150
11151 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11152 {
11153         struct drm_i915_private *dev_priv = dev->dev_private;
11154         enum pipe pipe;
11155         struct intel_crtc *crtc;
11156         struct intel_encoder *encoder;
11157         struct intel_connector *connector;
11158         int i;
11159
11160         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11161                             base.head) {
11162                 memset(&crtc->config, 0, sizeof(crtc->config));
11163
11164                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11165                                                                  &crtc->config);
11166
11167                 crtc->base.enabled = crtc->active;
11168                 crtc->primary_enabled = crtc->active;
11169
11170                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11171                               crtc->base.base.id,
11172                               crtc->active ? "enabled" : "disabled");
11173         }
11174
11175         /* FIXME: Smash this into the new shared dpll infrastructure. */
11176         if (HAS_DDI(dev))
11177                 intel_ddi_setup_hw_pll_state(dev);
11178
11179         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11180                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11181
11182                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11183                 pll->active = 0;
11184                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11185                                     base.head) {
11186                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11187                                 pll->active++;
11188                 }
11189                 pll->refcount = pll->active;
11190
11191                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11192                               pll->name, pll->refcount, pll->on);
11193         }
11194
11195         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11196                             base.head) {
11197                 pipe = 0;
11198
11199                 if (encoder->get_hw_state(encoder, &pipe)) {
11200                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11201                         encoder->base.crtc = &crtc->base;
11202                         encoder->get_config(encoder, &crtc->config);
11203                 } else {
11204                         encoder->base.crtc = NULL;
11205                 }
11206
11207                 encoder->connectors_active = false;
11208                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11209                               encoder->base.base.id,
11210                               drm_get_encoder_name(&encoder->base),
11211                               encoder->base.crtc ? "enabled" : "disabled",
11212                               pipe_name(pipe));
11213         }
11214
11215         list_for_each_entry(connector, &dev->mode_config.connector_list,
11216                             base.head) {
11217                 if (connector->get_hw_state(connector)) {
11218                         connector->base.dpms = DRM_MODE_DPMS_ON;
11219                         connector->encoder->connectors_active = true;
11220                         connector->base.encoder = &connector->encoder->base;
11221                 } else {
11222                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11223                         connector->base.encoder = NULL;
11224                 }
11225                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11226                               connector->base.base.id,
11227                               drm_get_connector_name(&connector->base),
11228                               connector->base.encoder ? "enabled" : "disabled");
11229         }
11230 }
11231
11232 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11233  * and i915 state tracking structures. */
11234 void intel_modeset_setup_hw_state(struct drm_device *dev,
11235                                   bool force_restore)
11236 {
11237         struct drm_i915_private *dev_priv = dev->dev_private;
11238         enum pipe pipe;
11239         struct intel_crtc *crtc;
11240         struct intel_encoder *encoder;
11241         int i;
11242
11243         intel_modeset_readout_hw_state(dev);
11244
11245         /*
11246          * Now that we have the config, copy it to each CRTC struct
11247          * Note that this could go away if we move to using crtc_config
11248          * checking everywhere.
11249          */
11250         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11251                             base.head) {
11252                 if (crtc->active && i915_fastboot) {
11253                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11254
11255                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11256                                       crtc->base.base.id);
11257                         drm_mode_debug_printmodeline(&crtc->base.mode);
11258                 }
11259         }
11260
11261         /* HW state is read out, now we need to sanitize this mess. */
11262         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11263                             base.head) {
11264                 intel_sanitize_encoder(encoder);
11265         }
11266
11267         for_each_pipe(pipe) {
11268                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11269                 intel_sanitize_crtc(crtc);
11270                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11271         }
11272
11273         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11274                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11275
11276                 if (!pll->on || pll->active)
11277                         continue;
11278
11279                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11280
11281                 pll->disable(dev_priv, pll);
11282                 pll->on = false;
11283         }
11284
11285         if (HAS_PCH_SPLIT(dev))
11286                 ilk_wm_get_hw_state(dev);
11287
11288         if (force_restore) {
11289                 i915_redisable_vga(dev);
11290
11291                 /*
11292                  * We need to use raw interfaces for restoring state to avoid
11293                  * checking (bogus) intermediate states.
11294                  */
11295                 for_each_pipe(pipe) {
11296                         struct drm_crtc *crtc =
11297                                 dev_priv->pipe_to_crtc_mapping[pipe];
11298
11299                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11300                                          crtc->fb);
11301                 }
11302         } else {
11303                 intel_modeset_update_staged_output_state(dev);
11304         }
11305
11306         intel_modeset_check_state(dev);
11307 }
11308
11309 void intel_modeset_gem_init(struct drm_device *dev)
11310 {
11311         intel_modeset_init_hw(dev);
11312
11313         intel_setup_overlay(dev);
11314
11315         mutex_lock(&dev->mode_config.mutex);
11316         drm_mode_config_reset(dev);
11317         intel_modeset_setup_hw_state(dev, false);
11318         mutex_unlock(&dev->mode_config.mutex);
11319 }
11320
11321 void intel_modeset_cleanup(struct drm_device *dev)
11322 {
11323         struct drm_i915_private *dev_priv = dev->dev_private;
11324         struct drm_crtc *crtc;
11325         struct drm_connector *connector;
11326
11327         /*
11328          * Interrupts and polling as the first thing to avoid creating havoc.
11329          * Too much stuff here (turning of rps, connectors, ...) would
11330          * experience fancy races otherwise.
11331          */
11332         drm_irq_uninstall(dev);
11333         cancel_work_sync(&dev_priv->hotplug_work);
11334         /*
11335          * Due to the hpd irq storm handling the hotplug work can re-arm the
11336          * poll handlers. Hence disable polling after hpd handling is shut down.
11337          */
11338         drm_kms_helper_poll_fini(dev);
11339
11340         mutex_lock(&dev->struct_mutex);
11341
11342         intel_unregister_dsm_handler();
11343
11344         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11345                 /* Skip inactive CRTCs */
11346                 if (!crtc->fb)
11347                         continue;
11348
11349                 intel_increase_pllclock(crtc);
11350         }
11351
11352         intel_disable_fbc(dev);
11353
11354         intel_disable_gt_powersave(dev);
11355
11356         ironlake_teardown_rc6(dev);
11357
11358         mutex_unlock(&dev->struct_mutex);
11359
11360         /* flush any delayed tasks or pending work */
11361         flush_scheduled_work();
11362
11363         /* destroy the backlight and sysfs files before encoders/connectors */
11364         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11365                 intel_panel_destroy_backlight(connector);
11366                 drm_sysfs_connector_remove(connector);
11367         }
11368
11369         drm_mode_config_cleanup(dev);
11370
11371         intel_cleanup_overlay(dev);
11372 }
11373
11374 /*
11375  * Return which encoder is currently attached for connector.
11376  */
11377 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11378 {
11379         return &intel_attached_encoder(connector)->base;
11380 }
11381
11382 void intel_connector_attach_encoder(struct intel_connector *connector,
11383                                     struct intel_encoder *encoder)
11384 {
11385         connector->encoder = encoder;
11386         drm_mode_connector_attach_encoder(&connector->base,
11387                                           &encoder->base);
11388 }
11389
11390 /*
11391  * set vga decode state - true == enable VGA decode
11392  */
11393 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11394 {
11395         struct drm_i915_private *dev_priv = dev->dev_private;
11396         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11397         u16 gmch_ctrl;
11398
11399         pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
11400         if (state)
11401                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11402         else
11403                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11404         pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
11405         return 0;
11406 }
11407
11408 struct intel_display_error_state {
11409
11410         u32 power_well_driver;
11411
11412         int num_transcoders;
11413
11414         struct intel_cursor_error_state {
11415                 u32 control;
11416                 u32 position;
11417                 u32 base;
11418                 u32 size;
11419         } cursor[I915_MAX_PIPES];
11420
11421         struct intel_pipe_error_state {
11422                 bool power_domain_on;
11423                 u32 source;
11424         } pipe[I915_MAX_PIPES];
11425
11426         struct intel_plane_error_state {
11427                 u32 control;
11428                 u32 stride;
11429                 u32 size;
11430                 u32 pos;
11431                 u32 addr;
11432                 u32 surface;
11433                 u32 tile_offset;
11434         } plane[I915_MAX_PIPES];
11435
11436         struct intel_transcoder_error_state {
11437                 bool power_domain_on;
11438                 enum transcoder cpu_transcoder;
11439
11440                 u32 conf;
11441
11442                 u32 htotal;
11443                 u32 hblank;
11444                 u32 hsync;
11445                 u32 vtotal;
11446                 u32 vblank;
11447                 u32 vsync;
11448         } transcoder[4];
11449 };
11450
11451 struct intel_display_error_state *
11452 intel_display_capture_error_state(struct drm_device *dev)
11453 {
11454         drm_i915_private_t *dev_priv = dev->dev_private;
11455         struct intel_display_error_state *error;
11456         int transcoders[] = {
11457                 TRANSCODER_A,
11458                 TRANSCODER_B,
11459                 TRANSCODER_C,
11460                 TRANSCODER_EDP,
11461         };
11462         int i;
11463
11464         if (INTEL_INFO(dev)->num_pipes == 0)
11465                 return NULL;
11466
11467         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11468         if (error == NULL)
11469                 return NULL;
11470
11471         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11472                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11473
11474         for_each_pipe(i) {
11475                 error->pipe[i].power_domain_on =
11476                         intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11477                 if (!error->pipe[i].power_domain_on)
11478                         continue;
11479
11480                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11481                         error->cursor[i].control = I915_READ(CURCNTR(i));
11482                         error->cursor[i].position = I915_READ(CURPOS(i));
11483                         error->cursor[i].base = I915_READ(CURBASE(i));
11484                 } else {
11485                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11486                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11487                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11488                 }
11489
11490                 error->plane[i].control = I915_READ(DSPCNTR(i));
11491                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11492                 if (INTEL_INFO(dev)->gen <= 3) {
11493                         error->plane[i].size = I915_READ(DSPSIZE(i));
11494                         error->plane[i].pos = I915_READ(DSPPOS(i));
11495                 }
11496                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11497                         error->plane[i].addr = I915_READ(DSPADDR(i));
11498                 if (INTEL_INFO(dev)->gen >= 4) {
11499                         error->plane[i].surface = I915_READ(DSPSURF(i));
11500                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11501                 }
11502
11503                 error->pipe[i].source = I915_READ(PIPESRC(i));
11504         }
11505
11506         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11507         if (HAS_DDI(dev_priv->dev))
11508                 error->num_transcoders++; /* Account for eDP. */
11509
11510         for (i = 0; i < error->num_transcoders; i++) {
11511                 enum transcoder cpu_transcoder = transcoders[i];
11512
11513                 error->transcoder[i].power_domain_on =
11514                         intel_display_power_enabled_sw(dev,
11515                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11516                 if (!error->transcoder[i].power_domain_on)
11517                         continue;
11518
11519                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11520
11521                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11522                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11523                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11524                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11525                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11526                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11527                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11528         }
11529
11530         return error;
11531 }
11532
11533 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11534
11535 void
11536 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11537                                 struct drm_device *dev,
11538                                 struct intel_display_error_state *error)
11539 {
11540         int i;
11541
11542         if (!error)
11543                 return;
11544
11545         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11546         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11547                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11548                            error->power_well_driver);
11549         for_each_pipe(i) {
11550                 err_printf(m, "Pipe [%d]:\n", i);
11551                 err_printf(m, "  Power: %s\n",
11552                            error->pipe[i].power_domain_on ? "on" : "off");
11553                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11554
11555                 err_printf(m, "Plane [%d]:\n", i);
11556                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11557                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11558                 if (INTEL_INFO(dev)->gen <= 3) {
11559                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11560                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11561                 }
11562                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11563                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11564                 if (INTEL_INFO(dev)->gen >= 4) {
11565                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11566                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11567                 }
11568
11569                 err_printf(m, "Cursor [%d]:\n", i);
11570                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11571                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11572                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11573         }
11574
11575         for (i = 0; i < error->num_transcoders; i++) {
11576                 err_printf(m, "CPU transcoder: %c\n",
11577                            transcoder_name(error->transcoder[i].cpu_transcoder));
11578                 err_printf(m, "  Power: %s\n",
11579                            error->transcoder[i].power_domain_on ? "on" : "off");
11580                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11581                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11582                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11583                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11584                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11585                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11586                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11587         }
11588 }