drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include "drmP.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "drm_dp_helper.h"
  40
  41 #include "drm_crtc_helper.h"
  42
  43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  44
  45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  46 static void intel_update_watermarks(struct drm_device *dev);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51     /* given values */
  52     int n;
  53     int m1, m2;
  54     int p1, p2;
  55     /* derived values */
  56     int dot;
  57     int vco;
  58     int m;
  59     int p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63     int min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67     int dot_limit;
  68     int p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75     intel_p2_t      p2;
  76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                       int, int, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *best_clock);
  86 static bool
  87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  88                         int target, int refclk, intel_clock_t *best_clock);
  89
  90 static bool
  91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  92                       int target, int refclk, intel_clock_t *best_clock);
  93 static bool
  94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                            int target, int refclk, intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2,.max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2,.max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 359                                                 int refclk)
 360 {
 361         struct drm_device *dev = crtc->dev;
 362         struct drm_i915_private *dev_priv = dev->dev_private;
 363         const intel_limit_t *limit;
 364
 365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 367                     LVDS_CLKB_POWER_UP) {
 368                         /* LVDS dual channel */
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_dual_lvds;
 373                 } else {
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_single_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_single_lvds;
 378                 }
 379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 380                         HAS_eDP)
 381                 limit = &intel_limits_ironlake_display_port;
 382         else
 383                 limit = &intel_limits_ironlake_dac;
 384
 385         return limit;
 386 }
 387
 388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 389 {
 390         struct drm_device *dev = crtc->dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         const intel_limit_t *limit;
 393
 394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 396                     LVDS_CLKB_POWER_UP)
 397                         /* LVDS with dual channel */
 398                         limit = &intel_limits_g4x_dual_channel_lvds;
 399                 else
 400                         /* LVDS with dual channel */
 401                         limit = &intel_limits_g4x_single_channel_lvds;
 402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 404                 limit = &intel_limits_g4x_hdmi;
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 406                 limit = &intel_limits_g4x_sdvo;
 407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 408                 limit = &intel_limits_g4x_display_port;
 409         } else /* The option is for other outputs */
 410                 limit = &intel_limits_i9xx_sdvo;
 411
 412         return limit;
 413 }
 414
 415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 416 {
 417         struct drm_device *dev = crtc->dev;
 418         const intel_limit_t *limit;
 419
 420         if (HAS_PCH_SPLIT(dev))
 421                 limit = intel_ironlake_limit(crtc, refclk);
 422         else if (IS_G4X(dev)) {
 423                 limit = intel_g4x_limit(crtc);
 424         } else if (IS_PINEVIEW(dev)) {
 425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 426                         limit = &intel_limits_pineview_lvds;
 427                 else
 428                         limit = &intel_limits_pineview_sdvo;
 429         } else if (!IS_GEN2(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_i9xx_lvds;
 432                 else
 433                         limit = &intel_limits_i9xx_sdvo;
 434         } else {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i8xx_lvds;
 437                 else
 438                         limit = &intel_limits_i8xx_dvo;
 439         }
 440         return limit;
 441 }
 442
 443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 444 static void pineview_clock(int refclk, intel_clock_t *clock)
 445 {
 446         clock->m = clock->m2 + 2;
 447         clock->p = clock->p1 * clock->p2;
 448         clock->vco = refclk * clock->m / clock->n;
 449         clock->dot = clock->vco / clock->p;
 450 }
 451
 452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 453 {
 454         if (IS_PINEVIEW(dev)) {
 455                 pineview_clock(refclk, clock);
 456                 return;
 457         }
 458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 459         clock->p = clock->p1 * clock->p2;
 460         clock->vco = refclk * clock->m / (clock->n + 2);
 461         clock->dot = clock->vco / clock->p;
 462 }
 463
 464 /**
 465  * Returns whether any output on the specified pipe is of the specified type
 466  */
 467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_mode_config *mode_config = &dev->mode_config;
 471         struct intel_encoder *encoder;
 472
 473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 474                 if (encoder->base.crtc == crtc && encoder->type == type)
 475                         return true;
 476
 477         return false;
 478 }
 479
 480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 481 /**
 482  * Returns whether the given set of divisors are valid for a given refclk with
 483  * the given connectors.
 484  */
 485
 486 static bool intel_PLL_is_valid(struct drm_device *dev,
 487                                const intel_limit_t *limit,
 488                                const intel_clock_t *clock)
 489 {
 490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 491                 INTELPllInvalid ("p1 out of range\n");
 492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 493                 INTELPllInvalid ("p out of range\n");
 494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 495                 INTELPllInvalid ("m2 out of range\n");
 496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 497                 INTELPllInvalid ("m1 out of range\n");
 498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 499                 INTELPllInvalid ("m1 <= m2\n");
 500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 501                 INTELPllInvalid ("m out of range\n");
 502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 503                 INTELPllInvalid ("n out of range\n");
 504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 505                 INTELPllInvalid ("vco out of range\n");
 506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 507          * connector, etc., rather than just a single range.
 508          */
 509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 510                 INTELPllInvalid ("dot out of range\n");
 511
 512         return true;
 513 }
 514
 515 static bool
 516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 517                     int target, int refclk, intel_clock_t *best_clock)
 518
 519 {
 520         struct drm_device *dev = crtc->dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         intel_clock_t clock;
 523         int err = target;
 524
 525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 526             (I915_READ(LVDS)) != 0) {
 527                 /*
 528                  * For LVDS, if the panel is on, just rely on its current
 529                  * settings for dual-channel.  We haven't figured out how to
 530                  * reliably set up different single/dual channel state, if we
 531                  * even can.
 532                  */
 533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 534                     LVDS_CLKB_POWER_UP)
 535                         clock.p2 = limit->p2.p2_fast;
 536                 else
 537                         clock.p2 = limit->p2.p2_slow;
 538         } else {
 539                 if (target < limit->p2.dot_limit)
 540                         clock.p2 = limit->p2.p2_slow;
 541                 else
 542                         clock.p2 = limit->p2.p2_fast;
 543         }
 544
 545         memset (best_clock, 0, sizeof (*best_clock));
 546
 547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 548              clock.m1++) {
 549                 for (clock.m2 = limit->m2.min;
 550                      clock.m2 <= limit->m2.max; clock.m2++) {
 551                         /* m1 is always 0 in Pineview */
 552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 553                                 break;
 554                         for (clock.n = limit->n.min;
 555                              clock.n <= limit->n.max; clock.n++) {
 556                                 for (clock.p1 = limit->p1.min;
 557                                         clock.p1 <= limit->p1.max; clock.p1++) {
 558                                         int this_err;
 559
 560                                         intel_clock(dev, refclk, &clock);
 561                                         if (!intel_PLL_is_valid(dev, limit,
 562                                                                 &clock))
 563                                                 continue;
 564
 565                                         this_err = abs(clock.dot - target);
 566                                         if (this_err < err) {
 567                                                 *best_clock = clock;
 568                                                 err = this_err;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573         }
 574
 575         return (err != target);
 576 }
 577
 578 static bool
 579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                         int target, int refclk, intel_clock_t *best_clock)
 581 {
 582         struct drm_device *dev = crtc->dev;
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         intel_clock_t clock;
 585         int max_n;
 586         bool found;
 587         /* approximately equals target * 0.00585 */
 588         int err_most = (target >> 8) + (target >> 9);
 589         found = false;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 int lvds_reg;
 593
 594                 if (HAS_PCH_SPLIT(dev))
 595                         lvds_reg = PCH_LVDS;
 596                 else
 597                         lvds_reg = LVDS;
 598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 599                     LVDS_CLKB_POWER_UP)
 600                         clock.p2 = limit->p2.p2_fast;
 601                 else
 602                         clock.p2 = limit->p2.p2_slow;
 603         } else {
 604                 if (target < limit->p2.dot_limit)
 605                         clock.p2 = limit->p2.p2_slow;
 606                 else
 607                         clock.p2 = limit->p2.p2_fast;
 608         }
 609
 610         memset(best_clock, 0, sizeof(*best_clock));
 611         max_n = limit->n.max;
 612         /* based on hardware requirement, prefer smaller n to precision */
 613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 614                 /* based on hardware requirement, prefere larger m1,m2 */
 615                 for (clock.m1 = limit->m1.max;
 616                      clock.m1 >= limit->m1.min; clock.m1--) {
 617                         for (clock.m2 = limit->m2.max;
 618                              clock.m2 >= limit->m2.min; clock.m2--) {
 619                                 for (clock.p1 = limit->p1.max;
 620                                      clock.p1 >= limit->p1.min; clock.p1--) {
 621                                         int this_err;
 622
 623                                         intel_clock(dev, refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err_most) {
 630                                                 *best_clock = clock;
 631                                                 err_most = this_err;
 632                                                 max_n = clock.n;
 633                                                 found = true;
 634                                         }
 635                                 }
 636                         }
 637                 }
 638         }
 639         return found;
 640 }
 641
 642 static bool
 643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 644                            int target, int refclk, intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         intel_clock_t clock;
 648
 649         if (target < 200000) {
 650                 clock.n = 1;
 651                 clock.p1 = 2;
 652                 clock.p2 = 10;
 653                 clock.m1 = 12;
 654                 clock.m2 = 9;
 655         } else {
 656                 clock.n = 2;
 657                 clock.p1 = 1;
 658                 clock.p2 = 10;
 659                 clock.m1 = 14;
 660                 clock.m2 = 8;
 661         }
 662         intel_clock(dev, refclk, &clock);
 663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 664         return true;
 665 }
 666
 667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 668 static bool
 669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                       int target, int refclk, intel_clock_t *best_clock)
 671 {
 672         intel_clock_t clock;
 673         if (target < 200000) {
 674                 clock.p1 = 2;
 675                 clock.p2 = 10;
 676                 clock.n = 2;
 677                 clock.m1 = 23;
 678                 clock.m2 = 8;
 679         } else {
 680                 clock.p1 = 1;
 681                 clock.p2 = 10;
 682                 clock.n = 1;
 683                 clock.m1 = 14;
 684                 clock.m2 = 2;
 685         }
 686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 687         clock.p = (clock.p1 * clock.p2);
 688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 689         clock.vco = 0;
 690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 691         return true;
 692 }
 693
 694 /**
 695  * intel_wait_for_vblank - wait for vblank on a given pipe
 696  * @dev: drm device
 697  * @pipe: pipe to wait for
 698  *
 699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 700  * mode setting code.
 701  */
 702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 703 {
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         int pipestat_reg = PIPESTAT(pipe);
 706
 707         /* Clear existing vblank status. Note this will clear any other
 708          * sticky status fields as well.
 709          *
 710          * This races with i915_driver_irq_handler() with the result
 711          * that either function could miss a vblank event.  Here it is not
 712          * fatal, as we will either wait upon the next vblank interrupt or
 713          * timeout.  Generally speaking intel_wait_for_vblank() is only
 714          * called during modeset at which time the GPU should be idle and
 715          * should *not* be performing page flips and thus not waiting on
 716          * vblanks...
 717          * Currently, the result of us stealing a vblank from the irq
 718          * handler is that a single frame will be skipped during swapbuffers.
 719          */
 720         I915_WRITE(pipestat_reg,
 721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 722
 723         /* Wait for vblank interrupt bit to set */
 724         if (wait_for(I915_READ(pipestat_reg) &
 725                      PIPE_VBLANK_INTERRUPT_STATUS,
 726                      50))
 727                 DRM_DEBUG_KMS("vblank wait timed out\n");
 728 }
 729
 730 /*
 731  * intel_wait_for_pipe_off - wait for pipe to turn off
 732  * @dev: drm device
 733  * @pipe: pipe to wait for
 734  *
 735  * After disabling a pipe, we can't wait for vblank in the usual way,
 736  * spinning on the vblank interrupt status bit, since we won't actually
 737  * see an interrupt when the pipe is disabled.
 738  *
 739  * On Gen4 and above:
 740  *   wait for the pipe register state bit to turn off
 741  *
 742  * Otherwise:
 743  *   wait for the display line value to settle (it usually
 744  *   ends up stopping at the start of the next frame).
 745  *
 746  */
 747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750
 751         if (INTEL_INFO(dev)->gen >= 4) {
 752                 int reg = PIPECONF(pipe);
 753
 754                 /* Wait for the Pipe State to go off */
 755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 756                              100))
 757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 758         } else {
 759                 u32 last_line;
 760                 int reg = PIPEDSL(pipe);
 761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 762
 763                 /* Wait for the display line to settle */
 764                 do {
 765                         last_line = I915_READ(reg) & DSL_LINEMASK;
 766                         mdelay(5);
 767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 768                          time_after(timeout, jiffies));
 769                 if (time_after(jiffies, timeout))
 770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 771         }
 772 }
 773
 774 static const char *state_string(bool enabled)
 775 {
 776         return enabled ? "on" : "off";
 777 }
 778
 779 /* Only for pre-ILK configs */
 780 static void assert_pll(struct drm_i915_private *dev_priv,
 781                        enum pipe pipe, bool state)
 782 {
 783         int reg;
 784         u32 val;
 785         bool cur_state;
 786
 787         reg = DPLL(pipe);
 788         val = I915_READ(reg);
 789         cur_state = !!(val & DPLL_VCO_ENABLE);
 790         WARN(cur_state != state,
 791              "PLL state assertion failure (expected %s, current %s)\n",
 792              state_string(state), state_string(cur_state));
 793 }
 794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 796
 797 /* For ILK+ */
 798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 799                            enum pipe pipe, bool state)
 800 {
 801         int reg;
 802         u32 val;
 803         bool cur_state;
 804
 805         reg = PCH_DPLL(pipe);
 806         val = I915_READ(reg);
 807         cur_state = !!(val & DPLL_VCO_ENABLE);
 808         WARN(cur_state != state,
 809              "PCH PLL state assertion failure (expected %s, current %s)\n",
 810              state_string(state), state_string(cur_state));
 811 }
 812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 814
 815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 816                           enum pipe pipe, bool state)
 817 {
 818         int reg;
 819         u32 val;
 820         bool cur_state;
 821
 822         reg = FDI_TX_CTL(pipe);
 823         val = I915_READ(reg);
 824         cur_state = !!(val & FDI_TX_ENABLE);
 825         WARN(cur_state != state,
 826              "FDI TX state assertion failure (expected %s, current %s)\n",
 827              state_string(state), state_string(cur_state));
 828 }
 829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 831
 832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 833                           enum pipe pipe, bool state)
 834 {
 835         int reg;
 836         u32 val;
 837         bool cur_state;
 838
 839         reg = FDI_RX_CTL(pipe);
 840         val = I915_READ(reg);
 841         cur_state = !!(val & FDI_RX_ENABLE);
 842         WARN(cur_state != state,
 843              "FDI RX state assertion failure (expected %s, current %s)\n",
 844              state_string(state), state_string(cur_state));
 845 }
 846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 848
 849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 850                                       enum pipe pipe)
 851 {
 852         int reg;
 853         u32 val;
 854
 855         /* ILK FDI PLL is always enabled */
 856         if (dev_priv->info->gen == 5)
 857                 return;
 858
 859         reg = FDI_TX_CTL(pipe);
 860         val = I915_READ(reg);
 861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 862 }
 863
 864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 865                                       enum pipe pipe)
 866 {
 867         int reg;
 868         u32 val;
 869
 870         reg = FDI_RX_CTL(pipe);
 871         val = I915_READ(reg);
 872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 873 }
 874
 875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 876                                   enum pipe pipe)
 877 {
 878         int pp_reg, lvds_reg;
 879         u32 val;
 880         enum pipe panel_pipe = PIPE_A;
 881         bool locked = locked;
 882
 883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 884                 pp_reg = PCH_PP_CONTROL;
 885                 lvds_reg = PCH_LVDS;
 886         } else {
 887                 pp_reg = PP_CONTROL;
 888                 lvds_reg = LVDS;
 889         }
 890
 891         val = I915_READ(pp_reg);
 892         if (!(val & PANEL_POWER_ON) ||
 893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 894                 locked = false;
 895
 896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 897                 panel_pipe = PIPE_B;
 898
 899         WARN(panel_pipe == pipe && locked,
 900              "panel assertion failure, pipe %c regs locked\n",
 901              pipe_name(pipe));
 902 }
 903
 904 static void assert_pipe(struct drm_i915_private *dev_priv,
 905                         enum pipe pipe, bool state)
 906 {
 907         int reg;
 908         u32 val;
 909         bool cur_state;
 910
 911         reg = PIPECONF(pipe);
 912         val = I915_READ(reg);
 913         cur_state = !!(val & PIPECONF_ENABLE);
 914         WARN(cur_state != state,
 915              "pipe %c assertion failure (expected %s, current %s)\n",
 916              pipe_name(pipe), state_string(state), state_string(cur_state));
 917 }
 918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 920
 921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 922                                  enum plane plane)
 923 {
 924         int reg;
 925         u32 val;
 926
 927         reg = DSPCNTR(plane);
 928         val = I915_READ(reg);
 929         WARN(!(val & DISPLAY_PLANE_ENABLE),
 930              "plane %c assertion failure, should be active but is disabled\n",
 931              plane_name(plane));
 932 }
 933
 934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 935                                    enum pipe pipe)
 936 {
 937         int reg, i;
 938         u32 val;
 939         int cur_pipe;
 940
 941         /* Planes are fixed to pipes on ILK+ */
 942         if (HAS_PCH_SPLIT(dev_priv->dev))
 943                 return;
 944
 945         /* Need to check both planes against the pipe */
 946         for (i = 0; i < 2; i++) {
 947                 reg = DSPCNTR(i);
 948                 val = I915_READ(reg);
 949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 950                         DISPPLANE_SEL_PIPE_SHIFT;
 951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 953                      plane_name(i), pipe_name(pipe));
 954         }
 955 }
 956
 957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 958 {
 959         u32 val;
 960         bool enabled;
 961
 962         val = I915_READ(PCH_DREF_CONTROL);
 963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 964                             DREF_SUPERSPREAD_SOURCE_MASK));
 965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 966 }
 967
 968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 969                                        enum pipe pipe)
 970 {
 971         int reg;
 972         u32 val;
 973         bool enabled;
 974
 975         reg = TRANSCONF(pipe);
 976         val = I915_READ(reg);
 977         enabled = !!(val & TRANS_ENABLE);
 978         WARN(enabled,
 979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 980              pipe_name(pipe));
 981 }
 982
 983 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
 984                             int reg, u32 port_sel, u32 val)
 985 {
 986         if ((val & DP_PORT_EN) == 0)
 987                 return false;
 988
 989         if (HAS_PCH_CPT(dev_priv->dev)) {
 990                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
 991                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
 992                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 993                         return false;
 994         } else {
 995                 if ((val & DP_PIPE_MASK) != (pipe << 30))
 996                         return false;
 997         }
 998         return true;
 999 }
1000
1001 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1002                                    enum pipe pipe, int reg, u32 port_sel)
1003 {
1004         u32 val = I915_READ(reg);
1005         WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
1006              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1007              reg, pipe_name(pipe));
1008 }
1009
1010 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1011                                      enum pipe pipe, int reg)
1012 {
1013         u32 val = I915_READ(reg);
1014         WARN(HDMI_PIPE_ENABLED(val, pipe),
1015              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1016              reg, pipe_name(pipe));
1017 }
1018
1019 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1020                                       enum pipe pipe)
1021 {
1022         int reg;
1023         u32 val;
1024
1025         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1026         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1027         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1028
1029         reg = PCH_ADPA;
1030         val = I915_READ(reg);
1031         WARN(ADPA_PIPE_ENABLED(val, pipe),
1032              "PCH VGA enabled on transcoder %c, should be disabled\n",
1033              pipe_name(pipe));
1034
1035         reg = PCH_LVDS;
1036         val = I915_READ(reg);
1037         WARN(LVDS_PIPE_ENABLED(val, pipe),
1038              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1039              pipe_name(pipe));
1040
1041         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1042         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1043         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1044 }
1045
1046 /**
1047  * intel_enable_pll - enable a PLL
1048  * @dev_priv: i915 private structure
1049  * @pipe: pipe PLL to enable
1050  *
1051  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1052  * make sure the PLL reg is writable first though, since the panel write
1053  * protect mechanism may be enabled.
1054  *
1055  * Note!  This is for pre-ILK only.
1056  */
1057 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1058 {
1059         int reg;
1060         u32 val;
1061
1062         /* No really, not for ILK+ */
1063         BUG_ON(dev_priv->info->gen >= 5);
1064
1065         /* PLL is protected by panel, make sure we can write it */
1066         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1067                 assert_panel_unlocked(dev_priv, pipe);
1068
1069         reg = DPLL(pipe);
1070         val = I915_READ(reg);
1071         val |= DPLL_VCO_ENABLE;
1072
1073         /* We do this three times for luck */
1074         I915_WRITE(reg, val);
1075         POSTING_READ(reg);
1076         udelay(150); /* wait for warmup */
1077         I915_WRITE(reg, val);
1078         POSTING_READ(reg);
1079         udelay(150); /* wait for warmup */
1080         I915_WRITE(reg, val);
1081         POSTING_READ(reg);
1082         udelay(150); /* wait for warmup */
1083 }
1084
1085 /**
1086  * intel_disable_pll - disable a PLL
1087  * @dev_priv: i915 private structure
1088  * @pipe: pipe PLL to disable
1089  *
1090  * Disable the PLL for @pipe, making sure the pipe is off first.
1091  *
1092  * Note!  This is for pre-ILK only.
1093  */
1094 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1095 {
1096         int reg;
1097         u32 val;
1098
1099         /* Don't disable pipe A or pipe A PLLs if needed */
1100         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1101                 return;
1102
1103         /* Make sure the pipe isn't still relying on us */
1104         assert_pipe_disabled(dev_priv, pipe);
1105
1106         reg = DPLL(pipe);
1107         val = I915_READ(reg);
1108         val &= ~DPLL_VCO_ENABLE;
1109         I915_WRITE(reg, val);
1110         POSTING_READ(reg);
1111 }
1112
1113 /**
1114  * intel_enable_pch_pll - enable PCH PLL
1115  * @dev_priv: i915 private structure
1116  * @pipe: pipe PLL to enable
1117  *
1118  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1119  * drives the transcoder clock.
1120  */
1121 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1122                                  enum pipe pipe)
1123 {
1124         int reg;
1125         u32 val;
1126
1127         /* PCH only available on ILK+ */
1128         BUG_ON(dev_priv->info->gen < 5);
1129
1130         /* PCH refclock must be enabled first */
1131         assert_pch_refclk_enabled(dev_priv);
1132
1133         reg = PCH_DPLL(pipe);
1134         val = I915_READ(reg);
1135         val |= DPLL_VCO_ENABLE;
1136         I915_WRITE(reg, val);
1137         POSTING_READ(reg);
1138         udelay(200);
1139 }
1140
1141 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1142                                   enum pipe pipe)
1143 {
1144         int reg;
1145         u32 val;
1146
1147         /* PCH only available on ILK+ */
1148         BUG_ON(dev_priv->info->gen < 5);
1149
1150         /* Make sure transcoder isn't still depending on us */
1151         assert_transcoder_disabled(dev_priv, pipe);
1152
1153         reg = PCH_DPLL(pipe);
1154         val = I915_READ(reg);
1155         val &= ~DPLL_VCO_ENABLE;
1156         I915_WRITE(reg, val);
1157         POSTING_READ(reg);
1158         udelay(200);
1159 }
1160
1161 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1162                                     enum pipe pipe)
1163 {
1164         int reg;
1165         u32 val;
1166
1167         /* PCH only available on ILK+ */
1168         BUG_ON(dev_priv->info->gen < 5);
1169
1170         /* Make sure PCH DPLL is enabled */
1171         assert_pch_pll_enabled(dev_priv, pipe);
1172
1173         /* FDI must be feeding us bits for PCH ports */
1174         assert_fdi_tx_enabled(dev_priv, pipe);
1175         assert_fdi_rx_enabled(dev_priv, pipe);
1176
1177         reg = TRANSCONF(pipe);
1178         val = I915_READ(reg);
1179
1180         if (HAS_PCH_IBX(dev_priv->dev)) {
1181                 /*
1182                  * make the BPC in transcoder be consistent with
1183                  * that in pipeconf reg.
1184                  */
1185                 val &= ~PIPE_BPC_MASK;
1186                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1187         }
1188         I915_WRITE(reg, val | TRANS_ENABLE);
1189         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1190                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1191 }
1192
1193 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1194                                      enum pipe pipe)
1195 {
1196         int reg;
1197         u32 val;
1198
1199         /* FDI relies on the transcoder */
1200         assert_fdi_tx_disabled(dev_priv, pipe);
1201         assert_fdi_rx_disabled(dev_priv, pipe);
1202
1203         /* Ports must be off as well */
1204         assert_pch_ports_disabled(dev_priv, pipe);
1205
1206         reg = TRANSCONF(pipe);
1207         val = I915_READ(reg);
1208         val &= ~TRANS_ENABLE;
1209         I915_WRITE(reg, val);
1210         /* wait for PCH transcoder off, transcoder state */
1211         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1212                 DRM_ERROR("failed to disable transcoder\n");
1213 }
1214
1215 /**
1216  * intel_enable_pipe - enable a pipe, asserting requirements
1217  * @dev_priv: i915 private structure
1218  * @pipe: pipe to enable
1219  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1220  *
1221  * Enable @pipe, making sure that various hardware specific requirements
1222  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1223  *
1224  * @pipe should be %PIPE_A or %PIPE_B.
1225  *
1226  * Will wait until the pipe is actually running (i.e. first vblank) before
1227  * returning.
1228  */
1229 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1230                               bool pch_port)
1231 {
1232         int reg;
1233         u32 val;
1234
1235         /*
1236          * A pipe without a PLL won't actually be able to drive bits from
1237          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1238          * need the check.
1239          */
1240         if (!HAS_PCH_SPLIT(dev_priv->dev))
1241                 assert_pll_enabled(dev_priv, pipe);
1242         else {
1243                 if (pch_port) {
1244                         /* if driving the PCH, we need FDI enabled */
1245                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1246                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1247                 }
1248                 /* FIXME: assert CPU port conditions for SNB+ */
1249         }
1250
1251         reg = PIPECONF(pipe);
1252         val = I915_READ(reg);
1253         if (val & PIPECONF_ENABLE)
1254                 return;
1255
1256         I915_WRITE(reg, val | PIPECONF_ENABLE);
1257         intel_wait_for_vblank(dev_priv->dev, pipe);
1258 }
1259
1260 /**
1261  * intel_disable_pipe - disable a pipe, asserting requirements
1262  * @dev_priv: i915 private structure
1263  * @pipe: pipe to disable
1264  *
1265  * Disable @pipe, making sure that various hardware specific requirements
1266  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1267  *
1268  * @pipe should be %PIPE_A or %PIPE_B.
1269  *
1270  * Will wait until the pipe has shut down before returning.
1271  */
1272 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1273                                enum pipe pipe)
1274 {
1275         int reg;
1276         u32 val;
1277
1278         /*
1279          * Make sure planes won't keep trying to pump pixels to us,
1280          * or we might hang the display.
1281          */
1282         assert_planes_disabled(dev_priv, pipe);
1283
1284         /* Don't disable pipe A or pipe A PLLs if needed */
1285         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1286                 return;
1287
1288         reg = PIPECONF(pipe);
1289         val = I915_READ(reg);
1290         if ((val & PIPECONF_ENABLE) == 0)
1291                 return;
1292
1293         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1294         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1295 }
1296
1297 /*
1298  * Plane regs are double buffered, going from enabled->disabled needs a
1299  * trigger in order to latch.  The display address reg provides this.
1300  */
1301 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1302                                       enum plane plane)
1303 {
1304         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1305         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1306 }
1307
1308 /**
1309  * intel_enable_plane - enable a display plane on a given pipe
1310  * @dev_priv: i915 private structure
1311  * @plane: plane to enable
1312  * @pipe: pipe being fed
1313  *
1314  * Enable @plane on @pipe, making sure that @pipe is running first.
1315  */
1316 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1317                                enum plane plane, enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321
1322         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1323         assert_pipe_enabled(dev_priv, pipe);
1324
1325         reg = DSPCNTR(plane);
1326         val = I915_READ(reg);
1327         if (val & DISPLAY_PLANE_ENABLE)
1328                 return;
1329
1330         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1331         intel_flush_display_plane(dev_priv, plane);
1332         intel_wait_for_vblank(dev_priv->dev, pipe);
1333 }
1334
1335 /**
1336  * intel_disable_plane - disable a display plane
1337  * @dev_priv: i915 private structure
1338  * @plane: plane to disable
1339  * @pipe: pipe consuming the data
1340  *
1341  * Disable @plane; should be an independent operation.
1342  */
1343 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1344                                 enum plane plane, enum pipe pipe)
1345 {
1346         int reg;
1347         u32 val;
1348
1349         reg = DSPCNTR(plane);
1350         val = I915_READ(reg);
1351         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1352                 return;
1353
1354         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1355         intel_flush_display_plane(dev_priv, plane);
1356         intel_wait_for_vblank(dev_priv->dev, pipe);
1357 }
1358
1359 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1360                            enum pipe pipe, int reg, u32 port_sel)
1361 {
1362         u32 val = I915_READ(reg);
1363         if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1364                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1365                 I915_WRITE(reg, val & ~DP_PORT_EN);
1366         }
1367 }
1368
1369 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1370                              enum pipe pipe, int reg)
1371 {
1372         u32 val = I915_READ(reg);
1373         if (HDMI_PIPE_ENABLED(val, pipe)) {
1374                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1375                               reg, pipe);
1376                 I915_WRITE(reg, val & ~PORT_ENABLE);
1377         }
1378 }
1379
1380 /* Disable any ports connected to this transcoder */
1381 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1382                                     enum pipe pipe)
1383 {
1384         u32 reg, val;
1385
1386         val = I915_READ(PCH_PP_CONTROL);
1387         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1388
1389         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1390         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1391         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1392
1393         reg = PCH_ADPA;
1394         val = I915_READ(reg);
1395         if (ADPA_PIPE_ENABLED(val, pipe))
1396                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1397
1398         reg = PCH_LVDS;
1399         val = I915_READ(reg);
1400         if (LVDS_PIPE_ENABLED(val, pipe)) {
1401                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1402                 POSTING_READ(reg);
1403                 udelay(100);
1404         }
1405
1406         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1407         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1408         disable_pch_hdmi(dev_priv, pipe, HDMID);
1409 }
1410
1411 static void i8xx_disable_fbc(struct drm_device *dev)
1412 {
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         u32 fbc_ctl;
1415
1416         /* Disable compression */
1417         fbc_ctl = I915_READ(FBC_CONTROL);
1418         if ((fbc_ctl & FBC_CTL_EN) == 0)
1419                 return;
1420
1421         fbc_ctl &= ~FBC_CTL_EN;
1422         I915_WRITE(FBC_CONTROL, fbc_ctl);
1423
1424         /* Wait for compressing bit to clear */
1425         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1426                 DRM_DEBUG_KMS("FBC idle timed out\n");
1427                 return;
1428         }
1429
1430         DRM_DEBUG_KMS("disabled FBC\n");
1431 }
1432
1433 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1434 {
1435         struct drm_device *dev = crtc->dev;
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437         struct drm_framebuffer *fb = crtc->fb;
1438         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1439         struct drm_i915_gem_object *obj = intel_fb->obj;
1440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1441         int cfb_pitch;
1442         int plane, i;
1443         u32 fbc_ctl, fbc_ctl2;
1444
1445         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1446         if (fb->pitch < cfb_pitch)
1447                 cfb_pitch = fb->pitch;
1448
1449         /* FBC_CTL wants 64B units */
1450         cfb_pitch = (cfb_pitch / 64) - 1;
1451         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1452
1453         /* Clear old tags */
1454         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1455                 I915_WRITE(FBC_TAG + (i * 4), 0);
1456
1457         /* Set it up... */
1458         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1459         fbc_ctl2 |= plane;
1460         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1461         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1462
1463         /* enable it... */
1464         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1465         if (IS_I945GM(dev))
1466                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1467         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1468         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1469         fbc_ctl |= obj->fence_reg;
1470         I915_WRITE(FBC_CONTROL, fbc_ctl);
1471
1472         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1473                       cfb_pitch, crtc->y, intel_crtc->plane);
1474 }
1475
1476 static bool i8xx_fbc_enabled(struct drm_device *dev)
1477 {
1478         struct drm_i915_private *dev_priv = dev->dev_private;
1479
1480         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1481 }
1482
1483 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1484 {
1485         struct drm_device *dev = crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         struct drm_framebuffer *fb = crtc->fb;
1488         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1489         struct drm_i915_gem_object *obj = intel_fb->obj;
1490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1491         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1492         unsigned long stall_watermark = 200;
1493         u32 dpfc_ctl;
1494
1495         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1496         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1497         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1498
1499         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1500                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1501                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1502         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1503
1504         /* enable it... */
1505         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1506
1507         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1508 }
1509
1510 static void g4x_disable_fbc(struct drm_device *dev)
1511 {
1512         struct drm_i915_private *dev_priv = dev->dev_private;
1513         u32 dpfc_ctl;
1514
1515         /* Disable compression */
1516         dpfc_ctl = I915_READ(DPFC_CONTROL);
1517         if (dpfc_ctl & DPFC_CTL_EN) {
1518                 dpfc_ctl &= ~DPFC_CTL_EN;
1519                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1520
1521                 DRM_DEBUG_KMS("disabled FBC\n");
1522         }
1523 }
1524
1525 static bool g4x_fbc_enabled(struct drm_device *dev)
1526 {
1527         struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1530 }
1531
1532 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1533 {
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         u32 blt_ecoskpd;
1536
1537         /* Make sure blitter notifies FBC of writes */
1538         gen6_gt_force_wake_get(dev_priv);
1539         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1540         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1541                 GEN6_BLITTER_LOCK_SHIFT;
1542         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1543         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1544         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1545         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1546                          GEN6_BLITTER_LOCK_SHIFT);
1547         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1549         gen6_gt_force_wake_put(dev_priv);
1550 }
1551
1552 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1553 {
1554         struct drm_device *dev = crtc->dev;
1555         struct drm_i915_private *dev_priv = dev->dev_private;
1556         struct drm_framebuffer *fb = crtc->fb;
1557         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1558         struct drm_i915_gem_object *obj = intel_fb->obj;
1559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1560         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1561         unsigned long stall_watermark = 200;
1562         u32 dpfc_ctl;
1563
1564         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1565         dpfc_ctl &= DPFC_RESERVED;
1566         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1567         /* Set persistent mode for front-buffer rendering, ala X. */
1568         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1569         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1570         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1571
1572         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1573                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1574                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1575         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1576         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1577         /* enable it... */
1578         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1579
1580         if (IS_GEN6(dev)) {
1581                 I915_WRITE(SNB_DPFC_CTL_SA,
1582                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1583                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1584                 sandybridge_blit_fbc_update(dev);
1585         }
1586
1587         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1588 }
1589
1590 static void ironlake_disable_fbc(struct drm_device *dev)
1591 {
1592         struct drm_i915_private *dev_priv = dev->dev_private;
1593         u32 dpfc_ctl;
1594
1595         /* Disable compression */
1596         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1597         if (dpfc_ctl & DPFC_CTL_EN) {
1598                 dpfc_ctl &= ~DPFC_CTL_EN;
1599                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1600
1601                 DRM_DEBUG_KMS("disabled FBC\n");
1602         }
1603 }
1604
1605 static bool ironlake_fbc_enabled(struct drm_device *dev)
1606 {
1607         struct drm_i915_private *dev_priv = dev->dev_private;
1608
1609         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1610 }
1611
1612 bool intel_fbc_enabled(struct drm_device *dev)
1613 {
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615
1616         if (!dev_priv->display.fbc_enabled)
1617                 return false;
1618
1619         return dev_priv->display.fbc_enabled(dev);
1620 }
1621
1622 static void intel_fbc_work_fn(struct work_struct *__work)
1623 {
1624         struct intel_fbc_work *work =
1625                 container_of(to_delayed_work(__work),
1626                              struct intel_fbc_work, work);
1627         struct drm_device *dev = work->crtc->dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630         mutex_lock(&dev->struct_mutex);
1631         if (work == dev_priv->fbc_work) {
1632                 /* Double check that we haven't switched fb without cancelling
1633                  * the prior work.
1634                  */
1635                 if (work->crtc->fb == work->fb) {
1636                         dev_priv->display.enable_fbc(work->crtc,
1637                                                      work->interval);
1638
1639                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1640                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1641                         dev_priv->cfb_y = work->crtc->y;
1642                 }
1643
1644                 dev_priv->fbc_work = NULL;
1645         }
1646         mutex_unlock(&dev->struct_mutex);
1647
1648         kfree(work);
1649 }
1650
1651 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1652 {
1653         if (dev_priv->fbc_work == NULL)
1654                 return;
1655
1656         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1657
1658         /* Synchronisation is provided by struct_mutex and checking of
1659          * dev_priv->fbc_work, so we can perform the cancellation
1660          * entirely asynchronously.
1661          */
1662         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1663                 /* tasklet was killed before being run, clean up */
1664                 kfree(dev_priv->fbc_work);
1665
1666         /* Mark the work as no longer wanted so that if it does
1667          * wake-up (because the work was already running and waiting
1668          * for our mutex), it will discover that is no longer
1669          * necessary to run.
1670          */
1671         dev_priv->fbc_work = NULL;
1672 }
1673
1674 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1675 {
1676         struct intel_fbc_work *work;
1677         struct drm_device *dev = crtc->dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679
1680         if (!dev_priv->display.enable_fbc)
1681                 return;
1682
1683         intel_cancel_fbc_work(dev_priv);
1684
1685         work = kzalloc(sizeof *work, GFP_KERNEL);
1686         if (work == NULL) {
1687                 dev_priv->display.enable_fbc(crtc, interval);
1688                 return;
1689         }
1690
1691         work->crtc = crtc;
1692         work->fb = crtc->fb;
1693         work->interval = interval;
1694         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1695
1696         dev_priv->fbc_work = work;
1697
1698         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1699
1700         /* Delay the actual enabling to let pageflipping cease and the
1701          * display to settle before starting the compression. Note that
1702          * this delay also serves a second purpose: it allows for a
1703          * vblank to pass after disabling the FBC before we attempt
1704          * to modify the control registers.
1705          *
1706          * A more complicated solution would involve tracking vblanks
1707          * following the termination of the page-flipping sequence
1708          * and indeed performing the enable as a co-routine and not
1709          * waiting synchronously upon the vblank.
1710          */
1711         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1712 }
1713
1714 void intel_disable_fbc(struct drm_device *dev)
1715 {
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718         intel_cancel_fbc_work(dev_priv);
1719
1720         if (!dev_priv->display.disable_fbc)
1721                 return;
1722
1723         dev_priv->display.disable_fbc(dev);
1724         dev_priv->cfb_plane = -1;
1725 }
1726
1727 /**
1728  * intel_update_fbc - enable/disable FBC as needed
1729  * @dev: the drm_device
1730  *
1731  * Set up the framebuffer compression hardware at mode set time.  We
1732  * enable it if possible:
1733  *   - plane A only (on pre-965)
1734  *   - no pixel mulitply/line duplication
1735  *   - no alpha buffer discard
1736  *   - no dual wide
1737  *   - framebuffer <= 2048 in width, 1536 in height
1738  *
1739  * We can't assume that any compression will take place (worst case),
1740  * so the compressed buffer has to be the same size as the uncompressed
1741  * one.  It also must reside (along with the line length buffer) in
1742  * stolen memory.
1743  *
1744  * We need to enable/disable FBC on a global basis.
1745  */
1746 static void intel_update_fbc(struct drm_device *dev)
1747 {
1748         struct drm_i915_private *dev_priv = dev->dev_private;
1749         struct drm_crtc *crtc = NULL, *tmp_crtc;
1750         struct intel_crtc *intel_crtc;
1751         struct drm_framebuffer *fb;
1752         struct intel_framebuffer *intel_fb;
1753         struct drm_i915_gem_object *obj;
1754
1755         DRM_DEBUG_KMS("\n");
1756
1757         if (!i915_powersave)
1758                 return;
1759
1760         if (!I915_HAS_FBC(dev))
1761                 return;
1762
1763         /*
1764          * If FBC is already on, we just have to verify that we can
1765          * keep it that way...
1766          * Need to disable if:
1767          *   - more than one pipe is active
1768          *   - changing FBC params (stride, fence, mode)
1769          *   - new fb is too large to fit in compressed buffer
1770          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1771          */
1772         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1773                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1774                         if (crtc) {
1775                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1776                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1777                                 goto out_disable;
1778                         }
1779                         crtc = tmp_crtc;
1780                 }
1781         }
1782
1783         if (!crtc || crtc->fb == NULL) {
1784                 DRM_DEBUG_KMS("no output, disabling\n");
1785                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1786                 goto out_disable;
1787         }
1788
1789         intel_crtc = to_intel_crtc(crtc);
1790         fb = crtc->fb;
1791         intel_fb = to_intel_framebuffer(fb);
1792         obj = intel_fb->obj;
1793
1794         if (!i915_enable_fbc) {
1795                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1796                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1797                 goto out_disable;
1798         }
1799         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1800                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1801                               "compression\n");
1802                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1803                 goto out_disable;
1804         }
1805         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1806             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1807                 DRM_DEBUG_KMS("mode incompatible with compression, "
1808                               "disabling\n");
1809                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1810                 goto out_disable;
1811         }
1812         if ((crtc->mode.hdisplay > 2048) ||
1813             (crtc->mode.vdisplay > 1536)) {
1814                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1815                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1816                 goto out_disable;
1817         }
1818         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1819                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1820                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1821                 goto out_disable;
1822         }
1823
1824         /* The use of a CPU fence is mandatory in order to detect writes
1825          * by the CPU to the scanout and trigger updates to the FBC.
1826          */
1827         if (obj->tiling_mode != I915_TILING_X ||
1828             obj->fence_reg == I915_FENCE_REG_NONE) {
1829                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1830                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1831                 goto out_disable;
1832         }
1833
1834         /* If the kernel debugger is active, always disable compression */
1835         if (in_dbg_master())
1836                 goto out_disable;
1837
1838         /* If the scanout has not changed, don't modify the FBC settings.
1839          * Note that we make the fundamental assumption that the fb->obj
1840          * cannot be unpinned (and have its GTT offset and fence revoked)
1841          * without first being decoupled from the scanout and FBC disabled.
1842          */
1843         if (dev_priv->cfb_plane == intel_crtc->plane &&
1844             dev_priv->cfb_fb == fb->base.id &&
1845             dev_priv->cfb_y == crtc->y)
1846                 return;
1847
1848         if (intel_fbc_enabled(dev)) {
1849                 /* We update FBC along two paths, after changing fb/crtc
1850                  * configuration (modeswitching) and after page-flipping
1851                  * finishes. For the latter, we know that not only did
1852                  * we disable the FBC at the start of the page-flip
1853                  * sequence, but also more than one vblank has passed.
1854                  *
1855                  * For the former case of modeswitching, it is possible
1856                  * to switch between two FBC valid configurations
1857                  * instantaneously so we do need to disable the FBC
1858                  * before we can modify its control registers. We also
1859                  * have to wait for the next vblank for that to take
1860                  * effect. However, since we delay enabling FBC we can
1861                  * assume that a vblank has passed since disabling and
1862                  * that we can safely alter the registers in the deferred
1863                  * callback.
1864                  *
1865                  * In the scenario that we go from a valid to invalid
1866                  * and then back to valid FBC configuration we have
1867                  * no strict enforcement that a vblank occurred since
1868                  * disabling the FBC. However, along all current pipe
1869                  * disabling paths we do need to wait for a vblank at
1870                  * some point. And we wait before enabling FBC anyway.
1871                  */
1872                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1873                 intel_disable_fbc(dev);
1874         }
1875
1876         intel_enable_fbc(crtc, 500);
1877         return;
1878
1879 out_disable:
1880         /* Multiple disables should be harmless */
1881         if (intel_fbc_enabled(dev)) {
1882                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1883                 intel_disable_fbc(dev);
1884         }
1885 }
1886
1887 int
1888 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1889                            struct drm_i915_gem_object *obj,
1890                            struct intel_ring_buffer *pipelined)
1891 {
1892         struct drm_i915_private *dev_priv = dev->dev_private;
1893         u32 alignment;
1894         int ret;
1895
1896         switch (obj->tiling_mode) {
1897         case I915_TILING_NONE:
1898                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1899                         alignment = 128 * 1024;
1900                 else if (INTEL_INFO(dev)->gen >= 4)
1901                         alignment = 4 * 1024;
1902                 else
1903                         alignment = 64 * 1024;
1904                 break;
1905         case I915_TILING_X:
1906                 /* pin() will align the object as required by fence */
1907                 alignment = 0;
1908                 break;
1909         case I915_TILING_Y:
1910                 /* FIXME: Is this true? */
1911                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1912                 return -EINVAL;
1913         default:
1914                 BUG();
1915         }
1916
1917         dev_priv->mm.interruptible = false;
1918         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1919         if (ret)
1920                 goto err_interruptible;
1921
1922         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1923          * fence, whereas 965+ only requires a fence if using
1924          * framebuffer compression.  For simplicity, we always install
1925          * a fence as the cost is not that onerous.
1926          */
1927         if (obj->tiling_mode != I915_TILING_NONE) {
1928                 ret = i915_gem_object_get_fence(obj, pipelined);
1929                 if (ret)
1930                         goto err_unpin;
1931         }
1932
1933         dev_priv->mm.interruptible = true;
1934         return 0;
1935
1936 err_unpin:
1937         i915_gem_object_unpin(obj);
1938 err_interruptible:
1939         dev_priv->mm.interruptible = true;
1940         return ret;
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944                              int x, int y)
1945 {
1946         struct drm_device *dev = crtc->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949         struct intel_framebuffer *intel_fb;
1950         struct drm_i915_gem_object *obj;
1951         int plane = intel_crtc->plane;
1952         unsigned long Start, Offset;
1953         u32 dspcntr;
1954         u32 reg;
1955
1956         switch (plane) {
1957         case 0:
1958         case 1:
1959                 break;
1960         default:
1961                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962                 return -EINVAL;
1963         }
1964
1965         intel_fb = to_intel_framebuffer(fb);
1966         obj = intel_fb->obj;
1967
1968         reg = DSPCNTR(plane);
1969         dspcntr = I915_READ(reg);
1970         /* Mask out pixel format bits in case we change it */
1971         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972         switch (fb->bits_per_pixel) {
1973         case 8:
1974                 dspcntr |= DISPPLANE_8BPP;
1975                 break;
1976         case 16:
1977                 if (fb->depth == 15)
1978                         dspcntr |= DISPPLANE_15_16BPP;
1979                 else
1980                         dspcntr |= DISPPLANE_16BPP;
1981                 break;
1982         case 24:
1983         case 32:
1984                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985                 break;
1986         default:
1987                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988                 return -EINVAL;
1989         }
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 if (obj->tiling_mode != I915_TILING_NONE)
1992                         dspcntr |= DISPPLANE_TILED;
1993                 else
1994                         dspcntr &= ~DISPPLANE_TILED;
1995         }
1996
1997         I915_WRITE(reg, dspcntr);
1998
1999         Start = obj->gtt_offset;
2000         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2001
2002         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003                       Start, Offset, x, y, fb->pitch);
2004         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2005         if (INTEL_INFO(dev)->gen >= 4) {
2006                 I915_WRITE(DSPSURF(plane), Start);
2007                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2008                 I915_WRITE(DSPADDR(plane), Offset);
2009         } else
2010                 I915_WRITE(DSPADDR(plane), Start + Offset);
2011         POSTING_READ(reg);
2012
2013         return 0;
2014 }
2015
2016 static int ironlake_update_plane(struct drm_crtc *crtc,
2017                                  struct drm_framebuffer *fb, int x, int y)
2018 {
2019         struct drm_device *dev = crtc->dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022         struct intel_framebuffer *intel_fb;
2023         struct drm_i915_gem_object *obj;
2024         int plane = intel_crtc->plane;
2025         unsigned long Start, Offset;
2026         u32 dspcntr;
2027         u32 reg;
2028
2029         switch (plane) {
2030         case 0:
2031         case 1:
2032                 break;
2033         default:
2034                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2035                 return -EINVAL;
2036         }
2037
2038         intel_fb = to_intel_framebuffer(fb);
2039         obj = intel_fb->obj;
2040
2041         reg = DSPCNTR(plane);
2042         dspcntr = I915_READ(reg);
2043         /* Mask out pixel format bits in case we change it */
2044         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2045         switch (fb->bits_per_pixel) {
2046         case 8:
2047                 dspcntr |= DISPPLANE_8BPP;
2048                 break;
2049         case 16:
2050                 if (fb->depth != 16)
2051                         return -EINVAL;
2052
2053                 dspcntr |= DISPPLANE_16BPP;
2054                 break;
2055         case 24:
2056         case 32:
2057                 if (fb->depth == 24)
2058                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2059                 else if (fb->depth == 30)
2060                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2061                 else
2062                         return -EINVAL;
2063                 break;
2064         default:
2065                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2066                 return -EINVAL;
2067         }
2068
2069         if (obj->tiling_mode != I915_TILING_NONE)
2070                 dspcntr |= DISPPLANE_TILED;
2071         else
2072                 dspcntr &= ~DISPPLANE_TILED;
2073
2074         /* must disable */
2075         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2076
2077         I915_WRITE(reg, dspcntr);
2078
2079         Start = obj->gtt_offset;
2080         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2081
2082         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2083                       Start, Offset, x, y, fb->pitch);
2084         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2085         I915_WRITE(DSPSURF(plane), Start);
2086         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2087         I915_WRITE(DSPADDR(plane), Offset);
2088         POSTING_READ(reg);
2089
2090         return 0;
2091 }
2092
2093 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2094 static int
2095 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2096                            int x, int y, enum mode_set_atomic state)
2097 {
2098         struct drm_device *dev = crtc->dev;
2099         struct drm_i915_private *dev_priv = dev->dev_private;
2100         int ret;
2101
2102         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2103         if (ret)
2104                 return ret;
2105
2106         intel_update_fbc(dev);
2107         intel_increase_pllclock(crtc);
2108
2109         return 0;
2110 }
2111
2112 static int
2113 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2114                     struct drm_framebuffer *old_fb)
2115 {
2116         struct drm_device *dev = crtc->dev;
2117         struct drm_i915_master_private *master_priv;
2118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119         int ret;
2120
2121         /* no fb bound */
2122         if (!crtc->fb) {
2123                 DRM_ERROR("No FB bound\n");
2124                 return 0;
2125         }
2126
2127         switch (intel_crtc->plane) {
2128         case 0:
2129         case 1:
2130                 break;
2131         default:
2132                 DRM_ERROR("no plane for crtc\n");
2133                 return -EINVAL;
2134         }
2135
2136         mutex_lock(&dev->struct_mutex);
2137         ret = intel_pin_and_fence_fb_obj(dev,
2138                                          to_intel_framebuffer(crtc->fb)->obj,
2139                                          NULL);
2140         if (ret != 0) {
2141                 mutex_unlock(&dev->struct_mutex);
2142                 DRM_ERROR("pin & fence failed\n");
2143                 return ret;
2144         }
2145
2146         if (old_fb) {
2147                 struct drm_i915_private *dev_priv = dev->dev_private;
2148                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2149
2150                 wait_event(dev_priv->pending_flip_queue,
2151                            atomic_read(&dev_priv->mm.wedged) ||
2152                            atomic_read(&obj->pending_flip) == 0);
2153
2154                 /* Big Hammer, we also need to ensure that any pending
2155                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2156                  * current scanout is retired before unpinning the old
2157                  * framebuffer.
2158                  *
2159                  * This should only fail upon a hung GPU, in which case we
2160                  * can safely continue.
2161                  */
2162                 ret = i915_gem_object_finish_gpu(obj);
2163                 (void) ret;
2164         }
2165
2166         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2167                                          LEAVE_ATOMIC_MODE_SET);
2168         if (ret) {
2169                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2170                 mutex_unlock(&dev->struct_mutex);
2171                 DRM_ERROR("failed to update base address\n");
2172                 return ret;
2173         }
2174
2175         if (old_fb) {
2176                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2177                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2178         }
2179
2180         mutex_unlock(&dev->struct_mutex);
2181
2182         if (!dev->primary->master)
2183                 return 0;
2184
2185         master_priv = dev->primary->master->driver_priv;
2186         if (!master_priv->sarea_priv)
2187                 return 0;
2188
2189         if (intel_crtc->pipe) {
2190                 master_priv->sarea_priv->pipeB_x = x;
2191                 master_priv->sarea_priv->pipeB_y = y;
2192         } else {
2193                 master_priv->sarea_priv->pipeA_x = x;
2194                 master_priv->sarea_priv->pipeA_y = y;
2195         }
2196
2197         return 0;
2198 }
2199
2200 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2201 {
2202         struct drm_device *dev = crtc->dev;
2203         struct drm_i915_private *dev_priv = dev->dev_private;
2204         u32 dpa_ctl;
2205
2206         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2207         dpa_ctl = I915_READ(DP_A);
2208         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2209
2210         if (clock < 200000) {
2211                 u32 temp;
2212                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2213                 /* workaround for 160Mhz:
2214                    1) program 0x4600c bits 15:0 = 0x8124
2215                    2) program 0x46010 bit 0 = 1
2216                    3) program 0x46034 bit 24 = 1
2217                    4) program 0x64000 bit 14 = 1
2218                    */
2219                 temp = I915_READ(0x4600c);
2220                 temp &= 0xffff0000;
2221                 I915_WRITE(0x4600c, temp | 0x8124);
2222
2223                 temp = I915_READ(0x46010);
2224                 I915_WRITE(0x46010, temp | 1);
2225
2226                 temp = I915_READ(0x46034);
2227                 I915_WRITE(0x46034, temp | (1 << 24));
2228         } else {
2229                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2230         }
2231         I915_WRITE(DP_A, dpa_ctl);
2232
2233         POSTING_READ(DP_A);
2234         udelay(500);
2235 }
2236
2237 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242         int pipe = intel_crtc->pipe;
2243         u32 reg, temp;
2244
2245         /* enable normal train */
2246         reg = FDI_TX_CTL(pipe);
2247         temp = I915_READ(reg);
2248         if (IS_IVYBRIDGE(dev)) {
2249                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2250                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2251         } else {
2252                 temp &= ~FDI_LINK_TRAIN_NONE;
2253                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2254         }
2255         I915_WRITE(reg, temp);
2256
2257         reg = FDI_RX_CTL(pipe);
2258         temp = I915_READ(reg);
2259         if (HAS_PCH_CPT(dev)) {
2260                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2261                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2262         } else {
2263                 temp &= ~FDI_LINK_TRAIN_NONE;
2264                 temp |= FDI_LINK_TRAIN_NONE;
2265         }
2266         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2267
2268         /* wait one idle pattern time */
2269         POSTING_READ(reg);
2270         udelay(1000);
2271
2272         /* IVB wants error correction enabled */
2273         if (IS_IVYBRIDGE(dev))
2274                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2275                            FDI_FE_ERRC_ENABLE);
2276 }
2277
2278 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2279 {
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281         u32 flags = I915_READ(SOUTH_CHICKEN1);
2282
2283         flags |= FDI_PHASE_SYNC_OVR(pipe);
2284         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2285         flags |= FDI_PHASE_SYNC_EN(pipe);
2286         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2287         POSTING_READ(SOUTH_CHICKEN1);
2288 }
2289
2290 /* The FDI link training functions for ILK/Ibexpeak. */
2291 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2292 {
2293         struct drm_device *dev = crtc->dev;
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296         int pipe = intel_crtc->pipe;
2297         int plane = intel_crtc->plane;
2298         u32 reg, temp, tries;
2299
2300         /* FDI needs bits from pipe & plane first */
2301         assert_pipe_enabled(dev_priv, pipe);
2302         assert_plane_enabled(dev_priv, plane);
2303
2304         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2305            for train result */
2306         reg = FDI_RX_IMR(pipe);
2307         temp = I915_READ(reg);
2308         temp &= ~FDI_RX_SYMBOL_LOCK;
2309         temp &= ~FDI_RX_BIT_LOCK;
2310         I915_WRITE(reg, temp);
2311         I915_READ(reg);
2312         udelay(150);
2313
2314         /* enable CPU FDI TX and PCH FDI RX */
2315         reg = FDI_TX_CTL(pipe);
2316         temp = I915_READ(reg);
2317         temp &= ~(7 << 19);
2318         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2319         temp &= ~FDI_LINK_TRAIN_NONE;
2320         temp |= FDI_LINK_TRAIN_PATTERN_1;
2321         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2322
2323         reg = FDI_RX_CTL(pipe);
2324         temp = I915_READ(reg);
2325         temp &= ~FDI_LINK_TRAIN_NONE;
2326         temp |= FDI_LINK_TRAIN_PATTERN_1;
2327         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2328
2329         POSTING_READ(reg);
2330         udelay(150);
2331
2332         /* Ironlake workaround, enable clock pointer after FDI enable*/
2333         if (HAS_PCH_IBX(dev)) {
2334                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2335                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2336                            FDI_RX_PHASE_SYNC_POINTER_EN);
2337         }
2338
2339         reg = FDI_RX_IIR(pipe);
2340         for (tries = 0; tries < 5; tries++) {
2341                 temp = I915_READ(reg);
2342                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2343
2344                 if ((temp & FDI_RX_BIT_LOCK)) {
2345                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2346                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2347                         break;
2348                 }
2349         }
2350         if (tries == 5)
2351                 DRM_ERROR("FDI train 1 fail!\n");
2352
2353         /* Train 2 */
2354         reg = FDI_TX_CTL(pipe);
2355         temp = I915_READ(reg);
2356         temp &= ~FDI_LINK_TRAIN_NONE;
2357         temp |= FDI_LINK_TRAIN_PATTERN_2;
2358         I915_WRITE(reg, temp);
2359
2360         reg = FDI_RX_CTL(pipe);
2361         temp = I915_READ(reg);
2362         temp &= ~FDI_LINK_TRAIN_NONE;
2363         temp |= FDI_LINK_TRAIN_PATTERN_2;
2364         I915_WRITE(reg, temp);
2365
2366         POSTING_READ(reg);
2367         udelay(150);
2368
2369         reg = FDI_RX_IIR(pipe);
2370         for (tries = 0; tries < 5; tries++) {
2371                 temp = I915_READ(reg);
2372                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2373
2374                 if (temp & FDI_RX_SYMBOL_LOCK) {
2375                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2376                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2377                         break;
2378                 }
2379         }
2380         if (tries == 5)
2381                 DRM_ERROR("FDI train 2 fail!\n");
2382
2383         DRM_DEBUG_KMS("FDI train done\n");
2384
2385 }
2386
2387 static const int snb_b_fdi_train_param [] = {
2388         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2389         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2390         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2391         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2392 };
2393
2394 /* The FDI link training functions for SNB/Cougarpoint. */
2395 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2396 {
2397         struct drm_device *dev = crtc->dev;
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400         int pipe = intel_crtc->pipe;
2401         u32 reg, temp, i;
2402
2403         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2404            for train result */
2405         reg = FDI_RX_IMR(pipe);
2406         temp = I915_READ(reg);
2407         temp &= ~FDI_RX_SYMBOL_LOCK;
2408         temp &= ~FDI_RX_BIT_LOCK;
2409         I915_WRITE(reg, temp);
2410
2411         POSTING_READ(reg);
2412         udelay(150);
2413
2414         /* enable CPU FDI TX and PCH FDI RX */
2415         reg = FDI_TX_CTL(pipe);
2416         temp = I915_READ(reg);
2417         temp &= ~(7 << 19);
2418         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2419         temp &= ~FDI_LINK_TRAIN_NONE;
2420         temp |= FDI_LINK_TRAIN_PATTERN_1;
2421         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2422         /* SNB-B */
2423         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2424         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2425
2426         reg = FDI_RX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         if (HAS_PCH_CPT(dev)) {
2429                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2430                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2431         } else {
2432                 temp &= ~FDI_LINK_TRAIN_NONE;
2433                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         }
2435         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437         POSTING_READ(reg);
2438         udelay(150);
2439
2440         if (HAS_PCH_CPT(dev))
2441                 cpt_phase_pointer_enable(dev, pipe);
2442
2443         for (i = 0; i < 4; i++ ) {
2444                 reg = FDI_TX_CTL(pipe);
2445                 temp = I915_READ(reg);
2446                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447                 temp |= snb_b_fdi_train_param[i];
2448                 I915_WRITE(reg, temp);
2449
2450                 POSTING_READ(reg);
2451                 udelay(500);
2452
2453                 reg = FDI_RX_IIR(pipe);
2454                 temp = I915_READ(reg);
2455                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2456
2457                 if (temp & FDI_RX_BIT_LOCK) {
2458                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2459                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2460                         break;
2461                 }
2462         }
2463         if (i == 4)
2464                 DRM_ERROR("FDI train 1 fail!\n");
2465
2466         /* Train 2 */
2467         reg = FDI_TX_CTL(pipe);
2468         temp = I915_READ(reg);
2469         temp &= ~FDI_LINK_TRAIN_NONE;
2470         temp |= FDI_LINK_TRAIN_PATTERN_2;
2471         if (IS_GEN6(dev)) {
2472                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473                 /* SNB-B */
2474                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2475         }
2476         I915_WRITE(reg, temp);
2477
2478         reg = FDI_RX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         if (HAS_PCH_CPT(dev)) {
2481                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2482                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2483         } else {
2484                 temp &= ~FDI_LINK_TRAIN_NONE;
2485                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2486         }
2487         I915_WRITE(reg, temp);
2488
2489         POSTING_READ(reg);
2490         udelay(150);
2491
2492         for (i = 0; i < 4; i++ ) {
2493                 reg = FDI_TX_CTL(pipe);
2494                 temp = I915_READ(reg);
2495                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2496                 temp |= snb_b_fdi_train_param[i];
2497                 I915_WRITE(reg, temp);
2498
2499                 POSTING_READ(reg);
2500                 udelay(500);
2501
2502                 reg = FDI_RX_IIR(pipe);
2503                 temp = I915_READ(reg);
2504                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505
2506                 if (temp & FDI_RX_SYMBOL_LOCK) {
2507                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2508                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2509                         break;
2510                 }
2511         }
2512         if (i == 4)
2513                 DRM_ERROR("FDI train 2 fail!\n");
2514
2515         DRM_DEBUG_KMS("FDI train done.\n");
2516 }
2517
2518 /* Manual link training for Ivy Bridge A0 parts */
2519 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2520 {
2521         struct drm_device *dev = crtc->dev;
2522         struct drm_i915_private *dev_priv = dev->dev_private;
2523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2524         int pipe = intel_crtc->pipe;
2525         u32 reg, temp, i;
2526
2527         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2528            for train result */
2529         reg = FDI_RX_IMR(pipe);
2530         temp = I915_READ(reg);
2531         temp &= ~FDI_RX_SYMBOL_LOCK;
2532         temp &= ~FDI_RX_BIT_LOCK;
2533         I915_WRITE(reg, temp);
2534
2535         POSTING_READ(reg);
2536         udelay(150);
2537
2538         /* enable CPU FDI TX and PCH FDI RX */
2539         reg = FDI_TX_CTL(pipe);
2540         temp = I915_READ(reg);
2541         temp &= ~(7 << 19);
2542         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2543         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2544         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2545         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2546         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2547         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2548
2549         reg = FDI_RX_CTL(pipe);
2550         temp = I915_READ(reg);
2551         temp &= ~FDI_LINK_TRAIN_AUTO;
2552         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2554         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         if (HAS_PCH_CPT(dev))
2560                 cpt_phase_pointer_enable(dev, pipe);
2561
2562         for (i = 0; i < 4; i++ ) {
2563                 reg = FDI_TX_CTL(pipe);
2564                 temp = I915_READ(reg);
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 temp |= snb_b_fdi_train_param[i];
2567                 I915_WRITE(reg, temp);
2568
2569                 POSTING_READ(reg);
2570                 udelay(500);
2571
2572                 reg = FDI_RX_IIR(pipe);
2573                 temp = I915_READ(reg);
2574                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575
2576                 if (temp & FDI_RX_BIT_LOCK ||
2577                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2578                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2579                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2580                         break;
2581                 }
2582         }
2583         if (i == 4)
2584                 DRM_ERROR("FDI train 1 fail!\n");
2585
2586         /* Train 2 */
2587         reg = FDI_TX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2590         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2591         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2593         I915_WRITE(reg, temp);
2594
2595         reg = FDI_RX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2599         I915_WRITE(reg, temp);
2600
2601         POSTING_READ(reg);
2602         udelay(150);
2603
2604         for (i = 0; i < 4; i++ ) {
2605                 reg = FDI_TX_CTL(pipe);
2606                 temp = I915_READ(reg);
2607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608                 temp |= snb_b_fdi_train_param[i];
2609                 I915_WRITE(reg, temp);
2610
2611                 POSTING_READ(reg);
2612                 udelay(500);
2613
2614                 reg = FDI_RX_IIR(pipe);
2615                 temp = I915_READ(reg);
2616                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617
2618                 if (temp & FDI_RX_SYMBOL_LOCK) {
2619                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2620                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2621                         break;
2622                 }
2623         }
2624         if (i == 4)
2625                 DRM_ERROR("FDI train 2 fail!\n");
2626
2627         DRM_DEBUG_KMS("FDI train done.\n");
2628 }
2629
2630 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2631 {
2632         struct drm_device *dev = crtc->dev;
2633         struct drm_i915_private *dev_priv = dev->dev_private;
2634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635         int pipe = intel_crtc->pipe;
2636         u32 reg, temp;
2637
2638         /* Write the TU size bits so error detection works */
2639         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2640                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2641
2642         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~((0x7 << 19) | (0x7 << 16));
2646         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2647         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2648         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2649
2650         POSTING_READ(reg);
2651         udelay(200);
2652
2653         /* Switch from Rawclk to PCDclk */
2654         temp = I915_READ(reg);
2655         I915_WRITE(reg, temp | FDI_PCDCLK);
2656
2657         POSTING_READ(reg);
2658         udelay(200);
2659
2660         /* Enable CPU FDI TX PLL, always on for Ironlake */
2661         reg = FDI_TX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2664                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2665
2666                 POSTING_READ(reg);
2667                 udelay(100);
2668         }
2669 }
2670
2671 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2672 {
2673         struct drm_i915_private *dev_priv = dev->dev_private;
2674         u32 flags = I915_READ(SOUTH_CHICKEN1);
2675
2676         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2677         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2678         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2679         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2680         POSTING_READ(SOUTH_CHICKEN1);
2681 }
2682 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2683 {
2684         struct drm_device *dev = crtc->dev;
2685         struct drm_i915_private *dev_priv = dev->dev_private;
2686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687         int pipe = intel_crtc->pipe;
2688         u32 reg, temp;
2689
2690         /* disable CPU FDI tx and PCH FDI rx */
2691         reg = FDI_TX_CTL(pipe);
2692         temp = I915_READ(reg);
2693         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2694         POSTING_READ(reg);
2695
2696         reg = FDI_RX_CTL(pipe);
2697         temp = I915_READ(reg);
2698         temp &= ~(0x7 << 16);
2699         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2700         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2701
2702         POSTING_READ(reg);
2703         udelay(100);
2704
2705         /* Ironlake workaround, disable clock pointer after downing FDI */
2706         if (HAS_PCH_IBX(dev)) {
2707                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2708                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2709                            I915_READ(FDI_RX_CHICKEN(pipe) &
2710                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2711         } else if (HAS_PCH_CPT(dev)) {
2712                 cpt_phase_pointer_disable(dev, pipe);
2713         }
2714
2715         /* still set train pattern 1 */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_LINK_TRAIN_NONE;
2719         temp |= FDI_LINK_TRAIN_PATTERN_1;
2720         I915_WRITE(reg, temp);
2721
2722         reg = FDI_RX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         if (HAS_PCH_CPT(dev)) {
2725                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2727         } else {
2728                 temp &= ~FDI_LINK_TRAIN_NONE;
2729                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2730         }
2731         /* BPC in FDI rx is consistent with that in PIPECONF */
2732         temp &= ~(0x07 << 16);
2733         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2734         I915_WRITE(reg, temp);
2735
2736         POSTING_READ(reg);
2737         udelay(100);
2738 }
2739
2740 /*
2741  * When we disable a pipe, we need to clear any pending scanline wait events
2742  * to avoid hanging the ring, which we assume we are waiting on.
2743  */
2744 static void intel_clear_scanline_wait(struct drm_device *dev)
2745 {
2746         struct drm_i915_private *dev_priv = dev->dev_private;
2747         struct intel_ring_buffer *ring;
2748         u32 tmp;
2749
2750         if (IS_GEN2(dev))
2751                 /* Can't break the hang on i8xx */
2752                 return;
2753
2754         ring = LP_RING(dev_priv);
2755         tmp = I915_READ_CTL(ring);
2756         if (tmp & RING_WAIT)
2757                 I915_WRITE_CTL(ring, tmp);
2758 }
2759
2760 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2761 {
2762         struct drm_i915_gem_object *obj;
2763         struct drm_i915_private *dev_priv;
2764
2765         if (crtc->fb == NULL)
2766                 return;
2767
2768         obj = to_intel_framebuffer(crtc->fb)->obj;
2769         dev_priv = crtc->dev->dev_private;
2770         wait_event(dev_priv->pending_flip_queue,
2771                    atomic_read(&obj->pending_flip) == 0);
2772 }
2773
2774 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2775 {
2776         struct drm_device *dev = crtc->dev;
2777         struct drm_mode_config *mode_config = &dev->mode_config;
2778         struct intel_encoder *encoder;
2779
2780         /*
2781          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2782          * must be driven by its own crtc; no sharing is possible.
2783          */
2784         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2785                 if (encoder->base.crtc != crtc)
2786                         continue;
2787
2788                 switch (encoder->type) {
2789                 case INTEL_OUTPUT_EDP:
2790                         if (!intel_encoder_is_pch_edp(&encoder->base))
2791                                 return false;
2792                         continue;
2793                 }
2794         }
2795
2796         return true;
2797 }
2798
2799 /*
2800  * Enable PCH resources required for PCH ports:
2801  *   - PCH PLLs
2802  *   - FDI training & RX/TX
2803  *   - update transcoder timings
2804  *   - DP transcoding bits
2805  *   - transcoder
2806  */
2807 static void ironlake_pch_enable(struct drm_crtc *crtc)
2808 {
2809         struct drm_device *dev = crtc->dev;
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2812         int pipe = intel_crtc->pipe;
2813         u32 reg, temp;
2814
2815         /* For PCH output, training FDI link */
2816         dev_priv->display.fdi_link_train(crtc);
2817
2818         intel_enable_pch_pll(dev_priv, pipe);
2819
2820         if (HAS_PCH_CPT(dev)) {
2821                 /* Be sure PCH DPLL SEL is set */
2822                 temp = I915_READ(PCH_DPLL_SEL);
2823                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2824                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2825                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2826                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2827                 I915_WRITE(PCH_DPLL_SEL, temp);
2828         }
2829
2830         /* set transcoder timing, panel must allow it */
2831         assert_panel_unlocked(dev_priv, pipe);
2832         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2833         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2834         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2835
2836         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2837         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2838         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2839
2840         intel_fdi_normal_train(crtc);
2841
2842         /* For PCH DP, enable TRANS_DP_CTL */
2843         if (HAS_PCH_CPT(dev) &&
2844             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2845                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2846                 reg = TRANS_DP_CTL(pipe);
2847                 temp = I915_READ(reg);
2848                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2849                           TRANS_DP_SYNC_MASK |
2850                           TRANS_DP_BPC_MASK);
2851                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2852                          TRANS_DP_ENH_FRAMING);
2853                 temp |= bpc << 9; /* same format but at 11:9 */
2854
2855                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2856                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2857                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2858                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2859
2860                 switch (intel_trans_dp_port_sel(crtc)) {
2861                 case PCH_DP_B:
2862                         temp |= TRANS_DP_PORT_SEL_B;
2863                         break;
2864                 case PCH_DP_C:
2865                         temp |= TRANS_DP_PORT_SEL_C;
2866                         break;
2867                 case PCH_DP_D:
2868                         temp |= TRANS_DP_PORT_SEL_D;
2869                         break;
2870                 default:
2871                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2872                         temp |= TRANS_DP_PORT_SEL_B;
2873                         break;
2874                 }
2875
2876                 I915_WRITE(reg, temp);
2877         }
2878
2879         intel_enable_transcoder(dev_priv, pipe);
2880 }
2881
2882 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2883 {
2884         struct drm_device *dev = crtc->dev;
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2887         int pipe = intel_crtc->pipe;
2888         int plane = intel_crtc->plane;
2889         u32 temp;
2890         bool is_pch_port;
2891
2892         if (intel_crtc->active)
2893                 return;
2894
2895         intel_crtc->active = true;
2896         intel_update_watermarks(dev);
2897
2898         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2899                 temp = I915_READ(PCH_LVDS);
2900                 if ((temp & LVDS_PORT_EN) == 0)
2901                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2902         }
2903
2904         is_pch_port = intel_crtc_driving_pch(crtc);
2905
2906         if (is_pch_port)
2907                 ironlake_fdi_pll_enable(crtc);
2908         else
2909                 ironlake_fdi_disable(crtc);
2910
2911         /* Enable panel fitting for LVDS */
2912         if (dev_priv->pch_pf_size &&
2913             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2914                 /* Force use of hard-coded filter coefficients
2915                  * as some pre-programmed values are broken,
2916                  * e.g. x201.
2917                  */
2918                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2919                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2920                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2921         }
2922
2923         /*
2924          * On ILK+ LUT must be loaded before the pipe is running but with
2925          * clocks enabled
2926          */
2927         intel_crtc_load_lut(crtc);
2928
2929         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2930         intel_enable_plane(dev_priv, plane, pipe);
2931
2932         if (is_pch_port)
2933                 ironlake_pch_enable(crtc);
2934
2935         mutex_lock(&dev->struct_mutex);
2936         intel_update_fbc(dev);
2937         mutex_unlock(&dev->struct_mutex);
2938
2939         intel_crtc_update_cursor(crtc, true);
2940 }
2941
2942 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2943 {
2944         struct drm_device *dev = crtc->dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947         int pipe = intel_crtc->pipe;
2948         int plane = intel_crtc->plane;
2949         u32 reg, temp;
2950
2951         if (!intel_crtc->active)
2952                 return;
2953
2954         intel_crtc_wait_for_pending_flips(crtc);
2955         drm_vblank_off(dev, pipe);
2956         intel_crtc_update_cursor(crtc, false);
2957
2958         intel_disable_plane(dev_priv, plane, pipe);
2959
2960         if (dev_priv->cfb_plane == plane)
2961                 intel_disable_fbc(dev);
2962
2963         intel_disable_pipe(dev_priv, pipe);
2964
2965         /* Disable PF */
2966         I915_WRITE(PF_CTL(pipe), 0);
2967         I915_WRITE(PF_WIN_SZ(pipe), 0);
2968
2969         ironlake_fdi_disable(crtc);
2970
2971         /* This is a horrible layering violation; we should be doing this in
2972          * the connector/encoder ->prepare instead, but we don't always have
2973          * enough information there about the config to know whether it will
2974          * actually be necessary or just cause undesired flicker.
2975          */
2976         intel_disable_pch_ports(dev_priv, pipe);
2977
2978         intel_disable_transcoder(dev_priv, pipe);
2979
2980         if (HAS_PCH_CPT(dev)) {
2981                 /* disable TRANS_DP_CTL */
2982                 reg = TRANS_DP_CTL(pipe);
2983                 temp = I915_READ(reg);
2984                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2985                 temp |= TRANS_DP_PORT_SEL_NONE;
2986                 I915_WRITE(reg, temp);
2987
2988                 /* disable DPLL_SEL */
2989                 temp = I915_READ(PCH_DPLL_SEL);
2990                 switch (pipe) {
2991                 case 0:
2992                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2993                         break;
2994                 case 1:
2995                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2996                         break;
2997                 case 2:
2998                         /* FIXME: manage transcoder PLLs? */
2999                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3000                         break;
3001                 default:
3002                         BUG(); /* wtf */
3003                 }
3004                 I915_WRITE(PCH_DPLL_SEL, temp);
3005         }
3006
3007         /* disable PCH DPLL */
3008         intel_disable_pch_pll(dev_priv, pipe);
3009
3010         /* Switch from PCDclk to Rawclk */
3011         reg = FDI_RX_CTL(pipe);
3012         temp = I915_READ(reg);
3013         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3014
3015         /* Disable CPU FDI TX PLL */
3016         reg = FDI_TX_CTL(pipe);
3017         temp = I915_READ(reg);
3018         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3019
3020         POSTING_READ(reg);
3021         udelay(100);
3022
3023         reg = FDI_RX_CTL(pipe);
3024         temp = I915_READ(reg);
3025         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3026
3027         /* Wait for the clocks to turn off. */
3028         POSTING_READ(reg);
3029         udelay(100);
3030
3031         intel_crtc->active = false;
3032         intel_update_watermarks(dev);
3033
3034         mutex_lock(&dev->struct_mutex);
3035         intel_update_fbc(dev);
3036         intel_clear_scanline_wait(dev);
3037         mutex_unlock(&dev->struct_mutex);
3038 }
3039
3040 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3041 {
3042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043         int pipe = intel_crtc->pipe;
3044         int plane = intel_crtc->plane;
3045
3046         /* XXX: When our outputs are all unaware of DPMS modes other than off
3047          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3048          */
3049         switch (mode) {
3050         case DRM_MODE_DPMS_ON:
3051         case DRM_MODE_DPMS_STANDBY:
3052         case DRM_MODE_DPMS_SUSPEND:
3053                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3054                 ironlake_crtc_enable(crtc);
3055                 break;
3056
3057         case DRM_MODE_DPMS_OFF:
3058                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3059                 ironlake_crtc_disable(crtc);
3060                 break;
3061         }
3062 }
3063
3064 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3065 {
3066         if (!enable && intel_crtc->overlay) {
3067                 struct drm_device *dev = intel_crtc->base.dev;
3068                 struct drm_i915_private *dev_priv = dev->dev_private;
3069
3070                 mutex_lock(&dev->struct_mutex);
3071                 dev_priv->mm.interruptible = false;
3072                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3073                 dev_priv->mm.interruptible = true;
3074                 mutex_unlock(&dev->struct_mutex);
3075         }
3076
3077         /* Let userspace switch the overlay on again. In most cases userspace
3078          * has to recompute where to put it anyway.
3079          */
3080 }
3081
3082 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         int plane = intel_crtc->plane;
3089
3090         if (intel_crtc->active)
3091                 return;
3092
3093         intel_crtc->active = true;
3094         intel_update_watermarks(dev);
3095
3096         intel_enable_pll(dev_priv, pipe);
3097         intel_enable_pipe(dev_priv, pipe, false);
3098         intel_enable_plane(dev_priv, plane, pipe);
3099
3100         intel_crtc_load_lut(crtc);
3101         intel_update_fbc(dev);
3102
3103         /* Give the overlay scaler a chance to enable if it's on this pipe */
3104         intel_crtc_dpms_overlay(intel_crtc, true);
3105         intel_crtc_update_cursor(crtc, true);
3106 }
3107
3108 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3109 {
3110         struct drm_device *dev = crtc->dev;
3111         struct drm_i915_private *dev_priv = dev->dev_private;
3112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3113         int pipe = intel_crtc->pipe;
3114         int plane = intel_crtc->plane;
3115
3116         if (!intel_crtc->active)
3117                 return;
3118
3119         /* Give the overlay scaler a chance to disable if it's on this pipe */
3120         intel_crtc_wait_for_pending_flips(crtc);
3121         drm_vblank_off(dev, pipe);
3122         intel_crtc_dpms_overlay(intel_crtc, false);
3123         intel_crtc_update_cursor(crtc, false);
3124
3125         if (dev_priv->cfb_plane == plane)
3126                 intel_disable_fbc(dev);
3127
3128         intel_disable_plane(dev_priv, plane, pipe);
3129         intel_disable_pipe(dev_priv, pipe);
3130         intel_disable_pll(dev_priv, pipe);
3131
3132         intel_crtc->active = false;
3133         intel_update_fbc(dev);
3134         intel_update_watermarks(dev);
3135         intel_clear_scanline_wait(dev);
3136 }
3137
3138 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3139 {
3140         /* XXX: When our outputs are all unaware of DPMS modes other than off
3141          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3142          */
3143         switch (mode) {
3144         case DRM_MODE_DPMS_ON:
3145         case DRM_MODE_DPMS_STANDBY:
3146         case DRM_MODE_DPMS_SUSPEND:
3147                 i9xx_crtc_enable(crtc);
3148                 break;
3149         case DRM_MODE_DPMS_OFF:
3150                 i9xx_crtc_disable(crtc);
3151                 break;
3152         }
3153 }
3154
3155 /**
3156  * Sets the power management mode of the pipe and plane.
3157  */
3158 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3159 {
3160         struct drm_device *dev = crtc->dev;
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162         struct drm_i915_master_private *master_priv;
3163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3164         int pipe = intel_crtc->pipe;
3165         bool enabled;
3166
3167         if (intel_crtc->dpms_mode == mode)
3168                 return;
3169
3170         intel_crtc->dpms_mode = mode;
3171
3172         dev_priv->display.dpms(crtc, mode);
3173
3174         if (!dev->primary->master)
3175                 return;
3176
3177         master_priv = dev->primary->master->driver_priv;
3178         if (!master_priv->sarea_priv)
3179                 return;
3180
3181         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3182
3183         switch (pipe) {
3184         case 0:
3185                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3186                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3187                 break;
3188         case 1:
3189                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3190                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3191                 break;
3192         default:
3193                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3194                 break;
3195         }
3196 }
3197
3198 static void intel_crtc_disable(struct drm_crtc *crtc)
3199 {
3200         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3201         struct drm_device *dev = crtc->dev;
3202
3203         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3204
3205         if (crtc->fb) {
3206                 mutex_lock(&dev->struct_mutex);
3207                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3208                 mutex_unlock(&dev->struct_mutex);
3209         }
3210 }
3211
3212 /* Prepare for a mode set.
3213  *
3214  * Note we could be a lot smarter here.  We need to figure out which outputs
3215  * will be enabled, which disabled (in short, how the config will changes)
3216  * and perform the minimum necessary steps to accomplish that, e.g. updating
3217  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3218  * panel fitting is in the proper state, etc.
3219  */
3220 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3221 {
3222         i9xx_crtc_disable(crtc);
3223 }
3224
3225 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3226 {
3227         i9xx_crtc_enable(crtc);
3228 }
3229
3230 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3231 {
3232         ironlake_crtc_disable(crtc);
3233 }
3234
3235 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3236 {
3237         ironlake_crtc_enable(crtc);
3238 }
3239
3240 void intel_encoder_prepare (struct drm_encoder *encoder)
3241 {
3242         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3243         /* lvds has its own version of prepare see intel_lvds_prepare */
3244         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3245 }
3246
3247 void intel_encoder_commit (struct drm_encoder *encoder)
3248 {
3249         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3250         /* lvds has its own version of commit see intel_lvds_commit */
3251         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3252 }
3253
3254 void intel_encoder_destroy(struct drm_encoder *encoder)
3255 {
3256         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3257
3258         drm_encoder_cleanup(encoder);
3259         kfree(intel_encoder);
3260 }
3261
3262 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3263                                   struct drm_display_mode *mode,
3264                                   struct drm_display_mode *adjusted_mode)
3265 {
3266         struct drm_device *dev = crtc->dev;
3267
3268         if (HAS_PCH_SPLIT(dev)) {
3269                 /* FDI link clock is fixed at 2.7G */
3270                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3271                         return false;
3272         }
3273
3274         /* XXX some encoders set the crtcinfo, others don't.
3275          * Obviously we need some form of conflict resolution here...
3276          */
3277         if (adjusted_mode->crtc_htotal == 0)
3278                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3279
3280         return true;
3281 }
3282
3283 static int i945_get_display_clock_speed(struct drm_device *dev)
3284 {
3285         return 400000;
3286 }
3287
3288 static int i915_get_display_clock_speed(struct drm_device *dev)
3289 {
3290         return 333000;
3291 }
3292
3293 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3294 {
3295         return 200000;
3296 }
3297
3298 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3299 {
3300         u16 gcfgc = 0;
3301
3302         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3303
3304         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3305                 return 133000;
3306         else {
3307                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3308                 case GC_DISPLAY_CLOCK_333_MHZ:
3309                         return 333000;
3310                 default:
3311                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3312                         return 190000;
3313                 }
3314         }
3315 }
3316
3317 static int i865_get_display_clock_speed(struct drm_device *dev)
3318 {
3319         return 266000;
3320 }
3321
3322 static int i855_get_display_clock_speed(struct drm_device *dev)
3323 {
3324         u16 hpllcc = 0;
3325         /* Assume that the hardware is in the high speed state.  This
3326          * should be the default.
3327          */
3328         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3329         case GC_CLOCK_133_200:
3330         case GC_CLOCK_100_200:
3331                 return 200000;
3332         case GC_CLOCK_166_250:
3333                 return 250000;
3334         case GC_CLOCK_100_133:
3335                 return 133000;
3336         }
3337
3338         /* Shouldn't happen */
3339         return 0;
3340 }
3341
3342 static int i830_get_display_clock_speed(struct drm_device *dev)
3343 {
3344         return 133000;
3345 }
3346
3347 struct fdi_m_n {
3348         u32        tu;
3349         u32        gmch_m;
3350         u32        gmch_n;
3351         u32        link_m;
3352         u32        link_n;
3353 };
3354
3355 static void
3356 fdi_reduce_ratio(u32 *num, u32 *den)
3357 {
3358         while (*num > 0xffffff || *den > 0xffffff) {
3359                 *num >>= 1;
3360                 *den >>= 1;
3361         }
3362 }
3363
3364 static void
3365 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3366                      int link_clock, struct fdi_m_n *m_n)
3367 {
3368         m_n->tu = 64; /* default size */
3369
3370         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3371         m_n->gmch_m = bits_per_pixel * pixel_clock;
3372         m_n->gmch_n = link_clock * nlanes * 8;
3373         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3374
3375         m_n->link_m = pixel_clock;
3376         m_n->link_n = link_clock;
3377         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3378 }
3379
3380
3381 struct intel_watermark_params {
3382         unsigned long fifo_size;
3383         unsigned long max_wm;
3384         unsigned long default_wm;
3385         unsigned long guard_size;
3386         unsigned long cacheline_size;
3387 };
3388
3389 /* Pineview has different values for various configs */
3390 static const struct intel_watermark_params pineview_display_wm = {
3391         PINEVIEW_DISPLAY_FIFO,
3392         PINEVIEW_MAX_WM,
3393         PINEVIEW_DFT_WM,
3394         PINEVIEW_GUARD_WM,
3395         PINEVIEW_FIFO_LINE_SIZE
3396 };
3397 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3398         PINEVIEW_DISPLAY_FIFO,
3399         PINEVIEW_MAX_WM,
3400         PINEVIEW_DFT_HPLLOFF_WM,
3401         PINEVIEW_GUARD_WM,
3402         PINEVIEW_FIFO_LINE_SIZE
3403 };
3404 static const struct intel_watermark_params pineview_cursor_wm = {
3405         PINEVIEW_CURSOR_FIFO,
3406         PINEVIEW_CURSOR_MAX_WM,
3407         PINEVIEW_CURSOR_DFT_WM,
3408         PINEVIEW_CURSOR_GUARD_WM,
3409         PINEVIEW_FIFO_LINE_SIZE,
3410 };
3411 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3412         PINEVIEW_CURSOR_FIFO,
3413         PINEVIEW_CURSOR_MAX_WM,
3414         PINEVIEW_CURSOR_DFT_WM,
3415         PINEVIEW_CURSOR_GUARD_WM,
3416         PINEVIEW_FIFO_LINE_SIZE
3417 };
3418 static const struct intel_watermark_params g4x_wm_info = {
3419         G4X_FIFO_SIZE,
3420         G4X_MAX_WM,
3421         G4X_MAX_WM,
3422         2,
3423         G4X_FIFO_LINE_SIZE,
3424 };
3425 static const struct intel_watermark_params g4x_cursor_wm_info = {
3426         I965_CURSOR_FIFO,
3427         I965_CURSOR_MAX_WM,
3428         I965_CURSOR_DFT_WM,
3429         2,
3430         G4X_FIFO_LINE_SIZE,
3431 };
3432 static const struct intel_watermark_params i965_cursor_wm_info = {
3433         I965_CURSOR_FIFO,
3434         I965_CURSOR_MAX_WM,
3435         I965_CURSOR_DFT_WM,
3436         2,
3437         I915_FIFO_LINE_SIZE,
3438 };
3439 static const struct intel_watermark_params i945_wm_info = {
3440         I945_FIFO_SIZE,
3441         I915_MAX_WM,
3442         1,
3443         2,
3444         I915_FIFO_LINE_SIZE
3445 };
3446 static const struct intel_watermark_params i915_wm_info = {
3447         I915_FIFO_SIZE,
3448         I915_MAX_WM,
3449         1,
3450         2,
3451         I915_FIFO_LINE_SIZE
3452 };
3453 static const struct intel_watermark_params i855_wm_info = {
3454         I855GM_FIFO_SIZE,
3455         I915_MAX_WM,
3456         1,
3457         2,
3458         I830_FIFO_LINE_SIZE
3459 };
3460 static const struct intel_watermark_params i830_wm_info = {
3461         I830_FIFO_SIZE,
3462         I915_MAX_WM,
3463         1,
3464         2,
3465         I830_FIFO_LINE_SIZE
3466 };
3467
3468 static const struct intel_watermark_params ironlake_display_wm_info = {
3469         ILK_DISPLAY_FIFO,
3470         ILK_DISPLAY_MAXWM,
3471         ILK_DISPLAY_DFTWM,
3472         2,
3473         ILK_FIFO_LINE_SIZE
3474 };
3475 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3476         ILK_CURSOR_FIFO,
3477         ILK_CURSOR_MAXWM,
3478         ILK_CURSOR_DFTWM,
3479         2,
3480         ILK_FIFO_LINE_SIZE
3481 };
3482 static const struct intel_watermark_params ironlake_display_srwm_info = {
3483         ILK_DISPLAY_SR_FIFO,
3484         ILK_DISPLAY_MAX_SRWM,
3485         ILK_DISPLAY_DFT_SRWM,
3486         2,
3487         ILK_FIFO_LINE_SIZE
3488 };
3489 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3490         ILK_CURSOR_SR_FIFO,
3491         ILK_CURSOR_MAX_SRWM,
3492         ILK_CURSOR_DFT_SRWM,
3493         2,
3494         ILK_FIFO_LINE_SIZE
3495 };
3496
3497 static const struct intel_watermark_params sandybridge_display_wm_info = {
3498         SNB_DISPLAY_FIFO,
3499         SNB_DISPLAY_MAXWM,
3500         SNB_DISPLAY_DFTWM,
3501         2,
3502         SNB_FIFO_LINE_SIZE
3503 };
3504 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3505         SNB_CURSOR_FIFO,
3506         SNB_CURSOR_MAXWM,
3507         SNB_CURSOR_DFTWM,
3508         2,
3509         SNB_FIFO_LINE_SIZE
3510 };
3511 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3512         SNB_DISPLAY_SR_FIFO,
3513         SNB_DISPLAY_MAX_SRWM,
3514         SNB_DISPLAY_DFT_SRWM,
3515         2,
3516         SNB_FIFO_LINE_SIZE
3517 };
3518 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3519         SNB_CURSOR_SR_FIFO,
3520         SNB_CURSOR_MAX_SRWM,
3521         SNB_CURSOR_DFT_SRWM,
3522         2,
3523         SNB_FIFO_LINE_SIZE
3524 };
3525
3526
3527 /**
3528  * intel_calculate_wm - calculate watermark level
3529  * @clock_in_khz: pixel clock
3530  * @wm: chip FIFO params
3531  * @pixel_size: display pixel size
3532  * @latency_ns: memory latency for the platform
3533  *
3534  * Calculate the watermark level (the level at which the display plane will
3535  * start fetching from memory again).  Each chip has a different display
3536  * FIFO size and allocation, so the caller needs to figure that out and pass
3537  * in the correct intel_watermark_params structure.
3538  *
3539  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3540  * on the pixel size.  When it reaches the watermark level, it'll start
3541  * fetching FIFO line sized based chunks from memory until the FIFO fills
3542  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3543  * will occur, and a display engine hang could result.
3544  */
3545 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3546                                         const struct intel_watermark_params *wm,
3547                                         int fifo_size,
3548                                         int pixel_size,
3549                                         unsigned long latency_ns)
3550 {
3551         long entries_required, wm_size;
3552
3553         /*
3554          * Note: we need to make sure we don't overflow for various clock &
3555          * latency values.
3556          * clocks go from a few thousand to several hundred thousand.
3557          * latency is usually a few thousand
3558          */
3559         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3560                 1000;
3561         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3562
3563         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3564
3565         wm_size = fifo_size - (entries_required + wm->guard_size);
3566
3567         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3568
3569         /* Don't promote wm_size to unsigned... */
3570         if (wm_size > (long)wm->max_wm)
3571                 wm_size = wm->max_wm;
3572         if (wm_size <= 0)
3573                 wm_size = wm->default_wm;
3574         return wm_size;
3575 }
3576
3577 struct cxsr_latency {
3578         int is_desktop;
3579         int is_ddr3;
3580         unsigned long fsb_freq;
3581         unsigned long mem_freq;
3582         unsigned long display_sr;
3583         unsigned long display_hpll_disable;
3584         unsigned long cursor_sr;
3585         unsigned long cursor_hpll_disable;
3586 };
3587
3588 static const struct cxsr_latency cxsr_latency_table[] = {
3589         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3590         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3591         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3592         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3593         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3594
3595         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3596         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3597         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3598         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3599         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3600
3601         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3602         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3603         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3604         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3605         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3606
3607         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3608         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3609         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3610         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3611         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3612
3613         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3614         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3615         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3616         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3617         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3618
3619         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3620         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3621         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3622         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3623         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3624 };
3625
3626 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3627                                                          int is_ddr3,
3628                                                          int fsb,
3629                                                          int mem)
3630 {
3631         const struct cxsr_latency *latency;
3632         int i;
3633
3634         if (fsb == 0 || mem == 0)
3635                 return NULL;
3636
3637         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3638                 latency = &cxsr_latency_table[i];
3639                 if (is_desktop == latency->is_desktop &&
3640                     is_ddr3 == latency->is_ddr3 &&
3641                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3642                         return latency;
3643         }
3644
3645         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3646
3647         return NULL;
3648 }
3649
3650 static void pineview_disable_cxsr(struct drm_device *dev)
3651 {
3652         struct drm_i915_private *dev_priv = dev->dev_private;
3653
3654         /* deactivate cxsr */
3655         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3656 }
3657
3658 /*
3659  * Latency for FIFO fetches is dependent on several factors:
3660  *   - memory configuration (speed, channels)
3661  *   - chipset
3662  *   - current MCH state
3663  * It can be fairly high in some situations, so here we assume a fairly
3664  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3665  * set this value too high, the FIFO will fetch frequently to stay full)
3666  * and power consumption (set it too low to save power and we might see
3667  * FIFO underruns and display "flicker").
3668  *
3669  * A value of 5us seems to be a good balance; safe for very low end
3670  * platforms but not overly aggressive on lower latency configs.
3671  */
3672 static const int latency_ns = 5000;
3673
3674 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3675 {
3676         struct drm_i915_private *dev_priv = dev->dev_private;
3677         uint32_t dsparb = I915_READ(DSPARB);
3678         int size;
3679
3680         size = dsparb & 0x7f;
3681         if (plane)
3682                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3683
3684         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3685                       plane ? "B" : "A", size);
3686
3687         return size;
3688 }
3689
3690 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3691 {
3692         struct drm_i915_private *dev_priv = dev->dev_private;
3693         uint32_t dsparb = I915_READ(DSPARB);
3694         int size;
3695
3696         size = dsparb & 0x1ff;
3697         if (plane)
3698                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3699         size >>= 1; /* Convert to cachelines */
3700
3701         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3702                       plane ? "B" : "A", size);
3703
3704         return size;
3705 }
3706
3707 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3708 {
3709         struct drm_i915_private *dev_priv = dev->dev_private;
3710         uint32_t dsparb = I915_READ(DSPARB);
3711         int size;
3712
3713         size = dsparb & 0x7f;
3714         size >>= 2; /* Convert to cachelines */
3715
3716         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3717                       plane ? "B" : "A",
3718                       size);
3719
3720         return size;
3721 }
3722
3723 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3724 {
3725         struct drm_i915_private *dev_priv = dev->dev_private;
3726         uint32_t dsparb = I915_READ(DSPARB);
3727         int size;
3728
3729         size = dsparb & 0x7f;
3730         size >>= 1; /* Convert to cachelines */
3731
3732         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3733                       plane ? "B" : "A", size);
3734
3735         return size;
3736 }
3737
3738 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3739 {
3740         struct drm_crtc *crtc, *enabled = NULL;
3741
3742         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3743                 if (crtc->enabled && crtc->fb) {
3744                         if (enabled)
3745                                 return NULL;
3746                         enabled = crtc;
3747                 }
3748         }
3749
3750         return enabled;
3751 }
3752
3753 static void pineview_update_wm(struct drm_device *dev)
3754 {
3755         struct drm_i915_private *dev_priv = dev->dev_private;
3756         struct drm_crtc *crtc;
3757         const struct cxsr_latency *latency;
3758         u32 reg;
3759         unsigned long wm;
3760
3761         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3762                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3763         if (!latency) {
3764                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3765                 pineview_disable_cxsr(dev);
3766                 return;
3767         }
3768
3769         crtc = single_enabled_crtc(dev);
3770         if (crtc) {
3771                 int clock = crtc->mode.clock;
3772                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3773
3774                 /* Display SR */
3775                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3776                                         pineview_display_wm.fifo_size,
3777                                         pixel_size, latency->display_sr);
3778                 reg = I915_READ(DSPFW1);
3779                 reg &= ~DSPFW_SR_MASK;
3780                 reg |= wm << DSPFW_SR_SHIFT;
3781                 I915_WRITE(DSPFW1, reg);
3782                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3783
3784                 /* cursor SR */
3785                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3786                                         pineview_display_wm.fifo_size,
3787                                         pixel_size, latency->cursor_sr);
3788                 reg = I915_READ(DSPFW3);
3789                 reg &= ~DSPFW_CURSOR_SR_MASK;
3790                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3791                 I915_WRITE(DSPFW3, reg);
3792
3793                 /* Display HPLL off SR */
3794                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3795                                         pineview_display_hplloff_wm.fifo_size,
3796                                         pixel_size, latency->display_hpll_disable);
3797                 reg = I915_READ(DSPFW3);
3798                 reg &= ~DSPFW_HPLL_SR_MASK;
3799                 reg |= wm & DSPFW_HPLL_SR_MASK;
3800                 I915_WRITE(DSPFW3, reg);
3801
3802                 /* cursor HPLL off SR */
3803                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3804                                         pineview_display_hplloff_wm.fifo_size,
3805                                         pixel_size, latency->cursor_hpll_disable);
3806                 reg = I915_READ(DSPFW3);
3807                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3808                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3809                 I915_WRITE(DSPFW3, reg);
3810                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3811
3812                 /* activate cxsr */
3813                 I915_WRITE(DSPFW3,
3814                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3815                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3816         } else {
3817                 pineview_disable_cxsr(dev);
3818                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3819         }
3820 }
3821
3822 static bool g4x_compute_wm0(struct drm_device *dev,
3823                             int plane,
3824                             const struct intel_watermark_params *display,
3825                             int display_latency_ns,
3826                             const struct intel_watermark_params *cursor,
3827                             int cursor_latency_ns,
3828                             int *plane_wm,
3829                             int *cursor_wm)
3830 {
3831         struct drm_crtc *crtc;
3832         int htotal, hdisplay, clock, pixel_size;
3833         int line_time_us, line_count;
3834         int entries, tlb_miss;
3835
3836         crtc = intel_get_crtc_for_plane(dev, plane);
3837         if (crtc->fb == NULL || !crtc->enabled) {
3838                 *cursor_wm = cursor->guard_size;
3839                 *plane_wm = display->guard_size;
3840                 return false;
3841         }
3842
3843         htotal = crtc->mode.htotal;
3844         hdisplay = crtc->mode.hdisplay;
3845         clock = crtc->mode.clock;
3846         pixel_size = crtc->fb->bits_per_pixel / 8;
3847
3848         /* Use the small buffer method to calculate plane watermark */
3849         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3850         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3851         if (tlb_miss > 0)
3852                 entries += tlb_miss;
3853         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3854         *plane_wm = entries + display->guard_size;
3855         if (*plane_wm > (int)display->max_wm)
3856                 *plane_wm = display->max_wm;
3857
3858         /* Use the large buffer method to calculate cursor watermark */
3859         line_time_us = ((htotal * 1000) / clock);
3860         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3861         entries = line_count * 64 * pixel_size;
3862         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3863         if (tlb_miss > 0)
3864                 entries += tlb_miss;
3865         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3866         *cursor_wm = entries + cursor->guard_size;
3867         if (*cursor_wm > (int)cursor->max_wm)
3868                 *cursor_wm = (int)cursor->max_wm;
3869
3870         return true;
3871 }
3872
3873 /*
3874  * Check the wm result.
3875  *
3876  * If any calculated watermark values is larger than the maximum value that
3877  * can be programmed into the associated watermark register, that watermark
3878  * must be disabled.
3879  */
3880 static bool g4x_check_srwm(struct drm_device *dev,
3881                            int display_wm, int cursor_wm,
3882                            const struct intel_watermark_params *display,
3883                            const struct intel_watermark_params *cursor)
3884 {
3885         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3886                       display_wm, cursor_wm);
3887
3888         if (display_wm > display->max_wm) {
3889                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3890                               display_wm, display->max_wm);
3891                 return false;
3892         }
3893
3894         if (cursor_wm > cursor->max_wm) {
3895                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3896                               cursor_wm, cursor->max_wm);
3897                 return false;
3898         }
3899
3900         if (!(display_wm || cursor_wm)) {
3901                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3902                 return false;
3903         }
3904
3905         return true;
3906 }
3907
3908 static bool g4x_compute_srwm(struct drm_device *dev,
3909                              int plane,
3910                              int latency_ns,
3911                              const struct intel_watermark_params *display,
3912                              const struct intel_watermark_params *cursor,
3913                              int *display_wm, int *cursor_wm)
3914 {
3915         struct drm_crtc *crtc;
3916         int hdisplay, htotal, pixel_size, clock;
3917         unsigned long line_time_us;
3918         int line_count, line_size;
3919         int small, large;
3920         int entries;
3921
3922         if (!latency_ns) {
3923                 *display_wm = *cursor_wm = 0;
3924                 return false;
3925         }
3926
3927         crtc = intel_get_crtc_for_plane(dev, plane);
3928         hdisplay = crtc->mode.hdisplay;
3929         htotal = crtc->mode.htotal;
3930         clock = crtc->mode.clock;
3931         pixel_size = crtc->fb->bits_per_pixel / 8;
3932
3933         line_time_us = (htotal * 1000) / clock;
3934         line_count = (latency_ns / line_time_us + 1000) / 1000;
3935         line_size = hdisplay * pixel_size;
3936
3937         /* Use the minimum of the small and large buffer method for primary */
3938         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3939         large = line_count * line_size;
3940
3941         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3942         *display_wm = entries + display->guard_size;
3943
3944         /* calculate the self-refresh watermark for display cursor */
3945         entries = line_count * pixel_size * 64;
3946         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3947         *cursor_wm = entries + cursor->guard_size;
3948
3949         return g4x_check_srwm(dev,
3950                               *display_wm, *cursor_wm,
3951                               display, cursor);
3952 }
3953
3954 #define single_plane_enabled(mask) is_power_of_2(mask)
3955
3956 static void g4x_update_wm(struct drm_device *dev)
3957 {
3958         static const int sr_latency_ns = 12000;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3961         int plane_sr, cursor_sr;
3962         unsigned int enabled = 0;
3963
3964         if (g4x_compute_wm0(dev, 0,
3965                             &g4x_wm_info, latency_ns,
3966                             &g4x_cursor_wm_info, latency_ns,
3967                             &planea_wm, &cursora_wm))
3968                 enabled |= 1;
3969
3970         if (g4x_compute_wm0(dev, 1,
3971                             &g4x_wm_info, latency_ns,
3972                             &g4x_cursor_wm_info, latency_ns,
3973                             &planeb_wm, &cursorb_wm))
3974                 enabled |= 2;
3975
3976         plane_sr = cursor_sr = 0;
3977         if (single_plane_enabled(enabled) &&
3978             g4x_compute_srwm(dev, ffs(enabled) - 1,
3979                              sr_latency_ns,
3980                              &g4x_wm_info,
3981                              &g4x_cursor_wm_info,
3982                              &plane_sr, &cursor_sr))
3983                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3984         else
3985                 I915_WRITE(FW_BLC_SELF,
3986                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3987
3988         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3989                       planea_wm, cursora_wm,
3990                       planeb_wm, cursorb_wm,
3991                       plane_sr, cursor_sr);
3992
3993         I915_WRITE(DSPFW1,
3994                    (plane_sr << DSPFW_SR_SHIFT) |
3995                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3996                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3997                    planea_wm);
3998         I915_WRITE(DSPFW2,
3999                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4000                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4001         /* HPLL off in SR has some issues on G4x... disable it */
4002         I915_WRITE(DSPFW3,
4003                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4004                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4005 }
4006
4007 static void i965_update_wm(struct drm_device *dev)
4008 {
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         struct drm_crtc *crtc;
4011         int srwm = 1;
4012         int cursor_sr = 16;
4013
4014         /* Calc sr entries for one plane configs */
4015         crtc = single_enabled_crtc(dev);
4016         if (crtc) {
4017                 /* self-refresh has much higher latency */
4018                 static const int sr_latency_ns = 12000;
4019                 int clock = crtc->mode.clock;
4020                 int htotal = crtc->mode.htotal;
4021                 int hdisplay = crtc->mode.hdisplay;
4022                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4023                 unsigned long line_time_us;
4024                 int entries;
4025
4026                 line_time_us = ((htotal * 1000) / clock);
4027
4028                 /* Use ns/us then divide to preserve precision */
4029                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4030                         pixel_size * hdisplay;
4031                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4032                 srwm = I965_FIFO_SIZE - entries;
4033                 if (srwm < 0)
4034                         srwm = 1;
4035                 srwm &= 0x1ff;
4036                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4037                               entries, srwm);
4038
4039                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4040                         pixel_size * 64;
4041                 entries = DIV_ROUND_UP(entries,
4042                                           i965_cursor_wm_info.cacheline_size);
4043                 cursor_sr = i965_cursor_wm_info.fifo_size -
4044                         (entries + i965_cursor_wm_info.guard_size);
4045
4046                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4047                         cursor_sr = i965_cursor_wm_info.max_wm;
4048
4049                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4050                               "cursor %d\n", srwm, cursor_sr);
4051
4052                 if (IS_CRESTLINE(dev))
4053                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4054         } else {
4055                 /* Turn off self refresh if both pipes are enabled */
4056                 if (IS_CRESTLINE(dev))
4057                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4058                                    & ~FW_BLC_SELF_EN);
4059         }
4060
4061         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4062                       srwm);
4063
4064         /* 965 has limitations... */
4065         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4066                    (8 << 16) | (8 << 8) | (8 << 0));
4067         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4068         /* update cursor SR watermark */
4069         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4070 }
4071
4072 static void i9xx_update_wm(struct drm_device *dev)
4073 {
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         const struct intel_watermark_params *wm_info;
4076         uint32_t fwater_lo;
4077         uint32_t fwater_hi;
4078         int cwm, srwm = 1;
4079         int fifo_size;
4080         int planea_wm, planeb_wm;
4081         struct drm_crtc *crtc, *enabled = NULL;
4082
4083         if (IS_I945GM(dev))
4084                 wm_info = &i945_wm_info;
4085         else if (!IS_GEN2(dev))
4086                 wm_info = &i915_wm_info;
4087         else
4088                 wm_info = &i855_wm_info;
4089
4090         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4091         crtc = intel_get_crtc_for_plane(dev, 0);
4092         if (crtc->enabled && crtc->fb) {
4093                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4094                                                wm_info, fifo_size,
4095                                                crtc->fb->bits_per_pixel / 8,
4096                                                latency_ns);
4097                 enabled = crtc;
4098         } else
4099                 planea_wm = fifo_size - wm_info->guard_size;
4100
4101         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4102         crtc = intel_get_crtc_for_plane(dev, 1);
4103         if (crtc->enabled && crtc->fb) {
4104                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4105                                                wm_info, fifo_size,
4106                                                crtc->fb->bits_per_pixel / 8,
4107                                                latency_ns);
4108                 if (enabled == NULL)
4109                         enabled = crtc;
4110                 else
4111                         enabled = NULL;
4112         } else
4113                 planeb_wm = fifo_size - wm_info->guard_size;
4114
4115         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4116
4117         /*
4118          * Overlay gets an aggressive default since video jitter is bad.
4119          */
4120         cwm = 2;
4121
4122         /* Play safe and disable self-refresh before adjusting watermarks. */
4123         if (IS_I945G(dev) || IS_I945GM(dev))
4124                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4125         else if (IS_I915GM(dev))
4126                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4127
4128         /* Calc sr entries for one plane configs */
4129         if (HAS_FW_BLC(dev) && enabled) {
4130                 /* self-refresh has much higher latency */
4131                 static const int sr_latency_ns = 6000;
4132                 int clock = enabled->mode.clock;
4133                 int htotal = enabled->mode.htotal;
4134                 int hdisplay = enabled->mode.hdisplay;
4135                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4136                 unsigned long line_time_us;
4137                 int entries;
4138
4139                 line_time_us = (htotal * 1000) / clock;
4140
4141                 /* Use ns/us then divide to preserve precision */
4142                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4143                         pixel_size * hdisplay;
4144                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4145                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4146                 srwm = wm_info->fifo_size - entries;
4147                 if (srwm < 0)
4148                         srwm = 1;
4149
4150                 if (IS_I945G(dev) || IS_I945GM(dev))
4151                         I915_WRITE(FW_BLC_SELF,
4152                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4153                 else if (IS_I915GM(dev))
4154                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4155         }
4156
4157         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4158                       planea_wm, planeb_wm, cwm, srwm);
4159
4160         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4161         fwater_hi = (cwm & 0x1f);
4162
4163         /* Set request length to 8 cachelines per fetch */
4164         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4165         fwater_hi = fwater_hi | (1 << 8);
4166
4167         I915_WRITE(FW_BLC, fwater_lo);
4168         I915_WRITE(FW_BLC2, fwater_hi);
4169
4170         if (HAS_FW_BLC(dev)) {
4171                 if (enabled) {
4172                         if (IS_I945G(dev) || IS_I945GM(dev))
4173                                 I915_WRITE(FW_BLC_SELF,
4174                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4175                         else if (IS_I915GM(dev))
4176                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4177                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4178                 } else
4179                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4180         }
4181 }
4182
4183 static void i830_update_wm(struct drm_device *dev)
4184 {
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         struct drm_crtc *crtc;
4187         uint32_t fwater_lo;
4188         int planea_wm;
4189
4190         crtc = single_enabled_crtc(dev);
4191         if (crtc == NULL)
4192                 return;
4193
4194         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4195                                        dev_priv->display.get_fifo_size(dev, 0),
4196                                        crtc->fb->bits_per_pixel / 8,
4197                                        latency_ns);
4198         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4199         fwater_lo |= (3<<8) | planea_wm;
4200
4201         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4202
4203         I915_WRITE(FW_BLC, fwater_lo);
4204 }
4205
4206 #define ILK_LP0_PLANE_LATENCY           700
4207 #define ILK_LP0_CURSOR_LATENCY          1300
4208
4209 /*
4210  * Check the wm result.
4211  *
4212  * If any calculated watermark values is larger than the maximum value that
4213  * can be programmed into the associated watermark register, that watermark
4214  * must be disabled.
4215  */
4216 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4217                                 int fbc_wm, int display_wm, int cursor_wm,
4218                                 const struct intel_watermark_params *display,
4219                                 const struct intel_watermark_params *cursor)
4220 {
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222
4223         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4224                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4225
4226         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4227                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4228                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4229
4230                 /* fbc has it's own way to disable FBC WM */
4231                 I915_WRITE(DISP_ARB_CTL,
4232                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4233                 return false;
4234         }
4235
4236         if (display_wm > display->max_wm) {
4237                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4238                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4239                 return false;
4240         }
4241
4242         if (cursor_wm > cursor->max_wm) {
4243                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4244                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4245                 return false;
4246         }
4247
4248         if (!(fbc_wm || display_wm || cursor_wm)) {
4249                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4250                 return false;
4251         }
4252
4253         return true;
4254 }
4255
4256 /*
4257  * Compute watermark values of WM[1-3],
4258  */
4259 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4260                                   int latency_ns,
4261                                   const struct intel_watermark_params *display,
4262                                   const struct intel_watermark_params *cursor,
4263                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4264 {
4265         struct drm_crtc *crtc;
4266         unsigned long line_time_us;
4267         int hdisplay, htotal, pixel_size, clock;
4268         int line_count, line_size;
4269         int small, large;
4270         int entries;
4271
4272         if (!latency_ns) {
4273                 *fbc_wm = *display_wm = *cursor_wm = 0;
4274                 return false;
4275         }
4276
4277         crtc = intel_get_crtc_for_plane(dev, plane);
4278         hdisplay = crtc->mode.hdisplay;
4279         htotal = crtc->mode.htotal;
4280         clock = crtc->mode.clock;
4281         pixel_size = crtc->fb->bits_per_pixel / 8;
4282
4283         line_time_us = (htotal * 1000) / clock;
4284         line_count = (latency_ns / line_time_us + 1000) / 1000;
4285         line_size = hdisplay * pixel_size;
4286
4287         /* Use the minimum of the small and large buffer method for primary */
4288         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4289         large = line_count * line_size;
4290
4291         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4292         *display_wm = entries + display->guard_size;
4293
4294         /*
4295          * Spec says:
4296          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4297          */
4298         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4299
4300         /* calculate the self-refresh watermark for display cursor */
4301         entries = line_count * pixel_size * 64;
4302         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4303         *cursor_wm = entries + cursor->guard_size;
4304
4305         return ironlake_check_srwm(dev, level,
4306                                    *fbc_wm, *display_wm, *cursor_wm,
4307                                    display, cursor);
4308 }
4309
4310 static void ironlake_update_wm(struct drm_device *dev)
4311 {
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         int fbc_wm, plane_wm, cursor_wm;
4314         unsigned int enabled;
4315
4316         enabled = 0;
4317         if (g4x_compute_wm0(dev, 0,
4318                             &ironlake_display_wm_info,
4319                             ILK_LP0_PLANE_LATENCY,
4320                             &ironlake_cursor_wm_info,
4321                             ILK_LP0_CURSOR_LATENCY,
4322                             &plane_wm, &cursor_wm)) {
4323                 I915_WRITE(WM0_PIPEA_ILK,
4324                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4325                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4326                               " plane %d, " "cursor: %d\n",
4327                               plane_wm, cursor_wm);
4328                 enabled |= 1;
4329         }
4330
4331         if (g4x_compute_wm0(dev, 1,
4332                             &ironlake_display_wm_info,
4333                             ILK_LP0_PLANE_LATENCY,
4334                             &ironlake_cursor_wm_info,
4335                             ILK_LP0_CURSOR_LATENCY,
4336                             &plane_wm, &cursor_wm)) {
4337                 I915_WRITE(WM0_PIPEB_ILK,
4338                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4339                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4340                               " plane %d, cursor: %d\n",
4341                               plane_wm, cursor_wm);
4342                 enabled |= 2;
4343         }
4344
4345         /*
4346          * Calculate and update the self-refresh watermark only when one
4347          * display plane is used.
4348          */
4349         I915_WRITE(WM3_LP_ILK, 0);
4350         I915_WRITE(WM2_LP_ILK, 0);
4351         I915_WRITE(WM1_LP_ILK, 0);
4352
4353         if (!single_plane_enabled(enabled))
4354                 return;
4355         enabled = ffs(enabled) - 1;
4356
4357         /* WM1 */
4358         if (!ironlake_compute_srwm(dev, 1, enabled,
4359                                    ILK_READ_WM1_LATENCY() * 500,
4360                                    &ironlake_display_srwm_info,
4361                                    &ironlake_cursor_srwm_info,
4362                                    &fbc_wm, &plane_wm, &cursor_wm))
4363                 return;
4364
4365         I915_WRITE(WM1_LP_ILK,
4366                    WM1_LP_SR_EN |
4367                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4368                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4369                    (plane_wm << WM1_LP_SR_SHIFT) |
4370                    cursor_wm);
4371
4372         /* WM2 */
4373         if (!ironlake_compute_srwm(dev, 2, enabled,
4374                                    ILK_READ_WM2_LATENCY() * 500,
4375                                    &ironlake_display_srwm_info,
4376                                    &ironlake_cursor_srwm_info,
4377                                    &fbc_wm, &plane_wm, &cursor_wm))
4378                 return;
4379
4380         I915_WRITE(WM2_LP_ILK,
4381                    WM2_LP_EN |
4382                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4383                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4384                    (plane_wm << WM1_LP_SR_SHIFT) |
4385                    cursor_wm);
4386
4387         /*
4388          * WM3 is unsupported on ILK, probably because we don't have latency
4389          * data for that power state
4390          */
4391 }
4392
4393 static void sandybridge_update_wm(struct drm_device *dev)
4394 {
4395         struct drm_i915_private *dev_priv = dev->dev_private;
4396         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4397         int fbc_wm, plane_wm, cursor_wm;
4398         unsigned int enabled;
4399
4400         enabled = 0;
4401         if (g4x_compute_wm0(dev, 0,
4402                             &sandybridge_display_wm_info, latency,
4403                             &sandybridge_cursor_wm_info, latency,
4404                             &plane_wm, &cursor_wm)) {
4405                 I915_WRITE(WM0_PIPEA_ILK,
4406                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4407                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4408                               " plane %d, " "cursor: %d\n",
4409                               plane_wm, cursor_wm);
4410                 enabled |= 1;
4411         }
4412
4413         if (g4x_compute_wm0(dev, 1,
4414                             &sandybridge_display_wm_info, latency,
4415                             &sandybridge_cursor_wm_info, latency,
4416                             &plane_wm, &cursor_wm)) {
4417                 I915_WRITE(WM0_PIPEB_ILK,
4418                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4419                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4420                               " plane %d, cursor: %d\n",
4421                               plane_wm, cursor_wm);
4422                 enabled |= 2;
4423         }
4424
4425         /*
4426          * Calculate and update the self-refresh watermark only when one
4427          * display plane is used.
4428          *
4429          * SNB support 3 levels of watermark.
4430          *
4431          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4432          * and disabled in the descending order
4433          *
4434          */
4435         I915_WRITE(WM3_LP_ILK, 0);
4436         I915_WRITE(WM2_LP_ILK, 0);
4437         I915_WRITE(WM1_LP_ILK, 0);
4438
4439         if (!single_plane_enabled(enabled))
4440                 return;
4441         enabled = ffs(enabled) - 1;
4442
4443         /* WM1 */
4444         if (!ironlake_compute_srwm(dev, 1, enabled,
4445                                    SNB_READ_WM1_LATENCY() * 500,
4446                                    &sandybridge_display_srwm_info,
4447                                    &sandybridge_cursor_srwm_info,
4448                                    &fbc_wm, &plane_wm, &cursor_wm))
4449                 return;
4450
4451         I915_WRITE(WM1_LP_ILK,
4452                    WM1_LP_SR_EN |
4453                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4454                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4455                    (plane_wm << WM1_LP_SR_SHIFT) |
4456                    cursor_wm);
4457
4458         /* WM2 */
4459         if (!ironlake_compute_srwm(dev, 2, enabled,
4460                                    SNB_READ_WM2_LATENCY() * 500,
4461                                    &sandybridge_display_srwm_info,
4462                                    &sandybridge_cursor_srwm_info,
4463                                    &fbc_wm, &plane_wm, &cursor_wm))
4464                 return;
4465
4466         I915_WRITE(WM2_LP_ILK,
4467                    WM2_LP_EN |
4468                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4469                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4470                    (plane_wm << WM1_LP_SR_SHIFT) |
4471                    cursor_wm);
4472
4473         /* WM3 */
4474         if (!ironlake_compute_srwm(dev, 3, enabled,
4475                                    SNB_READ_WM3_LATENCY() * 500,
4476                                    &sandybridge_display_srwm_info,
4477                                    &sandybridge_cursor_srwm_info,
4478                                    &fbc_wm, &plane_wm, &cursor_wm))
4479                 return;
4480
4481         I915_WRITE(WM3_LP_ILK,
4482                    WM3_LP_EN |
4483                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4484                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4485                    (plane_wm << WM1_LP_SR_SHIFT) |
4486                    cursor_wm);
4487 }
4488
4489 /**
4490  * intel_update_watermarks - update FIFO watermark values based on current modes
4491  *
4492  * Calculate watermark values for the various WM regs based on current mode
4493  * and plane configuration.
4494  *
4495  * There are several cases to deal with here:
4496  *   - normal (i.e. non-self-refresh)
4497  *   - self-refresh (SR) mode
4498  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4499  *   - lines are small relative to FIFO size (buffer can hold more than 2
4500  *     lines), so need to account for TLB latency
4501  *
4502  *   The normal calculation is:
4503  *     watermark = dotclock * bytes per pixel * latency
4504  *   where latency is platform & configuration dependent (we assume pessimal
4505  *   values here).
4506  *
4507  *   The SR calculation is:
4508  *     watermark = (trunc(latency/line time)+1) * surface width *
4509  *       bytes per pixel
4510  *   where
4511  *     line time = htotal / dotclock
4512  *     surface width = hdisplay for normal plane and 64 for cursor
4513  *   and latency is assumed to be high, as above.
4514  *
4515  * The final value programmed to the register should always be rounded up,
4516  * and include an extra 2 entries to account for clock crossings.
4517  *
4518  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4519  * to set the non-SR watermarks to 8.
4520  */
4521 static void intel_update_watermarks(struct drm_device *dev)
4522 {
4523         struct drm_i915_private *dev_priv = dev->dev_private;
4524
4525         if (dev_priv->display.update_wm)
4526                 dev_priv->display.update_wm(dev);
4527 }
4528
4529 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4530 {
4531         return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4532                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4533 }
4534
4535 /**
4536  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4537  * @crtc: CRTC structure
4538  *
4539  * A pipe may be connected to one or more outputs.  Based on the depth of the
4540  * attached framebuffer, choose a good color depth to use on the pipe.
4541  *
4542  * If possible, match the pipe depth to the fb depth.  In some cases, this
4543  * isn't ideal, because the connected output supports a lesser or restricted
4544  * set of depths.  Resolve that here:
4545  *    LVDS typically supports only 6bpc, so clamp down in that case
4546  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4547  *    Displays may support a restricted set as well, check EDID and clamp as
4548  *      appropriate.
4549  *
4550  * RETURNS:
4551  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4552  * true if they don't match).
4553  */
4554 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4555                                          unsigned int *pipe_bpp)
4556 {
4557         struct drm_device *dev = crtc->dev;
4558         struct drm_i915_private *dev_priv = dev->dev_private;
4559         struct drm_encoder *encoder;
4560         struct drm_connector *connector;
4561         unsigned int display_bpc = UINT_MAX, bpc;
4562
4563         /* Walk the encoders & connectors on this crtc, get min bpc */
4564         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4565                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4566
4567                 if (encoder->crtc != crtc)
4568                         continue;
4569
4570                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4571                         unsigned int lvds_bpc;
4572
4573                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4574                             LVDS_A3_POWER_UP)
4575                                 lvds_bpc = 8;
4576                         else
4577                                 lvds_bpc = 6;
4578
4579                         if (lvds_bpc < display_bpc) {
4580                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4581                                 display_bpc = lvds_bpc;
4582                         }
4583                         continue;
4584                 }
4585
4586                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4587                         /* Use VBT settings if we have an eDP panel */
4588                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4589
4590                         if (edp_bpc < display_bpc) {
4591                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4592                                 display_bpc = edp_bpc;
4593                         }
4594                         continue;
4595                 }
4596
4597                 /* Not one of the known troublemakers, check the EDID */
4598                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4599                                     head) {
4600                         if (connector->encoder != encoder)
4601                                 continue;
4602
4603                         if (connector->display_info.bpc < display_bpc) {
4604                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4605                                 display_bpc = connector->display_info.bpc;
4606                         }
4607                 }
4608
4609                 /*
4610                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4611                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4612                  */
4613                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4614                         if (display_bpc > 8 && display_bpc < 12) {
4615                                 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4616                                 display_bpc = 12;
4617                         } else {
4618                                 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4619                                 display_bpc = 8;
4620                         }
4621                 }
4622         }
4623
4624         /*
4625          * We could just drive the pipe at the highest bpc all the time and
4626          * enable dithering as needed, but that costs bandwidth.  So choose
4627          * the minimum value that expresses the full color range of the fb but
4628          * also stays within the max display bpc discovered above.
4629          */
4630
4631         switch (crtc->fb->depth) {
4632         case 8:
4633                 bpc = 8; /* since we go through a colormap */
4634                 break;
4635         case 15:
4636         case 16:
4637                 bpc = 6; /* min is 18bpp */
4638                 break;
4639         case 24:
4640                 bpc = min((unsigned int)8, display_bpc);
4641                 break;
4642         case 30:
4643                 bpc = min((unsigned int)10, display_bpc);
4644                 break;
4645         case 48:
4646                 bpc = min((unsigned int)12, display_bpc);
4647                 break;
4648         default:
4649                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4650                 bpc = min((unsigned int)8, display_bpc);
4651                 break;
4652         }
4653
4654         DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4655                          bpc, display_bpc);
4656
4657         *pipe_bpp = bpc * 3;
4658
4659         return display_bpc != bpc;
4660 }
4661
4662 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4663                               struct drm_display_mode *mode,
4664                               struct drm_display_mode *adjusted_mode,
4665                               int x, int y,
4666                               struct drm_framebuffer *old_fb)
4667 {
4668         struct drm_device *dev = crtc->dev;
4669         struct drm_i915_private *dev_priv = dev->dev_private;
4670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4671         int pipe = intel_crtc->pipe;
4672         int plane = intel_crtc->plane;
4673         int refclk, num_connectors = 0;
4674         intel_clock_t clock, reduced_clock;
4675         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4676         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4677         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4678         struct drm_mode_config *mode_config = &dev->mode_config;
4679         struct intel_encoder *encoder;
4680         const intel_limit_t *limit;
4681         int ret;
4682         u32 temp;
4683         u32 lvds_sync = 0;
4684
4685         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4686                 if (encoder->base.crtc != crtc)
4687                         continue;
4688
4689                 switch (encoder->type) {
4690                 case INTEL_OUTPUT_LVDS:
4691                         is_lvds = true;
4692                         break;
4693                 case INTEL_OUTPUT_SDVO:
4694                 case INTEL_OUTPUT_HDMI:
4695                         is_sdvo = true;
4696                         if (encoder->needs_tv_clock)
4697                                 is_tv = true;
4698                         break;
4699                 case INTEL_OUTPUT_DVO:
4700                         is_dvo = true;
4701                         break;
4702                 case INTEL_OUTPUT_TVOUT:
4703                         is_tv = true;
4704                         break;
4705                 case INTEL_OUTPUT_ANALOG:
4706                         is_crt = true;
4707                         break;
4708                 case INTEL_OUTPUT_DISPLAYPORT:
4709                         is_dp = true;
4710                         break;
4711                 }
4712
4713                 num_connectors++;
4714         }
4715
4716         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4717                 refclk = dev_priv->lvds_ssc_freq * 1000;
4718                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4719                               refclk / 1000);
4720         } else if (!IS_GEN2(dev)) {
4721                 refclk = 96000;
4722         } else {
4723                 refclk = 48000;
4724         }
4725
4726         /*
4727          * Returns a set of divisors for the desired target clock with the given
4728          * refclk, or FALSE.  The returned values represent the clock equation:
4729          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4730          */
4731         limit = intel_limit(crtc, refclk);
4732         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4733         if (!ok) {
4734                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4735                 return -EINVAL;
4736         }
4737
4738         /* Ensure that the cursor is valid for the new mode before changing... */
4739         intel_crtc_update_cursor(crtc, true);
4740
4741         if (is_lvds && dev_priv->lvds_downclock_avail) {
4742                 has_reduced_clock = limit->find_pll(limit, crtc,
4743                                                     dev_priv->lvds_downclock,
4744                                                     refclk,
4745                                                     &reduced_clock);
4746                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4747                         /*
4748                          * If the different P is found, it means that we can't
4749                          * switch the display clock by using the FP0/FP1.
4750                          * In such case we will disable the LVDS downclock
4751                          * feature.
4752                          */
4753                         DRM_DEBUG_KMS("Different P is found for "
4754                                       "LVDS clock/downclock\n");
4755                         has_reduced_clock = 0;
4756                 }
4757         }
4758         /* SDVO TV has fixed PLL values depend on its clock range,
4759            this mirrors vbios setting. */
4760         if (is_sdvo && is_tv) {
4761                 if (adjusted_mode->clock >= 100000
4762                     && adjusted_mode->clock < 140500) {
4763                         clock.p1 = 2;
4764                         clock.p2 = 10;
4765                         clock.n = 3;
4766                         clock.m1 = 16;
4767                         clock.m2 = 8;
4768                 } else if (adjusted_mode->clock >= 140500
4769                            && adjusted_mode->clock <= 200000) {
4770                         clock.p1 = 1;
4771                         clock.p2 = 10;
4772                         clock.n = 6;
4773                         clock.m1 = 12;
4774                         clock.m2 = 8;
4775                 }
4776         }
4777
4778         if (IS_PINEVIEW(dev)) {
4779                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4780                 if (has_reduced_clock)
4781                         fp2 = (1 << reduced_clock.n) << 16 |
4782                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4783         } else {
4784                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4785                 if (has_reduced_clock)
4786                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4787                                 reduced_clock.m2;
4788         }
4789
4790         dpll = DPLL_VGA_MODE_DIS;
4791
4792         if (!IS_GEN2(dev)) {
4793                 if (is_lvds)
4794                         dpll |= DPLLB_MODE_LVDS;
4795                 else
4796                         dpll |= DPLLB_MODE_DAC_SERIAL;
4797                 if (is_sdvo) {
4798                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4799                         if (pixel_multiplier > 1) {
4800                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4801                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4802                         }
4803                         dpll |= DPLL_DVO_HIGH_SPEED;
4804                 }
4805                 if (is_dp)
4806                         dpll |= DPLL_DVO_HIGH_SPEED;
4807
4808                 /* compute bitmask from p1 value */
4809                 if (IS_PINEVIEW(dev))
4810                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4811                 else {
4812                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4813                         if (IS_G4X(dev) && has_reduced_clock)
4814                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4815                 }
4816                 switch (clock.p2) {
4817                 case 5:
4818                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4819                         break;
4820                 case 7:
4821                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4822                         break;
4823                 case 10:
4824                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4825                         break;
4826                 case 14:
4827                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4828                         break;
4829                 }
4830                 if (INTEL_INFO(dev)->gen >= 4)
4831                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4832         } else {
4833                 if (is_lvds) {
4834                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4835                 } else {
4836                         if (clock.p1 == 2)
4837                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4838                         else
4839                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4840                         if (clock.p2 == 4)
4841                                 dpll |= PLL_P2_DIVIDE_BY_4;
4842                 }
4843         }
4844
4845         if (is_sdvo && is_tv)
4846                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4847         else if (is_tv)
4848                 /* XXX: just matching BIOS for now */
4849                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4850                 dpll |= 3;
4851         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4852                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4853         else
4854                 dpll |= PLL_REF_INPUT_DREFCLK;
4855
4856         /* setup pipeconf */
4857         pipeconf = I915_READ(PIPECONF(pipe));
4858
4859         /* Set up the display plane register */
4860         dspcntr = DISPPLANE_GAMMA_ENABLE;
4861
4862         /* Ironlake's plane is forced to pipe, bit 24 is to
4863            enable color space conversion */
4864         if (pipe == 0)
4865                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4866         else
4867                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4868
4869         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4870                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4871                  * core speed.
4872                  *
4873                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4874                  * pipe == 0 check?
4875                  */
4876                 if (mode->clock >
4877                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4878                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4879                 else
4880                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4881         }
4882
4883         dpll |= DPLL_VCO_ENABLE;
4884
4885         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4886         drm_mode_debug_printmodeline(mode);
4887
4888         I915_WRITE(FP0(pipe), fp);
4889         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4890
4891         POSTING_READ(DPLL(pipe));
4892         udelay(150);
4893
4894         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4895          * This is an exception to the general rule that mode_set doesn't turn
4896          * things on.
4897          */
4898         if (is_lvds) {
4899                 temp = I915_READ(LVDS);
4900                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4901                 if (pipe == 1) {
4902                         temp |= LVDS_PIPEB_SELECT;
4903                 } else {
4904                         temp &= ~LVDS_PIPEB_SELECT;
4905                 }
4906                 /* set the corresponsding LVDS_BORDER bit */
4907                 temp |= dev_priv->lvds_border_bits;
4908                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4909                  * set the DPLLs for dual-channel mode or not.
4910                  */
4911                 if (clock.p2 == 7)
4912                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4913                 else
4914                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4915
4916                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4917                  * appropriately here, but we need to look more thoroughly into how
4918                  * panels behave in the two modes.
4919                  */
4920                 /* set the dithering flag on LVDS as needed */
4921                 if (INTEL_INFO(dev)->gen >= 4) {
4922                         if (dev_priv->lvds_dither)
4923                                 temp |= LVDS_ENABLE_DITHER;
4924                         else
4925                                 temp &= ~LVDS_ENABLE_DITHER;
4926                 }
4927                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4928                         lvds_sync |= LVDS_HSYNC_POLARITY;
4929                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4930                         lvds_sync |= LVDS_VSYNC_POLARITY;
4931                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4932                     != lvds_sync) {
4933                         char flags[2] = "-+";
4934                         DRM_INFO("Changing LVDS panel from "
4935                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4936                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4937                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4938                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4939                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4940                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4941                         temp |= lvds_sync;
4942                 }
4943                 I915_WRITE(LVDS, temp);
4944         }
4945
4946         if (is_dp) {
4947                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4948         }
4949
4950         I915_WRITE(DPLL(pipe), dpll);
4951
4952         /* Wait for the clocks to stabilize. */
4953         POSTING_READ(DPLL(pipe));
4954         udelay(150);
4955
4956         if (INTEL_INFO(dev)->gen >= 4) {
4957                 temp = 0;
4958                 if (is_sdvo) {
4959                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4960                         if (temp > 1)
4961                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4962                         else
4963                                 temp = 0;
4964                 }
4965                 I915_WRITE(DPLL_MD(pipe), temp);
4966         } else {
4967                 /* The pixel multiplier can only be updated once the
4968                  * DPLL is enabled and the clocks are stable.
4969                  *
4970                  * So write it again.
4971                  */
4972                 I915_WRITE(DPLL(pipe), dpll);
4973         }
4974
4975         intel_crtc->lowfreq_avail = false;
4976         if (is_lvds && has_reduced_clock && i915_powersave) {
4977                 I915_WRITE(FP1(pipe), fp2);
4978                 intel_crtc->lowfreq_avail = true;
4979                 if (HAS_PIPE_CXSR(dev)) {
4980                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4981                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4982                 }
4983         } else {
4984                 I915_WRITE(FP1(pipe), fp);
4985                 if (HAS_PIPE_CXSR(dev)) {
4986                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4987                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4988                 }
4989         }
4990
4991         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4992                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4993                 /* the chip adds 2 halflines automatically */
4994                 adjusted_mode->crtc_vdisplay -= 1;
4995                 adjusted_mode->crtc_vtotal -= 1;
4996                 adjusted_mode->crtc_vblank_start -= 1;
4997                 adjusted_mode->crtc_vblank_end -= 1;
4998                 adjusted_mode->crtc_vsync_end -= 1;
4999                 adjusted_mode->crtc_vsync_start -= 1;
5000         } else
5001                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5002
5003         I915_WRITE(HTOTAL(pipe),
5004                    (adjusted_mode->crtc_hdisplay - 1) |
5005                    ((adjusted_mode->crtc_htotal - 1) << 16));
5006         I915_WRITE(HBLANK(pipe),
5007                    (adjusted_mode->crtc_hblank_start - 1) |
5008                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5009         I915_WRITE(HSYNC(pipe),
5010                    (adjusted_mode->crtc_hsync_start - 1) |
5011                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5012
5013         I915_WRITE(VTOTAL(pipe),
5014                    (adjusted_mode->crtc_vdisplay - 1) |
5015                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5016         I915_WRITE(VBLANK(pipe),
5017                    (adjusted_mode->crtc_vblank_start - 1) |
5018                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5019         I915_WRITE(VSYNC(pipe),
5020                    (adjusted_mode->crtc_vsync_start - 1) |
5021                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5022
5023         /* pipesrc and dspsize control the size that is scaled from,
5024          * which should always be the user's requested size.
5025          */
5026         I915_WRITE(DSPSIZE(plane),
5027                    ((mode->vdisplay - 1) << 16) |
5028                    (mode->hdisplay - 1));
5029         I915_WRITE(DSPPOS(plane), 0);
5030         I915_WRITE(PIPESRC(pipe),
5031                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5032
5033         I915_WRITE(PIPECONF(pipe), pipeconf);
5034         POSTING_READ(PIPECONF(pipe));
5035         intel_enable_pipe(dev_priv, pipe, false);
5036
5037         intel_wait_for_vblank(dev, pipe);
5038
5039         I915_WRITE(DSPCNTR(plane), dspcntr);
5040         POSTING_READ(DSPCNTR(plane));
5041         intel_enable_plane(dev_priv, plane, pipe);
5042
5043         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5044
5045         intel_update_watermarks(dev);
5046
5047         return ret;
5048 }
5049
5050 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5051                                   struct drm_display_mode *mode,
5052                                   struct drm_display_mode *adjusted_mode,
5053                                   int x, int y,
5054                                   struct drm_framebuffer *old_fb)
5055 {
5056         struct drm_device *dev = crtc->dev;
5057         struct drm_i915_private *dev_priv = dev->dev_private;
5058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059         int pipe = intel_crtc->pipe;
5060         int plane = intel_crtc->plane;
5061         int refclk, num_connectors = 0;
5062         intel_clock_t clock, reduced_clock;
5063         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5064         bool ok, has_reduced_clock = false, is_sdvo = false;
5065         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5066         struct intel_encoder *has_edp_encoder = NULL;
5067         struct drm_mode_config *mode_config = &dev->mode_config;
5068         struct intel_encoder *encoder;
5069         const intel_limit_t *limit;
5070         int ret;
5071         struct fdi_m_n m_n = {0};
5072         u32 temp;
5073         u32 lvds_sync = 0;
5074         int target_clock, pixel_multiplier, lane, link_bw, factor;
5075         unsigned int pipe_bpp;
5076         bool dither;
5077
5078         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5079                 if (encoder->base.crtc != crtc)
5080                         continue;
5081
5082                 switch (encoder->type) {
5083                 case INTEL_OUTPUT_LVDS:
5084                         is_lvds = true;
5085                         break;
5086                 case INTEL_OUTPUT_SDVO:
5087                 case INTEL_OUTPUT_HDMI:
5088                         is_sdvo = true;
5089                         if (encoder->needs_tv_clock)
5090                                 is_tv = true;
5091                         break;
5092                 case INTEL_OUTPUT_TVOUT:
5093                         is_tv = true;
5094                         break;
5095                 case INTEL_OUTPUT_ANALOG:
5096                         is_crt = true;
5097                         break;
5098                 case INTEL_OUTPUT_DISPLAYPORT:
5099                         is_dp = true;
5100                         break;
5101                 case INTEL_OUTPUT_EDP:
5102                         has_edp_encoder = encoder;
5103                         break;
5104                 }
5105
5106                 num_connectors++;
5107         }
5108
5109         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5110                 refclk = dev_priv->lvds_ssc_freq * 1000;
5111                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5112                               refclk / 1000);
5113         } else {
5114                 refclk = 96000;
5115                 if (!has_edp_encoder ||
5116                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
5117                         refclk = 120000; /* 120Mhz refclk */
5118         }
5119
5120         /*
5121          * Returns a set of divisors for the desired target clock with the given
5122          * refclk, or FALSE.  The returned values represent the clock equation:
5123          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5124          */
5125         limit = intel_limit(crtc, refclk);
5126         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5127         if (!ok) {
5128                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5129                 return -EINVAL;
5130         }
5131
5132         /* Ensure that the cursor is valid for the new mode before changing... */
5133         intel_crtc_update_cursor(crtc, true);
5134
5135         if (is_lvds && dev_priv->lvds_downclock_avail) {
5136                 has_reduced_clock = limit->find_pll(limit, crtc,
5137                                                     dev_priv->lvds_downclock,
5138                                                     refclk,
5139                                                     &reduced_clock);
5140                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5141                         /*
5142                          * If the different P is found, it means that we can't
5143                          * switch the display clock by using the FP0/FP1.
5144                          * In such case we will disable the LVDS downclock
5145                          * feature.
5146                          */
5147                         DRM_DEBUG_KMS("Different P is found for "
5148                                       "LVDS clock/downclock\n");
5149                         has_reduced_clock = 0;
5150                 }
5151         }
5152         /* SDVO TV has fixed PLL values depend on its clock range,
5153            this mirrors vbios setting. */
5154         if (is_sdvo && is_tv) {
5155                 if (adjusted_mode->clock >= 100000
5156                     && adjusted_mode->clock < 140500) {
5157                         clock.p1 = 2;
5158                         clock.p2 = 10;
5159                         clock.n = 3;
5160                         clock.m1 = 16;
5161                         clock.m2 = 8;
5162                 } else if (adjusted_mode->clock >= 140500
5163                            && adjusted_mode->clock <= 200000) {
5164                         clock.p1 = 1;
5165                         clock.p2 = 10;
5166                         clock.n = 6;
5167                         clock.m1 = 12;
5168                         clock.m2 = 8;
5169                 }
5170         }
5171
5172         /* FDI link */
5173         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5174         lane = 0;
5175         /* CPU eDP doesn't require FDI link, so just set DP M/N
5176            according to current link config */
5177         if (has_edp_encoder &&
5178             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5179                 target_clock = mode->clock;
5180                 intel_edp_link_config(has_edp_encoder,
5181                                       &lane, &link_bw);
5182         } else {
5183                 /* [e]DP over FDI requires target mode clock
5184                    instead of link clock */
5185                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5186                         target_clock = mode->clock;
5187                 else
5188                         target_clock = adjusted_mode->clock;
5189
5190                 /* FDI is a binary signal running at ~2.7GHz, encoding
5191                  * each output octet as 10 bits. The actual frequency
5192                  * is stored as a divider into a 100MHz clock, and the
5193                  * mode pixel clock is stored in units of 1KHz.
5194                  * Hence the bw of each lane in terms of the mode signal
5195                  * is:
5196                  */
5197                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5198         }
5199
5200         /* determine panel color depth */
5201         temp = I915_READ(PIPECONF(pipe));
5202         temp &= ~PIPE_BPC_MASK;
5203         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5204         switch (pipe_bpp) {
5205         case 18:
5206                 temp |= PIPE_6BPC;
5207                 break;
5208         case 24:
5209                 temp |= PIPE_8BPC;
5210                 break;
5211         case 30:
5212                 temp |= PIPE_10BPC;
5213                 break;
5214         case 36:
5215                 temp |= PIPE_12BPC;
5216                 break;
5217         default:
5218                 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5219                 temp |= PIPE_8BPC;
5220                 pipe_bpp = 24;
5221                 break;
5222         }
5223
5224         intel_crtc->bpp = pipe_bpp;
5225         I915_WRITE(PIPECONF(pipe), temp);
5226
5227         if (!lane) {
5228                 /*
5229                  * Account for spread spectrum to avoid
5230                  * oversubscribing the link. Max center spread
5231                  * is 2.5%; use 5% for safety's sake.
5232                  */
5233                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5234                 lane = bps / (link_bw * 8) + 1;
5235         }
5236
5237         intel_crtc->fdi_lanes = lane;
5238
5239         if (pixel_multiplier > 1)
5240                 link_bw *= pixel_multiplier;
5241         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5242                              &m_n);
5243
5244         /* Ironlake: try to setup display ref clock before DPLL
5245          * enabling. This is only under driver's control after
5246          * PCH B stepping, previous chipset stepping should be
5247          * ignoring this setting.
5248          */
5249         temp = I915_READ(PCH_DREF_CONTROL);
5250         /* Always enable nonspread source */
5251         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5252         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5253         temp &= ~DREF_SSC_SOURCE_MASK;
5254         temp |= DREF_SSC_SOURCE_ENABLE;
5255         I915_WRITE(PCH_DREF_CONTROL, temp);
5256
5257         POSTING_READ(PCH_DREF_CONTROL);
5258         udelay(200);
5259
5260         if (has_edp_encoder) {
5261                 if (intel_panel_use_ssc(dev_priv)) {
5262                         temp |= DREF_SSC1_ENABLE;
5263                         I915_WRITE(PCH_DREF_CONTROL, temp);
5264
5265                         POSTING_READ(PCH_DREF_CONTROL);
5266                         udelay(200);
5267                 }
5268                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5269
5270                 /* Enable CPU source on CPU attached eDP */
5271                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5272                         if (intel_panel_use_ssc(dev_priv))
5273                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5274                         else
5275                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5276                 } else {
5277                         /* Enable SSC on PCH eDP if needed */
5278                         if (intel_panel_use_ssc(dev_priv)) {
5279                                 DRM_ERROR("enabling SSC on PCH\n");
5280                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5281                         }
5282                 }
5283                 I915_WRITE(PCH_DREF_CONTROL, temp);
5284                 POSTING_READ(PCH_DREF_CONTROL);
5285                 udelay(200);
5286         }
5287
5288         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5289         if (has_reduced_clock)
5290                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5291                         reduced_clock.m2;
5292
5293         /* Enable autotuning of the PLL clock (if permissible) */
5294         factor = 21;
5295         if (is_lvds) {
5296                 if ((intel_panel_use_ssc(dev_priv) &&
5297                      dev_priv->lvds_ssc_freq == 100) ||
5298                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5299                         factor = 25;
5300         } else if (is_sdvo && is_tv)
5301                 factor = 20;
5302
5303         if (clock.m < factor * clock.n)
5304                 fp |= FP_CB_TUNE;
5305
5306         dpll = 0;
5307
5308         if (is_lvds)
5309                 dpll |= DPLLB_MODE_LVDS;
5310         else
5311                 dpll |= DPLLB_MODE_DAC_SERIAL;
5312         if (is_sdvo) {
5313                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5314                 if (pixel_multiplier > 1) {
5315                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5316                 }
5317                 dpll |= DPLL_DVO_HIGH_SPEED;
5318         }
5319         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5320                 dpll |= DPLL_DVO_HIGH_SPEED;
5321
5322         /* compute bitmask from p1 value */
5323         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5324         /* also FPA1 */
5325         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5326
5327         switch (clock.p2) {
5328         case 5:
5329                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5330                 break;
5331         case 7:
5332                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5333                 break;
5334         case 10:
5335                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5336                 break;
5337         case 14:
5338                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5339                 break;
5340         }
5341
5342         if (is_sdvo && is_tv)
5343                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5344         else if (is_tv)
5345                 /* XXX: just matching BIOS for now */
5346                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5347                 dpll |= 3;
5348         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5349                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5350         else
5351                 dpll |= PLL_REF_INPUT_DREFCLK;
5352
5353         /* setup pipeconf */
5354         pipeconf = I915_READ(PIPECONF(pipe));
5355
5356         /* Set up the display plane register */
5357         dspcntr = DISPPLANE_GAMMA_ENABLE;
5358
5359         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5360         drm_mode_debug_printmodeline(mode);
5361
5362         /* PCH eDP needs FDI, but CPU eDP does not */
5363         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5364                 I915_WRITE(PCH_FP0(pipe), fp);
5365                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5366
5367                 POSTING_READ(PCH_DPLL(pipe));
5368                 udelay(150);
5369         }
5370
5371         /* enable transcoder DPLL */
5372         if (HAS_PCH_CPT(dev)) {
5373                 temp = I915_READ(PCH_DPLL_SEL);
5374                 switch (pipe) {
5375                 case 0:
5376                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5377                         break;
5378                 case 1:
5379                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5380                         break;
5381                 case 2:
5382                         /* FIXME: manage transcoder PLLs? */
5383                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5384                         break;
5385                 default:
5386                         BUG();
5387                 }
5388                 I915_WRITE(PCH_DPLL_SEL, temp);
5389
5390                 POSTING_READ(PCH_DPLL_SEL);
5391                 udelay(150);
5392         }
5393
5394         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5395          * This is an exception to the general rule that mode_set doesn't turn
5396          * things on.
5397          */
5398         if (is_lvds) {
5399                 temp = I915_READ(PCH_LVDS);
5400                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5401                 if (pipe == 1) {
5402                         if (HAS_PCH_CPT(dev))
5403                                 temp |= PORT_TRANS_B_SEL_CPT;
5404                         else
5405                                 temp |= LVDS_PIPEB_SELECT;
5406                 } else {
5407                         if (HAS_PCH_CPT(dev))
5408                                 temp &= ~PORT_TRANS_SEL_MASK;
5409                         else
5410                                 temp &= ~LVDS_PIPEB_SELECT;
5411                 }
5412                 /* set the corresponsding LVDS_BORDER bit */
5413                 temp |= dev_priv->lvds_border_bits;
5414                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5415                  * set the DPLLs for dual-channel mode or not.
5416                  */
5417                 if (clock.p2 == 7)
5418                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5419                 else
5420                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5421
5422                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5423                  * appropriately here, but we need to look more thoroughly into how
5424                  * panels behave in the two modes.
5425                  */
5426                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5427                         lvds_sync |= LVDS_HSYNC_POLARITY;
5428                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5429                         lvds_sync |= LVDS_VSYNC_POLARITY;
5430                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5431                     != lvds_sync) {
5432                         char flags[2] = "-+";
5433                         DRM_INFO("Changing LVDS panel from "
5434                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5435                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5436                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5437                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5438                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5439                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5440                         temp |= lvds_sync;
5441                 }
5442                 I915_WRITE(PCH_LVDS, temp);
5443         }
5444
5445         pipeconf &= ~PIPECONF_DITHER_EN;
5446         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5447         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5448                 pipeconf |= PIPECONF_DITHER_EN;
5449                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5450         }
5451         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5452                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5453         } else {
5454                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5455                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5456                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5457                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5458                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5459         }
5460
5461         if (!has_edp_encoder ||
5462             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5463                 I915_WRITE(PCH_DPLL(pipe), dpll);
5464
5465                 /* Wait for the clocks to stabilize. */
5466                 POSTING_READ(PCH_DPLL(pipe));
5467                 udelay(150);
5468
5469                 /* The pixel multiplier can only be updated once the
5470                  * DPLL is enabled and the clocks are stable.
5471                  *
5472                  * So write it again.
5473                  */
5474                 I915_WRITE(PCH_DPLL(pipe), dpll);
5475         }
5476
5477         intel_crtc->lowfreq_avail = false;
5478         if (is_lvds && has_reduced_clock && i915_powersave) {
5479                 I915_WRITE(PCH_FP1(pipe), fp2);
5480                 intel_crtc->lowfreq_avail = true;
5481                 if (HAS_PIPE_CXSR(dev)) {
5482                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5483                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5484                 }
5485         } else {
5486                 I915_WRITE(PCH_FP1(pipe), fp);
5487                 if (HAS_PIPE_CXSR(dev)) {
5488                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5489                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5490                 }
5491         }
5492
5493         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5494                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5495                 /* the chip adds 2 halflines automatically */
5496                 adjusted_mode->crtc_vdisplay -= 1;
5497                 adjusted_mode->crtc_vtotal -= 1;
5498                 adjusted_mode->crtc_vblank_start -= 1;
5499                 adjusted_mode->crtc_vblank_end -= 1;
5500                 adjusted_mode->crtc_vsync_end -= 1;
5501                 adjusted_mode->crtc_vsync_start -= 1;
5502         } else
5503                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5504
5505         I915_WRITE(HTOTAL(pipe),
5506                    (adjusted_mode->crtc_hdisplay - 1) |
5507                    ((adjusted_mode->crtc_htotal - 1) << 16));
5508         I915_WRITE(HBLANK(pipe),
5509                    (adjusted_mode->crtc_hblank_start - 1) |
5510                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5511         I915_WRITE(HSYNC(pipe),
5512                    (adjusted_mode->crtc_hsync_start - 1) |
5513                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5514
5515         I915_WRITE(VTOTAL(pipe),
5516                    (adjusted_mode->crtc_vdisplay - 1) |
5517                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5518         I915_WRITE(VBLANK(pipe),
5519                    (adjusted_mode->crtc_vblank_start - 1) |
5520                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5521         I915_WRITE(VSYNC(pipe),
5522                    (adjusted_mode->crtc_vsync_start - 1) |
5523                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5524
5525         /* pipesrc controls the size that is scaled from, which should
5526          * always be the user's requested size.
5527          */
5528         I915_WRITE(PIPESRC(pipe),
5529                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5530
5531         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5532         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5533         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5534         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5535
5536         if (has_edp_encoder &&
5537             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5538                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5539         }
5540
5541         I915_WRITE(PIPECONF(pipe), pipeconf);
5542         POSTING_READ(PIPECONF(pipe));
5543
5544         intel_wait_for_vblank(dev, pipe);
5545
5546         if (IS_GEN5(dev)) {
5547                 /* enable address swizzle for tiling buffer */
5548                 temp = I915_READ(DISP_ARB_CTL);
5549                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5550         }
5551
5552         I915_WRITE(DSPCNTR(plane), dspcntr);
5553         POSTING_READ(DSPCNTR(plane));
5554
5555         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5556
5557         intel_update_watermarks(dev);
5558
5559         return ret;
5560 }
5561
5562 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5563                                struct drm_display_mode *mode,
5564                                struct drm_display_mode *adjusted_mode,
5565                                int x, int y,
5566                                struct drm_framebuffer *old_fb)
5567 {
5568         struct drm_device *dev = crtc->dev;
5569         struct drm_i915_private *dev_priv = dev->dev_private;
5570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5571         int pipe = intel_crtc->pipe;
5572         int ret;
5573
5574         drm_vblank_pre_modeset(dev, pipe);
5575
5576         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5577                                               x, y, old_fb);
5578
5579         drm_vblank_post_modeset(dev, pipe);
5580
5581         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5582
5583         return ret;
5584 }
5585
5586 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5587 void intel_crtc_load_lut(struct drm_crtc *crtc)
5588 {
5589         struct drm_device *dev = crtc->dev;
5590         struct drm_i915_private *dev_priv = dev->dev_private;
5591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5592         int palreg = PALETTE(intel_crtc->pipe);
5593         int i;
5594
5595         /* The clocks have to be on to load the palette. */
5596         if (!crtc->enabled)
5597                 return;
5598
5599         /* use legacy palette for Ironlake */
5600         if (HAS_PCH_SPLIT(dev))
5601                 palreg = LGC_PALETTE(intel_crtc->pipe);
5602
5603         for (i = 0; i < 256; i++) {
5604                 I915_WRITE(palreg + 4 * i,
5605                            (intel_crtc->lut_r[i] << 16) |
5606                            (intel_crtc->lut_g[i] << 8) |
5607                            intel_crtc->lut_b[i]);
5608         }
5609 }
5610
5611 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5612 {
5613         struct drm_device *dev = crtc->dev;
5614         struct drm_i915_private *dev_priv = dev->dev_private;
5615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5616         bool visible = base != 0;
5617         u32 cntl;
5618
5619         if (intel_crtc->cursor_visible == visible)
5620                 return;
5621
5622         cntl = I915_READ(_CURACNTR);
5623         if (visible) {
5624                 /* On these chipsets we can only modify the base whilst
5625                  * the cursor is disabled.
5626                  */
5627                 I915_WRITE(_CURABASE, base);
5628
5629                 cntl &= ~(CURSOR_FORMAT_MASK);
5630                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5631                 cntl |= CURSOR_ENABLE |
5632                         CURSOR_GAMMA_ENABLE |
5633                         CURSOR_FORMAT_ARGB;
5634         } else
5635                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5636         I915_WRITE(_CURACNTR, cntl);
5637
5638         intel_crtc->cursor_visible = visible;
5639 }
5640
5641 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5642 {
5643         struct drm_device *dev = crtc->dev;
5644         struct drm_i915_private *dev_priv = dev->dev_private;
5645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5646         int pipe = intel_crtc->pipe;
5647         bool visible = base != 0;
5648
5649         if (intel_crtc->cursor_visible != visible) {
5650                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5651                 if (base) {
5652                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5653                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5654                         cntl |= pipe << 28; /* Connect to correct pipe */
5655                 } else {
5656                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5657                         cntl |= CURSOR_MODE_DISABLE;
5658                 }
5659                 I915_WRITE(CURCNTR(pipe), cntl);
5660
5661                 intel_crtc->cursor_visible = visible;
5662         }
5663         /* and commit changes on next vblank */
5664         I915_WRITE(CURBASE(pipe), base);
5665 }
5666
5667 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5668 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5669                                      bool on)
5670 {
5671         struct drm_device *dev = crtc->dev;
5672         struct drm_i915_private *dev_priv = dev->dev_private;
5673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5674         int pipe = intel_crtc->pipe;
5675         int x = intel_crtc->cursor_x;
5676         int y = intel_crtc->cursor_y;
5677         u32 base, pos;
5678         bool visible;
5679
5680         pos = 0;
5681
5682         if (on && crtc->enabled && crtc->fb) {
5683                 base = intel_crtc->cursor_addr;
5684                 if (x > (int) crtc->fb->width)
5685                         base = 0;
5686
5687                 if (y > (int) crtc->fb->height)
5688                         base = 0;
5689         } else
5690                 base = 0;
5691
5692         if (x < 0) {
5693                 if (x + intel_crtc->cursor_width < 0)
5694                         base = 0;
5695
5696                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5697                 x = -x;
5698         }
5699         pos |= x << CURSOR_X_SHIFT;
5700
5701         if (y < 0) {
5702                 if (y + intel_crtc->cursor_height < 0)
5703                         base = 0;
5704
5705                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5706                 y = -y;
5707         }
5708         pos |= y << CURSOR_Y_SHIFT;
5709
5710         visible = base != 0;
5711         if (!visible && !intel_crtc->cursor_visible)
5712                 return;
5713
5714         I915_WRITE(CURPOS(pipe), pos);
5715         if (IS_845G(dev) || IS_I865G(dev))
5716                 i845_update_cursor(crtc, base);
5717         else
5718                 i9xx_update_cursor(crtc, base);
5719
5720         if (visible)
5721                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5722 }
5723
5724 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5725                                  struct drm_file *file,
5726                                  uint32_t handle,
5727                                  uint32_t width, uint32_t height)
5728 {
5729         struct drm_device *dev = crtc->dev;
5730         struct drm_i915_private *dev_priv = dev->dev_private;
5731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5732         struct drm_i915_gem_object *obj;
5733         uint32_t addr;
5734         int ret;
5735
5736         DRM_DEBUG_KMS("\n");
5737
5738         /* if we want to turn off the cursor ignore width and height */
5739         if (!handle) {
5740                 DRM_DEBUG_KMS("cursor off\n");
5741                 addr = 0;
5742                 obj = NULL;
5743                 mutex_lock(&dev->struct_mutex);
5744                 goto finish;
5745         }
5746
5747         /* Currently we only support 64x64 cursors */
5748         if (width != 64 || height != 64) {
5749                 DRM_ERROR("we currently only support 64x64 cursors\n");
5750                 return -EINVAL;
5751         }
5752
5753         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5754         if (&obj->base == NULL)
5755                 return -ENOENT;
5756
5757         if (obj->base.size < width * height * 4) {
5758                 DRM_ERROR("buffer is to small\n");
5759                 ret = -ENOMEM;
5760                 goto fail;
5761         }
5762
5763         /* we only need to pin inside GTT if cursor is non-phy */
5764         mutex_lock(&dev->struct_mutex);
5765         if (!dev_priv->info->cursor_needs_physical) {
5766                 if (obj->tiling_mode) {
5767                         DRM_ERROR("cursor cannot be tiled\n");
5768                         ret = -EINVAL;
5769                         goto fail_locked;
5770                 }
5771
5772                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5773                 if (ret) {
5774                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5775                         goto fail_locked;
5776                 }
5777
5778                 ret = i915_gem_object_put_fence(obj);
5779                 if (ret) {
5780                         DRM_ERROR("failed to release fence for cursor");
5781                         goto fail_unpin;
5782                 }
5783
5784                 addr = obj->gtt_offset;
5785         } else {
5786                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5787                 ret = i915_gem_attach_phys_object(dev, obj,
5788                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5789                                                   align);
5790                 if (ret) {
5791                         DRM_ERROR("failed to attach phys object\n");
5792                         goto fail_locked;
5793                 }
5794                 addr = obj->phys_obj->handle->busaddr;
5795         }
5796
5797         if (IS_GEN2(dev))
5798                 I915_WRITE(CURSIZE, (height << 12) | width);
5799
5800  finish:
5801         if (intel_crtc->cursor_bo) {
5802                 if (dev_priv->info->cursor_needs_physical) {
5803                         if (intel_crtc->cursor_bo != obj)
5804                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5805                 } else
5806                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5807                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5808         }
5809
5810         mutex_unlock(&dev->struct_mutex);
5811
5812         intel_crtc->cursor_addr = addr;
5813         intel_crtc->cursor_bo = obj;
5814         intel_crtc->cursor_width = width;
5815         intel_crtc->cursor_height = height;
5816
5817         intel_crtc_update_cursor(crtc, true);
5818
5819         return 0;
5820 fail_unpin:
5821         i915_gem_object_unpin(obj);
5822 fail_locked:
5823         mutex_unlock(&dev->struct_mutex);
5824 fail:
5825         drm_gem_object_unreference_unlocked(&obj->base);
5826         return ret;
5827 }
5828
5829 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5830 {
5831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5832
5833         intel_crtc->cursor_x = x;
5834         intel_crtc->cursor_y = y;
5835
5836         intel_crtc_update_cursor(crtc, true);
5837
5838         return 0;
5839 }
5840
5841 /** Sets the color ramps on behalf of RandR */
5842 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5843                                  u16 blue, int regno)
5844 {
5845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5846
5847         intel_crtc->lut_r[regno] = red >> 8;
5848         intel_crtc->lut_g[regno] = green >> 8;
5849         intel_crtc->lut_b[regno] = blue >> 8;
5850 }
5851
5852 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5853                              u16 *blue, int regno)
5854 {
5855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5856
5857         *red = intel_crtc->lut_r[regno] << 8;
5858         *green = intel_crtc->lut_g[regno] << 8;
5859         *blue = intel_crtc->lut_b[regno] << 8;
5860 }
5861
5862 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5863                                  u16 *blue, uint32_t start, uint32_t size)
5864 {
5865         int end = (start + size > 256) ? 256 : start + size, i;
5866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5867
5868         for (i = start; i < end; i++) {
5869                 intel_crtc->lut_r[i] = red[i] >> 8;
5870                 intel_crtc->lut_g[i] = green[i] >> 8;
5871                 intel_crtc->lut_b[i] = blue[i] >> 8;
5872         }
5873
5874         intel_crtc_load_lut(crtc);
5875 }
5876
5877 /**
5878  * Get a pipe with a simple mode set on it for doing load-based monitor
5879  * detection.
5880  *
5881  * It will be up to the load-detect code to adjust the pipe as appropriate for
5882  * its requirements.  The pipe will be connected to no other encoders.
5883  *
5884  * Currently this code will only succeed if there is a pipe with no encoders
5885  * configured for it.  In the future, it could choose to temporarily disable
5886  * some outputs to free up a pipe for its use.
5887  *
5888  * \return crtc, or NULL if no pipes are available.
5889  */
5890
5891 /* VESA 640x480x72Hz mode to set on the pipe */
5892 static struct drm_display_mode load_detect_mode = {
5893         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5894                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5895 };
5896
5897 static struct drm_framebuffer *
5898 intel_framebuffer_create(struct drm_device *dev,
5899                          struct drm_mode_fb_cmd *mode_cmd,
5900                          struct drm_i915_gem_object *obj)
5901 {
5902         struct intel_framebuffer *intel_fb;
5903         int ret;
5904
5905         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5906         if (!intel_fb) {
5907                 drm_gem_object_unreference_unlocked(&obj->base);
5908                 return ERR_PTR(-ENOMEM);
5909         }
5910
5911         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5912         if (ret) {
5913                 drm_gem_object_unreference_unlocked(&obj->base);
5914                 kfree(intel_fb);
5915                 return ERR_PTR(ret);
5916         }
5917
5918         return &intel_fb->base;
5919 }
5920
5921 static u32
5922 intel_framebuffer_pitch_for_width(int width, int bpp)
5923 {
5924         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5925         return ALIGN(pitch, 64);
5926 }
5927
5928 static u32
5929 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5930 {
5931         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5932         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5933 }
5934
5935 static struct drm_framebuffer *
5936 intel_framebuffer_create_for_mode(struct drm_device *dev,
5937                                   struct drm_display_mode *mode,
5938                                   int depth, int bpp)
5939 {
5940         struct drm_i915_gem_object *obj;
5941         struct drm_mode_fb_cmd mode_cmd;
5942
5943         obj = i915_gem_alloc_object(dev,
5944                                     intel_framebuffer_size_for_mode(mode, bpp));
5945         if (obj == NULL)
5946                 return ERR_PTR(-ENOMEM);
5947
5948         mode_cmd.width = mode->hdisplay;
5949         mode_cmd.height = mode->vdisplay;
5950         mode_cmd.depth = depth;
5951         mode_cmd.bpp = bpp;
5952         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5953
5954         return intel_framebuffer_create(dev, &mode_cmd, obj);
5955 }
5956
5957 static struct drm_framebuffer *
5958 mode_fits_in_fbdev(struct drm_device *dev,
5959                    struct drm_display_mode *mode)
5960 {
5961         struct drm_i915_private *dev_priv = dev->dev_private;
5962         struct drm_i915_gem_object *obj;
5963         struct drm_framebuffer *fb;
5964
5965         if (dev_priv->fbdev == NULL)
5966                 return NULL;
5967
5968         obj = dev_priv->fbdev->ifb.obj;
5969         if (obj == NULL)
5970                 return NULL;
5971
5972         fb = &dev_priv->fbdev->ifb.base;
5973         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5974                                                           fb->bits_per_pixel))
5975                 return NULL;
5976
5977         if (obj->base.size < mode->vdisplay * fb->pitch)
5978                 return NULL;
5979
5980         return fb;
5981 }
5982
5983 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5984                                 struct drm_connector *connector,
5985                                 struct drm_display_mode *mode,
5986                                 struct intel_load_detect_pipe *old)
5987 {
5988         struct intel_crtc *intel_crtc;
5989         struct drm_crtc *possible_crtc;
5990         struct drm_encoder *encoder = &intel_encoder->base;
5991         struct drm_crtc *crtc = NULL;
5992         struct drm_device *dev = encoder->dev;
5993         struct drm_framebuffer *old_fb;
5994         int i = -1;
5995
5996         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5997                       connector->base.id, drm_get_connector_name(connector),
5998                       encoder->base.id, drm_get_encoder_name(encoder));
5999
6000         /*
6001          * Algorithm gets a little messy:
6002          *
6003          *   - if the connector already has an assigned crtc, use it (but make
6004          *     sure it's on first)
6005          *
6006          *   - try to find the first unused crtc that can drive this connector,
6007          *     and use that if we find one
6008          */
6009
6010         /* See if we already have a CRTC for this connector */
6011         if (encoder->crtc) {
6012                 crtc = encoder->crtc;
6013
6014                 intel_crtc = to_intel_crtc(crtc);
6015                 old->dpms_mode = intel_crtc->dpms_mode;
6016                 old->load_detect_temp = false;
6017
6018                 /* Make sure the crtc and connector are running */
6019                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6020                         struct drm_encoder_helper_funcs *encoder_funcs;
6021                         struct drm_crtc_helper_funcs *crtc_funcs;
6022
6023                         crtc_funcs = crtc->helper_private;
6024                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6025
6026                         encoder_funcs = encoder->helper_private;
6027                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6028                 }
6029
6030                 return true;
6031         }
6032
6033         /* Find an unused one (if possible) */
6034         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6035                 i++;
6036                 if (!(encoder->possible_crtcs & (1 << i)))
6037                         continue;
6038                 if (!possible_crtc->enabled) {
6039                         crtc = possible_crtc;
6040                         break;
6041                 }
6042         }
6043
6044         /*
6045          * If we didn't find an unused CRTC, don't use any.
6046          */
6047         if (!crtc) {
6048                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6049                 return false;
6050         }
6051
6052         encoder->crtc = crtc;
6053         connector->encoder = encoder;
6054
6055         intel_crtc = to_intel_crtc(crtc);
6056         old->dpms_mode = intel_crtc->dpms_mode;
6057         old->load_detect_temp = true;
6058         old->release_fb = NULL;
6059
6060         if (!mode)
6061                 mode = &load_detect_mode;
6062
6063         old_fb = crtc->fb;
6064
6065         /* We need a framebuffer large enough to accommodate all accesses
6066          * that the plane may generate whilst we perform load detection.
6067          * We can not rely on the fbcon either being present (we get called
6068          * during its initialisation to detect all boot displays, or it may
6069          * not even exist) or that it is large enough to satisfy the
6070          * requested mode.
6071          */
6072         crtc->fb = mode_fits_in_fbdev(dev, mode);
6073         if (crtc->fb == NULL) {
6074                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6075                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6076                 old->release_fb = crtc->fb;
6077         } else
6078                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6079         if (IS_ERR(crtc->fb)) {
6080                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6081                 crtc->fb = old_fb;
6082                 return false;
6083         }
6084
6085         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6086                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6087                 if (old->release_fb)
6088                         old->release_fb->funcs->destroy(old->release_fb);
6089                 crtc->fb = old_fb;
6090                 return false;
6091         }
6092
6093         /* let the connector get through one full cycle before testing */
6094         intel_wait_for_vblank(dev, intel_crtc->pipe);
6095
6096         return true;
6097 }
6098
6099 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6100                                     struct drm_connector *connector,
6101                                     struct intel_load_detect_pipe *old)
6102 {
6103         struct drm_encoder *encoder = &intel_encoder->base;
6104         struct drm_device *dev = encoder->dev;
6105         struct drm_crtc *crtc = encoder->crtc;
6106         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6107         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6108
6109         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6110                       connector->base.id, drm_get_connector_name(connector),
6111                       encoder->base.id, drm_get_encoder_name(encoder));
6112
6113         if (old->load_detect_temp) {
6114                 connector->encoder = NULL;
6115                 drm_helper_disable_unused_functions(dev);
6116
6117                 if (old->release_fb)
6118                         old->release_fb->funcs->destroy(old->release_fb);
6119
6120                 return;
6121         }
6122
6123         /* Switch crtc and encoder back off if necessary */
6124         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6125                 encoder_funcs->dpms(encoder, old->dpms_mode);
6126                 crtc_funcs->dpms(crtc, old->dpms_mode);
6127         }
6128 }
6129
6130 /* Returns the clock of the currently programmed mode of the given pipe. */
6131 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6132 {
6133         struct drm_i915_private *dev_priv = dev->dev_private;
6134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135         int pipe = intel_crtc->pipe;
6136         u32 dpll = I915_READ(DPLL(pipe));
6137         u32 fp;
6138         intel_clock_t clock;
6139
6140         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6141                 fp = I915_READ(FP0(pipe));
6142         else
6143                 fp = I915_READ(FP1(pipe));
6144
6145         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6146         if (IS_PINEVIEW(dev)) {
6147                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6148                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6149         } else {
6150                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6151                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6152         }
6153
6154         if (!IS_GEN2(dev)) {
6155                 if (IS_PINEVIEW(dev))
6156                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6157                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6158                 else
6159                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6160                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6161
6162                 switch (dpll & DPLL_MODE_MASK) {
6163                 case DPLLB_MODE_DAC_SERIAL:
6164                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6165                                 5 : 10;
6166                         break;
6167                 case DPLLB_MODE_LVDS:
6168                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6169                                 7 : 14;
6170                         break;
6171                 default:
6172                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6173                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6174                         return 0;
6175                 }
6176
6177                 /* XXX: Handle the 100Mhz refclk */
6178                 intel_clock(dev, 96000, &clock);
6179         } else {
6180                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6181
6182                 if (is_lvds) {
6183                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6184                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6185                         clock.p2 = 14;
6186
6187                         if ((dpll & PLL_REF_INPUT_MASK) ==
6188                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6189                                 /* XXX: might not be 66MHz */
6190                                 intel_clock(dev, 66000, &clock);
6191                         } else
6192                                 intel_clock(dev, 48000, &clock);
6193                 } else {
6194                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6195                                 clock.p1 = 2;
6196                         else {
6197                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6198                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6199                         }
6200                         if (dpll & PLL_P2_DIVIDE_BY_4)
6201                                 clock.p2 = 4;
6202                         else
6203                                 clock.p2 = 2;
6204
6205                         intel_clock(dev, 48000, &clock);
6206                 }
6207         }
6208
6209         /* XXX: It would be nice to validate the clocks, but we can't reuse
6210          * i830PllIsValid() because it relies on the xf86_config connector
6211          * configuration being accurate, which it isn't necessarily.
6212          */
6213
6214         return clock.dot;
6215 }
6216
6217 /** Returns the currently programmed mode of the given pipe. */
6218 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6219                                              struct drm_crtc *crtc)
6220 {
6221         struct drm_i915_private *dev_priv = dev->dev_private;
6222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6223         int pipe = intel_crtc->pipe;
6224         struct drm_display_mode *mode;
6225         int htot = I915_READ(HTOTAL(pipe));
6226         int hsync = I915_READ(HSYNC(pipe));
6227         int vtot = I915_READ(VTOTAL(pipe));
6228         int vsync = I915_READ(VSYNC(pipe));
6229
6230         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6231         if (!mode)
6232                 return NULL;
6233
6234         mode->clock = intel_crtc_clock_get(dev, crtc);
6235         mode->hdisplay = (htot & 0xffff) + 1;
6236         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6237         mode->hsync_start = (hsync & 0xffff) + 1;
6238         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6239         mode->vdisplay = (vtot & 0xffff) + 1;
6240         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6241         mode->vsync_start = (vsync & 0xffff) + 1;
6242         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6243
6244         drm_mode_set_name(mode);
6245         drm_mode_set_crtcinfo(mode, 0);
6246
6247         return mode;
6248 }
6249
6250 #define GPU_IDLE_TIMEOUT 500 /* ms */
6251
6252 /* When this timer fires, we've been idle for awhile */
6253 static void intel_gpu_idle_timer(unsigned long arg)
6254 {
6255         struct drm_device *dev = (struct drm_device *)arg;
6256         drm_i915_private_t *dev_priv = dev->dev_private;
6257
6258         if (!list_empty(&dev_priv->mm.active_list)) {
6259                 /* Still processing requests, so just re-arm the timer. */
6260                 mod_timer(&dev_priv->idle_timer, jiffies +
6261                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6262                 return;
6263         }
6264
6265         dev_priv->busy = false;
6266         queue_work(dev_priv->wq, &dev_priv->idle_work);
6267 }
6268
6269 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6270
6271 static void intel_crtc_idle_timer(unsigned long arg)
6272 {
6273         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6274         struct drm_crtc *crtc = &intel_crtc->base;
6275         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6276         struct intel_framebuffer *intel_fb;
6277
6278         intel_fb = to_intel_framebuffer(crtc->fb);
6279         if (intel_fb && intel_fb->obj->active) {
6280                 /* The framebuffer is still being accessed by the GPU. */
6281                 mod_timer(&intel_crtc->idle_timer, jiffies +
6282                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6283                 return;
6284         }
6285
6286         intel_crtc->busy = false;
6287         queue_work(dev_priv->wq, &dev_priv->idle_work);
6288 }
6289
6290 static void intel_increase_pllclock(struct drm_crtc *crtc)
6291 {
6292         struct drm_device *dev = crtc->dev;
6293         drm_i915_private_t *dev_priv = dev->dev_private;
6294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6295         int pipe = intel_crtc->pipe;
6296         int dpll_reg = DPLL(pipe);
6297         int dpll;
6298
6299         if (HAS_PCH_SPLIT(dev))
6300                 return;
6301
6302         if (!dev_priv->lvds_downclock_avail)
6303                 return;
6304
6305         dpll = I915_READ(dpll_reg);
6306         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6307                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6308
6309                 /* Unlock panel regs */
6310                 I915_WRITE(PP_CONTROL,
6311                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6312
6313                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6314                 I915_WRITE(dpll_reg, dpll);
6315                 intel_wait_for_vblank(dev, pipe);
6316
6317                 dpll = I915_READ(dpll_reg);
6318                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6319                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6320
6321                 /* ...and lock them again */
6322                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6323         }
6324
6325         /* Schedule downclock */
6326         mod_timer(&intel_crtc->idle_timer, jiffies +
6327                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6328 }
6329
6330 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6331 {
6332         struct drm_device *dev = crtc->dev;
6333         drm_i915_private_t *dev_priv = dev->dev_private;
6334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335         int pipe = intel_crtc->pipe;
6336         int dpll_reg = DPLL(pipe);
6337         int dpll = I915_READ(dpll_reg);
6338
6339         if (HAS_PCH_SPLIT(dev))
6340                 return;
6341
6342         if (!dev_priv->lvds_downclock_avail)
6343                 return;
6344
6345         /*
6346          * Since this is called by a timer, we should never get here in
6347          * the manual case.
6348          */
6349         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6350                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6351
6352                 /* Unlock panel regs */
6353                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6354                            PANEL_UNLOCK_REGS);
6355
6356                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6357                 I915_WRITE(dpll_reg, dpll);
6358                 intel_wait_for_vblank(dev, pipe);
6359                 dpll = I915_READ(dpll_reg);
6360                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6361                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6362
6363                 /* ...and lock them again */
6364                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6365         }
6366
6367 }
6368
6369 /**
6370  * intel_idle_update - adjust clocks for idleness
6371  * @work: work struct
6372  *
6373  * Either the GPU or display (or both) went idle.  Check the busy status
6374  * here and adjust the CRTC and GPU clocks as necessary.
6375  */
6376 static void intel_idle_update(struct work_struct *work)
6377 {
6378         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6379                                                     idle_work);
6380         struct drm_device *dev = dev_priv->dev;
6381         struct drm_crtc *crtc;
6382         struct intel_crtc *intel_crtc;
6383
6384         if (!i915_powersave)
6385                 return;
6386
6387         mutex_lock(&dev->struct_mutex);
6388
6389         i915_update_gfx_val(dev_priv);
6390
6391         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6392                 /* Skip inactive CRTCs */
6393                 if (!crtc->fb)
6394                         continue;
6395
6396                 intel_crtc = to_intel_crtc(crtc);
6397                 if (!intel_crtc->busy)
6398                         intel_decrease_pllclock(crtc);
6399         }
6400
6401
6402         mutex_unlock(&dev->struct_mutex);
6403 }
6404
6405 /**
6406  * intel_mark_busy - mark the GPU and possibly the display busy
6407  * @dev: drm device
6408  * @obj: object we're operating on
6409  *
6410  * Callers can use this function to indicate that the GPU is busy processing
6411  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6412  * buffer), we'll also mark the display as busy, so we know to increase its
6413  * clock frequency.
6414  */
6415 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6416 {
6417         drm_i915_private_t *dev_priv = dev->dev_private;
6418         struct drm_crtc *crtc = NULL;
6419         struct intel_framebuffer *intel_fb;
6420         struct intel_crtc *intel_crtc;
6421
6422         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6423                 return;
6424
6425         if (!dev_priv->busy)
6426                 dev_priv->busy = true;
6427         else
6428                 mod_timer(&dev_priv->idle_timer, jiffies +
6429                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6430
6431         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6432                 if (!crtc->fb)
6433                         continue;
6434
6435                 intel_crtc = to_intel_crtc(crtc);
6436                 intel_fb = to_intel_framebuffer(crtc->fb);
6437                 if (intel_fb->obj == obj) {
6438                         if (!intel_crtc->busy) {
6439                                 /* Non-busy -> busy, upclock */
6440                                 intel_increase_pllclock(crtc);
6441                                 intel_crtc->busy = true;
6442                         } else {
6443                                 /* Busy -> busy, put off timer */
6444                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6445                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6446                         }
6447                 }
6448         }
6449 }
6450
6451 static void intel_crtc_destroy(struct drm_crtc *crtc)
6452 {
6453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6454         struct drm_device *dev = crtc->dev;
6455         struct intel_unpin_work *work;
6456         unsigned long flags;
6457
6458         spin_lock_irqsave(&dev->event_lock, flags);
6459         work = intel_crtc->unpin_work;
6460         intel_crtc->unpin_work = NULL;
6461         spin_unlock_irqrestore(&dev->event_lock, flags);
6462
6463         if (work) {
6464                 cancel_work_sync(&work->work);
6465                 kfree(work);
6466         }
6467
6468         drm_crtc_cleanup(crtc);
6469
6470         kfree(intel_crtc);
6471 }
6472
6473 static void intel_unpin_work_fn(struct work_struct *__work)
6474 {
6475         struct intel_unpin_work *work =
6476                 container_of(__work, struct intel_unpin_work, work);
6477
6478         mutex_lock(&work->dev->struct_mutex);
6479         i915_gem_object_unpin(work->old_fb_obj);
6480         drm_gem_object_unreference(&work->pending_flip_obj->base);
6481         drm_gem_object_unreference(&work->old_fb_obj->base);
6482
6483         intel_update_fbc(work->dev);
6484         mutex_unlock(&work->dev->struct_mutex);
6485         kfree(work);
6486 }
6487
6488 static void do_intel_finish_page_flip(struct drm_device *dev,
6489                                       struct drm_crtc *crtc)
6490 {
6491         drm_i915_private_t *dev_priv = dev->dev_private;
6492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6493         struct intel_unpin_work *work;
6494         struct drm_i915_gem_object *obj;
6495         struct drm_pending_vblank_event *e;
6496         struct timeval tnow, tvbl;
6497         unsigned long flags;
6498
6499         /* Ignore early vblank irqs */
6500         if (intel_crtc == NULL)
6501                 return;
6502
6503         do_gettimeofday(&tnow);
6504
6505         spin_lock_irqsave(&dev->event_lock, flags);
6506         work = intel_crtc->unpin_work;
6507         if (work == NULL || !work->pending) {
6508                 spin_unlock_irqrestore(&dev->event_lock, flags);
6509                 return;
6510         }
6511
6512         intel_crtc->unpin_work = NULL;
6513
6514         if (work->event) {
6515                 e = work->event;
6516                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6517
6518                 /* Called before vblank count and timestamps have
6519                  * been updated for the vblank interval of flip
6520                  * completion? Need to increment vblank count and
6521                  * add one videorefresh duration to returned timestamp
6522                  * to account for this. We assume this happened if we
6523                  * get called over 0.9 frame durations after the last
6524                  * timestamped vblank.
6525                  *
6526                  * This calculation can not be used with vrefresh rates
6527                  * below 5Hz (10Hz to be on the safe side) without
6528                  * promoting to 64 integers.
6529                  */
6530                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6531                     9 * crtc->framedur_ns) {
6532                         e->event.sequence++;
6533                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6534                                              crtc->framedur_ns);
6535                 }
6536
6537                 e->event.tv_sec = tvbl.tv_sec;
6538                 e->event.tv_usec = tvbl.tv_usec;
6539
6540                 list_add_tail(&e->base.link,
6541                               &e->base.file_priv->event_list);
6542                 wake_up_interruptible(&e->base.file_priv->event_wait);
6543         }
6544
6545         drm_vblank_put(dev, intel_crtc->pipe);
6546
6547         spin_unlock_irqrestore(&dev->event_lock, flags);
6548
6549         obj = work->old_fb_obj;
6550
6551         atomic_clear_mask(1 << intel_crtc->plane,
6552                           &obj->pending_flip.counter);
6553         if (atomic_read(&obj->pending_flip) == 0)
6554                 wake_up(&dev_priv->pending_flip_queue);
6555
6556         schedule_work(&work->work);
6557
6558         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6559 }
6560
6561 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6562 {
6563         drm_i915_private_t *dev_priv = dev->dev_private;
6564         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6565
6566         do_intel_finish_page_flip(dev, crtc);
6567 }
6568
6569 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6570 {
6571         drm_i915_private_t *dev_priv = dev->dev_private;
6572         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6573
6574         do_intel_finish_page_flip(dev, crtc);
6575 }
6576
6577 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6578 {
6579         drm_i915_private_t *dev_priv = dev->dev_private;
6580         struct intel_crtc *intel_crtc =
6581                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6582         unsigned long flags;
6583
6584         spin_lock_irqsave(&dev->event_lock, flags);
6585         if (intel_crtc->unpin_work) {
6586                 if ((++intel_crtc->unpin_work->pending) > 1)
6587                         DRM_ERROR("Prepared flip multiple times\n");
6588         } else {
6589                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6590         }
6591         spin_unlock_irqrestore(&dev->event_lock, flags);
6592 }
6593
6594 static int intel_gen2_queue_flip(struct drm_device *dev,
6595                                  struct drm_crtc *crtc,
6596                                  struct drm_framebuffer *fb,
6597                                  struct drm_i915_gem_object *obj)
6598 {
6599         struct drm_i915_private *dev_priv = dev->dev_private;
6600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601         unsigned long offset;
6602         u32 flip_mask;
6603         int ret;
6604
6605         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6606         if (ret)
6607                 goto out;
6608
6609         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6610         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6611
6612         ret = BEGIN_LP_RING(6);
6613         if (ret)
6614                 goto out;
6615
6616         /* Can't queue multiple flips, so wait for the previous
6617          * one to finish before executing the next.
6618          */
6619         if (intel_crtc->plane)
6620                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6621         else
6622                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6623         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6624         OUT_RING(MI_NOOP);
6625         OUT_RING(MI_DISPLAY_FLIP |
6626                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6627         OUT_RING(fb->pitch);
6628         OUT_RING(obj->gtt_offset + offset);
6629         OUT_RING(MI_NOOP);
6630         ADVANCE_LP_RING();
6631 out:
6632         return ret;
6633 }
6634
6635 static int intel_gen3_queue_flip(struct drm_device *dev,
6636                                  struct drm_crtc *crtc,
6637                                  struct drm_framebuffer *fb,
6638                                  struct drm_i915_gem_object *obj)
6639 {
6640         struct drm_i915_private *dev_priv = dev->dev_private;
6641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6642         unsigned long offset;
6643         u32 flip_mask;
6644         int ret;
6645
6646         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6647         if (ret)
6648                 goto out;
6649
6650         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6651         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6652
6653         ret = BEGIN_LP_RING(6);
6654         if (ret)
6655                 goto out;
6656
6657         if (intel_crtc->plane)
6658                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6659         else
6660                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6661         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6662         OUT_RING(MI_NOOP);
6663         OUT_RING(MI_DISPLAY_FLIP_I915 |
6664                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6665         OUT_RING(fb->pitch);
6666         OUT_RING(obj->gtt_offset + offset);
6667         OUT_RING(MI_NOOP);
6668
6669         ADVANCE_LP_RING();
6670 out:
6671         return ret;
6672 }
6673
6674 static int intel_gen4_queue_flip(struct drm_device *dev,
6675                                  struct drm_crtc *crtc,
6676                                  struct drm_framebuffer *fb,
6677                                  struct drm_i915_gem_object *obj)
6678 {
6679         struct drm_i915_private *dev_priv = dev->dev_private;
6680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6681         uint32_t pf, pipesrc;
6682         int ret;
6683
6684         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6685         if (ret)
6686                 goto out;
6687
6688         ret = BEGIN_LP_RING(4);
6689         if (ret)
6690                 goto out;
6691
6692         /* i965+ uses the linear or tiled offsets from the
6693          * Display Registers (which do not change across a page-flip)
6694          * so we need only reprogram the base address.
6695          */
6696         OUT_RING(MI_DISPLAY_FLIP |
6697                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6698         OUT_RING(fb->pitch);
6699         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6700
6701         /* XXX Enabling the panel-fitter across page-flip is so far
6702          * untested on non-native modes, so ignore it for now.
6703          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6704          */
6705         pf = 0;
6706         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6707         OUT_RING(pf | pipesrc);
6708         ADVANCE_LP_RING();
6709 out:
6710         return ret;
6711 }
6712
6713 static int intel_gen6_queue_flip(struct drm_device *dev,
6714                                  struct drm_crtc *crtc,
6715                                  struct drm_framebuffer *fb,
6716                                  struct drm_i915_gem_object *obj)
6717 {
6718         struct drm_i915_private *dev_priv = dev->dev_private;
6719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6720         uint32_t pf, pipesrc;
6721         int ret;
6722
6723         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6724         if (ret)
6725                 goto out;
6726
6727         ret = BEGIN_LP_RING(4);
6728         if (ret)
6729                 goto out;
6730
6731         OUT_RING(MI_DISPLAY_FLIP |
6732                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6733         OUT_RING(fb->pitch | obj->tiling_mode);
6734         OUT_RING(obj->gtt_offset);
6735
6736         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6737         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6738         OUT_RING(pf | pipesrc);
6739         ADVANCE_LP_RING();
6740 out:
6741         return ret;
6742 }
6743
6744 /*
6745  * On gen7 we currently use the blit ring because (in early silicon at least)
6746  * the render ring doesn't give us interrpts for page flip completion, which
6747  * means clients will hang after the first flip is queued.  Fortunately the
6748  * blit ring generates interrupts properly, so use it instead.
6749  */
6750 static int intel_gen7_queue_flip(struct drm_device *dev,
6751                                  struct drm_crtc *crtc,
6752                                  struct drm_framebuffer *fb,
6753                                  struct drm_i915_gem_object *obj)
6754 {
6755         struct drm_i915_private *dev_priv = dev->dev_private;
6756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6757         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6758         int ret;
6759
6760         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6761         if (ret)
6762                 goto out;
6763
6764         ret = intel_ring_begin(ring, 4);
6765         if (ret)
6766                 goto out;
6767
6768         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6769         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6770         intel_ring_emit(ring, (obj->gtt_offset));
6771         intel_ring_emit(ring, (MI_NOOP));
6772         intel_ring_advance(ring);
6773 out:
6774         return ret;
6775 }
6776
6777 static int intel_default_queue_flip(struct drm_device *dev,
6778                                     struct drm_crtc *crtc,
6779                                     struct drm_framebuffer *fb,
6780                                     struct drm_i915_gem_object *obj)
6781 {
6782         return -ENODEV;
6783 }
6784
6785 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6786                                 struct drm_framebuffer *fb,
6787                                 struct drm_pending_vblank_event *event)
6788 {
6789         struct drm_device *dev = crtc->dev;
6790         struct drm_i915_private *dev_priv = dev->dev_private;
6791         struct intel_framebuffer *intel_fb;
6792         struct drm_i915_gem_object *obj;
6793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6794         struct intel_unpin_work *work;
6795         unsigned long flags;
6796         int ret;
6797
6798         work = kzalloc(sizeof *work, GFP_KERNEL);
6799         if (work == NULL)
6800                 return -ENOMEM;
6801
6802         work->event = event;
6803         work->dev = crtc->dev;
6804         intel_fb = to_intel_framebuffer(crtc->fb);
6805         work->old_fb_obj = intel_fb->obj;
6806         INIT_WORK(&work->work, intel_unpin_work_fn);
6807
6808         /* We borrow the event spin lock for protecting unpin_work */
6809         spin_lock_irqsave(&dev->event_lock, flags);
6810         if (intel_crtc->unpin_work) {
6811                 spin_unlock_irqrestore(&dev->event_lock, flags);
6812                 kfree(work);
6813
6814                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6815                 return -EBUSY;
6816         }
6817         intel_crtc->unpin_work = work;
6818         spin_unlock_irqrestore(&dev->event_lock, flags);
6819
6820         intel_fb = to_intel_framebuffer(fb);
6821         obj = intel_fb->obj;
6822
6823         mutex_lock(&dev->struct_mutex);
6824
6825         /* Reference the objects for the scheduled work. */
6826         drm_gem_object_reference(&work->old_fb_obj->base);
6827         drm_gem_object_reference(&obj->base);
6828
6829         crtc->fb = fb;
6830
6831         ret = drm_vblank_get(dev, intel_crtc->pipe);
6832         if (ret)
6833                 goto cleanup_objs;
6834
6835         work->pending_flip_obj = obj;
6836
6837         work->enable_stall_check = true;
6838
6839         /* Block clients from rendering to the new back buffer until
6840          * the flip occurs and the object is no longer visible.
6841          */
6842         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6843
6844         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6845         if (ret)
6846                 goto cleanup_pending;
6847
6848         intel_disable_fbc(dev);
6849         mutex_unlock(&dev->struct_mutex);
6850
6851         trace_i915_flip_request(intel_crtc->plane, obj);
6852
6853         return 0;
6854
6855 cleanup_pending:
6856         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6857 cleanup_objs:
6858         drm_gem_object_unreference(&work->old_fb_obj->base);
6859         drm_gem_object_unreference(&obj->base);
6860         mutex_unlock(&dev->struct_mutex);
6861
6862         spin_lock_irqsave(&dev->event_lock, flags);
6863         intel_crtc->unpin_work = NULL;
6864         spin_unlock_irqrestore(&dev->event_lock, flags);
6865
6866         kfree(work);
6867
6868         return ret;
6869 }
6870
6871 static void intel_sanitize_modesetting(struct drm_device *dev,
6872                                        int pipe, int plane)
6873 {
6874         struct drm_i915_private *dev_priv = dev->dev_private;
6875         u32 reg, val;
6876
6877         if (HAS_PCH_SPLIT(dev))
6878                 return;
6879
6880         /* Who knows what state these registers were left in by the BIOS or
6881          * grub?
6882          *
6883          * If we leave the registers in a conflicting state (e.g. with the
6884          * display plane reading from the other pipe than the one we intend
6885          * to use) then when we attempt to teardown the active mode, we will
6886          * not disable the pipes and planes in the correct order -- leaving
6887          * a plane reading from a disabled pipe and possibly leading to
6888          * undefined behaviour.
6889          */
6890
6891         reg = DSPCNTR(plane);
6892         val = I915_READ(reg);
6893
6894         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6895                 return;
6896         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6897                 return;
6898
6899         /* This display plane is active and attached to the other CPU pipe. */
6900         pipe = !pipe;
6901
6902         /* Disable the plane and wait for it to stop reading from the pipe. */
6903         intel_disable_plane(dev_priv, plane, pipe);
6904         intel_disable_pipe(dev_priv, pipe);
6905 }
6906
6907 static void intel_crtc_reset(struct drm_crtc *crtc)
6908 {
6909         struct drm_device *dev = crtc->dev;
6910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6911
6912         /* Reset flags back to the 'unknown' status so that they
6913          * will be correctly set on the initial modeset.
6914          */
6915         intel_crtc->dpms_mode = -1;
6916
6917         /* We need to fix up any BIOS configuration that conflicts with
6918          * our expectations.
6919          */
6920         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6921 }
6922
6923 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6924         .dpms = intel_crtc_dpms,
6925         .mode_fixup = intel_crtc_mode_fixup,
6926         .mode_set = intel_crtc_mode_set,
6927         .mode_set_base = intel_pipe_set_base,
6928         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6929         .load_lut = intel_crtc_load_lut,
6930         .disable = intel_crtc_disable,
6931 };
6932
6933 static const struct drm_crtc_funcs intel_crtc_funcs = {
6934         .reset = intel_crtc_reset,
6935         .cursor_set = intel_crtc_cursor_set,
6936         .cursor_move = intel_crtc_cursor_move,
6937         .gamma_set = intel_crtc_gamma_set,
6938         .set_config = drm_crtc_helper_set_config,
6939         .destroy = intel_crtc_destroy,
6940         .page_flip = intel_crtc_page_flip,
6941 };
6942
6943 static void intel_crtc_init(struct drm_device *dev, int pipe)
6944 {
6945         drm_i915_private_t *dev_priv = dev->dev_private;
6946         struct intel_crtc *intel_crtc;
6947         int i;
6948
6949         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6950         if (intel_crtc == NULL)
6951                 return;
6952
6953         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6954
6955         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6956         for (i = 0; i < 256; i++) {
6957                 intel_crtc->lut_r[i] = i;
6958                 intel_crtc->lut_g[i] = i;
6959                 intel_crtc->lut_b[i] = i;
6960         }
6961
6962         /* Swap pipes & planes for FBC on pre-965 */
6963         intel_crtc->pipe = pipe;
6964         intel_crtc->plane = pipe;
6965         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6966                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6967                 intel_crtc->plane = !pipe;
6968         }
6969
6970         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6971                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6972         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6973         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6974
6975         intel_crtc_reset(&intel_crtc->base);
6976         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6977         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6978
6979         if (HAS_PCH_SPLIT(dev)) {
6980                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6981                 intel_helper_funcs.commit = ironlake_crtc_commit;
6982         } else {
6983                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6984                 intel_helper_funcs.commit = i9xx_crtc_commit;
6985         }
6986
6987         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6988
6989         intel_crtc->busy = false;
6990
6991         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6992                     (unsigned long)intel_crtc);
6993 }
6994
6995 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6996                                 struct drm_file *file)
6997 {
6998         drm_i915_private_t *dev_priv = dev->dev_private;
6999         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7000         struct drm_mode_object *drmmode_obj;
7001         struct intel_crtc *crtc;
7002
7003         if (!dev_priv) {
7004                 DRM_ERROR("called with no initialization\n");
7005                 return -EINVAL;
7006         }
7007
7008         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7009                         DRM_MODE_OBJECT_CRTC);
7010
7011         if (!drmmode_obj) {
7012                 DRM_ERROR("no such CRTC id\n");
7013                 return -EINVAL;
7014         }
7015
7016         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7017         pipe_from_crtc_id->pipe = crtc->pipe;
7018
7019         return 0;
7020 }
7021
7022 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7023 {
7024         struct intel_encoder *encoder;
7025         int index_mask = 0;
7026         int entry = 0;
7027
7028         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7029                 if (type_mask & encoder->clone_mask)
7030                         index_mask |= (1 << entry);
7031                 entry++;
7032         }
7033
7034         return index_mask;
7035 }
7036
7037 static bool has_edp_a(struct drm_device *dev)
7038 {
7039         struct drm_i915_private *dev_priv = dev->dev_private;
7040
7041         if (!IS_MOBILE(dev))
7042                 return false;
7043
7044         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7045                 return false;
7046
7047         if (IS_GEN5(dev) &&
7048             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7049                 return false;
7050
7051         return true;
7052 }
7053
7054 static void intel_setup_outputs(struct drm_device *dev)
7055 {
7056         struct drm_i915_private *dev_priv = dev->dev_private;
7057         struct intel_encoder *encoder;
7058         bool dpd_is_edp = false;
7059         bool has_lvds = false;
7060
7061         if (IS_MOBILE(dev) && !IS_I830(dev))
7062                 has_lvds = intel_lvds_init(dev);
7063         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7064                 /* disable the panel fitter on everything but LVDS */
7065                 I915_WRITE(PFIT_CONTROL, 0);
7066         }
7067
7068         if (HAS_PCH_SPLIT(dev)) {
7069                 dpd_is_edp = intel_dpd_is_edp(dev);
7070
7071                 if (has_edp_a(dev))
7072                         intel_dp_init(dev, DP_A);
7073
7074                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7075                         intel_dp_init(dev, PCH_DP_D);
7076         }
7077
7078         intel_crt_init(dev);
7079
7080         if (HAS_PCH_SPLIT(dev)) {
7081                 int found;
7082
7083                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7084                         /* PCH SDVOB multiplex with HDMIB */
7085                         found = intel_sdvo_init(dev, PCH_SDVOB);
7086                         if (!found)
7087                                 intel_hdmi_init(dev, HDMIB);
7088                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7089                                 intel_dp_init(dev, PCH_DP_B);
7090                 }
7091
7092                 if (I915_READ(HDMIC) & PORT_DETECTED)
7093                         intel_hdmi_init(dev, HDMIC);
7094
7095                 if (I915_READ(HDMID) & PORT_DETECTED)
7096                         intel_hdmi_init(dev, HDMID);
7097
7098                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7099                         intel_dp_init(dev, PCH_DP_C);
7100
7101                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7102                         intel_dp_init(dev, PCH_DP_D);
7103
7104         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7105                 bool found = false;
7106
7107                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7108                         DRM_DEBUG_KMS("probing SDVOB\n");
7109                         found = intel_sdvo_init(dev, SDVOB);
7110                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7111                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7112                                 intel_hdmi_init(dev, SDVOB);
7113                         }
7114
7115                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7116                                 DRM_DEBUG_KMS("probing DP_B\n");
7117                                 intel_dp_init(dev, DP_B);
7118                         }
7119                 }
7120
7121                 /* Before G4X SDVOC doesn't have its own detect register */
7122
7123                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7124                         DRM_DEBUG_KMS("probing SDVOC\n");
7125                         found = intel_sdvo_init(dev, SDVOC);
7126                 }
7127
7128                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7129
7130                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7131                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7132                                 intel_hdmi_init(dev, SDVOC);
7133                         }
7134                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7135                                 DRM_DEBUG_KMS("probing DP_C\n");
7136                                 intel_dp_init(dev, DP_C);
7137                         }
7138                 }
7139
7140                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7141                     (I915_READ(DP_D) & DP_DETECTED)) {
7142                         DRM_DEBUG_KMS("probing DP_D\n");
7143                         intel_dp_init(dev, DP_D);
7144                 }
7145         } else if (IS_GEN2(dev))
7146                 intel_dvo_init(dev);
7147
7148         if (SUPPORTS_TV(dev))
7149                 intel_tv_init(dev);
7150
7151         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7152                 encoder->base.possible_crtcs = encoder->crtc_mask;
7153                 encoder->base.possible_clones =
7154                         intel_encoder_clones(dev, encoder->clone_mask);
7155         }
7156
7157         intel_panel_setup_backlight(dev);
7158
7159         /* disable all the possible outputs/crtcs before entering KMS mode */
7160         drm_helper_disable_unused_functions(dev);
7161 }
7162
7163 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7164 {
7165         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7166
7167         drm_framebuffer_cleanup(fb);
7168         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7169
7170         kfree(intel_fb);
7171 }
7172
7173 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7174                                                 struct drm_file *file,
7175                                                 unsigned int *handle)
7176 {
7177         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7178         struct drm_i915_gem_object *obj = intel_fb->obj;
7179
7180         return drm_gem_handle_create(file, &obj->base, handle);
7181 }
7182
7183 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7184         .destroy = intel_user_framebuffer_destroy,
7185         .create_handle = intel_user_framebuffer_create_handle,
7186 };
7187
7188 int intel_framebuffer_init(struct drm_device *dev,
7189                            struct intel_framebuffer *intel_fb,
7190                            struct drm_mode_fb_cmd *mode_cmd,
7191                            struct drm_i915_gem_object *obj)
7192 {
7193         int ret;
7194
7195         if (obj->tiling_mode == I915_TILING_Y)
7196                 return -EINVAL;
7197
7198         if (mode_cmd->pitch & 63)
7199                 return -EINVAL;
7200
7201         switch (mode_cmd->bpp) {
7202         case 8:
7203         case 16:
7204                 /* Only pre-ILK can handle 5:5:5 */
7205                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7206                         return -EINVAL;
7207                 break;
7208
7209         case 24:
7210         case 32:
7211                 break;
7212         default:
7213                 return -EINVAL;
7214         }
7215
7216         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7217         if (ret) {
7218                 DRM_ERROR("framebuffer init failed %d\n", ret);
7219                 return ret;
7220         }
7221
7222         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7223         intel_fb->obj = obj;
7224         return 0;
7225 }
7226
7227 static struct drm_framebuffer *
7228 intel_user_framebuffer_create(struct drm_device *dev,
7229                               struct drm_file *filp,
7230                               struct drm_mode_fb_cmd *mode_cmd)
7231 {
7232         struct drm_i915_gem_object *obj;
7233
7234         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7235         if (&obj->base == NULL)
7236                 return ERR_PTR(-ENOENT);
7237
7238         return intel_framebuffer_create(dev, mode_cmd, obj);
7239 }
7240
7241 static const struct drm_mode_config_funcs intel_mode_funcs = {
7242         .fb_create = intel_user_framebuffer_create,
7243         .output_poll_changed = intel_fb_output_poll_changed,
7244 };
7245
7246 static struct drm_i915_gem_object *
7247 intel_alloc_context_page(struct drm_device *dev)
7248 {
7249         struct drm_i915_gem_object *ctx;
7250         int ret;
7251
7252         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7253
7254         ctx = i915_gem_alloc_object(dev, 4096);
7255         if (!ctx) {
7256                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7257                 return NULL;
7258         }
7259
7260         ret = i915_gem_object_pin(ctx, 4096, true);
7261         if (ret) {
7262                 DRM_ERROR("failed to pin power context: %d\n", ret);
7263                 goto err_unref;
7264         }
7265
7266         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7267         if (ret) {
7268                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7269                 goto err_unpin;
7270         }
7271
7272         return ctx;
7273
7274 err_unpin:
7275         i915_gem_object_unpin(ctx);
7276 err_unref:
7277         drm_gem_object_unreference(&ctx->base);
7278         mutex_unlock(&dev->struct_mutex);
7279         return NULL;
7280 }
7281
7282 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7283 {
7284         struct drm_i915_private *dev_priv = dev->dev_private;
7285         u16 rgvswctl;
7286
7287         rgvswctl = I915_READ16(MEMSWCTL);
7288         if (rgvswctl & MEMCTL_CMD_STS) {
7289                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7290                 return false; /* still busy with another command */
7291         }
7292
7293         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7294                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7295         I915_WRITE16(MEMSWCTL, rgvswctl);
7296         POSTING_READ16(MEMSWCTL);
7297
7298         rgvswctl |= MEMCTL_CMD_STS;
7299         I915_WRITE16(MEMSWCTL, rgvswctl);
7300
7301         return true;
7302 }
7303
7304 void ironlake_enable_drps(struct drm_device *dev)
7305 {
7306         struct drm_i915_private *dev_priv = dev->dev_private;
7307         u32 rgvmodectl = I915_READ(MEMMODECTL);
7308         u8 fmax, fmin, fstart, vstart;
7309
7310         /* Enable temp reporting */
7311         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7312         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7313
7314         /* 100ms RC evaluation intervals */
7315         I915_WRITE(RCUPEI, 100000);
7316         I915_WRITE(RCDNEI, 100000);
7317
7318         /* Set max/min thresholds to 90ms and 80ms respectively */
7319         I915_WRITE(RCBMAXAVG, 90000);
7320         I915_WRITE(RCBMINAVG, 80000);
7321
7322         I915_WRITE(MEMIHYST, 1);
7323
7324         /* Set up min, max, and cur for interrupt handling */
7325         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7326         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7327         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7328                 MEMMODE_FSTART_SHIFT;
7329
7330         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7331                 PXVFREQ_PX_SHIFT;
7332
7333         dev_priv->fmax = fmax; /* IPS callback will increase this */
7334         dev_priv->fstart = fstart;
7335
7336         dev_priv->max_delay = fstart;
7337         dev_priv->min_delay = fmin;
7338         dev_priv->cur_delay = fstart;
7339
7340         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7341                          fmax, fmin, fstart);
7342
7343         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7344
7345         /*
7346          * Interrupts will be enabled in ironlake_irq_postinstall
7347          */
7348
7349         I915_WRITE(VIDSTART, vstart);
7350         POSTING_READ(VIDSTART);
7351
7352         rgvmodectl |= MEMMODE_SWMODE_EN;
7353         I915_WRITE(MEMMODECTL, rgvmodectl);
7354
7355         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7356                 DRM_ERROR("stuck trying to change perf mode\n");
7357         msleep(1);
7358
7359         ironlake_set_drps(dev, fstart);
7360
7361         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7362                 I915_READ(0x112e0);
7363         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7364         dev_priv->last_count2 = I915_READ(0x112f4);
7365         getrawmonotonic(&dev_priv->last_time2);
7366 }
7367
7368 void ironlake_disable_drps(struct drm_device *dev)
7369 {
7370         struct drm_i915_private *dev_priv = dev->dev_private;
7371         u16 rgvswctl = I915_READ16(MEMSWCTL);
7372
7373         /* Ack interrupts, disable EFC interrupt */
7374         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7375         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7376         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7377         I915_WRITE(DEIIR, DE_PCU_EVENT);
7378         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7379
7380         /* Go back to the starting frequency */
7381         ironlake_set_drps(dev, dev_priv->fstart);
7382         msleep(1);
7383         rgvswctl |= MEMCTL_CMD_STS;
7384         I915_WRITE(MEMSWCTL, rgvswctl);
7385         msleep(1);
7386
7387 }
7388
7389 void gen6_set_rps(struct drm_device *dev, u8 val)
7390 {
7391         struct drm_i915_private *dev_priv = dev->dev_private;
7392         u32 swreq;
7393
7394         swreq = (val & 0x3ff) << 25;
7395         I915_WRITE(GEN6_RPNSWREQ, swreq);
7396 }
7397
7398 void gen6_disable_rps(struct drm_device *dev)
7399 {
7400         struct drm_i915_private *dev_priv = dev->dev_private;
7401
7402         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7403         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7404         I915_WRITE(GEN6_PMIER, 0);
7405
7406         spin_lock_irq(&dev_priv->rps_lock);
7407         dev_priv->pm_iir = 0;
7408         spin_unlock_irq(&dev_priv->rps_lock);
7409
7410         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7411 }
7412
7413 static unsigned long intel_pxfreq(u32 vidfreq)
7414 {
7415         unsigned long freq;
7416         int div = (vidfreq & 0x3f0000) >> 16;
7417         int post = (vidfreq & 0x3000) >> 12;
7418         int pre = (vidfreq & 0x7);
7419
7420         if (!pre)
7421                 return 0;
7422
7423         freq = ((div * 133333) / ((1<<post) * pre));
7424
7425         return freq;
7426 }
7427
7428 void intel_init_emon(struct drm_device *dev)
7429 {
7430         struct drm_i915_private *dev_priv = dev->dev_private;
7431         u32 lcfuse;
7432         u8 pxw[16];
7433         int i;
7434
7435         /* Disable to program */
7436         I915_WRITE(ECR, 0);
7437         POSTING_READ(ECR);
7438
7439         /* Program energy weights for various events */
7440         I915_WRITE(SDEW, 0x15040d00);
7441         I915_WRITE(CSIEW0, 0x007f0000);
7442         I915_WRITE(CSIEW1, 0x1e220004);
7443         I915_WRITE(CSIEW2, 0x04000004);
7444
7445         for (i = 0; i < 5; i++)
7446                 I915_WRITE(PEW + (i * 4), 0);
7447         for (i = 0; i < 3; i++)
7448                 I915_WRITE(DEW + (i * 4), 0);
7449
7450         /* Program P-state weights to account for frequency power adjustment */
7451         for (i = 0; i < 16; i++) {
7452                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7453                 unsigned long freq = intel_pxfreq(pxvidfreq);
7454                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7455                         PXVFREQ_PX_SHIFT;
7456                 unsigned long val;
7457
7458                 val = vid * vid;
7459                 val *= (freq / 1000);
7460                 val *= 255;
7461                 val /= (127*127*900);
7462                 if (val > 0xff)
7463                         DRM_ERROR("bad pxval: %ld\n", val);
7464                 pxw[i] = val;
7465         }
7466         /* Render standby states get 0 weight */
7467         pxw[14] = 0;
7468         pxw[15] = 0;
7469
7470         for (i = 0; i < 4; i++) {
7471                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7472                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7473                 I915_WRITE(PXW + (i * 4), val);
7474         }
7475
7476         /* Adjust magic regs to magic values (more experimental results) */
7477         I915_WRITE(OGW0, 0);
7478         I915_WRITE(OGW1, 0);
7479         I915_WRITE(EG0, 0x00007f00);
7480         I915_WRITE(EG1, 0x0000000e);
7481         I915_WRITE(EG2, 0x000e0000);
7482         I915_WRITE(EG3, 0x68000300);
7483         I915_WRITE(EG4, 0x42000000);
7484         I915_WRITE(EG5, 0x00140031);
7485         I915_WRITE(EG6, 0);
7486         I915_WRITE(EG7, 0);
7487
7488         for (i = 0; i < 8; i++)
7489                 I915_WRITE(PXWL + (i * 4), 0);
7490
7491         /* Enable PMON + select events */
7492         I915_WRITE(ECR, 0x80000019);
7493
7494         lcfuse = I915_READ(LCFUSE02);
7495
7496         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7497 }
7498
7499 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7500 {
7501         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7502         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7503         u32 pcu_mbox, rc6_mask = 0;
7504         int cur_freq, min_freq, max_freq;
7505         int i;
7506
7507         /* Here begins a magic sequence of register writes to enable
7508          * auto-downclocking.
7509          *
7510          * Perhaps there might be some value in exposing these to
7511          * userspace...
7512          */
7513         I915_WRITE(GEN6_RC_STATE, 0);
7514         mutex_lock(&dev_priv->dev->struct_mutex);
7515         gen6_gt_force_wake_get(dev_priv);
7516
7517         /* disable the counters and set deterministic thresholds */
7518         I915_WRITE(GEN6_RC_CONTROL, 0);
7519
7520         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7521         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7522         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7523         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7524         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7525
7526         for (i = 0; i < I915_NUM_RINGS; i++)
7527                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7528
7529         I915_WRITE(GEN6_RC_SLEEP, 0);
7530         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7531         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7532         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7533         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7534
7535         if (i915_enable_rc6)
7536                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7537                         GEN6_RC_CTL_RC6_ENABLE;
7538
7539         I915_WRITE(GEN6_RC_CONTROL,
7540                    rc6_mask |
7541                    GEN6_RC_CTL_EI_MODE(1) |
7542                    GEN6_RC_CTL_HW_ENABLE);
7543
7544         I915_WRITE(GEN6_RPNSWREQ,
7545                    GEN6_FREQUENCY(10) |
7546                    GEN6_OFFSET(0) |
7547                    GEN6_AGGRESSIVE_TURBO);
7548         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7549                    GEN6_FREQUENCY(12));
7550
7551         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7552         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7553                    18 << 24 |
7554                    6 << 16);
7555         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7556         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7557         I915_WRITE(GEN6_RP_UP_EI, 100000);
7558         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7559         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7560         I915_WRITE(GEN6_RP_CONTROL,
7561                    GEN6_RP_MEDIA_TURBO |
7562                    GEN6_RP_USE_NORMAL_FREQ |
7563                    GEN6_RP_MEDIA_IS_GFX |
7564                    GEN6_RP_ENABLE |
7565                    GEN6_RP_UP_BUSY_AVG |
7566                    GEN6_RP_DOWN_IDLE_CONT);
7567
7568         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7569                      500))
7570                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7571
7572         I915_WRITE(GEN6_PCODE_DATA, 0);
7573         I915_WRITE(GEN6_PCODE_MAILBOX,
7574                    GEN6_PCODE_READY |
7575                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7576         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7577                      500))
7578                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7579
7580         min_freq = (rp_state_cap & 0xff0000) >> 16;
7581         max_freq = rp_state_cap & 0xff;
7582         cur_freq = (gt_perf_status & 0xff00) >> 8;
7583
7584         /* Check for overclock support */
7585         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7586                      500))
7587                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7588         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7589         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7590         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7591                      500))
7592                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7593         if (pcu_mbox & (1<<31)) { /* OC supported */
7594                 max_freq = pcu_mbox & 0xff;
7595                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7596         }
7597
7598         /* In units of 100MHz */
7599         dev_priv->max_delay = max_freq;
7600         dev_priv->min_delay = min_freq;
7601         dev_priv->cur_delay = cur_freq;
7602
7603         /* requires MSI enabled */
7604         I915_WRITE(GEN6_PMIER,
7605                    GEN6_PM_MBOX_EVENT |
7606                    GEN6_PM_THERMAL_EVENT |
7607                    GEN6_PM_RP_DOWN_TIMEOUT |
7608                    GEN6_PM_RP_UP_THRESHOLD |
7609                    GEN6_PM_RP_DOWN_THRESHOLD |
7610                    GEN6_PM_RP_UP_EI_EXPIRED |
7611                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7612         spin_lock_irq(&dev_priv->rps_lock);
7613         WARN_ON(dev_priv->pm_iir != 0);
7614         I915_WRITE(GEN6_PMIMR, 0);
7615         spin_unlock_irq(&dev_priv->rps_lock);
7616         /* enable all PM interrupts */
7617         I915_WRITE(GEN6_PMINTRMSK, 0);
7618
7619         gen6_gt_force_wake_put(dev_priv);
7620         mutex_unlock(&dev_priv->dev->struct_mutex);
7621 }
7622
7623 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7624 {
7625         int min_freq = 15;
7626         int gpu_freq, ia_freq, max_ia_freq;
7627         int scaling_factor = 180;
7628
7629         max_ia_freq = cpufreq_quick_get_max(0);
7630         /*
7631          * Default to measured freq if none found, PCU will ensure we don't go
7632          * over
7633          */
7634         if (!max_ia_freq)
7635                 max_ia_freq = tsc_khz;
7636
7637         /* Convert from kHz to MHz */
7638         max_ia_freq /= 1000;
7639
7640         mutex_lock(&dev_priv->dev->struct_mutex);
7641
7642         /*
7643          * For each potential GPU frequency, load a ring frequency we'd like
7644          * to use for memory access.  We do this by specifying the IA frequency
7645          * the PCU should use as a reference to determine the ring frequency.
7646          */
7647         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7648              gpu_freq--) {
7649                 int diff = dev_priv->max_delay - gpu_freq;
7650
7651                 /*
7652                  * For GPU frequencies less than 750MHz, just use the lowest
7653                  * ring freq.
7654                  */
7655                 if (gpu_freq < min_freq)
7656                         ia_freq = 800;
7657                 else
7658                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7659                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7660
7661                 I915_WRITE(GEN6_PCODE_DATA,
7662                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7663                            gpu_freq);
7664                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7665                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7666                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7667                               GEN6_PCODE_READY) == 0, 10)) {
7668                         DRM_ERROR("pcode write of freq table timed out\n");
7669                         continue;
7670                 }
7671         }
7672
7673         mutex_unlock(&dev_priv->dev->struct_mutex);
7674 }
7675
7676 static void ironlake_init_clock_gating(struct drm_device *dev)
7677 {
7678         struct drm_i915_private *dev_priv = dev->dev_private;
7679         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7680
7681         /* Required for FBC */
7682         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7683                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7684                 DPFDUNIT_CLOCK_GATE_DISABLE;
7685         /* Required for CxSR */
7686         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7687
7688         I915_WRITE(PCH_3DCGDIS0,
7689                    MARIUNIT_CLOCK_GATE_DISABLE |
7690                    SVSMUNIT_CLOCK_GATE_DISABLE);
7691         I915_WRITE(PCH_3DCGDIS1,
7692                    VFMUNIT_CLOCK_GATE_DISABLE);
7693
7694         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7695
7696         /*
7697          * According to the spec the following bits should be set in
7698          * order to enable memory self-refresh
7699          * The bit 22/21 of 0x42004
7700          * The bit 5 of 0x42020
7701          * The bit 15 of 0x45000
7702          */
7703         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7704                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7705                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7706         I915_WRITE(ILK_DSPCLK_GATE,
7707                    (I915_READ(ILK_DSPCLK_GATE) |
7708                     ILK_DPARB_CLK_GATE));
7709         I915_WRITE(DISP_ARB_CTL,
7710                    (I915_READ(DISP_ARB_CTL) |
7711                     DISP_FBC_WM_DIS));
7712         I915_WRITE(WM3_LP_ILK, 0);
7713         I915_WRITE(WM2_LP_ILK, 0);
7714         I915_WRITE(WM1_LP_ILK, 0);
7715
7716         /*
7717          * Based on the document from hardware guys the following bits
7718          * should be set unconditionally in order to enable FBC.
7719          * The bit 22 of 0x42000
7720          * The bit 22 of 0x42004
7721          * The bit 7,8,9 of 0x42020.
7722          */
7723         if (IS_IRONLAKE_M(dev)) {
7724                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7725                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7726                            ILK_FBCQ_DIS);
7727                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7728                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7729                            ILK_DPARB_GATE);
7730                 I915_WRITE(ILK_DSPCLK_GATE,
7731                            I915_READ(ILK_DSPCLK_GATE) |
7732                            ILK_DPFC_DIS1 |
7733                            ILK_DPFC_DIS2 |
7734                            ILK_CLK_FBC);
7735         }
7736
7737         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7738                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7739                    ILK_ELPIN_409_SELECT);
7740         I915_WRITE(_3D_CHICKEN2,
7741                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7742                    _3D_CHICKEN2_WM_READ_PIPELINED);
7743 }
7744
7745 static void gen6_init_clock_gating(struct drm_device *dev)
7746 {
7747         struct drm_i915_private *dev_priv = dev->dev_private;
7748         int pipe;
7749         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7750
7751         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7752
7753         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7754                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7755                    ILK_ELPIN_409_SELECT);
7756
7757         I915_WRITE(WM3_LP_ILK, 0);
7758         I915_WRITE(WM2_LP_ILK, 0);
7759         I915_WRITE(WM1_LP_ILK, 0);
7760
7761         /*
7762          * According to the spec the following bits should be
7763          * set in order to enable memory self-refresh and fbc:
7764          * The bit21 and bit22 of 0x42000
7765          * The bit21 and bit22 of 0x42004
7766          * The bit5 and bit7 of 0x42020
7767          * The bit14 of 0x70180
7768          * The bit14 of 0x71180
7769          */
7770         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7771                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7772                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7773         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7774                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7775                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7776         I915_WRITE(ILK_DSPCLK_GATE,
7777                    I915_READ(ILK_DSPCLK_GATE) |
7778                    ILK_DPARB_CLK_GATE  |
7779                    ILK_DPFD_CLK_GATE);
7780
7781         for_each_pipe(pipe) {
7782                 I915_WRITE(DSPCNTR(pipe),
7783                            I915_READ(DSPCNTR(pipe)) |
7784                            DISPPLANE_TRICKLE_FEED_DISABLE);
7785                 intel_flush_display_plane(dev_priv, pipe);
7786         }
7787 }
7788
7789 static void ivybridge_init_clock_gating(struct drm_device *dev)
7790 {
7791         struct drm_i915_private *dev_priv = dev->dev_private;
7792         int pipe;
7793         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7794
7795         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7796
7797         I915_WRITE(WM3_LP_ILK, 0);
7798         I915_WRITE(WM2_LP_ILK, 0);
7799         I915_WRITE(WM1_LP_ILK, 0);
7800
7801         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7802
7803         for_each_pipe(pipe) {
7804                 I915_WRITE(DSPCNTR(pipe),
7805                            I915_READ(DSPCNTR(pipe)) |
7806                            DISPPLANE_TRICKLE_FEED_DISABLE);
7807                 intel_flush_display_plane(dev_priv, pipe);
7808         }
7809 }
7810
7811 static void g4x_init_clock_gating(struct drm_device *dev)
7812 {
7813         struct drm_i915_private *dev_priv = dev->dev_private;
7814         uint32_t dspclk_gate;
7815
7816         I915_WRITE(RENCLK_GATE_D1, 0);
7817         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7818                    GS_UNIT_CLOCK_GATE_DISABLE |
7819                    CL_UNIT_CLOCK_GATE_DISABLE);
7820         I915_WRITE(RAMCLK_GATE_D, 0);
7821         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7822                 OVRUNIT_CLOCK_GATE_DISABLE |
7823                 OVCUNIT_CLOCK_GATE_DISABLE;
7824         if (IS_GM45(dev))
7825                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7826         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7827 }
7828
7829 static void crestline_init_clock_gating(struct drm_device *dev)
7830 {
7831         struct drm_i915_private *dev_priv = dev->dev_private;
7832
7833         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7834         I915_WRITE(RENCLK_GATE_D2, 0);
7835         I915_WRITE(DSPCLK_GATE_D, 0);
7836         I915_WRITE(RAMCLK_GATE_D, 0);
7837         I915_WRITE16(DEUC, 0);
7838 }
7839
7840 static void broadwater_init_clock_gating(struct drm_device *dev)
7841 {
7842         struct drm_i915_private *dev_priv = dev->dev_private;
7843
7844         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7845                    I965_RCC_CLOCK_GATE_DISABLE |
7846                    I965_RCPB_CLOCK_GATE_DISABLE |
7847                    I965_ISC_CLOCK_GATE_DISABLE |
7848                    I965_FBC_CLOCK_GATE_DISABLE);
7849         I915_WRITE(RENCLK_GATE_D2, 0);
7850 }
7851
7852 static void gen3_init_clock_gating(struct drm_device *dev)
7853 {
7854         struct drm_i915_private *dev_priv = dev->dev_private;
7855         u32 dstate = I915_READ(D_STATE);
7856
7857         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7858                 DSTATE_DOT_CLOCK_GATING;
7859         I915_WRITE(D_STATE, dstate);
7860 }
7861
7862 static void i85x_init_clock_gating(struct drm_device *dev)
7863 {
7864         struct drm_i915_private *dev_priv = dev->dev_private;
7865
7866         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7867 }
7868
7869 static void i830_init_clock_gating(struct drm_device *dev)
7870 {
7871         struct drm_i915_private *dev_priv = dev->dev_private;
7872
7873         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7874 }
7875
7876 static void ibx_init_clock_gating(struct drm_device *dev)
7877 {
7878         struct drm_i915_private *dev_priv = dev->dev_private;
7879
7880         /*
7881          * On Ibex Peak and Cougar Point, we need to disable clock
7882          * gating for the panel power sequencer or it will fail to
7883          * start up when no ports are active.
7884          */
7885         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7886 }
7887
7888 static void cpt_init_clock_gating(struct drm_device *dev)
7889 {
7890         struct drm_i915_private *dev_priv = dev->dev_private;
7891         int pipe;
7892
7893         /*
7894          * On Ibex Peak and Cougar Point, we need to disable clock
7895          * gating for the panel power sequencer or it will fail to
7896          * start up when no ports are active.
7897          */
7898         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7899         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7900                    DPLS_EDP_PPS_FIX_DIS);
7901         /* Without this, mode sets may fail silently on FDI */
7902         for_each_pipe(pipe)
7903                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
7904 }
7905
7906 static void ironlake_teardown_rc6(struct drm_device *dev)
7907 {
7908         struct drm_i915_private *dev_priv = dev->dev_private;
7909
7910         if (dev_priv->renderctx) {
7911                 i915_gem_object_unpin(dev_priv->renderctx);
7912                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7913                 dev_priv->renderctx = NULL;
7914         }
7915
7916         if (dev_priv->pwrctx) {
7917                 i915_gem_object_unpin(dev_priv->pwrctx);
7918                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7919                 dev_priv->pwrctx = NULL;
7920         }
7921 }
7922
7923 static void ironlake_disable_rc6(struct drm_device *dev)
7924 {
7925         struct drm_i915_private *dev_priv = dev->dev_private;
7926
7927         if (I915_READ(PWRCTXA)) {
7928                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7929                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7930                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7931                          50);
7932
7933                 I915_WRITE(PWRCTXA, 0);
7934                 POSTING_READ(PWRCTXA);
7935
7936                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7937                 POSTING_READ(RSTDBYCTL);
7938         }
7939
7940         ironlake_teardown_rc6(dev);
7941 }
7942
7943 static int ironlake_setup_rc6(struct drm_device *dev)
7944 {
7945         struct drm_i915_private *dev_priv = dev->dev_private;
7946
7947         if (dev_priv->renderctx == NULL)
7948                 dev_priv->renderctx = intel_alloc_context_page(dev);
7949         if (!dev_priv->renderctx)
7950                 return -ENOMEM;
7951
7952         if (dev_priv->pwrctx == NULL)
7953                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7954         if (!dev_priv->pwrctx) {
7955                 ironlake_teardown_rc6(dev);
7956                 return -ENOMEM;
7957         }
7958
7959         return 0;
7960 }
7961
7962 void ironlake_enable_rc6(struct drm_device *dev)
7963 {
7964         struct drm_i915_private *dev_priv = dev->dev_private;
7965         int ret;
7966
7967         /* rc6 disabled by default due to repeated reports of hanging during
7968          * boot and resume.
7969          */
7970         if (!i915_enable_rc6)
7971                 return;
7972
7973         mutex_lock(&dev->struct_mutex);
7974         ret = ironlake_setup_rc6(dev);
7975         if (ret) {
7976                 mutex_unlock(&dev->struct_mutex);
7977                 return;
7978         }
7979
7980         /*
7981          * GPU can automatically power down the render unit if given a page
7982          * to save state.
7983          */
7984         ret = BEGIN_LP_RING(6);
7985         if (ret) {
7986                 ironlake_teardown_rc6(dev);
7987                 mutex_unlock(&dev->struct_mutex);
7988                 return;
7989         }
7990
7991         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7992         OUT_RING(MI_SET_CONTEXT);
7993         OUT_RING(dev_priv->renderctx->gtt_offset |
7994                  MI_MM_SPACE_GTT |
7995                  MI_SAVE_EXT_STATE_EN |
7996                  MI_RESTORE_EXT_STATE_EN |
7997                  MI_RESTORE_INHIBIT);
7998         OUT_RING(MI_SUSPEND_FLUSH);
7999         OUT_RING(MI_NOOP);
8000         OUT_RING(MI_FLUSH);
8001         ADVANCE_LP_RING();
8002
8003         /*
8004          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8005          * does an implicit flush, combined with MI_FLUSH above, it should be
8006          * safe to assume that renderctx is valid
8007          */
8008         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8009         if (ret) {
8010                 DRM_ERROR("failed to enable ironlake power power savings\n");
8011                 ironlake_teardown_rc6(dev);
8012                 mutex_unlock(&dev->struct_mutex);
8013                 return;
8014         }
8015
8016         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8017         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8018         mutex_unlock(&dev->struct_mutex);
8019 }
8020
8021 void intel_init_clock_gating(struct drm_device *dev)
8022 {
8023         struct drm_i915_private *dev_priv = dev->dev_private;
8024
8025         dev_priv->display.init_clock_gating(dev);
8026
8027         if (dev_priv->display.init_pch_clock_gating)
8028                 dev_priv->display.init_pch_clock_gating(dev);
8029 }
8030
8031 /* Set up chip specific display functions */
8032 static void intel_init_display(struct drm_device *dev)
8033 {
8034         struct drm_i915_private *dev_priv = dev->dev_private;
8035
8036         /* We always want a DPMS function */
8037         if (HAS_PCH_SPLIT(dev)) {
8038                 dev_priv->display.dpms = ironlake_crtc_dpms;
8039                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8040                 dev_priv->display.update_plane = ironlake_update_plane;
8041         } else {
8042                 dev_priv->display.dpms = i9xx_crtc_dpms;
8043                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8044                 dev_priv->display.update_plane = i9xx_update_plane;
8045         }
8046
8047         if (I915_HAS_FBC(dev)) {
8048                 if (HAS_PCH_SPLIT(dev)) {
8049                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8050                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8051                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8052                 } else if (IS_GM45(dev)) {
8053                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8054                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8055                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8056                 } else if (IS_CRESTLINE(dev)) {
8057                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8058                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8059                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8060                 }
8061                 /* 855GM needs testing */
8062         }
8063
8064         /* Returns the core display clock speed */
8065         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
8066                 dev_priv->display.get_display_clock_speed =
8067                         i945_get_display_clock_speed;
8068         else if (IS_I915G(dev))
8069                 dev_priv->display.get_display_clock_speed =
8070                         i915_get_display_clock_speed;
8071         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8072                 dev_priv->display.get_display_clock_speed =
8073                         i9xx_misc_get_display_clock_speed;
8074         else if (IS_I915GM(dev))
8075                 dev_priv->display.get_display_clock_speed =
8076                         i915gm_get_display_clock_speed;
8077         else if (IS_I865G(dev))
8078                 dev_priv->display.get_display_clock_speed =
8079                         i865_get_display_clock_speed;
8080         else if (IS_I85X(dev))
8081                 dev_priv->display.get_display_clock_speed =
8082                         i855_get_display_clock_speed;
8083         else /* 852, 830 */
8084                 dev_priv->display.get_display_clock_speed =
8085                         i830_get_display_clock_speed;
8086
8087         /* For FIFO watermark updates */
8088         if (HAS_PCH_SPLIT(dev)) {
8089                 if (HAS_PCH_IBX(dev))
8090                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8091                 else if (HAS_PCH_CPT(dev))
8092                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8093
8094                 if (IS_GEN5(dev)) {
8095                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8096                                 dev_priv->display.update_wm = ironlake_update_wm;
8097                         else {
8098                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8099                                               "Disable CxSR\n");
8100                                 dev_priv->display.update_wm = NULL;
8101                         }
8102                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8103                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8104                 } else if (IS_GEN6(dev)) {
8105                         if (SNB_READ_WM0_LATENCY()) {
8106                                 dev_priv->display.update_wm = sandybridge_update_wm;
8107                         } else {
8108                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8109                                               "Disable CxSR\n");
8110                                 dev_priv->display.update_wm = NULL;
8111                         }
8112                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8113                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8114                 } else if (IS_IVYBRIDGE(dev)) {
8115                         /* FIXME: detect B0+ stepping and use auto training */
8116                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8117                         if (SNB_READ_WM0_LATENCY()) {
8118                                 dev_priv->display.update_wm = sandybridge_update_wm;
8119                         } else {
8120                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8121                                               "Disable CxSR\n");
8122                                 dev_priv->display.update_wm = NULL;
8123                         }
8124                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8125
8126                 } else
8127                         dev_priv->display.update_wm = NULL;
8128         } else if (IS_PINEVIEW(dev)) {
8129                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8130                                             dev_priv->is_ddr3,
8131                                             dev_priv->fsb_freq,
8132                                             dev_priv->mem_freq)) {
8133                         DRM_INFO("failed to find known CxSR latency "
8134                                  "(found ddr%s fsb freq %d, mem freq %d), "
8135                                  "disabling CxSR\n",
8136                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
8137                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8138                         /* Disable CxSR and never update its watermark again */
8139                         pineview_disable_cxsr(dev);
8140                         dev_priv->display.update_wm = NULL;
8141                 } else
8142                         dev_priv->display.update_wm = pineview_update_wm;
8143                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8144         } else if (IS_G4X(dev)) {
8145                 dev_priv->display.update_wm = g4x_update_wm;
8146                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8147         } else if (IS_GEN4(dev)) {
8148                 dev_priv->display.update_wm = i965_update_wm;
8149                 if (IS_CRESTLINE(dev))
8150                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8151                 else if (IS_BROADWATER(dev))
8152                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8153         } else if (IS_GEN3(dev)) {
8154                 dev_priv->display.update_wm = i9xx_update_wm;
8155                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8156                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8157         } else if (IS_I865G(dev)) {
8158                 dev_priv->display.update_wm = i830_update_wm;
8159                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8160                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8161         } else if (IS_I85X(dev)) {
8162                 dev_priv->display.update_wm = i9xx_update_wm;
8163                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8164                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8165         } else {
8166                 dev_priv->display.update_wm = i830_update_wm;
8167                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8168                 if (IS_845G(dev))
8169                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8170                 else
8171                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8172         }
8173
8174         /* Default just returns -ENODEV to indicate unsupported */
8175         dev_priv->display.queue_flip = intel_default_queue_flip;
8176
8177         switch (INTEL_INFO(dev)->gen) {
8178         case 2:
8179                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8180                 break;
8181
8182         case 3:
8183                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8184                 break;
8185
8186         case 4:
8187         case 5:
8188                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8189                 break;
8190
8191         case 6:
8192                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8193                 break;
8194         case 7:
8195                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8196                 break;
8197         }
8198 }
8199
8200 /*
8201  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8202  * resume, or other times.  This quirk makes sure that's the case for
8203  * affected systems.
8204  */
8205 static void quirk_pipea_force (struct drm_device *dev)
8206 {
8207         struct drm_i915_private *dev_priv = dev->dev_private;
8208
8209         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8210         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8211 }
8212
8213 /*
8214  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8215  */
8216 static void quirk_ssc_force_disable(struct drm_device *dev)
8217 {
8218         struct drm_i915_private *dev_priv = dev->dev_private;
8219         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8220 }
8221
8222 struct intel_quirk {
8223         int device;
8224         int subsystem_vendor;
8225         int subsystem_device;
8226         void (*hook)(struct drm_device *dev);
8227 };
8228
8229 struct intel_quirk intel_quirks[] = {
8230         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8231         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8232         /* HP Mini needs pipe A force quirk (LP: #322104) */
8233         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8234
8235         /* Thinkpad R31 needs pipe A force quirk */
8236         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8237         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8238         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8239
8240         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8241         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8242         /* ThinkPad X40 needs pipe A force quirk */
8243
8244         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8245         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8246
8247         /* 855 & before need to leave pipe A & dpll A up */
8248         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8249         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8250
8251         /* Lenovo U160 cannot use SSC on LVDS */
8252         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8253
8254         /* Sony Vaio Y cannot use SSC on LVDS */
8255         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8256 };
8257
8258 static void intel_init_quirks(struct drm_device *dev)
8259 {
8260         struct pci_dev *d = dev->pdev;
8261         int i;
8262
8263         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8264                 struct intel_quirk *q = &intel_quirks[i];
8265
8266                 if (d->device == q->device &&
8267                     (d->subsystem_vendor == q->subsystem_vendor ||
8268                      q->subsystem_vendor == PCI_ANY_ID) &&
8269                     (d->subsystem_device == q->subsystem_device ||
8270                      q->subsystem_device == PCI_ANY_ID))
8271                         q->hook(dev);
8272         }
8273 }
8274
8275 /* Disable the VGA plane that we never use */
8276 static void i915_disable_vga(struct drm_device *dev)
8277 {
8278         struct drm_i915_private *dev_priv = dev->dev_private;
8279         u8 sr1;
8280         u32 vga_reg;
8281
8282         if (HAS_PCH_SPLIT(dev))
8283                 vga_reg = CPU_VGACNTRL;
8284         else
8285                 vga_reg = VGACNTRL;
8286
8287         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8288         outb(1, VGA_SR_INDEX);
8289         sr1 = inb(VGA_SR_DATA);
8290         outb(sr1 | 1<<5, VGA_SR_DATA);
8291         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8292         udelay(300);
8293
8294         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8295         POSTING_READ(vga_reg);
8296 }
8297
8298 void intel_modeset_init(struct drm_device *dev)
8299 {
8300         struct drm_i915_private *dev_priv = dev->dev_private;
8301         int i;
8302
8303         drm_mode_config_init(dev);
8304
8305         dev->mode_config.min_width = 0;
8306         dev->mode_config.min_height = 0;
8307
8308         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8309
8310         intel_init_quirks(dev);
8311
8312         intel_init_display(dev);
8313
8314         if (IS_GEN2(dev)) {
8315                 dev->mode_config.max_width = 2048;
8316                 dev->mode_config.max_height = 2048;
8317         } else if (IS_GEN3(dev)) {
8318                 dev->mode_config.max_width = 4096;
8319                 dev->mode_config.max_height = 4096;
8320         } else {
8321                 dev->mode_config.max_width = 8192;
8322                 dev->mode_config.max_height = 8192;
8323         }
8324         dev->mode_config.fb_base = dev->agp->base;
8325
8326         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8327                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8328
8329         for (i = 0; i < dev_priv->num_pipe; i++) {
8330                 intel_crtc_init(dev, i);
8331         }
8332
8333         /* Just disable it once at startup */
8334         i915_disable_vga(dev);
8335         intel_setup_outputs(dev);
8336
8337         intel_init_clock_gating(dev);
8338
8339         if (IS_IRONLAKE_M(dev)) {
8340                 ironlake_enable_drps(dev);
8341                 intel_init_emon(dev);
8342         }
8343
8344         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8345                 gen6_enable_rps(dev_priv);
8346                 gen6_update_ring_freq(dev_priv);
8347         }
8348
8349         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8350         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8351                     (unsigned long)dev);
8352 }
8353
8354 void intel_modeset_gem_init(struct drm_device *dev)
8355 {
8356         if (IS_IRONLAKE_M(dev))
8357                 ironlake_enable_rc6(dev);
8358
8359         intel_setup_overlay(dev);
8360 }
8361
8362 void intel_modeset_cleanup(struct drm_device *dev)
8363 {
8364         struct drm_i915_private *dev_priv = dev->dev_private;
8365         struct drm_crtc *crtc;
8366         struct intel_crtc *intel_crtc;
8367
8368         drm_kms_helper_poll_fini(dev);
8369         mutex_lock(&dev->struct_mutex);
8370
8371         intel_unregister_dsm_handler();
8372
8373
8374         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8375                 /* Skip inactive CRTCs */
8376                 if (!crtc->fb)
8377                         continue;
8378
8379                 intel_crtc = to_intel_crtc(crtc);
8380                 intel_increase_pllclock(crtc);
8381         }
8382
8383         intel_disable_fbc(dev);
8384
8385         if (IS_IRONLAKE_M(dev))
8386                 ironlake_disable_drps(dev);
8387         if (IS_GEN6(dev) || IS_GEN7(dev))
8388                 gen6_disable_rps(dev);
8389
8390         if (IS_IRONLAKE_M(dev))
8391                 ironlake_disable_rc6(dev);
8392
8393         mutex_unlock(&dev->struct_mutex);
8394
8395         /* Disable the irq before mode object teardown, for the irq might
8396          * enqueue unpin/hotplug work. */
8397         drm_irq_uninstall(dev);
8398         cancel_work_sync(&dev_priv->hotplug_work);
8399
8400         /* flush any delayed tasks or pending work */
8401         flush_scheduled_work();
8402
8403         /* Shut off idle work before the crtcs get freed. */
8404         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8405                 intel_crtc = to_intel_crtc(crtc);
8406                 del_timer_sync(&intel_crtc->idle_timer);
8407         }
8408         del_timer_sync(&dev_priv->idle_timer);
8409         cancel_work_sync(&dev_priv->idle_work);
8410
8411         drm_mode_config_cleanup(dev);
8412 }
8413
8414 /*
8415  * Return which encoder is currently attached for connector.
8416  */
8417 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8418 {
8419         return &intel_attached_encoder(connector)->base;
8420 }
8421
8422 void intel_connector_attach_encoder(struct intel_connector *connector,
8423                                     struct intel_encoder *encoder)
8424 {
8425         connector->encoder = encoder;
8426         drm_mode_connector_attach_encoder(&connector->base,
8427                                           &encoder->base);
8428 }
8429
8430 /*
8431  * set vga decode state - true == enable VGA decode
8432  */
8433 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8434 {
8435         struct drm_i915_private *dev_priv = dev->dev_private;
8436         u16 gmch_ctrl;
8437
8438         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8439         if (state)
8440                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8441         else
8442                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8443         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8444         return 0;
8445 }
8446
8447 #ifdef CONFIG_DEBUG_FS
8448 #include <linux/seq_file.h>
8449
8450 struct intel_display_error_state {
8451         struct intel_cursor_error_state {
8452                 u32 control;
8453                 u32 position;
8454                 u32 base;
8455                 u32 size;
8456         } cursor[2];
8457
8458         struct intel_pipe_error_state {
8459                 u32 conf;
8460                 u32 source;
8461
8462                 u32 htotal;
8463                 u32 hblank;
8464                 u32 hsync;
8465                 u32 vtotal;
8466                 u32 vblank;
8467                 u32 vsync;
8468         } pipe[2];
8469
8470         struct intel_plane_error_state {
8471                 u32 control;
8472                 u32 stride;
8473                 u32 size;
8474                 u32 pos;
8475                 u32 addr;
8476                 u32 surface;
8477                 u32 tile_offset;
8478         } plane[2];
8479 };
8480
8481 struct intel_display_error_state *
8482 intel_display_capture_error_state(struct drm_device *dev)
8483 {
8484         drm_i915_private_t *dev_priv = dev->dev_private;
8485         struct intel_display_error_state *error;
8486         int i;
8487
8488         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8489         if (error == NULL)
8490                 return NULL;
8491
8492         for (i = 0; i < 2; i++) {
8493                 error->cursor[i].control = I915_READ(CURCNTR(i));
8494                 error->cursor[i].position = I915_READ(CURPOS(i));
8495                 error->cursor[i].base = I915_READ(CURBASE(i));
8496
8497                 error->plane[i].control = I915_READ(DSPCNTR(i));
8498                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8499                 error->plane[i].size = I915_READ(DSPSIZE(i));
8500                 error->plane[i].pos= I915_READ(DSPPOS(i));
8501                 error->plane[i].addr = I915_READ(DSPADDR(i));
8502                 if (INTEL_INFO(dev)->gen >= 4) {
8503                         error->plane[i].surface = I915_READ(DSPSURF(i));
8504                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8505                 }
8506
8507                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8508                 error->pipe[i].source = I915_READ(PIPESRC(i));
8509                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8510                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8511                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8512                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8513                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8514                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8515         }
8516
8517         return error;
8518 }
8519
8520 void
8521 intel_display_print_error_state(struct seq_file *m,
8522                                 struct drm_device *dev,
8523                                 struct intel_display_error_state *error)
8524 {
8525         int i;
8526
8527         for (i = 0; i < 2; i++) {
8528                 seq_printf(m, "Pipe [%d]:\n", i);
8529                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8530                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8531                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8532                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8533                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8534                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8535                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8536                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8537
8538                 seq_printf(m, "Plane [%d]:\n", i);
8539                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8540                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8541                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8542                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8543                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8544                 if (INTEL_INFO(dev)->gen >= 4) {
8545                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8546                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8547                 }
8548
8549                 seq_printf(m, "Cursor [%d]:\n", i);
8550                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8551                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8552                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8553         }
8554 }
8555 #endif