drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_dmabuf.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct drm_device *dev,
 101                                   struct intel_framebuffer *ifb,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd,
 103                                   struct drm_i915_gem_object *obj);
 104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 108                                          struct intel_link_m_n *m_n,
 109                                          struct intel_link_m_n *m2_n2);
 110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 113 static void vlv_prepare_pll(struct intel_crtc *crtc,
 114                             const struct intel_crtc_state *pipe_config);
 115 static void chv_prepare_pll(struct intel_crtc *crtc,
 116                             const struct intel_crtc_state *pipe_config);
 117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 120         struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_device *dev,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 617             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 622                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 623                         INTELPllInvalid("p out of range\n");
 624                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 625                         INTELPllInvalid("m out of range\n");
 626         }
 627
 628         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 629                 INTELPllInvalid("vco out of range\n");
 630         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 631          * connector, etc., rather than just a single range.
 632          */
 633         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 634                 INTELPllInvalid("dot out of range\n");
 635
 636         return true;
 637 }
 638
 639 static int
 640 i9xx_select_p2_div(const struct intel_limit *limit,
 641                    const struct intel_crtc_state *crtc_state,
 642                    int target)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645
 646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 647                 /*
 648                  * For LVDS just rely on its current settings for dual-channel.
 649                  * We haven't figured out how to reliably set up different
 650                  * single/dual channel state, if we even can.
 651                  */
 652                 if (intel_is_dual_link_lvds(dev))
 653                         return limit->p2.p2_fast;
 654                 else
 655                         return limit->p2.p2_slow;
 656         } else {
 657                 if (target < limit->p2.dot_limit)
 658                         return limit->p2.p2_slow;
 659                 else
 660                         return limit->p2.p2_fast;
 661         }
 662 }
 663
 664 /*
 665  * Returns a set of divisors for the desired target clock with the given
 666  * refclk, or FALSE.  The returned values represent the clock equation:
 667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 668  *
 669  * Target and reference clocks are specified in kHz.
 670  *
 671  * If match_clock is provided, then best_clock P divider must match the P
 672  * divider from @match_clock used for LVDS downclocking.
 673  */
 674 static bool
 675 i9xx_find_best_dpll(const struct intel_limit *limit,
 676                     struct intel_crtc_state *crtc_state,
 677                     int target, int refclk, struct dpll *match_clock,
 678                     struct dpll *best_clock)
 679 {
 680         struct drm_device *dev = crtc_state->base.crtc->dev;
 681         struct dpll clock;
 682         int err = target;
 683
 684         memset(best_clock, 0, sizeof(*best_clock));
 685
 686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 687
 688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 689              clock.m1++) {
 690                 for (clock.m2 = limit->m2.min;
 691                      clock.m2 <= limit->m2.max; clock.m2++) {
 692                         if (clock.m2 >= clock.m1)
 693                                 break;
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         i9xx_calc_dpll_params(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 /*
 722  * Returns a set of divisors for the desired target clock with the given
 723  * refclk, or FALSE.  The returned values represent the clock equation:
 724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 725  *
 726  * Target and reference clocks are specified in kHz.
 727  *
 728  * If match_clock is provided, then best_clock P divider must match the P
 729  * divider from @match_clock used for LVDS downclocking.
 730  */
 731 static bool
 732 pnv_find_best_dpll(const struct intel_limit *limit,
 733                    struct intel_crtc_state *crtc_state,
 734                    int target, int refclk, struct dpll *match_clock,
 735                    struct dpll *best_clock)
 736 {
 737         struct drm_device *dev = crtc_state->base.crtc->dev;
 738         struct dpll clock;
 739         int err = target;
 740
 741         memset(best_clock, 0, sizeof(*best_clock));
 742
 743         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 744
 745         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 746              clock.m1++) {
 747                 for (clock.m2 = limit->m2.min;
 748                      clock.m2 <= limit->m2.max; clock.m2++) {
 749                         for (clock.n = limit->n.min;
 750                              clock.n <= limit->n.max; clock.n++) {
 751                                 for (clock.p1 = limit->p1.min;
 752                                         clock.p1 <= limit->p1.max; clock.p1++) {
 753                                         int this_err;
 754
 755                                         pnv_calc_dpll_params(refclk, &clock);
 756                                         if (!intel_PLL_is_valid(dev, limit,
 757                                                                 &clock))
 758                                                 continue;
 759                                         if (match_clock &&
 760                                             clock.p != match_clock->p)
 761                                                 continue;
 762
 763                                         this_err = abs(clock.dot - target);
 764                                         if (this_err < err) {
 765                                                 *best_clock = clock;
 766                                                 err = this_err;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772
 773         return (err != target);
 774 }
 775
 776 /*
 777  * Returns a set of divisors for the desired target clock with the given
 778  * refclk, or FALSE.  The returned values represent the clock equation:
 779  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 780  *
 781  * Target and reference clocks are specified in kHz.
 782  *
 783  * If match_clock is provided, then best_clock P divider must match the P
 784  * divider from @match_clock used for LVDS downclocking.
 785  */
 786 static bool
 787 g4x_find_best_dpll(const struct intel_limit *limit,
 788                    struct intel_crtc_state *crtc_state,
 789                    int target, int refclk, struct dpll *match_clock,
 790                    struct dpll *best_clock)
 791 {
 792         struct drm_device *dev = crtc_state->base.crtc->dev;
 793         struct dpll clock;
 794         int max_n;
 795         bool found = false;
 796         /* approximately equals target * 0.00585 */
 797         int err_most = (target >> 8) + (target >> 9);
 798
 799         memset(best_clock, 0, sizeof(*best_clock));
 800
 801         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 802
 803         max_n = limit->n.max;
 804         /* based on hardware requirement, prefer smaller n to precision */
 805         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 806                 /* based on hardware requirement, prefere larger m1,m2 */
 807                 for (clock.m1 = limit->m1.max;
 808                      clock.m1 >= limit->m1.min; clock.m1--) {
 809                         for (clock.m2 = limit->m2.max;
 810                              clock.m2 >= limit->m2.min; clock.m2--) {
 811                                 for (clock.p1 = limit->p1.max;
 812                                      clock.p1 >= limit->p1.min; clock.p1--) {
 813                                         int this_err;
 814
 815                                         i9xx_calc_dpll_params(refclk, &clock);
 816                                         if (!intel_PLL_is_valid(dev, limit,
 817                                                                 &clock))
 818                                                 continue;
 819
 820                                         this_err = abs(clock.dot - target);
 821                                         if (this_err < err_most) {
 822                                                 *best_clock = clock;
 823                                                 err_most = this_err;
 824                                                 max_n = clock.n;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831         return found;
 832 }
 833
 834 /*
 835  * Check if the calculated PLL configuration is more optimal compared to the
 836  * best configuration and error found so far. Return the calculated error.
 837  */
 838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 839                                const struct dpll *calculated_clock,
 840                                const struct dpll *best_clock,
 841                                unsigned int best_error_ppm,
 842                                unsigned int *error_ppm)
 843 {
 844         /*
 845          * For CHV ignore the error and consider only the P value.
 846          * Prefer a bigger P value based on HW requirements.
 847          */
 848         if (IS_CHERRYVIEW(dev)) {
 849                 *error_ppm = 0;
 850
 851                 return calculated_clock->p > best_clock->p;
 852         }
 853
 854         if (WARN_ON_ONCE(!target_freq))
 855                 return false;
 856
 857         *error_ppm = div_u64(1000000ULL *
 858                                 abs(target_freq - calculated_clock->dot),
 859                              target_freq);
 860         /*
 861          * Prefer a better P value over a better (smaller) error if the error
 862          * is small. Ensure this preference for future configurations too by
 863          * setting the error to 0.
 864          */
 865         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 866                 *error_ppm = 0;
 867
 868                 return true;
 869         }
 870
 871         return *error_ppm + 10 < best_error_ppm;
 872 }
 873
 874 /*
 875  * Returns a set of divisors for the desired target clock with the given
 876  * refclk, or FALSE.  The returned values represent the clock equation:
 877  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 878  */
 879 static bool
 880 vlv_find_best_dpll(const struct intel_limit *limit,
 881                    struct intel_crtc_state *crtc_state,
 882                    int target, int refclk, struct dpll *match_clock,
 883                    struct dpll *best_clock)
 884 {
 885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 886         struct drm_device *dev = crtc->base.dev;
 887         struct dpll clock;
 888         unsigned int bestppm = 1000000;
 889         /* min update 19.2 MHz */
 890         int max_n = min(limit->n.max, refclk / 19200);
 891         bool found = false;
 892
 893         target *= 5; /* fast clock */
 894
 895         memset(best_clock, 0, sizeof(*best_clock));
 896
 897         /* based on hardware requirement, prefer smaller n to precision */
 898         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 899                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 900                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 901                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 902                                 clock.p = clock.p1 * clock.p2;
 903                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 904                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 905                                         unsigned int ppm;
 906
 907                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 908                                                                      refclk * clock.m1);
 909
 910                                         vlv_calc_dpll_params(refclk, &clock);
 911
 912                                         if (!intel_PLL_is_valid(dev, limit,
 913                                                                 &clock))
 914                                                 continue;
 915
 916                                         if (!vlv_PLL_is_optimal(dev, target,
 917                                                                 &clock,
 918                                                                 best_clock,
 919                                                                 bestppm, &ppm))
 920                                                 continue;
 921
 922                                         *best_clock = clock;
 923                                         bestppm = ppm;
 924                                         found = true;
 925                                 }
 926                         }
 927                 }
 928         }
 929
 930         return found;
 931 }
 932
 933 /*
 934  * Returns a set of divisors for the desired target clock with the given
 935  * refclk, or FALSE.  The returned values represent the clock equation:
 936  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 937  */
 938 static bool
 939 chv_find_best_dpll(const struct intel_limit *limit,
 940                    struct intel_crtc_state *crtc_state,
 941                    int target, int refclk, struct dpll *match_clock,
 942                    struct dpll *best_clock)
 943 {
 944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 945         struct drm_device *dev = crtc->base.dev;
 946         unsigned int best_error_ppm;
 947         struct dpll clock;
 948         uint64_t m2;
 949         int found = false;
 950
 951         memset(best_clock, 0, sizeof(*best_clock));
 952         best_error_ppm = 1000000;
 953
 954         /*
 955          * Based on hardware doc, the n always set to 1, and m1 always
 956          * set to 2.  If requires to support 200Mhz refclk, we need to
 957          * revisit this because n may not 1 anymore.
 958          */
 959         clock.n = 1, clock.m1 = 2;
 960         target *= 5;    /* fast clock */
 961
 962         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 963                 for (clock.p2 = limit->p2.p2_fast;
 964                                 clock.p2 >= limit->p2.p2_slow;
 965                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 966                         unsigned int error_ppm;
 967
 968                         clock.p = clock.p1 * clock.p2;
 969
 970                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 971                                         clock.n) << 22, refclk * clock.m1);
 972
 973                         if (m2 > INT_MAX/clock.m1)
 974                                 continue;
 975
 976                         clock.m2 = m2;
 977
 978                         chv_calc_dpll_params(refclk, &clock);
 979
 980                         if (!intel_PLL_is_valid(dev, limit, &clock))
 981                                 continue;
 982
 983                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 984                                                 best_error_ppm, &error_ppm))
 985                                 continue;
 986
 987                         *best_clock = clock;
 988                         best_error_ppm = error_ppm;
 989                         found = true;
 990                 }
 991         }
 992
 993         return found;
 994 }
 995
 996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 997                         struct dpll *best_clock)
 998 {
 999         int refclk = 100000;
1000         const struct intel_limit *limit = &intel_limits_bxt;
1001
1002         return chv_find_best_dpll(limit, crtc_state,
1003                                   target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010         /* Be paranoid as we can arrive here with only partial
1011          * state retrieved from the hardware during setup.
1012          *
1013          * We can ditch the adjusted_mode.crtc_clock check as soon
1014          * as Haswell has gained clock readout/fastboot support.
1015          *
1016          * We can ditch the crtc->primary->fb check as soon as we can
1017          * properly reconstruct framebuffers.
1018          *
1019          * FIXME: The intel_crtc->active here should be switched to
1020          * crtc->state->active once we have proper CRTC states wired up
1021          * for atomic.
1022          */
1023         return intel_crtc->active && crtc->primary->state->fb &&
1024                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe)
1029 {
1030         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033         return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(dev);
1039         i915_reg_t reg = PIPEDSL(pipe);
1040         u32 line1, line2;
1041         u32 line_mask;
1042
1043         if (IS_GEN2(dev))
1044                 line_mask = DSL_LINEMASK_GEN2;
1045         else
1046                 line_mask = DSL_LINEMASK_GEN3;
1047
1048         line1 = I915_READ(reg) & line_mask;
1049         msleep(5);
1050         line2 = I915_READ(reg) & line_mask;
1051
1052         return line1 == line2;
1053 }
1054
1055 /*
1056  * intel_wait_for_pipe_off - wait for pipe to turn off
1057  * @crtc: crtc whose pipe to wait for
1058  *
1059  * After disabling a pipe, we can't wait for vblank in the usual way,
1060  * spinning on the vblank interrupt status bit, since we won't actually
1061  * see an interrupt when the pipe is disabled.
1062  *
1063  * On Gen4 and above:
1064  *   wait for the pipe register state bit to turn off
1065  *
1066  * Otherwise:
1067  *   wait for the display line value to settle (it usually
1068  *   ends up stopping at the start of the next frame).
1069  *
1070  */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->base.dev;
1074         struct drm_i915_private *dev_priv = to_i915(dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                            enum pipe pipe)
1192 {
1193         struct drm_device *dev = &dev_priv->drm;
1194         i915_reg_t pp_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198
1199         if (WARN_ON(HAS_DDI(dev)))
1200                 return;
1201
1202         if (HAS_PCH_SPLIT(dev)) {
1203                 u32 port_sel;
1204
1205                 pp_reg = PP_CONTROL(0);
1206                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210                         panel_pipe = PIPE_B;
1211                 /* XXX: else fix for eDP */
1212         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213                 /* presumably write lock depends on pipe, not port select */
1214                 pp_reg = PP_CONTROL(pipe);
1215                 panel_pipe = pipe;
1216         } else {
1217                 pp_reg = PP_CONTROL(0);
1218                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220         }
1221
1222         val = I915_READ(pp_reg);
1223         if (!(val & PANEL_POWER_ON) ||
1224             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225                 locked = false;
1226
1227         I915_STATE_WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233                           enum pipe pipe, bool state)
1234 {
1235         struct drm_device *dev = &dev_priv->drm;
1236         bool cur_state;
1237
1238         if (IS_845G(dev) || IS_I865G(dev))
1239                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240         else
1241                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243         I915_STATE_WARN(cur_state != state,
1244              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245                         pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251                  enum pipe pipe, bool state)
1252 {
1253         bool cur_state;
1254         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255                                                                       pipe);
1256         enum intel_display_power_domain power_domain;
1257
1258         /* if we need the pipe quirk it must be always on */
1259         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261                 state = true;
1262
1263         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266                 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268                 intel_display_power_put(dev_priv, power_domain);
1269         } else {
1270                 cur_state = false;
1271         }
1272
1273         I915_STATE_WARN(cur_state != state,
1274              "pipe %c assertion failure (expected %s, current %s)\n",
1275                         pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279                          enum plane plane, bool state)
1280 {
1281         u32 val;
1282         bool cur_state;
1283
1284         val = I915_READ(DSPCNTR(plane));
1285         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286         I915_STATE_WARN(cur_state != state,
1287              "plane %c assertion failure (expected %s, current %s)\n",
1288                         plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295                                    enum pipe pipe)
1296 {
1297         struct drm_device *dev = &dev_priv->drm;
1298         int i;
1299
1300         /* Primary planes are fixed to pipes on gen4+ */
1301         if (INTEL_INFO(dev)->gen >= 4) {
1302                 u32 val = I915_READ(DSPCNTR(pipe));
1303                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304                      "plane %c assertion failure, should be disabled but not\n",
1305                      plane_name(pipe));
1306                 return;
1307         }
1308
1309         /* Need to check both planes against the pipe */
1310         for_each_pipe(dev_priv, i) {
1311                 u32 val = I915_READ(DSPCNTR(i));
1312                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313                         DISPPLANE_SEL_PIPE_SHIFT;
1314                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316                      plane_name(i), pipe_name(pipe));
1317         }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321                                     enum pipe pipe)
1322 {
1323         struct drm_device *dev = &dev_priv->drm;
1324         int sprite;
1325
1326         if (INTEL_INFO(dev)->gen >= 9) {
1327                 for_each_sprite(dev_priv, pipe, sprite) {
1328                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331                              sprite, pipe_name(pipe));
1332                 }
1333         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334                 for_each_sprite(dev_priv, pipe, sprite) {
1335                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1336                         I915_STATE_WARN(val & SP_ENABLE,
1337                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338                              sprite_name(pipe, sprite), pipe_name(pipe));
1339                 }
1340         } else if (INTEL_INFO(dev)->gen >= 7) {
1341                 u32 val = I915_READ(SPRCTL(pipe));
1342                 I915_STATE_WARN(val & SPRITE_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         } else if (INTEL_INFO(dev)->gen >= 5) {
1346                 u32 val = I915_READ(DVSCNTR(pipe));
1347                 I915_STATE_WARN(val & DVS_ENABLE,
1348                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349                      plane_name(pipe), pipe_name(pipe));
1350         }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356                 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         u32 val;
1363         bool enabled;
1364
1365         val = I915_READ(PCH_TRANSCONF(pipe));
1366         enabled = !!(val & TRANS_ENABLE);
1367         I915_STATE_WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377
1378         if (HAS_PCH_CPT(dev_priv)) {
1379                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381                         return false;
1382         } else if (IS_CHERRYVIEW(dev_priv)) {
1383                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & SDVO_ENABLE) == 0)
1396                 return false;
1397
1398         if (HAS_PCH_CPT(dev_priv)) {
1399                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400                         return false;
1401         } else if (IS_CHERRYVIEW(dev_priv)) {
1402                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403                         return false;
1404         } else {
1405                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406                         return false;
1407         }
1408         return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412                               enum pipe pipe, u32 val)
1413 {
1414         if ((val & LVDS_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419                         return false;
1420         } else {
1421                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422                         return false;
1423         }
1424         return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428                               enum pipe pipe, u32 val)
1429 {
1430         if ((val & ADPA_DAC_ENABLE) == 0)
1431                 return false;
1432         if (HAS_PCH_CPT(dev_priv)) {
1433                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434                         return false;
1435         } else {
1436                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437                         return false;
1438         }
1439         return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443                                    enum pipe pipe, i915_reg_t reg,
1444                                    u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, i915_reg_t reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         u32 val;
1473
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         val = I915_READ(PCH_ADPA);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         val = I915_READ(PCH_LVDS);
1484         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494                             const struct intel_crtc_state *pipe_config)
1495 {
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         enum pipe pipe = crtc->pipe;
1498
1499         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500         POSTING_READ(DPLL(pipe));
1501         udelay(150);
1502
1503         if (intel_wait_for_register(dev_priv,
1504                                     DPLL(pipe),
1505                                     DPLL_LOCK_VLV,
1506                                     DPLL_LOCK_VLV,
1507                                     1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         enum pipe pipe = crtc->pipe;
1516
1517         assert_pipe_disabled(dev_priv, pipe);
1518
1519         /* PLL is protected by panel, make sure we can write it */
1520         assert_panel_unlocked(dev_priv, pipe);
1521
1522         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523                 _vlv_enable_pll(crtc, pipe_config);
1524
1525         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526         POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531                             const struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534         enum pipe pipe = crtc->pipe;
1535         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536         u32 tmp;
1537
1538         mutex_lock(&dev_priv->sb_lock);
1539
1540         /* Enable back the 10bit clock to display controller */
1541         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542         tmp |= DPIO_DCLKP_EN;
1543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545         mutex_unlock(&dev_priv->sb_lock);
1546
1547         /*
1548          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549          */
1550         udelay(1);
1551
1552         /* Enable PLL */
1553         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555         /* Check PLL is locked */
1556         if (intel_wait_for_register(dev_priv,
1557                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558                                     1))
1559                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563                            const struct intel_crtc_state *pipe_config)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567
1568         assert_pipe_disabled(dev_priv, pipe);
1569
1570         /* PLL is protected by panel, make sure we can write it */
1571         assert_panel_unlocked(dev_priv, pipe);
1572
1573         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574                 _chv_enable_pll(crtc, pipe_config);
1575
1576         if (pipe != PIPE_A) {
1577                 /*
1578                  * WaPixelRepeatModeFixForC0:chv
1579                  *
1580                  * DPLLCMD is AWOL. Use chicken bits to propagate
1581                  * the value from DPLLBMD to either pipe B or C.
1582                  */
1583                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585                 I915_WRITE(CBR4_VLV, 0);
1586                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588                 /*
1589                  * DPLLB VGA mode also seems to cause problems.
1590                  * We should always have it disabled.
1591                  */
1592                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593         } else {
1594                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595                 POSTING_READ(DPLL_MD(pipe));
1596         }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601         struct intel_crtc *crtc;
1602         int count = 0;
1603
1604         for_each_intel_crtc(dev, crtc) {
1605                 count += crtc->base.state->active &&
1606                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607         }
1608
1609         return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->base.dev;
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         i915_reg_t reg = DPLL(crtc->pipe);
1617         u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619         assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         /* Enable DVO 2x clock on both PLLs if necessary */
1626         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627                 /*
1628                  * It appears to be important that we don't enable this
1629                  * for the current pipe before otherwise configuring the
1630                  * PLL. No idea how this should be handled if multiple
1631                  * DVO outputs are enabled simultaneosly.
1632                  */
1633                 dpll |= DPLL_DVO_2X_MODE;
1634                 I915_WRITE(DPLL(!crtc->pipe),
1635                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636         }
1637
1638         /*
1639          * Apparently we need to have VGA mode enabled prior to changing
1640          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641          * dividers, even though the register value does change.
1642          */
1643         I915_WRITE(reg, 0);
1644
1645         I915_WRITE(reg, dpll);
1646
1647         /* Wait for the clocks to stabilize. */
1648         POSTING_READ(reg);
1649         udelay(150);
1650
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 I915_WRITE(DPLL_MD(crtc->pipe),
1653                            crtc->config->dpll_hw_state.dpll_md);
1654         } else {
1655                 /* The pixel multiplier can only be updated once the
1656                  * DPLL is enabled and the clocks are stable.
1657                  *
1658                  * So write it again.
1659                  */
1660                 I915_WRITE(reg, dpll);
1661         }
1662
1663         /* We do this three times for luck */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676  * i9xx_disable_pll - disable a PLL
1677  * @dev_priv: i915 private structure
1678  * @pipe: pipe PLL to disable
1679  *
1680  * Disable the PLL for @pipe, making sure the pipe is off first.
1681  *
1682  * Note!  This is for pre-ILK only.
1683  */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         enum pipe pipe = crtc->pipe;
1689
1690         /* Disable DVO 2x clock on both PLLs if necessary */
1691         if (IS_I830(dev) &&
1692             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693             !intel_num_dvo_pipes(dev)) {
1694                 I915_WRITE(DPLL(PIPE_B),
1695                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696                 I915_WRITE(DPLL(PIPE_A),
1697                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698         }
1699
1700         /* Don't disable pipe or pipe PLLs if needed */
1701         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703                 return;
1704
1705         /* Make sure the pipe isn't still relying on us */
1706         assert_pipe_disabled(dev_priv, pipe);
1707
1708         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709         POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         u32 val;
1715
1716         /* Make sure the pipe isn't still relying on us */
1717         assert_pipe_disabled(dev_priv, pipe);
1718
1719         val = DPLL_INTEGRATED_REF_CLK_VLV |
1720                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721         if (pipe != PIPE_A)
1722                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731         u32 val;
1732
1733         /* Make sure the pipe isn't still relying on us */
1734         assert_pipe_disabled(dev_priv, pipe);
1735
1736         val = DPLL_SSC_REF_CLK_CHV |
1737                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738         if (pipe != PIPE_A)
1739                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741         I915_WRITE(DPLL(pipe), val);
1742         POSTING_READ(DPLL(pipe));
1743
1744         mutex_lock(&dev_priv->sb_lock);
1745
1746         /* Disable 10bit clock to display controller */
1747         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748         val &= ~DPIO_DCLKP_EN;
1749         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751         mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755                          struct intel_digital_port *dport,
1756                          unsigned int expected_mask)
1757 {
1758         u32 port_mask;
1759         i915_reg_t dpll_reg;
1760
1761         switch (dport->port) {
1762         case PORT_B:
1763                 port_mask = DPLL_PORTB_READY_MASK;
1764                 dpll_reg = DPLL(0);
1765                 break;
1766         case PORT_C:
1767                 port_mask = DPLL_PORTC_READY_MASK;
1768                 dpll_reg = DPLL(0);
1769                 expected_mask <<= 4;
1770                 break;
1771         case PORT_D:
1772                 port_mask = DPLL_PORTD_READY_MASK;
1773                 dpll_reg = DPIO_PHY_STATUS;
1774                 break;
1775         default:
1776                 BUG();
1777         }
1778
1779         if (intel_wait_for_register(dev_priv,
1780                                     dpll_reg, port_mask, expected_mask,
1781                                     1000))
1782                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787                                            enum pipe pipe)
1788 {
1789         struct drm_device *dev = &dev_priv->drm;
1790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792         i915_reg_t reg;
1793         uint32_t val, pipeconf_val;
1794
1795         /* Make sure PCH DPLL is enabled */
1796         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798         /* FDI must be feeding us bits for PCH ports */
1799         assert_fdi_tx_enabled(dev_priv, pipe);
1800         assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802         if (HAS_PCH_CPT(dev)) {
1803                 /* Workaround: Set the timing override bit before enabling the
1804                  * pch transcoder. */
1805                 reg = TRANS_CHICKEN2(pipe);
1806                 val = I915_READ(reg);
1807                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808                 I915_WRITE(reg, val);
1809         }
1810
1811         reg = PCH_TRANSCONF(pipe);
1812         val = I915_READ(reg);
1813         pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815         if (HAS_PCH_IBX(dev_priv)) {
1816                 /*
1817                  * Make the BPC in transcoder be consistent with
1818                  * that in pipeconf reg. For HDMI we must use 8bpc
1819                  * here for both 8bpc and 12bpc.
1820                  */
1821                 val &= ~PIPECONF_BPC_MASK;
1822                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823                         val |= PIPECONF_8BPC;
1824                 else
1825                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1826         }
1827
1828         val &= ~TRANS_INTERLACE_MASK;
1829         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830                 if (HAS_PCH_IBX(dev_priv) &&
1831                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832                         val |= TRANS_LEGACY_INTERLACED_ILK;
1833                 else
1834                         val |= TRANS_INTERLACED;
1835         else
1836                 val |= TRANS_PROGRESSIVE;
1837
1838         I915_WRITE(reg, val | TRANS_ENABLE);
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841                                     100))
1842                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846                                       enum transcoder cpu_transcoder)
1847 {
1848         u32 val, pipeconf_val;
1849
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854         /* Workaround: set timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859         val = TRANS_ENABLE;
1860         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863             PIPECONF_INTERLACED_ILK)
1864                 val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(LPT_TRANSCONF, val);
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF,
1871                                     TRANS_STATE_ENABLE,
1872                                     TRANS_STATE_ENABLE,
1873                                     100))
1874                 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878                                             enum pipe pipe)
1879 {
1880         struct drm_device *dev = &dev_priv->drm;
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123         return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134         return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (intel_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185         struct drm_device *dev = fb->dev;
2186         struct drm_i915_private *dev_priv = to_i915(dev);
2187         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188         struct i915_ggtt_view view;
2189         struct i915_vma *vma;
2190         u32 alignment;
2191
2192         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196         intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198         /* Note that the w/a also requires 64 PTE of padding following the
2199          * bo. We currently fill all unused PTE with the shadow page and so
2200          * we should always have valid PTE following the scanout preventing
2201          * the VT-d warning.
2202          */
2203         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204                 alignment = 256 * 1024;
2205
2206         /*
2207          * Global gtt pte registers are special registers which actually forward
2208          * writes to a chunk of system memory. Which means that there is no risk
2209          * that the register values disappear as soon as we call
2210          * intel_runtime_pm_put(), so it is correct to wrap only the
2211          * pin/unpin/fence and not more.
2212          */
2213         intel_runtime_pm_get(dev_priv);
2214
2215         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216         if (IS_ERR(vma))
2217                 goto err;
2218
2219         if (i915_vma_is_map_and_fenceable(vma)) {
2220                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221                  * fence, whereas 965+ only requires a fence if using
2222                  * framebuffer compression.  For simplicity, we always, when
2223                  * possible, install a fence as the cost is not that onerous.
2224                  *
2225                  * If we fail to fence the tiled scanout, then either the
2226                  * modeset will reject the change (which is highly unlikely as
2227                  * the affected systems, all but one, do not have unmappable
2228                  * space) or we will not be able to enable full powersaving
2229                  * techniques (also likely not to apply due to various limits
2230                  * FBC and the like impose on the size of the buffer, which
2231                  * presumably we violated anyway with this unmappable buffer).
2232                  * Anyway, it is presumably better to stumble onwards with
2233                  * something and try to run the system in a "less than optimal"
2234                  * mode that matches the user configuration.
2235                  */
2236                 if (i915_vma_get_fence(vma) == 0)
2237                         i915_vma_pin_fence(vma);
2238         }
2239
2240 err:
2241         intel_runtime_pm_put(dev_priv);
2242         return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         struct i915_ggtt_view view;
2249         struct i915_vma *vma;
2250
2251         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254         vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256         i915_vma_unpin_fence(vma);
2257         i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261                           unsigned int rotation)
2262 {
2263         if (intel_rotation_90_or_270(rotation))
2264                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265         else
2266                 return fb->pitches[plane];
2267 }
2268
2269 /*
2270  * Convert the x/y offsets into a linear offset.
2271  * Only valid with 0/180 degree rotation, which is fine since linear
2272  * offset is only used with linear buffers on pre-hsw and tiled buffers
2273  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274  */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276                           const struct intel_plane_state *state,
2277                           int plane)
2278 {
2279         const struct drm_framebuffer *fb = state->base.fb;
2280         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281         unsigned int pitch = fb->pitches[plane];
2282
2283         return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287  * Add the x/y offsets derived from fb->offsets[] to the user
2288  * specified plane src x/y offsets. The resulting x/y offsets
2289  * specify the start of scanout from the beginning of the gtt mapping.
2290  */
2291 void intel_add_fb_offsets(int *x, int *y,
2292                           const struct intel_plane_state *state,
2293                           int plane)
2294
2295 {
2296         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297         unsigned int rotation = state->base.rotation;
2298
2299         if (intel_rotation_90_or_270(rotation)) {
2300                 *x += intel_fb->rotated[plane].x;
2301                 *y += intel_fb->rotated[plane].y;
2302         } else {
2303                 *x += intel_fb->normal[plane].x;
2304                 *y += intel_fb->normal[plane].y;
2305         }
2306 }
2307
2308 /*
2309  * Input tile dimensions and pitch must already be
2310  * rotated to match x and y, and in pixel units.
2311  */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313                                      unsigned int tile_width,
2314                                      unsigned int tile_height,
2315                                      unsigned int tile_size,
2316                                      unsigned int pitch_tiles,
2317                                      u32 old_offset,
2318                                      u32 new_offset)
2319 {
2320         unsigned int pitch_pixels = pitch_tiles * tile_width;
2321         unsigned int tiles;
2322
2323         WARN_ON(old_offset & (tile_size - 1));
2324         WARN_ON(new_offset & (tile_size - 1));
2325         WARN_ON(new_offset > old_offset);
2326
2327         tiles = (old_offset - new_offset) / tile_size;
2328
2329         *y += tiles / pitch_tiles * tile_height;
2330         *x += tiles % pitch_tiles * tile_width;
2331
2332         /* minimize x in case it got needlessly big */
2333         *y += *x / pitch_pixels * tile_height;
2334         *x %= pitch_pixels;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Adjust the tile offset by moving the difference into
2341  * the x/y offsets.
2342  */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344                                     const struct intel_plane_state *state, int plane,
2345                                     u32 old_offset, u32 new_offset)
2346 {
2347         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348         const struct drm_framebuffer *fb = state->base.fb;
2349         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350         unsigned int rotation = state->base.rotation;
2351         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353         WARN_ON(new_offset > old_offset);
2354
2355         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int pitch_tiles;
2358
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361                                 fb->modifier[plane], cpp);
2362
2363                 if (intel_rotation_90_or_270(rotation)) {
2364                         pitch_tiles = pitch / tile_height;
2365                         swap(tile_width, tile_height);
2366                 } else {
2367                         pitch_tiles = pitch / (tile_width * cpp);
2368                 }
2369
2370                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371                                           tile_size, pitch_tiles,
2372                                           old_offset, new_offset);
2373         } else {
2374                 old_offset += *y * pitch + *x * cpp;
2375
2376                 *y = (old_offset - new_offset) / pitch;
2377                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378         }
2379
2380         return new_offset;
2381 }
2382
2383 /*
2384  * Computes the linear offset to the base tile and adjusts
2385  * x, y. bytes per pixel is assumed to be a power-of-two.
2386  *
2387  * In the 90/270 rotated case, x and y are assumed
2388  * to be already rotated to match the rotated GTT view, and
2389  * pitch is the tile_height aligned framebuffer height.
2390  *
2391  * This function is used when computing the derived information
2392  * under intel_framebuffer, so using any of that information
2393  * here is not allowed. Anything under drm_framebuffer can be
2394  * used. This is why the user has to pass in the pitch since it
2395  * is specified in the rotated orientation.
2396  */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398                                       int *x, int *y,
2399                                       const struct drm_framebuffer *fb, int plane,
2400                                       unsigned int pitch,
2401                                       unsigned int rotation,
2402                                       u32 alignment)
2403 {
2404         uint64_t fb_modifier = fb->modifier[plane];
2405         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406         u32 offset, offset_aligned;
2407
2408         if (alignment)
2409                 alignment--;
2410
2411         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412                 unsigned int tile_size, tile_width, tile_height;
2413                 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415                 tile_size = intel_tile_size(dev_priv);
2416                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417                                 fb_modifier, cpp);
2418
2419                 if (intel_rotation_90_or_270(rotation)) {
2420                         pitch_tiles = pitch / tile_height;
2421                         swap(tile_width, tile_height);
2422                 } else {
2423                         pitch_tiles = pitch / (tile_width * cpp);
2424                 }
2425
2426                 tile_rows = *y / tile_height;
2427                 *y %= tile_height;
2428
2429                 tiles = *x / tile_width;
2430                 *x %= tile_width;
2431
2432                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433                 offset_aligned = offset & ~alignment;
2434
2435                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436                                           tile_size, pitch_tiles,
2437                                           offset, offset_aligned);
2438         } else {
2439                 offset = *y * pitch + *x * cpp;
2440                 offset_aligned = offset & ~alignment;
2441
2442                 *y = (offset & alignment) / pitch;
2443                 *x = ((offset & alignment) - *y * pitch) / cpp;
2444         }
2445
2446         return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450                               const struct intel_plane_state *state,
2451                               int plane)
2452 {
2453         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454         const struct drm_framebuffer *fb = state->base.fb;
2455         unsigned int rotation = state->base.rotation;
2456         int pitch = intel_fb_pitch(fb, plane, rotation);
2457         u32 alignment;
2458
2459         /* AUX_DIST needs only 4K alignment */
2460         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461                 alignment = 4096;
2462         else
2463                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466                                           rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471                                   const struct drm_framebuffer *fb, int plane)
2472 {
2473         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474         unsigned int pitch = fb->pitches[plane];
2475         u32 linear_offset = fb->offsets[plane];
2476
2477         *y = linear_offset / pitch;
2478         *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483         switch (fb_modifier) {
2484         case I915_FORMAT_MOD_X_TILED:
2485                 return I915_TILING_X;
2486         case I915_FORMAT_MOD_Y_TILED:
2487                 return I915_TILING_Y;
2488         default:
2489                 return I915_TILING_NONE;
2490         }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495                    struct drm_framebuffer *fb)
2496 {
2497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499         u32 gtt_offset_rotated = 0;
2500         unsigned int max_size = 0;
2501         uint32_t format = fb->pixel_format;
2502         int i, num_planes = drm_format_num_planes(format);
2503         unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505         for (i = 0; i < num_planes; i++) {
2506                 unsigned int width, height;
2507                 unsigned int cpp, size;
2508                 u32 offset;
2509                 int x, y;
2510
2511                 cpp = drm_format_plane_cpp(format, i);
2512                 width = drm_format_plane_width(fb->width, format, i);
2513                 height = drm_format_plane_height(fb->height, format, i);
2514
2515                 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517                 /*
2518                  * The fence (if used) is aligned to the start of the object
2519                  * so having the framebuffer wrap around across the edge of the
2520                  * fenced region doesn't really work. We have no API to configure
2521                  * the fence start offset within the object (nor could we probably
2522                  * on gen2/3). So it's just easier if we just require that the
2523                  * fb layout agrees with the fence layout. We already check that the
2524                  * fb stride matches the fence stride elsewhere.
2525                  */
2526                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527                     (x + width) * cpp > fb->pitches[i]) {
2528                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529                                   i, fb->offsets[i]);
2530                         return -EINVAL;
2531                 }
2532
2533                 /*
2534                  * First pixel of the framebuffer from
2535                  * the start of the normal gtt mapping.
2536                  */
2537                 intel_fb->normal[i].x = x;
2538                 intel_fb->normal[i].y = y;
2539
2540                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541                                                     fb, 0, fb->pitches[i],
2542                                                     DRM_ROTATE_0, tile_size);
2543                 offset /= tile_size;
2544
2545                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546                         unsigned int tile_width, tile_height;
2547                         unsigned int pitch_tiles;
2548                         struct drm_rect r;
2549
2550                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551                                         fb->modifier[i], cpp);
2552
2553                         rot_info->plane[i].offset = offset;
2554                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558                         intel_fb->rotated[i].pitch =
2559                                 rot_info->plane[i].height * tile_height;
2560
2561                         /* how many tiles does this plane need */
2562                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563                         /*
2564                          * If the plane isn't horizontally tile aligned,
2565                          * we need one more tile.
2566                          */
2567                         if (x != 0)
2568                                 size++;
2569
2570                         /* rotate the x/y offsets to match the GTT view */
2571                         r.x1 = x;
2572                         r.y1 = y;
2573                         r.x2 = x + width;
2574                         r.y2 = y + height;
2575                         drm_rect_rotate(&r,
2576                                         rot_info->plane[i].width * tile_width,
2577                                         rot_info->plane[i].height * tile_height,
2578                                         DRM_ROTATE_270);
2579                         x = r.x1;
2580                         y = r.y1;
2581
2582                         /* rotate the tile dimensions to match the GTT view */
2583                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584                         swap(tile_width, tile_height);
2585
2586                         /*
2587                          * We only keep the x/y offsets, so push all of the
2588                          * gtt offset into the x/y offsets.
2589                          */
2590                         _intel_adjust_tile_offset(&x, &y, tile_size,
2591                                                   tile_width, tile_height, pitch_tiles,
2592                                                   gtt_offset_rotated * tile_size, 0);
2593
2594                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596                         /*
2597                          * First pixel of the framebuffer from
2598                          * the start of the rotated gtt mapping.
2599                          */
2600                         intel_fb->rotated[i].x = x;
2601                         intel_fb->rotated[i].y = y;
2602                 } else {
2603                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604                                             x * cpp, tile_size);
2605                 }
2606
2607                 /* how many tiles in total needed in the bo */
2608                 max_size = max(max_size, offset + size);
2609         }
2610
2611         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614                 return -EINVAL;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622         switch (format) {
2623         case DISPPLANE_8BPP:
2624                 return DRM_FORMAT_C8;
2625         case DISPPLANE_BGRX555:
2626                 return DRM_FORMAT_XRGB1555;
2627         case DISPPLANE_BGRX565:
2628                 return DRM_FORMAT_RGB565;
2629         default:
2630         case DISPPLANE_BGRX888:
2631                 return DRM_FORMAT_XRGB8888;
2632         case DISPPLANE_RGBX888:
2633                 return DRM_FORMAT_XBGR8888;
2634         case DISPPLANE_BGRX101010:
2635                 return DRM_FORMAT_XRGB2101010;
2636         case DISPPLANE_RGBX101010:
2637                 return DRM_FORMAT_XBGR2101010;
2638         }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643         switch (format) {
2644         case PLANE_CTL_FORMAT_RGB_565:
2645                 return DRM_FORMAT_RGB565;
2646         default:
2647         case PLANE_CTL_FORMAT_XRGB_8888:
2648                 if (rgb_order) {
2649                         if (alpha)
2650                                 return DRM_FORMAT_ABGR8888;
2651                         else
2652                                 return DRM_FORMAT_XBGR8888;
2653                 } else {
2654                         if (alpha)
2655                                 return DRM_FORMAT_ARGB8888;
2656                         else
2657                                 return DRM_FORMAT_XRGB8888;
2658                 }
2659         case PLANE_CTL_FORMAT_XRGB_2101010:
2660                 if (rgb_order)
2661                         return DRM_FORMAT_XBGR2101010;
2662                 else
2663                         return DRM_FORMAT_XRGB2101010;
2664         }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669                               struct intel_initial_plane_config *plane_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674         struct drm_i915_gem_object *obj = NULL;
2675         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676         struct drm_framebuffer *fb = &plane_config->fb->base;
2677         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679                                     PAGE_SIZE);
2680
2681         size_aligned -= base_aligned;
2682
2683         if (plane_config->size == 0)
2684                 return false;
2685
2686         /* If the FB is too big, just don't use it since fbdev is not very
2687          * important and we should probably use that space with FBC or other
2688          * features. */
2689         if (size_aligned * 2 > ggtt->stolen_usable_size)
2690                 return false;
2691
2692         mutex_lock(&dev->struct_mutex);
2693
2694         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695                                                              base_aligned,
2696                                                              base_aligned,
2697                                                              size_aligned);
2698         if (!obj) {
2699                 mutex_unlock(&dev->struct_mutex);
2700                 return false;
2701         }
2702
2703         if (plane_config->tiling == I915_TILING_X)
2704                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706         mode_cmd.pixel_format = fb->pixel_format;
2707         mode_cmd.width = fb->width;
2708         mode_cmd.height = fb->height;
2709         mode_cmd.pitches[0] = fb->pitches[0];
2710         mode_cmd.modifier[0] = fb->modifier[0];
2711         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714                                    &mode_cmd, obj)) {
2715                 DRM_DEBUG_KMS("intel fb init failed\n");
2716                 goto out_unref_obj;
2717         }
2718
2719         mutex_unlock(&dev->struct_mutex);
2720
2721         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722         return true;
2723
2724 out_unref_obj:
2725         i915_gem_object_put(obj);
2726         mutex_unlock(&dev->struct_mutex);
2727         return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734         if (plane->fb == plane->state->fb)
2735                 return;
2736
2737         if (plane->state->fb)
2738                 drm_framebuffer_unreference(plane->state->fb);
2739         plane->state->fb = plane->fb;
2740         if (plane->state->fb)
2741                 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746                              struct intel_initial_plane_config *plane_config)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = to_i915(dev);
2750         struct drm_crtc *c;
2751         struct intel_crtc *i;
2752         struct drm_i915_gem_object *obj;
2753         struct drm_plane *primary = intel_crtc->base.primary;
2754         struct drm_plane_state *plane_state = primary->state;
2755         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756         struct intel_plane *intel_plane = to_intel_plane(primary);
2757         struct intel_plane_state *intel_state =
2758                 to_intel_plane_state(plane_state);
2759         struct drm_framebuffer *fb;
2760
2761         if (!plane_config->fb)
2762                 return;
2763
2764         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765                 fb = &plane_config->fb->base;
2766                 goto valid_fb;
2767         }
2768
2769         kfree(plane_config->fb);
2770
2771         /*
2772          * Failed to alloc the obj, check to see if we should share
2773          * an fb with another CRTC instead
2774          */
2775         for_each_crtc(dev, c) {
2776                 i = to_intel_crtc(c);
2777
2778                 if (c == &intel_crtc->base)
2779                         continue;
2780
2781                 if (!i->active)
2782                         continue;
2783
2784                 fb = c->primary->fb;
2785                 if (!fb)
2786                         continue;
2787
2788                 obj = intel_fb_obj(fb);
2789                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790                         drm_framebuffer_reference(fb);
2791                         goto valid_fb;
2792                 }
2793         }
2794
2795         /*
2796          * We've failed to reconstruct the BIOS FB.  Current display state
2797          * indicates that the primary plane is visible, but has a NULL FB,
2798          * which will lead to problems later if we don't fix it up.  The
2799          * simplest solution is to just disable the primary plane now and
2800          * pretend the BIOS never had it enabled.
2801          */
2802         to_intel_plane_state(plane_state)->base.visible = false;
2803         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805         intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807         return;
2808
2809 valid_fb:
2810         plane_state->src_x = 0;
2811         plane_state->src_y = 0;
2812         plane_state->src_w = fb->width << 16;
2813         plane_state->src_h = fb->height << 16;
2814
2815         plane_state->crtc_x = 0;
2816         plane_state->crtc_y = 0;
2817         plane_state->crtc_w = fb->width;
2818         plane_state->crtc_h = fb->height;
2819
2820         intel_state->base.src.x1 = plane_state->src_x;
2821         intel_state->base.src.y1 = plane_state->src_y;
2822         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824         intel_state->base.dst.x1 = plane_state->crtc_x;
2825         intel_state->base.dst.y1 = plane_state->crtc_y;
2826         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829         obj = intel_fb_obj(fb);
2830         if (i915_gem_object_is_tiled(obj))
2831                 dev_priv->preserve_bios_swizzle = true;
2832
2833         drm_framebuffer_reference(fb);
2834         primary->fb = primary->state->fb = fb;
2835         primary->crtc = primary->state->crtc = &intel_crtc->base;
2836         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838                   &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842                                unsigned int rotation)
2843 {
2844         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846         switch (fb->modifier[plane]) {
2847         case DRM_FORMAT_MOD_NONE:
2848         case I915_FORMAT_MOD_X_TILED:
2849                 switch (cpp) {
2850                 case 8:
2851                         return 4096;
2852                 case 4:
2853                 case 2:
2854                 case 1:
2855                         return 8192;
2856                 default:
2857                         MISSING_CASE(cpp);
2858                         break;
2859                 }
2860                 break;
2861         case I915_FORMAT_MOD_Y_TILED:
2862         case I915_FORMAT_MOD_Yf_TILED:
2863                 switch (cpp) {
2864                 case 8:
2865                         return 2048;
2866                 case 4:
2867                         return 4096;
2868                 case 2:
2869                 case 1:
2870                         return 8192;
2871                 default:
2872                         MISSING_CASE(cpp);
2873                         break;
2874                 }
2875                 break;
2876         default:
2877                 MISSING_CASE(fb->modifier[plane]);
2878         }
2879
2880         return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886         const struct drm_framebuffer *fb = plane_state->base.fb;
2887         unsigned int rotation = plane_state->base.rotation;
2888         int x = plane_state->base.src.x1 >> 16;
2889         int y = plane_state->base.src.y1 >> 16;
2890         int w = drm_rect_width(&plane_state->base.src) >> 16;
2891         int h = drm_rect_height(&plane_state->base.src) >> 16;
2892         int max_width = skl_max_plane_width(fb, 0, rotation);
2893         int max_height = 4096;
2894         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896         if (w > max_width || h > max_height) {
2897                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898                               w, h, max_width, max_height);
2899                 return -EINVAL;
2900         }
2901
2902         intel_add_fb_offsets(&x, &y, plane_state, 0);
2903         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907         /*
2908          * AUX surface offset is specified as the distance from the
2909          * main surface offset, and it must be non-negative. Make
2910          * sure that is what we will get.
2911          */
2912         if (offset > aux_offset)
2913                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914                                                   offset, aux_offset & ~(alignment - 1));
2915
2916         /*
2917          * When using an X-tiled surface, the plane blows up
2918          * if the x offset + width exceed the stride.
2919          *
2920          * TODO: linear and Y-tiled seem fine, Yf untested,
2921          */
2922         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925                 while ((x + w) * cpp > fb->pitches[0]) {
2926                         if (offset == 0) {
2927                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928                                 return -EINVAL;
2929                         }
2930
2931                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932                                                           offset, offset - alignment);
2933                 }
2934         }
2935
2936         plane_state->main.offset = offset;
2937         plane_state->main.x = x;
2938         plane_state->main.y = y;
2939
2940         return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945         const struct drm_framebuffer *fb = plane_state->base.fb;
2946         unsigned int rotation = plane_state->base.rotation;
2947         int max_width = skl_max_plane_width(fb, 1, rotation);
2948         int max_height = 4096;
2949         int x = plane_state->base.src.x1 >> 17;
2950         int y = plane_state->base.src.y1 >> 17;
2951         int w = drm_rect_width(&plane_state->base.src) >> 17;
2952         int h = drm_rect_height(&plane_state->base.src) >> 17;
2953         u32 offset;
2954
2955         intel_add_fb_offsets(&x, &y, plane_state, 1);
2956         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958         /* FIXME not quite sure how/if these apply to the chroma plane */
2959         if (w > max_width || h > max_height) {
2960                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961                               w, h, max_width, max_height);
2962                 return -EINVAL;
2963         }
2964
2965         plane_state->aux.offset = offset;
2966         plane_state->aux.x = x;
2967         plane_state->aux.y = y;
2968
2969         return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974         const struct drm_framebuffer *fb = plane_state->base.fb;
2975         unsigned int rotation = plane_state->base.rotation;
2976         int ret;
2977
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (intel_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width, fb->height, DRM_ROTATE_270);
2982
2983         /*
2984          * Handle the AUX surface first since
2985          * the main surface setup depends on it.
2986          */
2987         if (fb->pixel_format == DRM_FORMAT_NV12) {
2988                 ret = skl_check_nv12_aux_surface(plane_state);
2989                 if (ret)
2990                         return ret;
2991         } else {
2992                 plane_state->aux.offset = ~0xfff;
2993                 plane_state->aux.x = 0;
2994                 plane_state->aux.y = 0;
2995         }
2996
2997         ret = skl_check_main_surface(plane_state);
2998         if (ret)
2999                 return ret;
3000
3001         return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005                                       const struct intel_crtc_state *crtc_state,
3006                                       const struct intel_plane_state *plane_state)
3007 {
3008         struct drm_device *dev = primary->dev;
3009         struct drm_i915_private *dev_priv = to_i915(dev);
3010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011         struct drm_framebuffer *fb = plane_state->base.fb;
3012         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013         int plane = intel_crtc->plane;
3014         u32 linear_offset;
3015         u32 dspcntr;
3016         i915_reg_t reg = DSPCNTR(plane);
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x = plane_state->base.src.x1 >> 16;
3019         int y = plane_state->base.src.y1 >> 16;
3020
3021         dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023         dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025         if (INTEL_INFO(dev)->gen < 4) {
3026                 if (intel_crtc->pipe == PIPE_B)
3027                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029                 /* pipesrc and dspsize control the size that is scaled from,
3030                  * which should always be the user's requested size.
3031                  */
3032                 I915_WRITE(DSPSIZE(plane),
3033                            ((crtc_state->pipe_src_h - 1) << 16) |
3034                            (crtc_state->pipe_src_w - 1));
3035                 I915_WRITE(DSPPOS(plane), 0);
3036         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037                 I915_WRITE(PRIMSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(PRIMPOS(plane), 0);
3041                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042         }
3043
3044         switch (fb->pixel_format) {
3045         case DRM_FORMAT_C8:
3046                 dspcntr |= DISPPLANE_8BPP;
3047                 break;
3048         case DRM_FORMAT_XRGB1555:
3049                 dspcntr |= DISPPLANE_BGRX555;
3050                 break;
3051         case DRM_FORMAT_RGB565:
3052                 dspcntr |= DISPPLANE_BGRX565;
3053                 break;
3054         case DRM_FORMAT_XRGB8888:
3055                 dspcntr |= DISPPLANE_BGRX888;
3056                 break;
3057         case DRM_FORMAT_XBGR8888:
3058                 dspcntr |= DISPPLANE_RGBX888;
3059                 break;
3060         case DRM_FORMAT_XRGB2101010:
3061                 dspcntr |= DISPPLANE_BGRX101010;
3062                 break;
3063         case DRM_FORMAT_XBGR2101010:
3064                 dspcntr |= DISPPLANE_RGBX101010;
3065                 break;
3066         default:
3067                 BUG();
3068         }
3069
3070         if (INTEL_GEN(dev_priv) >= 4 &&
3071             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072                 dspcntr |= DISPPLANE_TILED;
3073
3074         if (IS_G4X(dev))
3075                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077         intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079         if (INTEL_INFO(dev)->gen >= 4)
3080                 intel_crtc->dspaddr_offset =
3081                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083         if (rotation == DRM_ROTATE_180) {
3084                 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086                 x += (crtc_state->pipe_src_w - 1);
3087                 y += (crtc_state->pipe_src_h - 1);
3088         }
3089
3090         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092         if (INTEL_INFO(dev)->gen < 4)
3093                 intel_crtc->dspaddr_offset = linear_offset;
3094
3095         intel_crtc->adjusted_x = x;
3096         intel_crtc->adjusted_y = y;
3097
3098         I915_WRITE(reg, dspcntr);
3099
3100         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101         if (INTEL_INFO(dev)->gen >= 4) {
3102                 I915_WRITE(DSPSURF(plane),
3103                            intel_fb_gtt_offset(fb, rotation) +
3104                            intel_crtc->dspaddr_offset);
3105                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107         } else
3108                 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109         POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113                                        struct drm_crtc *crtc)
3114 {
3115         struct drm_device *dev = crtc->dev;
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118         int plane = intel_crtc->plane;
3119
3120         I915_WRITE(DSPCNTR(plane), 0);
3121         if (INTEL_INFO(dev_priv)->gen >= 4)
3122                 I915_WRITE(DSPSURF(plane), 0);
3123         else
3124                 I915_WRITE(DSPADDR(plane), 0);
3125         POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129                                           const struct intel_crtc_state *crtc_state,
3130                                           const struct intel_plane_state *plane_state)
3131 {
3132         struct drm_device *dev = primary->dev;
3133         struct drm_i915_private *dev_priv = to_i915(dev);
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135         struct drm_framebuffer *fb = plane_state->base.fb;
3136         int plane = intel_crtc->plane;
3137         u32 linear_offset;
3138         u32 dspcntr;
3139         i915_reg_t reg = DSPCNTR(plane);
3140         unsigned int rotation = plane_state->base.rotation;
3141         int x = plane_state->base.src.x1 >> 16;
3142         int y = plane_state->base.src.y1 >> 16;
3143
3144         dspcntr = DISPPLANE_GAMMA_ENABLE;
3145         dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3148                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150         switch (fb->pixel_format) {
3151         case DRM_FORMAT_C8:
3152                 dspcntr |= DISPPLANE_8BPP;
3153                 break;
3154         case DRM_FORMAT_RGB565:
3155                 dspcntr |= DISPPLANE_BGRX565;
3156                 break;
3157         case DRM_FORMAT_XRGB8888:
3158                 dspcntr |= DISPPLANE_BGRX888;
3159                 break;
3160         case DRM_FORMAT_XBGR8888:
3161                 dspcntr |= DISPPLANE_RGBX888;
3162                 break;
3163         case DRM_FORMAT_XRGB2101010:
3164                 dspcntr |= DISPPLANE_BGRX101010;
3165                 break;
3166         case DRM_FORMAT_XBGR2101010:
3167                 dspcntr |= DISPPLANE_RGBX101010;
3168                 break;
3169         default:
3170                 BUG();
3171         }
3172
3173         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174                 dspcntr |= DISPPLANE_TILED;
3175
3176         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3177                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179         intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181         intel_crtc->dspaddr_offset =
3182                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184         if (rotation == DRM_ROTATE_180) {
3185                 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3188                         x += (crtc_state->pipe_src_w - 1);
3189                         y += (crtc_state->pipe_src_h - 1);
3190                 }
3191         }
3192
3193         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195         intel_crtc->adjusted_x = x;
3196         intel_crtc->adjusted_y = y;
3197
3198         I915_WRITE(reg, dspcntr);
3199
3200         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201         I915_WRITE(DSPSURF(plane),
3202                    intel_fb_gtt_offset(fb, rotation) +
3203                    intel_crtc->dspaddr_offset);
3204         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3205                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206         } else {
3207                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209         }
3210         POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214                               uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217                 return 64;
3218         } else {
3219                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222         }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226                         unsigned int rotation)
3227 {
3228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229         struct i915_ggtt_view view;
3230         struct i915_vma *vma;
3231
3232         intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234         vma = i915_gem_object_to_ggtt(obj, &view);
3235         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236                  view.type))
3237                 return -1;
3238
3239         return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244         struct drm_device *dev = intel_crtc->base.dev;
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253  * This function detaches (aka. unbinds) unused scalers in hardware
3254  */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257         struct intel_crtc_scaler_state *scaler_state;
3258         int i;
3259
3260         scaler_state = &intel_crtc->config->scaler_state;
3261
3262         /* loop through and disable scalers that aren't in use */
3263         for (i = 0; i < intel_crtc->num_scalers; i++) {
3264                 if (!scaler_state->scalers[i].in_use)
3265                         skl_detach_scaler(intel_crtc, i);
3266         }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270                      unsigned int rotation)
3271 {
3272         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273         u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275         /*
3276          * The stride is either expressed as a multiple of 64 bytes chunks for
3277          * linear buffers or in number of tiles for tiled buffers.
3278          */
3279         if (intel_rotation_90_or_270(rotation)) {
3280                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283         } else {
3284                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285                                                     fb->pixel_format);
3286         }
3287
3288         return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293         switch (pixel_format) {
3294         case DRM_FORMAT_C8:
3295                 return PLANE_CTL_FORMAT_INDEXED;
3296         case DRM_FORMAT_RGB565:
3297                 return PLANE_CTL_FORMAT_RGB_565;
3298         case DRM_FORMAT_XBGR8888:
3299                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300         case DRM_FORMAT_XRGB8888:
3301                 return PLANE_CTL_FORMAT_XRGB_8888;
3302         /*
3303          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304          * to be already pre-multiplied. We need to add a knob (or a different
3305          * DRM_FORMAT) for user-space to configure that.
3306          */
3307         case DRM_FORMAT_ABGR8888:
3308                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310         case DRM_FORMAT_ARGB8888:
3311                 return PLANE_CTL_FORMAT_XRGB_8888 |
3312                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313         case DRM_FORMAT_XRGB2101010:
3314                 return PLANE_CTL_FORMAT_XRGB_2101010;
3315         case DRM_FORMAT_XBGR2101010:
3316                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317         case DRM_FORMAT_YUYV:
3318                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319         case DRM_FORMAT_YVYU:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321         case DRM_FORMAT_UYVY:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323         case DRM_FORMAT_VYUY:
3324                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325         default:
3326                 MISSING_CASE(pixel_format);
3327         }
3328
3329         return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334         switch (fb_modifier) {
3335         case DRM_FORMAT_MOD_NONE:
3336                 break;
3337         case I915_FORMAT_MOD_X_TILED:
3338                 return PLANE_CTL_TILED_X;
3339         case I915_FORMAT_MOD_Y_TILED:
3340                 return PLANE_CTL_TILED_Y;
3341         case I915_FORMAT_MOD_Yf_TILED:
3342                 return PLANE_CTL_TILED_YF;
3343         default:
3344                 MISSING_CASE(fb_modifier);
3345         }
3346
3347         return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352         switch (rotation) {
3353         case DRM_ROTATE_0:
3354                 break;
3355         /*
3356          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357          * while i915 HW rotation is clockwise, thats why this swapping.
3358          */
3359         case DRM_ROTATE_90:
3360                 return PLANE_CTL_ROTATE_270;
3361         case DRM_ROTATE_180:
3362                 return PLANE_CTL_ROTATE_180;
3363         case DRM_ROTATE_270:
3364                 return PLANE_CTL_ROTATE_90;
3365         default:
3366                 MISSING_CASE(rotation);
3367         }
3368
3369         return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373                                          const struct intel_crtc_state *crtc_state,
3374                                          const struct intel_plane_state *plane_state)
3375 {
3376         struct drm_device *dev = plane->dev;
3377         struct drm_i915_private *dev_priv = to_i915(dev);
3378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379         struct drm_framebuffer *fb = plane_state->base.fb;
3380         int pipe = intel_crtc->pipe;
3381         u32 plane_ctl;
3382         unsigned int rotation = plane_state->base.rotation;
3383         u32 stride = skl_plane_stride(fb, 0, rotation);
3384         u32 surf_addr = plane_state->main.offset;
3385         int scaler_id = plane_state->scaler_id;
3386         int src_x = plane_state->main.x;
3387         int src_y = plane_state->main.y;
3388         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3389         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3390         int dst_x = plane_state->base.dst.x1;
3391         int dst_y = plane_state->base.dst.y1;
3392         int dst_w = drm_rect_width(&plane_state->base.dst);
3393         int dst_h = drm_rect_height(&plane_state->base.dst);
3394
3395         plane_ctl = PLANE_CTL_ENABLE |
3396                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3397                     PLANE_CTL_PIPE_CSC_ENABLE;
3398
3399         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3400         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3401         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3402         plane_ctl |= skl_plane_ctl_rotation(rotation);
3403
3404         /* Sizes are 0 based */
3405         src_w--;
3406         src_h--;
3407         dst_w--;
3408         dst_h--;
3409
3410         intel_crtc->adjusted_x = src_x;
3411         intel_crtc->adjusted_y = src_y;
3412
3413         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3414         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3415         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3416         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3417
3418         if (scaler_id >= 0) {
3419                 uint32_t ps_ctrl = 0;
3420
3421                 WARN_ON(!dst_w || !dst_h);
3422                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3423                         crtc_state->scaler_state.scalers[scaler_id].mode;
3424                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3425                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3426                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3427                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3428                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3429         } else {
3430                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3431         }
3432
3433         I915_WRITE(PLANE_SURF(pipe, 0),
3434                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3435
3436         POSTING_READ(PLANE_SURF(pipe, 0));
3437 }
3438
3439 static void skylake_disable_primary_plane(struct drm_plane *primary,
3440                                           struct drm_crtc *crtc)
3441 {
3442         struct drm_device *dev = crtc->dev;
3443         struct drm_i915_private *dev_priv = to_i915(dev);
3444         int pipe = to_intel_crtc(crtc)->pipe;
3445
3446         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3447         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3448         POSTING_READ(PLANE_SURF(pipe, 0));
3449 }
3450
3451 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3452 static int
3453 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3454                            int x, int y, enum mode_set_atomic state)
3455 {
3456         /* Support for kgdboc is disabled, this needs a major rework. */
3457         DRM_ERROR("legacy panic handler not supported any more.\n");
3458
3459         return -ENODEV;
3460 }
3461
3462 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3463 {
3464         struct intel_crtc *crtc;
3465
3466         for_each_intel_crtc(&dev_priv->drm, crtc)
3467                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3468 }
3469
3470 static void intel_update_primary_planes(struct drm_device *dev)
3471 {
3472         struct drm_crtc *crtc;
3473
3474         for_each_crtc(dev, crtc) {
3475                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3476                 struct intel_plane_state *plane_state =
3477                         to_intel_plane_state(plane->base.state);
3478
3479                 if (plane_state->base.visible)
3480                         plane->update_plane(&plane->base,
3481                                             to_intel_crtc_state(crtc->state),
3482                                             plane_state);
3483         }
3484 }
3485
3486 static int
3487 __intel_display_resume(struct drm_device *dev,
3488                        struct drm_atomic_state *state)
3489 {
3490         struct drm_crtc_state *crtc_state;
3491         struct drm_crtc *crtc;
3492         int i, ret;
3493
3494         intel_modeset_setup_hw_state(dev);
3495         i915_redisable_vga(dev);
3496
3497         if (!state)
3498                 return 0;
3499
3500         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3501                 /*
3502                  * Force recalculation even if we restore
3503                  * current state. With fast modeset this may not result
3504                  * in a modeset when the state is compatible.
3505                  */
3506                 crtc_state->mode_changed = true;
3507         }
3508
3509         /* ignore any reset values/BIOS leftovers in the WM registers */
3510         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3511
3512         ret = drm_atomic_commit(state);
3513
3514         WARN_ON(ret == -EDEADLK);
3515         return ret;
3516 }
3517
3518 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3519 {
3520         return intel_has_gpu_reset(dev_priv) &&
3521                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3522 }
3523
3524 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3525 {
3526         struct drm_device *dev = &dev_priv->drm;
3527         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3528         struct drm_atomic_state *state;
3529         int ret;
3530
3531         /*
3532          * Need mode_config.mutex so that we don't
3533          * trample ongoing ->detect() and whatnot.
3534          */
3535         mutex_lock(&dev->mode_config.mutex);
3536         drm_modeset_acquire_init(ctx, 0);
3537         while (1) {
3538                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3539                 if (ret != -EDEADLK)
3540                         break;
3541
3542                 drm_modeset_backoff(ctx);
3543         }
3544
3545         /* reset doesn't touch the display, but flips might get nuked anyway, */
3546         if (!i915.force_reset_modeset_test &&
3547             !gpu_reset_clobbers_display(dev_priv))
3548                 return;
3549
3550         /*
3551          * Disabling the crtcs gracefully seems nicer. Also the
3552          * g33 docs say we should at least disable all the planes.
3553          */
3554         state = drm_atomic_helper_duplicate_state(dev, ctx);
3555         if (IS_ERR(state)) {
3556                 ret = PTR_ERR(state);
3557                 state = NULL;
3558                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3559                 goto err;
3560         }
3561
3562         ret = drm_atomic_helper_disable_all(dev, ctx);
3563         if (ret) {
3564                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3565                 goto err;
3566         }
3567
3568         dev_priv->modeset_restore_state = state;
3569         state->acquire_ctx = ctx;
3570         return;
3571
3572 err:
3573         drm_atomic_state_free(state);
3574 }
3575
3576 void intel_finish_reset(struct drm_i915_private *dev_priv)
3577 {
3578         struct drm_device *dev = &dev_priv->drm;
3579         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3580         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3581         int ret;
3582
3583         /*
3584          * Flips in the rings will be nuked by the reset,
3585          * so complete all pending flips so that user space
3586          * will get its events and not get stuck.
3587          */
3588         intel_complete_page_flips(dev_priv);
3589
3590         dev_priv->modeset_restore_state = NULL;
3591
3592         /* reset doesn't touch the display */
3593         if (!gpu_reset_clobbers_display(dev_priv)) {
3594                 if (!state) {
3595                         /*
3596                          * Flips in the rings have been nuked by the reset,
3597                          * so update the base address of all primary
3598                          * planes to the the last fb to make sure we're
3599                          * showing the correct fb after a reset.
3600                          *
3601                          * FIXME: Atomic will make this obsolete since we won't schedule
3602                          * CS-based flips (which might get lost in gpu resets) any more.
3603                          */
3604                         intel_update_primary_planes(dev);
3605                 } else {
3606                         ret = __intel_display_resume(dev, state);
3607                         if (ret)
3608                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3609                 }
3610         } else {
3611                 /*
3612                  * The display has been reset as well,
3613                  * so need a full re-initialization.
3614                  */
3615                 intel_runtime_pm_disable_interrupts(dev_priv);
3616                 intel_runtime_pm_enable_interrupts(dev_priv);
3617
3618                 intel_modeset_init_hw(dev);
3619
3620                 spin_lock_irq(&dev_priv->irq_lock);
3621                 if (dev_priv->display.hpd_irq_setup)
3622                         dev_priv->display.hpd_irq_setup(dev_priv);
3623                 spin_unlock_irq(&dev_priv->irq_lock);
3624
3625                 ret = __intel_display_resume(dev, state);
3626                 if (ret)
3627                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3628
3629                 intel_hpd_init(dev_priv);
3630         }
3631
3632         drm_modeset_drop_locks(ctx);
3633         drm_modeset_acquire_fini(ctx);
3634         mutex_unlock(&dev->mode_config.mutex);
3635 }
3636
3637 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3638 {
3639         struct drm_device *dev = crtc->dev;
3640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3641         unsigned reset_counter;
3642         bool pending;
3643
3644         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3645         if (intel_crtc->reset_counter != reset_counter)
3646                 return false;
3647
3648         spin_lock_irq(&dev->event_lock);
3649         pending = to_intel_crtc(crtc)->flip_work != NULL;
3650         spin_unlock_irq(&dev->event_lock);
3651
3652         return pending;
3653 }
3654
3655 static void intel_update_pipe_config(struct intel_crtc *crtc,
3656                                      struct intel_crtc_state *old_crtc_state)
3657 {
3658         struct drm_device *dev = crtc->base.dev;
3659         struct drm_i915_private *dev_priv = to_i915(dev);
3660         struct intel_crtc_state *pipe_config =
3661                 to_intel_crtc_state(crtc->base.state);
3662
3663         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3664         crtc->base.mode = crtc->base.state->mode;
3665
3666         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3667                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3668                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3669
3670         /*
3671          * Update pipe size and adjust fitter if needed: the reason for this is
3672          * that in compute_mode_changes we check the native mode (not the pfit
3673          * mode) to see if we can flip rather than do a full mode set. In the
3674          * fastboot case, we'll flip, but if we don't update the pipesrc and
3675          * pfit state, we'll end up with a big fb scanned out into the wrong
3676          * sized surface.
3677          */
3678
3679         I915_WRITE(PIPESRC(crtc->pipe),
3680                    ((pipe_config->pipe_src_w - 1) << 16) |
3681                    (pipe_config->pipe_src_h - 1));
3682
3683         /* on skylake this is done by detaching scalers */
3684         if (INTEL_INFO(dev)->gen >= 9) {
3685                 skl_detach_scalers(crtc);
3686
3687                 if (pipe_config->pch_pfit.enabled)
3688                         skylake_pfit_enable(crtc);
3689         } else if (HAS_PCH_SPLIT(dev)) {
3690                 if (pipe_config->pch_pfit.enabled)
3691                         ironlake_pfit_enable(crtc);
3692                 else if (old_crtc_state->pch_pfit.enabled)
3693                         ironlake_pfit_disable(crtc, true);
3694         }
3695 }
3696
3697 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3698 {
3699         struct drm_device *dev = crtc->dev;
3700         struct drm_i915_private *dev_priv = to_i915(dev);
3701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3702         int pipe = intel_crtc->pipe;
3703         i915_reg_t reg;
3704         u32 temp;
3705
3706         /* enable normal train */
3707         reg = FDI_TX_CTL(pipe);
3708         temp = I915_READ(reg);
3709         if (IS_IVYBRIDGE(dev)) {
3710                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3711                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3712         } else {
3713                 temp &= ~FDI_LINK_TRAIN_NONE;
3714                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3715         }
3716         I915_WRITE(reg, temp);
3717
3718         reg = FDI_RX_CTL(pipe);
3719         temp = I915_READ(reg);
3720         if (HAS_PCH_CPT(dev)) {
3721                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3722                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3723         } else {
3724                 temp &= ~FDI_LINK_TRAIN_NONE;
3725                 temp |= FDI_LINK_TRAIN_NONE;
3726         }
3727         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3728
3729         /* wait one idle pattern time */
3730         POSTING_READ(reg);
3731         udelay(1000);
3732
3733         /* IVB wants error correction enabled */
3734         if (IS_IVYBRIDGE(dev))
3735                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3736                            FDI_FE_ERRC_ENABLE);
3737 }
3738
3739 /* The FDI link training functions for ILK/Ibexpeak. */
3740 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3741 {
3742         struct drm_device *dev = crtc->dev;
3743         struct drm_i915_private *dev_priv = to_i915(dev);
3744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3745         int pipe = intel_crtc->pipe;
3746         i915_reg_t reg;
3747         u32 temp, tries;
3748
3749         /* FDI needs bits from pipe first */
3750         assert_pipe_enabled(dev_priv, pipe);
3751
3752         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3753            for train result */
3754         reg = FDI_RX_IMR(pipe);
3755         temp = I915_READ(reg);
3756         temp &= ~FDI_RX_SYMBOL_LOCK;
3757         temp &= ~FDI_RX_BIT_LOCK;
3758         I915_WRITE(reg, temp);
3759         I915_READ(reg);
3760         udelay(150);
3761
3762         /* enable CPU FDI TX and PCH FDI RX */
3763         reg = FDI_TX_CTL(pipe);
3764         temp = I915_READ(reg);
3765         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3766         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3767         temp &= ~FDI_LINK_TRAIN_NONE;
3768         temp |= FDI_LINK_TRAIN_PATTERN_1;
3769         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3770
3771         reg = FDI_RX_CTL(pipe);
3772         temp = I915_READ(reg);
3773         temp &= ~FDI_LINK_TRAIN_NONE;
3774         temp |= FDI_LINK_TRAIN_PATTERN_1;
3775         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3776
3777         POSTING_READ(reg);
3778         udelay(150);
3779
3780         /* Ironlake workaround, enable clock pointer after FDI enable*/
3781         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3782         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3783                    FDI_RX_PHASE_SYNC_POINTER_EN);
3784
3785         reg = FDI_RX_IIR(pipe);
3786         for (tries = 0; tries < 5; tries++) {
3787                 temp = I915_READ(reg);
3788                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3789
3790                 if ((temp & FDI_RX_BIT_LOCK)) {
3791                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3792                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3793                         break;
3794                 }
3795         }
3796         if (tries == 5)
3797                 DRM_ERROR("FDI train 1 fail!\n");
3798
3799         /* Train 2 */
3800         reg = FDI_TX_CTL(pipe);
3801         temp = I915_READ(reg);
3802         temp &= ~FDI_LINK_TRAIN_NONE;
3803         temp |= FDI_LINK_TRAIN_PATTERN_2;
3804         I915_WRITE(reg, temp);
3805
3806         reg = FDI_RX_CTL(pipe);
3807         temp = I915_READ(reg);
3808         temp &= ~FDI_LINK_TRAIN_NONE;
3809         temp |= FDI_LINK_TRAIN_PATTERN_2;
3810         I915_WRITE(reg, temp);
3811
3812         POSTING_READ(reg);
3813         udelay(150);
3814
3815         reg = FDI_RX_IIR(pipe);
3816         for (tries = 0; tries < 5; tries++) {
3817                 temp = I915_READ(reg);
3818                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3819
3820                 if (temp & FDI_RX_SYMBOL_LOCK) {
3821                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3822                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3823                         break;
3824                 }
3825         }
3826         if (tries == 5)
3827                 DRM_ERROR("FDI train 2 fail!\n");
3828
3829         DRM_DEBUG_KMS("FDI train done\n");
3830
3831 }
3832
3833 static const int snb_b_fdi_train_param[] = {
3834         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3835         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3836         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3837         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3838 };
3839
3840 /* The FDI link training functions for SNB/Cougarpoint. */
3841 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_i915_private *dev_priv = to_i915(dev);
3845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846         int pipe = intel_crtc->pipe;
3847         i915_reg_t reg;
3848         u32 temp, i, retry;
3849
3850         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3851            for train result */
3852         reg = FDI_RX_IMR(pipe);
3853         temp = I915_READ(reg);
3854         temp &= ~FDI_RX_SYMBOL_LOCK;
3855         temp &= ~FDI_RX_BIT_LOCK;
3856         I915_WRITE(reg, temp);
3857
3858         POSTING_READ(reg);
3859         udelay(150);
3860
3861         /* enable CPU FDI TX and PCH FDI RX */
3862         reg = FDI_TX_CTL(pipe);
3863         temp = I915_READ(reg);
3864         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3865         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3866         temp &= ~FDI_LINK_TRAIN_NONE;
3867         temp |= FDI_LINK_TRAIN_PATTERN_1;
3868         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3869         /* SNB-B */
3870         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3871         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3872
3873         I915_WRITE(FDI_RX_MISC(pipe),
3874                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3875
3876         reg = FDI_RX_CTL(pipe);
3877         temp = I915_READ(reg);
3878         if (HAS_PCH_CPT(dev)) {
3879                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3880                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3881         } else {
3882                 temp &= ~FDI_LINK_TRAIN_NONE;
3883                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3884         }
3885         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3886
3887         POSTING_READ(reg);
3888         udelay(150);
3889
3890         for (i = 0; i < 4; i++) {
3891                 reg = FDI_TX_CTL(pipe);
3892                 temp = I915_READ(reg);
3893                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3894                 temp |= snb_b_fdi_train_param[i];
3895                 I915_WRITE(reg, temp);
3896
3897                 POSTING_READ(reg);
3898                 udelay(500);
3899
3900                 for (retry = 0; retry < 5; retry++) {
3901                         reg = FDI_RX_IIR(pipe);
3902                         temp = I915_READ(reg);
3903                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3904                         if (temp & FDI_RX_BIT_LOCK) {
3905                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3906                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3907                                 break;
3908                         }
3909                         udelay(50);
3910                 }
3911                 if (retry < 5)
3912                         break;
3913         }
3914         if (i == 4)
3915                 DRM_ERROR("FDI train 1 fail!\n");
3916
3917         /* Train 2 */
3918         reg = FDI_TX_CTL(pipe);
3919         temp = I915_READ(reg);
3920         temp &= ~FDI_LINK_TRAIN_NONE;
3921         temp |= FDI_LINK_TRAIN_PATTERN_2;
3922         if (IS_GEN6(dev)) {
3923                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3924                 /* SNB-B */
3925                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3926         }
3927         I915_WRITE(reg, temp);
3928
3929         reg = FDI_RX_CTL(pipe);
3930         temp = I915_READ(reg);
3931         if (HAS_PCH_CPT(dev)) {
3932                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3933                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3934         } else {
3935                 temp &= ~FDI_LINK_TRAIN_NONE;
3936                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3937         }
3938         I915_WRITE(reg, temp);
3939
3940         POSTING_READ(reg);
3941         udelay(150);
3942
3943         for (i = 0; i < 4; i++) {
3944                 reg = FDI_TX_CTL(pipe);
3945                 temp = I915_READ(reg);
3946                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3947                 temp |= snb_b_fdi_train_param[i];
3948                 I915_WRITE(reg, temp);
3949
3950                 POSTING_READ(reg);
3951                 udelay(500);
3952
3953                 for (retry = 0; retry < 5; retry++) {
3954                         reg = FDI_RX_IIR(pipe);
3955                         temp = I915_READ(reg);
3956                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3957                         if (temp & FDI_RX_SYMBOL_LOCK) {
3958                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3959                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3960                                 break;
3961                         }
3962                         udelay(50);
3963                 }
3964                 if (retry < 5)
3965                         break;
3966         }
3967         if (i == 4)
3968                 DRM_ERROR("FDI train 2 fail!\n");
3969
3970         DRM_DEBUG_KMS("FDI train done.\n");
3971 }
3972
3973 /* Manual link training for Ivy Bridge A0 parts */
3974 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3975 {
3976         struct drm_device *dev = crtc->dev;
3977         struct drm_i915_private *dev_priv = to_i915(dev);
3978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3979         int pipe = intel_crtc->pipe;
3980         i915_reg_t reg;
3981         u32 temp, i, j;
3982
3983         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3984            for train result */
3985         reg = FDI_RX_IMR(pipe);
3986         temp = I915_READ(reg);
3987         temp &= ~FDI_RX_SYMBOL_LOCK;
3988         temp &= ~FDI_RX_BIT_LOCK;
3989         I915_WRITE(reg, temp);
3990
3991         POSTING_READ(reg);
3992         udelay(150);
3993
3994         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3995                       I915_READ(FDI_RX_IIR(pipe)));
3996
3997         /* Try each vswing and preemphasis setting twice before moving on */
3998         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3999                 /* disable first in case we need to retry */
4000                 reg = FDI_TX_CTL(pipe);
4001                 temp = I915_READ(reg);
4002                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4003                 temp &= ~FDI_TX_ENABLE;
4004                 I915_WRITE(reg, temp);
4005
4006                 reg = FDI_RX_CTL(pipe);
4007                 temp = I915_READ(reg);
4008                 temp &= ~FDI_LINK_TRAIN_AUTO;
4009                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4010                 temp &= ~FDI_RX_ENABLE;
4011                 I915_WRITE(reg, temp);
4012
4013                 /* enable CPU FDI TX and PCH FDI RX */
4014                 reg = FDI_TX_CTL(pipe);
4015                 temp = I915_READ(reg);
4016                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4017                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4018                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4019                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4020                 temp |= snb_b_fdi_train_param[j/2];
4021                 temp |= FDI_COMPOSITE_SYNC;
4022                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4023
4024                 I915_WRITE(FDI_RX_MISC(pipe),
4025                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4026
4027                 reg = FDI_RX_CTL(pipe);
4028                 temp = I915_READ(reg);
4029                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4030                 temp |= FDI_COMPOSITE_SYNC;
4031                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4032
4033                 POSTING_READ(reg);
4034                 udelay(1); /* should be 0.5us */
4035
4036                 for (i = 0; i < 4; i++) {
4037                         reg = FDI_RX_IIR(pipe);
4038                         temp = I915_READ(reg);
4039                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4040
4041                         if (temp & FDI_RX_BIT_LOCK ||
4042                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4043                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4044                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4045                                               i);
4046                                 break;
4047                         }
4048                         udelay(1); /* should be 0.5us */
4049                 }
4050                 if (i == 4) {
4051                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4052                         continue;
4053                 }
4054
4055                 /* Train 2 */
4056                 reg = FDI_TX_CTL(pipe);
4057                 temp = I915_READ(reg);
4058                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4059                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4060                 I915_WRITE(reg, temp);
4061
4062                 reg = FDI_RX_CTL(pipe);
4063                 temp = I915_READ(reg);
4064                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4065                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4066                 I915_WRITE(reg, temp);
4067
4068                 POSTING_READ(reg);
4069                 udelay(2); /* should be 1.5us */
4070
4071                 for (i = 0; i < 4; i++) {
4072                         reg = FDI_RX_IIR(pipe);
4073                         temp = I915_READ(reg);
4074                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4075
4076                         if (temp & FDI_RX_SYMBOL_LOCK ||
4077                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4078                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4079                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4080                                               i);
4081                                 goto train_done;
4082                         }
4083                         udelay(2); /* should be 1.5us */
4084                 }
4085                 if (i == 4)
4086                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4087         }
4088
4089 train_done:
4090         DRM_DEBUG_KMS("FDI train done.\n");
4091 }
4092
4093 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4094 {
4095         struct drm_device *dev = intel_crtc->base.dev;
4096         struct drm_i915_private *dev_priv = to_i915(dev);
4097         int pipe = intel_crtc->pipe;
4098         i915_reg_t reg;
4099         u32 temp;
4100
4101         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4102         reg = FDI_RX_CTL(pipe);
4103         temp = I915_READ(reg);
4104         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4105         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4106         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4107         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4108
4109         POSTING_READ(reg);
4110         udelay(200);
4111
4112         /* Switch from Rawclk to PCDclk */
4113         temp = I915_READ(reg);
4114         I915_WRITE(reg, temp | FDI_PCDCLK);
4115
4116         POSTING_READ(reg);
4117         udelay(200);
4118
4119         /* Enable CPU FDI TX PLL, always on for Ironlake */
4120         reg = FDI_TX_CTL(pipe);
4121         temp = I915_READ(reg);
4122         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4123                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4124
4125                 POSTING_READ(reg);
4126                 udelay(100);
4127         }
4128 }
4129
4130 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4131 {
4132         struct drm_device *dev = intel_crtc->base.dev;
4133         struct drm_i915_private *dev_priv = to_i915(dev);
4134         int pipe = intel_crtc->pipe;
4135         i915_reg_t reg;
4136         u32 temp;
4137
4138         /* Switch from PCDclk to Rawclk */
4139         reg = FDI_RX_CTL(pipe);
4140         temp = I915_READ(reg);
4141         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4142
4143         /* Disable CPU FDI TX PLL */
4144         reg = FDI_TX_CTL(pipe);
4145         temp = I915_READ(reg);
4146         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4147
4148         POSTING_READ(reg);
4149         udelay(100);
4150
4151         reg = FDI_RX_CTL(pipe);
4152         temp = I915_READ(reg);
4153         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4154
4155         /* Wait for the clocks to turn off. */
4156         POSTING_READ(reg);
4157         udelay(100);
4158 }
4159
4160 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4161 {
4162         struct drm_device *dev = crtc->dev;
4163         struct drm_i915_private *dev_priv = to_i915(dev);
4164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4165         int pipe = intel_crtc->pipe;
4166         i915_reg_t reg;
4167         u32 temp;
4168
4169         /* disable CPU FDI tx and PCH FDI rx */
4170         reg = FDI_TX_CTL(pipe);
4171         temp = I915_READ(reg);
4172         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4173         POSTING_READ(reg);
4174
4175         reg = FDI_RX_CTL(pipe);
4176         temp = I915_READ(reg);
4177         temp &= ~(0x7 << 16);
4178         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4179         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4180
4181         POSTING_READ(reg);
4182         udelay(100);
4183
4184         /* Ironlake workaround, disable clock pointer after downing FDI */
4185         if (HAS_PCH_IBX(dev))
4186                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4187
4188         /* still set train pattern 1 */
4189         reg = FDI_TX_CTL(pipe);
4190         temp = I915_READ(reg);
4191         temp &= ~FDI_LINK_TRAIN_NONE;
4192         temp |= FDI_LINK_TRAIN_PATTERN_1;
4193         I915_WRITE(reg, temp);
4194
4195         reg = FDI_RX_CTL(pipe);
4196         temp = I915_READ(reg);
4197         if (HAS_PCH_CPT(dev)) {
4198                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4199                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4200         } else {
4201                 temp &= ~FDI_LINK_TRAIN_NONE;
4202                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4203         }
4204         /* BPC in FDI rx is consistent with that in PIPECONF */
4205         temp &= ~(0x07 << 16);
4206         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4207         I915_WRITE(reg, temp);
4208
4209         POSTING_READ(reg);
4210         udelay(100);
4211 }
4212
4213 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4214 {
4215         struct intel_crtc *crtc;
4216
4217         /* Note that we don't need to be called with mode_config.lock here
4218          * as our list of CRTC objects is static for the lifetime of the
4219          * device and so cannot disappear as we iterate. Similarly, we can
4220          * happily treat the predicates as racy, atomic checks as userspace
4221          * cannot claim and pin a new fb without at least acquring the
4222          * struct_mutex and so serialising with us.
4223          */
4224         for_each_intel_crtc(dev, crtc) {
4225                 if (atomic_read(&crtc->unpin_work_count) == 0)
4226                         continue;
4227
4228                 if (crtc->flip_work)
4229                         intel_wait_for_vblank(dev, crtc->pipe);
4230
4231                 return true;
4232         }
4233
4234         return false;
4235 }
4236
4237 static void page_flip_completed(struct intel_crtc *intel_crtc)
4238 {
4239         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4240         struct intel_flip_work *work = intel_crtc->flip_work;
4241
4242         intel_crtc->flip_work = NULL;
4243
4244         if (work->event)
4245                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4246
4247         drm_crtc_vblank_put(&intel_crtc->base);
4248
4249         wake_up_all(&dev_priv->pending_flip_queue);
4250         queue_work(dev_priv->wq, &work->unpin_work);
4251
4252         trace_i915_flip_complete(intel_crtc->plane,
4253                                  work->pending_flip_obj);
4254 }
4255
4256 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4257 {
4258         struct drm_device *dev = crtc->dev;
4259         struct drm_i915_private *dev_priv = to_i915(dev);
4260         long ret;
4261
4262         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4263
4264         ret = wait_event_interruptible_timeout(
4265                                         dev_priv->pending_flip_queue,
4266                                         !intel_crtc_has_pending_flip(crtc),
4267                                         60*HZ);
4268
4269         if (ret < 0)
4270                 return ret;
4271
4272         if (ret == 0) {
4273                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4274                 struct intel_flip_work *work;
4275
4276                 spin_lock_irq(&dev->event_lock);
4277                 work = intel_crtc->flip_work;
4278                 if (work && !is_mmio_work(work)) {
4279                         WARN_ONCE(1, "Removing stuck page flip\n");
4280                         page_flip_completed(intel_crtc);
4281                 }
4282                 spin_unlock_irq(&dev->event_lock);
4283         }
4284
4285         return 0;
4286 }
4287
4288 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4289 {
4290         u32 temp;
4291
4292         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4293
4294         mutex_lock(&dev_priv->sb_lock);
4295
4296         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4297         temp |= SBI_SSCCTL_DISABLE;
4298         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4299
4300         mutex_unlock(&dev_priv->sb_lock);
4301 }
4302
4303 /* Program iCLKIP clock to the desired frequency */
4304 static void lpt_program_iclkip(struct drm_crtc *crtc)
4305 {
4306         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4307         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4308         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4309         u32 temp;
4310
4311         lpt_disable_iclkip(dev_priv);
4312
4313         /* The iCLK virtual clock root frequency is in MHz,
4314          * but the adjusted_mode->crtc_clock in in KHz. To get the
4315          * divisors, it is necessary to divide one by another, so we
4316          * convert the virtual clock precision to KHz here for higher
4317          * precision.
4318          */
4319         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4320                 u32 iclk_virtual_root_freq = 172800 * 1000;
4321                 u32 iclk_pi_range = 64;
4322                 u32 desired_divisor;
4323
4324                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4325                                                     clock << auxdiv);
4326                 divsel = (desired_divisor / iclk_pi_range) - 2;
4327                 phaseinc = desired_divisor % iclk_pi_range;
4328
4329                 /*
4330                  * Near 20MHz is a corner case which is
4331                  * out of range for the 7-bit divisor
4332                  */
4333                 if (divsel <= 0x7f)
4334                         break;
4335         }
4336
4337         /* This should not happen with any sane values */
4338         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4339                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4340         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4341                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4342
4343         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4344                         clock,
4345                         auxdiv,
4346                         divsel,
4347                         phasedir,
4348                         phaseinc);
4349
4350         mutex_lock(&dev_priv->sb_lock);
4351
4352         /* Program SSCDIVINTPHASE6 */
4353         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4354         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4355         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4356         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4357         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4358         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4359         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4360         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4361
4362         /* Program SSCAUXDIV */
4363         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4364         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4365         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4366         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4367
4368         /* Enable modulator and associated divider */
4369         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4370         temp &= ~SBI_SSCCTL_DISABLE;
4371         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4372
4373         mutex_unlock(&dev_priv->sb_lock);
4374
4375         /* Wait for initialization time */
4376         udelay(24);
4377
4378         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4379 }
4380
4381 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4382 {
4383         u32 divsel, phaseinc, auxdiv;
4384         u32 iclk_virtual_root_freq = 172800 * 1000;
4385         u32 iclk_pi_range = 64;
4386         u32 desired_divisor;
4387         u32 temp;
4388
4389         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4390                 return 0;
4391
4392         mutex_lock(&dev_priv->sb_lock);
4393
4394         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4395         if (temp & SBI_SSCCTL_DISABLE) {
4396                 mutex_unlock(&dev_priv->sb_lock);
4397                 return 0;
4398         }
4399
4400         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4401         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4402                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4403         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4404                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4405
4406         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4407         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4408                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4409
4410         mutex_unlock(&dev_priv->sb_lock);
4411
4412         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4413
4414         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4415                                  desired_divisor << auxdiv);
4416 }
4417
4418 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4419                                                 enum pipe pch_transcoder)
4420 {
4421         struct drm_device *dev = crtc->base.dev;
4422         struct drm_i915_private *dev_priv = to_i915(dev);
4423         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4424
4425         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4426                    I915_READ(HTOTAL(cpu_transcoder)));
4427         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4428                    I915_READ(HBLANK(cpu_transcoder)));
4429         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4430                    I915_READ(HSYNC(cpu_transcoder)));
4431
4432         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4433                    I915_READ(VTOTAL(cpu_transcoder)));
4434         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4435                    I915_READ(VBLANK(cpu_transcoder)));
4436         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4437                    I915_READ(VSYNC(cpu_transcoder)));
4438         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4439                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4440 }
4441
4442 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4443 {
4444         struct drm_i915_private *dev_priv = to_i915(dev);
4445         uint32_t temp;
4446
4447         temp = I915_READ(SOUTH_CHICKEN1);
4448         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4449                 return;
4450
4451         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4452         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4453
4454         temp &= ~FDI_BC_BIFURCATION_SELECT;
4455         if (enable)
4456                 temp |= FDI_BC_BIFURCATION_SELECT;
4457
4458         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4459         I915_WRITE(SOUTH_CHICKEN1, temp);
4460         POSTING_READ(SOUTH_CHICKEN1);
4461 }
4462
4463 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4464 {
4465         struct drm_device *dev = intel_crtc->base.dev;
4466
4467         switch (intel_crtc->pipe) {
4468         case PIPE_A:
4469                 break;
4470         case PIPE_B:
4471                 if (intel_crtc->config->fdi_lanes > 2)
4472                         cpt_set_fdi_bc_bifurcation(dev, false);
4473                 else
4474                         cpt_set_fdi_bc_bifurcation(dev, true);
4475
4476                 break;
4477         case PIPE_C:
4478                 cpt_set_fdi_bc_bifurcation(dev, true);
4479
4480                 break;
4481         default:
4482                 BUG();
4483         }
4484 }
4485
4486 /* Return which DP Port should be selected for Transcoder DP control */
4487 static enum port
4488 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4489 {
4490         struct drm_device *dev = crtc->dev;
4491         struct intel_encoder *encoder;
4492
4493         for_each_encoder_on_crtc(dev, crtc, encoder) {
4494                 if (encoder->type == INTEL_OUTPUT_DP ||
4495                     encoder->type == INTEL_OUTPUT_EDP)
4496                         return enc_to_dig_port(&encoder->base)->port;
4497         }
4498
4499         return -1;
4500 }
4501
4502 /*
4503  * Enable PCH resources required for PCH ports:
4504  *   - PCH PLLs
4505  *   - FDI training & RX/TX
4506  *   - update transcoder timings
4507  *   - DP transcoding bits
4508  *   - transcoder
4509  */
4510 static void ironlake_pch_enable(struct drm_crtc *crtc)
4511 {
4512         struct drm_device *dev = crtc->dev;
4513         struct drm_i915_private *dev_priv = to_i915(dev);
4514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4515         int pipe = intel_crtc->pipe;
4516         u32 temp;
4517
4518         assert_pch_transcoder_disabled(dev_priv, pipe);
4519
4520         if (IS_IVYBRIDGE(dev))
4521                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4522
4523         /* Write the TU size bits before fdi link training, so that error
4524          * detection works. */
4525         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4526                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4527
4528         /* For PCH output, training FDI link */
4529         dev_priv->display.fdi_link_train(crtc);
4530
4531         /* We need to program the right clock selection before writing the pixel
4532          * mutliplier into the DPLL. */
4533         if (HAS_PCH_CPT(dev)) {
4534                 u32 sel;
4535
4536                 temp = I915_READ(PCH_DPLL_SEL);
4537                 temp |= TRANS_DPLL_ENABLE(pipe);
4538                 sel = TRANS_DPLLB_SEL(pipe);
4539                 if (intel_crtc->config->shared_dpll ==
4540                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4541                         temp |= sel;
4542                 else
4543                         temp &= ~sel;
4544                 I915_WRITE(PCH_DPLL_SEL, temp);
4545         }
4546
4547         /* XXX: pch pll's can be enabled any time before we enable the PCH
4548          * transcoder, and we actually should do this to not upset any PCH
4549          * transcoder that already use the clock when we share it.
4550          *
4551          * Note that enable_shared_dpll tries to do the right thing, but
4552          * get_shared_dpll unconditionally resets the pll - we need that to have
4553          * the right LVDS enable sequence. */
4554         intel_enable_shared_dpll(intel_crtc);
4555
4556         /* set transcoder timing, panel must allow it */
4557         assert_panel_unlocked(dev_priv, pipe);
4558         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4559
4560         intel_fdi_normal_train(crtc);
4561
4562         /* For PCH DP, enable TRANS_DP_CTL */
4563         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4564                 const struct drm_display_mode *adjusted_mode =
4565                         &intel_crtc->config->base.adjusted_mode;
4566                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4567                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4568                 temp = I915_READ(reg);
4569                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4570                           TRANS_DP_SYNC_MASK |
4571                           TRANS_DP_BPC_MASK);
4572                 temp |= TRANS_DP_OUTPUT_ENABLE;
4573                 temp |= bpc << 9; /* same format but at 11:9 */
4574
4575                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4576                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4577                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4578                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4579
4580                 switch (intel_trans_dp_port_sel(crtc)) {
4581                 case PORT_B:
4582                         temp |= TRANS_DP_PORT_SEL_B;
4583                         break;
4584                 case PORT_C:
4585                         temp |= TRANS_DP_PORT_SEL_C;
4586                         break;
4587                 case PORT_D:
4588                         temp |= TRANS_DP_PORT_SEL_D;
4589                         break;
4590                 default:
4591                         BUG();
4592                 }
4593
4594                 I915_WRITE(reg, temp);
4595         }
4596
4597         ironlake_enable_pch_transcoder(dev_priv, pipe);
4598 }
4599
4600 static void lpt_pch_enable(struct drm_crtc *crtc)
4601 {
4602         struct drm_device *dev = crtc->dev;
4603         struct drm_i915_private *dev_priv = to_i915(dev);
4604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4605         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4606
4607         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4608
4609         lpt_program_iclkip(crtc);
4610
4611         /* Set transcoder timing. */
4612         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4613
4614         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4615 }
4616
4617 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4618 {
4619         struct drm_i915_private *dev_priv = to_i915(dev);
4620         i915_reg_t dslreg = PIPEDSL(pipe);
4621         u32 temp;
4622
4623         temp = I915_READ(dslreg);
4624         udelay(500);
4625         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4626                 if (wait_for(I915_READ(dslreg) != temp, 5))
4627                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4628         }
4629 }
4630
4631 static int
4632 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4633                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4634                   int src_w, int src_h, int dst_w, int dst_h)
4635 {
4636         struct intel_crtc_scaler_state *scaler_state =
4637                 &crtc_state->scaler_state;
4638         struct intel_crtc *intel_crtc =
4639                 to_intel_crtc(crtc_state->base.crtc);
4640         int need_scaling;
4641
4642         need_scaling = intel_rotation_90_or_270(rotation) ?
4643                 (src_h != dst_w || src_w != dst_h):
4644                 (src_w != dst_w || src_h != dst_h);
4645
4646         /*
4647          * if plane is being disabled or scaler is no more required or force detach
4648          *  - free scaler binded to this plane/crtc
4649          *  - in order to do this, update crtc->scaler_usage
4650          *
4651          * Here scaler state in crtc_state is set free so that
4652          * scaler can be assigned to other user. Actual register
4653          * update to free the scaler is done in plane/panel-fit programming.
4654          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4655          */
4656         if (force_detach || !need_scaling) {
4657                 if (*scaler_id >= 0) {
4658                         scaler_state->scaler_users &= ~(1 << scaler_user);
4659                         scaler_state->scalers[*scaler_id].in_use = 0;
4660
4661                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4662                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4663                                 intel_crtc->pipe, scaler_user, *scaler_id,
4664                                 scaler_state->scaler_users);
4665                         *scaler_id = -1;
4666                 }
4667                 return 0;
4668         }
4669
4670         /* range checks */
4671         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4672                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4673
4674                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4675                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4676                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4677                         "size is out of scaler range\n",
4678                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4679                 return -EINVAL;
4680         }
4681
4682         /* mark this plane as a scaler user in crtc_state */
4683         scaler_state->scaler_users |= (1 << scaler_user);
4684         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4685                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4686                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4687                 scaler_state->scaler_users);
4688
4689         return 0;
4690 }
4691
4692 /**
4693  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4694  *
4695  * @state: crtc's scaler state
4696  *
4697  * Return
4698  *     0 - scaler_usage updated successfully
4699  *    error - requested scaling cannot be supported or other error condition
4700  */
4701 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4702 {
4703         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4704         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4705
4706         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4707                       intel_crtc->base.base.id, intel_crtc->base.name,
4708                       intel_crtc->pipe, SKL_CRTC_INDEX);
4709
4710         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4711                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4712                 state->pipe_src_w, state->pipe_src_h,
4713                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4714 }
4715
4716 /**
4717  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4718  *
4719  * @state: crtc's scaler state
4720  * @plane_state: atomic plane state to update
4721  *
4722  * Return
4723  *     0 - scaler_usage updated successfully
4724  *    error - requested scaling cannot be supported or other error condition
4725  */
4726 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4727                                    struct intel_plane_state *plane_state)
4728 {
4729
4730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4731         struct intel_plane *intel_plane =
4732                 to_intel_plane(plane_state->base.plane);
4733         struct drm_framebuffer *fb = plane_state->base.fb;
4734         int ret;
4735
4736         bool force_detach = !fb || !plane_state->base.visible;
4737
4738         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4739                       intel_plane->base.base.id, intel_plane->base.name,
4740                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4741
4742         ret = skl_update_scaler(crtc_state, force_detach,
4743                                 drm_plane_index(&intel_plane->base),
4744                                 &plane_state->scaler_id,
4745                                 plane_state->base.rotation,
4746                                 drm_rect_width(&plane_state->base.src) >> 16,
4747                                 drm_rect_height(&plane_state->base.src) >> 16,
4748                                 drm_rect_width(&plane_state->base.dst),
4749                                 drm_rect_height(&plane_state->base.dst));
4750
4751         if (ret || plane_state->scaler_id < 0)
4752                 return ret;
4753
4754         /* check colorkey */
4755         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4756                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4757                               intel_plane->base.base.id,
4758                               intel_plane->base.name);
4759                 return -EINVAL;
4760         }
4761
4762         /* Check src format */
4763         switch (fb->pixel_format) {
4764         case DRM_FORMAT_RGB565:
4765         case DRM_FORMAT_XBGR8888:
4766         case DRM_FORMAT_XRGB8888:
4767         case DRM_FORMAT_ABGR8888:
4768         case DRM_FORMAT_ARGB8888:
4769         case DRM_FORMAT_XRGB2101010:
4770         case DRM_FORMAT_XBGR2101010:
4771         case DRM_FORMAT_YUYV:
4772         case DRM_FORMAT_YVYU:
4773         case DRM_FORMAT_UYVY:
4774         case DRM_FORMAT_VYUY:
4775                 break;
4776         default:
4777                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4778                               intel_plane->base.base.id, intel_plane->base.name,
4779                               fb->base.id, fb->pixel_format);
4780                 return -EINVAL;
4781         }
4782
4783         return 0;
4784 }
4785
4786 static void skylake_scaler_disable(struct intel_crtc *crtc)
4787 {
4788         int i;
4789
4790         for (i = 0; i < crtc->num_scalers; i++)
4791                 skl_detach_scaler(crtc, i);
4792 }
4793
4794 static void skylake_pfit_enable(struct intel_crtc *crtc)
4795 {
4796         struct drm_device *dev = crtc->base.dev;
4797         struct drm_i915_private *dev_priv = to_i915(dev);
4798         int pipe = crtc->pipe;
4799         struct intel_crtc_scaler_state *scaler_state =
4800                 &crtc->config->scaler_state;
4801
4802         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4803
4804         if (crtc->config->pch_pfit.enabled) {
4805                 int id;
4806
4807                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4808                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4809                         return;
4810                 }
4811
4812                 id = scaler_state->scaler_id;
4813                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4814                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4815                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4816                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4817
4818                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4819         }
4820 }
4821
4822 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4823 {
4824         struct drm_device *dev = crtc->base.dev;
4825         struct drm_i915_private *dev_priv = to_i915(dev);
4826         int pipe = crtc->pipe;
4827
4828         if (crtc->config->pch_pfit.enabled) {
4829                 /* Force use of hard-coded filter coefficients
4830                  * as some pre-programmed values are broken,
4831                  * e.g. x201.
4832                  */
4833                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4834                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4835                                                  PF_PIPE_SEL_IVB(pipe));
4836                 else
4837                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4838                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4839                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4840         }
4841 }
4842
4843 void hsw_enable_ips(struct intel_crtc *crtc)
4844 {
4845         struct drm_device *dev = crtc->base.dev;
4846         struct drm_i915_private *dev_priv = to_i915(dev);
4847
4848         if (!crtc->config->ips_enabled)
4849                 return;
4850
4851         /*
4852          * We can only enable IPS after we enable a plane and wait for a vblank
4853          * This function is called from post_plane_update, which is run after
4854          * a vblank wait.
4855          */
4856
4857         assert_plane_enabled(dev_priv, crtc->plane);
4858         if (IS_BROADWELL(dev)) {
4859                 mutex_lock(&dev_priv->rps.hw_lock);
4860                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4861                 mutex_unlock(&dev_priv->rps.hw_lock);
4862                 /* Quoting Art Runyan: "its not safe to expect any particular
4863                  * value in IPS_CTL bit 31 after enabling IPS through the
4864                  * mailbox." Moreover, the mailbox may return a bogus state,
4865                  * so we need to just enable it and continue on.
4866                  */
4867         } else {
4868                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4869                 /* The bit only becomes 1 in the next vblank, so this wait here
4870                  * is essentially intel_wait_for_vblank. If we don't have this
4871                  * and don't wait for vblanks until the end of crtc_enable, then
4872                  * the HW state readout code will complain that the expected
4873                  * IPS_CTL value is not the one we read. */
4874                 if (intel_wait_for_register(dev_priv,
4875                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4876                                             50))
4877                         DRM_ERROR("Timed out waiting for IPS enable\n");
4878         }
4879 }
4880
4881 void hsw_disable_ips(struct intel_crtc *crtc)
4882 {
4883         struct drm_device *dev = crtc->base.dev;
4884         struct drm_i915_private *dev_priv = to_i915(dev);
4885
4886         if (!crtc->config->ips_enabled)
4887                 return;
4888
4889         assert_plane_enabled(dev_priv, crtc->plane);
4890         if (IS_BROADWELL(dev)) {
4891                 mutex_lock(&dev_priv->rps.hw_lock);
4892                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4893                 mutex_unlock(&dev_priv->rps.hw_lock);
4894                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4895                 if (intel_wait_for_register(dev_priv,
4896                                             IPS_CTL, IPS_ENABLE, 0,
4897                                             42))
4898                         DRM_ERROR("Timed out waiting for IPS disable\n");
4899         } else {
4900                 I915_WRITE(IPS_CTL, 0);
4901                 POSTING_READ(IPS_CTL);
4902         }
4903
4904         /* We need to wait for a vblank before we can disable the plane. */
4905         intel_wait_for_vblank(dev, crtc->pipe);
4906 }
4907
4908 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4909 {
4910         if (intel_crtc->overlay) {
4911                 struct drm_device *dev = intel_crtc->base.dev;
4912                 struct drm_i915_private *dev_priv = to_i915(dev);
4913
4914                 mutex_lock(&dev->struct_mutex);
4915                 dev_priv->mm.interruptible = false;
4916                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4917                 dev_priv->mm.interruptible = true;
4918                 mutex_unlock(&dev->struct_mutex);
4919         }
4920
4921         /* Let userspace switch the overlay on again. In most cases userspace
4922          * has to recompute where to put it anyway.
4923          */
4924 }
4925
4926 /**
4927  * intel_post_enable_primary - Perform operations after enabling primary plane
4928  * @crtc: the CRTC whose primary plane was just enabled
4929  *
4930  * Performs potentially sleeping operations that must be done after the primary
4931  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4932  * called due to an explicit primary plane update, or due to an implicit
4933  * re-enable that is caused when a sprite plane is updated to no longer
4934  * completely hide the primary plane.
4935  */
4936 static void
4937 intel_post_enable_primary(struct drm_crtc *crtc)
4938 {
4939         struct drm_device *dev = crtc->dev;
4940         struct drm_i915_private *dev_priv = to_i915(dev);
4941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942         int pipe = intel_crtc->pipe;
4943
4944         /*
4945          * FIXME IPS should be fine as long as one plane is
4946          * enabled, but in practice it seems to have problems
4947          * when going from primary only to sprite only and vice
4948          * versa.
4949          */
4950         hsw_enable_ips(intel_crtc);
4951
4952         /*
4953          * Gen2 reports pipe underruns whenever all planes are disabled.
4954          * So don't enable underrun reporting before at least some planes
4955          * are enabled.
4956          * FIXME: Need to fix the logic to work when we turn off all planes
4957          * but leave the pipe running.
4958          */
4959         if (IS_GEN2(dev))
4960                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4961
4962         /* Underruns don't always raise interrupts, so check manually. */
4963         intel_check_cpu_fifo_underruns(dev_priv);
4964         intel_check_pch_fifo_underruns(dev_priv);
4965 }
4966
4967 /* FIXME move all this to pre_plane_update() with proper state tracking */
4968 static void
4969 intel_pre_disable_primary(struct drm_crtc *crtc)
4970 {
4971         struct drm_device *dev = crtc->dev;
4972         struct drm_i915_private *dev_priv = to_i915(dev);
4973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974         int pipe = intel_crtc->pipe;
4975
4976         /*
4977          * Gen2 reports pipe underruns whenever all planes are disabled.
4978          * So diasble underrun reporting before all the planes get disabled.
4979          * FIXME: Need to fix the logic to work when we turn off all planes
4980          * but leave the pipe running.
4981          */
4982         if (IS_GEN2(dev))
4983                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4984
4985         /*
4986          * FIXME IPS should be fine as long as one plane is
4987          * enabled, but in practice it seems to have problems
4988          * when going from primary only to sprite only and vice
4989          * versa.
4990          */
4991         hsw_disable_ips(intel_crtc);
4992 }
4993
4994 /* FIXME get rid of this and use pre_plane_update */
4995 static void
4996 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4997 {
4998         struct drm_device *dev = crtc->dev;
4999         struct drm_i915_private *dev_priv = to_i915(dev);
5000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5001         int pipe = intel_crtc->pipe;
5002
5003         intel_pre_disable_primary(crtc);
5004
5005         /*
5006          * Vblank time updates from the shadow to live plane control register
5007          * are blocked if the memory self-refresh mode is active at that
5008          * moment. So to make sure the plane gets truly disabled, disable
5009          * first the self-refresh mode. The self-refresh enable bit in turn
5010          * will be checked/applied by the HW only at the next frame start
5011          * event which is after the vblank start event, so we need to have a
5012          * wait-for-vblank between disabling the plane and the pipe.
5013          */
5014         if (HAS_GMCH_DISPLAY(dev)) {
5015                 intel_set_memory_cxsr(dev_priv, false);
5016                 dev_priv->wm.vlv.cxsr = false;
5017                 intel_wait_for_vblank(dev, pipe);
5018         }
5019 }
5020
5021 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5022 {
5023         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5024         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5025         struct intel_crtc_state *pipe_config =
5026                 to_intel_crtc_state(crtc->base.state);
5027         struct drm_plane *primary = crtc->base.primary;
5028         struct drm_plane_state *old_pri_state =
5029                 drm_atomic_get_existing_plane_state(old_state, primary);
5030
5031         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5032
5033         crtc->wm.cxsr_allowed = true;
5034
5035         if (pipe_config->update_wm_post && pipe_config->base.active)
5036                 intel_update_watermarks(&crtc->base);
5037
5038         if (old_pri_state) {
5039                 struct intel_plane_state *primary_state =
5040                         to_intel_plane_state(primary->state);
5041                 struct intel_plane_state *old_primary_state =
5042                         to_intel_plane_state(old_pri_state);
5043
5044                 intel_fbc_post_update(crtc);
5045
5046                 if (primary_state->base.visible &&
5047                     (needs_modeset(&pipe_config->base) ||
5048                      !old_primary_state->base.visible))
5049                         intel_post_enable_primary(&crtc->base);
5050         }
5051 }
5052
5053 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5054 {
5055         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5056         struct drm_device *dev = crtc->base.dev;
5057         struct drm_i915_private *dev_priv = to_i915(dev);
5058         struct intel_crtc_state *pipe_config =
5059                 to_intel_crtc_state(crtc->base.state);
5060         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5061         struct drm_plane *primary = crtc->base.primary;
5062         struct drm_plane_state *old_pri_state =
5063                 drm_atomic_get_existing_plane_state(old_state, primary);
5064         bool modeset = needs_modeset(&pipe_config->base);
5065
5066         if (old_pri_state) {
5067                 struct intel_plane_state *primary_state =
5068                         to_intel_plane_state(primary->state);
5069                 struct intel_plane_state *old_primary_state =
5070                         to_intel_plane_state(old_pri_state);
5071
5072                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5073
5074                 if (old_primary_state->base.visible &&
5075                     (modeset || !primary_state->base.visible))
5076                         intel_pre_disable_primary(&crtc->base);
5077         }
5078
5079         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5080                 crtc->wm.cxsr_allowed = false;
5081
5082                 /*
5083                  * Vblank time updates from the shadow to live plane control register
5084                  * are blocked if the memory self-refresh mode is active at that
5085                  * moment. So to make sure the plane gets truly disabled, disable
5086                  * first the self-refresh mode. The self-refresh enable bit in turn
5087                  * will be checked/applied by the HW only at the next frame start
5088                  * event which is after the vblank start event, so we need to have a
5089                  * wait-for-vblank between disabling the plane and the pipe.
5090                  */
5091                 if (old_crtc_state->base.active) {
5092                         intel_set_memory_cxsr(dev_priv, false);
5093                         dev_priv->wm.vlv.cxsr = false;
5094                         intel_wait_for_vblank(dev, crtc->pipe);
5095                 }
5096         }
5097
5098         /*
5099          * IVB workaround: must disable low power watermarks for at least
5100          * one frame before enabling scaling.  LP watermarks can be re-enabled
5101          * when scaling is disabled.
5102          *
5103          * WaCxSRDisabledForSpriteScaling:ivb
5104          */
5105         if (pipe_config->disable_lp_wm) {
5106                 ilk_disable_lp_wm(dev);
5107                 intel_wait_for_vblank(dev, crtc->pipe);
5108         }
5109
5110         /*
5111          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5112          * watermark programming here.
5113          */
5114         if (needs_modeset(&pipe_config->base))
5115                 return;
5116
5117         /*
5118          * For platforms that support atomic watermarks, program the
5119          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5120          * will be the intermediate values that are safe for both pre- and
5121          * post- vblank; when vblank happens, the 'active' values will be set
5122          * to the final 'target' values and we'll do this again to get the
5123          * optimal watermarks.  For gen9+ platforms, the values we program here
5124          * will be the final target values which will get automatically latched
5125          * at vblank time; no further programming will be necessary.
5126          *
5127          * If a platform hasn't been transitioned to atomic watermarks yet,
5128          * we'll continue to update watermarks the old way, if flags tell
5129          * us to.
5130          */
5131         if (dev_priv->display.initial_watermarks != NULL)
5132                 dev_priv->display.initial_watermarks(pipe_config);
5133         else if (pipe_config->update_wm_pre)
5134                 intel_update_watermarks(&crtc->base);
5135 }
5136
5137 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5138 {
5139         struct drm_device *dev = crtc->dev;
5140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5141         struct drm_plane *p;
5142         int pipe = intel_crtc->pipe;
5143
5144         intel_crtc_dpms_overlay_disable(intel_crtc);
5145
5146         drm_for_each_plane_mask(p, dev, plane_mask)
5147                 to_intel_plane(p)->disable_plane(p, crtc);
5148
5149         /*
5150          * FIXME: Once we grow proper nuclear flip support out of this we need
5151          * to compute the mask of flip planes precisely. For the time being
5152          * consider this a flip to a NULL plane.
5153          */
5154         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5155 }
5156
5157 static void ironlake_crtc_enable(struct drm_crtc *crtc)
5158 {
5159         struct drm_device *dev = crtc->dev;
5160         struct drm_i915_private *dev_priv = to_i915(dev);
5161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5162         struct intel_encoder *encoder;
5163         int pipe = intel_crtc->pipe;
5164         struct intel_crtc_state *pipe_config =
5165                 to_intel_crtc_state(crtc->state);
5166
5167         if (WARN_ON(intel_crtc->active))
5168                 return;
5169
5170         /*
5171          * Sometimes spurious CPU pipe underruns happen during FDI
5172          * training, at least with VGA+HDMI cloning. Suppress them.
5173          *
5174          * On ILK we get an occasional spurious CPU pipe underruns
5175          * between eDP port A enable and vdd enable. Also PCH port
5176          * enable seems to result in the occasional CPU pipe underrun.
5177          *
5178          * Spurious PCH underruns also occur during PCH enabling.
5179          */
5180         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5181                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5182         if (intel_crtc->config->has_pch_encoder)
5183                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5184
5185         if (intel_crtc->config->has_pch_encoder)
5186                 intel_prepare_shared_dpll(intel_crtc);
5187
5188         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5189                 intel_dp_set_m_n(intel_crtc, M1_N1);
5190
5191         intel_set_pipe_timings(intel_crtc);
5192         intel_set_pipe_src_size(intel_crtc);
5193
5194         if (intel_crtc->config->has_pch_encoder) {
5195                 intel_cpu_transcoder_set_m_n(intel_crtc,
5196                                      &intel_crtc->config->fdi_m_n, NULL);
5197         }
5198
5199         ironlake_set_pipeconf(crtc);
5200
5201         intel_crtc->active = true;
5202
5203         for_each_encoder_on_crtc(dev, crtc, encoder)
5204                 if (encoder->pre_enable)
5205                         encoder->pre_enable(encoder);
5206
5207         if (intel_crtc->config->has_pch_encoder) {
5208                 /* Note: FDI PLL enabling _must_ be done before we enable the
5209                  * cpu pipes, hence this is separate from all the other fdi/pch
5210                  * enabling. */
5211                 ironlake_fdi_pll_enable(intel_crtc);
5212         } else {
5213                 assert_fdi_tx_disabled(dev_priv, pipe);
5214                 assert_fdi_rx_disabled(dev_priv, pipe);
5215         }
5216
5217         ironlake_pfit_enable(intel_crtc);
5218
5219         /*
5220          * On ILK+ LUT must be loaded before the pipe is running but with
5221          * clocks enabled
5222          */
5223         intel_color_load_luts(&pipe_config->base);
5224
5225         if (dev_priv->display.initial_watermarks != NULL)
5226                 dev_priv->display.initial_watermarks(intel_crtc->config);
5227         intel_enable_pipe(intel_crtc);
5228
5229         if (intel_crtc->config->has_pch_encoder)
5230                 ironlake_pch_enable(crtc);
5231
5232         assert_vblank_disabled(crtc);
5233         drm_crtc_vblank_on(crtc);
5234
5235         for_each_encoder_on_crtc(dev, crtc, encoder)
5236                 encoder->enable(encoder);
5237
5238         if (HAS_PCH_CPT(dev))
5239                 cpt_verify_modeset(dev, intel_crtc->pipe);
5240
5241         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5242         if (intel_crtc->config->has_pch_encoder)
5243                 intel_wait_for_vblank(dev, pipe);
5244         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5245         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5246 }
5247
5248 /* IPS only exists on ULT machines and is tied to pipe A. */
5249 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5250 {
5251         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5252 }
5253
5254 static void haswell_crtc_enable(struct drm_crtc *crtc)
5255 {
5256         struct drm_device *dev = crtc->dev;
5257         struct drm_i915_private *dev_priv = to_i915(dev);
5258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5259         struct intel_encoder *encoder;
5260         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5261         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5262         struct intel_crtc_state *pipe_config =
5263                 to_intel_crtc_state(crtc->state);
5264
5265         if (WARN_ON(intel_crtc->active))
5266                 return;
5267
5268         if (intel_crtc->config->has_pch_encoder)
5269                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5270                                                       false);
5271
5272         for_each_encoder_on_crtc(dev, crtc, encoder)
5273                 if (encoder->pre_pll_enable)
5274                         encoder->pre_pll_enable(encoder);
5275
5276         if (intel_crtc->config->shared_dpll)
5277                 intel_enable_shared_dpll(intel_crtc);
5278
5279         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5280                 intel_dp_set_m_n(intel_crtc, M1_N1);
5281
5282         if (!transcoder_is_dsi(cpu_transcoder))
5283                 intel_set_pipe_timings(intel_crtc);
5284
5285         intel_set_pipe_src_size(intel_crtc);
5286
5287         if (cpu_transcoder != TRANSCODER_EDP &&
5288             !transcoder_is_dsi(cpu_transcoder)) {
5289                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5290                            intel_crtc->config->pixel_multiplier - 1);
5291         }
5292
5293         if (intel_crtc->config->has_pch_encoder) {
5294                 intel_cpu_transcoder_set_m_n(intel_crtc,
5295                                      &intel_crtc->config->fdi_m_n, NULL);
5296         }
5297
5298         if (!transcoder_is_dsi(cpu_transcoder))
5299                 haswell_set_pipeconf(crtc);
5300
5301         haswell_set_pipemisc(crtc);
5302
5303         intel_color_set_csc(&pipe_config->base);
5304
5305         intel_crtc->active = true;
5306
5307         if (intel_crtc->config->has_pch_encoder)
5308                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5309         else
5310                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5311
5312         for_each_encoder_on_crtc(dev, crtc, encoder) {
5313                 if (encoder->pre_enable)
5314                         encoder->pre_enable(encoder);
5315         }
5316
5317         if (intel_crtc->config->has_pch_encoder)
5318                 dev_priv->display.fdi_link_train(crtc);
5319
5320         if (!transcoder_is_dsi(cpu_transcoder))
5321                 intel_ddi_enable_pipe_clock(intel_crtc);
5322
5323         if (INTEL_INFO(dev)->gen >= 9)
5324                 skylake_pfit_enable(intel_crtc);
5325         else
5326                 ironlake_pfit_enable(intel_crtc);
5327
5328         /*
5329          * On ILK+ LUT must be loaded before the pipe is running but with
5330          * clocks enabled
5331          */
5332         intel_color_load_luts(&pipe_config->base);
5333
5334         intel_ddi_set_pipe_settings(crtc);
5335         if (!transcoder_is_dsi(cpu_transcoder))
5336                 intel_ddi_enable_transcoder_func(crtc);
5337
5338         if (dev_priv->display.initial_watermarks != NULL)
5339                 dev_priv->display.initial_watermarks(pipe_config);
5340         else
5341                 intel_update_watermarks(crtc);
5342
5343         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5344         if (!transcoder_is_dsi(cpu_transcoder))
5345                 intel_enable_pipe(intel_crtc);
5346
5347         if (intel_crtc->config->has_pch_encoder)
5348                 lpt_pch_enable(crtc);
5349
5350         if (intel_crtc->config->dp_encoder_is_mst)
5351                 intel_ddi_set_vc_payload_alloc(crtc, true);
5352
5353         assert_vblank_disabled(crtc);
5354         drm_crtc_vblank_on(crtc);
5355
5356         for_each_encoder_on_crtc(dev, crtc, encoder) {
5357                 encoder->enable(encoder);
5358                 intel_opregion_notify_encoder(encoder, true);
5359         }
5360
5361         if (intel_crtc->config->has_pch_encoder) {
5362                 intel_wait_for_vblank(dev, pipe);
5363                 intel_wait_for_vblank(dev, pipe);
5364                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5365                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5366                                                       true);
5367         }
5368
5369         /* If we change the relative order between pipe/planes enabling, we need
5370          * to change the workaround. */
5371         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5372         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5373                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5374                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5375         }
5376 }
5377
5378 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5379 {
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_i915_private *dev_priv = to_i915(dev);
5382         int pipe = crtc->pipe;
5383
5384         /* To avoid upsetting the power well on haswell only disable the pfit if
5385          * it's in use. The hw state code will make sure we get this right. */
5386         if (force || crtc->config->pch_pfit.enabled) {
5387                 I915_WRITE(PF_CTL(pipe), 0);
5388                 I915_WRITE(PF_WIN_POS(pipe), 0);
5389                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5390         }
5391 }
5392
5393 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5394 {
5395         struct drm_device *dev = crtc->dev;
5396         struct drm_i915_private *dev_priv = to_i915(dev);
5397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5398         struct intel_encoder *encoder;
5399         int pipe = intel_crtc->pipe;
5400
5401         /*
5402          * Sometimes spurious CPU pipe underruns happen when the
5403          * pipe is already disabled, but FDI RX/TX is still enabled.
5404          * Happens at least with VGA+HDMI cloning. Suppress them.
5405          */
5406         if (intel_crtc->config->has_pch_encoder) {
5407                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5408                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5409         }
5410
5411         for_each_encoder_on_crtc(dev, crtc, encoder)
5412                 encoder->disable(encoder);
5413
5414         drm_crtc_vblank_off(crtc);
5415         assert_vblank_disabled(crtc);
5416
5417         intel_disable_pipe(intel_crtc);
5418
5419         ironlake_pfit_disable(intel_crtc, false);
5420
5421         if (intel_crtc->config->has_pch_encoder)
5422                 ironlake_fdi_disable(crtc);
5423
5424         for_each_encoder_on_crtc(dev, crtc, encoder)
5425                 if (encoder->post_disable)
5426                         encoder->post_disable(encoder);
5427
5428         if (intel_crtc->config->has_pch_encoder) {
5429                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5430
5431                 if (HAS_PCH_CPT(dev)) {
5432                         i915_reg_t reg;
5433                         u32 temp;
5434
5435                         /* disable TRANS_DP_CTL */
5436                         reg = TRANS_DP_CTL(pipe);
5437                         temp = I915_READ(reg);
5438                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5439                                   TRANS_DP_PORT_SEL_MASK);
5440                         temp |= TRANS_DP_PORT_SEL_NONE;
5441                         I915_WRITE(reg, temp);
5442
5443                         /* disable DPLL_SEL */
5444                         temp = I915_READ(PCH_DPLL_SEL);
5445                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5446                         I915_WRITE(PCH_DPLL_SEL, temp);
5447                 }
5448
5449                 ironlake_fdi_pll_disable(intel_crtc);
5450         }
5451
5452         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5453         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5454 }
5455
5456 static void haswell_crtc_disable(struct drm_crtc *crtc)
5457 {
5458         struct drm_device *dev = crtc->dev;
5459         struct drm_i915_private *dev_priv = to_i915(dev);
5460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5461         struct intel_encoder *encoder;
5462         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5463
5464         if (intel_crtc->config->has_pch_encoder)
5465                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5466                                                       false);
5467
5468         for_each_encoder_on_crtc(dev, crtc, encoder) {
5469                 intel_opregion_notify_encoder(encoder, false);
5470                 encoder->disable(encoder);
5471         }
5472
5473         drm_crtc_vblank_off(crtc);
5474         assert_vblank_disabled(crtc);
5475
5476         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5477         if (!transcoder_is_dsi(cpu_transcoder))
5478                 intel_disable_pipe(intel_crtc);
5479
5480         if (intel_crtc->config->dp_encoder_is_mst)
5481                 intel_ddi_set_vc_payload_alloc(crtc, false);
5482
5483         if (!transcoder_is_dsi(cpu_transcoder))
5484                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5485
5486         if (INTEL_INFO(dev)->gen >= 9)
5487                 skylake_scaler_disable(intel_crtc);
5488         else
5489                 ironlake_pfit_disable(intel_crtc, false);
5490
5491         if (!transcoder_is_dsi(cpu_transcoder))
5492                 intel_ddi_disable_pipe_clock(intel_crtc);
5493
5494         for_each_encoder_on_crtc(dev, crtc, encoder)
5495                 if (encoder->post_disable)
5496                         encoder->post_disable(encoder);
5497
5498         if (intel_crtc->config->has_pch_encoder) {
5499                 lpt_disable_pch_transcoder(dev_priv);
5500                 lpt_disable_iclkip(dev_priv);
5501                 intel_ddi_fdi_disable(crtc);
5502
5503                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5504                                                       true);
5505         }
5506 }
5507
5508 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5509 {
5510         struct drm_device *dev = crtc->base.dev;
5511         struct drm_i915_private *dev_priv = to_i915(dev);
5512         struct intel_crtc_state *pipe_config = crtc->config;
5513
5514         if (!pipe_config->gmch_pfit.control)
5515                 return;
5516
5517         /*
5518          * The panel fitter should only be adjusted whilst the pipe is disabled,
5519          * according to register description and PRM.
5520          */
5521         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5522         assert_pipe_disabled(dev_priv, crtc->pipe);
5523
5524         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5525         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5526
5527         /* Border color in case we don't scale up to the full screen. Black by
5528          * default, change to something else for debugging. */
5529         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5530 }
5531
5532 static enum intel_display_power_domain port_to_power_domain(enum port port)
5533 {
5534         switch (port) {
5535         case PORT_A:
5536                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5537         case PORT_B:
5538                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5539         case PORT_C:
5540                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5541         case PORT_D:
5542                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5543         case PORT_E:
5544                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5545         default:
5546                 MISSING_CASE(port);
5547                 return POWER_DOMAIN_PORT_OTHER;
5548         }
5549 }
5550
5551 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5552 {
5553         switch (port) {
5554         case PORT_A:
5555                 return POWER_DOMAIN_AUX_A;
5556         case PORT_B:
5557                 return POWER_DOMAIN_AUX_B;
5558         case PORT_C:
5559                 return POWER_DOMAIN_AUX_C;
5560         case PORT_D:
5561                 return POWER_DOMAIN_AUX_D;
5562         case PORT_E:
5563                 /* FIXME: Check VBT for actual wiring of PORT E */
5564                 return POWER_DOMAIN_AUX_D;
5565         default:
5566                 MISSING_CASE(port);
5567                 return POWER_DOMAIN_AUX_A;
5568         }
5569 }
5570
5571 enum intel_display_power_domain
5572 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5573 {
5574         struct drm_device *dev = intel_encoder->base.dev;
5575         struct intel_digital_port *intel_dig_port;
5576
5577         switch (intel_encoder->type) {
5578         case INTEL_OUTPUT_UNKNOWN:
5579                 /* Only DDI platforms should ever use this output type */
5580                 WARN_ON_ONCE(!HAS_DDI(dev));
5581         case INTEL_OUTPUT_DP:
5582         case INTEL_OUTPUT_HDMI:
5583         case INTEL_OUTPUT_EDP:
5584                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5585                 return port_to_power_domain(intel_dig_port->port);
5586         case INTEL_OUTPUT_DP_MST:
5587                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5588                 return port_to_power_domain(intel_dig_port->port);
5589         case INTEL_OUTPUT_ANALOG:
5590                 return POWER_DOMAIN_PORT_CRT;
5591         case INTEL_OUTPUT_DSI:
5592                 return POWER_DOMAIN_PORT_DSI;
5593         default:
5594                 return POWER_DOMAIN_PORT_OTHER;
5595         }
5596 }
5597
5598 enum intel_display_power_domain
5599 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5600 {
5601         struct drm_device *dev = intel_encoder->base.dev;
5602         struct intel_digital_port *intel_dig_port;
5603
5604         switch (intel_encoder->type) {
5605         case INTEL_OUTPUT_UNKNOWN:
5606         case INTEL_OUTPUT_HDMI:
5607                 /*
5608                  * Only DDI platforms should ever use these output types.
5609                  * We can get here after the HDMI detect code has already set
5610                  * the type of the shared encoder. Since we can't be sure
5611                  * what's the status of the given connectors, play safe and
5612                  * run the DP detection too.
5613                  */
5614                 WARN_ON_ONCE(!HAS_DDI(dev));
5615         case INTEL_OUTPUT_DP:
5616         case INTEL_OUTPUT_EDP:
5617                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5618                 return port_to_aux_power_domain(intel_dig_port->port);
5619         case INTEL_OUTPUT_DP_MST:
5620                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5621                 return port_to_aux_power_domain(intel_dig_port->port);
5622         default:
5623                 MISSING_CASE(intel_encoder->type);
5624                 return POWER_DOMAIN_AUX_A;
5625         }
5626 }
5627
5628 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5629                                             struct intel_crtc_state *crtc_state)
5630 {
5631         struct drm_device *dev = crtc->dev;
5632         struct drm_encoder *encoder;
5633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5634         enum pipe pipe = intel_crtc->pipe;
5635         unsigned long mask;
5636         enum transcoder transcoder = crtc_state->cpu_transcoder;
5637
5638         if (!crtc_state->base.active)
5639                 return 0;
5640
5641         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5642         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5643         if (crtc_state->pch_pfit.enabled ||
5644             crtc_state->pch_pfit.force_thru)
5645                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5646
5647         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5648                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5649
5650                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5651         }
5652
5653         if (crtc_state->shared_dpll)
5654                 mask |= BIT(POWER_DOMAIN_PLLS);
5655
5656         return mask;
5657 }
5658
5659 static unsigned long
5660 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5661                                struct intel_crtc_state *crtc_state)
5662 {
5663         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5665         enum intel_display_power_domain domain;
5666         unsigned long domains, new_domains, old_domains;
5667
5668         old_domains = intel_crtc->enabled_power_domains;
5669         intel_crtc->enabled_power_domains = new_domains =
5670                 get_crtc_power_domains(crtc, crtc_state);
5671
5672         domains = new_domains & ~old_domains;
5673
5674         for_each_power_domain(domain, domains)
5675                 intel_display_power_get(dev_priv, domain);
5676
5677         return old_domains & ~new_domains;
5678 }
5679
5680 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5681                                       unsigned long domains)
5682 {
5683         enum intel_display_power_domain domain;
5684
5685         for_each_power_domain(domain, domains)
5686                 intel_display_power_put(dev_priv, domain);
5687 }
5688
5689 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5690 {
5691         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5692
5693         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5694             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5695                 return max_cdclk_freq;
5696         else if (IS_CHERRYVIEW(dev_priv))
5697                 return max_cdclk_freq*95/100;
5698         else if (INTEL_INFO(dev_priv)->gen < 4)
5699                 return 2*max_cdclk_freq*90/100;
5700         else
5701                 return max_cdclk_freq*90/100;
5702 }
5703
5704 static int skl_calc_cdclk(int max_pixclk, int vco);
5705
5706 static void intel_update_max_cdclk(struct drm_device *dev)
5707 {
5708         struct drm_i915_private *dev_priv = to_i915(dev);
5709
5710         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5711                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5712                 int max_cdclk, vco;
5713
5714                 vco = dev_priv->skl_preferred_vco_freq;
5715                 WARN_ON(vco != 8100000 && vco != 8640000);
5716
5717                 /*
5718                  * Use the lower (vco 8640) cdclk values as a
5719                  * first guess. skl_calc_cdclk() will correct it
5720                  * if the preferred vco is 8100 instead.
5721                  */
5722                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5723                         max_cdclk = 617143;
5724                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5725                         max_cdclk = 540000;
5726                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5727                         max_cdclk = 432000;
5728                 else
5729                         max_cdclk = 308571;
5730
5731                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5732         } else if (IS_BROXTON(dev)) {
5733                 dev_priv->max_cdclk_freq = 624000;
5734         } else if (IS_BROADWELL(dev))  {
5735                 /*
5736                  * FIXME with extra cooling we can allow
5737                  * 540 MHz for ULX and 675 Mhz for ULT.
5738                  * How can we know if extra cooling is
5739                  * available? PCI ID, VTB, something else?
5740                  */
5741                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5742                         dev_priv->max_cdclk_freq = 450000;
5743                 else if (IS_BDW_ULX(dev))
5744                         dev_priv->max_cdclk_freq = 450000;
5745                 else if (IS_BDW_ULT(dev))
5746                         dev_priv->max_cdclk_freq = 540000;
5747                 else
5748                         dev_priv->max_cdclk_freq = 675000;
5749         } else if (IS_CHERRYVIEW(dev)) {
5750                 dev_priv->max_cdclk_freq = 320000;
5751         } else if (IS_VALLEYVIEW(dev)) {
5752                 dev_priv->max_cdclk_freq = 400000;
5753         } else {
5754                 /* otherwise assume cdclk is fixed */
5755                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5756         }
5757
5758         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5759
5760         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5761                          dev_priv->max_cdclk_freq);
5762
5763         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5764                          dev_priv->max_dotclk_freq);
5765 }
5766
5767 static void intel_update_cdclk(struct drm_device *dev)
5768 {
5769         struct drm_i915_private *dev_priv = to_i915(dev);
5770
5771         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5772
5773         if (INTEL_GEN(dev_priv) >= 9)
5774                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5775                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5776                                  dev_priv->cdclk_pll.ref);
5777         else
5778                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5779                                  dev_priv->cdclk_freq);
5780
5781         /*
5782          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5783          * Programmng [sic] note: bit[9:2] should be programmed to the number
5784          * of cdclk that generates 4MHz reference clock freq which is used to
5785          * generate GMBus clock. This will vary with the cdclk freq.
5786          */
5787         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5788                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5789 }
5790
5791 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5792 static int skl_cdclk_decimal(int cdclk)
5793 {
5794         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5795 }
5796
5797 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5798 {
5799         int ratio;
5800
5801         if (cdclk == dev_priv->cdclk_pll.ref)
5802                 return 0;
5803
5804         switch (cdclk) {
5805         default:
5806                 MISSING_CASE(cdclk);
5807         case 144000:
5808         case 288000:
5809         case 384000:
5810         case 576000:
5811                 ratio = 60;
5812                 break;
5813         case 624000:
5814                 ratio = 65;
5815                 break;
5816         }
5817
5818         return dev_priv->cdclk_pll.ref * ratio;
5819 }
5820
5821 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5822 {
5823         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5824
5825         /* Timeout 200us */
5826         if (intel_wait_for_register(dev_priv,
5827                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5828                                     1))
5829                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5830
5831         dev_priv->cdclk_pll.vco = 0;
5832 }
5833
5834 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5835 {
5836         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5837         u32 val;
5838
5839         val = I915_READ(BXT_DE_PLL_CTL);
5840         val &= ~BXT_DE_PLL_RATIO_MASK;
5841         val |= BXT_DE_PLL_RATIO(ratio);
5842         I915_WRITE(BXT_DE_PLL_CTL, val);
5843
5844         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5845
5846         /* Timeout 200us */
5847         if (intel_wait_for_register(dev_priv,
5848                                     BXT_DE_PLL_ENABLE,
5849                                     BXT_DE_PLL_LOCK,
5850                                     BXT_DE_PLL_LOCK,
5851                                     1))
5852                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5853
5854         dev_priv->cdclk_pll.vco = vco;
5855 }
5856
5857 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5858 {
5859         u32 val, divider;
5860         int vco, ret;
5861
5862         vco = bxt_de_pll_vco(dev_priv, cdclk);
5863
5864         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5865
5866         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5867         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5868         case 8:
5869                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5870                 break;
5871         case 4:
5872                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5873                 break;
5874         case 3:
5875                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5876                 break;
5877         case 2:
5878                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5879                 break;
5880         default:
5881                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5882                 WARN_ON(vco != 0);
5883
5884                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5885                 break;
5886         }
5887
5888         /* Inform power controller of upcoming frequency change */
5889         mutex_lock(&dev_priv->rps.hw_lock);
5890         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5891                                       0x80000000);
5892         mutex_unlock(&dev_priv->rps.hw_lock);
5893
5894         if (ret) {
5895                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5896                           ret, cdclk);
5897                 return;
5898         }
5899
5900         if (dev_priv->cdclk_pll.vco != 0 &&
5901             dev_priv->cdclk_pll.vco != vco)
5902                 bxt_de_pll_disable(dev_priv);
5903
5904         if (dev_priv->cdclk_pll.vco != vco)
5905                 bxt_de_pll_enable(dev_priv, vco);
5906
5907         val = divider | skl_cdclk_decimal(cdclk);
5908         /*
5909          * FIXME if only the cd2x divider needs changing, it could be done
5910          * without shutting off the pipe (if only one pipe is active).
5911          */
5912         val |= BXT_CDCLK_CD2X_PIPE_NONE;
5913         /*
5914          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5915          * enable otherwise.
5916          */
5917         if (cdclk >= 500000)
5918                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5919         I915_WRITE(CDCLK_CTL, val);
5920
5921         mutex_lock(&dev_priv->rps.hw_lock);
5922         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5923                                       DIV_ROUND_UP(cdclk, 25000));
5924         mutex_unlock(&dev_priv->rps.hw_lock);
5925
5926         if (ret) {
5927                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5928                           ret, cdclk);
5929                 return;
5930         }
5931
5932         intel_update_cdclk(&dev_priv->drm);
5933 }
5934
5935 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5936 {
5937         u32 cdctl, expected;
5938
5939         intel_update_cdclk(&dev_priv->drm);
5940
5941         if (dev_priv->cdclk_pll.vco == 0 ||
5942             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5943                 goto sanitize;
5944
5945         /* DPLL okay; verify the cdclock
5946          *
5947          * Some BIOS versions leave an incorrect decimal frequency value and
5948          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5949          * so sanitize this register.
5950          */
5951         cdctl = I915_READ(CDCLK_CTL);
5952         /*
5953          * Let's ignore the pipe field, since BIOS could have configured the
5954          * dividers both synching to an active pipe, or asynchronously
5955          * (PIPE_NONE).
5956          */
5957         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5958
5959         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5960                    skl_cdclk_decimal(dev_priv->cdclk_freq);
5961         /*
5962          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5963          * enable otherwise.
5964          */
5965         if (dev_priv->cdclk_freq >= 500000)
5966                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5967
5968         if (cdctl == expected)
5969                 /* All well; nothing to sanitize */
5970                 return;
5971
5972 sanitize:
5973         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5974
5975         /* force cdclk programming */
5976         dev_priv->cdclk_freq = 0;
5977
5978         /* force full PLL disable + enable */
5979         dev_priv->cdclk_pll.vco = -1;
5980 }
5981
5982 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5983 {
5984         bxt_sanitize_cdclk(dev_priv);
5985
5986         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5987                 return;
5988
5989         /*
5990          * FIXME:
5991          * - The initial CDCLK needs to be read from VBT.
5992          *   Need to make this change after VBT has changes for BXT.
5993          */
5994         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5995 }
5996
5997 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5998 {
5999         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6000 }
6001
6002 static int skl_calc_cdclk(int max_pixclk, int vco)
6003 {
6004         if (vco == 8640000) {
6005                 if (max_pixclk > 540000)
6006                         return 617143;
6007                 else if (max_pixclk > 432000)
6008                         return 540000;
6009                 else if (max_pixclk > 308571)
6010                         return 432000;
6011                 else
6012                         return 308571;
6013         } else {
6014                 if (max_pixclk > 540000)
6015                         return 675000;
6016                 else if (max_pixclk > 450000)
6017                         return 540000;
6018                 else if (max_pixclk > 337500)
6019                         return 450000;
6020                 else
6021                         return 337500;
6022         }
6023 }
6024
6025 static void
6026 skl_dpll0_update(struct drm_i915_private *dev_priv)
6027 {
6028         u32 val;
6029
6030         dev_priv->cdclk_pll.ref = 24000;
6031         dev_priv->cdclk_pll.vco = 0;
6032
6033         val = I915_READ(LCPLL1_CTL);
6034         if ((val & LCPLL_PLL_ENABLE) == 0)
6035                 return;
6036
6037         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6038                 return;
6039
6040         val = I915_READ(DPLL_CTRL1);
6041
6042         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6043                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6044                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6045                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6046                 return;
6047
6048         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6049         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6050         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6051         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6052         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6053                 dev_priv->cdclk_pll.vco = 8100000;
6054                 break;
6055         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6056         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6057                 dev_priv->cdclk_pll.vco = 8640000;
6058                 break;
6059         default:
6060                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6061                 break;
6062         }
6063 }
6064
6065 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6066 {
6067         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6068
6069         dev_priv->skl_preferred_vco_freq = vco;
6070
6071         if (changed)
6072                 intel_update_max_cdclk(&dev_priv->drm);
6073 }
6074
6075 static void
6076 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6077 {
6078         int min_cdclk = skl_calc_cdclk(0, vco);
6079         u32 val;
6080
6081         WARN_ON(vco != 8100000 && vco != 8640000);
6082
6083         /* select the minimum CDCLK before enabling DPLL 0 */
6084         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6085         I915_WRITE(CDCLK_CTL, val);
6086         POSTING_READ(CDCLK_CTL);
6087
6088         /*
6089          * We always enable DPLL0 with the lowest link rate possible, but still
6090          * taking into account the VCO required to operate the eDP panel at the
6091          * desired frequency. The usual DP link rates operate with a VCO of
6092          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6093          * The modeset code is responsible for the selection of the exact link
6094          * rate later on, with the constraint of choosing a frequency that
6095          * works with vco.
6096          */
6097         val = I915_READ(DPLL_CTRL1);
6098
6099         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6100                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6101         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6102         if (vco == 8640000)
6103                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6104                                             SKL_DPLL0);
6105         else
6106                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6107                                             SKL_DPLL0);
6108
6109         I915_WRITE(DPLL_CTRL1, val);
6110         POSTING_READ(DPLL_CTRL1);
6111
6112         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6113
6114         if (intel_wait_for_register(dev_priv,
6115                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6116                                     5))
6117                 DRM_ERROR("DPLL0 not locked\n");
6118
6119         dev_priv->cdclk_pll.vco = vco;
6120
6121         /* We'll want to keep using the current vco from now on. */
6122         skl_set_preferred_cdclk_vco(dev_priv, vco);
6123 }
6124
6125 static void
6126 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6127 {
6128         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6129         if (intel_wait_for_register(dev_priv,
6130                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6131                                    1))
6132                 DRM_ERROR("Couldn't disable DPLL0\n");
6133
6134         dev_priv->cdclk_pll.vco = 0;
6135 }
6136
6137 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6138 {
6139         int ret;
6140         u32 val;
6141
6142         /* inform PCU we want to change CDCLK */
6143         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6144         mutex_lock(&dev_priv->rps.hw_lock);
6145         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6146         mutex_unlock(&dev_priv->rps.hw_lock);
6147
6148         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6149 }
6150
6151 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6152 {
6153         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6154 }
6155
6156 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6157 {
6158         struct drm_device *dev = &dev_priv->drm;
6159         u32 freq_select, pcu_ack;
6160
6161         WARN_ON((cdclk == 24000) != (vco == 0));
6162
6163         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6164
6165         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6166                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6167                 return;
6168         }
6169
6170         /* set CDCLK_CTL */
6171         switch (cdclk) {
6172         case 450000:
6173         case 432000:
6174                 freq_select = CDCLK_FREQ_450_432;
6175                 pcu_ack = 1;
6176                 break;
6177         case 540000:
6178                 freq_select = CDCLK_FREQ_540;
6179                 pcu_ack = 2;
6180                 break;
6181         case 308571:
6182         case 337500:
6183         default:
6184                 freq_select = CDCLK_FREQ_337_308;
6185                 pcu_ack = 0;
6186                 break;
6187         case 617143:
6188         case 675000:
6189                 freq_select = CDCLK_FREQ_675_617;
6190                 pcu_ack = 3;
6191                 break;
6192         }
6193
6194         if (dev_priv->cdclk_pll.vco != 0 &&
6195             dev_priv->cdclk_pll.vco != vco)
6196                 skl_dpll0_disable(dev_priv);
6197
6198         if (dev_priv->cdclk_pll.vco != vco)
6199                 skl_dpll0_enable(dev_priv, vco);
6200
6201         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6202         POSTING_READ(CDCLK_CTL);
6203
6204         /* inform PCU of the change */
6205         mutex_lock(&dev_priv->rps.hw_lock);
6206         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6207         mutex_unlock(&dev_priv->rps.hw_lock);
6208
6209         intel_update_cdclk(dev);
6210 }
6211
6212 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6213
6214 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6215 {
6216         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6217 }
6218
6219 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6220 {
6221         int cdclk, vco;
6222
6223         skl_sanitize_cdclk(dev_priv);
6224
6225         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6226                 /*
6227                  * Use the current vco as our initial
6228                  * guess as to what the preferred vco is.
6229                  */
6230                 if (dev_priv->skl_preferred_vco_freq == 0)
6231                         skl_set_preferred_cdclk_vco(dev_priv,
6232                                                     dev_priv->cdclk_pll.vco);
6233                 return;
6234         }
6235
6236         vco = dev_priv->skl_preferred_vco_freq;
6237         if (vco == 0)
6238                 vco = 8100000;
6239         cdclk = skl_calc_cdclk(0, vco);
6240
6241         skl_set_cdclk(dev_priv, cdclk, vco);
6242 }
6243
6244 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6245 {
6246         uint32_t cdctl, expected;
6247
6248         /*
6249          * check if the pre-os intialized the display
6250          * There is SWF18 scratchpad register defined which is set by the
6251          * pre-os which can be used by the OS drivers to check the status
6252          */
6253         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6254                 goto sanitize;
6255
6256         intel_update_cdclk(&dev_priv->drm);
6257         /* Is PLL enabled and locked ? */
6258         if (dev_priv->cdclk_pll.vco == 0 ||
6259             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6260                 goto sanitize;
6261
6262         /* DPLL okay; verify the cdclock
6263          *
6264          * Noticed in some instances that the freq selection is correct but
6265          * decimal part is programmed wrong from BIOS where pre-os does not
6266          * enable display. Verify the same as well.
6267          */
6268         cdctl = I915_READ(CDCLK_CTL);
6269         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6270                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6271         if (cdctl == expected)
6272                 /* All well; nothing to sanitize */
6273                 return;
6274
6275 sanitize:
6276         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6277
6278         /* force cdclk programming */
6279         dev_priv->cdclk_freq = 0;
6280         /* force full PLL disable + enable */
6281         dev_priv->cdclk_pll.vco = -1;
6282 }
6283
6284 /* Adjust CDclk dividers to allow high res or save power if possible */
6285 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6286 {
6287         struct drm_i915_private *dev_priv = to_i915(dev);
6288         u32 val, cmd;
6289
6290         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6291                                         != dev_priv->cdclk_freq);
6292
6293         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6294                 cmd = 2;
6295         else if (cdclk == 266667)
6296                 cmd = 1;
6297         else
6298                 cmd = 0;
6299
6300         mutex_lock(&dev_priv->rps.hw_lock);
6301         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6302         val &= ~DSPFREQGUAR_MASK;
6303         val |= (cmd << DSPFREQGUAR_SHIFT);
6304         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6305         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6306                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6307                      50)) {
6308                 DRM_ERROR("timed out waiting for CDclk change\n");
6309         }
6310         mutex_unlock(&dev_priv->rps.hw_lock);
6311
6312         mutex_lock(&dev_priv->sb_lock);
6313
6314         if (cdclk == 400000) {
6315                 u32 divider;
6316
6317                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6318
6319                 /* adjust cdclk divider */
6320                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6321                 val &= ~CCK_FREQUENCY_VALUES;
6322                 val |= divider;
6323                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6324
6325                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6326                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6327                              50))
6328                         DRM_ERROR("timed out waiting for CDclk change\n");
6329         }
6330
6331         /* adjust self-refresh exit latency value */
6332         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6333         val &= ~0x7f;
6334
6335         /*
6336          * For high bandwidth configs, we set a higher latency in the bunit
6337          * so that the core display fetch happens in time to avoid underruns.
6338          */
6339         if (cdclk == 400000)
6340                 val |= 4500 / 250; /* 4.5 usec */
6341         else
6342                 val |= 3000 / 250; /* 3.0 usec */
6343         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6344
6345         mutex_unlock(&dev_priv->sb_lock);
6346
6347         intel_update_cdclk(dev);
6348 }
6349
6350 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6351 {
6352         struct drm_i915_private *dev_priv = to_i915(dev);
6353         u32 val, cmd;
6354
6355         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6356                                                 != dev_priv->cdclk_freq);
6357
6358         switch (cdclk) {
6359         case 333333:
6360         case 320000:
6361         case 266667:
6362         case 200000:
6363                 break;
6364         default:
6365                 MISSING_CASE(cdclk);
6366                 return;
6367         }
6368
6369         /*
6370          * Specs are full of misinformation, but testing on actual
6371          * hardware has shown that we just need to write the desired
6372          * CCK divider into the Punit register.
6373          */
6374         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6375
6376         mutex_lock(&dev_priv->rps.hw_lock);
6377         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6378         val &= ~DSPFREQGUAR_MASK_CHV;
6379         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6380         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6381         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6382                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6383                      50)) {
6384                 DRM_ERROR("timed out waiting for CDclk change\n");
6385         }
6386         mutex_unlock(&dev_priv->rps.hw_lock);
6387
6388         intel_update_cdclk(dev);
6389 }
6390
6391 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6392                                  int max_pixclk)
6393 {
6394         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6395         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6396
6397         /*
6398          * Really only a few cases to deal with, as only 4 CDclks are supported:
6399          *   200MHz
6400          *   267MHz
6401          *   320/333MHz (depends on HPLL freq)
6402          *   400MHz (VLV only)
6403          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6404          * of the lower bin and adjust if needed.
6405          *
6406          * We seem to get an unstable or solid color picture at 200MHz.
6407          * Not sure what's wrong. For now use 200MHz only when all pipes
6408          * are off.
6409          */
6410         if (!IS_CHERRYVIEW(dev_priv) &&
6411             max_pixclk > freq_320*limit/100)
6412                 return 400000;
6413         else if (max_pixclk > 266667*limit/100)
6414                 return freq_320;
6415         else if (max_pixclk > 0)
6416                 return 266667;
6417         else
6418                 return 200000;
6419 }
6420
6421 static int bxt_calc_cdclk(int max_pixclk)
6422 {
6423         if (max_pixclk > 576000)
6424                 return 624000;
6425         else if (max_pixclk > 384000)
6426                 return 576000;
6427         else if (max_pixclk > 288000)
6428                 return 384000;
6429         else if (max_pixclk > 144000)
6430                 return 288000;
6431         else
6432                 return 144000;
6433 }
6434
6435 /* Compute the max pixel clock for new configuration. */
6436 static int intel_mode_max_pixclk(struct drm_device *dev,
6437                                  struct drm_atomic_state *state)
6438 {
6439         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6440         struct drm_i915_private *dev_priv = to_i915(dev);
6441         struct drm_crtc *crtc;
6442         struct drm_crtc_state *crtc_state;
6443         unsigned max_pixclk = 0, i;
6444         enum pipe pipe;
6445
6446         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6447                sizeof(intel_state->min_pixclk));
6448
6449         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6450                 int pixclk = 0;
6451
6452                 if (crtc_state->enable)
6453                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6454
6455                 intel_state->min_pixclk[i] = pixclk;
6456         }
6457
6458         for_each_pipe(dev_priv, pipe)
6459                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6460
6461         return max_pixclk;
6462 }
6463
6464 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6465 {
6466         struct drm_device *dev = state->dev;
6467         struct drm_i915_private *dev_priv = to_i915(dev);
6468         int max_pixclk = intel_mode_max_pixclk(dev, state);
6469         struct intel_atomic_state *intel_state =
6470                 to_intel_atomic_state(state);
6471
6472         intel_state->cdclk = intel_state->dev_cdclk =
6473                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6474
6475         if (!intel_state->active_crtcs)
6476                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6477
6478         return 0;
6479 }
6480
6481 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6482 {
6483         int max_pixclk = ilk_max_pixel_rate(state);
6484         struct intel_atomic_state *intel_state =
6485                 to_intel_atomic_state(state);
6486
6487         intel_state->cdclk = intel_state->dev_cdclk =
6488                 bxt_calc_cdclk(max_pixclk);
6489
6490         if (!intel_state->active_crtcs)
6491                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6492
6493         return 0;
6494 }
6495
6496 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6497 {
6498         unsigned int credits, default_credits;
6499
6500         if (IS_CHERRYVIEW(dev_priv))
6501                 default_credits = PFI_CREDIT(12);
6502         else
6503                 default_credits = PFI_CREDIT(8);
6504
6505         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6506                 /* CHV suggested value is 31 or 63 */
6507                 if (IS_CHERRYVIEW(dev_priv))
6508                         credits = PFI_CREDIT_63;
6509                 else
6510                         credits = PFI_CREDIT(15);
6511         } else {
6512                 credits = default_credits;
6513         }
6514
6515         /*
6516          * WA - write default credits before re-programming
6517          * FIXME: should we also set the resend bit here?
6518          */
6519         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6520                    default_credits);
6521
6522         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6523                    credits | PFI_CREDIT_RESEND);
6524
6525         /*
6526          * FIXME is this guaranteed to clear
6527          * immediately or should we poll for it?
6528          */
6529         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6530 }
6531
6532 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6533 {
6534         struct drm_device *dev = old_state->dev;
6535         struct drm_i915_private *dev_priv = to_i915(dev);
6536         struct intel_atomic_state *old_intel_state =
6537                 to_intel_atomic_state(old_state);
6538         unsigned req_cdclk = old_intel_state->dev_cdclk;
6539
6540         /*
6541          * FIXME: We can end up here with all power domains off, yet
6542          * with a CDCLK frequency other than the minimum. To account
6543          * for this take the PIPE-A power domain, which covers the HW
6544          * blocks needed for the following programming. This can be
6545          * removed once it's guaranteed that we get here either with
6546          * the minimum CDCLK set, or the required power domains
6547          * enabled.
6548          */
6549         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6550
6551         if (IS_CHERRYVIEW(dev))
6552                 cherryview_set_cdclk(dev, req_cdclk);
6553         else
6554                 valleyview_set_cdclk(dev, req_cdclk);
6555
6556         vlv_program_pfi_credits(dev_priv);
6557
6558         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6559 }
6560
6561 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6562 {
6563         struct drm_device *dev = crtc->dev;
6564         struct drm_i915_private *dev_priv = to_i915(dev);
6565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6566         struct intel_encoder *encoder;
6567         struct intel_crtc_state *pipe_config =
6568                 to_intel_crtc_state(crtc->state);
6569         int pipe = intel_crtc->pipe;
6570
6571         if (WARN_ON(intel_crtc->active))
6572                 return;
6573
6574         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6575                 intel_dp_set_m_n(intel_crtc, M1_N1);
6576
6577         intel_set_pipe_timings(intel_crtc);
6578         intel_set_pipe_src_size(intel_crtc);
6579
6580         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6581                 struct drm_i915_private *dev_priv = to_i915(dev);
6582
6583                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6584                 I915_WRITE(CHV_CANVAS(pipe), 0);
6585         }
6586
6587         i9xx_set_pipeconf(intel_crtc);
6588
6589         intel_crtc->active = true;
6590
6591         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6592
6593         for_each_encoder_on_crtc(dev, crtc, encoder)
6594                 if (encoder->pre_pll_enable)
6595                         encoder->pre_pll_enable(encoder);
6596
6597         if (IS_CHERRYVIEW(dev)) {
6598                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6599                 chv_enable_pll(intel_crtc, intel_crtc->config);
6600         } else {
6601                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6602                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6603         }
6604
6605         for_each_encoder_on_crtc(dev, crtc, encoder)
6606                 if (encoder->pre_enable)
6607                         encoder->pre_enable(encoder);
6608
6609         i9xx_pfit_enable(intel_crtc);
6610
6611         intel_color_load_luts(&pipe_config->base);
6612
6613         intel_update_watermarks(crtc);
6614         intel_enable_pipe(intel_crtc);
6615
6616         assert_vblank_disabled(crtc);
6617         drm_crtc_vblank_on(crtc);
6618
6619         for_each_encoder_on_crtc(dev, crtc, encoder)
6620                 encoder->enable(encoder);
6621 }
6622
6623 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6624 {
6625         struct drm_device *dev = crtc->base.dev;
6626         struct drm_i915_private *dev_priv = to_i915(dev);
6627
6628         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6629         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6630 }
6631
6632 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6633 {
6634         struct drm_device *dev = crtc->dev;
6635         struct drm_i915_private *dev_priv = to_i915(dev);
6636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6637         struct intel_encoder *encoder;
6638         struct intel_crtc_state *pipe_config =
6639                 to_intel_crtc_state(crtc->state);
6640         enum pipe pipe = intel_crtc->pipe;
6641
6642         if (WARN_ON(intel_crtc->active))
6643                 return;
6644
6645         i9xx_set_pll_dividers(intel_crtc);
6646
6647         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6648                 intel_dp_set_m_n(intel_crtc, M1_N1);
6649
6650         intel_set_pipe_timings(intel_crtc);
6651         intel_set_pipe_src_size(intel_crtc);
6652
6653         i9xx_set_pipeconf(intel_crtc);
6654
6655         intel_crtc->active = true;
6656
6657         if (!IS_GEN2(dev))
6658                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6659
6660         for_each_encoder_on_crtc(dev, crtc, encoder)
6661                 if (encoder->pre_enable)
6662                         encoder->pre_enable(encoder);
6663
6664         i9xx_enable_pll(intel_crtc);
6665
6666         i9xx_pfit_enable(intel_crtc);
6667
6668         intel_color_load_luts(&pipe_config->base);
6669
6670         intel_update_watermarks(crtc);
6671         intel_enable_pipe(intel_crtc);
6672
6673         assert_vblank_disabled(crtc);
6674         drm_crtc_vblank_on(crtc);
6675
6676         for_each_encoder_on_crtc(dev, crtc, encoder)
6677                 encoder->enable(encoder);
6678 }
6679
6680 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6681 {
6682         struct drm_device *dev = crtc->base.dev;
6683         struct drm_i915_private *dev_priv = to_i915(dev);
6684
6685         if (!crtc->config->gmch_pfit.control)
6686                 return;
6687
6688         assert_pipe_disabled(dev_priv, crtc->pipe);
6689
6690         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6691                          I915_READ(PFIT_CONTROL));
6692         I915_WRITE(PFIT_CONTROL, 0);
6693 }
6694
6695 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6696 {
6697         struct drm_device *dev = crtc->dev;
6698         struct drm_i915_private *dev_priv = to_i915(dev);
6699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6700         struct intel_encoder *encoder;
6701         int pipe = intel_crtc->pipe;
6702
6703         /*
6704          * On gen2 planes are double buffered but the pipe isn't, so we must
6705          * wait for planes to fully turn off before disabling the pipe.
6706          */
6707         if (IS_GEN2(dev))
6708                 intel_wait_for_vblank(dev, pipe);
6709
6710         for_each_encoder_on_crtc(dev, crtc, encoder)
6711                 encoder->disable(encoder);
6712
6713         drm_crtc_vblank_off(crtc);
6714         assert_vblank_disabled(crtc);
6715
6716         intel_disable_pipe(intel_crtc);
6717
6718         i9xx_pfit_disable(intel_crtc);
6719
6720         for_each_encoder_on_crtc(dev, crtc, encoder)
6721                 if (encoder->post_disable)
6722                         encoder->post_disable(encoder);
6723
6724         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6725                 if (IS_CHERRYVIEW(dev))
6726                         chv_disable_pll(dev_priv, pipe);
6727                 else if (IS_VALLEYVIEW(dev))
6728                         vlv_disable_pll(dev_priv, pipe);
6729                 else
6730                         i9xx_disable_pll(intel_crtc);
6731         }
6732
6733         for_each_encoder_on_crtc(dev, crtc, encoder)
6734                 if (encoder->post_pll_disable)
6735                         encoder->post_pll_disable(encoder);
6736
6737         if (!IS_GEN2(dev))
6738                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6739 }
6740
6741 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6742 {
6743         struct intel_encoder *encoder;
6744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6745         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6746         enum intel_display_power_domain domain;
6747         unsigned long domains;
6748
6749         if (!intel_crtc->active)
6750                 return;
6751
6752         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6753                 WARN_ON(intel_crtc->flip_work);
6754
6755                 intel_pre_disable_primary_noatomic(crtc);
6756
6757                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6758                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6759         }
6760
6761         dev_priv->display.crtc_disable(crtc);
6762
6763         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6764                       crtc->base.id, crtc->name);
6765
6766         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6767         crtc->state->active = false;
6768         intel_crtc->active = false;
6769         crtc->enabled = false;
6770         crtc->state->connector_mask = 0;
6771         crtc->state->encoder_mask = 0;
6772
6773         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6774                 encoder->base.crtc = NULL;
6775
6776         intel_fbc_disable(intel_crtc);
6777         intel_update_watermarks(crtc);
6778         intel_disable_shared_dpll(intel_crtc);
6779
6780         domains = intel_crtc->enabled_power_domains;
6781         for_each_power_domain(domain, domains)
6782                 intel_display_power_put(dev_priv, domain);
6783         intel_crtc->enabled_power_domains = 0;
6784
6785         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6786         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6787 }
6788
6789 /*
6790  * turn all crtc's off, but do not adjust state
6791  * This has to be paired with a call to intel_modeset_setup_hw_state.
6792  */
6793 int intel_display_suspend(struct drm_device *dev)
6794 {
6795         struct drm_i915_private *dev_priv = to_i915(dev);
6796         struct drm_atomic_state *state;
6797         int ret;
6798
6799         state = drm_atomic_helper_suspend(dev);
6800         ret = PTR_ERR_OR_ZERO(state);
6801         if (ret)
6802                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6803         else
6804                 dev_priv->modeset_restore_state = state;
6805         return ret;
6806 }
6807
6808 void intel_encoder_destroy(struct drm_encoder *encoder)
6809 {
6810         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6811
6812         drm_encoder_cleanup(encoder);
6813         kfree(intel_encoder);
6814 }
6815
6816 /* Cross check the actual hw state with our own modeset state tracking (and it's
6817  * internal consistency). */
6818 static void intel_connector_verify_state(struct intel_connector *connector)
6819 {
6820         struct drm_crtc *crtc = connector->base.state->crtc;
6821
6822         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6823                       connector->base.base.id,
6824                       connector->base.name);
6825
6826         if (connector->get_hw_state(connector)) {
6827                 struct intel_encoder *encoder = connector->encoder;
6828                 struct drm_connector_state *conn_state = connector->base.state;
6829
6830                 I915_STATE_WARN(!crtc,
6831                          "connector enabled without attached crtc\n");
6832
6833                 if (!crtc)
6834                         return;
6835
6836                 I915_STATE_WARN(!crtc->state->active,
6837                       "connector is active, but attached crtc isn't\n");
6838
6839                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6840                         return;
6841
6842                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6843                         "atomic encoder doesn't match attached encoder\n");
6844
6845                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6846                         "attached encoder crtc differs from connector crtc\n");
6847         } else {
6848                 I915_STATE_WARN(crtc && crtc->state->active,
6849                         "attached crtc is active, but connector isn't\n");
6850                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6851                         "best encoder set without crtc!\n");
6852         }
6853 }
6854
6855 int intel_connector_init(struct intel_connector *connector)
6856 {
6857         drm_atomic_helper_connector_reset(&connector->base);
6858
6859         if (!connector->base.state)
6860                 return -ENOMEM;
6861
6862         return 0;
6863 }
6864
6865 struct intel_connector *intel_connector_alloc(void)
6866 {
6867         struct intel_connector *connector;
6868
6869         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6870         if (!connector)
6871                 return NULL;
6872
6873         if (intel_connector_init(connector) < 0) {
6874                 kfree(connector);
6875                 return NULL;
6876         }
6877
6878         return connector;
6879 }
6880
6881 /* Simple connector->get_hw_state implementation for encoders that support only
6882  * one connector and no cloning and hence the encoder state determines the state
6883  * of the connector. */
6884 bool intel_connector_get_hw_state(struct intel_connector *connector)
6885 {
6886         enum pipe pipe = 0;
6887         struct intel_encoder *encoder = connector->encoder;
6888
6889         return encoder->get_hw_state(encoder, &pipe);
6890 }
6891
6892 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6893 {
6894         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6895                 return crtc_state->fdi_lanes;
6896
6897         return 0;
6898 }
6899
6900 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6901                                      struct intel_crtc_state *pipe_config)
6902 {
6903         struct drm_atomic_state *state = pipe_config->base.state;
6904         struct intel_crtc *other_crtc;
6905         struct intel_crtc_state *other_crtc_state;
6906
6907         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6908                       pipe_name(pipe), pipe_config->fdi_lanes);
6909         if (pipe_config->fdi_lanes > 4) {
6910                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6911                               pipe_name(pipe), pipe_config->fdi_lanes);
6912                 return -EINVAL;
6913         }
6914
6915         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6916                 if (pipe_config->fdi_lanes > 2) {
6917                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6918                                       pipe_config->fdi_lanes);
6919                         return -EINVAL;
6920                 } else {
6921                         return 0;
6922                 }
6923         }
6924
6925         if (INTEL_INFO(dev)->num_pipes == 2)
6926                 return 0;
6927
6928         /* Ivybridge 3 pipe is really complicated */
6929         switch (pipe) {
6930         case PIPE_A:
6931                 return 0;
6932         case PIPE_B:
6933                 if (pipe_config->fdi_lanes <= 2)
6934                         return 0;
6935
6936                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6937                 other_crtc_state =
6938                         intel_atomic_get_crtc_state(state, other_crtc);
6939                 if (IS_ERR(other_crtc_state))
6940                         return PTR_ERR(other_crtc_state);
6941
6942                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6943                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6944                                       pipe_name(pipe), pipe_config->fdi_lanes);
6945                         return -EINVAL;
6946                 }
6947                 return 0;
6948         case PIPE_C:
6949                 if (pipe_config->fdi_lanes > 2) {
6950                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6951                                       pipe_name(pipe), pipe_config->fdi_lanes);
6952                         return -EINVAL;
6953                 }
6954
6955                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6956                 other_crtc_state =
6957                         intel_atomic_get_crtc_state(state, other_crtc);
6958                 if (IS_ERR(other_crtc_state))
6959                         return PTR_ERR(other_crtc_state);
6960
6961                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6962                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6963                         return -EINVAL;
6964                 }
6965                 return 0;
6966         default:
6967                 BUG();
6968         }
6969 }
6970
6971 #define RETRY 1
6972 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6973                                        struct intel_crtc_state *pipe_config)
6974 {
6975         struct drm_device *dev = intel_crtc->base.dev;
6976         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6977         int lane, link_bw, fdi_dotclock, ret;
6978         bool needs_recompute = false;
6979
6980 retry:
6981         /* FDI is a binary signal running at ~2.7GHz, encoding
6982          * each output octet as 10 bits. The actual frequency
6983          * is stored as a divider into a 100MHz clock, and the
6984          * mode pixel clock is stored in units of 1KHz.
6985          * Hence the bw of each lane in terms of the mode signal
6986          * is:
6987          */
6988         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6989
6990         fdi_dotclock = adjusted_mode->crtc_clock;
6991
6992         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6993                                            pipe_config->pipe_bpp);
6994
6995         pipe_config->fdi_lanes = lane;
6996
6997         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6998                                link_bw, &pipe_config->fdi_m_n);
6999
7000         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7001         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7002                 pipe_config->pipe_bpp -= 2*3;
7003                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7004                               pipe_config->pipe_bpp);
7005                 needs_recompute = true;
7006                 pipe_config->bw_constrained = true;
7007
7008                 goto retry;
7009         }
7010
7011         if (needs_recompute)
7012                 return RETRY;
7013
7014         return ret;
7015 }
7016
7017 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7018                                      struct intel_crtc_state *pipe_config)
7019 {
7020         if (pipe_config->pipe_bpp > 24)
7021                 return false;
7022
7023         /* HSW can handle pixel rate up to cdclk? */
7024         if (IS_HASWELL(dev_priv))
7025                 return true;
7026
7027         /*
7028          * We compare against max which means we must take
7029          * the increased cdclk requirement into account when
7030          * calculating the new cdclk.
7031          *
7032          * Should measure whether using a lower cdclk w/o IPS
7033          */
7034         return ilk_pipe_pixel_rate(pipe_config) <=
7035                 dev_priv->max_cdclk_freq * 95 / 100;
7036 }
7037
7038 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7039                                    struct intel_crtc_state *pipe_config)
7040 {
7041         struct drm_device *dev = crtc->base.dev;
7042         struct drm_i915_private *dev_priv = to_i915(dev);
7043
7044         pipe_config->ips_enabled = i915.enable_ips &&
7045                 hsw_crtc_supports_ips(crtc) &&
7046                 pipe_config_supports_ips(dev_priv, pipe_config);
7047 }
7048
7049 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7050 {
7051         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7052
7053         /* GDG double wide on either pipe, otherwise pipe A only */
7054         return INTEL_INFO(dev_priv)->gen < 4 &&
7055                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7056 }
7057
7058 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7059                                      struct intel_crtc_state *pipe_config)
7060 {
7061         struct drm_device *dev = crtc->base.dev;
7062         struct drm_i915_private *dev_priv = to_i915(dev);
7063         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7064         int clock_limit = dev_priv->max_dotclk_freq;
7065
7066         if (INTEL_INFO(dev)->gen < 4) {
7067                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7068
7069                 /*
7070                  * Enable double wide mode when the dot clock
7071                  * is > 90% of the (display) core speed.
7072                  */
7073                 if (intel_crtc_supports_double_wide(crtc) &&
7074                     adjusted_mode->crtc_clock > clock_limit) {
7075                         clock_limit = dev_priv->max_dotclk_freq;
7076                         pipe_config->double_wide = true;
7077                 }
7078         }
7079
7080         if (adjusted_mode->crtc_clock > clock_limit) {
7081                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7082                               adjusted_mode->crtc_clock, clock_limit,
7083                               yesno(pipe_config->double_wide));
7084                 return -EINVAL;
7085         }
7086
7087         /*
7088          * Pipe horizontal size must be even in:
7089          * - DVO ganged mode
7090          * - LVDS dual channel mode
7091          * - Double wide pipe
7092          */
7093         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7094              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7095                 pipe_config->pipe_src_w &= ~1;
7096
7097         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7098          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7099          */
7100         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7101                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7102                 return -EINVAL;
7103
7104         if (HAS_IPS(dev))
7105                 hsw_compute_ips_config(crtc, pipe_config);
7106
7107         if (pipe_config->has_pch_encoder)
7108                 return ironlake_fdi_compute_config(crtc, pipe_config);
7109
7110         return 0;
7111 }
7112
7113 static int skylake_get_display_clock_speed(struct drm_device *dev)
7114 {
7115         struct drm_i915_private *dev_priv = to_i915(dev);
7116         uint32_t cdctl;
7117
7118         skl_dpll0_update(dev_priv);
7119
7120         if (dev_priv->cdclk_pll.vco == 0)
7121                 return dev_priv->cdclk_pll.ref;
7122
7123         cdctl = I915_READ(CDCLK_CTL);
7124
7125         if (dev_priv->cdclk_pll.vco == 8640000) {
7126                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7127                 case CDCLK_FREQ_450_432:
7128                         return 432000;
7129                 case CDCLK_FREQ_337_308:
7130                         return 308571;
7131                 case CDCLK_FREQ_540:
7132                         return 540000;
7133                 case CDCLK_FREQ_675_617:
7134                         return 617143;
7135                 default:
7136                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7137                 }
7138         } else {
7139                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7140                 case CDCLK_FREQ_450_432:
7141                         return 450000;
7142                 case CDCLK_FREQ_337_308:
7143                         return 337500;
7144                 case CDCLK_FREQ_540:
7145                         return 540000;
7146                 case CDCLK_FREQ_675_617:
7147                         return 675000;
7148                 default:
7149                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7150                 }
7151         }
7152
7153         return dev_priv->cdclk_pll.ref;
7154 }
7155
7156 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7157 {
7158         u32 val;
7159
7160         dev_priv->cdclk_pll.ref = 19200;
7161         dev_priv->cdclk_pll.vco = 0;
7162
7163         val = I915_READ(BXT_DE_PLL_ENABLE);
7164         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7165                 return;
7166
7167         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7168                 return;
7169
7170         val = I915_READ(BXT_DE_PLL_CTL);
7171         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7172                 dev_priv->cdclk_pll.ref;
7173 }
7174
7175 static int broxton_get_display_clock_speed(struct drm_device *dev)
7176 {
7177         struct drm_i915_private *dev_priv = to_i915(dev);
7178         u32 divider;
7179         int div, vco;
7180
7181         bxt_de_pll_update(dev_priv);
7182
7183         vco = dev_priv->cdclk_pll.vco;
7184         if (vco == 0)
7185                 return dev_priv->cdclk_pll.ref;
7186
7187         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7188
7189         switch (divider) {
7190         case BXT_CDCLK_CD2X_DIV_SEL_1:
7191                 div = 2;
7192                 break;
7193         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7194                 div = 3;
7195                 break;
7196         case BXT_CDCLK_CD2X_DIV_SEL_2:
7197                 div = 4;
7198                 break;
7199         case BXT_CDCLK_CD2X_DIV_SEL_4:
7200                 div = 8;
7201                 break;
7202         default:
7203                 MISSING_CASE(divider);
7204                 return dev_priv->cdclk_pll.ref;
7205         }
7206
7207         return DIV_ROUND_CLOSEST(vco, div);
7208 }
7209
7210 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7211 {
7212         struct drm_i915_private *dev_priv = to_i915(dev);
7213         uint32_t lcpll = I915_READ(LCPLL_CTL);
7214         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7215
7216         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7217                 return 800000;
7218         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7219                 return 450000;
7220         else if (freq == LCPLL_CLK_FREQ_450)
7221                 return 450000;
7222         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7223                 return 540000;
7224         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7225                 return 337500;
7226         else
7227                 return 675000;
7228 }
7229
7230 static int haswell_get_display_clock_speed(struct drm_device *dev)
7231 {
7232         struct drm_i915_private *dev_priv = to_i915(dev);
7233         uint32_t lcpll = I915_READ(LCPLL_CTL);
7234         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7235
7236         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7237                 return 800000;
7238         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7239                 return 450000;
7240         else if (freq == LCPLL_CLK_FREQ_450)
7241                 return 450000;
7242         else if (IS_HSW_ULT(dev))
7243                 return 337500;
7244         else
7245                 return 540000;
7246 }
7247
7248 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7249 {
7250         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7251                                       CCK_DISPLAY_CLOCK_CONTROL);
7252 }
7253
7254 static int ilk_get_display_clock_speed(struct drm_device *dev)
7255 {
7256         return 450000;
7257 }
7258
7259 static int i945_get_display_clock_speed(struct drm_device *dev)
7260 {
7261         return 400000;
7262 }
7263
7264 static int i915_get_display_clock_speed(struct drm_device *dev)
7265 {
7266         return 333333;
7267 }
7268
7269 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7270 {
7271         return 200000;
7272 }
7273
7274 static int pnv_get_display_clock_speed(struct drm_device *dev)
7275 {
7276         u16 gcfgc = 0;
7277
7278         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7279
7280         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7281         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7282                 return 266667;
7283         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7284                 return 333333;
7285         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7286                 return 444444;
7287         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7288                 return 200000;
7289         default:
7290                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7291         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7292                 return 133333;
7293         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7294                 return 166667;
7295         }
7296 }
7297
7298 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7299 {
7300         u16 gcfgc = 0;
7301
7302         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7303
7304         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7305                 return 133333;
7306         else {
7307                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7308                 case GC_DISPLAY_CLOCK_333_MHZ:
7309                         return 333333;
7310                 default:
7311                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7312                         return 190000;
7313                 }
7314         }
7315 }
7316
7317 static int i865_get_display_clock_speed(struct drm_device *dev)
7318 {
7319         return 266667;
7320 }
7321
7322 static int i85x_get_display_clock_speed(struct drm_device *dev)
7323 {
7324         u16 hpllcc = 0;
7325
7326         /*
7327          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7328          * encoding is different :(
7329          * FIXME is this the right way to detect 852GM/852GMV?
7330          */
7331         if (dev->pdev->revision == 0x1)
7332                 return 133333;
7333
7334         pci_bus_read_config_word(dev->pdev->bus,
7335                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7336
7337         /* Assume that the hardware is in the high speed state.  This
7338          * should be the default.
7339          */
7340         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7341         case GC_CLOCK_133_200:
7342         case GC_CLOCK_133_200_2:
7343         case GC_CLOCK_100_200:
7344                 return 200000;
7345         case GC_CLOCK_166_250:
7346                 return 250000;
7347         case GC_CLOCK_100_133:
7348                 return 133333;
7349         case GC_CLOCK_133_266:
7350         case GC_CLOCK_133_266_2:
7351         case GC_CLOCK_166_266:
7352                 return 266667;
7353         }
7354
7355         /* Shouldn't happen */
7356         return 0;
7357 }
7358
7359 static int i830_get_display_clock_speed(struct drm_device *dev)
7360 {
7361         return 133333;
7362 }
7363
7364 static unsigned int intel_hpll_vco(struct drm_device *dev)
7365 {
7366         struct drm_i915_private *dev_priv = to_i915(dev);
7367         static const unsigned int blb_vco[8] = {
7368                 [0] = 3200000,
7369                 [1] = 4000000,
7370                 [2] = 5333333,
7371                 [3] = 4800000,
7372                 [4] = 6400000,
7373         };
7374         static const unsigned int pnv_vco[8] = {
7375                 [0] = 3200000,
7376                 [1] = 4000000,
7377                 [2] = 5333333,
7378                 [3] = 4800000,
7379                 [4] = 2666667,
7380         };
7381         static const unsigned int cl_vco[8] = {
7382                 [0] = 3200000,
7383                 [1] = 4000000,
7384                 [2] = 5333333,
7385                 [3] = 6400000,
7386                 [4] = 3333333,
7387                 [5] = 3566667,
7388                 [6] = 4266667,
7389         };
7390         static const unsigned int elk_vco[8] = {
7391                 [0] = 3200000,
7392                 [1] = 4000000,
7393                 [2] = 5333333,
7394                 [3] = 4800000,
7395         };
7396         static const unsigned int ctg_vco[8] = {
7397                 [0] = 3200000,
7398                 [1] = 4000000,
7399                 [2] = 5333333,
7400                 [3] = 6400000,
7401                 [4] = 2666667,
7402                 [5] = 4266667,
7403         };
7404         const unsigned int *vco_table;
7405         unsigned int vco;
7406         uint8_t tmp = 0;
7407
7408         /* FIXME other chipsets? */
7409         if (IS_GM45(dev))
7410                 vco_table = ctg_vco;
7411         else if (IS_G4X(dev))
7412                 vco_table = elk_vco;
7413         else if (IS_CRESTLINE(dev))
7414                 vco_table = cl_vco;
7415         else if (IS_PINEVIEW(dev))
7416                 vco_table = pnv_vco;
7417         else if (IS_G33(dev))
7418                 vco_table = blb_vco;
7419         else
7420                 return 0;
7421
7422         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7423
7424         vco = vco_table[tmp & 0x7];
7425         if (vco == 0)
7426                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7427         else
7428                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7429
7430         return vco;
7431 }
7432
7433 static int gm45_get_display_clock_speed(struct drm_device *dev)
7434 {
7435         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7436         uint16_t tmp = 0;
7437
7438         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7439
7440         cdclk_sel = (tmp >> 12) & 0x1;
7441
7442         switch (vco) {
7443         case 2666667:
7444         case 4000000:
7445         case 5333333:
7446                 return cdclk_sel ? 333333 : 222222;
7447         case 3200000:
7448                 return cdclk_sel ? 320000 : 228571;
7449         default:
7450                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7451                 return 222222;
7452         }
7453 }
7454
7455 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7456 {
7457         static const uint8_t div_3200[] = { 16, 10,  8 };
7458         static const uint8_t div_4000[] = { 20, 12, 10 };
7459         static const uint8_t div_5333[] = { 24, 16, 14 };
7460         const uint8_t *div_table;
7461         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7462         uint16_t tmp = 0;
7463
7464         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7465
7466         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7467
7468         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7469                 goto fail;
7470
7471         switch (vco) {
7472         case 3200000:
7473                 div_table = div_3200;
7474                 break;
7475         case 4000000:
7476                 div_table = div_4000;
7477                 break;
7478         case 5333333:
7479                 div_table = div_5333;
7480                 break;
7481         default:
7482                 goto fail;
7483         }
7484
7485         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7486
7487 fail:
7488         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7489         return 200000;
7490 }
7491
7492 static int g33_get_display_clock_speed(struct drm_device *dev)
7493 {
7494         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7495         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7496         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7497         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7498         const uint8_t *div_table;
7499         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7500         uint16_t tmp = 0;
7501
7502         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7503
7504         cdclk_sel = (tmp >> 4) & 0x7;
7505
7506         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7507                 goto fail;
7508
7509         switch (vco) {
7510         case 3200000:
7511                 div_table = div_3200;
7512                 break;
7513         case 4000000:
7514                 div_table = div_4000;
7515                 break;
7516         case 4800000:
7517                 div_table = div_4800;
7518                 break;
7519         case 5333333:
7520                 div_table = div_5333;
7521                 break;
7522         default:
7523                 goto fail;
7524         }
7525
7526         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7527
7528 fail:
7529         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7530         return 190476;
7531 }
7532
7533 static void
7534 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7535 {
7536         while (*num > DATA_LINK_M_N_MASK ||
7537                *den > DATA_LINK_M_N_MASK) {
7538                 *num >>= 1;
7539                 *den >>= 1;
7540         }
7541 }
7542
7543 static void compute_m_n(unsigned int m, unsigned int n,
7544                         uint32_t *ret_m, uint32_t *ret_n)
7545 {
7546         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7547         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7548         intel_reduce_m_n_ratio(ret_m, ret_n);
7549 }
7550
7551 void
7552 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7553                        int pixel_clock, int link_clock,
7554                        struct intel_link_m_n *m_n)
7555 {
7556         m_n->tu = 64;
7557
7558         compute_m_n(bits_per_pixel * pixel_clock,
7559                     link_clock * nlanes * 8,
7560                     &m_n->gmch_m, &m_n->gmch_n);
7561
7562         compute_m_n(pixel_clock, link_clock,
7563                     &m_n->link_m, &m_n->link_n);
7564 }
7565
7566 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7567 {
7568         if (i915.panel_use_ssc >= 0)
7569                 return i915.panel_use_ssc != 0;
7570         return dev_priv->vbt.lvds_use_ssc
7571                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7572 }
7573
7574 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7575 {
7576         return (1 << dpll->n) << 16 | dpll->m2;
7577 }
7578
7579 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7580 {
7581         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7582 }
7583
7584 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7585                                      struct intel_crtc_state *crtc_state,
7586                                      struct dpll *reduced_clock)
7587 {
7588         struct drm_device *dev = crtc->base.dev;
7589         u32 fp, fp2 = 0;
7590
7591         if (IS_PINEVIEW(dev)) {
7592                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7593                 if (reduced_clock)
7594                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7595         } else {
7596                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7597                 if (reduced_clock)
7598                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7599         }
7600
7601         crtc_state->dpll_hw_state.fp0 = fp;
7602
7603         crtc->lowfreq_avail = false;
7604         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7605             reduced_clock) {
7606                 crtc_state->dpll_hw_state.fp1 = fp2;
7607                 crtc->lowfreq_avail = true;
7608         } else {
7609                 crtc_state->dpll_hw_state.fp1 = fp;
7610         }
7611 }
7612
7613 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7614                 pipe)
7615 {
7616         u32 reg_val;
7617
7618         /*
7619          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7620          * and set it to a reasonable value instead.
7621          */
7622         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7623         reg_val &= 0xffffff00;
7624         reg_val |= 0x00000030;
7625         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7626
7627         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7628         reg_val &= 0x8cffffff;
7629         reg_val = 0x8c000000;
7630         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7631
7632         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7633         reg_val &= 0xffffff00;
7634         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7635
7636         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7637         reg_val &= 0x00ffffff;
7638         reg_val |= 0xb0000000;
7639         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7640 }
7641
7642 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7643                                          struct intel_link_m_n *m_n)
7644 {
7645         struct drm_device *dev = crtc->base.dev;
7646         struct drm_i915_private *dev_priv = to_i915(dev);
7647         int pipe = crtc->pipe;
7648
7649         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7650         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7651         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7652         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7653 }
7654
7655 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7656                                          struct intel_link_m_n *m_n,
7657                                          struct intel_link_m_n *m2_n2)
7658 {
7659         struct drm_device *dev = crtc->base.dev;
7660         struct drm_i915_private *dev_priv = to_i915(dev);
7661         int pipe = crtc->pipe;
7662         enum transcoder transcoder = crtc->config->cpu_transcoder;
7663
7664         if (INTEL_INFO(dev)->gen >= 5) {
7665                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7666                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7667                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7668                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7669                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7670                  * for gen < 8) and if DRRS is supported (to make sure the
7671                  * registers are not unnecessarily accessed).
7672                  */
7673                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7674                         crtc->config->has_drrs) {
7675                         I915_WRITE(PIPE_DATA_M2(transcoder),
7676                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7677                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7678                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7679                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7680                 }
7681         } else {
7682                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7683                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7684                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7685                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7686         }
7687 }
7688
7689 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7690 {
7691         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7692
7693         if (m_n == M1_N1) {
7694                 dp_m_n = &crtc->config->dp_m_n;
7695                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7696         } else if (m_n == M2_N2) {
7697
7698                 /*
7699                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7700                  * needs to be programmed into M1_N1.
7701                  */
7702                 dp_m_n = &crtc->config->dp_m2_n2;
7703         } else {
7704                 DRM_ERROR("Unsupported divider value\n");
7705                 return;
7706         }
7707
7708         if (crtc->config->has_pch_encoder)
7709                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7710         else
7711                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7712 }
7713
7714 static void vlv_compute_dpll(struct intel_crtc *crtc,
7715                              struct intel_crtc_state *pipe_config)
7716 {
7717         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7718                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7719         if (crtc->pipe != PIPE_A)
7720                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7721
7722         /* DPLL not used with DSI, but still need the rest set up */
7723         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7724                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7725                         DPLL_EXT_BUFFER_ENABLE_VLV;
7726
7727         pipe_config->dpll_hw_state.dpll_md =
7728                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7729 }
7730
7731 static void chv_compute_dpll(struct intel_crtc *crtc,
7732                              struct intel_crtc_state *pipe_config)
7733 {
7734         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7735                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7736         if (crtc->pipe != PIPE_A)
7737                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7738
7739         /* DPLL not used with DSI, but still need the rest set up */
7740         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7741                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7742
7743         pipe_config->dpll_hw_state.dpll_md =
7744                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7745 }
7746
7747 static void vlv_prepare_pll(struct intel_crtc *crtc,
7748                             const struct intel_crtc_state *pipe_config)
7749 {
7750         struct drm_device *dev = crtc->base.dev;
7751         struct drm_i915_private *dev_priv = to_i915(dev);
7752         enum pipe pipe = crtc->pipe;
7753         u32 mdiv;
7754         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7755         u32 coreclk, reg_val;
7756
7757         /* Enable Refclk */
7758         I915_WRITE(DPLL(pipe),
7759                    pipe_config->dpll_hw_state.dpll &
7760                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7761
7762         /* No need to actually set up the DPLL with DSI */
7763         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7764                 return;
7765
7766         mutex_lock(&dev_priv->sb_lock);
7767
7768         bestn = pipe_config->dpll.n;
7769         bestm1 = pipe_config->dpll.m1;
7770         bestm2 = pipe_config->dpll.m2;
7771         bestp1 = pipe_config->dpll.p1;
7772         bestp2 = pipe_config->dpll.p2;
7773
7774         /* See eDP HDMI DPIO driver vbios notes doc */
7775
7776         /* PLL B needs special handling */
7777         if (pipe == PIPE_B)
7778                 vlv_pllb_recal_opamp(dev_priv, pipe);
7779
7780         /* Set up Tx target for periodic Rcomp update */
7781         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7782
7783         /* Disable target IRef on PLL */
7784         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7785         reg_val &= 0x00ffffff;
7786         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7787
7788         /* Disable fast lock */
7789         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7790
7791         /* Set idtafcrecal before PLL is enabled */
7792         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7793         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7794         mdiv |= ((bestn << DPIO_N_SHIFT));
7795         mdiv |= (1 << DPIO_K_SHIFT);
7796
7797         /*
7798          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7799          * but we don't support that).
7800          * Note: don't use the DAC post divider as it seems unstable.
7801          */
7802         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7803         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7804
7805         mdiv |= DPIO_ENABLE_CALIBRATION;
7806         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7807
7808         /* Set HBR and RBR LPF coefficients */
7809         if (pipe_config->port_clock == 162000 ||
7810             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7811             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7812                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7813                                  0x009f0003);
7814         else
7815                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7816                                  0x00d0000f);
7817
7818         if (intel_crtc_has_dp_encoder(pipe_config)) {
7819                 /* Use SSC source */
7820                 if (pipe == PIPE_A)
7821                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7822                                          0x0df40000);
7823                 else
7824                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7825                                          0x0df70000);
7826         } else { /* HDMI or VGA */
7827                 /* Use bend source */
7828                 if (pipe == PIPE_A)
7829                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7830                                          0x0df70000);
7831                 else
7832                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7833                                          0x0df40000);
7834         }
7835
7836         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7837         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7838         if (intel_crtc_has_dp_encoder(crtc->config))
7839                 coreclk |= 0x01000000;
7840         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7841
7842         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7843         mutex_unlock(&dev_priv->sb_lock);
7844 }
7845
7846 static void chv_prepare_pll(struct intel_crtc *crtc,
7847                             const struct intel_crtc_state *pipe_config)
7848 {
7849         struct drm_device *dev = crtc->base.dev;
7850         struct drm_i915_private *dev_priv = to_i915(dev);
7851         enum pipe pipe = crtc->pipe;
7852         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7853         u32 loopfilter, tribuf_calcntr;
7854         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7855         u32 dpio_val;
7856         int vco;
7857
7858         /* Enable Refclk and SSC */
7859         I915_WRITE(DPLL(pipe),
7860                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7861
7862         /* No need to actually set up the DPLL with DSI */
7863         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7864                 return;
7865
7866         bestn = pipe_config->dpll.n;
7867         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7868         bestm1 = pipe_config->dpll.m1;
7869         bestm2 = pipe_config->dpll.m2 >> 22;
7870         bestp1 = pipe_config->dpll.p1;
7871         bestp2 = pipe_config->dpll.p2;
7872         vco = pipe_config->dpll.vco;
7873         dpio_val = 0;
7874         loopfilter = 0;
7875
7876         mutex_lock(&dev_priv->sb_lock);
7877
7878         /* p1 and p2 divider */
7879         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7880                         5 << DPIO_CHV_S1_DIV_SHIFT |
7881                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7882                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7883                         1 << DPIO_CHV_K_DIV_SHIFT);
7884
7885         /* Feedback post-divider - m2 */
7886         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7887
7888         /* Feedback refclk divider - n and m1 */
7889         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7890                         DPIO_CHV_M1_DIV_BY_2 |
7891                         1 << DPIO_CHV_N_DIV_SHIFT);
7892
7893         /* M2 fraction division */
7894         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7895
7896         /* M2 fraction division enable */
7897         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7898         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7899         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7900         if (bestm2_frac)
7901                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7902         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7903
7904         /* Program digital lock detect threshold */
7905         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7906         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7907                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7908         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7909         if (!bestm2_frac)
7910                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7911         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7912
7913         /* Loop filter */
7914         if (vco == 5400000) {
7915                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7916                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7917                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7918                 tribuf_calcntr = 0x9;
7919         } else if (vco <= 6200000) {
7920                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7921                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7922                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7923                 tribuf_calcntr = 0x9;
7924         } else if (vco <= 6480000) {
7925                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7926                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7927                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7928                 tribuf_calcntr = 0x8;
7929         } else {
7930                 /* Not supported. Apply the same limits as in the max case */
7931                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7932                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7933                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7934                 tribuf_calcntr = 0;
7935         }
7936         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7937
7938         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7939         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7940         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7941         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7942
7943         /* AFC Recal */
7944         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7945                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7946                         DPIO_AFC_RECAL);
7947
7948         mutex_unlock(&dev_priv->sb_lock);
7949 }
7950
7951 /**
7952  * vlv_force_pll_on - forcibly enable just the PLL
7953  * @dev_priv: i915 private structure
7954  * @pipe: pipe PLL to enable
7955  * @dpll: PLL configuration
7956  *
7957  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7958  * in cases where we need the PLL enabled even when @pipe is not going to
7959  * be enabled.
7960  */
7961 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7962                      const struct dpll *dpll)
7963 {
7964         struct intel_crtc *crtc =
7965                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7966         struct intel_crtc_state *pipe_config;
7967
7968         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7969         if (!pipe_config)
7970                 return -ENOMEM;
7971
7972         pipe_config->base.crtc = &crtc->base;
7973         pipe_config->pixel_multiplier = 1;
7974         pipe_config->dpll = *dpll;
7975
7976         if (IS_CHERRYVIEW(dev)) {
7977                 chv_compute_dpll(crtc, pipe_config);
7978                 chv_prepare_pll(crtc, pipe_config);
7979                 chv_enable_pll(crtc, pipe_config);
7980         } else {
7981                 vlv_compute_dpll(crtc, pipe_config);
7982                 vlv_prepare_pll(crtc, pipe_config);
7983                 vlv_enable_pll(crtc, pipe_config);
7984         }
7985
7986         kfree(pipe_config);
7987
7988         return 0;
7989 }
7990
7991 /**
7992  * vlv_force_pll_off - forcibly disable just the PLL
7993  * @dev_priv: i915 private structure
7994  * @pipe: pipe PLL to disable
7995  *
7996  * Disable the PLL for @pipe. To be used in cases where we need
7997  * the PLL enabled even when @pipe is not going to be enabled.
7998  */
7999 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8000 {
8001         if (IS_CHERRYVIEW(dev))
8002                 chv_disable_pll(to_i915(dev), pipe);
8003         else
8004                 vlv_disable_pll(to_i915(dev), pipe);
8005 }
8006
8007 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8008                               struct intel_crtc_state *crtc_state,
8009                               struct dpll *reduced_clock)
8010 {
8011         struct drm_device *dev = crtc->base.dev;
8012         struct drm_i915_private *dev_priv = to_i915(dev);
8013         u32 dpll;
8014         struct dpll *clock = &crtc_state->dpll;
8015
8016         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8017
8018         dpll = DPLL_VGA_MODE_DIS;
8019
8020         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8021                 dpll |= DPLLB_MODE_LVDS;
8022         else
8023                 dpll |= DPLLB_MODE_DAC_SERIAL;
8024
8025         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8026                 dpll |= (crtc_state->pixel_multiplier - 1)
8027                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8028         }
8029
8030         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8031             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8032                 dpll |= DPLL_SDVO_HIGH_SPEED;
8033
8034         if (intel_crtc_has_dp_encoder(crtc_state))
8035                 dpll |= DPLL_SDVO_HIGH_SPEED;
8036
8037         /* compute bitmask from p1 value */
8038         if (IS_PINEVIEW(dev))
8039                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8040         else {
8041                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8042                 if (IS_G4X(dev) && reduced_clock)
8043                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8044         }
8045         switch (clock->p2) {
8046         case 5:
8047                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8048                 break;
8049         case 7:
8050                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8051                 break;
8052         case 10:
8053                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8054                 break;
8055         case 14:
8056                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8057                 break;
8058         }
8059         if (INTEL_INFO(dev)->gen >= 4)
8060                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8061
8062         if (crtc_state->sdvo_tv_clock)
8063                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8064         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8065                  intel_panel_use_ssc(dev_priv))
8066                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8067         else
8068                 dpll |= PLL_REF_INPUT_DREFCLK;
8069
8070         dpll |= DPLL_VCO_ENABLE;
8071         crtc_state->dpll_hw_state.dpll = dpll;
8072
8073         if (INTEL_INFO(dev)->gen >= 4) {
8074                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8075                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8076                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8077         }
8078 }
8079
8080 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8081                               struct intel_crtc_state *crtc_state,
8082                               struct dpll *reduced_clock)
8083 {
8084         struct drm_device *dev = crtc->base.dev;
8085         struct drm_i915_private *dev_priv = to_i915(dev);
8086         u32 dpll;
8087         struct dpll *clock = &crtc_state->dpll;
8088
8089         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8090
8091         dpll = DPLL_VGA_MODE_DIS;
8092
8093         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8094                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8095         } else {
8096                 if (clock->p1 == 2)
8097                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8098                 else
8099                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8100                 if (clock->p2 == 4)
8101                         dpll |= PLL_P2_DIVIDE_BY_4;
8102         }
8103
8104         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8105                 dpll |= DPLL_DVO_2X_MODE;
8106
8107         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8108             intel_panel_use_ssc(dev_priv))
8109                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8110         else
8111                 dpll |= PLL_REF_INPUT_DREFCLK;
8112
8113         dpll |= DPLL_VCO_ENABLE;
8114         crtc_state->dpll_hw_state.dpll = dpll;
8115 }
8116
8117 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8118 {
8119         struct drm_device *dev = intel_crtc->base.dev;
8120         struct drm_i915_private *dev_priv = to_i915(dev);
8121         enum pipe pipe = intel_crtc->pipe;
8122         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8123         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8124         uint32_t crtc_vtotal, crtc_vblank_end;
8125         int vsyncshift = 0;
8126
8127         /* We need to be careful not to changed the adjusted mode, for otherwise
8128          * the hw state checker will get angry at the mismatch. */
8129         crtc_vtotal = adjusted_mode->crtc_vtotal;
8130         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8131
8132         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8133                 /* the chip adds 2 halflines automatically */
8134                 crtc_vtotal -= 1;
8135                 crtc_vblank_end -= 1;
8136
8137                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8138                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8139                 else
8140                         vsyncshift = adjusted_mode->crtc_hsync_start -
8141                                 adjusted_mode->crtc_htotal / 2;
8142                 if (vsyncshift < 0)
8143                         vsyncshift += adjusted_mode->crtc_htotal;
8144         }
8145
8146         if (INTEL_INFO(dev)->gen > 3)
8147                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8148
8149         I915_WRITE(HTOTAL(cpu_transcoder),
8150                    (adjusted_mode->crtc_hdisplay - 1) |
8151                    ((adjusted_mode->crtc_htotal - 1) << 16));
8152         I915_WRITE(HBLANK(cpu_transcoder),
8153                    (adjusted_mode->crtc_hblank_start - 1) |
8154                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8155         I915_WRITE(HSYNC(cpu_transcoder),
8156                    (adjusted_mode->crtc_hsync_start - 1) |
8157                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8158
8159         I915_WRITE(VTOTAL(cpu_transcoder),
8160                    (adjusted_mode->crtc_vdisplay - 1) |
8161                    ((crtc_vtotal - 1) << 16));
8162         I915_WRITE(VBLANK(cpu_transcoder),
8163                    (adjusted_mode->crtc_vblank_start - 1) |
8164                    ((crtc_vblank_end - 1) << 16));
8165         I915_WRITE(VSYNC(cpu_transcoder),
8166                    (adjusted_mode->crtc_vsync_start - 1) |
8167                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8168
8169         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8170          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8171          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8172          * bits. */
8173         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8174             (pipe == PIPE_B || pipe == PIPE_C))
8175                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8176
8177 }
8178
8179 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8180 {
8181         struct drm_device *dev = intel_crtc->base.dev;
8182         struct drm_i915_private *dev_priv = to_i915(dev);
8183         enum pipe pipe = intel_crtc->pipe;
8184
8185         /* pipesrc controls the size that is scaled from, which should
8186          * always be the user's requested size.
8187          */
8188         I915_WRITE(PIPESRC(pipe),
8189                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8190                    (intel_crtc->config->pipe_src_h - 1));
8191 }
8192
8193 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8194                                    struct intel_crtc_state *pipe_config)
8195 {
8196         struct drm_device *dev = crtc->base.dev;
8197         struct drm_i915_private *dev_priv = to_i915(dev);
8198         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8199         uint32_t tmp;
8200
8201         tmp = I915_READ(HTOTAL(cpu_transcoder));
8202         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8203         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8204         tmp = I915_READ(HBLANK(cpu_transcoder));
8205         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8206         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8207         tmp = I915_READ(HSYNC(cpu_transcoder));
8208         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8209         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8210
8211         tmp = I915_READ(VTOTAL(cpu_transcoder));
8212         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8213         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8214         tmp = I915_READ(VBLANK(cpu_transcoder));
8215         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8216         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8217         tmp = I915_READ(VSYNC(cpu_transcoder));
8218         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8219         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8220
8221         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8222                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8223                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8224                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8225         }
8226 }
8227
8228 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8229                                     struct intel_crtc_state *pipe_config)
8230 {
8231         struct drm_device *dev = crtc->base.dev;
8232         struct drm_i915_private *dev_priv = to_i915(dev);
8233         u32 tmp;
8234
8235         tmp = I915_READ(PIPESRC(crtc->pipe));
8236         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8237         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8238
8239         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8240         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8241 }
8242
8243 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8244                                  struct intel_crtc_state *pipe_config)
8245 {
8246         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8247         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8248         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8249         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8250
8251         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8252         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8253         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8254         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8255
8256         mode->flags = pipe_config->base.adjusted_mode.flags;
8257         mode->type = DRM_MODE_TYPE_DRIVER;
8258
8259         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8260         mode->flags |= pipe_config->base.adjusted_mode.flags;
8261
8262         mode->hsync = drm_mode_hsync(mode);
8263         mode->vrefresh = drm_mode_vrefresh(mode);
8264         drm_mode_set_name(mode);
8265 }
8266
8267 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8268 {
8269         struct drm_device *dev = intel_crtc->base.dev;
8270         struct drm_i915_private *dev_priv = to_i915(dev);
8271         uint32_t pipeconf;
8272
8273         pipeconf = 0;
8274
8275         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8276             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8277                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8278
8279         if (intel_crtc->config->double_wide)
8280                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8281
8282         /* only g4x and later have fancy bpc/dither controls */
8283         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8284                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8285                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8286                         pipeconf |= PIPECONF_DITHER_EN |
8287                                     PIPECONF_DITHER_TYPE_SP;
8288
8289                 switch (intel_crtc->config->pipe_bpp) {
8290                 case 18:
8291                         pipeconf |= PIPECONF_6BPC;
8292                         break;
8293                 case 24:
8294                         pipeconf |= PIPECONF_8BPC;
8295                         break;
8296                 case 30:
8297                         pipeconf |= PIPECONF_10BPC;
8298                         break;
8299                 default:
8300                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8301                         BUG();
8302                 }
8303         }
8304
8305         if (HAS_PIPE_CXSR(dev)) {
8306                 if (intel_crtc->lowfreq_avail) {
8307                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8308                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8309                 } else {
8310                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8311                 }
8312         }
8313
8314         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8315                 if (INTEL_INFO(dev)->gen < 4 ||
8316                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8317                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8318                 else
8319                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8320         } else
8321                 pipeconf |= PIPECONF_PROGRESSIVE;
8322
8323         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8324              intel_crtc->config->limited_color_range)
8325                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8326
8327         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8328         POSTING_READ(PIPECONF(intel_crtc->pipe));
8329 }
8330
8331 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8332                                    struct intel_crtc_state *crtc_state)
8333 {
8334         struct drm_device *dev = crtc->base.dev;
8335         struct drm_i915_private *dev_priv = to_i915(dev);
8336         const struct intel_limit *limit;
8337         int refclk = 48000;
8338
8339         memset(&crtc_state->dpll_hw_state, 0,
8340                sizeof(crtc_state->dpll_hw_state));
8341
8342         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8343                 if (intel_panel_use_ssc(dev_priv)) {
8344                         refclk = dev_priv->vbt.lvds_ssc_freq;
8345                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8346                 }
8347
8348                 limit = &intel_limits_i8xx_lvds;
8349         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8350                 limit = &intel_limits_i8xx_dvo;
8351         } else {
8352                 limit = &intel_limits_i8xx_dac;
8353         }
8354
8355         if (!crtc_state->clock_set &&
8356             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8357                                  refclk, NULL, &crtc_state->dpll)) {
8358                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8359                 return -EINVAL;
8360         }
8361
8362         i8xx_compute_dpll(crtc, crtc_state, NULL);
8363
8364         return 0;
8365 }
8366
8367 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8368                                   struct intel_crtc_state *crtc_state)
8369 {
8370         struct drm_device *dev = crtc->base.dev;
8371         struct drm_i915_private *dev_priv = to_i915(dev);
8372         const struct intel_limit *limit;
8373         int refclk = 96000;
8374
8375         memset(&crtc_state->dpll_hw_state, 0,
8376                sizeof(crtc_state->dpll_hw_state));
8377
8378         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8379                 if (intel_panel_use_ssc(dev_priv)) {
8380                         refclk = dev_priv->vbt.lvds_ssc_freq;
8381                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8382                 }
8383
8384                 if (intel_is_dual_link_lvds(dev))
8385                         limit = &intel_limits_g4x_dual_channel_lvds;
8386                 else
8387                         limit = &intel_limits_g4x_single_channel_lvds;
8388         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8389                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8390                 limit = &intel_limits_g4x_hdmi;
8391         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8392                 limit = &intel_limits_g4x_sdvo;
8393         } else {
8394                 /* The option is for other outputs */
8395                 limit = &intel_limits_i9xx_sdvo;
8396         }
8397
8398         if (!crtc_state->clock_set &&
8399             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8400                                 refclk, NULL, &crtc_state->dpll)) {
8401                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8402                 return -EINVAL;
8403         }
8404
8405         i9xx_compute_dpll(crtc, crtc_state, NULL);
8406
8407         return 0;
8408 }
8409
8410 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8411                                   struct intel_crtc_state *crtc_state)
8412 {
8413         struct drm_device *dev = crtc->base.dev;
8414         struct drm_i915_private *dev_priv = to_i915(dev);
8415         const struct intel_limit *limit;
8416         int refclk = 96000;
8417
8418         memset(&crtc_state->dpll_hw_state, 0,
8419                sizeof(crtc_state->dpll_hw_state));
8420
8421         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8422                 if (intel_panel_use_ssc(dev_priv)) {
8423                         refclk = dev_priv->vbt.lvds_ssc_freq;
8424                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8425                 }
8426
8427                 limit = &intel_limits_pineview_lvds;
8428         } else {
8429                 limit = &intel_limits_pineview_sdvo;
8430         }
8431
8432         if (!crtc_state->clock_set &&
8433             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8434                                 refclk, NULL, &crtc_state->dpll)) {
8435                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8436                 return -EINVAL;
8437         }
8438
8439         i9xx_compute_dpll(crtc, crtc_state, NULL);
8440
8441         return 0;
8442 }
8443
8444 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8445                                    struct intel_crtc_state *crtc_state)
8446 {
8447         struct drm_device *dev = crtc->base.dev;
8448         struct drm_i915_private *dev_priv = to_i915(dev);
8449         const struct intel_limit *limit;
8450         int refclk = 96000;
8451
8452         memset(&crtc_state->dpll_hw_state, 0,
8453                sizeof(crtc_state->dpll_hw_state));
8454
8455         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8456                 if (intel_panel_use_ssc(dev_priv)) {
8457                         refclk = dev_priv->vbt.lvds_ssc_freq;
8458                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8459                 }
8460
8461                 limit = &intel_limits_i9xx_lvds;
8462         } else {
8463                 limit = &intel_limits_i9xx_sdvo;
8464         }
8465
8466         if (!crtc_state->clock_set &&
8467             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8468                                  refclk, NULL, &crtc_state->dpll)) {
8469                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8470                 return -EINVAL;
8471         }
8472
8473         i9xx_compute_dpll(crtc, crtc_state, NULL);
8474
8475         return 0;
8476 }
8477
8478 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8479                                   struct intel_crtc_state *crtc_state)
8480 {
8481         int refclk = 100000;
8482         const struct intel_limit *limit = &intel_limits_chv;
8483
8484         memset(&crtc_state->dpll_hw_state, 0,
8485                sizeof(crtc_state->dpll_hw_state));
8486
8487         if (!crtc_state->clock_set &&
8488             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8489                                 refclk, NULL, &crtc_state->dpll)) {
8490                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8491                 return -EINVAL;
8492         }
8493
8494         chv_compute_dpll(crtc, crtc_state);
8495
8496         return 0;
8497 }
8498
8499 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8500                                   struct intel_crtc_state *crtc_state)
8501 {
8502         int refclk = 100000;
8503         const struct intel_limit *limit = &intel_limits_vlv;
8504
8505         memset(&crtc_state->dpll_hw_state, 0,
8506                sizeof(crtc_state->dpll_hw_state));
8507
8508         if (!crtc_state->clock_set &&
8509             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8510                                 refclk, NULL, &crtc_state->dpll)) {
8511                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8512                 return -EINVAL;
8513         }
8514
8515         vlv_compute_dpll(crtc, crtc_state);
8516
8517         return 0;
8518 }
8519
8520 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8521                                  struct intel_crtc_state *pipe_config)
8522 {
8523         struct drm_device *dev = crtc->base.dev;
8524         struct drm_i915_private *dev_priv = to_i915(dev);
8525         uint32_t tmp;
8526
8527         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8528                 return;
8529
8530         tmp = I915_READ(PFIT_CONTROL);
8531         if (!(tmp & PFIT_ENABLE))
8532                 return;
8533
8534         /* Check whether the pfit is attached to our pipe. */
8535         if (INTEL_INFO(dev)->gen < 4) {
8536                 if (crtc->pipe != PIPE_B)
8537                         return;
8538         } else {
8539                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8540                         return;
8541         }
8542
8543         pipe_config->gmch_pfit.control = tmp;
8544         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8545 }
8546
8547 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8548                                struct intel_crtc_state *pipe_config)
8549 {
8550         struct drm_device *dev = crtc->base.dev;
8551         struct drm_i915_private *dev_priv = to_i915(dev);
8552         int pipe = pipe_config->cpu_transcoder;
8553         struct dpll clock;
8554         u32 mdiv;
8555         int refclk = 100000;
8556
8557         /* In case of DSI, DPLL will not be used */
8558         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8559                 return;
8560
8561         mutex_lock(&dev_priv->sb_lock);
8562         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8563         mutex_unlock(&dev_priv->sb_lock);
8564
8565         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8566         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8567         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8568         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8569         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8570
8571         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8572 }
8573
8574 static void
8575 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8576                               struct intel_initial_plane_config *plane_config)
8577 {
8578         struct drm_device *dev = crtc->base.dev;
8579         struct drm_i915_private *dev_priv = to_i915(dev);
8580         u32 val, base, offset;
8581         int pipe = crtc->pipe, plane = crtc->plane;
8582         int fourcc, pixel_format;
8583         unsigned int aligned_height;
8584         struct drm_framebuffer *fb;
8585         struct intel_framebuffer *intel_fb;
8586
8587         val = I915_READ(DSPCNTR(plane));
8588         if (!(val & DISPLAY_PLANE_ENABLE))
8589                 return;
8590
8591         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8592         if (!intel_fb) {
8593                 DRM_DEBUG_KMS("failed to alloc fb\n");
8594                 return;
8595         }
8596
8597         fb = &intel_fb->base;
8598
8599         if (INTEL_INFO(dev)->gen >= 4) {
8600                 if (val & DISPPLANE_TILED) {
8601                         plane_config->tiling = I915_TILING_X;
8602                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8603                 }
8604         }
8605
8606         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8607         fourcc = i9xx_format_to_fourcc(pixel_format);
8608         fb->pixel_format = fourcc;
8609         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8610
8611         if (INTEL_INFO(dev)->gen >= 4) {
8612                 if (plane_config->tiling)
8613                         offset = I915_READ(DSPTILEOFF(plane));
8614                 else
8615                         offset = I915_READ(DSPLINOFF(plane));
8616                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8617         } else {
8618                 base = I915_READ(DSPADDR(plane));
8619         }
8620         plane_config->base = base;
8621
8622         val = I915_READ(PIPESRC(pipe));
8623         fb->width = ((val >> 16) & 0xfff) + 1;
8624         fb->height = ((val >> 0) & 0xfff) + 1;
8625
8626         val = I915_READ(DSPSTRIDE(pipe));
8627         fb->pitches[0] = val & 0xffffffc0;
8628
8629         aligned_height = intel_fb_align_height(dev, fb->height,
8630                                                fb->pixel_format,
8631                                                fb->modifier[0]);
8632
8633         plane_config->size = fb->pitches[0] * aligned_height;
8634
8635         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8636                       pipe_name(pipe), plane, fb->width, fb->height,
8637                       fb->bits_per_pixel, base, fb->pitches[0],
8638                       plane_config->size);
8639
8640         plane_config->fb = intel_fb;
8641 }
8642
8643 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8644                                struct intel_crtc_state *pipe_config)
8645 {
8646         struct drm_device *dev = crtc->base.dev;
8647         struct drm_i915_private *dev_priv = to_i915(dev);
8648         int pipe = pipe_config->cpu_transcoder;
8649         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8650         struct dpll clock;
8651         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8652         int refclk = 100000;
8653
8654         /* In case of DSI, DPLL will not be used */
8655         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8656                 return;
8657
8658         mutex_lock(&dev_priv->sb_lock);
8659         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8660         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8661         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8662         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8663         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8664         mutex_unlock(&dev_priv->sb_lock);
8665
8666         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8667         clock.m2 = (pll_dw0 & 0xff) << 22;
8668         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8669                 clock.m2 |= pll_dw2 & 0x3fffff;
8670         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8671         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8672         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8673
8674         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8675 }
8676
8677 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8678                                  struct intel_crtc_state *pipe_config)
8679 {
8680         struct drm_device *dev = crtc->base.dev;
8681         struct drm_i915_private *dev_priv = to_i915(dev);
8682         enum intel_display_power_domain power_domain;
8683         uint32_t tmp;
8684         bool ret;
8685
8686         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8687         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8688                 return false;
8689
8690         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8691         pipe_config->shared_dpll = NULL;
8692
8693         ret = false;
8694
8695         tmp = I915_READ(PIPECONF(crtc->pipe));
8696         if (!(tmp & PIPECONF_ENABLE))
8697                 goto out;
8698
8699         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8700                 switch (tmp & PIPECONF_BPC_MASK) {
8701                 case PIPECONF_6BPC:
8702                         pipe_config->pipe_bpp = 18;
8703                         break;
8704                 case PIPECONF_8BPC:
8705                         pipe_config->pipe_bpp = 24;
8706                         break;
8707                 case PIPECONF_10BPC:
8708                         pipe_config->pipe_bpp = 30;
8709                         break;
8710                 default:
8711                         break;
8712                 }
8713         }
8714
8715         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8716             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8717                 pipe_config->limited_color_range = true;
8718
8719         if (INTEL_INFO(dev)->gen < 4)
8720                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8721
8722         intel_get_pipe_timings(crtc, pipe_config);
8723         intel_get_pipe_src_size(crtc, pipe_config);
8724
8725         i9xx_get_pfit_config(crtc, pipe_config);
8726
8727         if (INTEL_INFO(dev)->gen >= 4) {
8728                 /* No way to read it out on pipes B and C */
8729                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8730                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8731                 else
8732                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8733                 pipe_config->pixel_multiplier =
8734                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8735                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8736                 pipe_config->dpll_hw_state.dpll_md = tmp;
8737         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8738                 tmp = I915_READ(DPLL(crtc->pipe));
8739                 pipe_config->pixel_multiplier =
8740                         ((tmp & SDVO_MULTIPLIER_MASK)
8741                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8742         } else {
8743                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8744                  * port and will be fixed up in the encoder->get_config
8745                  * function. */
8746                 pipe_config->pixel_multiplier = 1;
8747         }
8748         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8749         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8750                 /*
8751                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8752                  * on 830. Filter it out here so that we don't
8753                  * report errors due to that.
8754                  */
8755                 if (IS_I830(dev))
8756                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8757
8758                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8759                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8760         } else {
8761                 /* Mask out read-only status bits. */
8762                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8763                                                      DPLL_PORTC_READY_MASK |
8764                                                      DPLL_PORTB_READY_MASK);
8765         }
8766
8767         if (IS_CHERRYVIEW(dev))
8768                 chv_crtc_clock_get(crtc, pipe_config);
8769         else if (IS_VALLEYVIEW(dev))
8770                 vlv_crtc_clock_get(crtc, pipe_config);
8771         else
8772                 i9xx_crtc_clock_get(crtc, pipe_config);
8773
8774         /*
8775          * Normally the dotclock is filled in by the encoder .get_config()
8776          * but in case the pipe is enabled w/o any ports we need a sane
8777          * default.
8778          */
8779         pipe_config->base.adjusted_mode.crtc_clock =
8780                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8781
8782         ret = true;
8783
8784 out:
8785         intel_display_power_put(dev_priv, power_domain);
8786
8787         return ret;
8788 }
8789
8790 static void ironlake_init_pch_refclk(struct drm_device *dev)
8791 {
8792         struct drm_i915_private *dev_priv = to_i915(dev);
8793         struct intel_encoder *encoder;
8794         int i;
8795         u32 val, final;
8796         bool has_lvds = false;
8797         bool has_cpu_edp = false;
8798         bool has_panel = false;
8799         bool has_ck505 = false;
8800         bool can_ssc = false;
8801         bool using_ssc_source = false;
8802
8803         /* We need to take the global config into account */
8804         for_each_intel_encoder(dev, encoder) {
8805                 switch (encoder->type) {
8806                 case INTEL_OUTPUT_LVDS:
8807                         has_panel = true;
8808                         has_lvds = true;
8809                         break;
8810                 case INTEL_OUTPUT_EDP:
8811                         has_panel = true;
8812                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8813                                 has_cpu_edp = true;
8814                         break;
8815                 default:
8816                         break;
8817                 }
8818         }
8819
8820         if (HAS_PCH_IBX(dev)) {
8821                 has_ck505 = dev_priv->vbt.display_clock_mode;
8822                 can_ssc = has_ck505;
8823         } else {
8824                 has_ck505 = false;
8825                 can_ssc = true;
8826         }
8827
8828         /* Check if any DPLLs are using the SSC source */
8829         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8830                 u32 temp = I915_READ(PCH_DPLL(i));
8831
8832                 if (!(temp & DPLL_VCO_ENABLE))
8833                         continue;
8834
8835                 if ((temp & PLL_REF_INPUT_MASK) ==
8836                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8837                         using_ssc_source = true;
8838                         break;
8839                 }
8840         }
8841
8842         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8843                       has_panel, has_lvds, has_ck505, using_ssc_source);
8844
8845         /* Ironlake: try to setup display ref clock before DPLL
8846          * enabling. This is only under driver's control after
8847          * PCH B stepping, previous chipset stepping should be
8848          * ignoring this setting.
8849          */
8850         val = I915_READ(PCH_DREF_CONTROL);
8851
8852         /* As we must carefully and slowly disable/enable each source in turn,
8853          * compute the final state we want first and check if we need to
8854          * make any changes at all.
8855          */
8856         final = val;
8857         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8858         if (has_ck505)
8859                 final |= DREF_NONSPREAD_CK505_ENABLE;
8860         else
8861                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8862
8863         final &= ~DREF_SSC_SOURCE_MASK;
8864         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8865         final &= ~DREF_SSC1_ENABLE;
8866
8867         if (has_panel) {
8868                 final |= DREF_SSC_SOURCE_ENABLE;
8869
8870                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8871                         final |= DREF_SSC1_ENABLE;
8872
8873                 if (has_cpu_edp) {
8874                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8875                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8876                         else
8877                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8878                 } else
8879                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8880         } else if (using_ssc_source) {
8881                 final |= DREF_SSC_SOURCE_ENABLE;
8882                 final |= DREF_SSC1_ENABLE;
8883         }
8884
8885         if (final == val)
8886                 return;
8887
8888         /* Always enable nonspread source */
8889         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8890
8891         if (has_ck505)
8892                 val |= DREF_NONSPREAD_CK505_ENABLE;
8893         else
8894                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8895
8896         if (has_panel) {
8897                 val &= ~DREF_SSC_SOURCE_MASK;
8898                 val |= DREF_SSC_SOURCE_ENABLE;
8899
8900                 /* SSC must be turned on before enabling the CPU output  */
8901                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8902                         DRM_DEBUG_KMS("Using SSC on panel\n");
8903                         val |= DREF_SSC1_ENABLE;
8904                 } else
8905                         val &= ~DREF_SSC1_ENABLE;
8906
8907                 /* Get SSC going before enabling the outputs */
8908                 I915_WRITE(PCH_DREF_CONTROL, val);
8909                 POSTING_READ(PCH_DREF_CONTROL);
8910                 udelay(200);
8911
8912                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8913
8914                 /* Enable CPU source on CPU attached eDP */
8915                 if (has_cpu_edp) {
8916                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8917                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8918                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8919                         } else
8920                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8921                 } else
8922                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8923
8924                 I915_WRITE(PCH_DREF_CONTROL, val);
8925                 POSTING_READ(PCH_DREF_CONTROL);
8926                 udelay(200);
8927         } else {
8928                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8929
8930                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8931
8932                 /* Turn off CPU output */
8933                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8934
8935                 I915_WRITE(PCH_DREF_CONTROL, val);
8936                 POSTING_READ(PCH_DREF_CONTROL);
8937                 udelay(200);
8938
8939                 if (!using_ssc_source) {
8940                         DRM_DEBUG_KMS("Disabling SSC source\n");
8941
8942                         /* Turn off the SSC source */
8943                         val &= ~DREF_SSC_SOURCE_MASK;
8944                         val |= DREF_SSC_SOURCE_DISABLE;
8945
8946                         /* Turn off SSC1 */
8947                         val &= ~DREF_SSC1_ENABLE;
8948
8949                         I915_WRITE(PCH_DREF_CONTROL, val);
8950                         POSTING_READ(PCH_DREF_CONTROL);
8951                         udelay(200);
8952                 }
8953         }
8954
8955         BUG_ON(val != final);
8956 }
8957
8958 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8959 {
8960         uint32_t tmp;
8961
8962         tmp = I915_READ(SOUTH_CHICKEN2);
8963         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8964         I915_WRITE(SOUTH_CHICKEN2, tmp);
8965
8966         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8967                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8968                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8969
8970         tmp = I915_READ(SOUTH_CHICKEN2);
8971         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8972         I915_WRITE(SOUTH_CHICKEN2, tmp);
8973
8974         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8975                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8976                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8977 }
8978
8979 /* WaMPhyProgramming:hsw */
8980 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8981 {
8982         uint32_t tmp;
8983
8984         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8985         tmp &= ~(0xFF << 24);
8986         tmp |= (0x12 << 24);
8987         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8988
8989         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8990         tmp |= (1 << 11);
8991         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8992
8993         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8994         tmp |= (1 << 11);
8995         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8996
8997         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8998         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8999         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9000
9001         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9002         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9003         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9004
9005         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9006         tmp &= ~(7 << 13);
9007         tmp |= (5 << 13);
9008         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9009
9010         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9011         tmp &= ~(7 << 13);
9012         tmp |= (5 << 13);
9013         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9014
9015         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9016         tmp &= ~0xFF;
9017         tmp |= 0x1C;
9018         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9019
9020         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9021         tmp &= ~0xFF;
9022         tmp |= 0x1C;
9023         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9024
9025         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9026         tmp &= ~(0xFF << 16);
9027         tmp |= (0x1C << 16);
9028         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9029
9030         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9031         tmp &= ~(0xFF << 16);
9032         tmp |= (0x1C << 16);
9033         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9034
9035         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9036         tmp |= (1 << 27);
9037         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9038
9039         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9040         tmp |= (1 << 27);
9041         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9042
9043         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9044         tmp &= ~(0xF << 28);
9045         tmp |= (4 << 28);
9046         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9047
9048         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9049         tmp &= ~(0xF << 28);
9050         tmp |= (4 << 28);
9051         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9052 }
9053
9054 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9055  * Programming" based on the parameters passed:
9056  * - Sequence to enable CLKOUT_DP
9057  * - Sequence to enable CLKOUT_DP without spread
9058  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9059  */
9060 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9061                                  bool with_fdi)
9062 {
9063         struct drm_i915_private *dev_priv = to_i915(dev);
9064         uint32_t reg, tmp;
9065
9066         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9067                 with_spread = true;
9068         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9069                 with_fdi = false;
9070
9071         mutex_lock(&dev_priv->sb_lock);
9072
9073         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9074         tmp &= ~SBI_SSCCTL_DISABLE;
9075         tmp |= SBI_SSCCTL_PATHALT;
9076         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9077
9078         udelay(24);
9079
9080         if (with_spread) {
9081                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9082                 tmp &= ~SBI_SSCCTL_PATHALT;
9083                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9084
9085                 if (with_fdi) {
9086                         lpt_reset_fdi_mphy(dev_priv);
9087                         lpt_program_fdi_mphy(dev_priv);
9088                 }
9089         }
9090
9091         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9092         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9093         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9094         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9095
9096         mutex_unlock(&dev_priv->sb_lock);
9097 }
9098
9099 /* Sequence to disable CLKOUT_DP */
9100 static void lpt_disable_clkout_dp(struct drm_device *dev)
9101 {
9102         struct drm_i915_private *dev_priv = to_i915(dev);
9103         uint32_t reg, tmp;
9104
9105         mutex_lock(&dev_priv->sb_lock);
9106
9107         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9108         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9109         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9110         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9111
9112         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9113         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9114                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9115                         tmp |= SBI_SSCCTL_PATHALT;
9116                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9117                         udelay(32);
9118                 }
9119                 tmp |= SBI_SSCCTL_DISABLE;
9120                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9121         }
9122
9123         mutex_unlock(&dev_priv->sb_lock);
9124 }
9125
9126 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9127
9128 static const uint16_t sscdivintphase[] = {
9129         [BEND_IDX( 50)] = 0x3B23,
9130         [BEND_IDX( 45)] = 0x3B23,
9131         [BEND_IDX( 40)] = 0x3C23,
9132         [BEND_IDX( 35)] = 0x3C23,
9133         [BEND_IDX( 30)] = 0x3D23,
9134         [BEND_IDX( 25)] = 0x3D23,
9135         [BEND_IDX( 20)] = 0x3E23,
9136         [BEND_IDX( 15)] = 0x3E23,
9137         [BEND_IDX( 10)] = 0x3F23,
9138         [BEND_IDX(  5)] = 0x3F23,
9139         [BEND_IDX(  0)] = 0x0025,
9140         [BEND_IDX( -5)] = 0x0025,
9141         [BEND_IDX(-10)] = 0x0125,
9142         [BEND_IDX(-15)] = 0x0125,
9143         [BEND_IDX(-20)] = 0x0225,
9144         [BEND_IDX(-25)] = 0x0225,
9145         [BEND_IDX(-30)] = 0x0325,
9146         [BEND_IDX(-35)] = 0x0325,
9147         [BEND_IDX(-40)] = 0x0425,
9148         [BEND_IDX(-45)] = 0x0425,
9149         [BEND_IDX(-50)] = 0x0525,
9150 };
9151
9152 /*
9153  * Bend CLKOUT_DP
9154  * steps -50 to 50 inclusive, in steps of 5
9155  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9156  * change in clock period = -(steps / 10) * 5.787 ps
9157  */
9158 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9159 {
9160         uint32_t tmp;
9161         int idx = BEND_IDX(steps);
9162
9163         if (WARN_ON(steps % 5 != 0))
9164                 return;
9165
9166         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9167                 return;
9168
9169         mutex_lock(&dev_priv->sb_lock);
9170
9171         if (steps % 10 != 0)
9172                 tmp = 0xAAAAAAAB;
9173         else
9174                 tmp = 0x00000000;
9175         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9176
9177         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9178         tmp &= 0xffff0000;
9179         tmp |= sscdivintphase[idx];
9180         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9181
9182         mutex_unlock(&dev_priv->sb_lock);
9183 }
9184
9185 #undef BEND_IDX
9186
9187 static void lpt_init_pch_refclk(struct drm_device *dev)
9188 {
9189         struct intel_encoder *encoder;
9190         bool has_vga = false;
9191
9192         for_each_intel_encoder(dev, encoder) {
9193                 switch (encoder->type) {
9194                 case INTEL_OUTPUT_ANALOG:
9195                         has_vga = true;
9196                         break;
9197                 default:
9198                         break;
9199                 }
9200         }
9201
9202         if (has_vga) {
9203                 lpt_bend_clkout_dp(to_i915(dev), 0);
9204                 lpt_enable_clkout_dp(dev, true, true);
9205         } else {
9206                 lpt_disable_clkout_dp(dev);
9207         }
9208 }
9209
9210 /*
9211  * Initialize reference clocks when the driver loads
9212  */
9213 void intel_init_pch_refclk(struct drm_device *dev)
9214 {
9215         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9216                 ironlake_init_pch_refclk(dev);
9217         else if (HAS_PCH_LPT(dev))
9218                 lpt_init_pch_refclk(dev);
9219 }
9220
9221 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9222 {
9223         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9225         int pipe = intel_crtc->pipe;
9226         uint32_t val;
9227
9228         val = 0;
9229
9230         switch (intel_crtc->config->pipe_bpp) {
9231         case 18:
9232                 val |= PIPECONF_6BPC;
9233                 break;
9234         case 24:
9235                 val |= PIPECONF_8BPC;
9236                 break;
9237         case 30:
9238                 val |= PIPECONF_10BPC;
9239                 break;
9240         case 36:
9241                 val |= PIPECONF_12BPC;
9242                 break;
9243         default:
9244                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9245                 BUG();
9246         }
9247
9248         if (intel_crtc->config->dither)
9249                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9250
9251         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9252                 val |= PIPECONF_INTERLACED_ILK;
9253         else
9254                 val |= PIPECONF_PROGRESSIVE;
9255
9256         if (intel_crtc->config->limited_color_range)
9257                 val |= PIPECONF_COLOR_RANGE_SELECT;
9258
9259         I915_WRITE(PIPECONF(pipe), val);
9260         POSTING_READ(PIPECONF(pipe));
9261 }
9262
9263 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9264 {
9265         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9267         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9268         u32 val = 0;
9269
9270         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9271                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9272
9273         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9274                 val |= PIPECONF_INTERLACED_ILK;
9275         else
9276                 val |= PIPECONF_PROGRESSIVE;
9277
9278         I915_WRITE(PIPECONF(cpu_transcoder), val);
9279         POSTING_READ(PIPECONF(cpu_transcoder));
9280 }
9281
9282 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9283 {
9284         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9286
9287         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9288                 u32 val = 0;
9289
9290                 switch (intel_crtc->config->pipe_bpp) {
9291                 case 18:
9292                         val |= PIPEMISC_DITHER_6_BPC;
9293                         break;
9294                 case 24:
9295                         val |= PIPEMISC_DITHER_8_BPC;
9296                         break;
9297                 case 30:
9298                         val |= PIPEMISC_DITHER_10_BPC;
9299                         break;
9300                 case 36:
9301                         val |= PIPEMISC_DITHER_12_BPC;
9302                         break;
9303                 default:
9304                         /* Case prevented by pipe_config_set_bpp. */
9305                         BUG();
9306                 }
9307
9308                 if (intel_crtc->config->dither)
9309                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9310
9311                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9312         }
9313 }
9314
9315 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9316 {
9317         /*
9318          * Account for spread spectrum to avoid
9319          * oversubscribing the link. Max center spread
9320          * is 2.5%; use 5% for safety's sake.
9321          */
9322         u32 bps = target_clock * bpp * 21 / 20;
9323         return DIV_ROUND_UP(bps, link_bw * 8);
9324 }
9325
9326 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9327 {
9328         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9329 }
9330
9331 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9332                                   struct intel_crtc_state *crtc_state,
9333                                   struct dpll *reduced_clock)
9334 {
9335         struct drm_crtc *crtc = &intel_crtc->base;
9336         struct drm_device *dev = crtc->dev;
9337         struct drm_i915_private *dev_priv = to_i915(dev);
9338         u32 dpll, fp, fp2;
9339         int factor;
9340
9341         /* Enable autotuning of the PLL clock (if permissible) */
9342         factor = 21;
9343         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9344                 if ((intel_panel_use_ssc(dev_priv) &&
9345                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9346                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9347                         factor = 25;
9348         } else if (crtc_state->sdvo_tv_clock)
9349                 factor = 20;
9350
9351         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9352
9353         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9354                 fp |= FP_CB_TUNE;
9355
9356         if (reduced_clock) {
9357                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9358
9359                 if (reduced_clock->m < factor * reduced_clock->n)
9360                         fp2 |= FP_CB_TUNE;
9361         } else {
9362                 fp2 = fp;
9363         }
9364
9365         dpll = 0;
9366
9367         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9368                 dpll |= DPLLB_MODE_LVDS;
9369         else
9370                 dpll |= DPLLB_MODE_DAC_SERIAL;
9371
9372         dpll |= (crtc_state->pixel_multiplier - 1)
9373                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9374
9375         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9376             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9377                 dpll |= DPLL_SDVO_HIGH_SPEED;
9378
9379         if (intel_crtc_has_dp_encoder(crtc_state))
9380                 dpll |= DPLL_SDVO_HIGH_SPEED;
9381
9382         /* compute bitmask from p1 value */
9383         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9384         /* also FPA1 */
9385         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9386
9387         switch (crtc_state->dpll.p2) {
9388         case 5:
9389                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9390                 break;
9391         case 7:
9392                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9393                 break;
9394         case 10:
9395                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9396                 break;
9397         case 14:
9398                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9399                 break;
9400         }
9401
9402         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9403             intel_panel_use_ssc(dev_priv))
9404                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9405         else
9406                 dpll |= PLL_REF_INPUT_DREFCLK;
9407
9408         dpll |= DPLL_VCO_ENABLE;
9409
9410         crtc_state->dpll_hw_state.dpll = dpll;
9411         crtc_state->dpll_hw_state.fp0 = fp;
9412         crtc_state->dpll_hw_state.fp1 = fp2;
9413 }
9414
9415 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9416                                        struct intel_crtc_state *crtc_state)
9417 {
9418         struct drm_device *dev = crtc->base.dev;
9419         struct drm_i915_private *dev_priv = to_i915(dev);
9420         struct dpll reduced_clock;
9421         bool has_reduced_clock = false;
9422         struct intel_shared_dpll *pll;
9423         const struct intel_limit *limit;
9424         int refclk = 120000;
9425
9426         memset(&crtc_state->dpll_hw_state, 0,
9427                sizeof(crtc_state->dpll_hw_state));
9428
9429         crtc->lowfreq_avail = false;
9430
9431         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9432         if (!crtc_state->has_pch_encoder)
9433                 return 0;
9434
9435         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9436                 if (intel_panel_use_ssc(dev_priv)) {
9437                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9438                                       dev_priv->vbt.lvds_ssc_freq);
9439                         refclk = dev_priv->vbt.lvds_ssc_freq;
9440                 }
9441
9442                 if (intel_is_dual_link_lvds(dev)) {
9443                         if (refclk == 100000)
9444                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9445                         else
9446                                 limit = &intel_limits_ironlake_dual_lvds;
9447                 } else {
9448                         if (refclk == 100000)
9449                                 limit = &intel_limits_ironlake_single_lvds_100m;
9450                         else
9451                                 limit = &intel_limits_ironlake_single_lvds;
9452                 }
9453         } else {
9454                 limit = &intel_limits_ironlake_dac;
9455         }
9456
9457         if (!crtc_state->clock_set &&
9458             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9459                                 refclk, NULL, &crtc_state->dpll)) {
9460                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9461                 return -EINVAL;
9462         }
9463
9464         ironlake_compute_dpll(crtc, crtc_state,
9465                               has_reduced_clock ? &reduced_clock : NULL);
9466
9467         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9468         if (pll == NULL) {
9469                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9470                                  pipe_name(crtc->pipe));
9471                 return -EINVAL;
9472         }
9473
9474         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9475             has_reduced_clock)
9476                 crtc->lowfreq_avail = true;
9477
9478         return 0;
9479 }
9480
9481 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9482                                          struct intel_link_m_n *m_n)
9483 {
9484         struct drm_device *dev = crtc->base.dev;
9485         struct drm_i915_private *dev_priv = to_i915(dev);
9486         enum pipe pipe = crtc->pipe;
9487
9488         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9489         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9490         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9491                 & ~TU_SIZE_MASK;
9492         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9493         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9494                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9495 }
9496
9497 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9498                                          enum transcoder transcoder,
9499                                          struct intel_link_m_n *m_n,
9500                                          struct intel_link_m_n *m2_n2)
9501 {
9502         struct drm_device *dev = crtc->base.dev;
9503         struct drm_i915_private *dev_priv = to_i915(dev);
9504         enum pipe pipe = crtc->pipe;
9505
9506         if (INTEL_INFO(dev)->gen >= 5) {
9507                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9508                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9509                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9510                         & ~TU_SIZE_MASK;
9511                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9512                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9513                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9514                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9515                  * gen < 8) and if DRRS is supported (to make sure the
9516                  * registers are not unnecessarily read).
9517                  */
9518                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9519                         crtc->config->has_drrs) {
9520                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9521                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9522                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9523                                         & ~TU_SIZE_MASK;
9524                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9525                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9526                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9527                 }
9528         } else {
9529                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9530                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9531                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9532                         & ~TU_SIZE_MASK;
9533                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9534                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9535                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9536         }
9537 }
9538
9539 void intel_dp_get_m_n(struct intel_crtc *crtc,
9540                       struct intel_crtc_state *pipe_config)
9541 {
9542         if (pipe_config->has_pch_encoder)
9543                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9544         else
9545                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9546                                              &pipe_config->dp_m_n,
9547                                              &pipe_config->dp_m2_n2);
9548 }
9549
9550 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9551                                         struct intel_crtc_state *pipe_config)
9552 {
9553         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9554                                      &pipe_config->fdi_m_n, NULL);
9555 }
9556
9557 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9558                                     struct intel_crtc_state *pipe_config)
9559 {
9560         struct drm_device *dev = crtc->base.dev;
9561         struct drm_i915_private *dev_priv = to_i915(dev);
9562         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9563         uint32_t ps_ctrl = 0;
9564         int id = -1;
9565         int i;
9566
9567         /* find scaler attached to this pipe */
9568         for (i = 0; i < crtc->num_scalers; i++) {
9569                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9570                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9571                         id = i;
9572                         pipe_config->pch_pfit.enabled = true;
9573                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9574                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9575                         break;
9576                 }
9577         }
9578
9579         scaler_state->scaler_id = id;
9580         if (id >= 0) {
9581                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9582         } else {
9583                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9584         }
9585 }
9586
9587 static void
9588 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9589                                  struct intel_initial_plane_config *plane_config)
9590 {
9591         struct drm_device *dev = crtc->base.dev;
9592         struct drm_i915_private *dev_priv = to_i915(dev);
9593         u32 val, base, offset, stride_mult, tiling;
9594         int pipe = crtc->pipe;
9595         int fourcc, pixel_format;
9596         unsigned int aligned_height;
9597         struct drm_framebuffer *fb;
9598         struct intel_framebuffer *intel_fb;
9599
9600         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9601         if (!intel_fb) {
9602                 DRM_DEBUG_KMS("failed to alloc fb\n");
9603                 return;
9604         }
9605
9606         fb = &intel_fb->base;
9607
9608         val = I915_READ(PLANE_CTL(pipe, 0));
9609         if (!(val & PLANE_CTL_ENABLE))
9610                 goto error;
9611
9612         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9613         fourcc = skl_format_to_fourcc(pixel_format,
9614                                       val & PLANE_CTL_ORDER_RGBX,
9615                                       val & PLANE_CTL_ALPHA_MASK);
9616         fb->pixel_format = fourcc;
9617         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9618
9619         tiling = val & PLANE_CTL_TILED_MASK;
9620         switch (tiling) {
9621         case PLANE_CTL_TILED_LINEAR:
9622                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9623                 break;
9624         case PLANE_CTL_TILED_X:
9625                 plane_config->tiling = I915_TILING_X;
9626                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9627                 break;
9628         case PLANE_CTL_TILED_Y:
9629                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9630                 break;
9631         case PLANE_CTL_TILED_YF:
9632                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9633                 break;
9634         default:
9635                 MISSING_CASE(tiling);
9636                 goto error;
9637         }
9638
9639         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9640         plane_config->base = base;
9641
9642         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9643
9644         val = I915_READ(PLANE_SIZE(pipe, 0));
9645         fb->height = ((val >> 16) & 0xfff) + 1;
9646         fb->width = ((val >> 0) & 0x1fff) + 1;
9647
9648         val = I915_READ(PLANE_STRIDE(pipe, 0));
9649         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9650                                                 fb->pixel_format);
9651         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9652
9653         aligned_height = intel_fb_align_height(dev, fb->height,
9654                                                fb->pixel_format,
9655                                                fb->modifier[0]);
9656
9657         plane_config->size = fb->pitches[0] * aligned_height;
9658
9659         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9660                       pipe_name(pipe), fb->width, fb->height,
9661                       fb->bits_per_pixel, base, fb->pitches[0],
9662                       plane_config->size);
9663
9664         plane_config->fb = intel_fb;
9665         return;
9666
9667 error:
9668         kfree(fb);
9669 }
9670
9671 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9672                                      struct intel_crtc_state *pipe_config)
9673 {
9674         struct drm_device *dev = crtc->base.dev;
9675         struct drm_i915_private *dev_priv = to_i915(dev);
9676         uint32_t tmp;
9677
9678         tmp = I915_READ(PF_CTL(crtc->pipe));
9679
9680         if (tmp & PF_ENABLE) {
9681                 pipe_config->pch_pfit.enabled = true;
9682                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9683                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9684
9685                 /* We currently do not free assignements of panel fitters on
9686                  * ivb/hsw (since we don't use the higher upscaling modes which
9687                  * differentiates them) so just WARN about this case for now. */
9688                 if (IS_GEN7(dev)) {
9689                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9690                                 PF_PIPE_SEL_IVB(crtc->pipe));
9691                 }
9692         }
9693 }
9694
9695 static void
9696 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9697                                   struct intel_initial_plane_config *plane_config)
9698 {
9699         struct drm_device *dev = crtc->base.dev;
9700         struct drm_i915_private *dev_priv = to_i915(dev);
9701         u32 val, base, offset;
9702         int pipe = crtc->pipe;
9703         int fourcc, pixel_format;
9704         unsigned int aligned_height;
9705         struct drm_framebuffer *fb;
9706         struct intel_framebuffer *intel_fb;
9707
9708         val = I915_READ(DSPCNTR(pipe));
9709         if (!(val & DISPLAY_PLANE_ENABLE))
9710                 return;
9711
9712         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9713         if (!intel_fb) {
9714                 DRM_DEBUG_KMS("failed to alloc fb\n");
9715                 return;
9716         }
9717
9718         fb = &intel_fb->base;
9719
9720         if (INTEL_INFO(dev)->gen >= 4) {
9721                 if (val & DISPPLANE_TILED) {
9722                         plane_config->tiling = I915_TILING_X;
9723                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9724                 }
9725         }
9726
9727         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9728         fourcc = i9xx_format_to_fourcc(pixel_format);
9729         fb->pixel_format = fourcc;
9730         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9731
9732         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9733         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9734                 offset = I915_READ(DSPOFFSET(pipe));
9735         } else {
9736                 if (plane_config->tiling)
9737                         offset = I915_READ(DSPTILEOFF(pipe));
9738                 else
9739                         offset = I915_READ(DSPLINOFF(pipe));
9740         }
9741         plane_config->base = base;
9742
9743         val = I915_READ(PIPESRC(pipe));
9744         fb->width = ((val >> 16) & 0xfff) + 1;
9745         fb->height = ((val >> 0) & 0xfff) + 1;
9746
9747         val = I915_READ(DSPSTRIDE(pipe));
9748         fb->pitches[0] = val & 0xffffffc0;
9749
9750         aligned_height = intel_fb_align_height(dev, fb->height,
9751                                                fb->pixel_format,
9752                                                fb->modifier[0]);
9753
9754         plane_config->size = fb->pitches[0] * aligned_height;
9755
9756         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9757                       pipe_name(pipe), fb->width, fb->height,
9758                       fb->bits_per_pixel, base, fb->pitches[0],
9759                       plane_config->size);
9760
9761         plane_config->fb = intel_fb;
9762 }
9763
9764 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9765                                      struct intel_crtc_state *pipe_config)
9766 {
9767         struct drm_device *dev = crtc->base.dev;
9768         struct drm_i915_private *dev_priv = to_i915(dev);
9769         enum intel_display_power_domain power_domain;
9770         uint32_t tmp;
9771         bool ret;
9772
9773         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9774         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9775                 return false;
9776
9777         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9778         pipe_config->shared_dpll = NULL;
9779
9780         ret = false;
9781         tmp = I915_READ(PIPECONF(crtc->pipe));
9782         if (!(tmp & PIPECONF_ENABLE))
9783                 goto out;
9784
9785         switch (tmp & PIPECONF_BPC_MASK) {
9786         case PIPECONF_6BPC:
9787                 pipe_config->pipe_bpp = 18;
9788                 break;
9789         case PIPECONF_8BPC:
9790                 pipe_config->pipe_bpp = 24;
9791                 break;
9792         case PIPECONF_10BPC:
9793                 pipe_config->pipe_bpp = 30;
9794                 break;
9795         case PIPECONF_12BPC:
9796                 pipe_config->pipe_bpp = 36;
9797                 break;
9798         default:
9799                 break;
9800         }
9801
9802         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9803                 pipe_config->limited_color_range = true;
9804
9805         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9806                 struct intel_shared_dpll *pll;
9807                 enum intel_dpll_id pll_id;
9808
9809                 pipe_config->has_pch_encoder = true;
9810
9811                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9812                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9813                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9814
9815                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9816
9817                 if (HAS_PCH_IBX(dev_priv)) {
9818                         /*
9819                          * The pipe->pch transcoder and pch transcoder->pll
9820                          * mapping is fixed.
9821                          */
9822                         pll_id = (enum intel_dpll_id) crtc->pipe;
9823                 } else {
9824                         tmp = I915_READ(PCH_DPLL_SEL);
9825                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9826                                 pll_id = DPLL_ID_PCH_PLL_B;
9827                         else
9828                                 pll_id= DPLL_ID_PCH_PLL_A;
9829                 }
9830
9831                 pipe_config->shared_dpll =
9832                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9833                 pll = pipe_config->shared_dpll;
9834
9835                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9836                                                  &pipe_config->dpll_hw_state));
9837
9838                 tmp = pipe_config->dpll_hw_state.dpll;
9839                 pipe_config->pixel_multiplier =
9840                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9841                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9842
9843                 ironlake_pch_clock_get(crtc, pipe_config);
9844         } else {
9845                 pipe_config->pixel_multiplier = 1;
9846         }
9847
9848         intel_get_pipe_timings(crtc, pipe_config);
9849         intel_get_pipe_src_size(crtc, pipe_config);
9850
9851         ironlake_get_pfit_config(crtc, pipe_config);
9852
9853         ret = true;
9854
9855 out:
9856         intel_display_power_put(dev_priv, power_domain);
9857
9858         return ret;
9859 }
9860
9861 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9862 {
9863         struct drm_device *dev = &dev_priv->drm;
9864         struct intel_crtc *crtc;
9865
9866         for_each_intel_crtc(dev, crtc)
9867                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9868                      pipe_name(crtc->pipe));
9869
9870         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9871         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9872         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9873         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9874         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9875         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9876              "CPU PWM1 enabled\n");
9877         if (IS_HASWELL(dev))
9878                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9879                      "CPU PWM2 enabled\n");
9880         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9881              "PCH PWM1 enabled\n");
9882         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9883              "Utility pin enabled\n");
9884         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9885
9886         /*
9887          * In theory we can still leave IRQs enabled, as long as only the HPD
9888          * interrupts remain enabled. We used to check for that, but since it's
9889          * gen-specific and since we only disable LCPLL after we fully disable
9890          * the interrupts, the check below should be enough.
9891          */
9892         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9893 }
9894
9895 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9896 {
9897         struct drm_device *dev = &dev_priv->drm;
9898
9899         if (IS_HASWELL(dev))
9900                 return I915_READ(D_COMP_HSW);
9901         else
9902                 return I915_READ(D_COMP_BDW);
9903 }
9904
9905 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9906 {
9907         struct drm_device *dev = &dev_priv->drm;
9908
9909         if (IS_HASWELL(dev)) {
9910                 mutex_lock(&dev_priv->rps.hw_lock);
9911                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9912                                             val))
9913                         DRM_ERROR("Failed to write to D_COMP\n");
9914                 mutex_unlock(&dev_priv->rps.hw_lock);
9915         } else {
9916                 I915_WRITE(D_COMP_BDW, val);
9917                 POSTING_READ(D_COMP_BDW);
9918         }
9919 }
9920
9921 /*
9922  * This function implements pieces of two sequences from BSpec:
9923  * - Sequence for display software to disable LCPLL
9924  * - Sequence for display software to allow package C8+
9925  * The steps implemented here are just the steps that actually touch the LCPLL
9926  * register. Callers should take care of disabling all the display engine
9927  * functions, doing the mode unset, fixing interrupts, etc.
9928  */
9929 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9930                               bool switch_to_fclk, bool allow_power_down)
9931 {
9932         uint32_t val;
9933
9934         assert_can_disable_lcpll(dev_priv);
9935
9936         val = I915_READ(LCPLL_CTL);
9937
9938         if (switch_to_fclk) {
9939                 val |= LCPLL_CD_SOURCE_FCLK;
9940                 I915_WRITE(LCPLL_CTL, val);
9941
9942                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9943                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9944                         DRM_ERROR("Switching to FCLK failed\n");
9945
9946                 val = I915_READ(LCPLL_CTL);
9947         }
9948
9949         val |= LCPLL_PLL_DISABLE;
9950         I915_WRITE(LCPLL_CTL, val);
9951         POSTING_READ(LCPLL_CTL);
9952
9953         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9954                 DRM_ERROR("LCPLL still locked\n");
9955
9956         val = hsw_read_dcomp(dev_priv);
9957         val |= D_COMP_COMP_DISABLE;
9958         hsw_write_dcomp(dev_priv, val);
9959         ndelay(100);
9960
9961         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9962                      1))
9963                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9964
9965         if (allow_power_down) {
9966                 val = I915_READ(LCPLL_CTL);
9967                 val |= LCPLL_POWER_DOWN_ALLOW;
9968                 I915_WRITE(LCPLL_CTL, val);
9969                 POSTING_READ(LCPLL_CTL);
9970         }
9971 }
9972
9973 /*
9974  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9975  * source.
9976  */
9977 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9978 {
9979         uint32_t val;
9980
9981         val = I915_READ(LCPLL_CTL);
9982
9983         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9984                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9985                 return;
9986
9987         /*
9988          * Make sure we're not on PC8 state before disabling PC8, otherwise
9989          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9990          */
9991         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9992
9993         if (val & LCPLL_POWER_DOWN_ALLOW) {
9994                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9995                 I915_WRITE(LCPLL_CTL, val);
9996                 POSTING_READ(LCPLL_CTL);
9997         }
9998
9999         val = hsw_read_dcomp(dev_priv);
10000         val |= D_COMP_COMP_FORCE;
10001         val &= ~D_COMP_COMP_DISABLE;
10002         hsw_write_dcomp(dev_priv, val);
10003
10004         val = I915_READ(LCPLL_CTL);
10005         val &= ~LCPLL_PLL_DISABLE;
10006         I915_WRITE(LCPLL_CTL, val);
10007
10008         if (intel_wait_for_register(dev_priv,
10009                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10010                                     5))
10011                 DRM_ERROR("LCPLL not locked yet\n");
10012
10013         if (val & LCPLL_CD_SOURCE_FCLK) {
10014                 val = I915_READ(LCPLL_CTL);
10015                 val &= ~LCPLL_CD_SOURCE_FCLK;
10016                 I915_WRITE(LCPLL_CTL, val);
10017
10018                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10019                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10020                         DRM_ERROR("Switching back to LCPLL failed\n");
10021         }
10022
10023         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10024         intel_update_cdclk(&dev_priv->drm);
10025 }
10026
10027 /*
10028  * Package states C8 and deeper are really deep PC states that can only be
10029  * reached when all the devices on the system allow it, so even if the graphics
10030  * device allows PC8+, it doesn't mean the system will actually get to these
10031  * states. Our driver only allows PC8+ when going into runtime PM.
10032  *
10033  * The requirements for PC8+ are that all the outputs are disabled, the power
10034  * well is disabled and most interrupts are disabled, and these are also
10035  * requirements for runtime PM. When these conditions are met, we manually do
10036  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10037  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10038  * hang the machine.
10039  *
10040  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10041  * the state of some registers, so when we come back from PC8+ we need to
10042  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10043  * need to take care of the registers kept by RC6. Notice that this happens even
10044  * if we don't put the device in PCI D3 state (which is what currently happens
10045  * because of the runtime PM support).
10046  *
10047  * For more, read "Display Sequences for Package C8" on the hardware
10048  * documentation.
10049  */
10050 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10051 {
10052         struct drm_device *dev = &dev_priv->drm;
10053         uint32_t val;
10054
10055         DRM_DEBUG_KMS("Enabling package C8+\n");
10056
10057         if (HAS_PCH_LPT_LP(dev)) {
10058                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10059                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10060                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10061         }
10062
10063         lpt_disable_clkout_dp(dev);
10064         hsw_disable_lcpll(dev_priv, true, true);
10065 }
10066
10067 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10068 {
10069         struct drm_device *dev = &dev_priv->drm;
10070         uint32_t val;
10071
10072         DRM_DEBUG_KMS("Disabling package C8+\n");
10073
10074         hsw_restore_lcpll(dev_priv);
10075         lpt_init_pch_refclk(dev);
10076
10077         if (HAS_PCH_LPT_LP(dev)) {
10078                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10079                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10080                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10081         }
10082 }
10083
10084 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10085 {
10086         struct drm_device *dev = old_state->dev;
10087         struct intel_atomic_state *old_intel_state =
10088                 to_intel_atomic_state(old_state);
10089         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10090
10091         bxt_set_cdclk(to_i915(dev), req_cdclk);
10092 }
10093
10094 /* compute the max rate for new configuration */
10095 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10096 {
10097         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10098         struct drm_i915_private *dev_priv = to_i915(state->dev);
10099         struct drm_crtc *crtc;
10100         struct drm_crtc_state *cstate;
10101         struct intel_crtc_state *crtc_state;
10102         unsigned max_pixel_rate = 0, i;
10103         enum pipe pipe;
10104
10105         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10106                sizeof(intel_state->min_pixclk));
10107
10108         for_each_crtc_in_state(state, crtc, cstate, i) {
10109                 int pixel_rate;
10110
10111                 crtc_state = to_intel_crtc_state(cstate);
10112                 if (!crtc_state->base.enable) {
10113                         intel_state->min_pixclk[i] = 0;
10114                         continue;
10115                 }
10116
10117                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10118
10119                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10120                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10121                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10122
10123                 intel_state->min_pixclk[i] = pixel_rate;
10124         }
10125
10126         for_each_pipe(dev_priv, pipe)
10127                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10128
10129         return max_pixel_rate;
10130 }
10131
10132 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10133 {
10134         struct drm_i915_private *dev_priv = to_i915(dev);
10135         uint32_t val, data;
10136         int ret;
10137
10138         if (WARN((I915_READ(LCPLL_CTL) &
10139                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10140                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10141                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10142                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10143                  "trying to change cdclk frequency with cdclk not enabled\n"))
10144                 return;
10145
10146         mutex_lock(&dev_priv->rps.hw_lock);
10147         ret = sandybridge_pcode_write(dev_priv,
10148                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10149         mutex_unlock(&dev_priv->rps.hw_lock);
10150         if (ret) {
10151                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10152                 return;
10153         }
10154
10155         val = I915_READ(LCPLL_CTL);
10156         val |= LCPLL_CD_SOURCE_FCLK;
10157         I915_WRITE(LCPLL_CTL, val);
10158
10159         if (wait_for_us(I915_READ(LCPLL_CTL) &
10160                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10161                 DRM_ERROR("Switching to FCLK failed\n");
10162
10163         val = I915_READ(LCPLL_CTL);
10164         val &= ~LCPLL_CLK_FREQ_MASK;
10165
10166         switch (cdclk) {
10167         case 450000:
10168                 val |= LCPLL_CLK_FREQ_450;
10169                 data = 0;
10170                 break;
10171         case 540000:
10172                 val |= LCPLL_CLK_FREQ_54O_BDW;
10173                 data = 1;
10174                 break;
10175         case 337500:
10176                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10177                 data = 2;
10178                 break;
10179         case 675000:
10180                 val |= LCPLL_CLK_FREQ_675_BDW;
10181                 data = 3;
10182                 break;
10183         default:
10184                 WARN(1, "invalid cdclk frequency\n");
10185                 return;
10186         }
10187
10188         I915_WRITE(LCPLL_CTL, val);
10189
10190         val = I915_READ(LCPLL_CTL);
10191         val &= ~LCPLL_CD_SOURCE_FCLK;
10192         I915_WRITE(LCPLL_CTL, val);
10193
10194         if (wait_for_us((I915_READ(LCPLL_CTL) &
10195                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10196                 DRM_ERROR("Switching back to LCPLL failed\n");
10197
10198         mutex_lock(&dev_priv->rps.hw_lock);
10199         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10200         mutex_unlock(&dev_priv->rps.hw_lock);
10201
10202         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10203
10204         intel_update_cdclk(dev);
10205
10206         WARN(cdclk != dev_priv->cdclk_freq,
10207              "cdclk requested %d kHz but got %d kHz\n",
10208              cdclk, dev_priv->cdclk_freq);
10209 }
10210
10211 static int broadwell_calc_cdclk(int max_pixclk)
10212 {
10213         if (max_pixclk > 540000)
10214                 return 675000;
10215         else if (max_pixclk > 450000)
10216                 return 540000;
10217         else if (max_pixclk > 337500)
10218                 return 450000;
10219         else
10220                 return 337500;
10221 }
10222
10223 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10224 {
10225         struct drm_i915_private *dev_priv = to_i915(state->dev);
10226         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10227         int max_pixclk = ilk_max_pixel_rate(state);
10228         int cdclk;
10229
10230         /*
10231          * FIXME should also account for plane ratio
10232          * once 64bpp pixel formats are supported.
10233          */
10234         cdclk = broadwell_calc_cdclk(max_pixclk);
10235
10236         if (cdclk > dev_priv->max_cdclk_freq) {
10237                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10238                               cdclk, dev_priv->max_cdclk_freq);
10239                 return -EINVAL;
10240         }
10241
10242         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10243         if (!intel_state->active_crtcs)
10244                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10245
10246         return 0;
10247 }
10248
10249 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10250 {
10251         struct drm_device *dev = old_state->dev;
10252         struct intel_atomic_state *old_intel_state =
10253                 to_intel_atomic_state(old_state);
10254         unsigned req_cdclk = old_intel_state->dev_cdclk;
10255
10256         broadwell_set_cdclk(dev, req_cdclk);
10257 }
10258
10259 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10260 {
10261         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10262         struct drm_i915_private *dev_priv = to_i915(state->dev);
10263         const int max_pixclk = ilk_max_pixel_rate(state);
10264         int vco = intel_state->cdclk_pll_vco;
10265         int cdclk;
10266
10267         /*
10268          * FIXME should also account for plane ratio
10269          * once 64bpp pixel formats are supported.
10270          */
10271         cdclk = skl_calc_cdclk(max_pixclk, vco);
10272
10273         /*
10274          * FIXME move the cdclk caclulation to
10275          * compute_config() so we can fail gracegully.
10276          */
10277         if (cdclk > dev_priv->max_cdclk_freq) {
10278                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10279                           cdclk, dev_priv->max_cdclk_freq);
10280                 cdclk = dev_priv->max_cdclk_freq;
10281         }
10282
10283         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10284         if (!intel_state->active_crtcs)
10285                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10286
10287         return 0;
10288 }
10289
10290 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10291 {
10292         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10293         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10294         unsigned int req_cdclk = intel_state->dev_cdclk;
10295         unsigned int req_vco = intel_state->cdclk_pll_vco;
10296
10297         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10298 }
10299
10300 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10301                                       struct intel_crtc_state *crtc_state)
10302 {
10303         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10304                 if (!intel_ddi_pll_select(crtc, crtc_state))
10305                         return -EINVAL;
10306         }
10307
10308         crtc->lowfreq_avail = false;
10309
10310         return 0;
10311 }
10312
10313 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10314                                 enum port port,
10315                                 struct intel_crtc_state *pipe_config)
10316 {
10317         enum intel_dpll_id id;
10318
10319         switch (port) {
10320         case PORT_A:
10321                 pipe_config->ddi_pll_sel = SKL_DPLL0;
10322                 id = DPLL_ID_SKL_DPLL0;
10323                 break;
10324         case PORT_B:
10325                 pipe_config->ddi_pll_sel = SKL_DPLL1;
10326                 id = DPLL_ID_SKL_DPLL1;
10327                 break;
10328         case PORT_C:
10329                 pipe_config->ddi_pll_sel = SKL_DPLL2;
10330                 id = DPLL_ID_SKL_DPLL2;
10331                 break;
10332         default:
10333                 DRM_ERROR("Incorrect port type\n");
10334                 return;
10335         }
10336
10337         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10338 }
10339
10340 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10341                                 enum port port,
10342                                 struct intel_crtc_state *pipe_config)
10343 {
10344         enum intel_dpll_id id;
10345         u32 temp;
10346
10347         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10348         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
10349
10350         switch (pipe_config->ddi_pll_sel) {
10351         case SKL_DPLL0:
10352                 id = DPLL_ID_SKL_DPLL0;
10353                 break;
10354         case SKL_DPLL1:
10355                 id = DPLL_ID_SKL_DPLL1;
10356                 break;
10357         case SKL_DPLL2:
10358                 id = DPLL_ID_SKL_DPLL2;
10359                 break;
10360         case SKL_DPLL3:
10361                 id = DPLL_ID_SKL_DPLL3;
10362                 break;
10363         default:
10364                 MISSING_CASE(pipe_config->ddi_pll_sel);
10365                 return;
10366         }
10367
10368         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10369 }
10370
10371 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10372                                 enum port port,
10373                                 struct intel_crtc_state *pipe_config)
10374 {
10375         enum intel_dpll_id id;
10376
10377         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10378
10379         switch (pipe_config->ddi_pll_sel) {
10380         case PORT_CLK_SEL_WRPLL1:
10381                 id = DPLL_ID_WRPLL1;
10382                 break;
10383         case PORT_CLK_SEL_WRPLL2:
10384                 id = DPLL_ID_WRPLL2;
10385                 break;
10386         case PORT_CLK_SEL_SPLL:
10387                 id = DPLL_ID_SPLL;
10388                 break;
10389         case PORT_CLK_SEL_LCPLL_810:
10390                 id = DPLL_ID_LCPLL_810;
10391                 break;
10392         case PORT_CLK_SEL_LCPLL_1350:
10393                 id = DPLL_ID_LCPLL_1350;
10394                 break;
10395         case PORT_CLK_SEL_LCPLL_2700:
10396                 id = DPLL_ID_LCPLL_2700;
10397                 break;
10398         default:
10399                 MISSING_CASE(pipe_config->ddi_pll_sel);
10400                 /* fall through */
10401         case PORT_CLK_SEL_NONE:
10402                 return;
10403         }
10404
10405         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10406 }
10407
10408 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10409                                      struct intel_crtc_state *pipe_config,
10410                                      unsigned long *power_domain_mask)
10411 {
10412         struct drm_device *dev = crtc->base.dev;
10413         struct drm_i915_private *dev_priv = to_i915(dev);
10414         enum intel_display_power_domain power_domain;
10415         u32 tmp;
10416
10417         /*
10418          * The pipe->transcoder mapping is fixed with the exception of the eDP
10419          * transcoder handled below.
10420          */
10421         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10422
10423         /*
10424          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10425          * consistency and less surprising code; it's in always on power).
10426          */
10427         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10428         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10429                 enum pipe trans_edp_pipe;
10430                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10431                 default:
10432                         WARN(1, "unknown pipe linked to edp transcoder\n");
10433                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10434                 case TRANS_DDI_EDP_INPUT_A_ON:
10435                         trans_edp_pipe = PIPE_A;
10436                         break;
10437                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10438                         trans_edp_pipe = PIPE_B;
10439                         break;
10440                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10441                         trans_edp_pipe = PIPE_C;
10442                         break;
10443                 }
10444
10445                 if (trans_edp_pipe == crtc->pipe)
10446                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10447         }
10448
10449         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10450         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10451                 return false;
10452         *power_domain_mask |= BIT(power_domain);
10453
10454         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10455
10456         return tmp & PIPECONF_ENABLE;
10457 }
10458
10459 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10460                                          struct intel_crtc_state *pipe_config,
10461                                          unsigned long *power_domain_mask)
10462 {
10463         struct drm_device *dev = crtc->base.dev;
10464         struct drm_i915_private *dev_priv = to_i915(dev);
10465         enum intel_display_power_domain power_domain;
10466         enum port port;
10467         enum transcoder cpu_transcoder;
10468         u32 tmp;
10469
10470         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10471                 if (port == PORT_A)
10472                         cpu_transcoder = TRANSCODER_DSI_A;
10473                 else
10474                         cpu_transcoder = TRANSCODER_DSI_C;
10475
10476                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10477                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10478                         continue;
10479                 *power_domain_mask |= BIT(power_domain);
10480
10481                 /*
10482                  * The PLL needs to be enabled with a valid divider
10483                  * configuration, otherwise accessing DSI registers will hang
10484                  * the machine. See BSpec North Display Engine
10485                  * registers/MIPI[BXT]. We can break out here early, since we
10486                  * need the same DSI PLL to be enabled for both DSI ports.
10487                  */
10488                 if (!intel_dsi_pll_is_enabled(dev_priv))
10489                         break;
10490
10491                 /* XXX: this works for video mode only */
10492                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10493                 if (!(tmp & DPI_ENABLE))
10494                         continue;
10495
10496                 tmp = I915_READ(MIPI_CTRL(port));
10497                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10498                         continue;
10499
10500                 pipe_config->cpu_transcoder = cpu_transcoder;
10501                 break;
10502         }
10503
10504         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10505 }
10506
10507 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10508                                        struct intel_crtc_state *pipe_config)
10509 {
10510         struct drm_device *dev = crtc->base.dev;
10511         struct drm_i915_private *dev_priv = to_i915(dev);
10512         struct intel_shared_dpll *pll;
10513         enum port port;
10514         uint32_t tmp;
10515
10516         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10517
10518         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10519
10520         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10521                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10522         else if (IS_BROXTON(dev))
10523                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10524         else
10525                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10526
10527         pll = pipe_config->shared_dpll;
10528         if (pll) {
10529                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10530                                                  &pipe_config->dpll_hw_state));
10531         }
10532
10533         /*
10534          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10535          * DDI E. So just check whether this pipe is wired to DDI E and whether
10536          * the PCH transcoder is on.
10537          */
10538         if (INTEL_INFO(dev)->gen < 9 &&
10539             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10540                 pipe_config->has_pch_encoder = true;
10541
10542                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10543                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10544                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10545
10546                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10547         }
10548 }
10549
10550 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10551                                     struct intel_crtc_state *pipe_config)
10552 {
10553         struct drm_device *dev = crtc->base.dev;
10554         struct drm_i915_private *dev_priv = to_i915(dev);
10555         enum intel_display_power_domain power_domain;
10556         unsigned long power_domain_mask;
10557         bool active;
10558
10559         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10560         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10561                 return false;
10562         power_domain_mask = BIT(power_domain);
10563
10564         pipe_config->shared_dpll = NULL;
10565
10566         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10567
10568         if (IS_BROXTON(dev_priv) &&
10569             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10570                 WARN_ON(active);
10571                 active = true;
10572         }
10573
10574         if (!active)
10575                 goto out;
10576
10577         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10578                 haswell_get_ddi_port_state(crtc, pipe_config);
10579                 intel_get_pipe_timings(crtc, pipe_config);
10580         }
10581
10582         intel_get_pipe_src_size(crtc, pipe_config);
10583
10584         pipe_config->gamma_mode =
10585                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10586
10587         if (INTEL_INFO(dev)->gen >= 9) {
10588                 skl_init_scalers(dev, crtc, pipe_config);
10589         }
10590
10591         if (INTEL_INFO(dev)->gen >= 9) {
10592                 pipe_config->scaler_state.scaler_id = -1;
10593                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10594         }
10595
10596         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10597         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10598                 power_domain_mask |= BIT(power_domain);
10599                 if (INTEL_INFO(dev)->gen >= 9)
10600                         skylake_get_pfit_config(crtc, pipe_config);
10601                 else
10602                         ironlake_get_pfit_config(crtc, pipe_config);
10603         }
10604
10605         if (IS_HASWELL(dev))
10606                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10607                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10608
10609         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10610             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10611                 pipe_config->pixel_multiplier =
10612                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10613         } else {
10614                 pipe_config->pixel_multiplier = 1;
10615         }
10616
10617 out:
10618         for_each_power_domain(power_domain, power_domain_mask)
10619                 intel_display_power_put(dev_priv, power_domain);
10620
10621         return active;
10622 }
10623
10624 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10625                                const struct intel_plane_state *plane_state)
10626 {
10627         struct drm_device *dev = crtc->dev;
10628         struct drm_i915_private *dev_priv = to_i915(dev);
10629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10630         uint32_t cntl = 0, size = 0;
10631
10632         if (plane_state && plane_state->base.visible) {
10633                 unsigned int width = plane_state->base.crtc_w;
10634                 unsigned int height = plane_state->base.crtc_h;
10635                 unsigned int stride = roundup_pow_of_two(width) * 4;
10636
10637                 switch (stride) {
10638                 default:
10639                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10640                                   width, stride);
10641                         stride = 256;
10642                         /* fallthrough */
10643                 case 256:
10644                 case 512:
10645                 case 1024:
10646                 case 2048:
10647                         break;
10648                 }
10649
10650                 cntl |= CURSOR_ENABLE |
10651                         CURSOR_GAMMA_ENABLE |
10652                         CURSOR_FORMAT_ARGB |
10653                         CURSOR_STRIDE(stride);
10654
10655                 size = (height << 12) | width;
10656         }
10657
10658         if (intel_crtc->cursor_cntl != 0 &&
10659             (intel_crtc->cursor_base != base ||
10660              intel_crtc->cursor_size != size ||
10661              intel_crtc->cursor_cntl != cntl)) {
10662                 /* On these chipsets we can only modify the base/size/stride
10663                  * whilst the cursor is disabled.
10664                  */
10665                 I915_WRITE(CURCNTR(PIPE_A), 0);
10666                 POSTING_READ(CURCNTR(PIPE_A));
10667                 intel_crtc->cursor_cntl = 0;
10668         }
10669
10670         if (intel_crtc->cursor_base != base) {
10671                 I915_WRITE(CURBASE(PIPE_A), base);
10672                 intel_crtc->cursor_base = base;
10673         }
10674
10675         if (intel_crtc->cursor_size != size) {
10676                 I915_WRITE(CURSIZE, size);
10677                 intel_crtc->cursor_size = size;
10678         }
10679
10680         if (intel_crtc->cursor_cntl != cntl) {
10681                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10682                 POSTING_READ(CURCNTR(PIPE_A));
10683                 intel_crtc->cursor_cntl = cntl;
10684         }
10685 }
10686
10687 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10688                                const struct intel_plane_state *plane_state)
10689 {
10690         struct drm_device *dev = crtc->dev;
10691         struct drm_i915_private *dev_priv = to_i915(dev);
10692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10693         int pipe = intel_crtc->pipe;
10694         uint32_t cntl = 0;
10695
10696         if (plane_state && plane_state->base.visible) {
10697                 cntl = MCURSOR_GAMMA_ENABLE;
10698                 switch (plane_state->base.crtc_w) {
10699                         case 64:
10700                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10701                                 break;
10702                         case 128:
10703                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10704                                 break;
10705                         case 256:
10706                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10707                                 break;
10708                         default:
10709                                 MISSING_CASE(plane_state->base.crtc_w);
10710                                 return;
10711                 }
10712                 cntl |= pipe << 28; /* Connect to correct pipe */
10713
10714                 if (HAS_DDI(dev))
10715                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10716
10717                 if (plane_state->base.rotation == DRM_ROTATE_180)
10718                         cntl |= CURSOR_ROTATE_180;
10719         }
10720
10721         if (intel_crtc->cursor_cntl != cntl) {
10722                 I915_WRITE(CURCNTR(pipe), cntl);
10723                 POSTING_READ(CURCNTR(pipe));
10724                 intel_crtc->cursor_cntl = cntl;
10725         }
10726
10727         /* and commit changes on next vblank */
10728         I915_WRITE(CURBASE(pipe), base);
10729         POSTING_READ(CURBASE(pipe));
10730
10731         intel_crtc->cursor_base = base;
10732 }
10733
10734 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10735 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10736                                      const struct intel_plane_state *plane_state)
10737 {
10738         struct drm_device *dev = crtc->dev;
10739         struct drm_i915_private *dev_priv = to_i915(dev);
10740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10741         int pipe = intel_crtc->pipe;
10742         u32 base = intel_crtc->cursor_addr;
10743         u32 pos = 0;
10744
10745         if (plane_state) {
10746                 int x = plane_state->base.crtc_x;
10747                 int y = plane_state->base.crtc_y;
10748
10749                 if (x < 0) {
10750                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10751                         x = -x;
10752                 }
10753                 pos |= x << CURSOR_X_SHIFT;
10754
10755                 if (y < 0) {
10756                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10757                         y = -y;
10758                 }
10759                 pos |= y << CURSOR_Y_SHIFT;
10760
10761                 /* ILK+ do this automagically */
10762                 if (HAS_GMCH_DISPLAY(dev) &&
10763                     plane_state->base.rotation == DRM_ROTATE_180) {
10764                         base += (plane_state->base.crtc_h *
10765                                  plane_state->base.crtc_w - 1) * 4;
10766                 }
10767         }
10768
10769         I915_WRITE(CURPOS(pipe), pos);
10770
10771         if (IS_845G(dev) || IS_I865G(dev))
10772                 i845_update_cursor(crtc, base, plane_state);
10773         else
10774                 i9xx_update_cursor(crtc, base, plane_state);
10775 }
10776
10777 static bool cursor_size_ok(struct drm_device *dev,
10778                            uint32_t width, uint32_t height)
10779 {
10780         if (width == 0 || height == 0)
10781                 return false;
10782
10783         /*
10784          * 845g/865g are special in that they are only limited by
10785          * the width of their cursors, the height is arbitrary up to
10786          * the precision of the register. Everything else requires
10787          * square cursors, limited to a few power-of-two sizes.
10788          */
10789         if (IS_845G(dev) || IS_I865G(dev)) {
10790                 if ((width & 63) != 0)
10791                         return false;
10792
10793                 if (width > (IS_845G(dev) ? 64 : 512))
10794                         return false;
10795
10796                 if (height > 1023)
10797                         return false;
10798         } else {
10799                 switch (width | height) {
10800                 case 256:
10801                 case 128:
10802                         if (IS_GEN2(dev))
10803                                 return false;
10804                 case 64:
10805                         break;
10806                 default:
10807                         return false;
10808                 }
10809         }
10810
10811         return true;
10812 }
10813
10814 /* VESA 640x480x72Hz mode to set on the pipe */
10815 static struct drm_display_mode load_detect_mode = {
10816         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10817                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10818 };
10819
10820 struct drm_framebuffer *
10821 __intel_framebuffer_create(struct drm_device *dev,
10822                            struct drm_mode_fb_cmd2 *mode_cmd,
10823                            struct drm_i915_gem_object *obj)
10824 {
10825         struct intel_framebuffer *intel_fb;
10826         int ret;
10827
10828         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10829         if (!intel_fb)
10830                 return ERR_PTR(-ENOMEM);
10831
10832         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10833         if (ret)
10834                 goto err;
10835
10836         return &intel_fb->base;
10837
10838 err:
10839         kfree(intel_fb);
10840         return ERR_PTR(ret);
10841 }
10842
10843 static struct drm_framebuffer *
10844 intel_framebuffer_create(struct drm_device *dev,
10845                          struct drm_mode_fb_cmd2 *mode_cmd,
10846                          struct drm_i915_gem_object *obj)
10847 {
10848         struct drm_framebuffer *fb;
10849         int ret;
10850
10851         ret = i915_mutex_lock_interruptible(dev);
10852         if (ret)
10853                 return ERR_PTR(ret);
10854         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10855         mutex_unlock(&dev->struct_mutex);
10856
10857         return fb;
10858 }
10859
10860 static u32
10861 intel_framebuffer_pitch_for_width(int width, int bpp)
10862 {
10863         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10864         return ALIGN(pitch, 64);
10865 }
10866
10867 static u32
10868 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10869 {
10870         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10871         return PAGE_ALIGN(pitch * mode->vdisplay);
10872 }
10873
10874 static struct drm_framebuffer *
10875 intel_framebuffer_create_for_mode(struct drm_device *dev,
10876                                   struct drm_display_mode *mode,
10877                                   int depth, int bpp)
10878 {
10879         struct drm_framebuffer *fb;
10880         struct drm_i915_gem_object *obj;
10881         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10882
10883         obj = i915_gem_object_create(dev,
10884                                     intel_framebuffer_size_for_mode(mode, bpp));
10885         if (IS_ERR(obj))
10886                 return ERR_CAST(obj);
10887
10888         mode_cmd.width = mode->hdisplay;
10889         mode_cmd.height = mode->vdisplay;
10890         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10891                                                                 bpp);
10892         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10893
10894         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10895         if (IS_ERR(fb))
10896                 i915_gem_object_put_unlocked(obj);
10897
10898         return fb;
10899 }
10900
10901 static struct drm_framebuffer *
10902 mode_fits_in_fbdev(struct drm_device *dev,
10903                    struct drm_display_mode *mode)
10904 {
10905 #ifdef CONFIG_DRM_FBDEV_EMULATION
10906         struct drm_i915_private *dev_priv = to_i915(dev);
10907         struct drm_i915_gem_object *obj;
10908         struct drm_framebuffer *fb;
10909
10910         if (!dev_priv->fbdev)
10911                 return NULL;
10912
10913         if (!dev_priv->fbdev->fb)
10914                 return NULL;
10915
10916         obj = dev_priv->fbdev->fb->obj;
10917         BUG_ON(!obj);
10918
10919         fb = &dev_priv->fbdev->fb->base;
10920         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10921                                                                fb->bits_per_pixel))
10922                 return NULL;
10923
10924         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10925                 return NULL;
10926
10927         drm_framebuffer_reference(fb);
10928         return fb;
10929 #else
10930         return NULL;
10931 #endif
10932 }
10933
10934 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10935                                            struct drm_crtc *crtc,
10936                                            struct drm_display_mode *mode,
10937                                            struct drm_framebuffer *fb,
10938                                            int x, int y)
10939 {
10940         struct drm_plane_state *plane_state;
10941         int hdisplay, vdisplay;
10942         int ret;
10943
10944         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10945         if (IS_ERR(plane_state))
10946                 return PTR_ERR(plane_state);
10947
10948         if (mode)
10949                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10950         else
10951                 hdisplay = vdisplay = 0;
10952
10953         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10954         if (ret)
10955                 return ret;
10956         drm_atomic_set_fb_for_plane(plane_state, fb);
10957         plane_state->crtc_x = 0;
10958         plane_state->crtc_y = 0;
10959         plane_state->crtc_w = hdisplay;
10960         plane_state->crtc_h = vdisplay;
10961         plane_state->src_x = x << 16;
10962         plane_state->src_y = y << 16;
10963         plane_state->src_w = hdisplay << 16;
10964         plane_state->src_h = vdisplay << 16;
10965
10966         return 0;
10967 }
10968
10969 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10970                                 struct drm_display_mode *mode,
10971                                 struct intel_load_detect_pipe *old,
10972                                 struct drm_modeset_acquire_ctx *ctx)
10973 {
10974         struct intel_crtc *intel_crtc;
10975         struct intel_encoder *intel_encoder =
10976                 intel_attached_encoder(connector);
10977         struct drm_crtc *possible_crtc;
10978         struct drm_encoder *encoder = &intel_encoder->base;
10979         struct drm_crtc *crtc = NULL;
10980         struct drm_device *dev = encoder->dev;
10981         struct drm_framebuffer *fb;
10982         struct drm_mode_config *config = &dev->mode_config;
10983         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10984         struct drm_connector_state *connector_state;
10985         struct intel_crtc_state *crtc_state;
10986         int ret, i = -1;
10987
10988         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10989                       connector->base.id, connector->name,
10990                       encoder->base.id, encoder->name);
10991
10992         old->restore_state = NULL;
10993
10994 retry:
10995         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10996         if (ret)
10997                 goto fail;
10998
10999         /*
11000          * Algorithm gets a little messy:
11001          *
11002          *   - if the connector already has an assigned crtc, use it (but make
11003          *     sure it's on first)
11004          *
11005          *   - try to find the first unused crtc that can drive this connector,
11006          *     and use that if we find one
11007          */
11008
11009         /* See if we already have a CRTC for this connector */
11010         if (connector->state->crtc) {
11011                 crtc = connector->state->crtc;
11012
11013                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11014                 if (ret)
11015                         goto fail;
11016
11017                 /* Make sure the crtc and connector are running */
11018                 goto found;
11019         }
11020
11021         /* Find an unused one (if possible) */
11022         for_each_crtc(dev, possible_crtc) {
11023                 i++;
11024                 if (!(encoder->possible_crtcs & (1 << i)))
11025                         continue;
11026
11027                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11028                 if (ret)
11029                         goto fail;
11030
11031                 if (possible_crtc->state->enable) {
11032                         drm_modeset_unlock(&possible_crtc->mutex);
11033                         continue;
11034                 }
11035
11036                 crtc = possible_crtc;
11037                 break;
11038         }
11039
11040         /*
11041          * If we didn't find an unused CRTC, don't use any.
11042          */
11043         if (!crtc) {
11044                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11045                 goto fail;
11046         }
11047
11048 found:
11049         intel_crtc = to_intel_crtc(crtc);
11050
11051         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11052         if (ret)
11053                 goto fail;
11054
11055         state = drm_atomic_state_alloc(dev);
11056         restore_state = drm_atomic_state_alloc(dev);
11057         if (!state || !restore_state) {
11058                 ret = -ENOMEM;
11059                 goto fail;
11060         }
11061
11062         state->acquire_ctx = ctx;
11063         restore_state->acquire_ctx = ctx;
11064
11065         connector_state = drm_atomic_get_connector_state(state, connector);
11066         if (IS_ERR(connector_state)) {
11067                 ret = PTR_ERR(connector_state);
11068                 goto fail;
11069         }
11070
11071         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11072         if (ret)
11073                 goto fail;
11074
11075         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11076         if (IS_ERR(crtc_state)) {
11077                 ret = PTR_ERR(crtc_state);
11078                 goto fail;
11079         }
11080
11081         crtc_state->base.active = crtc_state->base.enable = true;
11082
11083         if (!mode)
11084                 mode = &load_detect_mode;
11085
11086         /* We need a framebuffer large enough to accommodate all accesses
11087          * that the plane may generate whilst we perform load detection.
11088          * We can not rely on the fbcon either being present (we get called
11089          * during its initialisation to detect all boot displays, or it may
11090          * not even exist) or that it is large enough to satisfy the
11091          * requested mode.
11092          */
11093         fb = mode_fits_in_fbdev(dev, mode);
11094         if (fb == NULL) {
11095                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11096                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11097         } else
11098                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11099         if (IS_ERR(fb)) {
11100                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11101                 goto fail;
11102         }
11103
11104         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11105         if (ret)
11106                 goto fail;
11107
11108         drm_framebuffer_unreference(fb);
11109
11110         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11111         if (ret)
11112                 goto fail;
11113
11114         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11115         if (!ret)
11116                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11117         if (!ret)
11118                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11119         if (ret) {
11120                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11121                 goto fail;
11122         }
11123
11124         ret = drm_atomic_commit(state);
11125         if (ret) {
11126                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11127                 goto fail;
11128         }
11129
11130         old->restore_state = restore_state;
11131
11132         /* let the connector get through one full cycle before testing */
11133         intel_wait_for_vblank(dev, intel_crtc->pipe);
11134         return true;
11135
11136 fail:
11137         drm_atomic_state_free(state);
11138         drm_atomic_state_free(restore_state);
11139         restore_state = state = NULL;
11140
11141         if (ret == -EDEADLK) {
11142                 drm_modeset_backoff(ctx);
11143                 goto retry;
11144         }
11145
11146         return false;
11147 }
11148
11149 void intel_release_load_detect_pipe(struct drm_connector *connector,
11150                                     struct intel_load_detect_pipe *old,
11151                                     struct drm_modeset_acquire_ctx *ctx)
11152 {
11153         struct intel_encoder *intel_encoder =
11154                 intel_attached_encoder(connector);
11155         struct drm_encoder *encoder = &intel_encoder->base;
11156         struct drm_atomic_state *state = old->restore_state;
11157         int ret;
11158
11159         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11160                       connector->base.id, connector->name,
11161                       encoder->base.id, encoder->name);
11162
11163         if (!state)
11164                 return;
11165
11166         ret = drm_atomic_commit(state);
11167         if (ret) {
11168                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11169                 drm_atomic_state_free(state);
11170         }
11171 }
11172
11173 static int i9xx_pll_refclk(struct drm_device *dev,
11174                            const struct intel_crtc_state *pipe_config)
11175 {
11176         struct drm_i915_private *dev_priv = to_i915(dev);
11177         u32 dpll = pipe_config->dpll_hw_state.dpll;
11178
11179         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11180                 return dev_priv->vbt.lvds_ssc_freq;
11181         else if (HAS_PCH_SPLIT(dev))
11182                 return 120000;
11183         else if (!IS_GEN2(dev))
11184                 return 96000;
11185         else
11186                 return 48000;
11187 }
11188
11189 /* Returns the clock of the currently programmed mode of the given pipe. */
11190 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11191                                 struct intel_crtc_state *pipe_config)
11192 {
11193         struct drm_device *dev = crtc->base.dev;
11194         struct drm_i915_private *dev_priv = to_i915(dev);
11195         int pipe = pipe_config->cpu_transcoder;
11196         u32 dpll = pipe_config->dpll_hw_state.dpll;
11197         u32 fp;
11198         struct dpll clock;
11199         int port_clock;
11200         int refclk = i9xx_pll_refclk(dev, pipe_config);
11201
11202         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11203                 fp = pipe_config->dpll_hw_state.fp0;
11204         else
11205                 fp = pipe_config->dpll_hw_state.fp1;
11206
11207         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11208         if (IS_PINEVIEW(dev)) {
11209                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11210                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11211         } else {
11212                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11213                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11214         }
11215
11216         if (!IS_GEN2(dev)) {
11217                 if (IS_PINEVIEW(dev))
11218                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11219                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11220                 else
11221                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11222                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11223
11224                 switch (dpll & DPLL_MODE_MASK) {
11225                 case DPLLB_MODE_DAC_SERIAL:
11226                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11227                                 5 : 10;
11228                         break;
11229                 case DPLLB_MODE_LVDS:
11230                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11231                                 7 : 14;
11232                         break;
11233                 default:
11234                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11235                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11236                         return;
11237                 }
11238
11239                 if (IS_PINEVIEW(dev))
11240                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11241                 else
11242                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11243         } else {
11244                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11245                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11246
11247                 if (is_lvds) {
11248                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11249                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11250
11251                         if (lvds & LVDS_CLKB_POWER_UP)
11252                                 clock.p2 = 7;
11253                         else
11254                                 clock.p2 = 14;
11255                 } else {
11256                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11257                                 clock.p1 = 2;
11258                         else {
11259                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11260                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11261                         }
11262                         if (dpll & PLL_P2_DIVIDE_BY_4)
11263                                 clock.p2 = 4;
11264                         else
11265                                 clock.p2 = 2;
11266                 }
11267
11268                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11269         }
11270
11271         /*
11272          * This value includes pixel_multiplier. We will use
11273          * port_clock to compute adjusted_mode.crtc_clock in the
11274          * encoder's get_config() function.
11275          */
11276         pipe_config->port_clock = port_clock;
11277 }
11278
11279 int intel_dotclock_calculate(int link_freq,
11280                              const struct intel_link_m_n *m_n)
11281 {
11282         /*
11283          * The calculation for the data clock is:
11284          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11285          * But we want to avoid losing precison if possible, so:
11286          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11287          *
11288          * and the link clock is simpler:
11289          * link_clock = (m * link_clock) / n
11290          */
11291
11292         if (!m_n->link_n)
11293                 return 0;
11294
11295         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11296 }
11297
11298 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11299                                    struct intel_crtc_state *pipe_config)
11300 {
11301         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11302
11303         /* read out port_clock from the DPLL */
11304         i9xx_crtc_clock_get(crtc, pipe_config);
11305
11306         /*
11307          * In case there is an active pipe without active ports,
11308          * we may need some idea for the dotclock anyway.
11309          * Calculate one based on the FDI configuration.
11310          */
11311         pipe_config->base.adjusted_mode.crtc_clock =
11312                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11313                                          &pipe_config->fdi_m_n);
11314 }
11315
11316 /** Returns the currently programmed mode of the given pipe. */
11317 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11318                                              struct drm_crtc *crtc)
11319 {
11320         struct drm_i915_private *dev_priv = to_i915(dev);
11321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11322         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11323         struct drm_display_mode *mode;
11324         struct intel_crtc_state *pipe_config;
11325         int htot = I915_READ(HTOTAL(cpu_transcoder));
11326         int hsync = I915_READ(HSYNC(cpu_transcoder));
11327         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11328         int vsync = I915_READ(VSYNC(cpu_transcoder));
11329         enum pipe pipe = intel_crtc->pipe;
11330
11331         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11332         if (!mode)
11333                 return NULL;
11334
11335         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11336         if (!pipe_config) {
11337                 kfree(mode);
11338                 return NULL;
11339         }
11340
11341         /*
11342          * Construct a pipe_config sufficient for getting the clock info
11343          * back out of crtc_clock_get.
11344          *
11345          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11346          * to use a real value here instead.
11347          */
11348         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11349         pipe_config->pixel_multiplier = 1;
11350         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11351         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11352         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11353         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11354
11355         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11356         mode->hdisplay = (htot & 0xffff) + 1;
11357         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11358         mode->hsync_start = (hsync & 0xffff) + 1;
11359         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11360         mode->vdisplay = (vtot & 0xffff) + 1;
11361         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11362         mode->vsync_start = (vsync & 0xffff) + 1;
11363         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11364
11365         drm_mode_set_name(mode);
11366
11367         kfree(pipe_config);
11368
11369         return mode;
11370 }
11371
11372 static void intel_crtc_destroy(struct drm_crtc *crtc)
11373 {
11374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11375         struct drm_device *dev = crtc->dev;
11376         struct intel_flip_work *work;
11377
11378         spin_lock_irq(&dev->event_lock);
11379         work = intel_crtc->flip_work;
11380         intel_crtc->flip_work = NULL;
11381         spin_unlock_irq(&dev->event_lock);
11382
11383         if (work) {
11384                 cancel_work_sync(&work->mmio_work);
11385                 cancel_work_sync(&work->unpin_work);
11386                 kfree(work);
11387         }
11388
11389         drm_crtc_cleanup(crtc);
11390
11391         kfree(intel_crtc);
11392 }
11393
11394 static void intel_unpin_work_fn(struct work_struct *__work)
11395 {
11396         struct intel_flip_work *work =
11397                 container_of(__work, struct intel_flip_work, unpin_work);
11398         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11399         struct drm_device *dev = crtc->base.dev;
11400         struct drm_plane *primary = crtc->base.primary;
11401
11402         if (is_mmio_work(work))
11403                 flush_work(&work->mmio_work);
11404
11405         mutex_lock(&dev->struct_mutex);
11406         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11407         i915_gem_object_put(work->pending_flip_obj);
11408         mutex_unlock(&dev->struct_mutex);
11409
11410         i915_gem_request_put(work->flip_queued_req);
11411
11412         intel_frontbuffer_flip_complete(to_i915(dev),
11413                                         to_intel_plane(primary)->frontbuffer_bit);
11414         intel_fbc_post_update(crtc);
11415         drm_framebuffer_unreference(work->old_fb);
11416
11417         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11418         atomic_dec(&crtc->unpin_work_count);
11419
11420         kfree(work);
11421 }
11422
11423 /* Is 'a' after or equal to 'b'? */
11424 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11425 {
11426         return !((a - b) & 0x80000000);
11427 }
11428
11429 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11430                                    struct intel_flip_work *work)
11431 {
11432         struct drm_device *dev = crtc->base.dev;
11433         struct drm_i915_private *dev_priv = to_i915(dev);
11434         unsigned reset_counter;
11435
11436         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11437         if (crtc->reset_counter != reset_counter)
11438                 return true;
11439
11440         /*
11441          * The relevant registers doen't exist on pre-ctg.
11442          * As the flip done interrupt doesn't trigger for mmio
11443          * flips on gmch platforms, a flip count check isn't
11444          * really needed there. But since ctg has the registers,
11445          * include it in the check anyway.
11446          */
11447         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11448                 return true;
11449
11450         /*
11451          * BDW signals flip done immediately if the plane
11452          * is disabled, even if the plane enable is already
11453          * armed to occur at the next vblank :(
11454          */
11455
11456         /*
11457          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11458          * used the same base address. In that case the mmio flip might
11459          * have completed, but the CS hasn't even executed the flip yet.
11460          *
11461          * A flip count check isn't enough as the CS might have updated
11462          * the base address just after start of vblank, but before we
11463          * managed to process the interrupt. This means we'd complete the
11464          * CS flip too soon.
11465          *
11466          * Combining both checks should get us a good enough result. It may
11467          * still happen that the CS flip has been executed, but has not
11468          * yet actually completed. But in case the base address is the same
11469          * anyway, we don't really care.
11470          */
11471         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11472                 crtc->flip_work->gtt_offset &&
11473                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11474                                     crtc->flip_work->flip_count);
11475 }
11476
11477 static bool
11478 __pageflip_finished_mmio(struct intel_crtc *crtc,
11479                                struct intel_flip_work *work)
11480 {
11481         /*
11482          * MMIO work completes when vblank is different from
11483          * flip_queued_vblank.
11484          *
11485          * Reset counter value doesn't matter, this is handled by
11486          * i915_wait_request finishing early, so no need to handle
11487          * reset here.
11488          */
11489         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11490 }
11491
11492
11493 static bool pageflip_finished(struct intel_crtc *crtc,
11494                               struct intel_flip_work *work)
11495 {
11496         if (!atomic_read(&work->pending))
11497                 return false;
11498
11499         smp_rmb();
11500
11501         if (is_mmio_work(work))
11502                 return __pageflip_finished_mmio(crtc, work);
11503         else
11504                 return __pageflip_finished_cs(crtc, work);
11505 }
11506
11507 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11508 {
11509         struct drm_device *dev = &dev_priv->drm;
11510         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11512         struct intel_flip_work *work;
11513         unsigned long flags;
11514
11515         /* Ignore early vblank irqs */
11516         if (!crtc)
11517                 return;
11518
11519         /*
11520          * This is called both by irq handlers and the reset code (to complete
11521          * lost pageflips) so needs the full irqsave spinlocks.
11522          */
11523         spin_lock_irqsave(&dev->event_lock, flags);
11524         work = intel_crtc->flip_work;
11525
11526         if (work != NULL &&
11527             !is_mmio_work(work) &&
11528             pageflip_finished(intel_crtc, work))
11529                 page_flip_completed(intel_crtc);
11530
11531         spin_unlock_irqrestore(&dev->event_lock, flags);
11532 }
11533
11534 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11535 {
11536         struct drm_device *dev = &dev_priv->drm;
11537         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11539         struct intel_flip_work *work;
11540         unsigned long flags;
11541
11542         /* Ignore early vblank irqs */
11543         if (!crtc)
11544                 return;
11545
11546         /*
11547          * This is called both by irq handlers and the reset code (to complete
11548          * lost pageflips) so needs the full irqsave spinlocks.
11549          */
11550         spin_lock_irqsave(&dev->event_lock, flags);
11551         work = intel_crtc->flip_work;
11552
11553         if (work != NULL &&
11554             is_mmio_work(work) &&
11555             pageflip_finished(intel_crtc, work))
11556                 page_flip_completed(intel_crtc);
11557
11558         spin_unlock_irqrestore(&dev->event_lock, flags);
11559 }
11560
11561 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11562                                                struct intel_flip_work *work)
11563 {
11564         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11565
11566         /* Ensure that the work item is consistent when activating it ... */
11567         smp_mb__before_atomic();
11568         atomic_set(&work->pending, 1);
11569 }
11570
11571 static int intel_gen2_queue_flip(struct drm_device *dev,
11572                                  struct drm_crtc *crtc,
11573                                  struct drm_framebuffer *fb,
11574                                  struct drm_i915_gem_object *obj,
11575                                  struct drm_i915_gem_request *req,
11576                                  uint32_t flags)
11577 {
11578         struct intel_ring *ring = req->ring;
11579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11580         u32 flip_mask;
11581         int ret;
11582
11583         ret = intel_ring_begin(req, 6);
11584         if (ret)
11585                 return ret;
11586
11587         /* Can't queue multiple flips, so wait for the previous
11588          * one to finish before executing the next.
11589          */
11590         if (intel_crtc->plane)
11591                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11592         else
11593                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11594         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11595         intel_ring_emit(ring, MI_NOOP);
11596         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11597                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11598         intel_ring_emit(ring, fb->pitches[0]);
11599         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11600         intel_ring_emit(ring, 0); /* aux display base address, unused */
11601
11602         return 0;
11603 }
11604
11605 static int intel_gen3_queue_flip(struct drm_device *dev,
11606                                  struct drm_crtc *crtc,
11607                                  struct drm_framebuffer *fb,
11608                                  struct drm_i915_gem_object *obj,
11609                                  struct drm_i915_gem_request *req,
11610                                  uint32_t flags)
11611 {
11612         struct intel_ring *ring = req->ring;
11613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11614         u32 flip_mask;
11615         int ret;
11616
11617         ret = intel_ring_begin(req, 6);
11618         if (ret)
11619                 return ret;
11620
11621         if (intel_crtc->plane)
11622                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11623         else
11624                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11625         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11626         intel_ring_emit(ring, MI_NOOP);
11627         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11628                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11629         intel_ring_emit(ring, fb->pitches[0]);
11630         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11631         intel_ring_emit(ring, MI_NOOP);
11632
11633         return 0;
11634 }
11635
11636 static int intel_gen4_queue_flip(struct drm_device *dev,
11637                                  struct drm_crtc *crtc,
11638                                  struct drm_framebuffer *fb,
11639                                  struct drm_i915_gem_object *obj,
11640                                  struct drm_i915_gem_request *req,
11641                                  uint32_t flags)
11642 {
11643         struct intel_ring *ring = req->ring;
11644         struct drm_i915_private *dev_priv = to_i915(dev);
11645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11646         uint32_t pf, pipesrc;
11647         int ret;
11648
11649         ret = intel_ring_begin(req, 4);
11650         if (ret)
11651                 return ret;
11652
11653         /* i965+ uses the linear or tiled offsets from the
11654          * Display Registers (which do not change across a page-flip)
11655          * so we need only reprogram the base address.
11656          */
11657         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11658                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11659         intel_ring_emit(ring, fb->pitches[0]);
11660         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11661                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11662
11663         /* XXX Enabling the panel-fitter across page-flip is so far
11664          * untested on non-native modes, so ignore it for now.
11665          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11666          */
11667         pf = 0;
11668         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11669         intel_ring_emit(ring, pf | pipesrc);
11670
11671         return 0;
11672 }
11673
11674 static int intel_gen6_queue_flip(struct drm_device *dev,
11675                                  struct drm_crtc *crtc,
11676                                  struct drm_framebuffer *fb,
11677                                  struct drm_i915_gem_object *obj,
11678                                  struct drm_i915_gem_request *req,
11679                                  uint32_t flags)
11680 {
11681         struct intel_ring *ring = req->ring;
11682         struct drm_i915_private *dev_priv = to_i915(dev);
11683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11684         uint32_t pf, pipesrc;
11685         int ret;
11686
11687         ret = intel_ring_begin(req, 4);
11688         if (ret)
11689                 return ret;
11690
11691         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11692                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11693         intel_ring_emit(ring, fb->pitches[0] |
11694                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11695         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11696
11697         /* Contrary to the suggestions in the documentation,
11698          * "Enable Panel Fitter" does not seem to be required when page
11699          * flipping with a non-native mode, and worse causes a normal
11700          * modeset to fail.
11701          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11702          */
11703         pf = 0;
11704         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11705         intel_ring_emit(ring, pf | pipesrc);
11706
11707         return 0;
11708 }
11709
11710 static int intel_gen7_queue_flip(struct drm_device *dev,
11711                                  struct drm_crtc *crtc,
11712                                  struct drm_framebuffer *fb,
11713                                  struct drm_i915_gem_object *obj,
11714                                  struct drm_i915_gem_request *req,
11715                                  uint32_t flags)
11716 {
11717         struct intel_ring *ring = req->ring;
11718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11719         uint32_t plane_bit = 0;
11720         int len, ret;
11721
11722         switch (intel_crtc->plane) {
11723         case PLANE_A:
11724                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11725                 break;
11726         case PLANE_B:
11727                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11728                 break;
11729         case PLANE_C:
11730                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11731                 break;
11732         default:
11733                 WARN_ONCE(1, "unknown plane in flip command\n");
11734                 return -ENODEV;
11735         }
11736
11737         len = 4;
11738         if (req->engine->id == RCS) {
11739                 len += 6;
11740                 /*
11741                  * On Gen 8, SRM is now taking an extra dword to accommodate
11742                  * 48bits addresses, and we need a NOOP for the batch size to
11743                  * stay even.
11744                  */
11745                 if (IS_GEN8(dev))
11746                         len += 2;
11747         }
11748
11749         /*
11750          * BSpec MI_DISPLAY_FLIP for IVB:
11751          * "The full packet must be contained within the same cache line."
11752          *
11753          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11754          * cacheline, if we ever start emitting more commands before
11755          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11756          * then do the cacheline alignment, and finally emit the
11757          * MI_DISPLAY_FLIP.
11758          */
11759         ret = intel_ring_cacheline_align(req);
11760         if (ret)
11761                 return ret;
11762
11763         ret = intel_ring_begin(req, len);
11764         if (ret)
11765                 return ret;
11766
11767         /* Unmask the flip-done completion message. Note that the bspec says that
11768          * we should do this for both the BCS and RCS, and that we must not unmask
11769          * more than one flip event at any time (or ensure that one flip message
11770          * can be sent by waiting for flip-done prior to queueing new flips).
11771          * Experimentation says that BCS works despite DERRMR masking all
11772          * flip-done completion events and that unmasking all planes at once
11773          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11774          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11775          */
11776         if (req->engine->id == RCS) {
11777                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11778                 intel_ring_emit_reg(ring, DERRMR);
11779                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11780                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11781                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11782                 if (IS_GEN8(dev))
11783                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11784                                               MI_SRM_LRM_GLOBAL_GTT);
11785                 else
11786                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11787                                               MI_SRM_LRM_GLOBAL_GTT);
11788                 intel_ring_emit_reg(ring, DERRMR);
11789                 intel_ring_emit(ring,
11790                                 i915_ggtt_offset(req->engine->scratch) + 256);
11791                 if (IS_GEN8(dev)) {
11792                         intel_ring_emit(ring, 0);
11793                         intel_ring_emit(ring, MI_NOOP);
11794                 }
11795         }
11796
11797         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11798         intel_ring_emit(ring, fb->pitches[0] |
11799                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11800         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11801         intel_ring_emit(ring, (MI_NOOP));
11802
11803         return 0;
11804 }
11805
11806 static bool use_mmio_flip(struct intel_engine_cs *engine,
11807                           struct drm_i915_gem_object *obj)
11808 {
11809         struct reservation_object *resv;
11810
11811         /*
11812          * This is not being used for older platforms, because
11813          * non-availability of flip done interrupt forces us to use
11814          * CS flips. Older platforms derive flip done using some clever
11815          * tricks involving the flip_pending status bits and vblank irqs.
11816          * So using MMIO flips there would disrupt this mechanism.
11817          */
11818
11819         if (engine == NULL)
11820                 return true;
11821
11822         if (INTEL_GEN(engine->i915) < 5)
11823                 return false;
11824
11825         if (i915.use_mmio_flip < 0)
11826                 return false;
11827         else if (i915.use_mmio_flip > 0)
11828                 return true;
11829         else if (i915.enable_execlists)
11830                 return true;
11831
11832         resv = i915_gem_object_get_dmabuf_resv(obj);
11833         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11834                 return true;
11835
11836         return engine != i915_gem_active_get_engine(&obj->last_write,
11837                                                     &obj->base.dev->struct_mutex);
11838 }
11839
11840 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11841                              unsigned int rotation,
11842                              struct intel_flip_work *work)
11843 {
11844         struct drm_device *dev = intel_crtc->base.dev;
11845         struct drm_i915_private *dev_priv = to_i915(dev);
11846         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11847         const enum pipe pipe = intel_crtc->pipe;
11848         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11849
11850         ctl = I915_READ(PLANE_CTL(pipe, 0));
11851         ctl &= ~PLANE_CTL_TILED_MASK;
11852         switch (fb->modifier[0]) {
11853         case DRM_FORMAT_MOD_NONE:
11854                 break;
11855         case I915_FORMAT_MOD_X_TILED:
11856                 ctl |= PLANE_CTL_TILED_X;
11857                 break;
11858         case I915_FORMAT_MOD_Y_TILED:
11859                 ctl |= PLANE_CTL_TILED_Y;
11860                 break;
11861         case I915_FORMAT_MOD_Yf_TILED:
11862                 ctl |= PLANE_CTL_TILED_YF;
11863                 break;
11864         default:
11865                 MISSING_CASE(fb->modifier[0]);
11866         }
11867
11868         /*
11869          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11870          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11871          */
11872         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11873         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11874
11875         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11876         POSTING_READ(PLANE_SURF(pipe, 0));
11877 }
11878
11879 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11880                              struct intel_flip_work *work)
11881 {
11882         struct drm_device *dev = intel_crtc->base.dev;
11883         struct drm_i915_private *dev_priv = to_i915(dev);
11884         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11885         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11886         u32 dspcntr;
11887
11888         dspcntr = I915_READ(reg);
11889
11890         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
11891                 dspcntr |= DISPPLANE_TILED;
11892         else
11893                 dspcntr &= ~DISPPLANE_TILED;
11894
11895         I915_WRITE(reg, dspcntr);
11896
11897         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11898         POSTING_READ(DSPSURF(intel_crtc->plane));
11899 }
11900
11901 static void intel_mmio_flip_work_func(struct work_struct *w)
11902 {
11903         struct intel_flip_work *work =
11904                 container_of(w, struct intel_flip_work, mmio_work);
11905         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11906         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11907         struct intel_framebuffer *intel_fb =
11908                 to_intel_framebuffer(crtc->base.primary->fb);
11909         struct drm_i915_gem_object *obj = intel_fb->obj;
11910         struct reservation_object *resv;
11911
11912         if (work->flip_queued_req)
11913                 WARN_ON(i915_wait_request(work->flip_queued_req,
11914                                           false, NULL,
11915                                           NO_WAITBOOST));
11916
11917         /* For framebuffer backed by dmabuf, wait for fence */
11918         resv = i915_gem_object_get_dmabuf_resv(obj);
11919         if (resv)
11920                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11921                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11922
11923         intel_pipe_update_start(crtc);
11924
11925         if (INTEL_GEN(dev_priv) >= 9)
11926                 skl_do_mmio_flip(crtc, work->rotation, work);
11927         else
11928                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11929                 ilk_do_mmio_flip(crtc, work);
11930
11931         intel_pipe_update_end(crtc, work);
11932 }
11933
11934 static int intel_default_queue_flip(struct drm_device *dev,
11935                                     struct drm_crtc *crtc,
11936                                     struct drm_framebuffer *fb,
11937                                     struct drm_i915_gem_object *obj,
11938                                     struct drm_i915_gem_request *req,
11939                                     uint32_t flags)
11940 {
11941         return -ENODEV;
11942 }
11943
11944 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11945                                       struct intel_crtc *intel_crtc,
11946                                       struct intel_flip_work *work)
11947 {
11948         u32 addr, vblank;
11949
11950         if (!atomic_read(&work->pending))
11951                 return false;
11952
11953         smp_rmb();
11954
11955         vblank = intel_crtc_get_vblank_counter(intel_crtc);
11956         if (work->flip_ready_vblank == 0) {
11957                 if (work->flip_queued_req &&
11958                     !i915_gem_request_completed(work->flip_queued_req))
11959                         return false;
11960
11961                 work->flip_ready_vblank = vblank;
11962         }
11963
11964         if (vblank - work->flip_ready_vblank < 3)
11965                 return false;
11966
11967         /* Potential stall - if we see that the flip has happened,
11968          * assume a missed interrupt. */
11969         if (INTEL_GEN(dev_priv) >= 4)
11970                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11971         else
11972                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11973
11974         /* There is a potential issue here with a false positive after a flip
11975          * to the same address. We could address this by checking for a
11976          * non-incrementing frame counter.
11977          */
11978         return addr == work->gtt_offset;
11979 }
11980
11981 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11982 {
11983         struct drm_device *dev = &dev_priv->drm;
11984         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11986         struct intel_flip_work *work;
11987
11988         WARN_ON(!in_interrupt());
11989
11990         if (crtc == NULL)
11991                 return;
11992
11993         spin_lock(&dev->event_lock);
11994         work = intel_crtc->flip_work;
11995
11996         if (work != NULL && !is_mmio_work(work) &&
11997             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11998                 WARN_ONCE(1,
11999                           "Kicking stuck page flip: queued at %d, now %d\n",
12000                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12001                 page_flip_completed(intel_crtc);
12002                 work = NULL;
12003         }
12004
12005         if (work != NULL && !is_mmio_work(work) &&
12006             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12007                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12008         spin_unlock(&dev->event_lock);
12009 }
12010
12011 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12012                                 struct drm_framebuffer *fb,
12013                                 struct drm_pending_vblank_event *event,
12014                                 uint32_t page_flip_flags)
12015 {
12016         struct drm_device *dev = crtc->dev;
12017         struct drm_i915_private *dev_priv = to_i915(dev);
12018         struct drm_framebuffer *old_fb = crtc->primary->fb;
12019         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12021         struct drm_plane *primary = crtc->primary;
12022         enum pipe pipe = intel_crtc->pipe;
12023         struct intel_flip_work *work;
12024         struct intel_engine_cs *engine;
12025         bool mmio_flip;
12026         struct drm_i915_gem_request *request;
12027         struct i915_vma *vma;
12028         int ret;
12029
12030         /*
12031          * drm_mode_page_flip_ioctl() should already catch this, but double
12032          * check to be safe.  In the future we may enable pageflipping from
12033          * a disabled primary plane.
12034          */
12035         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12036                 return -EBUSY;
12037
12038         /* Can't change pixel format via MI display flips. */
12039         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12040                 return -EINVAL;
12041
12042         /*
12043          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12044          * Note that pitch changes could also affect these register.
12045          */
12046         if (INTEL_INFO(dev)->gen > 3 &&
12047             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12048              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12049                 return -EINVAL;
12050
12051         if (i915_terminally_wedged(&dev_priv->gpu_error))
12052                 goto out_hang;
12053
12054         work = kzalloc(sizeof(*work), GFP_KERNEL);
12055         if (work == NULL)
12056                 return -ENOMEM;
12057
12058         work->event = event;
12059         work->crtc = crtc;
12060         work->old_fb = old_fb;
12061         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12062
12063         ret = drm_crtc_vblank_get(crtc);
12064         if (ret)
12065                 goto free_work;
12066
12067         /* We borrow the event spin lock for protecting flip_work */
12068         spin_lock_irq(&dev->event_lock);
12069         if (intel_crtc->flip_work) {
12070                 /* Before declaring the flip queue wedged, check if
12071                  * the hardware completed the operation behind our backs.
12072                  */
12073                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12074                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12075                         page_flip_completed(intel_crtc);
12076                 } else {
12077                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12078                         spin_unlock_irq(&dev->event_lock);
12079
12080                         drm_crtc_vblank_put(crtc);
12081                         kfree(work);
12082                         return -EBUSY;
12083                 }
12084         }
12085         intel_crtc->flip_work = work;
12086         spin_unlock_irq(&dev->event_lock);
12087
12088         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12089                 flush_workqueue(dev_priv->wq);
12090
12091         /* Reference the objects for the scheduled work. */
12092         drm_framebuffer_reference(work->old_fb);
12093
12094         crtc->primary->fb = fb;
12095         update_state_fb(crtc->primary);
12096
12097         work->pending_flip_obj = i915_gem_object_get(obj);
12098
12099         ret = i915_mutex_lock_interruptible(dev);
12100         if (ret)
12101                 goto cleanup;
12102
12103         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
12104         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
12105                 ret = -EIO;
12106                 goto cleanup;
12107         }
12108
12109         atomic_inc(&intel_crtc->unpin_work_count);
12110
12111         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12112                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12113
12114         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12115                 engine = &dev_priv->engine[BCS];
12116                 if (fb->modifier[0] != old_fb->modifier[0])
12117                         /* vlv: DISPLAY_FLIP fails to change tiling */
12118                         engine = NULL;
12119         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12120                 engine = &dev_priv->engine[BCS];
12121         } else if (INTEL_INFO(dev)->gen >= 7) {
12122                 engine = i915_gem_active_get_engine(&obj->last_write,
12123                                                     &obj->base.dev->struct_mutex);
12124                 if (engine == NULL || engine->id != RCS)
12125                         engine = &dev_priv->engine[BCS];
12126         } else {
12127                 engine = &dev_priv->engine[RCS];
12128         }
12129
12130         mmio_flip = use_mmio_flip(engine, obj);
12131
12132         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12133         if (IS_ERR(vma)) {
12134                 ret = PTR_ERR(vma);
12135                 goto cleanup_pending;
12136         }
12137
12138         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12139         work->gtt_offset += intel_crtc->dspaddr_offset;
12140         work->rotation = crtc->primary->state->rotation;
12141
12142         /*
12143          * There's the potential that the next frame will not be compatible with
12144          * FBC, so we want to call pre_update() before the actual page flip.
12145          * The problem is that pre_update() caches some information about the fb
12146          * object, so we want to do this only after the object is pinned. Let's
12147          * be on the safe side and do this immediately before scheduling the
12148          * flip.
12149          */
12150         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12151                              to_intel_plane_state(primary->state));
12152
12153         if (mmio_flip) {
12154                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12155
12156                 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12157                                                             &obj->base.dev->struct_mutex);
12158                 schedule_work(&work->mmio_work);
12159         } else {
12160                 request = i915_gem_request_alloc(engine, engine->last_context);
12161                 if (IS_ERR(request)) {
12162                         ret = PTR_ERR(request);
12163                         goto cleanup_unpin;
12164                 }
12165
12166                 ret = i915_gem_object_sync(obj, request);
12167                 if (ret)
12168                         goto cleanup_request;
12169
12170                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12171                                                    page_flip_flags);
12172                 if (ret)
12173                         goto cleanup_request;
12174
12175                 intel_mark_page_flip_active(intel_crtc, work);
12176
12177                 work->flip_queued_req = i915_gem_request_get(request);
12178                 i915_add_request_no_flush(request);
12179         }
12180
12181         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12182                           to_intel_plane(primary)->frontbuffer_bit);
12183         mutex_unlock(&dev->struct_mutex);
12184
12185         intel_frontbuffer_flip_prepare(to_i915(dev),
12186                                        to_intel_plane(primary)->frontbuffer_bit);
12187
12188         trace_i915_flip_request(intel_crtc->plane, obj);
12189
12190         return 0;
12191
12192 cleanup_request:
12193         i915_add_request_no_flush(request);
12194 cleanup_unpin:
12195         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12196 cleanup_pending:
12197         atomic_dec(&intel_crtc->unpin_work_count);
12198         mutex_unlock(&dev->struct_mutex);
12199 cleanup:
12200         crtc->primary->fb = old_fb;
12201         update_state_fb(crtc->primary);
12202
12203         i915_gem_object_put_unlocked(obj);
12204         drm_framebuffer_unreference(work->old_fb);
12205
12206         spin_lock_irq(&dev->event_lock);
12207         intel_crtc->flip_work = NULL;
12208         spin_unlock_irq(&dev->event_lock);
12209
12210         drm_crtc_vblank_put(crtc);
12211 free_work:
12212         kfree(work);
12213
12214         if (ret == -EIO) {
12215                 struct drm_atomic_state *state;
12216                 struct drm_plane_state *plane_state;
12217
12218 out_hang:
12219                 state = drm_atomic_state_alloc(dev);
12220                 if (!state)
12221                         return -ENOMEM;
12222                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12223
12224 retry:
12225                 plane_state = drm_atomic_get_plane_state(state, primary);
12226                 ret = PTR_ERR_OR_ZERO(plane_state);
12227                 if (!ret) {
12228                         drm_atomic_set_fb_for_plane(plane_state, fb);
12229
12230                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12231                         if (!ret)
12232                                 ret = drm_atomic_commit(state);
12233                 }
12234
12235                 if (ret == -EDEADLK) {
12236                         drm_modeset_backoff(state->acquire_ctx);
12237                         drm_atomic_state_clear(state);
12238                         goto retry;
12239                 }
12240
12241                 if (ret)
12242                         drm_atomic_state_free(state);
12243
12244                 if (ret == 0 && event) {
12245                         spin_lock_irq(&dev->event_lock);
12246                         drm_crtc_send_vblank_event(crtc, event);
12247                         spin_unlock_irq(&dev->event_lock);
12248                 }
12249         }
12250         return ret;
12251 }
12252
12253
12254 /**
12255  * intel_wm_need_update - Check whether watermarks need updating
12256  * @plane: drm plane
12257  * @state: new plane state
12258  *
12259  * Check current plane state versus the new one to determine whether
12260  * watermarks need to be recalculated.
12261  *
12262  * Returns true or false.
12263  */
12264 static bool intel_wm_need_update(struct drm_plane *plane,
12265                                  struct drm_plane_state *state)
12266 {
12267         struct intel_plane_state *new = to_intel_plane_state(state);
12268         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12269
12270         /* Update watermarks on tiling or size changes. */
12271         if (new->base.visible != cur->base.visible)
12272                 return true;
12273
12274         if (!cur->base.fb || !new->base.fb)
12275                 return false;
12276
12277         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12278             cur->base.rotation != new->base.rotation ||
12279             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12280             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12281             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12282             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12283                 return true;
12284
12285         return false;
12286 }
12287
12288 static bool needs_scaling(struct intel_plane_state *state)
12289 {
12290         int src_w = drm_rect_width(&state->base.src) >> 16;
12291         int src_h = drm_rect_height(&state->base.src) >> 16;
12292         int dst_w = drm_rect_width(&state->base.dst);
12293         int dst_h = drm_rect_height(&state->base.dst);
12294
12295         return (src_w != dst_w || src_h != dst_h);
12296 }
12297
12298 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12299                                     struct drm_plane_state *plane_state)
12300 {
12301         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12302         struct drm_crtc *crtc = crtc_state->crtc;
12303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12304         struct drm_plane *plane = plane_state->plane;
12305         struct drm_device *dev = crtc->dev;
12306         struct drm_i915_private *dev_priv = to_i915(dev);
12307         struct intel_plane_state *old_plane_state =
12308                 to_intel_plane_state(plane->state);
12309         bool mode_changed = needs_modeset(crtc_state);
12310         bool was_crtc_enabled = crtc->state->active;
12311         bool is_crtc_enabled = crtc_state->active;
12312         bool turn_off, turn_on, visible, was_visible;
12313         struct drm_framebuffer *fb = plane_state->fb;
12314         int ret;
12315
12316         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12317                 ret = skl_update_scaler_plane(
12318                         to_intel_crtc_state(crtc_state),
12319                         to_intel_plane_state(plane_state));
12320                 if (ret)
12321                         return ret;
12322         }
12323
12324         was_visible = old_plane_state->base.visible;
12325         visible = to_intel_plane_state(plane_state)->base.visible;
12326
12327         if (!was_crtc_enabled && WARN_ON(was_visible))
12328                 was_visible = false;
12329
12330         /*
12331          * Visibility is calculated as if the crtc was on, but
12332          * after scaler setup everything depends on it being off
12333          * when the crtc isn't active.
12334          *
12335          * FIXME this is wrong for watermarks. Watermarks should also
12336          * be computed as if the pipe would be active. Perhaps move
12337          * per-plane wm computation to the .check_plane() hook, and
12338          * only combine the results from all planes in the current place?
12339          */
12340         if (!is_crtc_enabled)
12341                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12342
12343         if (!was_visible && !visible)
12344                 return 0;
12345
12346         if (fb != old_plane_state->base.fb)
12347                 pipe_config->fb_changed = true;
12348
12349         turn_off = was_visible && (!visible || mode_changed);
12350         turn_on = visible && (!was_visible || mode_changed);
12351
12352         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12353                          intel_crtc->base.base.id,
12354                          intel_crtc->base.name,
12355                          plane->base.id, plane->name,
12356                          fb ? fb->base.id : -1);
12357
12358         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12359                          plane->base.id, plane->name,
12360                          was_visible, visible,
12361                          turn_off, turn_on, mode_changed);
12362
12363         if (turn_on) {
12364                 pipe_config->update_wm_pre = true;
12365
12366                 /* must disable cxsr around plane enable/disable */
12367                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12368                         pipe_config->disable_cxsr = true;
12369         } else if (turn_off) {
12370                 pipe_config->update_wm_post = true;
12371
12372                 /* must disable cxsr around plane enable/disable */
12373                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12374                         pipe_config->disable_cxsr = true;
12375         } else if (intel_wm_need_update(plane, plane_state)) {
12376                 /* FIXME bollocks */
12377                 pipe_config->update_wm_pre = true;
12378                 pipe_config->update_wm_post = true;
12379         }
12380
12381         /* Pre-gen9 platforms need two-step watermark updates */
12382         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12383             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12384                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12385
12386         if (visible || was_visible)
12387                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12388
12389         /*
12390          * WaCxSRDisabledForSpriteScaling:ivb
12391          *
12392          * cstate->update_wm was already set above, so this flag will
12393          * take effect when we commit and program watermarks.
12394          */
12395         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12396             needs_scaling(to_intel_plane_state(plane_state)) &&
12397             !needs_scaling(old_plane_state))
12398                 pipe_config->disable_lp_wm = true;
12399
12400         return 0;
12401 }
12402
12403 static bool encoders_cloneable(const struct intel_encoder *a,
12404                                const struct intel_encoder *b)
12405 {
12406         /* masks could be asymmetric, so check both ways */
12407         return a == b || (a->cloneable & (1 << b->type) &&
12408                           b->cloneable & (1 << a->type));
12409 }
12410
12411 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12412                                          struct intel_crtc *crtc,
12413                                          struct intel_encoder *encoder)
12414 {
12415         struct intel_encoder *source_encoder;
12416         struct drm_connector *connector;
12417         struct drm_connector_state *connector_state;
12418         int i;
12419
12420         for_each_connector_in_state(state, connector, connector_state, i) {
12421                 if (connector_state->crtc != &crtc->base)
12422                         continue;
12423
12424                 source_encoder =
12425                         to_intel_encoder(connector_state->best_encoder);
12426                 if (!encoders_cloneable(encoder, source_encoder))
12427                         return false;
12428         }
12429
12430         return true;
12431 }
12432
12433 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12434                                    struct drm_crtc_state *crtc_state)
12435 {
12436         struct drm_device *dev = crtc->dev;
12437         struct drm_i915_private *dev_priv = to_i915(dev);
12438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12439         struct intel_crtc_state *pipe_config =
12440                 to_intel_crtc_state(crtc_state);
12441         struct drm_atomic_state *state = crtc_state->state;
12442         int ret;
12443         bool mode_changed = needs_modeset(crtc_state);
12444
12445         if (mode_changed && !crtc_state->active)
12446                 pipe_config->update_wm_post = true;
12447
12448         if (mode_changed && crtc_state->enable &&
12449             dev_priv->display.crtc_compute_clock &&
12450             !WARN_ON(pipe_config->shared_dpll)) {
12451                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12452                                                            pipe_config);
12453                 if (ret)
12454                         return ret;
12455         }
12456
12457         if (crtc_state->color_mgmt_changed) {
12458                 ret = intel_color_check(crtc, crtc_state);
12459                 if (ret)
12460                         return ret;
12461
12462                 /*
12463                  * Changing color management on Intel hardware is
12464                  * handled as part of planes update.
12465                  */
12466                 crtc_state->planes_changed = true;
12467         }
12468
12469         ret = 0;
12470         if (dev_priv->display.compute_pipe_wm) {
12471                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12472                 if (ret) {
12473                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12474                         return ret;
12475                 }
12476         }
12477
12478         if (dev_priv->display.compute_intermediate_wm &&
12479             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12480                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12481                         return 0;
12482
12483                 /*
12484                  * Calculate 'intermediate' watermarks that satisfy both the
12485                  * old state and the new state.  We can program these
12486                  * immediately.
12487                  */
12488                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12489                                                                 intel_crtc,
12490                                                                 pipe_config);
12491                 if (ret) {
12492                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12493                         return ret;
12494                 }
12495         } else if (dev_priv->display.compute_intermediate_wm) {
12496                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12497                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12498         }
12499
12500         if (INTEL_INFO(dev)->gen >= 9) {
12501                 if (mode_changed)
12502                         ret = skl_update_scaler_crtc(pipe_config);
12503
12504                 if (!ret)
12505                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12506                                                          pipe_config);
12507         }
12508
12509         return ret;
12510 }
12511
12512 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12513         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12514         .atomic_begin = intel_begin_crtc_commit,
12515         .atomic_flush = intel_finish_crtc_commit,
12516         .atomic_check = intel_crtc_atomic_check,
12517 };
12518
12519 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12520 {
12521         struct intel_connector *connector;
12522
12523         for_each_intel_connector(dev, connector) {
12524                 if (connector->base.state->crtc)
12525                         drm_connector_unreference(&connector->base);
12526
12527                 if (connector->base.encoder) {
12528                         connector->base.state->best_encoder =
12529                                 connector->base.encoder;
12530                         connector->base.state->crtc =
12531                                 connector->base.encoder->crtc;
12532
12533                         drm_connector_reference(&connector->base);
12534                 } else {
12535                         connector->base.state->best_encoder = NULL;
12536                         connector->base.state->crtc = NULL;
12537                 }
12538         }
12539 }
12540
12541 static void
12542 connected_sink_compute_bpp(struct intel_connector *connector,
12543                            struct intel_crtc_state *pipe_config)
12544 {
12545         int bpp = pipe_config->pipe_bpp;
12546
12547         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12548                 connector->base.base.id,
12549                 connector->base.name);
12550
12551         /* Don't use an invalid EDID bpc value */
12552         if (connector->base.display_info.bpc &&
12553             connector->base.display_info.bpc * 3 < bpp) {
12554                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12555                               bpp, connector->base.display_info.bpc*3);
12556                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12557         }
12558
12559         /* Clamp bpp to 8 on screens without EDID 1.4 */
12560         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12561                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12562                               bpp);
12563                 pipe_config->pipe_bpp = 24;
12564         }
12565 }
12566
12567 static int
12568 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12569                           struct intel_crtc_state *pipe_config)
12570 {
12571         struct drm_device *dev = crtc->base.dev;
12572         struct drm_atomic_state *state;
12573         struct drm_connector *connector;
12574         struct drm_connector_state *connector_state;
12575         int bpp, i;
12576
12577         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12578                 bpp = 10*3;
12579         else if (INTEL_INFO(dev)->gen >= 5)
12580                 bpp = 12*3;
12581         else
12582                 bpp = 8*3;
12583
12584
12585         pipe_config->pipe_bpp = bpp;
12586
12587         state = pipe_config->base.state;
12588
12589         /* Clamp display bpp to EDID value */
12590         for_each_connector_in_state(state, connector, connector_state, i) {
12591                 if (connector_state->crtc != &crtc->base)
12592                         continue;
12593
12594                 connected_sink_compute_bpp(to_intel_connector(connector),
12595                                            pipe_config);
12596         }
12597
12598         return bpp;
12599 }
12600
12601 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12602 {
12603         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12604                         "type: 0x%x flags: 0x%x\n",
12605                 mode->crtc_clock,
12606                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12607                 mode->crtc_hsync_end, mode->crtc_htotal,
12608                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12609                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12610 }
12611
12612 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12613                                    struct intel_crtc_state *pipe_config,
12614                                    const char *context)
12615 {
12616         struct drm_device *dev = crtc->base.dev;
12617         struct drm_plane *plane;
12618         struct intel_plane *intel_plane;
12619         struct intel_plane_state *state;
12620         struct drm_framebuffer *fb;
12621
12622         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12623                       crtc->base.base.id, crtc->base.name,
12624                       context, pipe_config, pipe_name(crtc->pipe));
12625
12626         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12627         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12628                       pipe_config->pipe_bpp, pipe_config->dither);
12629         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12630                       pipe_config->has_pch_encoder,
12631                       pipe_config->fdi_lanes,
12632                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12633                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12634                       pipe_config->fdi_m_n.tu);
12635         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12636                       intel_crtc_has_dp_encoder(pipe_config),
12637                       pipe_config->lane_count,
12638                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12639                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12640                       pipe_config->dp_m_n.tu);
12641
12642         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12643                       intel_crtc_has_dp_encoder(pipe_config),
12644                       pipe_config->lane_count,
12645                       pipe_config->dp_m2_n2.gmch_m,
12646                       pipe_config->dp_m2_n2.gmch_n,
12647                       pipe_config->dp_m2_n2.link_m,
12648                       pipe_config->dp_m2_n2.link_n,
12649                       pipe_config->dp_m2_n2.tu);
12650
12651         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12652                       pipe_config->has_audio,
12653                       pipe_config->has_infoframe);
12654
12655         DRM_DEBUG_KMS("requested mode:\n");
12656         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12657         DRM_DEBUG_KMS("adjusted mode:\n");
12658         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12659         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12660         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12661         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12662                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12663         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12664                       crtc->num_scalers,
12665                       pipe_config->scaler_state.scaler_users,
12666                       pipe_config->scaler_state.scaler_id);
12667         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12668                       pipe_config->gmch_pfit.control,
12669                       pipe_config->gmch_pfit.pgm_ratios,
12670                       pipe_config->gmch_pfit.lvds_border_bits);
12671         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12672                       pipe_config->pch_pfit.pos,
12673                       pipe_config->pch_pfit.size,
12674                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12675         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12676         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12677
12678         if (IS_BROXTON(dev)) {
12679                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12680                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12681                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12682                               pipe_config->ddi_pll_sel,
12683                               pipe_config->dpll_hw_state.ebb0,
12684                               pipe_config->dpll_hw_state.ebb4,
12685                               pipe_config->dpll_hw_state.pll0,
12686                               pipe_config->dpll_hw_state.pll1,
12687                               pipe_config->dpll_hw_state.pll2,
12688                               pipe_config->dpll_hw_state.pll3,
12689                               pipe_config->dpll_hw_state.pll6,
12690                               pipe_config->dpll_hw_state.pll8,
12691                               pipe_config->dpll_hw_state.pll9,
12692                               pipe_config->dpll_hw_state.pll10,
12693                               pipe_config->dpll_hw_state.pcsdw12);
12694         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12695                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12696                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12697                               pipe_config->ddi_pll_sel,
12698                               pipe_config->dpll_hw_state.ctrl1,
12699                               pipe_config->dpll_hw_state.cfgcr1,
12700                               pipe_config->dpll_hw_state.cfgcr2);
12701         } else if (HAS_DDI(dev)) {
12702                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12703                               pipe_config->ddi_pll_sel,
12704                               pipe_config->dpll_hw_state.wrpll,
12705                               pipe_config->dpll_hw_state.spll);
12706         } else {
12707                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12708                               "fp0: 0x%x, fp1: 0x%x\n",
12709                               pipe_config->dpll_hw_state.dpll,
12710                               pipe_config->dpll_hw_state.dpll_md,
12711                               pipe_config->dpll_hw_state.fp0,
12712                               pipe_config->dpll_hw_state.fp1);
12713         }
12714
12715         DRM_DEBUG_KMS("planes on this crtc\n");
12716         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12717                 intel_plane = to_intel_plane(plane);
12718                 if (intel_plane->pipe != crtc->pipe)
12719                         continue;
12720
12721                 state = to_intel_plane_state(plane->state);
12722                 fb = state->base.fb;
12723                 if (!fb) {
12724                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12725                                       plane->base.id, plane->name, state->scaler_id);
12726                         continue;
12727                 }
12728
12729                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12730                               plane->base.id, plane->name);
12731                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12732                               fb->base.id, fb->width, fb->height,
12733                               drm_get_format_name(fb->pixel_format));
12734                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12735                               state->scaler_id,
12736                               state->base.src.x1 >> 16,
12737                               state->base.src.y1 >> 16,
12738                               drm_rect_width(&state->base.src) >> 16,
12739                               drm_rect_height(&state->base.src) >> 16,
12740                               state->base.dst.x1, state->base.dst.y1,
12741                               drm_rect_width(&state->base.dst),
12742                               drm_rect_height(&state->base.dst));
12743         }
12744 }
12745
12746 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12747 {
12748         struct drm_device *dev = state->dev;
12749         struct drm_connector *connector;
12750         unsigned int used_ports = 0;
12751         unsigned int used_mst_ports = 0;
12752
12753         /*
12754          * Walk the connector list instead of the encoder
12755          * list to detect the problem on ddi platforms
12756          * where there's just one encoder per digital port.
12757          */
12758         drm_for_each_connector(connector, dev) {
12759                 struct drm_connector_state *connector_state;
12760                 struct intel_encoder *encoder;
12761
12762                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12763                 if (!connector_state)
12764                         connector_state = connector->state;
12765
12766                 if (!connector_state->best_encoder)
12767                         continue;
12768
12769                 encoder = to_intel_encoder(connector_state->best_encoder);
12770
12771                 WARN_ON(!connector_state->crtc);
12772
12773                 switch (encoder->type) {
12774                         unsigned int port_mask;
12775                 case INTEL_OUTPUT_UNKNOWN:
12776                         if (WARN_ON(!HAS_DDI(dev)))
12777                                 break;
12778                 case INTEL_OUTPUT_DP:
12779                 case INTEL_OUTPUT_HDMI:
12780                 case INTEL_OUTPUT_EDP:
12781                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12782
12783                         /* the same port mustn't appear more than once */
12784                         if (used_ports & port_mask)
12785                                 return false;
12786
12787                         used_ports |= port_mask;
12788                         break;
12789                 case INTEL_OUTPUT_DP_MST:
12790                         used_mst_ports |=
12791                                 1 << enc_to_mst(&encoder->base)->primary->port;
12792                         break;
12793                 default:
12794                         break;
12795                 }
12796         }
12797
12798         /* can't mix MST and SST/HDMI on the same port */
12799         if (used_ports & used_mst_ports)
12800                 return false;
12801
12802         return true;
12803 }
12804
12805 static void
12806 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12807 {
12808         struct drm_crtc_state tmp_state;
12809         struct intel_crtc_scaler_state scaler_state;
12810         struct intel_dpll_hw_state dpll_hw_state;
12811         struct intel_shared_dpll *shared_dpll;
12812         uint32_t ddi_pll_sel;
12813         bool force_thru;
12814
12815         /* FIXME: before the switch to atomic started, a new pipe_config was
12816          * kzalloc'd. Code that depends on any field being zero should be
12817          * fixed, so that the crtc_state can be safely duplicated. For now,
12818          * only fields that are know to not cause problems are preserved. */
12819
12820         tmp_state = crtc_state->base;
12821         scaler_state = crtc_state->scaler_state;
12822         shared_dpll = crtc_state->shared_dpll;
12823         dpll_hw_state = crtc_state->dpll_hw_state;
12824         ddi_pll_sel = crtc_state->ddi_pll_sel;
12825         force_thru = crtc_state->pch_pfit.force_thru;
12826
12827         memset(crtc_state, 0, sizeof *crtc_state);
12828
12829         crtc_state->base = tmp_state;
12830         crtc_state->scaler_state = scaler_state;
12831         crtc_state->shared_dpll = shared_dpll;
12832         crtc_state->dpll_hw_state = dpll_hw_state;
12833         crtc_state->ddi_pll_sel = ddi_pll_sel;
12834         crtc_state->pch_pfit.force_thru = force_thru;
12835 }
12836
12837 static int
12838 intel_modeset_pipe_config(struct drm_crtc *crtc,
12839                           struct intel_crtc_state *pipe_config)
12840 {
12841         struct drm_atomic_state *state = pipe_config->base.state;
12842         struct intel_encoder *encoder;
12843         struct drm_connector *connector;
12844         struct drm_connector_state *connector_state;
12845         int base_bpp, ret = -EINVAL;
12846         int i;
12847         bool retry = true;
12848
12849         clear_intel_crtc_state(pipe_config);
12850
12851         pipe_config->cpu_transcoder =
12852                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12853
12854         /*
12855          * Sanitize sync polarity flags based on requested ones. If neither
12856          * positive or negative polarity is requested, treat this as meaning
12857          * negative polarity.
12858          */
12859         if (!(pipe_config->base.adjusted_mode.flags &
12860               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12861                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12862
12863         if (!(pipe_config->base.adjusted_mode.flags &
12864               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12865                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12866
12867         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12868                                              pipe_config);
12869         if (base_bpp < 0)
12870                 goto fail;
12871
12872         /*
12873          * Determine the real pipe dimensions. Note that stereo modes can
12874          * increase the actual pipe size due to the frame doubling and
12875          * insertion of additional space for blanks between the frame. This
12876          * is stored in the crtc timings. We use the requested mode to do this
12877          * computation to clearly distinguish it from the adjusted mode, which
12878          * can be changed by the connectors in the below retry loop.
12879          */
12880         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12881                                &pipe_config->pipe_src_w,
12882                                &pipe_config->pipe_src_h);
12883
12884         for_each_connector_in_state(state, connector, connector_state, i) {
12885                 if (connector_state->crtc != crtc)
12886                         continue;
12887
12888                 encoder = to_intel_encoder(connector_state->best_encoder);
12889
12890                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12891                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12892                         goto fail;
12893                 }
12894
12895                 /*
12896                  * Determine output_types before calling the .compute_config()
12897                  * hooks so that the hooks can use this information safely.
12898                  */
12899                 pipe_config->output_types |= 1 << encoder->type;
12900         }
12901
12902 encoder_retry:
12903         /* Ensure the port clock defaults are reset when retrying. */
12904         pipe_config->port_clock = 0;
12905         pipe_config->pixel_multiplier = 1;
12906
12907         /* Fill in default crtc timings, allow encoders to overwrite them. */
12908         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12909                               CRTC_STEREO_DOUBLE);
12910
12911         /* Pass our mode to the connectors and the CRTC to give them a chance to
12912          * adjust it according to limitations or connector properties, and also
12913          * a chance to reject the mode entirely.
12914          */
12915         for_each_connector_in_state(state, connector, connector_state, i) {
12916                 if (connector_state->crtc != crtc)
12917                         continue;
12918
12919                 encoder = to_intel_encoder(connector_state->best_encoder);
12920
12921                 if (!(encoder->compute_config(encoder, pipe_config))) {
12922                         DRM_DEBUG_KMS("Encoder config failure\n");
12923                         goto fail;
12924                 }
12925         }
12926
12927         /* Set default port clock if not overwritten by the encoder. Needs to be
12928          * done afterwards in case the encoder adjusts the mode. */
12929         if (!pipe_config->port_clock)
12930                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12931                         * pipe_config->pixel_multiplier;
12932
12933         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12934         if (ret < 0) {
12935                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12936                 goto fail;
12937         }
12938
12939         if (ret == RETRY) {
12940                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12941                         ret = -EINVAL;
12942                         goto fail;
12943                 }
12944
12945                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12946                 retry = false;
12947                 goto encoder_retry;
12948         }
12949
12950         /* Dithering seems to not pass-through bits correctly when it should, so
12951          * only enable it on 6bpc panels. */
12952         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12953         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12954                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12955
12956 fail:
12957         return ret;
12958 }
12959
12960 static void
12961 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12962 {
12963         struct drm_crtc *crtc;
12964         struct drm_crtc_state *crtc_state;
12965         int i;
12966
12967         /* Double check state. */
12968         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12969                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12970
12971                 /* Update hwmode for vblank functions */
12972                 if (crtc->state->active)
12973                         crtc->hwmode = crtc->state->adjusted_mode;
12974                 else
12975                         crtc->hwmode.crtc_clock = 0;
12976
12977                 /*
12978                  * Update legacy state to satisfy fbc code. This can
12979                  * be removed when fbc uses the atomic state.
12980                  */
12981                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12982                         struct drm_plane_state *plane_state = crtc->primary->state;
12983
12984                         crtc->primary->fb = plane_state->fb;
12985                         crtc->x = plane_state->src_x >> 16;
12986                         crtc->y = plane_state->src_y >> 16;
12987                 }
12988         }
12989 }
12990
12991 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12992 {
12993         int diff;
12994
12995         if (clock1 == clock2)
12996                 return true;
12997
12998         if (!clock1 || !clock2)
12999                 return false;
13000
13001         diff = abs(clock1 - clock2);
13002
13003         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13004                 return true;
13005
13006         return false;
13007 }
13008
13009 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
13010         list_for_each_entry((intel_crtc), \
13011                             &(dev)->mode_config.crtc_list, \
13012                             base.head) \
13013                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
13014
13015 static bool
13016 intel_compare_m_n(unsigned int m, unsigned int n,
13017                   unsigned int m2, unsigned int n2,
13018                   bool exact)
13019 {
13020         if (m == m2 && n == n2)
13021                 return true;
13022
13023         if (exact || !m || !n || !m2 || !n2)
13024                 return false;
13025
13026         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13027
13028         if (n > n2) {
13029                 while (n > n2) {
13030                         m2 <<= 1;
13031                         n2 <<= 1;
13032                 }
13033         } else if (n < n2) {
13034                 while (n < n2) {
13035                         m <<= 1;
13036                         n <<= 1;
13037                 }
13038         }
13039
13040         if (n != n2)
13041                 return false;
13042
13043         return intel_fuzzy_clock_check(m, m2);
13044 }
13045
13046 static bool
13047 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13048                        struct intel_link_m_n *m2_n2,
13049                        bool adjust)
13050 {
13051         if (m_n->tu == m2_n2->tu &&
13052             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13053                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13054             intel_compare_m_n(m_n->link_m, m_n->link_n,
13055                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13056                 if (adjust)
13057                         *m2_n2 = *m_n;
13058
13059                 return true;
13060         }
13061
13062         return false;
13063 }
13064
13065 static bool
13066 intel_pipe_config_compare(struct drm_device *dev,
13067                           struct intel_crtc_state *current_config,
13068                           struct intel_crtc_state *pipe_config,
13069                           bool adjust)
13070 {
13071         bool ret = true;
13072
13073 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13074         do { \
13075                 if (!adjust) \
13076                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13077                 else \
13078                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13079         } while (0)
13080
13081 #define PIPE_CONF_CHECK_X(name) \
13082         if (current_config->name != pipe_config->name) { \
13083                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13084                           "(expected 0x%08x, found 0x%08x)\n", \
13085                           current_config->name, \
13086                           pipe_config->name); \
13087                 ret = false; \
13088         }
13089
13090 #define PIPE_CONF_CHECK_I(name) \
13091         if (current_config->name != pipe_config->name) { \
13092                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13093                           "(expected %i, found %i)\n", \
13094                           current_config->name, \
13095                           pipe_config->name); \
13096                 ret = false; \
13097         }
13098
13099 #define PIPE_CONF_CHECK_P(name) \
13100         if (current_config->name != pipe_config->name) { \
13101                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13102                           "(expected %p, found %p)\n", \
13103                           current_config->name, \
13104                           pipe_config->name); \
13105                 ret = false; \
13106         }
13107
13108 #define PIPE_CONF_CHECK_M_N(name) \
13109         if (!intel_compare_link_m_n(&current_config->name, \
13110                                     &pipe_config->name,\
13111                                     adjust)) { \
13112                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13113                           "(expected tu %i gmch %i/%i link %i/%i, " \
13114                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13115                           current_config->name.tu, \
13116                           current_config->name.gmch_m, \
13117                           current_config->name.gmch_n, \
13118                           current_config->name.link_m, \
13119                           current_config->name.link_n, \
13120                           pipe_config->name.tu, \
13121                           pipe_config->name.gmch_m, \
13122                           pipe_config->name.gmch_n, \
13123                           pipe_config->name.link_m, \
13124                           pipe_config->name.link_n); \
13125                 ret = false; \
13126         }
13127
13128 /* This is required for BDW+ where there is only one set of registers for
13129  * switching between high and low RR.
13130  * This macro can be used whenever a comparison has to be made between one
13131  * hw state and multiple sw state variables.
13132  */
13133 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13134         if (!intel_compare_link_m_n(&current_config->name, \
13135                                     &pipe_config->name, adjust) && \
13136             !intel_compare_link_m_n(&current_config->alt_name, \
13137                                     &pipe_config->name, adjust)) { \
13138                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13139                           "(expected tu %i gmch %i/%i link %i/%i, " \
13140                           "or tu %i gmch %i/%i link %i/%i, " \
13141                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13142                           current_config->name.tu, \
13143                           current_config->name.gmch_m, \
13144                           current_config->name.gmch_n, \
13145                           current_config->name.link_m, \
13146                           current_config->name.link_n, \
13147                           current_config->alt_name.tu, \
13148                           current_config->alt_name.gmch_m, \
13149                           current_config->alt_name.gmch_n, \
13150                           current_config->alt_name.link_m, \
13151                           current_config->alt_name.link_n, \
13152                           pipe_config->name.tu, \
13153                           pipe_config->name.gmch_m, \
13154                           pipe_config->name.gmch_n, \
13155                           pipe_config->name.link_m, \
13156                           pipe_config->name.link_n); \
13157                 ret = false; \
13158         }
13159
13160 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13161         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13162                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13163                           "(expected %i, found %i)\n", \
13164                           current_config->name & (mask), \
13165                           pipe_config->name & (mask)); \
13166                 ret = false; \
13167         }
13168
13169 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13170         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13171                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13172                           "(expected %i, found %i)\n", \
13173                           current_config->name, \
13174                           pipe_config->name); \
13175                 ret = false; \
13176         }
13177
13178 #define PIPE_CONF_QUIRK(quirk)  \
13179         ((current_config->quirks | pipe_config->quirks) & (quirk))
13180
13181         PIPE_CONF_CHECK_I(cpu_transcoder);
13182
13183         PIPE_CONF_CHECK_I(has_pch_encoder);
13184         PIPE_CONF_CHECK_I(fdi_lanes);
13185         PIPE_CONF_CHECK_M_N(fdi_m_n);
13186
13187         PIPE_CONF_CHECK_I(lane_count);
13188         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13189
13190         if (INTEL_INFO(dev)->gen < 8) {
13191                 PIPE_CONF_CHECK_M_N(dp_m_n);
13192
13193                 if (current_config->has_drrs)
13194                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13195         } else
13196                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13197
13198         PIPE_CONF_CHECK_X(output_types);
13199
13200         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13201         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13202         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13203         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13204         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13205         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13206
13207         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13208         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13209         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13210         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13211         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13212         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13213
13214         PIPE_CONF_CHECK_I(pixel_multiplier);
13215         PIPE_CONF_CHECK_I(has_hdmi_sink);
13216         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13217             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13218                 PIPE_CONF_CHECK_I(limited_color_range);
13219         PIPE_CONF_CHECK_I(has_infoframe);
13220
13221         PIPE_CONF_CHECK_I(has_audio);
13222
13223         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13224                               DRM_MODE_FLAG_INTERLACE);
13225
13226         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13227                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13228                                       DRM_MODE_FLAG_PHSYNC);
13229                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13230                                       DRM_MODE_FLAG_NHSYNC);
13231                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13232                                       DRM_MODE_FLAG_PVSYNC);
13233                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13234                                       DRM_MODE_FLAG_NVSYNC);
13235         }
13236
13237         PIPE_CONF_CHECK_X(gmch_pfit.control);
13238         /* pfit ratios are autocomputed by the hw on gen4+ */
13239         if (INTEL_INFO(dev)->gen < 4)
13240                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13241         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13242
13243         if (!adjust) {
13244                 PIPE_CONF_CHECK_I(pipe_src_w);
13245                 PIPE_CONF_CHECK_I(pipe_src_h);
13246
13247                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13248                 if (current_config->pch_pfit.enabled) {
13249                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13250                         PIPE_CONF_CHECK_X(pch_pfit.size);
13251                 }
13252
13253                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13254         }
13255
13256         /* BDW+ don't expose a synchronous way to read the state */
13257         if (IS_HASWELL(dev))
13258                 PIPE_CONF_CHECK_I(ips_enabled);
13259
13260         PIPE_CONF_CHECK_I(double_wide);
13261
13262         PIPE_CONF_CHECK_X(ddi_pll_sel);
13263
13264         PIPE_CONF_CHECK_P(shared_dpll);
13265         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13266         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13267         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13268         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13269         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13270         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13271         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13272         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13273         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13274
13275         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13276         PIPE_CONF_CHECK_X(dsi_pll.div);
13277
13278         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13279                 PIPE_CONF_CHECK_I(pipe_bpp);
13280
13281         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13282         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13283
13284 #undef PIPE_CONF_CHECK_X
13285 #undef PIPE_CONF_CHECK_I
13286 #undef PIPE_CONF_CHECK_P
13287 #undef PIPE_CONF_CHECK_FLAGS
13288 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13289 #undef PIPE_CONF_QUIRK
13290 #undef INTEL_ERR_OR_DBG_KMS
13291
13292         return ret;
13293 }
13294
13295 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13296                                            const struct intel_crtc_state *pipe_config)
13297 {
13298         if (pipe_config->has_pch_encoder) {
13299                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13300                                                             &pipe_config->fdi_m_n);
13301                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13302
13303                 /*
13304                  * FDI already provided one idea for the dotclock.
13305                  * Yell if the encoder disagrees.
13306                  */
13307                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13308                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13309                      fdi_dotclock, dotclock);
13310         }
13311 }
13312
13313 static void verify_wm_state(struct drm_crtc *crtc,
13314                             struct drm_crtc_state *new_state)
13315 {
13316         struct drm_device *dev = crtc->dev;
13317         struct drm_i915_private *dev_priv = to_i915(dev);
13318         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13319         struct skl_ddb_entry *hw_entry, *sw_entry;
13320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13321         const enum pipe pipe = intel_crtc->pipe;
13322         int plane;
13323
13324         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13325                 return;
13326
13327         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13328         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13329
13330         /* planes */
13331         for_each_plane(dev_priv, pipe, plane) {
13332                 hw_entry = &hw_ddb.plane[pipe][plane];
13333                 sw_entry = &sw_ddb->plane[pipe][plane];
13334
13335                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13336                         continue;
13337
13338                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13339                           "(expected (%u,%u), found (%u,%u))\n",
13340                           pipe_name(pipe), plane + 1,
13341                           sw_entry->start, sw_entry->end,
13342                           hw_entry->start, hw_entry->end);
13343         }
13344
13345         /* cursor */
13346         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13347         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13348
13349         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13350                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13351                           "(expected (%u,%u), found (%u,%u))\n",
13352                           pipe_name(pipe),
13353                           sw_entry->start, sw_entry->end,
13354                           hw_entry->start, hw_entry->end);
13355         }
13356 }
13357
13358 static void
13359 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13360 {
13361         struct drm_connector *connector;
13362
13363         drm_for_each_connector(connector, dev) {
13364                 struct drm_encoder *encoder = connector->encoder;
13365                 struct drm_connector_state *state = connector->state;
13366
13367                 if (state->crtc != crtc)
13368                         continue;
13369
13370                 intel_connector_verify_state(to_intel_connector(connector));
13371
13372                 I915_STATE_WARN(state->best_encoder != encoder,
13373                      "connector's atomic encoder doesn't match legacy encoder\n");
13374         }
13375 }
13376
13377 static void
13378 verify_encoder_state(struct drm_device *dev)
13379 {
13380         struct intel_encoder *encoder;
13381         struct intel_connector *connector;
13382
13383         for_each_intel_encoder(dev, encoder) {
13384                 bool enabled = false;
13385                 enum pipe pipe;
13386
13387                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13388                               encoder->base.base.id,
13389                               encoder->base.name);
13390
13391                 for_each_intel_connector(dev, connector) {
13392                         if (connector->base.state->best_encoder != &encoder->base)
13393                                 continue;
13394                         enabled = true;
13395
13396                         I915_STATE_WARN(connector->base.state->crtc !=
13397                                         encoder->base.crtc,
13398                              "connector's crtc doesn't match encoder crtc\n");
13399                 }
13400
13401                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13402                      "encoder's enabled state mismatch "
13403                      "(expected %i, found %i)\n",
13404                      !!encoder->base.crtc, enabled);
13405
13406                 if (!encoder->base.crtc) {
13407                         bool active;
13408
13409                         active = encoder->get_hw_state(encoder, &pipe);
13410                         I915_STATE_WARN(active,
13411                              "encoder detached but still enabled on pipe %c.\n",
13412                              pipe_name(pipe));
13413                 }
13414         }
13415 }
13416
13417 static void
13418 verify_crtc_state(struct drm_crtc *crtc,
13419                   struct drm_crtc_state *old_crtc_state,
13420                   struct drm_crtc_state *new_crtc_state)
13421 {
13422         struct drm_device *dev = crtc->dev;
13423         struct drm_i915_private *dev_priv = to_i915(dev);
13424         struct intel_encoder *encoder;
13425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13426         struct intel_crtc_state *pipe_config, *sw_config;
13427         struct drm_atomic_state *old_state;
13428         bool active;
13429
13430         old_state = old_crtc_state->state;
13431         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13432         pipe_config = to_intel_crtc_state(old_crtc_state);
13433         memset(pipe_config, 0, sizeof(*pipe_config));
13434         pipe_config->base.crtc = crtc;
13435         pipe_config->base.state = old_state;
13436
13437         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13438
13439         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13440
13441         /* hw state is inconsistent with the pipe quirk */
13442         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13443             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13444                 active = new_crtc_state->active;
13445
13446         I915_STATE_WARN(new_crtc_state->active != active,
13447              "crtc active state doesn't match with hw state "
13448              "(expected %i, found %i)\n", new_crtc_state->active, active);
13449
13450         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13451              "transitional active state does not match atomic hw state "
13452              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13453
13454         for_each_encoder_on_crtc(dev, crtc, encoder) {
13455                 enum pipe pipe;
13456
13457                 active = encoder->get_hw_state(encoder, &pipe);
13458                 I915_STATE_WARN(active != new_crtc_state->active,
13459                         "[ENCODER:%i] active %i with crtc active %i\n",
13460                         encoder->base.base.id, active, new_crtc_state->active);
13461
13462                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13463                                 "Encoder connected to wrong pipe %c\n",
13464                                 pipe_name(pipe));
13465
13466                 if (active) {
13467                         pipe_config->output_types |= 1 << encoder->type;
13468                         encoder->get_config(encoder, pipe_config);
13469                 }
13470         }
13471
13472         if (!new_crtc_state->active)
13473                 return;
13474
13475         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13476
13477         sw_config = to_intel_crtc_state(crtc->state);
13478         if (!intel_pipe_config_compare(dev, sw_config,
13479                                        pipe_config, false)) {
13480                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13481                 intel_dump_pipe_config(intel_crtc, pipe_config,
13482                                        "[hw state]");
13483                 intel_dump_pipe_config(intel_crtc, sw_config,
13484                                        "[sw state]");
13485         }
13486 }
13487
13488 static void
13489 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13490                          struct intel_shared_dpll *pll,
13491                          struct drm_crtc *crtc,
13492                          struct drm_crtc_state *new_state)
13493 {
13494         struct intel_dpll_hw_state dpll_hw_state;
13495         unsigned crtc_mask;
13496         bool active;
13497
13498         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13499
13500         DRM_DEBUG_KMS("%s\n", pll->name);
13501
13502         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13503
13504         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13505                 I915_STATE_WARN(!pll->on && pll->active_mask,
13506                      "pll in active use but not on in sw tracking\n");
13507                 I915_STATE_WARN(pll->on && !pll->active_mask,
13508                      "pll is on but not used by any active crtc\n");
13509                 I915_STATE_WARN(pll->on != active,
13510                      "pll on state mismatch (expected %i, found %i)\n",
13511                      pll->on, active);
13512         }
13513
13514         if (!crtc) {
13515                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13516                                 "more active pll users than references: %x vs %x\n",
13517                                 pll->active_mask, pll->config.crtc_mask);
13518
13519                 return;
13520         }
13521
13522         crtc_mask = 1 << drm_crtc_index(crtc);
13523
13524         if (new_state->active)
13525                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13526                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13527                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13528         else
13529                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13530                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13531                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13532
13533         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13534                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13535                         crtc_mask, pll->config.crtc_mask);
13536
13537         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13538                                           &dpll_hw_state,
13539                                           sizeof(dpll_hw_state)),
13540                         "pll hw state mismatch\n");
13541 }
13542
13543 static void
13544 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13545                          struct drm_crtc_state *old_crtc_state,
13546                          struct drm_crtc_state *new_crtc_state)
13547 {
13548         struct drm_i915_private *dev_priv = to_i915(dev);
13549         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13550         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13551
13552         if (new_state->shared_dpll)
13553                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13554
13555         if (old_state->shared_dpll &&
13556             old_state->shared_dpll != new_state->shared_dpll) {
13557                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13558                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13559
13560                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13561                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13562                                 pipe_name(drm_crtc_index(crtc)));
13563                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13564                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13565                                 pipe_name(drm_crtc_index(crtc)));
13566         }
13567 }
13568
13569 static void
13570 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13571                          struct drm_crtc_state *old_state,
13572                          struct drm_crtc_state *new_state)
13573 {
13574         if (!needs_modeset(new_state) &&
13575             !to_intel_crtc_state(new_state)->update_pipe)
13576                 return;
13577
13578         verify_wm_state(crtc, new_state);
13579         verify_connector_state(crtc->dev, crtc);
13580         verify_crtc_state(crtc, old_state, new_state);
13581         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13582 }
13583
13584 static void
13585 verify_disabled_dpll_state(struct drm_device *dev)
13586 {
13587         struct drm_i915_private *dev_priv = to_i915(dev);
13588         int i;
13589
13590         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13591                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13592 }
13593
13594 static void
13595 intel_modeset_verify_disabled(struct drm_device *dev)
13596 {
13597         verify_encoder_state(dev);
13598         verify_connector_state(dev, NULL);
13599         verify_disabled_dpll_state(dev);
13600 }
13601
13602 static void update_scanline_offset(struct intel_crtc *crtc)
13603 {
13604         struct drm_device *dev = crtc->base.dev;
13605
13606         /*
13607          * The scanline counter increments at the leading edge of hsync.
13608          *
13609          * On most platforms it starts counting from vtotal-1 on the
13610          * first active line. That means the scanline counter value is
13611          * always one less than what we would expect. Ie. just after
13612          * start of vblank, which also occurs at start of hsync (on the
13613          * last active line), the scanline counter will read vblank_start-1.
13614          *
13615          * On gen2 the scanline counter starts counting from 1 instead
13616          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13617          * to keep the value positive), instead of adding one.
13618          *
13619          * On HSW+ the behaviour of the scanline counter depends on the output
13620          * type. For DP ports it behaves like most other platforms, but on HDMI
13621          * there's an extra 1 line difference. So we need to add two instead of
13622          * one to the value.
13623          */
13624         if (IS_GEN2(dev)) {
13625                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13626                 int vtotal;
13627
13628                 vtotal = adjusted_mode->crtc_vtotal;
13629                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13630                         vtotal /= 2;
13631
13632                 crtc->scanline_offset = vtotal - 1;
13633         } else if (HAS_DDI(dev) &&
13634                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13635                 crtc->scanline_offset = 2;
13636         } else
13637                 crtc->scanline_offset = 1;
13638 }
13639
13640 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13641 {
13642         struct drm_device *dev = state->dev;
13643         struct drm_i915_private *dev_priv = to_i915(dev);
13644         struct intel_shared_dpll_config *shared_dpll = NULL;
13645         struct drm_crtc *crtc;
13646         struct drm_crtc_state *crtc_state;
13647         int i;
13648
13649         if (!dev_priv->display.crtc_compute_clock)
13650                 return;
13651
13652         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13653                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13654                 struct intel_shared_dpll *old_dpll =
13655                         to_intel_crtc_state(crtc->state)->shared_dpll;
13656
13657                 if (!needs_modeset(crtc_state))
13658                         continue;
13659
13660                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13661
13662                 if (!old_dpll)
13663                         continue;
13664
13665                 if (!shared_dpll)
13666                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13667
13668                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13669         }
13670 }
13671
13672 /*
13673  * This implements the workaround described in the "notes" section of the mode
13674  * set sequence documentation. When going from no pipes or single pipe to
13675  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13676  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13677  */
13678 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13679 {
13680         struct drm_crtc_state *crtc_state;
13681         struct intel_crtc *intel_crtc;
13682         struct drm_crtc *crtc;
13683         struct intel_crtc_state *first_crtc_state = NULL;
13684         struct intel_crtc_state *other_crtc_state = NULL;
13685         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13686         int i;
13687
13688         /* look at all crtc's that are going to be enabled in during modeset */
13689         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13690                 intel_crtc = to_intel_crtc(crtc);
13691
13692                 if (!crtc_state->active || !needs_modeset(crtc_state))
13693                         continue;
13694
13695                 if (first_crtc_state) {
13696                         other_crtc_state = to_intel_crtc_state(crtc_state);
13697                         break;
13698                 } else {
13699                         first_crtc_state = to_intel_crtc_state(crtc_state);
13700                         first_pipe = intel_crtc->pipe;
13701                 }
13702         }
13703
13704         /* No workaround needed? */
13705         if (!first_crtc_state)
13706                 return 0;
13707
13708         /* w/a possibly needed, check how many crtc's are already enabled. */
13709         for_each_intel_crtc(state->dev, intel_crtc) {
13710                 struct intel_crtc_state *pipe_config;
13711
13712                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13713                 if (IS_ERR(pipe_config))
13714                         return PTR_ERR(pipe_config);
13715
13716                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13717
13718                 if (!pipe_config->base.active ||
13719                     needs_modeset(&pipe_config->base))
13720                         continue;
13721
13722                 /* 2 or more enabled crtcs means no need for w/a */
13723                 if (enabled_pipe != INVALID_PIPE)
13724                         return 0;
13725
13726                 enabled_pipe = intel_crtc->pipe;
13727         }
13728
13729         if (enabled_pipe != INVALID_PIPE)
13730                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13731         else if (other_crtc_state)
13732                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13733
13734         return 0;
13735 }
13736
13737 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13738 {
13739         struct drm_crtc *crtc;
13740         struct drm_crtc_state *crtc_state;
13741         int ret = 0;
13742
13743         /* add all active pipes to the state */
13744         for_each_crtc(state->dev, crtc) {
13745                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13746                 if (IS_ERR(crtc_state))
13747                         return PTR_ERR(crtc_state);
13748
13749                 if (!crtc_state->active || needs_modeset(crtc_state))
13750                         continue;
13751
13752                 crtc_state->mode_changed = true;
13753
13754                 ret = drm_atomic_add_affected_connectors(state, crtc);
13755                 if (ret)
13756                         break;
13757
13758                 ret = drm_atomic_add_affected_planes(state, crtc);
13759                 if (ret)
13760                         break;
13761         }
13762
13763         return ret;
13764 }
13765
13766 static int intel_modeset_checks(struct drm_atomic_state *state)
13767 {
13768         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13769         struct drm_i915_private *dev_priv = to_i915(state->dev);
13770         struct drm_crtc *crtc;
13771         struct drm_crtc_state *crtc_state;
13772         int ret = 0, i;
13773
13774         if (!check_digital_port_conflicts(state)) {
13775                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13776                 return -EINVAL;
13777         }
13778
13779         intel_state->modeset = true;
13780         intel_state->active_crtcs = dev_priv->active_crtcs;
13781
13782         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13783                 if (crtc_state->active)
13784                         intel_state->active_crtcs |= 1 << i;
13785                 else
13786                         intel_state->active_crtcs &= ~(1 << i);
13787
13788                 if (crtc_state->active != crtc->state->active)
13789                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13790         }
13791
13792         /*
13793          * See if the config requires any additional preparation, e.g.
13794          * to adjust global state with pipes off.  We need to do this
13795          * here so we can get the modeset_pipe updated config for the new
13796          * mode set on this crtc.  For other crtcs we need to use the
13797          * adjusted_mode bits in the crtc directly.
13798          */
13799         if (dev_priv->display.modeset_calc_cdclk) {
13800                 if (!intel_state->cdclk_pll_vco)
13801                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13802                 if (!intel_state->cdclk_pll_vco)
13803                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13804
13805                 ret = dev_priv->display.modeset_calc_cdclk(state);
13806                 if (ret < 0)
13807                         return ret;
13808
13809                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13810                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13811                         ret = intel_modeset_all_pipes(state);
13812
13813                 if (ret < 0)
13814                         return ret;
13815
13816                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13817                               intel_state->cdclk, intel_state->dev_cdclk);
13818         } else
13819                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13820
13821         intel_modeset_clear_plls(state);
13822
13823         if (IS_HASWELL(dev_priv))
13824                 return haswell_mode_set_planes_workaround(state);
13825
13826         return 0;
13827 }
13828
13829 /*
13830  * Handle calculation of various watermark data at the end of the atomic check
13831  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13832  * handlers to ensure that all derived state has been updated.
13833  */
13834 static int calc_watermark_data(struct drm_atomic_state *state)
13835 {
13836         struct drm_device *dev = state->dev;
13837         struct drm_i915_private *dev_priv = to_i915(dev);
13838
13839         /* Is there platform-specific watermark information to calculate? */
13840         if (dev_priv->display.compute_global_watermarks)
13841                 return dev_priv->display.compute_global_watermarks(state);
13842
13843         return 0;
13844 }
13845
13846 /**
13847  * intel_atomic_check - validate state object
13848  * @dev: drm device
13849  * @state: state to validate
13850  */
13851 static int intel_atomic_check(struct drm_device *dev,
13852                               struct drm_atomic_state *state)
13853 {
13854         struct drm_i915_private *dev_priv = to_i915(dev);
13855         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13856         struct drm_crtc *crtc;
13857         struct drm_crtc_state *crtc_state;
13858         int ret, i;
13859         bool any_ms = false;
13860
13861         ret = drm_atomic_helper_check_modeset(dev, state);
13862         if (ret)
13863                 return ret;
13864
13865         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13866                 struct intel_crtc_state *pipe_config =
13867                         to_intel_crtc_state(crtc_state);
13868
13869                 /* Catch I915_MODE_FLAG_INHERITED */
13870                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13871                         crtc_state->mode_changed = true;
13872
13873                 if (!needs_modeset(crtc_state))
13874                         continue;
13875
13876                 if (!crtc_state->enable) {
13877                         any_ms = true;
13878                         continue;
13879                 }
13880
13881                 /* FIXME: For only active_changed we shouldn't need to do any
13882                  * state recomputation at all. */
13883
13884                 ret = drm_atomic_add_affected_connectors(state, crtc);
13885                 if (ret)
13886                         return ret;
13887
13888                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13889                 if (ret) {
13890                         intel_dump_pipe_config(to_intel_crtc(crtc),
13891                                                pipe_config, "[failed]");
13892                         return ret;
13893                 }
13894
13895                 if (i915.fastboot &&
13896                     intel_pipe_config_compare(dev,
13897                                         to_intel_crtc_state(crtc->state),
13898                                         pipe_config, true)) {
13899                         crtc_state->mode_changed = false;
13900                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13901                 }
13902
13903                 if (needs_modeset(crtc_state))
13904                         any_ms = true;
13905
13906                 ret = drm_atomic_add_affected_planes(state, crtc);
13907                 if (ret)
13908                         return ret;
13909
13910                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13911                                        needs_modeset(crtc_state) ?
13912                                        "[modeset]" : "[fastset]");
13913         }
13914
13915         if (any_ms) {
13916                 ret = intel_modeset_checks(state);
13917
13918                 if (ret)
13919                         return ret;
13920         } else
13921                 intel_state->cdclk = dev_priv->cdclk_freq;
13922
13923         ret = drm_atomic_helper_check_planes(dev, state);
13924         if (ret)
13925                 return ret;
13926
13927         intel_fbc_choose_crtc(dev_priv, state);
13928         return calc_watermark_data(state);
13929 }
13930
13931 static int intel_atomic_prepare_commit(struct drm_device *dev,
13932                                        struct drm_atomic_state *state,
13933                                        bool nonblock)
13934 {
13935         struct drm_i915_private *dev_priv = to_i915(dev);
13936         struct drm_plane_state *plane_state;
13937         struct drm_crtc_state *crtc_state;
13938         struct drm_plane *plane;
13939         struct drm_crtc *crtc;
13940         int i, ret;
13941
13942         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13943                 if (state->legacy_cursor_update)
13944                         continue;
13945
13946                 ret = intel_crtc_wait_for_pending_flips(crtc);
13947                 if (ret)
13948                         return ret;
13949
13950                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13951                         flush_workqueue(dev_priv->wq);
13952         }
13953
13954         ret = mutex_lock_interruptible(&dev->struct_mutex);
13955         if (ret)
13956                 return ret;
13957
13958         ret = drm_atomic_helper_prepare_planes(dev, state);
13959         mutex_unlock(&dev->struct_mutex);
13960
13961         if (!ret && !nonblock) {
13962                 for_each_plane_in_state(state, plane, plane_state, i) {
13963                         struct intel_plane_state *intel_plane_state =
13964                                 to_intel_plane_state(plane_state);
13965
13966                         if (!intel_plane_state->wait_req)
13967                                 continue;
13968
13969                         ret = i915_wait_request(intel_plane_state->wait_req,
13970                                                 true, NULL, NULL);
13971                         if (ret) {
13972                                 /* Any hang should be swallowed by the wait */
13973                                 WARN_ON(ret == -EIO);
13974                                 mutex_lock(&dev->struct_mutex);
13975                                 drm_atomic_helper_cleanup_planes(dev, state);
13976                                 mutex_unlock(&dev->struct_mutex);
13977                                 break;
13978                         }
13979                 }
13980         }
13981
13982         return ret;
13983 }
13984
13985 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13986 {
13987         struct drm_device *dev = crtc->base.dev;
13988
13989         if (!dev->max_vblank_count)
13990                 return drm_accurate_vblank_count(&crtc->base);
13991
13992         return dev->driver->get_vblank_counter(dev, crtc->pipe);
13993 }
13994
13995 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13996                                           struct drm_i915_private *dev_priv,
13997                                           unsigned crtc_mask)
13998 {
13999         unsigned last_vblank_count[I915_MAX_PIPES];
14000         enum pipe pipe;
14001         int ret;
14002
14003         if (!crtc_mask)
14004                 return;
14005
14006         for_each_pipe(dev_priv, pipe) {
14007                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14008
14009                 if (!((1 << pipe) & crtc_mask))
14010                         continue;
14011
14012                 ret = drm_crtc_vblank_get(crtc);
14013                 if (WARN_ON(ret != 0)) {
14014                         crtc_mask &= ~(1 << pipe);
14015                         continue;
14016                 }
14017
14018                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14019         }
14020
14021         for_each_pipe(dev_priv, pipe) {
14022                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14023                 long lret;
14024
14025                 if (!((1 << pipe) & crtc_mask))
14026                         continue;
14027
14028                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14029                                 last_vblank_count[pipe] !=
14030                                         drm_crtc_vblank_count(crtc),
14031                                 msecs_to_jiffies(50));
14032
14033                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14034
14035                 drm_crtc_vblank_put(crtc);
14036         }
14037 }
14038
14039 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14040 {
14041         /* fb updated, need to unpin old fb */
14042         if (crtc_state->fb_changed)
14043                 return true;
14044
14045         /* wm changes, need vblank before final wm's */
14046         if (crtc_state->update_wm_post)
14047                 return true;
14048
14049         /*
14050          * cxsr is re-enabled after vblank.
14051          * This is already handled by crtc_state->update_wm_post,
14052          * but added for clarity.
14053          */
14054         if (crtc_state->disable_cxsr)
14055                 return true;
14056
14057         return false;
14058 }
14059
14060 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14061 {
14062         struct drm_device *dev = state->dev;
14063         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14064         struct drm_i915_private *dev_priv = to_i915(dev);
14065         struct drm_crtc_state *old_crtc_state;
14066         struct drm_crtc *crtc;
14067         struct intel_crtc_state *intel_cstate;
14068         struct drm_plane *plane;
14069         struct drm_plane_state *plane_state;
14070         bool hw_check = intel_state->modeset;
14071         unsigned long put_domains[I915_MAX_PIPES] = {};
14072         unsigned crtc_vblank_mask = 0;
14073         int i, ret;
14074
14075         for_each_plane_in_state(state, plane, plane_state, i) {
14076                 struct intel_plane_state *intel_plane_state =
14077                         to_intel_plane_state(plane_state);
14078
14079                 if (!intel_plane_state->wait_req)
14080                         continue;
14081
14082                 ret = i915_wait_request(intel_plane_state->wait_req,
14083                                         true, NULL, NULL);
14084                 /* EIO should be eaten, and we can't get interrupted in the
14085                  * worker, and blocking commits have waited already. */
14086                 WARN_ON(ret);
14087         }
14088
14089         drm_atomic_helper_wait_for_dependencies(state);
14090
14091         if (intel_state->modeset) {
14092                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14093                        sizeof(intel_state->min_pixclk));
14094                 dev_priv->active_crtcs = intel_state->active_crtcs;
14095                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14096
14097                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14098         }
14099
14100         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14101                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14102
14103                 if (needs_modeset(crtc->state) ||
14104                     to_intel_crtc_state(crtc->state)->update_pipe) {
14105                         hw_check = true;
14106
14107                         put_domains[to_intel_crtc(crtc)->pipe] =
14108                                 modeset_get_crtc_power_domains(crtc,
14109                                         to_intel_crtc_state(crtc->state));
14110                 }
14111
14112                 if (!needs_modeset(crtc->state))
14113                         continue;
14114
14115                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14116
14117                 if (old_crtc_state->active) {
14118                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14119                         dev_priv->display.crtc_disable(crtc);
14120                         intel_crtc->active = false;
14121                         intel_fbc_disable(intel_crtc);
14122                         intel_disable_shared_dpll(intel_crtc);
14123
14124                         /*
14125                          * Underruns don't always raise
14126                          * interrupts, so check manually.
14127                          */
14128                         intel_check_cpu_fifo_underruns(dev_priv);
14129                         intel_check_pch_fifo_underruns(dev_priv);
14130
14131                         if (!crtc->state->active)
14132                                 intel_update_watermarks(crtc);
14133                 }
14134         }
14135
14136         /* Only after disabling all output pipelines that will be changed can we
14137          * update the the output configuration. */
14138         intel_modeset_update_crtc_state(state);
14139
14140         if (intel_state->modeset) {
14141                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14142
14143                 if (dev_priv->display.modeset_commit_cdclk &&
14144                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14145                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14146                         dev_priv->display.modeset_commit_cdclk(state);
14147
14148                 intel_modeset_verify_disabled(dev);
14149         }
14150
14151         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14152         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14153                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14154                 bool modeset = needs_modeset(crtc->state);
14155                 struct intel_crtc_state *pipe_config =
14156                         to_intel_crtc_state(crtc->state);
14157
14158                 if (modeset && crtc->state->active) {
14159                         update_scanline_offset(to_intel_crtc(crtc));
14160                         dev_priv->display.crtc_enable(crtc);
14161                 }
14162
14163                 /* Complete events for now disable pipes here. */
14164                 if (modeset && !crtc->state->active && crtc->state->event) {
14165                         spin_lock_irq(&dev->event_lock);
14166                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14167                         spin_unlock_irq(&dev->event_lock);
14168
14169                         crtc->state->event = NULL;
14170                 }
14171
14172                 if (!modeset)
14173                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14174
14175                 if (crtc->state->active &&
14176                     drm_atomic_get_existing_plane_state(state, crtc->primary))
14177                         intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
14178
14179                 if (crtc->state->active)
14180                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14181
14182                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
14183                         crtc_vblank_mask |= 1 << i;
14184         }
14185
14186         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14187          * already, but still need the state for the delayed optimization. To
14188          * fix this:
14189          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14190          * - schedule that vblank worker _before_ calling hw_done
14191          * - at the start of commit_tail, cancel it _synchrously
14192          * - switch over to the vblank wait helper in the core after that since
14193          *   we don't need out special handling any more.
14194          */
14195         if (!state->legacy_cursor_update)
14196                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14197
14198         /*
14199          * Now that the vblank has passed, we can go ahead and program the
14200          * optimal watermarks on platforms that need two-step watermark
14201          * programming.
14202          *
14203          * TODO: Move this (and other cleanup) to an async worker eventually.
14204          */
14205         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14206                 intel_cstate = to_intel_crtc_state(crtc->state);
14207
14208                 if (dev_priv->display.optimize_watermarks)
14209                         dev_priv->display.optimize_watermarks(intel_cstate);
14210         }
14211
14212         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14213                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14214
14215                 if (put_domains[i])
14216                         modeset_put_power_domains(dev_priv, put_domains[i]);
14217
14218                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14219         }
14220
14221         drm_atomic_helper_commit_hw_done(state);
14222
14223         if (intel_state->modeset)
14224                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14225
14226         mutex_lock(&dev->struct_mutex);
14227         drm_atomic_helper_cleanup_planes(dev, state);
14228         mutex_unlock(&dev->struct_mutex);
14229
14230         drm_atomic_helper_commit_cleanup_done(state);
14231
14232         drm_atomic_state_free(state);
14233
14234         /* As one of the primary mmio accessors, KMS has a high likelihood
14235          * of triggering bugs in unclaimed access. After we finish
14236          * modesetting, see if an error has been flagged, and if so
14237          * enable debugging for the next modeset - and hope we catch
14238          * the culprit.
14239          *
14240          * XXX note that we assume display power is on at this point.
14241          * This might hold true now but we need to add pm helper to check
14242          * unclaimed only when the hardware is on, as atomic commits
14243          * can happen also when the device is completely off.
14244          */
14245         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14246 }
14247
14248 static void intel_atomic_commit_work(struct work_struct *work)
14249 {
14250         struct drm_atomic_state *state = container_of(work,
14251                                                       struct drm_atomic_state,
14252                                                       commit_work);
14253         intel_atomic_commit_tail(state);
14254 }
14255
14256 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14257 {
14258         struct drm_plane_state *old_plane_state;
14259         struct drm_plane *plane;
14260         int i;
14261
14262         for_each_plane_in_state(state, plane, old_plane_state, i)
14263                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14264                                   intel_fb_obj(plane->state->fb),
14265                                   to_intel_plane(plane)->frontbuffer_bit);
14266 }
14267
14268 /**
14269  * intel_atomic_commit - commit validated state object
14270  * @dev: DRM device
14271  * @state: the top-level driver state object
14272  * @nonblock: nonblocking commit
14273  *
14274  * This function commits a top-level state object that has been validated
14275  * with drm_atomic_helper_check().
14276  *
14277  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
14278  * nonblocking commits are only safe for pure plane updates. Everything else
14279  * should work though.
14280  *
14281  * RETURNS
14282  * Zero for success or -errno.
14283  */
14284 static int intel_atomic_commit(struct drm_device *dev,
14285                                struct drm_atomic_state *state,
14286                                bool nonblock)
14287 {
14288         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14289         struct drm_i915_private *dev_priv = to_i915(dev);
14290         int ret = 0;
14291
14292         if (intel_state->modeset && nonblock) {
14293                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14294                 return -EINVAL;
14295         }
14296
14297         ret = drm_atomic_helper_setup_commit(state, nonblock);
14298         if (ret)
14299                 return ret;
14300
14301         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14302
14303         ret = intel_atomic_prepare_commit(dev, state, nonblock);
14304         if (ret) {
14305                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14306                 return ret;
14307         }
14308
14309         drm_atomic_helper_swap_state(state, true);
14310         dev_priv->wm.distrust_bios_wm = false;
14311         dev_priv->wm.skl_results = intel_state->wm_results;
14312         intel_shared_dpll_commit(state);
14313         intel_atomic_track_fbs(state);
14314
14315         if (nonblock)
14316                 queue_work(system_unbound_wq, &state->commit_work);
14317         else
14318                 intel_atomic_commit_tail(state);
14319
14320         return 0;
14321 }
14322
14323 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14324 {
14325         struct drm_device *dev = crtc->dev;
14326         struct drm_atomic_state *state;
14327         struct drm_crtc_state *crtc_state;
14328         int ret;
14329
14330         state = drm_atomic_state_alloc(dev);
14331         if (!state) {
14332                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14333                               crtc->base.id, crtc->name);
14334                 return;
14335         }
14336
14337         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14338
14339 retry:
14340         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14341         ret = PTR_ERR_OR_ZERO(crtc_state);
14342         if (!ret) {
14343                 if (!crtc_state->active)
14344                         goto out;
14345
14346                 crtc_state->mode_changed = true;
14347                 ret = drm_atomic_commit(state);
14348         }
14349
14350         if (ret == -EDEADLK) {
14351                 drm_atomic_state_clear(state);
14352                 drm_modeset_backoff(state->acquire_ctx);
14353                 goto retry;
14354         }
14355
14356         if (ret)
14357 out:
14358                 drm_atomic_state_free(state);
14359 }
14360
14361 #undef for_each_intel_crtc_masked
14362
14363 /*
14364  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14365  *        drm_atomic_helper_legacy_gamma_set() directly.
14366  */
14367 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14368                                          u16 *red, u16 *green, u16 *blue,
14369                                          uint32_t size)
14370 {
14371         struct drm_device *dev = crtc->dev;
14372         struct drm_mode_config *config = &dev->mode_config;
14373         struct drm_crtc_state *state;
14374         int ret;
14375
14376         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14377         if (ret)
14378                 return ret;
14379
14380         /*
14381          * Make sure we update the legacy properties so this works when
14382          * atomic is not enabled.
14383          */
14384
14385         state = crtc->state;
14386
14387         drm_object_property_set_value(&crtc->base,
14388                                       config->degamma_lut_property,
14389                                       (state->degamma_lut) ?
14390                                       state->degamma_lut->base.id : 0);
14391
14392         drm_object_property_set_value(&crtc->base,
14393                                       config->ctm_property,
14394                                       (state->ctm) ?
14395                                       state->ctm->base.id : 0);
14396
14397         drm_object_property_set_value(&crtc->base,
14398                                       config->gamma_lut_property,
14399                                       (state->gamma_lut) ?
14400                                       state->gamma_lut->base.id : 0);
14401
14402         return 0;
14403 }
14404
14405 static const struct drm_crtc_funcs intel_crtc_funcs = {
14406         .gamma_set = intel_atomic_legacy_gamma_set,
14407         .set_config = drm_atomic_helper_set_config,
14408         .set_property = drm_atomic_helper_crtc_set_property,
14409         .destroy = intel_crtc_destroy,
14410         .page_flip = intel_crtc_page_flip,
14411         .atomic_duplicate_state = intel_crtc_duplicate_state,
14412         .atomic_destroy_state = intel_crtc_destroy_state,
14413 };
14414
14415 /**
14416  * intel_prepare_plane_fb - Prepare fb for usage on plane
14417  * @plane: drm plane to prepare for
14418  * @fb: framebuffer to prepare for presentation
14419  *
14420  * Prepares a framebuffer for usage on a display plane.  Generally this
14421  * involves pinning the underlying object and updating the frontbuffer tracking
14422  * bits.  Some older platforms need special physical address handling for
14423  * cursor planes.
14424  *
14425  * Must be called with struct_mutex held.
14426  *
14427  * Returns 0 on success, negative error code on failure.
14428  */
14429 int
14430 intel_prepare_plane_fb(struct drm_plane *plane,
14431                        const struct drm_plane_state *new_state)
14432 {
14433         struct drm_device *dev = plane->dev;
14434         struct drm_framebuffer *fb = new_state->fb;
14435         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14436         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14437         struct reservation_object *resv;
14438         int ret = 0;
14439
14440         if (!obj && !old_obj)
14441                 return 0;
14442
14443         if (old_obj) {
14444                 struct drm_crtc_state *crtc_state =
14445                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14446
14447                 /* Big Hammer, we also need to ensure that any pending
14448                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14449                  * current scanout is retired before unpinning the old
14450                  * framebuffer. Note that we rely on userspace rendering
14451                  * into the buffer attached to the pipe they are waiting
14452                  * on. If not, userspace generates a GPU hang with IPEHR
14453                  * point to the MI_WAIT_FOR_EVENT.
14454                  *
14455                  * This should only fail upon a hung GPU, in which case we
14456                  * can safely continue.
14457                  */
14458                 if (needs_modeset(crtc_state))
14459                         ret = i915_gem_object_wait_rendering(old_obj, true);
14460                 if (ret) {
14461                         /* GPU hangs should have been swallowed by the wait */
14462                         WARN_ON(ret == -EIO);
14463                         return ret;
14464                 }
14465         }
14466
14467         if (!obj)
14468                 return 0;
14469
14470         /* For framebuffer backed by dmabuf, wait for fence */
14471         resv = i915_gem_object_get_dmabuf_resv(obj);
14472         if (resv) {
14473                 long lret;
14474
14475                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14476                                                            MAX_SCHEDULE_TIMEOUT);
14477                 if (lret == -ERESTARTSYS)
14478                         return lret;
14479
14480                 WARN(lret < 0, "waiting returns %li\n", lret);
14481         }
14482
14483         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14484             INTEL_INFO(dev)->cursor_needs_physical) {
14485                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14486                 ret = i915_gem_object_attach_phys(obj, align);
14487                 if (ret)
14488                         DRM_DEBUG_KMS("failed to attach phys object\n");
14489         } else {
14490                 struct i915_vma *vma;
14491
14492                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14493                 if (IS_ERR(vma))
14494                         ret = PTR_ERR(vma);
14495         }
14496
14497         if (ret == 0) {
14498                 to_intel_plane_state(new_state)->wait_req =
14499                         i915_gem_active_get(&obj->last_write,
14500                                             &obj->base.dev->struct_mutex);
14501         }
14502
14503         return ret;
14504 }
14505
14506 /**
14507  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14508  * @plane: drm plane to clean up for
14509  * @fb: old framebuffer that was on plane
14510  *
14511  * Cleans up a framebuffer that has just been removed from a plane.
14512  *
14513  * Must be called with struct_mutex held.
14514  */
14515 void
14516 intel_cleanup_plane_fb(struct drm_plane *plane,
14517                        const struct drm_plane_state *old_state)
14518 {
14519         struct drm_device *dev = plane->dev;
14520         struct intel_plane_state *old_intel_state;
14521         struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14522         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14523         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14524
14525         old_intel_state = to_intel_plane_state(old_state);
14526
14527         if (!obj && !old_obj)
14528                 return;
14529
14530         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14531             !INTEL_INFO(dev)->cursor_needs_physical))
14532                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14533
14534         i915_gem_request_assign(&intel_state->wait_req, NULL);
14535         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14536 }
14537
14538 int
14539 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14540 {
14541         int max_scale;
14542         int crtc_clock, cdclk;
14543
14544         if (!intel_crtc || !crtc_state->base.enable)
14545                 return DRM_PLANE_HELPER_NO_SCALING;
14546
14547         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14548         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14549
14550         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14551                 return DRM_PLANE_HELPER_NO_SCALING;
14552
14553         /*
14554          * skl max scale is lower of:
14555          *    close to 3 but not 3, -1 is for that purpose
14556          *            or
14557          *    cdclk/crtc_clock
14558          */
14559         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14560
14561         return max_scale;
14562 }
14563
14564 static int
14565 intel_check_primary_plane(struct drm_plane *plane,
14566                           struct intel_crtc_state *crtc_state,
14567                           struct intel_plane_state *state)
14568 {
14569         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14570         struct drm_crtc *crtc = state->base.crtc;
14571         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14572         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14573         bool can_position = false;
14574         int ret;
14575
14576         if (INTEL_GEN(dev_priv) >= 9) {
14577                 /* use scaler when colorkey is not required */
14578                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14579                         min_scale = 1;
14580                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14581                 }
14582                 can_position = true;
14583         }
14584
14585         ret = drm_plane_helper_check_state(&state->base,
14586                                            &state->clip,
14587                                            min_scale, max_scale,
14588                                            can_position, true);
14589         if (ret)
14590                 return ret;
14591
14592         if (!state->base.fb)
14593                 return 0;
14594
14595         if (INTEL_GEN(dev_priv) >= 9) {
14596                 ret = skl_check_plane_surface(state);
14597                 if (ret)
14598                         return ret;
14599         }
14600
14601         return 0;
14602 }
14603
14604 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14605                                     struct drm_crtc_state *old_crtc_state)
14606 {
14607         struct drm_device *dev = crtc->dev;
14608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14609         struct intel_crtc_state *old_intel_state =
14610                 to_intel_crtc_state(old_crtc_state);
14611         bool modeset = needs_modeset(crtc->state);
14612
14613         /* Perform vblank evasion around commit operation */
14614         intel_pipe_update_start(intel_crtc);
14615
14616         if (modeset)
14617                 return;
14618
14619         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14620                 intel_color_set_csc(crtc->state);
14621                 intel_color_load_luts(crtc->state);
14622         }
14623
14624         if (to_intel_crtc_state(crtc->state)->update_pipe)
14625                 intel_update_pipe_config(intel_crtc, old_intel_state);
14626         else if (INTEL_INFO(dev)->gen >= 9)
14627                 skl_detach_scalers(intel_crtc);
14628 }
14629
14630 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14631                                      struct drm_crtc_state *old_crtc_state)
14632 {
14633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14634
14635         intel_pipe_update_end(intel_crtc, NULL);
14636 }
14637
14638 /**
14639  * intel_plane_destroy - destroy a plane
14640  * @plane: plane to destroy
14641  *
14642  * Common destruction function for all types of planes (primary, cursor,
14643  * sprite).
14644  */
14645 void intel_plane_destroy(struct drm_plane *plane)
14646 {
14647         if (!plane)
14648                 return;
14649
14650         drm_plane_cleanup(plane);
14651         kfree(to_intel_plane(plane));
14652 }
14653
14654 const struct drm_plane_funcs intel_plane_funcs = {
14655         .update_plane = drm_atomic_helper_update_plane,
14656         .disable_plane = drm_atomic_helper_disable_plane,
14657         .destroy = intel_plane_destroy,
14658         .set_property = drm_atomic_helper_plane_set_property,
14659         .atomic_get_property = intel_plane_atomic_get_property,
14660         .atomic_set_property = intel_plane_atomic_set_property,
14661         .atomic_duplicate_state = intel_plane_duplicate_state,
14662         .atomic_destroy_state = intel_plane_destroy_state,
14663
14664 };
14665
14666 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14667                                                     int pipe)
14668 {
14669         struct intel_plane *primary = NULL;
14670         struct intel_plane_state *state = NULL;
14671         const uint32_t *intel_primary_formats;
14672         unsigned int num_formats;
14673         int ret;
14674
14675         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14676         if (!primary)
14677                 goto fail;
14678
14679         state = intel_create_plane_state(&primary->base);
14680         if (!state)
14681                 goto fail;
14682         primary->base.state = &state->base;
14683
14684         primary->can_scale = false;
14685         primary->max_downscale = 1;
14686         if (INTEL_INFO(dev)->gen >= 9) {
14687                 primary->can_scale = true;
14688                 state->scaler_id = -1;
14689         }
14690         primary->pipe = pipe;
14691         primary->plane = pipe;
14692         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14693         primary->check_plane = intel_check_primary_plane;
14694         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14695                 primary->plane = !pipe;
14696
14697         if (INTEL_INFO(dev)->gen >= 9) {
14698                 intel_primary_formats = skl_primary_formats;
14699                 num_formats = ARRAY_SIZE(skl_primary_formats);
14700
14701                 primary->update_plane = skylake_update_primary_plane;
14702                 primary->disable_plane = skylake_disable_primary_plane;
14703         } else if (HAS_PCH_SPLIT(dev)) {
14704                 intel_primary_formats = i965_primary_formats;
14705                 num_formats = ARRAY_SIZE(i965_primary_formats);
14706
14707                 primary->update_plane = ironlake_update_primary_plane;
14708                 primary->disable_plane = i9xx_disable_primary_plane;
14709         } else if (INTEL_INFO(dev)->gen >= 4) {
14710                 intel_primary_formats = i965_primary_formats;
14711                 num_formats = ARRAY_SIZE(i965_primary_formats);
14712
14713                 primary->update_plane = i9xx_update_primary_plane;
14714                 primary->disable_plane = i9xx_disable_primary_plane;
14715         } else {
14716                 intel_primary_formats = i8xx_primary_formats;
14717                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14718
14719                 primary->update_plane = i9xx_update_primary_plane;
14720                 primary->disable_plane = i9xx_disable_primary_plane;
14721         }
14722
14723         if (INTEL_INFO(dev)->gen >= 9)
14724                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14725                                                &intel_plane_funcs,
14726                                                intel_primary_formats, num_formats,
14727                                                DRM_PLANE_TYPE_PRIMARY,
14728                                                "plane 1%c", pipe_name(pipe));
14729         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14730                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14731                                                &intel_plane_funcs,
14732                                                intel_primary_formats, num_formats,
14733                                                DRM_PLANE_TYPE_PRIMARY,
14734                                                "primary %c", pipe_name(pipe));
14735         else
14736                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14737                                                &intel_plane_funcs,
14738                                                intel_primary_formats, num_formats,
14739                                                DRM_PLANE_TYPE_PRIMARY,
14740                                                "plane %c", plane_name(primary->plane));
14741         if (ret)
14742                 goto fail;
14743
14744         if (INTEL_INFO(dev)->gen >= 4)
14745                 intel_create_rotation_property(dev, primary);
14746
14747         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14748
14749         return &primary->base;
14750
14751 fail:
14752         kfree(state);
14753         kfree(primary);
14754
14755         return NULL;
14756 }
14757
14758 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14759 {
14760         if (!dev->mode_config.rotation_property) {
14761                 unsigned long flags = DRM_ROTATE_0 |
14762                         DRM_ROTATE_180;
14763
14764                 if (INTEL_INFO(dev)->gen >= 9)
14765                         flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
14766
14767                 dev->mode_config.rotation_property =
14768                         drm_mode_create_rotation_property(dev, flags);
14769         }
14770         if (dev->mode_config.rotation_property)
14771                 drm_object_attach_property(&plane->base.base,
14772                                 dev->mode_config.rotation_property,
14773                                 plane->base.state->rotation);
14774 }
14775
14776 static int
14777 intel_check_cursor_plane(struct drm_plane *plane,
14778                          struct intel_crtc_state *crtc_state,
14779                          struct intel_plane_state *state)
14780 {
14781         struct drm_framebuffer *fb = state->base.fb;
14782         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14783         enum pipe pipe = to_intel_plane(plane)->pipe;
14784         unsigned stride;
14785         int ret;
14786
14787         ret = drm_plane_helper_check_state(&state->base,
14788                                            &state->clip,
14789                                            DRM_PLANE_HELPER_NO_SCALING,
14790                                            DRM_PLANE_HELPER_NO_SCALING,
14791                                            true, true);
14792         if (ret)
14793                 return ret;
14794
14795         /* if we want to turn off the cursor ignore width and height */
14796         if (!obj)
14797                 return 0;
14798
14799         /* Check for which cursor types we support */
14800         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14801                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14802                           state->base.crtc_w, state->base.crtc_h);
14803                 return -EINVAL;
14804         }
14805
14806         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14807         if (obj->base.size < stride * state->base.crtc_h) {
14808                 DRM_DEBUG_KMS("buffer is too small\n");
14809                 return -ENOMEM;
14810         }
14811
14812         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14813                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14814                 return -EINVAL;
14815         }
14816
14817         /*
14818          * There's something wrong with the cursor on CHV pipe C.
14819          * If it straddles the left edge of the screen then
14820          * moving it away from the edge or disabling it often
14821          * results in a pipe underrun, and often that can lead to
14822          * dead pipe (constant underrun reported, and it scans
14823          * out just a solid color). To recover from that, the
14824          * display power well must be turned off and on again.
14825          * Refuse the put the cursor into that compromised position.
14826          */
14827         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14828             state->base.visible && state->base.crtc_x < 0) {
14829                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14830                 return -EINVAL;
14831         }
14832
14833         return 0;
14834 }
14835
14836 static void
14837 intel_disable_cursor_plane(struct drm_plane *plane,
14838                            struct drm_crtc *crtc)
14839 {
14840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14841
14842         intel_crtc->cursor_addr = 0;
14843         intel_crtc_update_cursor(crtc, NULL);
14844 }
14845
14846 static void
14847 intel_update_cursor_plane(struct drm_plane *plane,
14848                           const struct intel_crtc_state *crtc_state,
14849                           const struct intel_plane_state *state)
14850 {
14851         struct drm_crtc *crtc = crtc_state->base.crtc;
14852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14853         struct drm_device *dev = plane->dev;
14854         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14855         uint32_t addr;
14856
14857         if (!obj)
14858                 addr = 0;
14859         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14860                 addr = i915_gem_object_ggtt_offset(obj, NULL);
14861         else
14862                 addr = obj->phys_handle->busaddr;
14863
14864         intel_crtc->cursor_addr = addr;
14865         intel_crtc_update_cursor(crtc, state);
14866 }
14867
14868 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14869                                                    int pipe)
14870 {
14871         struct intel_plane *cursor = NULL;
14872         struct intel_plane_state *state = NULL;
14873         int ret;
14874
14875         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14876         if (!cursor)
14877                 goto fail;
14878
14879         state = intel_create_plane_state(&cursor->base);
14880         if (!state)
14881                 goto fail;
14882         cursor->base.state = &state->base;
14883
14884         cursor->can_scale = false;
14885         cursor->max_downscale = 1;
14886         cursor->pipe = pipe;
14887         cursor->plane = pipe;
14888         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14889         cursor->check_plane = intel_check_cursor_plane;
14890         cursor->update_plane = intel_update_cursor_plane;
14891         cursor->disable_plane = intel_disable_cursor_plane;
14892
14893         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14894                                        &intel_plane_funcs,
14895                                        intel_cursor_formats,
14896                                        ARRAY_SIZE(intel_cursor_formats),
14897                                        DRM_PLANE_TYPE_CURSOR,
14898                                        "cursor %c", pipe_name(pipe));
14899         if (ret)
14900                 goto fail;
14901
14902         if (INTEL_INFO(dev)->gen >= 4) {
14903                 if (!dev->mode_config.rotation_property)
14904                         dev->mode_config.rotation_property =
14905                                 drm_mode_create_rotation_property(dev,
14906                                                         DRM_ROTATE_0 |
14907                                                         DRM_ROTATE_180);
14908                 if (dev->mode_config.rotation_property)
14909                         drm_object_attach_property(&cursor->base.base,
14910                                 dev->mode_config.rotation_property,
14911                                 state->base.rotation);
14912         }
14913
14914         if (INTEL_INFO(dev)->gen >=9)
14915                 state->scaler_id = -1;
14916
14917         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14918
14919         return &cursor->base;
14920
14921 fail:
14922         kfree(state);
14923         kfree(cursor);
14924
14925         return NULL;
14926 }
14927
14928 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14929         struct intel_crtc_state *crtc_state)
14930 {
14931         int i;
14932         struct intel_scaler *intel_scaler;
14933         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14934
14935         for (i = 0; i < intel_crtc->num_scalers; i++) {
14936                 intel_scaler = &scaler_state->scalers[i];
14937                 intel_scaler->in_use = 0;
14938                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14939         }
14940
14941         scaler_state->scaler_id = -1;
14942 }
14943
14944 static void intel_crtc_init(struct drm_device *dev, int pipe)
14945 {
14946         struct drm_i915_private *dev_priv = to_i915(dev);
14947         struct intel_crtc *intel_crtc;
14948         struct intel_crtc_state *crtc_state = NULL;
14949         struct drm_plane *primary = NULL;
14950         struct drm_plane *cursor = NULL;
14951         int ret;
14952
14953         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14954         if (intel_crtc == NULL)
14955                 return;
14956
14957         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14958         if (!crtc_state)
14959                 goto fail;
14960         intel_crtc->config = crtc_state;
14961         intel_crtc->base.state = &crtc_state->base;
14962         crtc_state->base.crtc = &intel_crtc->base;
14963
14964         /* initialize shared scalers */
14965         if (INTEL_INFO(dev)->gen >= 9) {
14966                 if (pipe == PIPE_C)
14967                         intel_crtc->num_scalers = 1;
14968                 else
14969                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14970
14971                 skl_init_scalers(dev, intel_crtc, crtc_state);
14972         }
14973
14974         primary = intel_primary_plane_create(dev, pipe);
14975         if (!primary)
14976                 goto fail;
14977
14978         cursor = intel_cursor_plane_create(dev, pipe);
14979         if (!cursor)
14980                 goto fail;
14981
14982         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14983                                         cursor, &intel_crtc_funcs,
14984                                         "pipe %c", pipe_name(pipe));
14985         if (ret)
14986                 goto fail;
14987
14988         /*
14989          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14990          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14991          */
14992         intel_crtc->pipe = pipe;
14993         intel_crtc->plane = pipe;
14994         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14995                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14996                 intel_crtc->plane = !pipe;
14997         }
14998
14999         intel_crtc->cursor_base = ~0;
15000         intel_crtc->cursor_cntl = ~0;
15001         intel_crtc->cursor_size = ~0;
15002
15003         intel_crtc->wm.cxsr_allowed = true;
15004
15005         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15006                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15007         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15008         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15009
15010         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15011
15012         intel_color_init(&intel_crtc->base);
15013
15014         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15015         return;
15016
15017 fail:
15018         intel_plane_destroy(primary);
15019         intel_plane_destroy(cursor);
15020         kfree(crtc_state);
15021         kfree(intel_crtc);
15022 }
15023
15024 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15025 {
15026         struct drm_encoder *encoder = connector->base.encoder;
15027         struct drm_device *dev = connector->base.dev;
15028
15029         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15030
15031         if (!encoder || WARN_ON(!encoder->crtc))
15032                 return INVALID_PIPE;
15033
15034         return to_intel_crtc(encoder->crtc)->pipe;
15035 }
15036
15037 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15038                                 struct drm_file *file)
15039 {
15040         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15041         struct drm_crtc *drmmode_crtc;
15042         struct intel_crtc *crtc;
15043
15044         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15045         if (!drmmode_crtc)
15046                 return -ENOENT;
15047
15048         crtc = to_intel_crtc(drmmode_crtc);
15049         pipe_from_crtc_id->pipe = crtc->pipe;
15050
15051         return 0;
15052 }
15053
15054 static int intel_encoder_clones(struct intel_encoder *encoder)
15055 {
15056         struct drm_device *dev = encoder->base.dev;
15057         struct intel_encoder *source_encoder;
15058         int index_mask = 0;
15059         int entry = 0;
15060
15061         for_each_intel_encoder(dev, source_encoder) {
15062                 if (encoders_cloneable(encoder, source_encoder))
15063                         index_mask |= (1 << entry);
15064
15065                 entry++;
15066         }
15067
15068         return index_mask;
15069 }
15070
15071 static bool has_edp_a(struct drm_device *dev)
15072 {
15073         struct drm_i915_private *dev_priv = to_i915(dev);
15074
15075         if (!IS_MOBILE(dev))
15076                 return false;
15077
15078         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15079                 return false;
15080
15081         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15082                 return false;
15083
15084         return true;
15085 }
15086
15087 static bool intel_crt_present(struct drm_device *dev)
15088 {
15089         struct drm_i915_private *dev_priv = to_i915(dev);
15090
15091         if (INTEL_INFO(dev)->gen >= 9)
15092                 return false;
15093
15094         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15095                 return false;
15096
15097         if (IS_CHERRYVIEW(dev))
15098                 return false;
15099
15100         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15101                 return false;
15102
15103         /* DDI E can't be used if DDI A requires 4 lanes */
15104         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15105                 return false;
15106
15107         if (!dev_priv->vbt.int_crt_support)
15108                 return false;
15109
15110         return true;
15111 }
15112
15113 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15114 {
15115         int pps_num;
15116         int pps_idx;
15117
15118         if (HAS_DDI(dev_priv))
15119                 return;
15120         /*
15121          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15122          * everywhere where registers can be write protected.
15123          */
15124         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15125                 pps_num = 2;
15126         else
15127                 pps_num = 1;
15128
15129         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15130                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15131
15132                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15133                 I915_WRITE(PP_CONTROL(pps_idx), val);
15134         }
15135 }
15136
15137 static void intel_pps_init(struct drm_i915_private *dev_priv)
15138 {
15139         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15140                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15141         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15142                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15143         else
15144                 dev_priv->pps_mmio_base = PPS_BASE;
15145
15146         intel_pps_unlock_regs_wa(dev_priv);
15147 }
15148
15149 static void intel_setup_outputs(struct drm_device *dev)
15150 {
15151         struct drm_i915_private *dev_priv = to_i915(dev);
15152         struct intel_encoder *encoder;
15153         bool dpd_is_edp = false;
15154
15155         intel_pps_init(dev_priv);
15156
15157         /*
15158          * intel_edp_init_connector() depends on this completing first, to
15159          * prevent the registeration of both eDP and LVDS and the incorrect
15160          * sharing of the PPS.
15161          */
15162         intel_lvds_init(dev);
15163
15164         if (intel_crt_present(dev))
15165                 intel_crt_init(dev);
15166
15167         if (IS_BROXTON(dev)) {
15168                 /*
15169                  * FIXME: Broxton doesn't support port detection via the
15170                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15171                  * detect the ports.
15172                  */
15173                 intel_ddi_init(dev, PORT_A);
15174                 intel_ddi_init(dev, PORT_B);
15175                 intel_ddi_init(dev, PORT_C);
15176
15177                 intel_dsi_init(dev);
15178         } else if (HAS_DDI(dev)) {
15179                 int found;
15180
15181                 /*
15182                  * Haswell uses DDI functions to detect digital outputs.
15183                  * On SKL pre-D0 the strap isn't connected, so we assume
15184                  * it's there.
15185                  */
15186                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15187                 /* WaIgnoreDDIAStrap: skl */
15188                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15189                         intel_ddi_init(dev, PORT_A);
15190
15191                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15192                  * register */
15193                 found = I915_READ(SFUSE_STRAP);
15194
15195                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15196                         intel_ddi_init(dev, PORT_B);
15197                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15198                         intel_ddi_init(dev, PORT_C);
15199                 if (found & SFUSE_STRAP_DDID_DETECTED)
15200                         intel_ddi_init(dev, PORT_D);
15201                 /*
15202                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15203                  */
15204                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15205                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15206                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15207                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15208                         intel_ddi_init(dev, PORT_E);
15209
15210         } else if (HAS_PCH_SPLIT(dev)) {
15211                 int found;
15212                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15213
15214                 if (has_edp_a(dev))
15215                         intel_dp_init(dev, DP_A, PORT_A);
15216
15217                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15218                         /* PCH SDVOB multiplex with HDMIB */
15219                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15220                         if (!found)
15221                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15222                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15223                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15224                 }
15225
15226                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15227                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15228
15229                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15230                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15231
15232                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15233                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15234
15235                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15236                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15237         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15238                 bool has_edp, has_port;
15239
15240                 /*
15241                  * The DP_DETECTED bit is the latched state of the DDC
15242                  * SDA pin at boot. However since eDP doesn't require DDC
15243                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15244                  * eDP ports may have been muxed to an alternate function.
15245                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15246                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15247                  * detect eDP ports.
15248                  *
15249                  * Sadly the straps seem to be missing sometimes even for HDMI
15250                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15251                  * and VBT for the presence of the port. Additionally we can't
15252                  * trust the port type the VBT declares as we've seen at least
15253                  * HDMI ports that the VBT claim are DP or eDP.
15254                  */
15255                 has_edp = intel_dp_is_edp(dev, PORT_B);
15256                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15257                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15258                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15259                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15260                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15261
15262                 has_edp = intel_dp_is_edp(dev, PORT_C);
15263                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15264                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15265                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15266                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15267                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15268
15269                 if (IS_CHERRYVIEW(dev)) {
15270                         /*
15271                          * eDP not supported on port D,
15272                          * so no need to worry about it
15273                          */
15274                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15275                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15276                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15277                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15278                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15279                 }
15280
15281                 intel_dsi_init(dev);
15282         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15283                 bool found = false;
15284
15285                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15286                         DRM_DEBUG_KMS("probing SDVOB\n");
15287                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15288                         if (!found && IS_G4X(dev)) {
15289                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15290                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15291                         }
15292
15293                         if (!found && IS_G4X(dev))
15294                                 intel_dp_init(dev, DP_B, PORT_B);
15295                 }
15296
15297                 /* Before G4X SDVOC doesn't have its own detect register */
15298
15299                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15300                         DRM_DEBUG_KMS("probing SDVOC\n");
15301                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15302                 }
15303
15304                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15305
15306                         if (IS_G4X(dev)) {
15307                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15308                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15309                         }
15310                         if (IS_G4X(dev))
15311                                 intel_dp_init(dev, DP_C, PORT_C);
15312                 }
15313
15314                 if (IS_G4X(dev) &&
15315                     (I915_READ(DP_D) & DP_DETECTED))
15316                         intel_dp_init(dev, DP_D, PORT_D);
15317         } else if (IS_GEN2(dev))
15318                 intel_dvo_init(dev);
15319
15320         if (SUPPORTS_TV(dev))
15321                 intel_tv_init(dev);
15322
15323         intel_psr_init(dev);
15324
15325         for_each_intel_encoder(dev, encoder) {
15326                 encoder->base.possible_crtcs = encoder->crtc_mask;
15327                 encoder->base.possible_clones =
15328                         intel_encoder_clones(encoder);
15329         }
15330
15331         intel_init_pch_refclk(dev);
15332
15333         drm_helper_move_panel_connectors_to_head(dev);
15334 }
15335
15336 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15337 {
15338         struct drm_device *dev = fb->dev;
15339         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15340
15341         drm_framebuffer_cleanup(fb);
15342         mutex_lock(&dev->struct_mutex);
15343         WARN_ON(!intel_fb->obj->framebuffer_references--);
15344         i915_gem_object_put(intel_fb->obj);
15345         mutex_unlock(&dev->struct_mutex);
15346         kfree(intel_fb);
15347 }
15348
15349 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15350                                                 struct drm_file *file,
15351                                                 unsigned int *handle)
15352 {
15353         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15354         struct drm_i915_gem_object *obj = intel_fb->obj;
15355
15356         if (obj->userptr.mm) {
15357                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15358                 return -EINVAL;
15359         }
15360
15361         return drm_gem_handle_create(file, &obj->base, handle);
15362 }
15363
15364 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15365                                         struct drm_file *file,
15366                                         unsigned flags, unsigned color,
15367                                         struct drm_clip_rect *clips,
15368                                         unsigned num_clips)
15369 {
15370         struct drm_device *dev = fb->dev;
15371         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15372         struct drm_i915_gem_object *obj = intel_fb->obj;
15373
15374         mutex_lock(&dev->struct_mutex);
15375         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15376         mutex_unlock(&dev->struct_mutex);
15377
15378         return 0;
15379 }
15380
15381 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15382         .destroy = intel_user_framebuffer_destroy,
15383         .create_handle = intel_user_framebuffer_create_handle,
15384         .dirty = intel_user_framebuffer_dirty,
15385 };
15386
15387 static
15388 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15389                          uint32_t pixel_format)
15390 {
15391         u32 gen = INTEL_INFO(dev)->gen;
15392
15393         if (gen >= 9) {
15394                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15395
15396                 /* "The stride in bytes must not exceed the of the size of 8K
15397                  *  pixels and 32K bytes."
15398                  */
15399                 return min(8192 * cpp, 32768);
15400         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15401                 return 32*1024;
15402         } else if (gen >= 4) {
15403                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15404                         return 16*1024;
15405                 else
15406                         return 32*1024;
15407         } else if (gen >= 3) {
15408                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15409                         return 8*1024;
15410                 else
15411                         return 16*1024;
15412         } else {
15413                 /* XXX DSPC is limited to 4k tiled */
15414                 return 8*1024;
15415         }
15416 }
15417
15418 static int intel_framebuffer_init(struct drm_device *dev,
15419                                   struct intel_framebuffer *intel_fb,
15420                                   struct drm_mode_fb_cmd2 *mode_cmd,
15421                                   struct drm_i915_gem_object *obj)
15422 {
15423         struct drm_i915_private *dev_priv = to_i915(dev);
15424         unsigned int tiling = i915_gem_object_get_tiling(obj);
15425         int ret;
15426         u32 pitch_limit, stride_alignment;
15427
15428         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15429
15430         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15431                 /*
15432                  * If there's a fence, enforce that
15433                  * the fb modifier and tiling mode match.
15434                  */
15435                 if (tiling != I915_TILING_NONE &&
15436                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15437                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15438                         return -EINVAL;
15439                 }
15440         } else {
15441                 if (tiling == I915_TILING_X) {
15442                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15443                 } else if (tiling == I915_TILING_Y) {
15444                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15445                         return -EINVAL;
15446                 }
15447         }
15448
15449         /* Passed in modifier sanity checking. */
15450         switch (mode_cmd->modifier[0]) {
15451         case I915_FORMAT_MOD_Y_TILED:
15452         case I915_FORMAT_MOD_Yf_TILED:
15453                 if (INTEL_INFO(dev)->gen < 9) {
15454                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15455                                   mode_cmd->modifier[0]);
15456                         return -EINVAL;
15457                 }
15458         case DRM_FORMAT_MOD_NONE:
15459         case I915_FORMAT_MOD_X_TILED:
15460                 break;
15461         default:
15462                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15463                           mode_cmd->modifier[0]);
15464                 return -EINVAL;
15465         }
15466
15467         /*
15468          * gen2/3 display engine uses the fence if present,
15469          * so the tiling mode must match the fb modifier exactly.
15470          */
15471         if (INTEL_INFO(dev_priv)->gen < 4 &&
15472             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15473                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15474                 return -EINVAL;
15475         }
15476
15477         stride_alignment = intel_fb_stride_alignment(dev_priv,
15478                                                      mode_cmd->modifier[0],
15479                                                      mode_cmd->pixel_format);
15480         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15481                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15482                           mode_cmd->pitches[0], stride_alignment);
15483                 return -EINVAL;
15484         }
15485
15486         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15487                                            mode_cmd->pixel_format);
15488         if (mode_cmd->pitches[0] > pitch_limit) {
15489                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15490                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15491                           "tiled" : "linear",
15492                           mode_cmd->pitches[0], pitch_limit);
15493                 return -EINVAL;
15494         }
15495
15496         /*
15497          * If there's a fence, enforce that
15498          * the fb pitch and fence stride match.
15499          */
15500         if (tiling != I915_TILING_NONE &&
15501             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15502                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15503                           mode_cmd->pitches[0],
15504                           i915_gem_object_get_stride(obj));
15505                 return -EINVAL;
15506         }
15507
15508         /* Reject formats not supported by any plane early. */
15509         switch (mode_cmd->pixel_format) {
15510         case DRM_FORMAT_C8:
15511         case DRM_FORMAT_RGB565:
15512         case DRM_FORMAT_XRGB8888:
15513         case DRM_FORMAT_ARGB8888:
15514                 break;
15515         case DRM_FORMAT_XRGB1555:
15516                 if (INTEL_INFO(dev)->gen > 3) {
15517                         DRM_DEBUG("unsupported pixel format: %s\n",
15518                                   drm_get_format_name(mode_cmd->pixel_format));
15519                         return -EINVAL;
15520                 }
15521                 break;
15522         case DRM_FORMAT_ABGR8888:
15523                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15524                     INTEL_INFO(dev)->gen < 9) {
15525                         DRM_DEBUG("unsupported pixel format: %s\n",
15526                                   drm_get_format_name(mode_cmd->pixel_format));
15527                         return -EINVAL;
15528                 }
15529                 break;
15530         case DRM_FORMAT_XBGR8888:
15531         case DRM_FORMAT_XRGB2101010:
15532         case DRM_FORMAT_XBGR2101010:
15533                 if (INTEL_INFO(dev)->gen < 4) {
15534                         DRM_DEBUG("unsupported pixel format: %s\n",
15535                                   drm_get_format_name(mode_cmd->pixel_format));
15536                         return -EINVAL;
15537                 }
15538                 break;
15539         case DRM_FORMAT_ABGR2101010:
15540                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15541                         DRM_DEBUG("unsupported pixel format: %s\n",
15542                                   drm_get_format_name(mode_cmd->pixel_format));
15543                         return -EINVAL;
15544                 }
15545                 break;
15546         case DRM_FORMAT_YUYV:
15547         case DRM_FORMAT_UYVY:
15548         case DRM_FORMAT_YVYU:
15549         case DRM_FORMAT_VYUY:
15550                 if (INTEL_INFO(dev)->gen < 5) {
15551                         DRM_DEBUG("unsupported pixel format: %s\n",
15552                                   drm_get_format_name(mode_cmd->pixel_format));
15553                         return -EINVAL;
15554                 }
15555                 break;
15556         default:
15557                 DRM_DEBUG("unsupported pixel format: %s\n",
15558                           drm_get_format_name(mode_cmd->pixel_format));
15559                 return -EINVAL;
15560         }
15561
15562         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15563         if (mode_cmd->offsets[0] != 0)
15564                 return -EINVAL;
15565
15566         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15567         intel_fb->obj = obj;
15568
15569         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15570         if (ret)
15571                 return ret;
15572
15573         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15574         if (ret) {
15575                 DRM_ERROR("framebuffer init failed %d\n", ret);
15576                 return ret;
15577         }
15578
15579         intel_fb->obj->framebuffer_references++;
15580
15581         return 0;
15582 }
15583
15584 static struct drm_framebuffer *
15585 intel_user_framebuffer_create(struct drm_device *dev,
15586                               struct drm_file *filp,
15587                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15588 {
15589         struct drm_framebuffer *fb;
15590         struct drm_i915_gem_object *obj;
15591         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15592
15593         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15594         if (!obj)
15595                 return ERR_PTR(-ENOENT);
15596
15597         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15598         if (IS_ERR(fb))
15599                 i915_gem_object_put_unlocked(obj);
15600
15601         return fb;
15602 }
15603
15604 #ifndef CONFIG_DRM_FBDEV_EMULATION
15605 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15606 {
15607 }
15608 #endif
15609
15610 static const struct drm_mode_config_funcs intel_mode_funcs = {
15611         .fb_create = intel_user_framebuffer_create,
15612         .output_poll_changed = intel_fbdev_output_poll_changed,
15613         .atomic_check = intel_atomic_check,
15614         .atomic_commit = intel_atomic_commit,
15615         .atomic_state_alloc = intel_atomic_state_alloc,
15616         .atomic_state_clear = intel_atomic_state_clear,
15617 };
15618
15619 /**
15620  * intel_init_display_hooks - initialize the display modesetting hooks
15621  * @dev_priv: device private
15622  */
15623 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15624 {
15625         if (INTEL_INFO(dev_priv)->gen >= 9) {
15626                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15627                 dev_priv->display.get_initial_plane_config =
15628                         skylake_get_initial_plane_config;
15629                 dev_priv->display.crtc_compute_clock =
15630                         haswell_crtc_compute_clock;
15631                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15632                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15633         } else if (HAS_DDI(dev_priv)) {
15634                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15635                 dev_priv->display.get_initial_plane_config =
15636                         ironlake_get_initial_plane_config;
15637                 dev_priv->display.crtc_compute_clock =
15638                         haswell_crtc_compute_clock;
15639                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15640                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15641         } else if (HAS_PCH_SPLIT(dev_priv)) {
15642                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15643                 dev_priv->display.get_initial_plane_config =
15644                         ironlake_get_initial_plane_config;
15645                 dev_priv->display.crtc_compute_clock =
15646                         ironlake_crtc_compute_clock;
15647                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15648                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15649         } else if (IS_CHERRYVIEW(dev_priv)) {
15650                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15651                 dev_priv->display.get_initial_plane_config =
15652                         i9xx_get_initial_plane_config;
15653                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15654                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15655                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15656         } else if (IS_VALLEYVIEW(dev_priv)) {
15657                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15658                 dev_priv->display.get_initial_plane_config =
15659                         i9xx_get_initial_plane_config;
15660                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15661                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15662                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15663         } else if (IS_G4X(dev_priv)) {
15664                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15665                 dev_priv->display.get_initial_plane_config =
15666                         i9xx_get_initial_plane_config;
15667                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15668                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15669                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15670         } else if (IS_PINEVIEW(dev_priv)) {
15671                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15672                 dev_priv->display.get_initial_plane_config =
15673                         i9xx_get_initial_plane_config;
15674                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15675                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15676                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15677         } else if (!IS_GEN2(dev_priv)) {
15678                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15679                 dev_priv->display.get_initial_plane_config =
15680                         i9xx_get_initial_plane_config;
15681                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15682                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15683                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15684         } else {
15685                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15686                 dev_priv->display.get_initial_plane_config =
15687                         i9xx_get_initial_plane_config;
15688                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15689                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15690                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15691         }
15692
15693         /* Returns the core display clock speed */
15694         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15695                 dev_priv->display.get_display_clock_speed =
15696                         skylake_get_display_clock_speed;
15697         else if (IS_BROXTON(dev_priv))
15698                 dev_priv->display.get_display_clock_speed =
15699                         broxton_get_display_clock_speed;
15700         else if (IS_BROADWELL(dev_priv))
15701                 dev_priv->display.get_display_clock_speed =
15702                         broadwell_get_display_clock_speed;
15703         else if (IS_HASWELL(dev_priv))
15704                 dev_priv->display.get_display_clock_speed =
15705                         haswell_get_display_clock_speed;
15706         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15707                 dev_priv->display.get_display_clock_speed =
15708                         valleyview_get_display_clock_speed;
15709         else if (IS_GEN5(dev_priv))
15710                 dev_priv->display.get_display_clock_speed =
15711                         ilk_get_display_clock_speed;
15712         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15713                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15714                 dev_priv->display.get_display_clock_speed =
15715                         i945_get_display_clock_speed;
15716         else if (IS_GM45(dev_priv))
15717                 dev_priv->display.get_display_clock_speed =
15718                         gm45_get_display_clock_speed;
15719         else if (IS_CRESTLINE(dev_priv))
15720                 dev_priv->display.get_display_clock_speed =
15721                         i965gm_get_display_clock_speed;
15722         else if (IS_PINEVIEW(dev_priv))
15723                 dev_priv->display.get_display_clock_speed =
15724                         pnv_get_display_clock_speed;
15725         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15726                 dev_priv->display.get_display_clock_speed =
15727                         g33_get_display_clock_speed;
15728         else if (IS_I915G(dev_priv))
15729                 dev_priv->display.get_display_clock_speed =
15730                         i915_get_display_clock_speed;
15731         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15732                 dev_priv->display.get_display_clock_speed =
15733                         i9xx_misc_get_display_clock_speed;
15734         else if (IS_I915GM(dev_priv))
15735                 dev_priv->display.get_display_clock_speed =
15736                         i915gm_get_display_clock_speed;
15737         else if (IS_I865G(dev_priv))
15738                 dev_priv->display.get_display_clock_speed =
15739                         i865_get_display_clock_speed;
15740         else if (IS_I85X(dev_priv))
15741                 dev_priv->display.get_display_clock_speed =
15742                         i85x_get_display_clock_speed;
15743         else { /* 830 */
15744                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15745                 dev_priv->display.get_display_clock_speed =
15746                         i830_get_display_clock_speed;
15747         }
15748
15749         if (IS_GEN5(dev_priv)) {
15750                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15751         } else if (IS_GEN6(dev_priv)) {
15752                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15753         } else if (IS_IVYBRIDGE(dev_priv)) {
15754                 /* FIXME: detect B0+ stepping and use auto training */
15755                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15756         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15757                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15758         }
15759
15760         if (IS_BROADWELL(dev_priv)) {
15761                 dev_priv->display.modeset_commit_cdclk =
15762                         broadwell_modeset_commit_cdclk;
15763                 dev_priv->display.modeset_calc_cdclk =
15764                         broadwell_modeset_calc_cdclk;
15765         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15766                 dev_priv->display.modeset_commit_cdclk =
15767                         valleyview_modeset_commit_cdclk;
15768                 dev_priv->display.modeset_calc_cdclk =
15769                         valleyview_modeset_calc_cdclk;
15770         } else if (IS_BROXTON(dev_priv)) {
15771                 dev_priv->display.modeset_commit_cdclk =
15772                         bxt_modeset_commit_cdclk;
15773                 dev_priv->display.modeset_calc_cdclk =
15774                         bxt_modeset_calc_cdclk;
15775         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15776                 dev_priv->display.modeset_commit_cdclk =
15777                         skl_modeset_commit_cdclk;
15778                 dev_priv->display.modeset_calc_cdclk =
15779                         skl_modeset_calc_cdclk;
15780         }
15781
15782         switch (INTEL_INFO(dev_priv)->gen) {
15783         case 2:
15784                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15785                 break;
15786
15787         case 3:
15788                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15789                 break;
15790
15791         case 4:
15792         case 5:
15793                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15794                 break;
15795
15796         case 6:
15797                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15798                 break;
15799         case 7:
15800         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15801                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15802                 break;
15803         case 9:
15804                 /* Drop through - unsupported since execlist only. */
15805         default:
15806                 /* Default just returns -ENODEV to indicate unsupported */
15807                 dev_priv->display.queue_flip = intel_default_queue_flip;
15808         }
15809 }
15810
15811 /*
15812  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15813  * resume, or other times.  This quirk makes sure that's the case for
15814  * affected systems.
15815  */
15816 static void quirk_pipea_force(struct drm_device *dev)
15817 {
15818         struct drm_i915_private *dev_priv = to_i915(dev);
15819
15820         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15821         DRM_INFO("applying pipe a force quirk\n");
15822 }
15823
15824 static void quirk_pipeb_force(struct drm_device *dev)
15825 {
15826         struct drm_i915_private *dev_priv = to_i915(dev);
15827
15828         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15829         DRM_INFO("applying pipe b force quirk\n");
15830 }
15831
15832 /*
15833  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15834  */
15835 static void quirk_ssc_force_disable(struct drm_device *dev)
15836 {
15837         struct drm_i915_private *dev_priv = to_i915(dev);
15838         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15839         DRM_INFO("applying lvds SSC disable quirk\n");
15840 }
15841
15842 /*
15843  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15844  * brightness value
15845  */
15846 static void quirk_invert_brightness(struct drm_device *dev)
15847 {
15848         struct drm_i915_private *dev_priv = to_i915(dev);
15849         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15850         DRM_INFO("applying inverted panel brightness quirk\n");
15851 }
15852
15853 /* Some VBT's incorrectly indicate no backlight is present */
15854 static void quirk_backlight_present(struct drm_device *dev)
15855 {
15856         struct drm_i915_private *dev_priv = to_i915(dev);
15857         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15858         DRM_INFO("applying backlight present quirk\n");
15859 }
15860
15861 struct intel_quirk {
15862         int device;
15863         int subsystem_vendor;
15864         int subsystem_device;
15865         void (*hook)(struct drm_device *dev);
15866 };
15867
15868 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15869 struct intel_dmi_quirk {
15870         void (*hook)(struct drm_device *dev);
15871         const struct dmi_system_id (*dmi_id_list)[];
15872 };
15873
15874 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15875 {
15876         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15877         return 1;
15878 }
15879
15880 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15881         {
15882                 .dmi_id_list = &(const struct dmi_system_id[]) {
15883                         {
15884                                 .callback = intel_dmi_reverse_brightness,
15885                                 .ident = "NCR Corporation",
15886                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15887                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15888                                 },
15889                         },
15890                         { }  /* terminating entry */
15891                 },
15892                 .hook = quirk_invert_brightness,
15893         },
15894 };
15895
15896 static struct intel_quirk intel_quirks[] = {
15897         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15898         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15899
15900         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15901         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15902
15903         /* 830 needs to leave pipe A & dpll A up */
15904         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15905
15906         /* 830 needs to leave pipe B & dpll B up */
15907         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15908
15909         /* Lenovo U160 cannot use SSC on LVDS */
15910         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15911
15912         /* Sony Vaio Y cannot use SSC on LVDS */
15913         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15914
15915         /* Acer Aspire 5734Z must invert backlight brightness */
15916         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15917
15918         /* Acer/eMachines G725 */
15919         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15920
15921         /* Acer/eMachines e725 */
15922         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15923
15924         /* Acer/Packard Bell NCL20 */
15925         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15926
15927         /* Acer Aspire 4736Z */
15928         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15929
15930         /* Acer Aspire 5336 */
15931         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15932
15933         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15934         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15935
15936         /* Acer C720 Chromebook (Core i3 4005U) */
15937         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15938
15939         /* Apple Macbook 2,1 (Core 2 T7400) */
15940         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15941
15942         /* Apple Macbook 4,1 */
15943         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15944
15945         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15946         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15947
15948         /* HP Chromebook 14 (Celeron 2955U) */
15949         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15950
15951         /* Dell Chromebook 11 */
15952         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15953
15954         /* Dell Chromebook 11 (2015 version) */
15955         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15956 };
15957
15958 static void intel_init_quirks(struct drm_device *dev)
15959 {
15960         struct pci_dev *d = dev->pdev;
15961         int i;
15962
15963         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15964                 struct intel_quirk *q = &intel_quirks[i];
15965
15966                 if (d->device == q->device &&
15967                     (d->subsystem_vendor == q->subsystem_vendor ||
15968                      q->subsystem_vendor == PCI_ANY_ID) &&
15969                     (d->subsystem_device == q->subsystem_device ||
15970                      q->subsystem_device == PCI_ANY_ID))
15971                         q->hook(dev);
15972         }
15973         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15974                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15975                         intel_dmi_quirks[i].hook(dev);
15976         }
15977 }
15978
15979 /* Disable the VGA plane that we never use */
15980 static void i915_disable_vga(struct drm_device *dev)
15981 {
15982         struct drm_i915_private *dev_priv = to_i915(dev);
15983         u8 sr1;
15984         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15985
15986         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15987         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15988         outb(SR01, VGA_SR_INDEX);
15989         sr1 = inb(VGA_SR_DATA);
15990         outb(sr1 | 1<<5, VGA_SR_DATA);
15991         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15992         udelay(300);
15993
15994         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15995         POSTING_READ(vga_reg);
15996 }
15997
15998 void intel_modeset_init_hw(struct drm_device *dev)
15999 {
16000         struct drm_i915_private *dev_priv = to_i915(dev);
16001
16002         intel_update_cdclk(dev);
16003
16004         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16005
16006         intel_init_clock_gating(dev);
16007 }
16008
16009 /*
16010  * Calculate what we think the watermarks should be for the state we've read
16011  * out of the hardware and then immediately program those watermarks so that
16012  * we ensure the hardware settings match our internal state.
16013  *
16014  * We can calculate what we think WM's should be by creating a duplicate of the
16015  * current state (which was constructed during hardware readout) and running it
16016  * through the atomic check code to calculate new watermark values in the
16017  * state object.
16018  */
16019 static void sanitize_watermarks(struct drm_device *dev)
16020 {
16021         struct drm_i915_private *dev_priv = to_i915(dev);
16022         struct drm_atomic_state *state;
16023         struct drm_crtc *crtc;
16024         struct drm_crtc_state *cstate;
16025         struct drm_modeset_acquire_ctx ctx;
16026         int ret;
16027         int i;
16028
16029         /* Only supported on platforms that use atomic watermark design */
16030         if (!dev_priv->display.optimize_watermarks)
16031                 return;
16032
16033         /*
16034          * We need to hold connection_mutex before calling duplicate_state so
16035          * that the connector loop is protected.
16036          */
16037         drm_modeset_acquire_init(&ctx, 0);
16038 retry:
16039         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16040         if (ret == -EDEADLK) {
16041                 drm_modeset_backoff(&ctx);
16042                 goto retry;
16043         } else if (WARN_ON(ret)) {
16044                 goto fail;
16045         }
16046
16047         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16048         if (WARN_ON(IS_ERR(state)))
16049                 goto fail;
16050
16051         /*
16052          * Hardware readout is the only time we don't want to calculate
16053          * intermediate watermarks (since we don't trust the current
16054          * watermarks).
16055          */
16056         to_intel_atomic_state(state)->skip_intermediate_wm = true;
16057
16058         ret = intel_atomic_check(dev, state);
16059         if (ret) {
16060                 /*
16061                  * If we fail here, it means that the hardware appears to be
16062                  * programmed in a way that shouldn't be possible, given our
16063                  * understanding of watermark requirements.  This might mean a
16064                  * mistake in the hardware readout code or a mistake in the
16065                  * watermark calculations for a given platform.  Raise a WARN
16066                  * so that this is noticeable.
16067                  *
16068                  * If this actually happens, we'll have to just leave the
16069                  * BIOS-programmed watermarks untouched and hope for the best.
16070                  */
16071                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16072                 goto fail;
16073         }
16074
16075         /* Write calculated watermark values back */
16076         for_each_crtc_in_state(state, crtc, cstate, i) {
16077                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16078
16079                 cs->wm.need_postvbl_update = true;
16080                 dev_priv->display.optimize_watermarks(cs);
16081         }
16082
16083         drm_atomic_state_free(state);
16084 fail:
16085         drm_modeset_drop_locks(&ctx);
16086         drm_modeset_acquire_fini(&ctx);
16087 }
16088
16089 void intel_modeset_init(struct drm_device *dev)
16090 {
16091         struct drm_i915_private *dev_priv = to_i915(dev);
16092         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16093         int sprite, ret;
16094         enum pipe pipe;
16095         struct intel_crtc *crtc;
16096
16097         drm_mode_config_init(dev);
16098
16099         dev->mode_config.min_width = 0;
16100         dev->mode_config.min_height = 0;
16101
16102         dev->mode_config.preferred_depth = 24;
16103         dev->mode_config.prefer_shadow = 1;
16104
16105         dev->mode_config.allow_fb_modifiers = true;
16106
16107         dev->mode_config.funcs = &intel_mode_funcs;
16108
16109         intel_init_quirks(dev);
16110
16111         intel_init_pm(dev);
16112
16113         if (INTEL_INFO(dev)->num_pipes == 0)
16114                 return;
16115
16116         /*
16117          * There may be no VBT; and if the BIOS enabled SSC we can
16118          * just keep using it to avoid unnecessary flicker.  Whereas if the
16119          * BIOS isn't using it, don't assume it will work even if the VBT
16120          * indicates as much.
16121          */
16122         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16123                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16124                                             DREF_SSC1_ENABLE);
16125
16126                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16127                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16128                                      bios_lvds_use_ssc ? "en" : "dis",
16129                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16130                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16131                 }
16132         }
16133
16134         if (IS_GEN2(dev)) {
16135                 dev->mode_config.max_width = 2048;
16136                 dev->mode_config.max_height = 2048;
16137         } else if (IS_GEN3(dev)) {
16138                 dev->mode_config.max_width = 4096;
16139                 dev->mode_config.max_height = 4096;
16140         } else {
16141                 dev->mode_config.max_width = 8192;
16142                 dev->mode_config.max_height = 8192;
16143         }
16144
16145         if (IS_845G(dev) || IS_I865G(dev)) {
16146                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16147                 dev->mode_config.cursor_height = 1023;
16148         } else if (IS_GEN2(dev)) {
16149                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16150                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16151         } else {
16152                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16153                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16154         }
16155
16156         dev->mode_config.fb_base = ggtt->mappable_base;
16157
16158         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16159                       INTEL_INFO(dev)->num_pipes,
16160                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16161
16162         for_each_pipe(dev_priv, pipe) {
16163                 intel_crtc_init(dev, pipe);
16164                 for_each_sprite(dev_priv, pipe, sprite) {
16165                         ret = intel_plane_init(dev, pipe, sprite);
16166                         if (ret)
16167                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16168                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
16169                 }
16170         }
16171
16172         intel_update_czclk(dev_priv);
16173         intel_update_cdclk(dev);
16174
16175         intel_shared_dpll_init(dev);
16176
16177         if (dev_priv->max_cdclk_freq == 0)
16178                 intel_update_max_cdclk(dev);
16179
16180         /* Just disable it once at startup */
16181         i915_disable_vga(dev);
16182         intel_setup_outputs(dev);
16183
16184         drm_modeset_lock_all(dev);
16185         intel_modeset_setup_hw_state(dev);
16186         drm_modeset_unlock_all(dev);
16187
16188         for_each_intel_crtc(dev, crtc) {
16189                 struct intel_initial_plane_config plane_config = {};
16190
16191                 if (!crtc->active)
16192                         continue;
16193
16194                 /*
16195                  * Note that reserving the BIOS fb up front prevents us
16196                  * from stuffing other stolen allocations like the ring
16197                  * on top.  This prevents some ugliness at boot time, and
16198                  * can even allow for smooth boot transitions if the BIOS
16199                  * fb is large enough for the active pipe configuration.
16200                  */
16201                 dev_priv->display.get_initial_plane_config(crtc,
16202                                                            &plane_config);
16203
16204                 /*
16205                  * If the fb is shared between multiple heads, we'll
16206                  * just get the first one.
16207                  */
16208                 intel_find_initial_plane_obj(crtc, &plane_config);
16209         }
16210
16211         /*
16212          * Make sure hardware watermarks really match the state we read out.
16213          * Note that we need to do this after reconstructing the BIOS fb's
16214          * since the watermark calculation done here will use pstate->fb.
16215          */
16216         sanitize_watermarks(dev);
16217 }
16218
16219 static void intel_enable_pipe_a(struct drm_device *dev)
16220 {
16221         struct intel_connector *connector;
16222         struct drm_connector *crt = NULL;
16223         struct intel_load_detect_pipe load_detect_temp;
16224         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16225
16226         /* We can't just switch on the pipe A, we need to set things up with a
16227          * proper mode and output configuration. As a gross hack, enable pipe A
16228          * by enabling the load detect pipe once. */
16229         for_each_intel_connector(dev, connector) {
16230                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16231                         crt = &connector->base;
16232                         break;
16233                 }
16234         }
16235
16236         if (!crt)
16237                 return;
16238
16239         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16240                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16241 }
16242
16243 static bool
16244 intel_check_plane_mapping(struct intel_crtc *crtc)
16245 {
16246         struct drm_device *dev = crtc->base.dev;
16247         struct drm_i915_private *dev_priv = to_i915(dev);
16248         u32 val;
16249
16250         if (INTEL_INFO(dev)->num_pipes == 1)
16251                 return true;
16252
16253         val = I915_READ(DSPCNTR(!crtc->plane));
16254
16255         if ((val & DISPLAY_PLANE_ENABLE) &&
16256             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16257                 return false;
16258
16259         return true;
16260 }
16261
16262 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16263 {
16264         struct drm_device *dev = crtc->base.dev;
16265         struct intel_encoder *encoder;
16266
16267         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16268                 return true;
16269
16270         return false;
16271 }
16272
16273 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
16274 {
16275         struct drm_device *dev = encoder->base.dev;
16276         struct intel_connector *connector;
16277
16278         for_each_connector_on_encoder(dev, &encoder->base, connector)
16279                 return true;
16280
16281         return false;
16282 }
16283
16284 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16285                               enum transcoder pch_transcoder)
16286 {
16287         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16288                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16289 }
16290
16291 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16292 {
16293         struct drm_device *dev = crtc->base.dev;
16294         struct drm_i915_private *dev_priv = to_i915(dev);
16295         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16296
16297         /* Clear any frame start delays used for debugging left by the BIOS */
16298         if (!transcoder_is_dsi(cpu_transcoder)) {
16299                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16300
16301                 I915_WRITE(reg,
16302                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16303         }
16304
16305         /* restore vblank interrupts to correct state */
16306         drm_crtc_vblank_reset(&crtc->base);
16307         if (crtc->active) {
16308                 struct intel_plane *plane;
16309
16310                 drm_crtc_vblank_on(&crtc->base);
16311
16312                 /* Disable everything but the primary plane */
16313                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16314                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16315                                 continue;
16316
16317                         plane->disable_plane(&plane->base, &crtc->base);
16318                 }
16319         }
16320
16321         /* We need to sanitize the plane -> pipe mapping first because this will
16322          * disable the crtc (and hence change the state) if it is wrong. Note
16323          * that gen4+ has a fixed plane -> pipe mapping.  */
16324         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16325                 bool plane;
16326
16327                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16328                               crtc->base.base.id, crtc->base.name);
16329
16330                 /* Pipe has the wrong plane attached and the plane is active.
16331                  * Temporarily change the plane mapping and disable everything
16332                  * ...  */
16333                 plane = crtc->plane;
16334                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16335                 crtc->plane = !plane;
16336                 intel_crtc_disable_noatomic(&crtc->base);
16337                 crtc->plane = plane;
16338         }
16339
16340         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16341             crtc->pipe == PIPE_A && !crtc->active) {
16342                 /* BIOS forgot to enable pipe A, this mostly happens after
16343                  * resume. Force-enable the pipe to fix this, the update_dpms
16344                  * call below we restore the pipe to the right state, but leave
16345                  * the required bits on. */
16346                 intel_enable_pipe_a(dev);
16347         }
16348
16349         /* Adjust the state of the output pipe according to whether we
16350          * have active connectors/encoders. */
16351         if (crtc->active && !intel_crtc_has_encoders(crtc))
16352                 intel_crtc_disable_noatomic(&crtc->base);
16353
16354         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16355                 /*
16356                  * We start out with underrun reporting disabled to avoid races.
16357                  * For correct bookkeeping mark this on active crtcs.
16358                  *
16359                  * Also on gmch platforms we dont have any hardware bits to
16360                  * disable the underrun reporting. Which means we need to start
16361                  * out with underrun reporting disabled also on inactive pipes,
16362                  * since otherwise we'll complain about the garbage we read when
16363                  * e.g. coming up after runtime pm.
16364                  *
16365                  * No protection against concurrent access is required - at
16366                  * worst a fifo underrun happens which also sets this to false.
16367                  */
16368                 crtc->cpu_fifo_underrun_disabled = true;
16369                 /*
16370                  * We track the PCH trancoder underrun reporting state
16371                  * within the crtc. With crtc for pipe A housing the underrun
16372                  * reporting state for PCH transcoder A, crtc for pipe B housing
16373                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16374                  * and marking underrun reporting as disabled for the non-existing
16375                  * PCH transcoders B and C would prevent enabling the south
16376                  * error interrupt (see cpt_can_enable_serr_int()).
16377                  */
16378                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16379                         crtc->pch_fifo_underrun_disabled = true;
16380         }
16381 }
16382
16383 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16384 {
16385         struct intel_connector *connector;
16386         struct drm_device *dev = encoder->base.dev;
16387
16388         /* We need to check both for a crtc link (meaning that the
16389          * encoder is active and trying to read from a pipe) and the
16390          * pipe itself being active. */
16391         bool has_active_crtc = encoder->base.crtc &&
16392                 to_intel_crtc(encoder->base.crtc)->active;
16393
16394         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
16395                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16396                               encoder->base.base.id,
16397                               encoder->base.name);
16398
16399                 /* Connector is active, but has no active pipe. This is
16400                  * fallout from our resume register restoring. Disable
16401                  * the encoder manually again. */
16402                 if (encoder->base.crtc) {
16403                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16404                                       encoder->base.base.id,
16405                                       encoder->base.name);
16406                         encoder->disable(encoder);
16407                         if (encoder->post_disable)
16408                                 encoder->post_disable(encoder);
16409                 }
16410                 encoder->base.crtc = NULL;
16411
16412                 /* Inconsistent output/port/pipe state happens presumably due to
16413                  * a bug in one of the get_hw_state functions. Or someplace else
16414                  * in our code, like the register restore mess on resume. Clamp
16415                  * things to off as a safer default. */
16416                 for_each_intel_connector(dev, connector) {
16417                         if (connector->encoder != encoder)
16418                                 continue;
16419                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16420                         connector->base.encoder = NULL;
16421                 }
16422         }
16423         /* Enabled encoders without active connectors will be fixed in
16424          * the crtc fixup. */
16425 }
16426
16427 void i915_redisable_vga_power_on(struct drm_device *dev)
16428 {
16429         struct drm_i915_private *dev_priv = to_i915(dev);
16430         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16431
16432         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16433                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16434                 i915_disable_vga(dev);
16435         }
16436 }
16437
16438 void i915_redisable_vga(struct drm_device *dev)
16439 {
16440         struct drm_i915_private *dev_priv = to_i915(dev);
16441
16442         /* This function can be called both from intel_modeset_setup_hw_state or
16443          * at a very early point in our resume sequence, where the power well
16444          * structures are not yet restored. Since this function is at a very
16445          * paranoid "someone might have enabled VGA while we were not looking"
16446          * level, just check if the power well is enabled instead of trying to
16447          * follow the "don't touch the power well if we don't need it" policy
16448          * the rest of the driver uses. */
16449         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16450                 return;
16451
16452         i915_redisable_vga_power_on(dev);
16453
16454         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16455 }
16456
16457 static bool primary_get_hw_state(struct intel_plane *plane)
16458 {
16459         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16460
16461         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16462 }
16463
16464 /* FIXME read out full plane state for all planes */
16465 static void readout_plane_state(struct intel_crtc *crtc)
16466 {
16467         struct drm_plane *primary = crtc->base.primary;
16468         struct intel_plane_state *plane_state =
16469                 to_intel_plane_state(primary->state);
16470
16471         plane_state->base.visible = crtc->active &&
16472                 primary_get_hw_state(to_intel_plane(primary));
16473
16474         if (plane_state->base.visible)
16475                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16476 }
16477
16478 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16479 {
16480         struct drm_i915_private *dev_priv = to_i915(dev);
16481         enum pipe pipe;
16482         struct intel_crtc *crtc;
16483         struct intel_encoder *encoder;
16484         struct intel_connector *connector;
16485         int i;
16486
16487         dev_priv->active_crtcs = 0;
16488
16489         for_each_intel_crtc(dev, crtc) {
16490                 struct intel_crtc_state *crtc_state = crtc->config;
16491                 int pixclk = 0;
16492
16493                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16494                 memset(crtc_state, 0, sizeof(*crtc_state));
16495                 crtc_state->base.crtc = &crtc->base;
16496
16497                 crtc_state->base.active = crtc_state->base.enable =
16498                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16499
16500                 crtc->base.enabled = crtc_state->base.enable;
16501                 crtc->active = crtc_state->base.active;
16502
16503                 if (crtc_state->base.active) {
16504                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16505
16506                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16507                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16508                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16509                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16510                         else
16511                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16512
16513                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16514                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16515                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16516                 }
16517
16518                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16519
16520                 readout_plane_state(crtc);
16521
16522                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16523                               crtc->base.base.id, crtc->base.name,
16524                               crtc->active ? "enabled" : "disabled");
16525         }
16526
16527         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16528                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16529
16530                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16531                                                   &pll->config.hw_state);
16532                 pll->config.crtc_mask = 0;
16533                 for_each_intel_crtc(dev, crtc) {
16534                         if (crtc->active && crtc->config->shared_dpll == pll)
16535                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16536                 }
16537                 pll->active_mask = pll->config.crtc_mask;
16538
16539                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16540                               pll->name, pll->config.crtc_mask, pll->on);
16541         }
16542
16543         for_each_intel_encoder(dev, encoder) {
16544                 pipe = 0;
16545
16546                 if (encoder->get_hw_state(encoder, &pipe)) {
16547                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16548                         encoder->base.crtc = &crtc->base;
16549                         crtc->config->output_types |= 1 << encoder->type;
16550                         encoder->get_config(encoder, crtc->config);
16551                 } else {
16552                         encoder->base.crtc = NULL;
16553                 }
16554
16555                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16556                               encoder->base.base.id,
16557                               encoder->base.name,
16558                               encoder->base.crtc ? "enabled" : "disabled",
16559                               pipe_name(pipe));
16560         }
16561
16562         for_each_intel_connector(dev, connector) {
16563                 if (connector->get_hw_state(connector)) {
16564                         connector->base.dpms = DRM_MODE_DPMS_ON;
16565
16566                         encoder = connector->encoder;
16567                         connector->base.encoder = &encoder->base;
16568
16569                         if (encoder->base.crtc &&
16570                             encoder->base.crtc->state->active) {
16571                                 /*
16572                                  * This has to be done during hardware readout
16573                                  * because anything calling .crtc_disable may
16574                                  * rely on the connector_mask being accurate.
16575                                  */
16576                                 encoder->base.crtc->state->connector_mask |=
16577                                         1 << drm_connector_index(&connector->base);
16578                                 encoder->base.crtc->state->encoder_mask |=
16579                                         1 << drm_encoder_index(&encoder->base);
16580                         }
16581
16582                 } else {
16583                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16584                         connector->base.encoder = NULL;
16585                 }
16586                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16587                               connector->base.base.id,
16588                               connector->base.name,
16589                               connector->base.encoder ? "enabled" : "disabled");
16590         }
16591
16592         for_each_intel_crtc(dev, crtc) {
16593                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16594
16595                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16596                 if (crtc->base.state->active) {
16597                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16598                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16599                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16600
16601                         /*
16602                          * The initial mode needs to be set in order to keep
16603                          * the atomic core happy. It wants a valid mode if the
16604                          * crtc's enabled, so we do the above call.
16605                          *
16606                          * At this point some state updated by the connectors
16607                          * in their ->detect() callback has not run yet, so
16608                          * no recalculation can be done yet.
16609                          *
16610                          * Even if we could do a recalculation and modeset
16611                          * right now it would cause a double modeset if
16612                          * fbdev or userspace chooses a different initial mode.
16613                          *
16614                          * If that happens, someone indicated they wanted a
16615                          * mode change, which means it's safe to do a full
16616                          * recalculation.
16617                          */
16618                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16619
16620                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16621                         update_scanline_offset(crtc);
16622                 }
16623
16624                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16625         }
16626 }
16627
16628 /* Scan out the current hw modeset state,
16629  * and sanitizes it to the current state
16630  */
16631 static void
16632 intel_modeset_setup_hw_state(struct drm_device *dev)
16633 {
16634         struct drm_i915_private *dev_priv = to_i915(dev);
16635         enum pipe pipe;
16636         struct intel_crtc *crtc;
16637         struct intel_encoder *encoder;
16638         int i;
16639
16640         intel_modeset_readout_hw_state(dev);
16641
16642         /* HW state is read out, now we need to sanitize this mess. */
16643         for_each_intel_encoder(dev, encoder) {
16644                 intel_sanitize_encoder(encoder);
16645         }
16646
16647         for_each_pipe(dev_priv, pipe) {
16648                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16649                 intel_sanitize_crtc(crtc);
16650                 intel_dump_pipe_config(crtc, crtc->config,
16651                                        "[setup_hw_state]");
16652         }
16653
16654         intel_modeset_update_connector_atomic_state(dev);
16655
16656         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16657                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16658
16659                 if (!pll->on || pll->active_mask)
16660                         continue;
16661
16662                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16663
16664                 pll->funcs.disable(dev_priv, pll);
16665                 pll->on = false;
16666         }
16667
16668         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16669                 vlv_wm_get_hw_state(dev);
16670         else if (IS_GEN9(dev))
16671                 skl_wm_get_hw_state(dev);
16672         else if (HAS_PCH_SPLIT(dev))
16673                 ilk_wm_get_hw_state(dev);
16674
16675         for_each_intel_crtc(dev, crtc) {
16676                 unsigned long put_domains;
16677
16678                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16679                 if (WARN_ON(put_domains))
16680                         modeset_put_power_domains(dev_priv, put_domains);
16681         }
16682         intel_display_set_init_power(dev_priv, false);
16683
16684         intel_fbc_init_pipe_state(dev_priv);
16685 }
16686
16687 void intel_display_resume(struct drm_device *dev)
16688 {
16689         struct drm_i915_private *dev_priv = to_i915(dev);
16690         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16691         struct drm_modeset_acquire_ctx ctx;
16692         int ret;
16693
16694         dev_priv->modeset_restore_state = NULL;
16695         if (state)
16696                 state->acquire_ctx = &ctx;
16697
16698         /*
16699          * This is a cludge because with real atomic modeset mode_config.mutex
16700          * won't be taken. Unfortunately some probed state like
16701          * audio_codec_enable is still protected by mode_config.mutex, so lock
16702          * it here for now.
16703          */
16704         mutex_lock(&dev->mode_config.mutex);
16705         drm_modeset_acquire_init(&ctx, 0);
16706
16707         while (1) {
16708                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16709                 if (ret != -EDEADLK)
16710                         break;
16711
16712                 drm_modeset_backoff(&ctx);
16713         }
16714
16715         if (!ret)
16716                 ret = __intel_display_resume(dev, state);
16717
16718         drm_modeset_drop_locks(&ctx);
16719         drm_modeset_acquire_fini(&ctx);
16720         mutex_unlock(&dev->mode_config.mutex);
16721
16722         if (ret) {
16723                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16724                 drm_atomic_state_free(state);
16725         }
16726 }
16727
16728 void intel_modeset_gem_init(struct drm_device *dev)
16729 {
16730         struct drm_i915_private *dev_priv = to_i915(dev);
16731         struct drm_crtc *c;
16732         struct drm_i915_gem_object *obj;
16733
16734         intel_init_gt_powersave(dev_priv);
16735
16736         intel_modeset_init_hw(dev);
16737
16738         intel_setup_overlay(dev_priv);
16739
16740         /*
16741          * Make sure any fbs we allocated at startup are properly
16742          * pinned & fenced.  When we do the allocation it's too early
16743          * for this.
16744          */
16745         for_each_crtc(dev, c) {
16746                 struct i915_vma *vma;
16747
16748                 obj = intel_fb_obj(c->primary->fb);
16749                 if (obj == NULL)
16750                         continue;
16751
16752                 mutex_lock(&dev->struct_mutex);
16753                 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
16754                                                  c->primary->state->rotation);
16755                 mutex_unlock(&dev->struct_mutex);
16756                 if (IS_ERR(vma)) {
16757                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16758                                   to_intel_crtc(c)->pipe);
16759                         drm_framebuffer_unreference(c->primary->fb);
16760                         c->primary->fb = NULL;
16761                         c->primary->crtc = c->primary->state->crtc = NULL;
16762                         update_state_fb(c->primary);
16763                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16764                 }
16765         }
16766 }
16767
16768 int intel_connector_register(struct drm_connector *connector)
16769 {
16770         struct intel_connector *intel_connector = to_intel_connector(connector);
16771         int ret;
16772
16773         ret = intel_backlight_device_register(intel_connector);
16774         if (ret)
16775                 goto err;
16776
16777         return 0;
16778
16779 err:
16780         return ret;
16781 }
16782
16783 void intel_connector_unregister(struct drm_connector *connector)
16784 {
16785         struct intel_connector *intel_connector = to_intel_connector(connector);
16786
16787         intel_backlight_device_unregister(intel_connector);
16788         intel_panel_destroy_backlight(connector);
16789 }
16790
16791 void intel_modeset_cleanup(struct drm_device *dev)
16792 {
16793         struct drm_i915_private *dev_priv = to_i915(dev);
16794
16795         intel_disable_gt_powersave(dev_priv);
16796
16797         /*
16798          * Interrupts and polling as the first thing to avoid creating havoc.
16799          * Too much stuff here (turning of connectors, ...) would
16800          * experience fancy races otherwise.
16801          */
16802         intel_irq_uninstall(dev_priv);
16803
16804         /*
16805          * Due to the hpd irq storm handling the hotplug work can re-arm the
16806          * poll handlers. Hence disable polling after hpd handling is shut down.
16807          */
16808         drm_kms_helper_poll_fini(dev);
16809
16810         intel_unregister_dsm_handler();
16811
16812         intel_fbc_global_disable(dev_priv);
16813
16814         /* flush any delayed tasks or pending work */
16815         flush_scheduled_work();
16816
16817         drm_mode_config_cleanup(dev);
16818
16819         intel_cleanup_overlay(dev_priv);
16820
16821         intel_cleanup_gt_powersave(dev_priv);
16822
16823         intel_teardown_gmbus(dev);
16824 }
16825
16826 void intel_connector_attach_encoder(struct intel_connector *connector,
16827                                     struct intel_encoder *encoder)
16828 {
16829         connector->encoder = encoder;
16830         drm_mode_connector_attach_encoder(&connector->base,
16831                                           &encoder->base);
16832 }
16833
16834 /*
16835  * set vga decode state - true == enable VGA decode
16836  */
16837 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16838 {
16839         struct drm_i915_private *dev_priv = to_i915(dev);
16840         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16841         u16 gmch_ctrl;
16842
16843         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16844                 DRM_ERROR("failed to read control word\n");
16845                 return -EIO;
16846         }
16847
16848         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16849                 return 0;
16850
16851         if (state)
16852                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16853         else
16854                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16855
16856         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16857                 DRM_ERROR("failed to write control word\n");
16858                 return -EIO;
16859         }
16860
16861         return 0;
16862 }
16863
16864 struct intel_display_error_state {
16865
16866         u32 power_well_driver;
16867
16868         int num_transcoders;
16869
16870         struct intel_cursor_error_state {
16871                 u32 control;
16872                 u32 position;
16873                 u32 base;
16874                 u32 size;
16875         } cursor[I915_MAX_PIPES];
16876
16877         struct intel_pipe_error_state {
16878                 bool power_domain_on;
16879                 u32 source;
16880                 u32 stat;
16881         } pipe[I915_MAX_PIPES];
16882
16883         struct intel_plane_error_state {
16884                 u32 control;
16885                 u32 stride;
16886                 u32 size;
16887                 u32 pos;
16888                 u32 addr;
16889                 u32 surface;
16890                 u32 tile_offset;
16891         } plane[I915_MAX_PIPES];
16892
16893         struct intel_transcoder_error_state {
16894                 bool power_domain_on;
16895                 enum transcoder cpu_transcoder;
16896
16897                 u32 conf;
16898
16899                 u32 htotal;
16900                 u32 hblank;
16901                 u32 hsync;
16902                 u32 vtotal;
16903                 u32 vblank;
16904                 u32 vsync;
16905         } transcoder[4];
16906 };
16907
16908 struct intel_display_error_state *
16909 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16910 {
16911         struct intel_display_error_state *error;
16912         int transcoders[] = {
16913                 TRANSCODER_A,
16914                 TRANSCODER_B,
16915                 TRANSCODER_C,
16916                 TRANSCODER_EDP,
16917         };
16918         int i;
16919
16920         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16921                 return NULL;
16922
16923         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16924         if (error == NULL)
16925                 return NULL;
16926
16927         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16928                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16929
16930         for_each_pipe(dev_priv, i) {
16931                 error->pipe[i].power_domain_on =
16932                         __intel_display_power_is_enabled(dev_priv,
16933                                                          POWER_DOMAIN_PIPE(i));
16934                 if (!error->pipe[i].power_domain_on)
16935                         continue;
16936
16937                 error->cursor[i].control = I915_READ(CURCNTR(i));
16938                 error->cursor[i].position = I915_READ(CURPOS(i));
16939                 error->cursor[i].base = I915_READ(CURBASE(i));
16940
16941                 error->plane[i].control = I915_READ(DSPCNTR(i));
16942                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16943                 if (INTEL_GEN(dev_priv) <= 3) {
16944                         error->plane[i].size = I915_READ(DSPSIZE(i));
16945                         error->plane[i].pos = I915_READ(DSPPOS(i));
16946                 }
16947                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16948                         error->plane[i].addr = I915_READ(DSPADDR(i));
16949                 if (INTEL_GEN(dev_priv) >= 4) {
16950                         error->plane[i].surface = I915_READ(DSPSURF(i));
16951                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16952                 }
16953
16954                 error->pipe[i].source = I915_READ(PIPESRC(i));
16955
16956                 if (HAS_GMCH_DISPLAY(dev_priv))
16957                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16958         }
16959
16960         /* Note: this does not include DSI transcoders. */
16961         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16962         if (HAS_DDI(dev_priv))
16963                 error->num_transcoders++; /* Account for eDP. */
16964
16965         for (i = 0; i < error->num_transcoders; i++) {
16966                 enum transcoder cpu_transcoder = transcoders[i];
16967
16968                 error->transcoder[i].power_domain_on =
16969                         __intel_display_power_is_enabled(dev_priv,
16970                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16971                 if (!error->transcoder[i].power_domain_on)
16972                         continue;
16973
16974                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16975
16976                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16977                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16978                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16979                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16980                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16981                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16982                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16983         }
16984
16985         return error;
16986 }
16987
16988 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16989
16990 void
16991 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16992                                 struct drm_device *dev,
16993                                 struct intel_display_error_state *error)
16994 {
16995         struct drm_i915_private *dev_priv = to_i915(dev);
16996         int i;
16997
16998         if (!error)
16999                 return;
17000
17001         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17002         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17003                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17004                            error->power_well_driver);
17005         for_each_pipe(dev_priv, i) {
17006                 err_printf(m, "Pipe [%d]:\n", i);
17007                 err_printf(m, "  Power: %s\n",
17008                            onoff(error->pipe[i].power_domain_on));
17009                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17010                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17011
17012                 err_printf(m, "Plane [%d]:\n", i);
17013                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17014                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17015                 if (INTEL_INFO(dev)->gen <= 3) {
17016                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17017                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17018                 }
17019                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17020                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17021                 if (INTEL_INFO(dev)->gen >= 4) {
17022                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17023                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17024                 }
17025
17026                 err_printf(m, "Cursor [%d]:\n", i);
17027                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17028                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17029                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17030         }
17031
17032         for (i = 0; i < error->num_transcoders; i++) {
17033                 err_printf(m, "CPU transcoder: %s\n",
17034                            transcoder_name(error->transcoder[i].cpu_transcoder));
17035                 err_printf(m, "  Power: %s\n",
17036                            onoff(error->transcoder[i].power_domain_on));
17037                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17038                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17039                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17040                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17041                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17042                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17043                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17044         }
17045 }