drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_framebuffer_init(struct drm_device *dev,
  90                                   struct intel_framebuffer *ifb,
  91                                   struct drm_mode_fb_cmd2 *mode_cmd,
  92                                   struct drm_i915_gem_object *obj);
  93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  96                                          struct intel_link_m_n *m_n,
  97                                          struct intel_link_m_n *m2_n2);
  98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 101 static void vlv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void chv_prepare_pll(struct intel_crtc *crtc,
 104                             const struct intel_crtc_state *pipe_config);
 105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 108         struct intel_crtc_state *crtc_state);
 109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 110                            int num_connectors);
 111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static const intel_limit_t intel_limits_bxt = {
 402         /* FIXME: find real dot limits */
 403         .dot = { .min = 0, .max = INT_MAX },
 404         .vco = { .min = 4800000, .max = 6700000 },
 405         .n = { .min = 1, .max = 1 },
 406         .m1 = { .min = 2, .max = 2 },
 407         /* FIXME: find real m2 limits */
 408         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 409         .p1 = { .min = 2, .max = 4 },
 410         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 411 };
 412
 413 static bool
 414 needs_modeset(struct drm_crtc_state *state)
 415 {
 416         return drm_atomic_crtc_needs_modeset(state);
 417 }
 418
 419 /**
 420  * Returns whether any output on the specified pipe is of the specified type
 421  */
 422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         struct intel_encoder *encoder;
 426
 427         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 428                 if (encoder->type == type)
 429                         return true;
 430
 431         return false;
 432 }
 433
 434 /**
 435  * Returns whether any output on the specified pipe will have the specified
 436  * type after a staged modeset is complete, i.e., the same as
 437  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 438  * encoder->crtc.
 439  */
 440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 441                                       int type)
 442 {
 443         struct drm_atomic_state *state = crtc_state->base.state;
 444         struct drm_connector *connector;
 445         struct drm_connector_state *connector_state;
 446         struct intel_encoder *encoder;
 447         int i, num_connectors = 0;
 448
 449         for_each_connector_in_state(state, connector, connector_state, i) {
 450                 if (connector_state->crtc != crtc_state->base.crtc)
 451                         continue;
 452
 453                 num_connectors++;
 454
 455                 encoder = to_intel_encoder(connector_state->best_encoder);
 456                 if (encoder->type == type)
 457                         return true;
 458         }
 459
 460         WARN_ON(num_connectors == 0);
 461
 462         return false;
 463 }
 464
 465 static const intel_limit_t *
 466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 467 {
 468         struct drm_device *dev = crtc_state->base.crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 472                 if (intel_is_dual_link_lvds(dev)) {
 473                         if (refclk == 100000)
 474                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 475                         else
 476                                 limit = &intel_limits_ironlake_dual_lvds;
 477                 } else {
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_single_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_single_lvds;
 482                 }
 483         } else
 484                 limit = &intel_limits_ironlake_dac;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *
 490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 491 {
 492         struct drm_device *dev = crtc_state->base.crtc->dev;
 493         const intel_limit_t *limit;
 494
 495         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 496                 if (intel_is_dual_link_lvds(dev))
 497                         limit = &intel_limits_g4x_dual_channel_lvds;
 498                 else
 499                         limit = &intel_limits_g4x_single_channel_lvds;
 500         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 501                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 502                 limit = &intel_limits_g4x_hdmi;
 503         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 504                 limit = &intel_limits_g4x_sdvo;
 505         } else /* The option is for other outputs */
 506                 limit = &intel_limits_i9xx_sdvo;
 507
 508         return limit;
 509 }
 510
 511 static const intel_limit_t *
 512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 513 {
 514         struct drm_device *dev = crtc_state->base.crtc->dev;
 515         const intel_limit_t *limit;
 516
 517         if (IS_BROXTON(dev))
 518                 limit = &intel_limits_bxt;
 519         else if (HAS_PCH_SPLIT(dev))
 520                 limit = intel_ironlake_limit(crtc_state, refclk);
 521         else if (IS_G4X(dev)) {
 522                 limit = intel_g4x_limit(crtc_state);
 523         } else if (IS_PINEVIEW(dev)) {
 524                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 525                         limit = &intel_limits_pineview_lvds;
 526                 else
 527                         limit = &intel_limits_pineview_sdvo;
 528         } else if (IS_CHERRYVIEW(dev)) {
 529                 limit = &intel_limits_chv;
 530         } else if (IS_VALLEYVIEW(dev)) {
 531                 limit = &intel_limits_vlv;
 532         } else if (!IS_GEN2(dev)) {
 533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_i9xx_lvds;
 535                 else
 536                         limit = &intel_limits_i9xx_sdvo;
 537         } else {
 538                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_i8xx_lvds;
 540                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 541                         limit = &intel_limits_i8xx_dvo;
 542                 else
 543                         limit = &intel_limits_i8xx_dac;
 544         }
 545         return limit;
 546 }
 547
 548 /*
 549  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 550  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 551  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 552  * The helpers' return value is the rate of the clock that is fed to the
 553  * display engine's pipe which can be the above fast dot clock rate or a
 554  * divided-down version of it.
 555  */
 556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 558 {
 559         clock->m = clock->m2 + 2;
 560         clock->p = clock->p1 * clock->p2;
 561         if (WARN_ON(clock->n == 0 || clock->p == 0))
 562                 return 0;
 563         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 564         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 565
 566         return clock->dot;
 567 }
 568
 569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 570 {
 571         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 572 }
 573
 574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 575 {
 576         clock->m = i9xx_dpll_compute_m(clock);
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 587 {
 588         clock->m = clock->m1 * clock->m2;
 589         clock->p = clock->p1 * clock->p2;
 590         if (WARN_ON(clock->n == 0 || clock->p == 0))
 591                 return 0;
 592         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot / 5;
 596 }
 597
 598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 599 {
 600         clock->m = clock->m1 * clock->m2;
 601         clock->p = clock->p1 * clock->p2;
 602         if (WARN_ON(clock->n == 0 || clock->p == 0))
 603                 return 0;
 604         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 605                         clock->n << 22);
 606         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 607
 608         return clock->dot / 5;
 609 }
 610
 611 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 612 /**
 613  * Returns whether the given set of divisors are valid for a given refclk with
 614  * the given connectors.
 615  */
 616
 617 static bool intel_PLL_is_valid(struct drm_device *dev,
 618                                const intel_limit_t *limit,
 619                                const intel_clock_t *clock)
 620 {
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 624                 INTELPllInvalid("p1 out of range\n");
 625         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 626                 INTELPllInvalid("m2 out of range\n");
 627         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 628                 INTELPllInvalid("m1 out of range\n");
 629
 630         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 631                 if (clock->m1 <= clock->m2)
 632                         INTELPllInvalid("m1 <= m2\n");
 633
 634         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 635                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 636                         INTELPllInvalid("p out of range\n");
 637                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 638                         INTELPllInvalid("m out of range\n");
 639         }
 640
 641         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 642                 INTELPllInvalid("vco out of range\n");
 643         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 644          * connector, etc., rather than just a single range.
 645          */
 646         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 647                 INTELPllInvalid("dot out of range\n");
 648
 649         return true;
 650 }
 651
 652 static int
 653 i9xx_select_p2_div(const intel_limit_t *limit,
 654                    const struct intel_crtc_state *crtc_state,
 655                    int target)
 656 {
 657         struct drm_device *dev = crtc_state->base.crtc->dev;
 658
 659         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 660                 /*
 661                  * For LVDS just rely on its current settings for dual-channel.
 662                  * We haven't figured out how to reliably set up different
 663                  * single/dual channel state, if we even can.
 664                  */
 665                 if (intel_is_dual_link_lvds(dev))
 666                         return limit->p2.p2_fast;
 667                 else
 668                         return limit->p2.p2_slow;
 669         } else {
 670                 if (target < limit->p2.dot_limit)
 671                         return limit->p2.p2_slow;
 672                 else
 673                         return limit->p2.p2_fast;
 674         }
 675 }
 676
 677 static bool
 678 i9xx_find_best_dpll(const intel_limit_t *limit,
 679                     struct intel_crtc_state *crtc_state,
 680                     int target, int refclk, intel_clock_t *match_clock,
 681                     intel_clock_t *best_clock)
 682 {
 683         struct drm_device *dev = crtc_state->base.crtc->dev;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         memset(best_clock, 0, sizeof(*best_clock));
 688
 689         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         if (clock.m2 >= clock.m1)
 696                                 break;
 697                         for (clock.n = limit->n.min;
 698                              clock.n <= limit->n.max; clock.n++) {
 699                                 for (clock.p1 = limit->p1.min;
 700                                         clock.p1 <= limit->p1.max; clock.p1++) {
 701                                         int this_err;
 702
 703                                         i9xx_calc_dpll_params(refclk, &clock);
 704                                         if (!intel_PLL_is_valid(dev, limit,
 705                                                                 &clock))
 706                                                 continue;
 707                                         if (match_clock &&
 708                                             clock.p != match_clock->p)
 709                                                 continue;
 710
 711                                         this_err = abs(clock.dot - target);
 712                                         if (this_err < err) {
 713                                                 *best_clock = clock;
 714                                                 err = this_err;
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return (err != target);
 722 }
 723
 724 static bool
 725 pnv_find_best_dpll(const intel_limit_t *limit,
 726                    struct intel_crtc_state *crtc_state,
 727                    int target, int refclk, intel_clock_t *match_clock,
 728                    intel_clock_t *best_clock)
 729 {
 730         struct drm_device *dev = crtc_state->base.crtc->dev;
 731         intel_clock_t clock;
 732         int err = target;
 733
 734         memset(best_clock, 0, sizeof(*best_clock));
 735
 736         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 737
 738         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 739              clock.m1++) {
 740                 for (clock.m2 = limit->m2.min;
 741                      clock.m2 <= limit->m2.max; clock.m2++) {
 742                         for (clock.n = limit->n.min;
 743                              clock.n <= limit->n.max; clock.n++) {
 744                                 for (clock.p1 = limit->p1.min;
 745                                         clock.p1 <= limit->p1.max; clock.p1++) {
 746                                         int this_err;
 747
 748                                         pnv_calc_dpll_params(refclk, &clock);
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752                                         if (match_clock &&
 753                                             clock.p != match_clock->p)
 754                                                 continue;
 755
 756                                         this_err = abs(clock.dot - target);
 757                                         if (this_err < err) {
 758                                                 *best_clock = clock;
 759                                                 err = this_err;
 760                                         }
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         return (err != target);
 767 }
 768
 769 static bool
 770 g4x_find_best_dpll(const intel_limit_t *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, intel_clock_t *match_clock,
 773                    intel_clock_t *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->base.crtc->dev;
 776         intel_clock_t clock;
 777         int max_n;
 778         bool found = false;
 779         /* approximately equals target * 0.00585 */
 780         int err_most = (target >> 8) + (target >> 9);
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         max_n = limit->n.max;
 787         /* based on hardware requirement, prefer smaller n to precision */
 788         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 789                 /* based on hardware requirement, prefere larger m1,m2 */
 790                 for (clock.m1 = limit->m1.max;
 791                      clock.m1 >= limit->m1.min; clock.m1--) {
 792                         for (clock.m2 = limit->m2.max;
 793                              clock.m2 >= limit->m2.min; clock.m2--) {
 794                                 for (clock.p1 = limit->p1.max;
 795                                      clock.p1 >= limit->p1.min; clock.p1--) {
 796                                         int this_err;
 797
 798                                         i9xx_calc_dpll_params(refclk, &clock);
 799                                         if (!intel_PLL_is_valid(dev, limit,
 800                                                                 &clock))
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err_most) {
 805                                                 *best_clock = clock;
 806                                                 err_most = this_err;
 807                                                 max_n = clock.n;
 808                                                 found = true;
 809                                         }
 810                                 }
 811                         }
 812                 }
 813         }
 814         return found;
 815 }
 816
 817 /*
 818  * Check if the calculated PLL configuration is more optimal compared to the
 819  * best configuration and error found so far. Return the calculated error.
 820  */
 821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 822                                const intel_clock_t *calculated_clock,
 823                                const intel_clock_t *best_clock,
 824                                unsigned int best_error_ppm,
 825                                unsigned int *error_ppm)
 826 {
 827         /*
 828          * For CHV ignore the error and consider only the P value.
 829          * Prefer a bigger P value based on HW requirements.
 830          */
 831         if (IS_CHERRYVIEW(dev)) {
 832                 *error_ppm = 0;
 833
 834                 return calculated_clock->p > best_clock->p;
 835         }
 836
 837         if (WARN_ON_ONCE(!target_freq))
 838                 return false;
 839
 840         *error_ppm = div_u64(1000000ULL *
 841                                 abs(target_freq - calculated_clock->dot),
 842                              target_freq);
 843         /*
 844          * Prefer a better P value over a better (smaller) error if the error
 845          * is small. Ensure this preference for future configurations too by
 846          * setting the error to 0.
 847          */
 848         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 849                 *error_ppm = 0;
 850
 851                 return true;
 852         }
 853
 854         return *error_ppm + 10 < best_error_ppm;
 855 }
 856
 857 static bool
 858 vlv_find_best_dpll(const intel_limit_t *limit,
 859                    struct intel_crtc_state *crtc_state,
 860                    int target, int refclk, intel_clock_t *match_clock,
 861                    intel_clock_t *best_clock)
 862 {
 863         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 864         struct drm_device *dev = crtc->base.dev;
 865         intel_clock_t clock;
 866         unsigned int bestppm = 1000000;
 867         /* min update 19.2 MHz */
 868         int max_n = min(limit->n.max, refclk / 19200);
 869         bool found = false;
 870
 871         target *= 5; /* fast clock */
 872
 873         memset(best_clock, 0, sizeof(*best_clock));
 874
 875         /* based on hardware requirement, prefer smaller n to precision */
 876         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 877                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 878                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 879                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 880                                 clock.p = clock.p1 * clock.p2;
 881                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 882                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 883                                         unsigned int ppm;
 884
 885                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 886                                                                      refclk * clock.m1);
 887
 888                                         vlv_calc_dpll_params(refclk, &clock);
 889
 890                                         if (!intel_PLL_is_valid(dev, limit,
 891                                                                 &clock))
 892                                                 continue;
 893
 894                                         if (!vlv_PLL_is_optimal(dev, target,
 895                                                                 &clock,
 896                                                                 best_clock,
 897                                                                 bestppm, &ppm))
 898                                                 continue;
 899
 900                                         *best_clock = clock;
 901                                         bestppm = ppm;
 902                                         found = true;
 903                                 }
 904                         }
 905                 }
 906         }
 907
 908         return found;
 909 }
 910
 911 static bool
 912 chv_find_best_dpll(const intel_limit_t *limit,
 913                    struct intel_crtc_state *crtc_state,
 914                    int target, int refclk, intel_clock_t *match_clock,
 915                    intel_clock_t *best_clock)
 916 {
 917         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 918         struct drm_device *dev = crtc->base.dev;
 919         unsigned int best_error_ppm;
 920         intel_clock_t clock;
 921         uint64_t m2;
 922         int found = false;
 923
 924         memset(best_clock, 0, sizeof(*best_clock));
 925         best_error_ppm = 1000000;
 926
 927         /*
 928          * Based on hardware doc, the n always set to 1, and m1 always
 929          * set to 2.  If requires to support 200Mhz refclk, we need to
 930          * revisit this because n may not 1 anymore.
 931          */
 932         clock.n = 1, clock.m1 = 2;
 933         target *= 5;    /* fast clock */
 934
 935         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 936                 for (clock.p2 = limit->p2.p2_fast;
 937                                 clock.p2 >= limit->p2.p2_slow;
 938                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                         unsigned int error_ppm;
 940
 941                         clock.p = clock.p1 * clock.p2;
 942
 943                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 944                                         clock.n) << 22, refclk * clock.m1);
 945
 946                         if (m2 > INT_MAX/clock.m1)
 947                                 continue;
 948
 949                         clock.m2 = m2;
 950
 951                         chv_calc_dpll_params(refclk, &clock);
 952
 953                         if (!intel_PLL_is_valid(dev, limit, &clock))
 954                                 continue;
 955
 956                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 957                                                 best_error_ppm, &error_ppm))
 958                                 continue;
 959
 960                         *best_clock = clock;
 961                         best_error_ppm = error_ppm;
 962                         found = true;
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 970                         intel_clock_t *best_clock)
 971 {
 972         int refclk = i9xx_get_refclk(crtc_state, 0);
 973
 974         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 975                                   target_clock, refclk, NULL, best_clock);
 976 }
 977
 978 bool intel_crtc_active(struct drm_crtc *crtc)
 979 {
 980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 981
 982         /* Be paranoid as we can arrive here with only partial
 983          * state retrieved from the hardware during setup.
 984          *
 985          * We can ditch the adjusted_mode.crtc_clock check as soon
 986          * as Haswell has gained clock readout/fastboot support.
 987          *
 988          * We can ditch the crtc->primary->fb check as soon as we can
 989          * properly reconstruct framebuffers.
 990          *
 991          * FIXME: The intel_crtc->active here should be switched to
 992          * crtc->state->active once we have proper CRTC states wired up
 993          * for atomic.
 994          */
 995         return intel_crtc->active && crtc->primary->state->fb &&
 996                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 997 }
 998
 999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000                                              enum pipe pipe)
1001 {
1002         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005         return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         u32 reg = PIPEDSL(pipe);
1012         u32 line1, line2;
1013         u32 line_mask;
1014
1015         if (IS_GEN2(dev))
1016                 line_mask = DSL_LINEMASK_GEN2;
1017         else
1018                 line_mask = DSL_LINEMASK_GEN3;
1019
1020         line1 = I915_READ(reg) & line_mask;
1021         msleep(5);
1022         line2 = I915_READ(reg) & line_mask;
1023
1024         return line1 == line2;
1025 }
1026
1027 /*
1028  * intel_wait_for_pipe_off - wait for pipe to turn off
1029  * @crtc: crtc whose pipe to wait for
1030  *
1031  * After disabling a pipe, we can't wait for vblank in the usual way,
1032  * spinning on the vblank interrupt status bit, since we won't actually
1033  * see an interrupt when the pipe is disabled.
1034  *
1035  * On Gen4 and above:
1036  *   wait for the pipe register state bit to turn off
1037  *
1038  * Otherwise:
1039  *   wait for the display line value to settle (it usually
1040  *   ends up stopping at the start of the next frame).
1041  *
1042  */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045         struct drm_device *dev = crtc->base.dev;
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048         enum pipe pipe = crtc->pipe;
1049
1050         if (INTEL_INFO(dev)->gen >= 4) {
1051                 int reg = PIPECONF(cpu_transcoder);
1052
1053                 /* Wait for the Pipe State to go off */
1054                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055                              100))
1056                         WARN(1, "pipe_off wait timed out\n");
1057         } else {
1058                 /* Wait for the display line to settle */
1059                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060                         WARN(1, "pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 /*
1065  * ibx_digital_port_connected - is the specified port connected?
1066  * @dev_priv: i915 private structure
1067  * @port: the port to test
1068  *
1069  * Returns true if @port is connected, false otherwise.
1070  */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072                                 struct intel_digital_port *port)
1073 {
1074         u32 bit;
1075
1076         if (HAS_PCH_IBX(dev_priv->dev)) {
1077                 switch (port->port) {
1078                 case PORT_B:
1079                         bit = SDE_PORTB_HOTPLUG;
1080                         break;
1081                 case PORT_C:
1082                         bit = SDE_PORTC_HOTPLUG;
1083                         break;
1084                 case PORT_D:
1085                         bit = SDE_PORTD_HOTPLUG;
1086                         break;
1087                 default:
1088                         return true;
1089                 }
1090         } else {
1091                 switch (port->port) {
1092                 case PORT_B:
1093                         bit = SDE_PORTB_HOTPLUG_CPT;
1094                         break;
1095                 case PORT_C:
1096                         bit = SDE_PORTC_HOTPLUG_CPT;
1097                         break;
1098                 case PORT_D:
1099                         bit = SDE_PORTD_HOTPLUG_CPT;
1100                         break;
1101                 default:
1102                         return true;
1103                 }
1104         }
1105
1106         return I915_READ(SDEISR) & bit;
1107 }
1108
1109 static const char *state_string(bool enabled)
1110 {
1111         return enabled ? "on" : "off";
1112 }
1113
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116                 enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121
1122         reg = DPLL(pipe);
1123         val = I915_READ(reg);
1124         cur_state = !!(val & DPLL_VCO_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "PLL state assertion failure (expected %s, current %s)\n",
1127              state_string(state), state_string(cur_state));
1128 }
1129
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132 {
1133         u32 val;
1134         bool cur_state;
1135
1136         mutex_lock(&dev_priv->sb_lock);
1137         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138         mutex_unlock(&dev_priv->sb_lock);
1139
1140         cur_state = val & DSI_PLL_VCO_EN;
1141         I915_STATE_WARN(cur_state != state,
1142              "DSI PLL state assertion failure (expected %s, current %s)\n",
1143              state_string(state), state_string(cur_state));
1144 }
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150 {
1151         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
1153         if (crtc->config->shared_dpll < 0)
1154                 return NULL;
1155
1156         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1157 }
1158
1159 /* For ILK+ */
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161                         struct intel_shared_dpll *pll,
1162                         bool state)
1163 {
1164         bool cur_state;
1165         struct intel_dpll_hw_state hw_state;
1166
1167         if (WARN (!pll,
1168                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1169                 return;
1170
1171         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172         I915_STATE_WARN(cur_state != state,
1173              "%s assertion failure (expected %s, current %s)\n",
1174              pll->name, state_string(state), state_string(cur_state));
1175 }
1176
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178                           enum pipe pipe, bool state)
1179 {
1180         int reg;
1181         u32 val;
1182         bool cur_state;
1183         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184                                                                       pipe);
1185
1186         if (HAS_DDI(dev_priv->dev)) {
1187                 /* DDI does not have a specific FDI_TX register */
1188                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189                 val = I915_READ(reg);
1190                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1191         } else {
1192                 reg = FDI_TX_CTL(pipe);
1193                 val = I915_READ(reg);
1194                 cur_state = !!(val & FDI_TX_ENABLE);
1195         }
1196         I915_STATE_WARN(cur_state != state,
1197              "FDI TX state assertion failure (expected %s, current %s)\n",
1198              state_string(state), state_string(cur_state));
1199 }
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204                           enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209
1210         reg = FDI_RX_CTL(pipe);
1211         val = I915_READ(reg);
1212         cur_state = !!(val & FDI_RX_ENABLE);
1213         I915_STATE_WARN(cur_state != state,
1214              "FDI RX state assertion failure (expected %s, current %s)\n",
1215              state_string(state), state_string(cur_state));
1216 }
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221                                       enum pipe pipe)
1222 {
1223         int reg;
1224         u32 val;
1225
1226         /* ILK FDI PLL is always enabled */
1227         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1228                 return;
1229
1230         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231         if (HAS_DDI(dev_priv->dev))
1232                 return;
1233
1234         reg = FDI_TX_CTL(pipe);
1235         val = I915_READ(reg);
1236         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1237 }
1238
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240                        enum pipe pipe, bool state)
1241 {
1242         int reg;
1243         u32 val;
1244         bool cur_state;
1245
1246         reg = FDI_RX_CTL(pipe);
1247         val = I915_READ(reg);
1248         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255                            enum pipe pipe)
1256 {
1257         struct drm_device *dev = dev_priv->dev;
1258         int pp_reg;
1259         u32 val;
1260         enum pipe panel_pipe = PIPE_A;
1261         bool locked = true;
1262
1263         if (WARN_ON(HAS_DDI(dev)))
1264                 return;
1265
1266         if (HAS_PCH_SPLIT(dev)) {
1267                 u32 port_sel;
1268
1269                 pp_reg = PCH_PP_CONTROL;
1270                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274                         panel_pipe = PIPE_B;
1275                 /* XXX: else fix for eDP */
1276         } else if (IS_VALLEYVIEW(dev)) {
1277                 /* presumably write lock depends on pipe, not port select */
1278                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279                 panel_pipe = pipe;
1280         } else {
1281                 pp_reg = PP_CONTROL;
1282                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283                         panel_pipe = PIPE_B;
1284         }
1285
1286         val = I915_READ(pp_reg);
1287         if (!(val & PANEL_POWER_ON) ||
1288             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1289                 locked = false;
1290
1291         I915_STATE_WARN(panel_pipe == pipe && locked,
1292              "panel assertion failure, pipe %c regs locked\n",
1293              pipe_name(pipe));
1294 }
1295
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297                           enum pipe pipe, bool state)
1298 {
1299         struct drm_device *dev = dev_priv->dev;
1300         bool cur_state;
1301
1302         if (IS_845G(dev) || IS_I865G(dev))
1303                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1304         else
1305                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1306
1307         I915_STATE_WARN(cur_state != state,
1308              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309              pipe_name(pipe), state_string(state), state_string(cur_state));
1310 }
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315                  enum pipe pipe, bool state)
1316 {
1317         int reg;
1318         u32 val;
1319         bool cur_state;
1320         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321                                                                       pipe);
1322
1323         /* if we need the pipe quirk it must be always on */
1324         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1326                 state = true;
1327
1328         if (!intel_display_power_is_enabled(dev_priv,
1329                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1330                 cur_state = false;
1331         } else {
1332                 reg = PIPECONF(cpu_transcoder);
1333                 val = I915_READ(reg);
1334                 cur_state = !!(val & PIPECONF_ENABLE);
1335         }
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343                          enum plane plane, bool state)
1344 {
1345         int reg;
1346         u32 val;
1347         bool cur_state;
1348
1349         reg = DSPCNTR(plane);
1350         val = I915_READ(reg);
1351         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352         I915_STATE_WARN(cur_state != state,
1353              "plane %c assertion failure (expected %s, current %s)\n",
1354              plane_name(plane), state_string(state), state_string(cur_state));
1355 }
1356
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361                                    enum pipe pipe)
1362 {
1363         struct drm_device *dev = dev_priv->dev;
1364         int reg, i;
1365         u32 val;
1366         int cur_pipe;
1367
1368         /* Primary planes are fixed to pipes on gen4+ */
1369         if (INTEL_INFO(dev)->gen >= 4) {
1370                 reg = DSPCNTR(pipe);
1371                 val = I915_READ(reg);
1372                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373                      "plane %c assertion failure, should be disabled but not\n",
1374                      plane_name(pipe));
1375                 return;
1376         }
1377
1378         /* Need to check both planes against the pipe */
1379         for_each_pipe(dev_priv, i) {
1380                 reg = DSPCNTR(i);
1381                 val = I915_READ(reg);
1382                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383                         DISPPLANE_SEL_PIPE_SHIFT;
1384                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386                      plane_name(i), pipe_name(pipe));
1387         }
1388 }
1389
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391                                     enum pipe pipe)
1392 {
1393         struct drm_device *dev = dev_priv->dev;
1394         int reg, sprite;
1395         u32 val;
1396
1397         if (INTEL_INFO(dev)->gen >= 9) {
1398                 for_each_sprite(dev_priv, pipe, sprite) {
1399                         val = I915_READ(PLANE_CTL(pipe, sprite));
1400                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402                              sprite, pipe_name(pipe));
1403                 }
1404         } else if (IS_VALLEYVIEW(dev)) {
1405                 for_each_sprite(dev_priv, pipe, sprite) {
1406                         reg = SPCNTR(pipe, sprite);
1407                         val = I915_READ(reg);
1408                         I915_STATE_WARN(val & SP_ENABLE,
1409                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410                              sprite_name(pipe, sprite), pipe_name(pipe));
1411                 }
1412         } else if (INTEL_INFO(dev)->gen >= 7) {
1413                 reg = SPRCTL(pipe);
1414                 val = I915_READ(reg);
1415                 I915_STATE_WARN(val & SPRITE_ENABLE,
1416                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417                      plane_name(pipe), pipe_name(pipe));
1418         } else if (INTEL_INFO(dev)->gen >= 5) {
1419                 reg = DVSCNTR(pipe);
1420                 val = I915_READ(reg);
1421                 I915_STATE_WARN(val & DVS_ENABLE,
1422                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423                      plane_name(pipe), pipe_name(pipe));
1424         }
1425 }
1426
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1428 {
1429         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430                 drm_crtc_vblank_put(crtc);
1431 }
1432
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1434 {
1435         u32 val;
1436         bool enabled;
1437
1438         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1439
1440         val = I915_READ(PCH_DREF_CONTROL);
1441         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442                             DREF_SUPERSPREAD_SOURCE_MASK));
1443         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1444 }
1445
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447                                            enum pipe pipe)
1448 {
1449         int reg;
1450         u32 val;
1451         bool enabled;
1452
1453         reg = PCH_TRANSCONF(pipe);
1454         val = I915_READ(reg);
1455         enabled = !!(val & TRANS_ENABLE);
1456         I915_STATE_WARN(enabled,
1457              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458              pipe_name(pipe));
1459 }
1460
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462                             enum pipe pipe, u32 port_sel, u32 val)
1463 {
1464         if ((val & DP_PORT_EN) == 0)
1465                 return false;
1466
1467         if (HAS_PCH_CPT(dev_priv->dev)) {
1468                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471                         return false;
1472         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483                               enum pipe pipe, u32 val)
1484 {
1485         if ((val & SDVO_ENABLE) == 0)
1486                 return false;
1487
1488         if (HAS_PCH_CPT(dev_priv->dev)) {
1489                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1490                         return false;
1491         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493                         return false;
1494         } else {
1495                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1496                         return false;
1497         }
1498         return true;
1499 }
1500
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502                               enum pipe pipe, u32 val)
1503 {
1504         if ((val & LVDS_PORT_EN) == 0)
1505                 return false;
1506
1507         if (HAS_PCH_CPT(dev_priv->dev)) {
1508                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & ADPA_DAC_ENABLE) == 0)
1521                 return false;
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533                                    enum pipe pipe, int reg, u32 port_sel)
1534 {
1535         u32 val = I915_READ(reg);
1536         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538              reg, pipe_name(pipe));
1539
1540         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541              && (val & DP_PIPEB_SELECT),
1542              "IBX PCH dp port still using transcoder B\n");
1543 }
1544
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546                                      enum pipe pipe, int reg)
1547 {
1548         u32 val = I915_READ(reg);
1549         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551              reg, pipe_name(pipe));
1552
1553         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554              && (val & SDVO_PIPE_B_SELECT),
1555              "IBX PCH hdmi port still using transcoder B\n");
1556 }
1557
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559                                       enum pipe pipe)
1560 {
1561         int reg;
1562         u32 val;
1563
1564         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1567
1568         reg = PCH_ADPA;
1569         val = I915_READ(reg);
1570         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571              "PCH VGA enabled on transcoder %c, should be disabled\n",
1572              pipe_name(pipe));
1573
1574         reg = PCH_LVDS;
1575         val = I915_READ(reg);
1576         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1578              pipe_name(pipe));
1579
1580         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1583 }
1584
1585 static void intel_init_dpio(struct drm_device *dev)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589         if (!IS_VALLEYVIEW(dev))
1590                 return;
1591
1592         /*
1593          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594          * CHV x1 PHY (DP/HDMI D)
1595          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596          */
1597         if (IS_CHERRYVIEW(dev)) {
1598                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600         } else {
1601                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602         }
1603 }
1604
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606                            const struct intel_crtc_state *pipe_config)
1607 {
1608         struct drm_device *dev = crtc->base.dev;
1609         struct drm_i915_private *dev_priv = dev->dev_private;
1610         int reg = DPLL(crtc->pipe);
1611         u32 dpll = pipe_config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* No really, not for ILK+ */
1616         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618         /* PLL is protected by panel, make sure we can write it */
1619         if (IS_MOBILE(dev_priv->dev))
1620                 assert_panel_unlocked(dev_priv, crtc->pipe);
1621
1622         I915_WRITE(reg, dpll);
1623         POSTING_READ(reg);
1624         udelay(150);
1625
1626         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
1629         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630         POSTING_READ(DPLL_MD(crtc->pipe));
1631
1632         /* We do this three times for luck */
1633         I915_WRITE(reg, dpll);
1634         POSTING_READ(reg);
1635         udelay(150); /* wait for warmup */
1636         I915_WRITE(reg, dpll);
1637         POSTING_READ(reg);
1638         udelay(150); /* wait for warmup */
1639         I915_WRITE(reg, dpll);
1640         POSTING_READ(reg);
1641         udelay(150); /* wait for warmup */
1642 }
1643
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645                            const struct intel_crtc_state *pipe_config)
1646 {
1647         struct drm_device *dev = crtc->base.dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         int pipe = crtc->pipe;
1650         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1651         u32 tmp;
1652
1653         assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
1657         mutex_lock(&dev_priv->sb_lock);
1658
1659         /* Enable back the 10bit clock to display controller */
1660         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661         tmp |= DPIO_DCLKP_EN;
1662         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
1664         mutex_unlock(&dev_priv->sb_lock);
1665
1666         /*
1667          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668          */
1669         udelay(1);
1670
1671         /* Enable PLL */
1672         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1673
1674         /* Check PLL is locked */
1675         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
1678         /* not sure when this should be written */
1679         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680         POSTING_READ(DPLL_MD(pipe));
1681 }
1682
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1684 {
1685         struct intel_crtc *crtc;
1686         int count = 0;
1687
1688         for_each_intel_crtc(dev, crtc)
1689                 count += crtc->base.state->active &&
1690                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1691
1692         return count;
1693 }
1694
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1696 {
1697         struct drm_device *dev = crtc->base.dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699         int reg = DPLL(crtc->pipe);
1700         u32 dpll = crtc->config->dpll_hw_state.dpll;
1701
1702         assert_pipe_disabled(dev_priv, crtc->pipe);
1703
1704         /* No really, not for ILK+ */
1705         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1706
1707         /* PLL is protected by panel, make sure we can write it */
1708         if (IS_MOBILE(dev) && !IS_I830(dev))
1709                 assert_panel_unlocked(dev_priv, crtc->pipe);
1710
1711         /* Enable DVO 2x clock on both PLLs if necessary */
1712         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713                 /*
1714                  * It appears to be important that we don't enable this
1715                  * for the current pipe before otherwise configuring the
1716                  * PLL. No idea how this should be handled if multiple
1717                  * DVO outputs are enabled simultaneosly.
1718                  */
1719                 dpll |= DPLL_DVO_2X_MODE;
1720                 I915_WRITE(DPLL(!crtc->pipe),
1721                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722         }
1723
1724         /* Wait for the clocks to stabilize. */
1725         POSTING_READ(reg);
1726         udelay(150);
1727
1728         if (INTEL_INFO(dev)->gen >= 4) {
1729                 I915_WRITE(DPLL_MD(crtc->pipe),
1730                            crtc->config->dpll_hw_state.dpll_md);
1731         } else {
1732                 /* The pixel multiplier can only be updated once the
1733                  * DPLL is enabled and the clocks are stable.
1734                  *
1735                  * So write it again.
1736                  */
1737                 I915_WRITE(reg, dpll);
1738         }
1739
1740         /* We do this three times for luck */
1741         I915_WRITE(reg, dpll);
1742         POSTING_READ(reg);
1743         udelay(150); /* wait for warmup */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750 }
1751
1752 /**
1753  * i9xx_disable_pll - disable a PLL
1754  * @dev_priv: i915 private structure
1755  * @pipe: pipe PLL to disable
1756  *
1757  * Disable the PLL for @pipe, making sure the pipe is off first.
1758  *
1759  * Note!  This is for pre-ILK only.
1760  */
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1762 {
1763         struct drm_device *dev = crtc->base.dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         enum pipe pipe = crtc->pipe;
1766
1767         /* Disable DVO 2x clock on both PLLs if necessary */
1768         if (IS_I830(dev) &&
1769             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770             !intel_num_dvo_pipes(dev)) {
1771                 I915_WRITE(DPLL(PIPE_B),
1772                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773                 I915_WRITE(DPLL(PIPE_A),
1774                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775         }
1776
1777         /* Don't disable pipe or pipe PLLs if needed */
1778         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1780                 return;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786         POSTING_READ(DPLL(pipe));
1787 }
1788
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790 {
1791         u32 val;
1792
1793         /* Make sure the pipe isn't still relying on us */
1794         assert_pipe_disabled(dev_priv, pipe);
1795
1796         /*
1797          * Leave integrated clock source and reference clock enabled for pipe B.
1798          * The latter is needed for VGA hotplug / manual detection.
1799          */
1800         val = DPLL_VGA_MODE_DIS;
1801         if (pipe == PIPE_B)
1802                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803         I915_WRITE(DPLL(pipe), val);
1804         POSTING_READ(DPLL(pipe));
1805
1806 }
1807
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809 {
1810         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1811         u32 val;
1812
1813         /* Make sure the pipe isn't still relying on us */
1814         assert_pipe_disabled(dev_priv, pipe);
1815
1816         /* Set PLL en = 0 */
1817         val = DPLL_SSC_REF_CLK_CHV |
1818                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1819         if (pipe != PIPE_A)
1820                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821         I915_WRITE(DPLL(pipe), val);
1822         POSTING_READ(DPLL(pipe));
1823
1824         mutex_lock(&dev_priv->sb_lock);
1825
1826         /* Disable 10bit clock to display controller */
1827         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828         val &= ~DPIO_DCLKP_EN;
1829         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
1831         /* disable left/right clock distribution */
1832         if (pipe != PIPE_B) {
1833                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836         } else {
1837                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840         }
1841
1842         mutex_unlock(&dev_priv->sb_lock);
1843 }
1844
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846                          struct intel_digital_port *dport,
1847                          unsigned int expected_mask)
1848 {
1849         u32 port_mask;
1850         int dpll_reg;
1851
1852         switch (dport->port) {
1853         case PORT_B:
1854                 port_mask = DPLL_PORTB_READY_MASK;
1855                 dpll_reg = DPLL(0);
1856                 break;
1857         case PORT_C:
1858                 port_mask = DPLL_PORTC_READY_MASK;
1859                 dpll_reg = DPLL(0);
1860                 expected_mask <<= 4;
1861                 break;
1862         case PORT_D:
1863                 port_mask = DPLL_PORTD_READY_MASK;
1864                 dpll_reg = DPIO_PHY_STATUS;
1865                 break;
1866         default:
1867                 BUG();
1868         }
1869
1870         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1873 }
1874
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876 {
1877         struct drm_device *dev = crtc->base.dev;
1878         struct drm_i915_private *dev_priv = dev->dev_private;
1879         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
1881         if (WARN_ON(pll == NULL))
1882                 return;
1883
1884         WARN_ON(!pll->config.crtc_mask);
1885         if (pll->active == 0) {
1886                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887                 WARN_ON(pll->on);
1888                 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890                 pll->mode_set(dev_priv, pll);
1891         }
1892 }
1893
1894 /**
1895  * intel_enable_shared_dpll - enable PCH PLL
1896  * @dev_priv: i915 private structure
1897  * @pipe: pipe PLL to enable
1898  *
1899  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900  * drives the transcoder clock.
1901  */
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1903 {
1904         struct drm_device *dev = crtc->base.dev;
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1907
1908         if (WARN_ON(pll == NULL))
1909                 return;
1910
1911         if (WARN_ON(pll->config.crtc_mask == 0))
1912                 return;
1913
1914         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915                       pll->name, pll->active, pll->on,
1916                       crtc->base.base.id);
1917
1918         if (pll->active++) {
1919                 WARN_ON(!pll->on);
1920                 assert_shared_dpll_enabled(dev_priv, pll);
1921                 return;
1922         }
1923         WARN_ON(pll->on);
1924
1925         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
1927         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928         pll->enable(dev_priv, pll);
1929         pll->on = true;
1930 }
1931
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1933 {
1934         struct drm_device *dev = crtc->base.dev;
1935         struct drm_i915_private *dev_priv = dev->dev_private;
1936         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1937
1938         /* PCH only available on ILK+ */
1939         if (INTEL_INFO(dev)->gen < 5)
1940                 return;
1941
1942         if (pll == NULL)
1943                 return;
1944
1945         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1946                 return;
1947
1948         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949                       pll->name, pll->active, pll->on,
1950                       crtc->base.base.id);
1951
1952         if (WARN_ON(pll->active == 0)) {
1953                 assert_shared_dpll_disabled(dev_priv, pll);
1954                 return;
1955         }
1956
1957         assert_shared_dpll_enabled(dev_priv, pll);
1958         WARN_ON(!pll->on);
1959         if (--pll->active)
1960                 return;
1961
1962         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1963         pll->disable(dev_priv, pll);
1964         pll->on = false;
1965
1966         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1967 }
1968
1969 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970                                            enum pipe pipe)
1971 {
1972         struct drm_device *dev = dev_priv->dev;
1973         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975         uint32_t reg, val, pipeconf_val;
1976
1977         /* PCH only available on ILK+ */
1978         BUG_ON(!HAS_PCH_SPLIT(dev));
1979
1980         /* Make sure PCH DPLL is enabled */
1981         assert_shared_dpll_enabled(dev_priv,
1982                                    intel_crtc_to_shared_dpll(intel_crtc));
1983
1984         /* FDI must be feeding us bits for PCH ports */
1985         assert_fdi_tx_enabled(dev_priv, pipe);
1986         assert_fdi_rx_enabled(dev_priv, pipe);
1987
1988         if (HAS_PCH_CPT(dev)) {
1989                 /* Workaround: Set the timing override bit before enabling the
1990                  * pch transcoder. */
1991                 reg = TRANS_CHICKEN2(pipe);
1992                 val = I915_READ(reg);
1993                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994                 I915_WRITE(reg, val);
1995         }
1996
1997         reg = PCH_TRANSCONF(pipe);
1998         val = I915_READ(reg);
1999         pipeconf_val = I915_READ(PIPECONF(pipe));
2000
2001         if (HAS_PCH_IBX(dev_priv->dev)) {
2002                 /*
2003                  * Make the BPC in transcoder be consistent with
2004                  * that in pipeconf reg. For HDMI we must use 8bpc
2005                  * here for both 8bpc and 12bpc.
2006                  */
2007                 val &= ~PIPECONF_BPC_MASK;
2008                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009                         val |= PIPECONF_8BPC;
2010                 else
2011                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2012         }
2013
2014         val &= ~TRANS_INTERLACE_MASK;
2015         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016                 if (HAS_PCH_IBX(dev_priv->dev) &&
2017                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018                         val |= TRANS_LEGACY_INTERLACED_ILK;
2019                 else
2020                         val |= TRANS_INTERLACED;
2021         else
2022                 val |= TRANS_PROGRESSIVE;
2023
2024         I915_WRITE(reg, val | TRANS_ENABLE);
2025         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 }
2028
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030                                       enum transcoder cpu_transcoder)
2031 {
2032         u32 val, pipeconf_val;
2033
2034         /* PCH only available on ILK+ */
2035         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2036
2037         /* FDI must be feeding us bits for PCH ports */
2038         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2040
2041         /* Workaround: set timing override bit. */
2042         val = I915_READ(_TRANSA_CHICKEN2);
2043         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044         I915_WRITE(_TRANSA_CHICKEN2, val);
2045
2046         val = TRANS_ENABLE;
2047         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2048
2049         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050             PIPECONF_INTERLACED_ILK)
2051                 val |= TRANS_INTERLACED;
2052         else
2053                 val |= TRANS_PROGRESSIVE;
2054
2055         I915_WRITE(LPT_TRANSCONF, val);
2056         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057                 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 }
2059
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061                                             enum pipe pipe)
2062 {
2063         struct drm_device *dev = dev_priv->dev;
2064         uint32_t reg, val;
2065
2066         /* FDI relies on the transcoder */
2067         assert_fdi_tx_disabled(dev_priv, pipe);
2068         assert_fdi_rx_disabled(dev_priv, pipe);
2069
2070         /* Ports must be off as well */
2071         assert_pch_ports_disabled(dev_priv, pipe);
2072
2073         reg = PCH_TRANSCONF(pipe);
2074         val = I915_READ(reg);
2075         val &= ~TRANS_ENABLE;
2076         I915_WRITE(reg, val);
2077         /* wait for PCH transcoder off, transcoder state */
2078         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2080
2081         if (!HAS_PCH_IBX(dev)) {
2082                 /* Workaround: Clear the timing override chicken bit again. */
2083                 reg = TRANS_CHICKEN2(pipe);
2084                 val = I915_READ(reg);
2085                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086                 I915_WRITE(reg, val);
2087         }
2088 }
2089
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2091 {
2092         u32 val;
2093
2094         val = I915_READ(LPT_TRANSCONF);
2095         val &= ~TRANS_ENABLE;
2096         I915_WRITE(LPT_TRANSCONF, val);
2097         /* wait for PCH transcoder off, transcoder state */
2098         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099                 DRM_ERROR("Failed to disable PCH transcoder\n");
2100
2101         /* Workaround: clear timing override bit. */
2102         val = I915_READ(_TRANSA_CHICKEN2);
2103         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104         I915_WRITE(_TRANSA_CHICKEN2, val);
2105 }
2106
2107 /**
2108  * intel_enable_pipe - enable a pipe, asserting requirements
2109  * @crtc: crtc responsible for the pipe
2110  *
2111  * Enable @crtc's pipe, making sure that various hardware specific requirements
2112  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113  */
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2115 {
2116         struct drm_device *dev = crtc->base.dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118         enum pipe pipe = crtc->pipe;
2119         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120                                                                       pipe);
2121         enum pipe pch_transcoder;
2122         int reg;
2123         u32 val;
2124
2125         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2126
2127         assert_planes_disabled(dev_priv, pipe);
2128         assert_cursor_disabled(dev_priv, pipe);
2129         assert_sprites_disabled(dev_priv, pipe);
2130
2131         if (HAS_PCH_LPT(dev_priv->dev))
2132                 pch_transcoder = TRANSCODER_A;
2133         else
2134                 pch_transcoder = pipe;
2135
2136         /*
2137          * A pipe without a PLL won't actually be able to drive bits from
2138          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2139          * need the check.
2140          */
2141         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2142                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2143                         assert_dsi_pll_enabled(dev_priv);
2144                 else
2145                         assert_pll_enabled(dev_priv, pipe);
2146         else {
2147                 if (crtc->config->has_pch_encoder) {
2148                         /* if driving the PCH, we need FDI enabled */
2149                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2150                         assert_fdi_tx_pll_enabled(dev_priv,
2151                                                   (enum pipe) cpu_transcoder);
2152                 }
2153                 /* FIXME: assert CPU port conditions for SNB+ */
2154         }
2155
2156         reg = PIPECONF(cpu_transcoder);
2157         val = I915_READ(reg);
2158         if (val & PIPECONF_ENABLE) {
2159                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2161                 return;
2162         }
2163
2164         I915_WRITE(reg, val | PIPECONF_ENABLE);
2165         POSTING_READ(reg);
2166 }
2167
2168 /**
2169  * intel_disable_pipe - disable a pipe, asserting requirements
2170  * @crtc: crtc whose pipes is to be disabled
2171  *
2172  * Disable the pipe of @crtc, making sure that various hardware
2173  * specific requirements are met, if applicable, e.g. plane
2174  * disabled, panel fitter off, etc.
2175  *
2176  * Will wait until the pipe has shut down before returning.
2177  */
2178 static void intel_disable_pipe(struct intel_crtc *crtc)
2179 {
2180         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2181         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2182         enum pipe pipe = crtc->pipe;
2183         int reg;
2184         u32 val;
2185
2186         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187
2188         /*
2189          * Make sure planes won't keep trying to pump pixels to us,
2190          * or we might hang the display.
2191          */
2192         assert_planes_disabled(dev_priv, pipe);
2193         assert_cursor_disabled(dev_priv, pipe);
2194         assert_sprites_disabled(dev_priv, pipe);
2195
2196         reg = PIPECONF(cpu_transcoder);
2197         val = I915_READ(reg);
2198         if ((val & PIPECONF_ENABLE) == 0)
2199                 return;
2200
2201         /*
2202          * Double wide has implications for planes
2203          * so best keep it disabled when not needed.
2204          */
2205         if (crtc->config->double_wide)
2206                 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208         /* Don't disable pipe or pipe PLLs if needed */
2209         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211                 val &= ~PIPECONF_ENABLE;
2212
2213         I915_WRITE(reg, val);
2214         if ((val & PIPECONF_ENABLE) == 0)
2215                 intel_wait_for_pipe_off(crtc);
2216 }
2217
2218 static bool need_vtd_wa(struct drm_device *dev)
2219 {
2220 #ifdef CONFIG_INTEL_IOMMU
2221         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2222                 return true;
2223 #endif
2224         return false;
2225 }
2226
2227 unsigned int
2228 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229                   uint64_t fb_format_modifier)
2230 {
2231         unsigned int tile_height;
2232         uint32_t pixel_bytes;
2233
2234         switch (fb_format_modifier) {
2235         case DRM_FORMAT_MOD_NONE:
2236                 tile_height = 1;
2237                 break;
2238         case I915_FORMAT_MOD_X_TILED:
2239                 tile_height = IS_GEN2(dev) ? 16 : 8;
2240                 break;
2241         case I915_FORMAT_MOD_Y_TILED:
2242                 tile_height = 32;
2243                 break;
2244         case I915_FORMAT_MOD_Yf_TILED:
2245                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246                 switch (pixel_bytes) {
2247                 default:
2248                 case 1:
2249                         tile_height = 64;
2250                         break;
2251                 case 2:
2252                 case 4:
2253                         tile_height = 32;
2254                         break;
2255                 case 8:
2256                         tile_height = 16;
2257                         break;
2258                 case 16:
2259                         WARN_ONCE(1,
2260                                   "128-bit pixels are not supported for display!");
2261                         tile_height = 16;
2262                         break;
2263                 }
2264                 break;
2265         default:
2266                 MISSING_CASE(fb_format_modifier);
2267                 tile_height = 1;
2268                 break;
2269         }
2270
2271         return tile_height;
2272 }
2273
2274 unsigned int
2275 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276                       uint32_t pixel_format, uint64_t fb_format_modifier)
2277 {
2278         return ALIGN(height, intel_tile_height(dev, pixel_format,
2279                                                fb_format_modifier));
2280 }
2281
2282 static int
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284                         const struct drm_plane_state *plane_state)
2285 {
2286         struct intel_rotation_info *info = &view->rotation_info;
2287         unsigned int tile_height, tile_pitch;
2288
2289         *view = i915_ggtt_view_normal;
2290
2291         if (!plane_state)
2292                 return 0;
2293
2294         if (!intel_rotation_90_or_270(plane_state->rotation))
2295                 return 0;
2296
2297         *view = i915_ggtt_view_rotated;
2298
2299         info->height = fb->height;
2300         info->pixel_format = fb->pixel_format;
2301         info->pitch = fb->pitches[0];
2302         info->fb_modifier = fb->modifier[0];
2303
2304         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305                                         fb->modifier[0]);
2306         tile_pitch = PAGE_SIZE / tile_height;
2307         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2310
2311         return 0;
2312 }
2313
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315 {
2316         if (INTEL_INFO(dev_priv)->gen >= 9)
2317                 return 256 * 1024;
2318         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319                  IS_VALLEYVIEW(dev_priv))
2320                 return 128 * 1024;
2321         else if (INTEL_INFO(dev_priv)->gen >= 4)
2322                 return 4 * 1024;
2323         else
2324                 return 0;
2325 }
2326
2327 int
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329                            struct drm_framebuffer *fb,
2330                            const struct drm_plane_state *plane_state,
2331                            struct intel_engine_cs *pipelined,
2332                            struct drm_i915_gem_request **pipelined_request)
2333 {
2334         struct drm_device *dev = fb->dev;
2335         struct drm_i915_private *dev_priv = dev->dev_private;
2336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337         struct i915_ggtt_view view;
2338         u32 alignment;
2339         int ret;
2340
2341         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343         switch (fb->modifier[0]) {
2344         case DRM_FORMAT_MOD_NONE:
2345                 alignment = intel_linear_alignment(dev_priv);
2346                 break;
2347         case I915_FORMAT_MOD_X_TILED:
2348                 if (INTEL_INFO(dev)->gen >= 9)
2349                         alignment = 256 * 1024;
2350                 else {
2351                         /* pin() will align the object as required by fence */
2352                         alignment = 0;
2353                 }
2354                 break;
2355         case I915_FORMAT_MOD_Y_TILED:
2356         case I915_FORMAT_MOD_Yf_TILED:
2357                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358                           "Y tiling bo slipped through, driver bug!\n"))
2359                         return -EINVAL;
2360                 alignment = 1 * 1024 * 1024;
2361                 break;
2362         default:
2363                 MISSING_CASE(fb->modifier[0]);
2364                 return -EINVAL;
2365         }
2366
2367         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2368         if (ret)
2369                 return ret;
2370
2371         /* Note that the w/a also requires 64 PTE of padding following the
2372          * bo. We currently fill all unused PTE with the shadow page and so
2373          * we should always have valid PTE following the scanout preventing
2374          * the VT-d warning.
2375          */
2376         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377                 alignment = 256 * 1024;
2378
2379         /*
2380          * Global gtt pte registers are special registers which actually forward
2381          * writes to a chunk of system memory. Which means that there is no risk
2382          * that the register values disappear as soon as we call
2383          * intel_runtime_pm_put(), so it is correct to wrap only the
2384          * pin/unpin/fence and not more.
2385          */
2386         intel_runtime_pm_get(dev_priv);
2387
2388         dev_priv->mm.interruptible = false;
2389         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2390                                                    pipelined_request, &view);
2391         if (ret)
2392                 goto err_interruptible;
2393
2394         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395          * fence, whereas 965+ only requires a fence if using
2396          * framebuffer compression.  For simplicity, we always install
2397          * a fence as the cost is not that onerous.
2398          */
2399         ret = i915_gem_object_get_fence(obj);
2400         if (ret)
2401                 goto err_unpin;
2402
2403         i915_gem_object_pin_fence(obj);
2404
2405         dev_priv->mm.interruptible = true;
2406         intel_runtime_pm_put(dev_priv);
2407         return 0;
2408
2409 err_unpin:
2410         i915_gem_object_unpin_from_display_plane(obj, &view);
2411 err_interruptible:
2412         dev_priv->mm.interruptible = true;
2413         intel_runtime_pm_put(dev_priv);
2414         return ret;
2415 }
2416
2417 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2418                                const struct drm_plane_state *plane_state)
2419 {
2420         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2421         struct i915_ggtt_view view;
2422         int ret;
2423
2424         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2425
2426         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2427         WARN_ONCE(ret, "Couldn't get view from plane state!");
2428
2429         i915_gem_object_unpin_fence(obj);
2430         i915_gem_object_unpin_from_display_plane(obj, &view);
2431 }
2432
2433 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2434  * is assumed to be a power-of-two. */
2435 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2436                                              int *x, int *y,
2437                                              unsigned int tiling_mode,
2438                                              unsigned int cpp,
2439                                              unsigned int pitch)
2440 {
2441         if (tiling_mode != I915_TILING_NONE) {
2442                 unsigned int tile_rows, tiles;
2443
2444                 tile_rows = *y / 8;
2445                 *y %= 8;
2446
2447                 tiles = *x / (512/cpp);
2448                 *x %= 512/cpp;
2449
2450                 return tile_rows * pitch * 8 + tiles * 4096;
2451         } else {
2452                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2453                 unsigned int offset;
2454
2455                 offset = *y * pitch + *x * cpp;
2456                 *y = (offset & alignment) / pitch;
2457                 *x = ((offset & alignment) - *y * pitch) / cpp;
2458                 return offset & ~alignment;
2459         }
2460 }
2461
2462 static int i9xx_format_to_fourcc(int format)
2463 {
2464         switch (format) {
2465         case DISPPLANE_8BPP:
2466                 return DRM_FORMAT_C8;
2467         case DISPPLANE_BGRX555:
2468                 return DRM_FORMAT_XRGB1555;
2469         case DISPPLANE_BGRX565:
2470                 return DRM_FORMAT_RGB565;
2471         default:
2472         case DISPPLANE_BGRX888:
2473                 return DRM_FORMAT_XRGB8888;
2474         case DISPPLANE_RGBX888:
2475                 return DRM_FORMAT_XBGR8888;
2476         case DISPPLANE_BGRX101010:
2477                 return DRM_FORMAT_XRGB2101010;
2478         case DISPPLANE_RGBX101010:
2479                 return DRM_FORMAT_XBGR2101010;
2480         }
2481 }
2482
2483 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484 {
2485         switch (format) {
2486         case PLANE_CTL_FORMAT_RGB_565:
2487                 return DRM_FORMAT_RGB565;
2488         default:
2489         case PLANE_CTL_FORMAT_XRGB_8888:
2490                 if (rgb_order) {
2491                         if (alpha)
2492                                 return DRM_FORMAT_ABGR8888;
2493                         else
2494                                 return DRM_FORMAT_XBGR8888;
2495                 } else {
2496                         if (alpha)
2497                                 return DRM_FORMAT_ARGB8888;
2498                         else
2499                                 return DRM_FORMAT_XRGB8888;
2500                 }
2501         case PLANE_CTL_FORMAT_XRGB_2101010:
2502                 if (rgb_order)
2503                         return DRM_FORMAT_XBGR2101010;
2504                 else
2505                         return DRM_FORMAT_XRGB2101010;
2506         }
2507 }
2508
2509 static bool
2510 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511                               struct intel_initial_plane_config *plane_config)
2512 {
2513         struct drm_device *dev = crtc->base.dev;
2514         struct drm_i915_gem_object *obj = NULL;
2515         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2516         struct drm_framebuffer *fb = &plane_config->fb->base;
2517         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519                                     PAGE_SIZE);
2520
2521         size_aligned -= base_aligned;
2522
2523         if (plane_config->size == 0)
2524                 return false;
2525
2526         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527                                                              base_aligned,
2528                                                              base_aligned,
2529                                                              size_aligned);
2530         if (!obj)
2531                 return false;
2532
2533         obj->tiling_mode = plane_config->tiling;
2534         if (obj->tiling_mode == I915_TILING_X)
2535                 obj->stride = fb->pitches[0];
2536
2537         mode_cmd.pixel_format = fb->pixel_format;
2538         mode_cmd.width = fb->width;
2539         mode_cmd.height = fb->height;
2540         mode_cmd.pitches[0] = fb->pitches[0];
2541         mode_cmd.modifier[0] = fb->modifier[0];
2542         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2543
2544         mutex_lock(&dev->struct_mutex);
2545         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2546                                    &mode_cmd, obj)) {
2547                 DRM_DEBUG_KMS("intel fb init failed\n");
2548                 goto out_unref_obj;
2549         }
2550         mutex_unlock(&dev->struct_mutex);
2551
2552         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2553         return true;
2554
2555 out_unref_obj:
2556         drm_gem_object_unreference(&obj->base);
2557         mutex_unlock(&dev->struct_mutex);
2558         return false;
2559 }
2560
2561 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2562 static void
2563 update_state_fb(struct drm_plane *plane)
2564 {
2565         if (plane->fb == plane->state->fb)
2566                 return;
2567
2568         if (plane->state->fb)
2569                 drm_framebuffer_unreference(plane->state->fb);
2570         plane->state->fb = plane->fb;
2571         if (plane->state->fb)
2572                 drm_framebuffer_reference(plane->state->fb);
2573 }
2574
2575 static void
2576 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577                              struct intel_initial_plane_config *plane_config)
2578 {
2579         struct drm_device *dev = intel_crtc->base.dev;
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581         struct drm_crtc *c;
2582         struct intel_crtc *i;
2583         struct drm_i915_gem_object *obj;
2584         struct drm_plane *primary = intel_crtc->base.primary;
2585         struct drm_plane_state *plane_state = primary->state;
2586         struct drm_framebuffer *fb;
2587
2588         if (!plane_config->fb)
2589                 return;
2590
2591         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2592                 fb = &plane_config->fb->base;
2593                 goto valid_fb;
2594         }
2595
2596         kfree(plane_config->fb);
2597
2598         /*
2599          * Failed to alloc the obj, check to see if we should share
2600          * an fb with another CRTC instead
2601          */
2602         for_each_crtc(dev, c) {
2603                 i = to_intel_crtc(c);
2604
2605                 if (c == &intel_crtc->base)
2606                         continue;
2607
2608                 if (!i->active)
2609                         continue;
2610
2611                 fb = c->primary->fb;
2612                 if (!fb)
2613                         continue;
2614
2615                 obj = intel_fb_obj(fb);
2616                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2617                         drm_framebuffer_reference(fb);
2618                         goto valid_fb;
2619                 }
2620         }
2621
2622         return;
2623
2624 valid_fb:
2625         plane_state->src_x = plane_state->src_y = 0;
2626         plane_state->src_w = fb->width << 16;
2627         plane_state->src_h = fb->height << 16;
2628
2629         plane_state->crtc_x = plane_state->src_y = 0;
2630         plane_state->crtc_w = fb->width;
2631         plane_state->crtc_h = fb->height;
2632
2633         obj = intel_fb_obj(fb);
2634         if (obj->tiling_mode != I915_TILING_NONE)
2635                 dev_priv->preserve_bios_swizzle = true;
2636
2637         drm_framebuffer_reference(fb);
2638         primary->fb = primary->state->fb = fb;
2639         primary->crtc = primary->state->crtc = &intel_crtc->base;
2640         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2641         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2642 }
2643
2644 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2645                                       struct drm_framebuffer *fb,
2646                                       int x, int y)
2647 {
2648         struct drm_device *dev = crtc->dev;
2649         struct drm_i915_private *dev_priv = dev->dev_private;
2650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651         struct drm_plane *primary = crtc->primary;
2652         bool visible = to_intel_plane_state(primary->state)->visible;
2653         struct drm_i915_gem_object *obj;
2654         int plane = intel_crtc->plane;
2655         unsigned long linear_offset;
2656         u32 dspcntr;
2657         u32 reg = DSPCNTR(plane);
2658         int pixel_size;
2659
2660         if (!visible || !fb) {
2661                 I915_WRITE(reg, 0);
2662                 if (INTEL_INFO(dev)->gen >= 4)
2663                         I915_WRITE(DSPSURF(plane), 0);
2664                 else
2665                         I915_WRITE(DSPADDR(plane), 0);
2666                 POSTING_READ(reg);
2667                 return;
2668         }
2669
2670         obj = intel_fb_obj(fb);
2671         if (WARN_ON(obj == NULL))
2672                 return;
2673
2674         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2675
2676         dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678         dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680         if (INTEL_INFO(dev)->gen < 4) {
2681                 if (intel_crtc->pipe == PIPE_B)
2682                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684                 /* pipesrc and dspsize control the size that is scaled from,
2685                  * which should always be the user's requested size.
2686                  */
2687                 I915_WRITE(DSPSIZE(plane),
2688                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689                            (intel_crtc->config->pipe_src_w - 1));
2690                 I915_WRITE(DSPPOS(plane), 0);
2691         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692                 I915_WRITE(PRIMSIZE(plane),
2693                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694                            (intel_crtc->config->pipe_src_w - 1));
2695                 I915_WRITE(PRIMPOS(plane), 0);
2696                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697         }
2698
2699         switch (fb->pixel_format) {
2700         case DRM_FORMAT_C8:
2701                 dspcntr |= DISPPLANE_8BPP;
2702                 break;
2703         case DRM_FORMAT_XRGB1555:
2704                 dspcntr |= DISPPLANE_BGRX555;
2705                 break;
2706         case DRM_FORMAT_RGB565:
2707                 dspcntr |= DISPPLANE_BGRX565;
2708                 break;
2709         case DRM_FORMAT_XRGB8888:
2710                 dspcntr |= DISPPLANE_BGRX888;
2711                 break;
2712         case DRM_FORMAT_XBGR8888:
2713                 dspcntr |= DISPPLANE_RGBX888;
2714                 break;
2715         case DRM_FORMAT_XRGB2101010:
2716                 dspcntr |= DISPPLANE_BGRX101010;
2717                 break;
2718         case DRM_FORMAT_XBGR2101010:
2719                 dspcntr |= DISPPLANE_RGBX101010;
2720                 break;
2721         default:
2722                 BUG();
2723         }
2724
2725         if (INTEL_INFO(dev)->gen >= 4 &&
2726             obj->tiling_mode != I915_TILING_NONE)
2727                 dspcntr |= DISPPLANE_TILED;
2728
2729         if (IS_G4X(dev))
2730                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732         linear_offset = y * fb->pitches[0] + x * pixel_size;
2733
2734         if (INTEL_INFO(dev)->gen >= 4) {
2735                 intel_crtc->dspaddr_offset =
2736                         intel_gen4_compute_page_offset(dev_priv,
2737                                                        &x, &y, obj->tiling_mode,
2738                                                        pixel_size,
2739                                                        fb->pitches[0]);
2740                 linear_offset -= intel_crtc->dspaddr_offset;
2741         } else {
2742                 intel_crtc->dspaddr_offset = linear_offset;
2743         }
2744
2745         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2746                 dspcntr |= DISPPLANE_ROTATE_180;
2747
2748                 x += (intel_crtc->config->pipe_src_w - 1);
2749                 y += (intel_crtc->config->pipe_src_h - 1);
2750
2751                 /* Finding the last pixel of the last line of the display
2752                 data and adding to linear_offset*/
2753                 linear_offset +=
2754                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2756         }
2757
2758         I915_WRITE(reg, dspcntr);
2759
2760         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2761         if (INTEL_INFO(dev)->gen >= 4) {
2762                 I915_WRITE(DSPSURF(plane),
2763                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2764                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2765                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2766         } else
2767                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2768         POSTING_READ(reg);
2769 }
2770
2771 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2772                                           struct drm_framebuffer *fb,
2773                                           int x, int y)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         struct drm_plane *primary = crtc->primary;
2779         bool visible = to_intel_plane_state(primary->state)->visible;
2780         struct drm_i915_gem_object *obj;
2781         int plane = intel_crtc->plane;
2782         unsigned long linear_offset;
2783         u32 dspcntr;
2784         u32 reg = DSPCNTR(plane);
2785         int pixel_size;
2786
2787         if (!visible || !fb) {
2788                 I915_WRITE(reg, 0);
2789                 I915_WRITE(DSPSURF(plane), 0);
2790                 POSTING_READ(reg);
2791                 return;
2792         }
2793
2794         obj = intel_fb_obj(fb);
2795         if (WARN_ON(obj == NULL))
2796                 return;
2797
2798         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2799
2800         dspcntr = DISPPLANE_GAMMA_ENABLE;
2801
2802         dspcntr |= DISPLAY_PLANE_ENABLE;
2803
2804         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2805                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2806
2807         switch (fb->pixel_format) {
2808         case DRM_FORMAT_C8:
2809                 dspcntr |= DISPPLANE_8BPP;
2810                 break;
2811         case DRM_FORMAT_RGB565:
2812                 dspcntr |= DISPPLANE_BGRX565;
2813                 break;
2814         case DRM_FORMAT_XRGB8888:
2815                 dspcntr |= DISPPLANE_BGRX888;
2816                 break;
2817         case DRM_FORMAT_XBGR8888:
2818                 dspcntr |= DISPPLANE_RGBX888;
2819                 break;
2820         case DRM_FORMAT_XRGB2101010:
2821                 dspcntr |= DISPPLANE_BGRX101010;
2822                 break;
2823         case DRM_FORMAT_XBGR2101010:
2824                 dspcntr |= DISPPLANE_RGBX101010;
2825                 break;
2826         default:
2827                 BUG();
2828         }
2829
2830         if (obj->tiling_mode != I915_TILING_NONE)
2831                 dspcntr |= DISPPLANE_TILED;
2832
2833         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2834                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2835
2836         linear_offset = y * fb->pitches[0] + x * pixel_size;
2837         intel_crtc->dspaddr_offset =
2838                 intel_gen4_compute_page_offset(dev_priv,
2839                                                &x, &y, obj->tiling_mode,
2840                                                pixel_size,
2841                                                fb->pitches[0]);
2842         linear_offset -= intel_crtc->dspaddr_offset;
2843         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2844                 dspcntr |= DISPPLANE_ROTATE_180;
2845
2846                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2847                         x += (intel_crtc->config->pipe_src_w - 1);
2848                         y += (intel_crtc->config->pipe_src_h - 1);
2849
2850                         /* Finding the last pixel of the last line of the display
2851                         data and adding to linear_offset*/
2852                         linear_offset +=
2853                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2854                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2855                 }
2856         }
2857
2858         I915_WRITE(reg, dspcntr);
2859
2860         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2861         I915_WRITE(DSPSURF(plane),
2862                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2863         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2864                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2865         } else {
2866                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2867                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2868         }
2869         POSTING_READ(reg);
2870 }
2871
2872 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2873                               uint32_t pixel_format)
2874 {
2875         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2876
2877         /*
2878          * The stride is either expressed as a multiple of 64 bytes
2879          * chunks for linear buffers or in number of tiles for tiled
2880          * buffers.
2881          */
2882         switch (fb_modifier) {
2883         case DRM_FORMAT_MOD_NONE:
2884                 return 64;
2885         case I915_FORMAT_MOD_X_TILED:
2886                 if (INTEL_INFO(dev)->gen == 2)
2887                         return 128;
2888                 return 512;
2889         case I915_FORMAT_MOD_Y_TILED:
2890                 /* No need to check for old gens and Y tiling since this is
2891                  * about the display engine and those will be blocked before
2892                  * we get here.
2893                  */
2894                 return 128;
2895         case I915_FORMAT_MOD_Yf_TILED:
2896                 if (bits_per_pixel == 8)
2897                         return 64;
2898                 else
2899                         return 128;
2900         default:
2901                 MISSING_CASE(fb_modifier);
2902                 return 64;
2903         }
2904 }
2905
2906 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2907                                      struct drm_i915_gem_object *obj)
2908 {
2909         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2910
2911         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2912                 view = &i915_ggtt_view_rotated;
2913
2914         return i915_gem_obj_ggtt_offset_view(obj, view);
2915 }
2916
2917 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2918 {
2919         struct drm_device *dev = intel_crtc->base.dev;
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921
2922         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2923         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2924         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2925         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2926                 intel_crtc->base.base.id, intel_crtc->pipe, id);
2927 }
2928
2929 /*
2930  * This function detaches (aka. unbinds) unused scalers in hardware
2931  */
2932 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2933 {
2934         struct intel_crtc_scaler_state *scaler_state;
2935         int i;
2936
2937         scaler_state = &intel_crtc->config->scaler_state;
2938
2939         /* loop through and disable scalers that aren't in use */
2940         for (i = 0; i < intel_crtc->num_scalers; i++) {
2941                 if (!scaler_state->scalers[i].in_use)
2942                         skl_detach_scaler(intel_crtc, i);
2943         }
2944 }
2945
2946 u32 skl_plane_ctl_format(uint32_t pixel_format)
2947 {
2948         switch (pixel_format) {
2949         case DRM_FORMAT_C8:
2950                 return PLANE_CTL_FORMAT_INDEXED;
2951         case DRM_FORMAT_RGB565:
2952                 return PLANE_CTL_FORMAT_RGB_565;
2953         case DRM_FORMAT_XBGR8888:
2954                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2955         case DRM_FORMAT_XRGB8888:
2956                 return PLANE_CTL_FORMAT_XRGB_8888;
2957         /*
2958          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2959          * to be already pre-multiplied. We need to add a knob (or a different
2960          * DRM_FORMAT) for user-space to configure that.
2961          */
2962         case DRM_FORMAT_ABGR8888:
2963                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2964                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2965         case DRM_FORMAT_ARGB8888:
2966                 return PLANE_CTL_FORMAT_XRGB_8888 |
2967                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2968         case DRM_FORMAT_XRGB2101010:
2969                 return PLANE_CTL_FORMAT_XRGB_2101010;
2970         case DRM_FORMAT_XBGR2101010:
2971                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2972         case DRM_FORMAT_YUYV:
2973                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2974         case DRM_FORMAT_YVYU:
2975                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2976         case DRM_FORMAT_UYVY:
2977                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2978         case DRM_FORMAT_VYUY:
2979                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2980         default:
2981                 MISSING_CASE(pixel_format);
2982         }
2983
2984         return 0;
2985 }
2986
2987 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2988 {
2989         switch (fb_modifier) {
2990         case DRM_FORMAT_MOD_NONE:
2991                 break;
2992         case I915_FORMAT_MOD_X_TILED:
2993                 return PLANE_CTL_TILED_X;
2994         case I915_FORMAT_MOD_Y_TILED:
2995                 return PLANE_CTL_TILED_Y;
2996         case I915_FORMAT_MOD_Yf_TILED:
2997                 return PLANE_CTL_TILED_YF;
2998         default:
2999                 MISSING_CASE(fb_modifier);
3000         }
3001
3002         return 0;
3003 }
3004
3005 u32 skl_plane_ctl_rotation(unsigned int rotation)
3006 {
3007         switch (rotation) {
3008         case BIT(DRM_ROTATE_0):
3009                 break;
3010         /*
3011          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3012          * while i915 HW rotation is clockwise, thats why this swapping.
3013          */
3014         case BIT(DRM_ROTATE_90):
3015                 return PLANE_CTL_ROTATE_270;
3016         case BIT(DRM_ROTATE_180):
3017                 return PLANE_CTL_ROTATE_180;
3018         case BIT(DRM_ROTATE_270):
3019                 return PLANE_CTL_ROTATE_90;
3020         default:
3021                 MISSING_CASE(rotation);
3022         }
3023
3024         return 0;
3025 }
3026
3027 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3028                                          struct drm_framebuffer *fb,
3029                                          int x, int y)
3030 {
3031         struct drm_device *dev = crtc->dev;
3032         struct drm_i915_private *dev_priv = dev->dev_private;
3033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034         struct drm_plane *plane = crtc->primary;
3035         bool visible = to_intel_plane_state(plane->state)->visible;
3036         struct drm_i915_gem_object *obj;
3037         int pipe = intel_crtc->pipe;
3038         u32 plane_ctl, stride_div, stride;
3039         u32 tile_height, plane_offset, plane_size;
3040         unsigned int rotation;
3041         int x_offset, y_offset;
3042         unsigned long surf_addr;
3043         struct intel_crtc_state *crtc_state = intel_crtc->config;
3044         struct intel_plane_state *plane_state;
3045         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3046         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3047         int scaler_id = -1;
3048
3049         plane_state = to_intel_plane_state(plane->state);
3050
3051         if (!visible || !fb) {
3052                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3053                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3054                 POSTING_READ(PLANE_CTL(pipe, 0));
3055                 return;
3056         }
3057
3058         plane_ctl = PLANE_CTL_ENABLE |
3059                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3060                     PLANE_CTL_PIPE_CSC_ENABLE;
3061
3062         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3063         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3064         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3065
3066         rotation = plane->state->rotation;
3067         plane_ctl |= skl_plane_ctl_rotation(rotation);
3068
3069         obj = intel_fb_obj(fb);
3070         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3071                                                fb->pixel_format);
3072         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3073
3074         /*
3075          * FIXME: intel_plane_state->src, dst aren't set when transitional
3076          * update_plane helpers are called from legacy paths.
3077          * Once full atomic crtc is available, below check can be avoided.
3078          */
3079         if (drm_rect_width(&plane_state->src)) {
3080                 scaler_id = plane_state->scaler_id;
3081                 src_x = plane_state->src.x1 >> 16;
3082                 src_y = plane_state->src.y1 >> 16;
3083                 src_w = drm_rect_width(&plane_state->src) >> 16;
3084                 src_h = drm_rect_height(&plane_state->src) >> 16;
3085                 dst_x = plane_state->dst.x1;
3086                 dst_y = plane_state->dst.y1;
3087                 dst_w = drm_rect_width(&plane_state->dst);
3088                 dst_h = drm_rect_height(&plane_state->dst);
3089
3090                 WARN_ON(x != src_x || y != src_y);
3091         } else {
3092                 src_w = intel_crtc->config->pipe_src_w;
3093                 src_h = intel_crtc->config->pipe_src_h;
3094         }
3095
3096         if (intel_rotation_90_or_270(rotation)) {
3097                 /* stride = Surface height in tiles */
3098                 tile_height = intel_tile_height(dev, fb->pixel_format,
3099                                                 fb->modifier[0]);
3100                 stride = DIV_ROUND_UP(fb->height, tile_height);
3101                 x_offset = stride * tile_height - y - src_h;
3102                 y_offset = x;
3103                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3104         } else {
3105                 stride = fb->pitches[0] / stride_div;
3106                 x_offset = x;
3107                 y_offset = y;
3108                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3109         }
3110         plane_offset = y_offset << 16 | x_offset;
3111
3112         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3113         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3114         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3115         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3116
3117         if (scaler_id >= 0) {
3118                 uint32_t ps_ctrl = 0;
3119
3120                 WARN_ON(!dst_w || !dst_h);
3121                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3122                         crtc_state->scaler_state.scalers[scaler_id].mode;
3123                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3124                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3125                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3126                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3127                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3128         } else {
3129                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3130         }
3131
3132         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3133
3134         POSTING_READ(PLANE_SURF(pipe, 0));
3135 }
3136
3137 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3138 static int
3139 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3140                            int x, int y, enum mode_set_atomic state)
3141 {
3142         struct drm_device *dev = crtc->dev;
3143         struct drm_i915_private *dev_priv = dev->dev_private;
3144
3145         if (dev_priv->fbc.disable_fbc)
3146                 dev_priv->fbc.disable_fbc(dev_priv);
3147
3148         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3149
3150         return 0;
3151 }
3152
3153 static void intel_complete_page_flips(struct drm_device *dev)
3154 {
3155         struct drm_crtc *crtc;
3156
3157         for_each_crtc(dev, crtc) {
3158                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159                 enum plane plane = intel_crtc->plane;
3160
3161                 intel_prepare_page_flip(dev, plane);
3162                 intel_finish_page_flip_plane(dev, plane);
3163         }
3164 }
3165
3166 static void intel_update_primary_planes(struct drm_device *dev)
3167 {
3168         struct drm_i915_private *dev_priv = dev->dev_private;
3169         struct drm_crtc *crtc;
3170
3171         for_each_crtc(dev, crtc) {
3172                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173
3174                 drm_modeset_lock(&crtc->mutex, NULL);
3175                 /*
3176                  * FIXME: Once we have proper support for primary planes (and
3177                  * disabling them without disabling the entire crtc) allow again
3178                  * a NULL crtc->primary->fb.
3179                  */
3180                 if (intel_crtc->active && crtc->primary->fb)
3181                         dev_priv->display.update_primary_plane(crtc,
3182                                                                crtc->primary->fb,
3183                                                                crtc->x,
3184                                                                crtc->y);
3185                 drm_modeset_unlock(&crtc->mutex);
3186         }
3187 }
3188
3189 void intel_prepare_reset(struct drm_device *dev)
3190 {
3191         /* no reset support for gen2 */
3192         if (IS_GEN2(dev))
3193                 return;
3194
3195         /* reset doesn't touch the display */
3196         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3197                 return;
3198
3199         drm_modeset_lock_all(dev);
3200         /*
3201          * Disabling the crtcs gracefully seems nicer. Also the
3202          * g33 docs say we should at least disable all the planes.
3203          */
3204         intel_display_suspend(dev);
3205 }
3206
3207 void intel_finish_reset(struct drm_device *dev)
3208 {
3209         struct drm_i915_private *dev_priv = to_i915(dev);
3210
3211         /*
3212          * Flips in the rings will be nuked by the reset,
3213          * so complete all pending flips so that user space
3214          * will get its events and not get stuck.
3215          */
3216         intel_complete_page_flips(dev);
3217
3218         /* no reset support for gen2 */
3219         if (IS_GEN2(dev))
3220                 return;
3221
3222         /* reset doesn't touch the display */
3223         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3224                 /*
3225                  * Flips in the rings have been nuked by the reset,
3226                  * so update the base address of all primary
3227                  * planes to the the last fb to make sure we're
3228                  * showing the correct fb after a reset.
3229                  */
3230                 intel_update_primary_planes(dev);
3231                 return;
3232         }
3233
3234         /*
3235          * The display has been reset as well,
3236          * so need a full re-initialization.
3237          */
3238         intel_runtime_pm_disable_interrupts(dev_priv);
3239         intel_runtime_pm_enable_interrupts(dev_priv);
3240
3241         intel_modeset_init_hw(dev);
3242
3243         spin_lock_irq(&dev_priv->irq_lock);
3244         if (dev_priv->display.hpd_irq_setup)
3245                 dev_priv->display.hpd_irq_setup(dev);
3246         spin_unlock_irq(&dev_priv->irq_lock);
3247
3248         intel_display_resume(dev);
3249
3250         intel_hpd_init(dev_priv);
3251
3252         drm_modeset_unlock_all(dev);
3253 }
3254
3255 static void
3256 intel_finish_fb(struct drm_framebuffer *old_fb)
3257 {
3258         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3259         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3260         bool was_interruptible = dev_priv->mm.interruptible;
3261         int ret;
3262
3263         /* Big Hammer, we also need to ensure that any pending
3264          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3265          * current scanout is retired before unpinning the old
3266          * framebuffer. Note that we rely on userspace rendering
3267          * into the buffer attached to the pipe they are waiting
3268          * on. If not, userspace generates a GPU hang with IPEHR
3269          * point to the MI_WAIT_FOR_EVENT.
3270          *
3271          * This should only fail upon a hung GPU, in which case we
3272          * can safely continue.
3273          */
3274         dev_priv->mm.interruptible = false;
3275         ret = i915_gem_object_wait_rendering(obj, true);
3276         dev_priv->mm.interruptible = was_interruptible;
3277
3278         WARN_ON(ret);
3279 }
3280
3281 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3282 {
3283         struct drm_device *dev = crtc->dev;
3284         struct drm_i915_private *dev_priv = dev->dev_private;
3285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286         bool pending;
3287
3288         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3289             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3290                 return false;
3291
3292         spin_lock_irq(&dev->event_lock);
3293         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3294         spin_unlock_irq(&dev->event_lock);
3295
3296         return pending;
3297 }
3298
3299 static void intel_update_pipe_size(struct intel_crtc *crtc)
3300 {
3301         struct drm_device *dev = crtc->base.dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         const struct drm_display_mode *adjusted_mode;
3304
3305         if (!i915.fastboot)
3306                 return;
3307
3308         /*
3309          * Update pipe size and adjust fitter if needed: the reason for this is
3310          * that in compute_mode_changes we check the native mode (not the pfit
3311          * mode) to see if we can flip rather than do a full mode set. In the
3312          * fastboot case, we'll flip, but if we don't update the pipesrc and
3313          * pfit state, we'll end up with a big fb scanned out into the wrong
3314          * sized surface.
3315          *
3316          * To fix this properly, we need to hoist the checks up into
3317          * compute_mode_changes (or above), check the actual pfit state and
3318          * whether the platform allows pfit disable with pipe active, and only
3319          * then update the pipesrc and pfit state, even on the flip path.
3320          */
3321
3322         adjusted_mode = &crtc->config->base.adjusted_mode;
3323
3324         I915_WRITE(PIPESRC(crtc->pipe),
3325                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3326                    (adjusted_mode->crtc_vdisplay - 1));
3327         if (!crtc->config->pch_pfit.enabled &&
3328             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3329              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3330                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3331                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3332                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3333         }
3334         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3335         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3336 }
3337
3338 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3339 {
3340         struct drm_device *dev = crtc->dev;
3341         struct drm_i915_private *dev_priv = dev->dev_private;
3342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343         int pipe = intel_crtc->pipe;
3344         u32 reg, temp;
3345
3346         /* enable normal train */
3347         reg = FDI_TX_CTL(pipe);
3348         temp = I915_READ(reg);
3349         if (IS_IVYBRIDGE(dev)) {
3350                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3351                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3352         } else {
3353                 temp &= ~FDI_LINK_TRAIN_NONE;
3354                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3355         }
3356         I915_WRITE(reg, temp);
3357
3358         reg = FDI_RX_CTL(pipe);
3359         temp = I915_READ(reg);
3360         if (HAS_PCH_CPT(dev)) {
3361                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3362                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3363         } else {
3364                 temp &= ~FDI_LINK_TRAIN_NONE;
3365                 temp |= FDI_LINK_TRAIN_NONE;
3366         }
3367         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3368
3369         /* wait one idle pattern time */
3370         POSTING_READ(reg);
3371         udelay(1000);
3372
3373         /* IVB wants error correction enabled */
3374         if (IS_IVYBRIDGE(dev))
3375                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3376                            FDI_FE_ERRC_ENABLE);
3377 }
3378
3379 /* The FDI link training functions for ILK/Ibexpeak. */
3380 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3381 {
3382         struct drm_device *dev = crtc->dev;
3383         struct drm_i915_private *dev_priv = dev->dev_private;
3384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385         int pipe = intel_crtc->pipe;
3386         u32 reg, temp, tries;
3387
3388         /* FDI needs bits from pipe first */
3389         assert_pipe_enabled(dev_priv, pipe);
3390
3391         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3392            for train result */
3393         reg = FDI_RX_IMR(pipe);
3394         temp = I915_READ(reg);
3395         temp &= ~FDI_RX_SYMBOL_LOCK;
3396         temp &= ~FDI_RX_BIT_LOCK;
3397         I915_WRITE(reg, temp);
3398         I915_READ(reg);
3399         udelay(150);
3400
3401         /* enable CPU FDI TX and PCH FDI RX */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3405         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3406         temp &= ~FDI_LINK_TRAIN_NONE;
3407         temp |= FDI_LINK_TRAIN_PATTERN_1;
3408         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3409
3410         reg = FDI_RX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         temp &= ~FDI_LINK_TRAIN_NONE;
3413         temp |= FDI_LINK_TRAIN_PATTERN_1;
3414         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3415
3416         POSTING_READ(reg);
3417         udelay(150);
3418
3419         /* Ironlake workaround, enable clock pointer after FDI enable*/
3420         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3421         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3422                    FDI_RX_PHASE_SYNC_POINTER_EN);
3423
3424         reg = FDI_RX_IIR(pipe);
3425         for (tries = 0; tries < 5; tries++) {
3426                 temp = I915_READ(reg);
3427                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428
3429                 if ((temp & FDI_RX_BIT_LOCK)) {
3430                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3431                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3432                         break;
3433                 }
3434         }
3435         if (tries == 5)
3436                 DRM_ERROR("FDI train 1 fail!\n");
3437
3438         /* Train 2 */
3439         reg = FDI_TX_CTL(pipe);
3440         temp = I915_READ(reg);
3441         temp &= ~FDI_LINK_TRAIN_NONE;
3442         temp |= FDI_LINK_TRAIN_PATTERN_2;
3443         I915_WRITE(reg, temp);
3444
3445         reg = FDI_RX_CTL(pipe);
3446         temp = I915_READ(reg);
3447         temp &= ~FDI_LINK_TRAIN_NONE;
3448         temp |= FDI_LINK_TRAIN_PATTERN_2;
3449         I915_WRITE(reg, temp);
3450
3451         POSTING_READ(reg);
3452         udelay(150);
3453
3454         reg = FDI_RX_IIR(pipe);
3455         for (tries = 0; tries < 5; tries++) {
3456                 temp = I915_READ(reg);
3457                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3458
3459                 if (temp & FDI_RX_SYMBOL_LOCK) {
3460                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3461                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3462                         break;
3463                 }
3464         }
3465         if (tries == 5)
3466                 DRM_ERROR("FDI train 2 fail!\n");
3467
3468         DRM_DEBUG_KMS("FDI train done\n");
3469
3470 }
3471
3472 static const int snb_b_fdi_train_param[] = {
3473         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3474         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3475         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3476         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3477 };
3478
3479 /* The FDI link training functions for SNB/Cougarpoint. */
3480 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3481 {
3482         struct drm_device *dev = crtc->dev;
3483         struct drm_i915_private *dev_priv = dev->dev_private;
3484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3485         int pipe = intel_crtc->pipe;
3486         u32 reg, temp, i, retry;
3487
3488         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3489            for train result */
3490         reg = FDI_RX_IMR(pipe);
3491         temp = I915_READ(reg);
3492         temp &= ~FDI_RX_SYMBOL_LOCK;
3493         temp &= ~FDI_RX_BIT_LOCK;
3494         I915_WRITE(reg, temp);
3495
3496         POSTING_READ(reg);
3497         udelay(150);
3498
3499         /* enable CPU FDI TX and PCH FDI RX */
3500         reg = FDI_TX_CTL(pipe);
3501         temp = I915_READ(reg);
3502         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3503         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3504         temp &= ~FDI_LINK_TRAIN_NONE;
3505         temp |= FDI_LINK_TRAIN_PATTERN_1;
3506         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3507         /* SNB-B */
3508         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3509         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3510
3511         I915_WRITE(FDI_RX_MISC(pipe),
3512                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3513
3514         reg = FDI_RX_CTL(pipe);
3515         temp = I915_READ(reg);
3516         if (HAS_PCH_CPT(dev)) {
3517                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3519         } else {
3520                 temp &= ~FDI_LINK_TRAIN_NONE;
3521                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3522         }
3523         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3524
3525         POSTING_READ(reg);
3526         udelay(150);
3527
3528         for (i = 0; i < 4; i++) {
3529                 reg = FDI_TX_CTL(pipe);
3530                 temp = I915_READ(reg);
3531                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3532                 temp |= snb_b_fdi_train_param[i];
3533                 I915_WRITE(reg, temp);
3534
3535                 POSTING_READ(reg);
3536                 udelay(500);
3537
3538                 for (retry = 0; retry < 5; retry++) {
3539                         reg = FDI_RX_IIR(pipe);
3540                         temp = I915_READ(reg);
3541                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3542                         if (temp & FDI_RX_BIT_LOCK) {
3543                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3544                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3545                                 break;
3546                         }
3547                         udelay(50);
3548                 }
3549                 if (retry < 5)
3550                         break;
3551         }
3552         if (i == 4)
3553                 DRM_ERROR("FDI train 1 fail!\n");
3554
3555         /* Train 2 */
3556         reg = FDI_TX_CTL(pipe);
3557         temp = I915_READ(reg);
3558         temp &= ~FDI_LINK_TRAIN_NONE;
3559         temp |= FDI_LINK_TRAIN_PATTERN_2;
3560         if (IS_GEN6(dev)) {
3561                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3562                 /* SNB-B */
3563                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3564         }
3565         I915_WRITE(reg, temp);
3566
3567         reg = FDI_RX_CTL(pipe);
3568         temp = I915_READ(reg);
3569         if (HAS_PCH_CPT(dev)) {
3570                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3572         } else {
3573                 temp &= ~FDI_LINK_TRAIN_NONE;
3574                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3575         }
3576         I915_WRITE(reg, temp);
3577
3578         POSTING_READ(reg);
3579         udelay(150);
3580
3581         for (i = 0; i < 4; i++) {
3582                 reg = FDI_TX_CTL(pipe);
3583                 temp = I915_READ(reg);
3584                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3585                 temp |= snb_b_fdi_train_param[i];
3586                 I915_WRITE(reg, temp);
3587
3588                 POSTING_READ(reg);
3589                 udelay(500);
3590
3591                 for (retry = 0; retry < 5; retry++) {
3592                         reg = FDI_RX_IIR(pipe);
3593                         temp = I915_READ(reg);
3594                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3595                         if (temp & FDI_RX_SYMBOL_LOCK) {
3596                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3597                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3598                                 break;
3599                         }
3600                         udelay(50);
3601                 }
3602                 if (retry < 5)
3603                         break;
3604         }
3605         if (i == 4)
3606                 DRM_ERROR("FDI train 2 fail!\n");
3607
3608         DRM_DEBUG_KMS("FDI train done.\n");
3609 }
3610
3611 /* Manual link training for Ivy Bridge A0 parts */
3612 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3613 {
3614         struct drm_device *dev = crtc->dev;
3615         struct drm_i915_private *dev_priv = dev->dev_private;
3616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617         int pipe = intel_crtc->pipe;
3618         u32 reg, temp, i, j;
3619
3620         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3621            for train result */
3622         reg = FDI_RX_IMR(pipe);
3623         temp = I915_READ(reg);
3624         temp &= ~FDI_RX_SYMBOL_LOCK;
3625         temp &= ~FDI_RX_BIT_LOCK;
3626         I915_WRITE(reg, temp);
3627
3628         POSTING_READ(reg);
3629         udelay(150);
3630
3631         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3632                       I915_READ(FDI_RX_IIR(pipe)));
3633
3634         /* Try each vswing and preemphasis setting twice before moving on */
3635         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3636                 /* disable first in case we need to retry */
3637                 reg = FDI_TX_CTL(pipe);
3638                 temp = I915_READ(reg);
3639                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3640                 temp &= ~FDI_TX_ENABLE;
3641                 I915_WRITE(reg, temp);
3642
3643                 reg = FDI_RX_CTL(pipe);
3644                 temp = I915_READ(reg);
3645                 temp &= ~FDI_LINK_TRAIN_AUTO;
3646                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3647                 temp &= ~FDI_RX_ENABLE;
3648                 I915_WRITE(reg, temp);
3649
3650                 /* enable CPU FDI TX and PCH FDI RX */
3651                 reg = FDI_TX_CTL(pipe);
3652                 temp = I915_READ(reg);
3653                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3654                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3655                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3656                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3657                 temp |= snb_b_fdi_train_param[j/2];
3658                 temp |= FDI_COMPOSITE_SYNC;
3659                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3660
3661                 I915_WRITE(FDI_RX_MISC(pipe),
3662                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3663
3664                 reg = FDI_RX_CTL(pipe);
3665                 temp = I915_READ(reg);
3666                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3667                 temp |= FDI_COMPOSITE_SYNC;
3668                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3669
3670                 POSTING_READ(reg);
3671                 udelay(1); /* should be 0.5us */
3672
3673                 for (i = 0; i < 4; i++) {
3674                         reg = FDI_RX_IIR(pipe);
3675                         temp = I915_READ(reg);
3676                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3677
3678                         if (temp & FDI_RX_BIT_LOCK ||
3679                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3680                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3681                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3682                                               i);
3683                                 break;
3684                         }
3685                         udelay(1); /* should be 0.5us */
3686                 }
3687                 if (i == 4) {
3688                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3689                         continue;
3690                 }
3691
3692                 /* Train 2 */
3693                 reg = FDI_TX_CTL(pipe);
3694                 temp = I915_READ(reg);
3695                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3696                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3697                 I915_WRITE(reg, temp);
3698
3699                 reg = FDI_RX_CTL(pipe);
3700                 temp = I915_READ(reg);
3701                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3702                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3703                 I915_WRITE(reg, temp);
3704
3705                 POSTING_READ(reg);
3706                 udelay(2); /* should be 1.5us */
3707
3708                 for (i = 0; i < 4; i++) {
3709                         reg = FDI_RX_IIR(pipe);
3710                         temp = I915_READ(reg);
3711                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3712
3713                         if (temp & FDI_RX_SYMBOL_LOCK ||
3714                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3715                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3716                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3717                                               i);
3718                                 goto train_done;
3719                         }
3720                         udelay(2); /* should be 1.5us */
3721                 }
3722                 if (i == 4)
3723                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3724         }
3725
3726 train_done:
3727         DRM_DEBUG_KMS("FDI train done.\n");
3728 }
3729
3730 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3731 {
3732         struct drm_device *dev = intel_crtc->base.dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         int pipe = intel_crtc->pipe;
3735         u32 reg, temp;
3736
3737
3738         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3739         reg = FDI_RX_CTL(pipe);
3740         temp = I915_READ(reg);
3741         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3742         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3743         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3744         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3745
3746         POSTING_READ(reg);
3747         udelay(200);
3748
3749         /* Switch from Rawclk to PCDclk */
3750         temp = I915_READ(reg);
3751         I915_WRITE(reg, temp | FDI_PCDCLK);
3752
3753         POSTING_READ(reg);
3754         udelay(200);
3755
3756         /* Enable CPU FDI TX PLL, always on for Ironlake */
3757         reg = FDI_TX_CTL(pipe);
3758         temp = I915_READ(reg);
3759         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3760                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3761
3762                 POSTING_READ(reg);
3763                 udelay(100);
3764         }
3765 }
3766
3767 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3768 {
3769         struct drm_device *dev = intel_crtc->base.dev;
3770         struct drm_i915_private *dev_priv = dev->dev_private;
3771         int pipe = intel_crtc->pipe;
3772         u32 reg, temp;
3773
3774         /* Switch from PCDclk to Rawclk */
3775         reg = FDI_RX_CTL(pipe);
3776         temp = I915_READ(reg);
3777         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3778
3779         /* Disable CPU FDI TX PLL */
3780         reg = FDI_TX_CTL(pipe);
3781         temp = I915_READ(reg);
3782         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3783
3784         POSTING_READ(reg);
3785         udelay(100);
3786
3787         reg = FDI_RX_CTL(pipe);
3788         temp = I915_READ(reg);
3789         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3790
3791         /* Wait for the clocks to turn off. */
3792         POSTING_READ(reg);
3793         udelay(100);
3794 }
3795
3796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3797 {
3798         struct drm_device *dev = crtc->dev;
3799         struct drm_i915_private *dev_priv = dev->dev_private;
3800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3801         int pipe = intel_crtc->pipe;
3802         u32 reg, temp;
3803
3804         /* disable CPU FDI tx and PCH FDI rx */
3805         reg = FDI_TX_CTL(pipe);
3806         temp = I915_READ(reg);
3807         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3808         POSTING_READ(reg);
3809
3810         reg = FDI_RX_CTL(pipe);
3811         temp = I915_READ(reg);
3812         temp &= ~(0x7 << 16);
3813         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3814         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3815
3816         POSTING_READ(reg);
3817         udelay(100);
3818
3819         /* Ironlake workaround, disable clock pointer after downing FDI */
3820         if (HAS_PCH_IBX(dev))
3821                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3822
3823         /* still set train pattern 1 */
3824         reg = FDI_TX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         temp &= ~FDI_LINK_TRAIN_NONE;
3827         temp |= FDI_LINK_TRAIN_PATTERN_1;
3828         I915_WRITE(reg, temp);
3829
3830         reg = FDI_RX_CTL(pipe);
3831         temp = I915_READ(reg);
3832         if (HAS_PCH_CPT(dev)) {
3833                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3834                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3835         } else {
3836                 temp &= ~FDI_LINK_TRAIN_NONE;
3837                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3838         }
3839         /* BPC in FDI rx is consistent with that in PIPECONF */
3840         temp &= ~(0x07 << 16);
3841         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3842         I915_WRITE(reg, temp);
3843
3844         POSTING_READ(reg);
3845         udelay(100);
3846 }
3847
3848 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3849 {
3850         struct intel_crtc *crtc;
3851
3852         /* Note that we don't need to be called with mode_config.lock here
3853          * as our list of CRTC objects is static for the lifetime of the
3854          * device and so cannot disappear as we iterate. Similarly, we can
3855          * happily treat the predicates as racy, atomic checks as userspace
3856          * cannot claim and pin a new fb without at least acquring the
3857          * struct_mutex and so serialising with us.
3858          */
3859         for_each_intel_crtc(dev, crtc) {
3860                 if (atomic_read(&crtc->unpin_work_count) == 0)
3861                         continue;
3862
3863                 if (crtc->unpin_work)
3864                         intel_wait_for_vblank(dev, crtc->pipe);
3865
3866                 return true;
3867         }
3868
3869         return false;
3870 }
3871
3872 static void page_flip_completed(struct intel_crtc *intel_crtc)
3873 {
3874         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3875         struct intel_unpin_work *work = intel_crtc->unpin_work;
3876
3877         /* ensure that the unpin work is consistent wrt ->pending. */
3878         smp_rmb();
3879         intel_crtc->unpin_work = NULL;
3880
3881         if (work->event)
3882                 drm_send_vblank_event(intel_crtc->base.dev,
3883                                       intel_crtc->pipe,
3884                                       work->event);
3885
3886         drm_crtc_vblank_put(&intel_crtc->base);
3887
3888         wake_up_all(&dev_priv->pending_flip_queue);
3889         queue_work(dev_priv->wq, &work->work);
3890
3891         trace_i915_flip_complete(intel_crtc->plane,
3892                                  work->pending_flip_obj);
3893 }
3894
3895 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3896 {
3897         struct drm_device *dev = crtc->dev;
3898         struct drm_i915_private *dev_priv = dev->dev_private;
3899
3900         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3901         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3902                                        !intel_crtc_has_pending_flip(crtc),
3903                                        60*HZ) == 0)) {
3904                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3905
3906                 spin_lock_irq(&dev->event_lock);
3907                 if (intel_crtc->unpin_work) {
3908                         WARN_ONCE(1, "Removing stuck page flip\n");
3909                         page_flip_completed(intel_crtc);
3910                 }
3911                 spin_unlock_irq(&dev->event_lock);
3912         }
3913
3914         if (crtc->primary->fb) {
3915                 mutex_lock(&dev->struct_mutex);
3916                 intel_finish_fb(crtc->primary->fb);
3917                 mutex_unlock(&dev->struct_mutex);
3918         }
3919 }
3920
3921 /* Program iCLKIP clock to the desired frequency */
3922 static void lpt_program_iclkip(struct drm_crtc *crtc)
3923 {
3924         struct drm_device *dev = crtc->dev;
3925         struct drm_i915_private *dev_priv = dev->dev_private;
3926         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3927         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3928         u32 temp;
3929
3930         mutex_lock(&dev_priv->sb_lock);
3931
3932         /* It is necessary to ungate the pixclk gate prior to programming
3933          * the divisors, and gate it back when it is done.
3934          */
3935         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3936
3937         /* Disable SSCCTL */
3938         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3939                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3940                                 SBI_SSCCTL_DISABLE,
3941                         SBI_ICLK);
3942
3943         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3944         if (clock == 20000) {
3945                 auxdiv = 1;
3946                 divsel = 0x41;
3947                 phaseinc = 0x20;
3948         } else {
3949                 /* The iCLK virtual clock root frequency is in MHz,
3950                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3951                  * divisors, it is necessary to divide one by another, so we
3952                  * convert the virtual clock precision to KHz here for higher
3953                  * precision.
3954                  */
3955                 u32 iclk_virtual_root_freq = 172800 * 1000;
3956                 u32 iclk_pi_range = 64;
3957                 u32 desired_divisor, msb_divisor_value, pi_value;
3958
3959                 desired_divisor = (iclk_virtual_root_freq / clock);
3960                 msb_divisor_value = desired_divisor / iclk_pi_range;
3961                 pi_value = desired_divisor % iclk_pi_range;
3962
3963                 auxdiv = 0;
3964                 divsel = msb_divisor_value - 2;
3965                 phaseinc = pi_value;
3966         }
3967
3968         /* This should not happen with any sane values */
3969         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3970                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3971         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3972                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3973
3974         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3975                         clock,
3976                         auxdiv,
3977                         divsel,
3978                         phasedir,
3979                         phaseinc);
3980
3981         /* Program SSCDIVINTPHASE6 */
3982         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3983         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3984         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3985         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3986         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3987         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3988         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3989         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3990
3991         /* Program SSCAUXDIV */
3992         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3993         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3994         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3995         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3996
3997         /* Enable modulator and associated divider */
3998         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3999         temp &= ~SBI_SSCCTL_DISABLE;
4000         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4001
4002         /* Wait for initialization time */
4003         udelay(24);
4004
4005         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4006
4007         mutex_unlock(&dev_priv->sb_lock);
4008 }
4009
4010 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4011                                                 enum pipe pch_transcoder)
4012 {
4013         struct drm_device *dev = crtc->base.dev;
4014         struct drm_i915_private *dev_priv = dev->dev_private;
4015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4016
4017         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4018                    I915_READ(HTOTAL(cpu_transcoder)));
4019         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4020                    I915_READ(HBLANK(cpu_transcoder)));
4021         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4022                    I915_READ(HSYNC(cpu_transcoder)));
4023
4024         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4025                    I915_READ(VTOTAL(cpu_transcoder)));
4026         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4027                    I915_READ(VBLANK(cpu_transcoder)));
4028         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4029                    I915_READ(VSYNC(cpu_transcoder)));
4030         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4031                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4032 }
4033
4034 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4035 {
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         uint32_t temp;
4038
4039         temp = I915_READ(SOUTH_CHICKEN1);
4040         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4041                 return;
4042
4043         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4044         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4045
4046         temp &= ~FDI_BC_BIFURCATION_SELECT;
4047         if (enable)
4048                 temp |= FDI_BC_BIFURCATION_SELECT;
4049
4050         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4051         I915_WRITE(SOUTH_CHICKEN1, temp);
4052         POSTING_READ(SOUTH_CHICKEN1);
4053 }
4054
4055 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4056 {
4057         struct drm_device *dev = intel_crtc->base.dev;
4058
4059         switch (intel_crtc->pipe) {
4060         case PIPE_A:
4061                 break;
4062         case PIPE_B:
4063                 if (intel_crtc->config->fdi_lanes > 2)
4064                         cpt_set_fdi_bc_bifurcation(dev, false);
4065                 else
4066                         cpt_set_fdi_bc_bifurcation(dev, true);
4067
4068                 break;
4069         case PIPE_C:
4070                 cpt_set_fdi_bc_bifurcation(dev, true);
4071
4072                 break;
4073         default:
4074                 BUG();
4075         }
4076 }
4077
4078 /*
4079  * Enable PCH resources required for PCH ports:
4080  *   - PCH PLLs
4081  *   - FDI training & RX/TX
4082  *   - update transcoder timings
4083  *   - DP transcoding bits
4084  *   - transcoder
4085  */
4086 static void ironlake_pch_enable(struct drm_crtc *crtc)
4087 {
4088         struct drm_device *dev = crtc->dev;
4089         struct drm_i915_private *dev_priv = dev->dev_private;
4090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4091         int pipe = intel_crtc->pipe;
4092         u32 reg, temp;
4093
4094         assert_pch_transcoder_disabled(dev_priv, pipe);
4095
4096         if (IS_IVYBRIDGE(dev))
4097                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4098
4099         /* Write the TU size bits before fdi link training, so that error
4100          * detection works. */
4101         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4102                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4103
4104         /* For PCH output, training FDI link */
4105         dev_priv->display.fdi_link_train(crtc);
4106
4107         /* We need to program the right clock selection before writing the pixel
4108          * mutliplier into the DPLL. */
4109         if (HAS_PCH_CPT(dev)) {
4110                 u32 sel;
4111
4112                 temp = I915_READ(PCH_DPLL_SEL);
4113                 temp |= TRANS_DPLL_ENABLE(pipe);
4114                 sel = TRANS_DPLLB_SEL(pipe);
4115                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4116                         temp |= sel;
4117                 else
4118                         temp &= ~sel;
4119                 I915_WRITE(PCH_DPLL_SEL, temp);
4120         }
4121
4122         /* XXX: pch pll's can be enabled any time before we enable the PCH
4123          * transcoder, and we actually should do this to not upset any PCH
4124          * transcoder that already use the clock when we share it.
4125          *
4126          * Note that enable_shared_dpll tries to do the right thing, but
4127          * get_shared_dpll unconditionally resets the pll - we need that to have
4128          * the right LVDS enable sequence. */
4129         intel_enable_shared_dpll(intel_crtc);
4130
4131         /* set transcoder timing, panel must allow it */
4132         assert_panel_unlocked(dev_priv, pipe);
4133         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4134
4135         intel_fdi_normal_train(crtc);
4136
4137         /* For PCH DP, enable TRANS_DP_CTL */
4138         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4139                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4140                 reg = TRANS_DP_CTL(pipe);
4141                 temp = I915_READ(reg);
4142                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4143                           TRANS_DP_SYNC_MASK |
4144                           TRANS_DP_BPC_MASK);
4145                 temp |= TRANS_DP_OUTPUT_ENABLE;
4146                 temp |= bpc << 9; /* same format but at 11:9 */
4147
4148                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4149                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4150                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4151                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4152
4153                 switch (intel_trans_dp_port_sel(crtc)) {
4154                 case PCH_DP_B:
4155                         temp |= TRANS_DP_PORT_SEL_B;
4156                         break;
4157                 case PCH_DP_C:
4158                         temp |= TRANS_DP_PORT_SEL_C;
4159                         break;
4160                 case PCH_DP_D:
4161                         temp |= TRANS_DP_PORT_SEL_D;
4162                         break;
4163                 default:
4164                         BUG();
4165                 }
4166
4167                 I915_WRITE(reg, temp);
4168         }
4169
4170         ironlake_enable_pch_transcoder(dev_priv, pipe);
4171 }
4172
4173 static void lpt_pch_enable(struct drm_crtc *crtc)
4174 {
4175         struct drm_device *dev = crtc->dev;
4176         struct drm_i915_private *dev_priv = dev->dev_private;
4177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4179
4180         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4181
4182         lpt_program_iclkip(crtc);
4183
4184         /* Set transcoder timing. */
4185         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4186
4187         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4188 }
4189
4190 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4191                                                 struct intel_crtc_state *crtc_state)
4192 {
4193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4194         struct intel_shared_dpll *pll;
4195         struct intel_shared_dpll_config *shared_dpll;
4196         enum intel_dpll_id i;
4197
4198         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4199
4200         if (HAS_PCH_IBX(dev_priv->dev)) {
4201                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4202                 i = (enum intel_dpll_id) crtc->pipe;
4203                 pll = &dev_priv->shared_dplls[i];
4204
4205                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4206                               crtc->base.base.id, pll->name);
4207
4208                 WARN_ON(shared_dpll[i].crtc_mask);
4209
4210                 goto found;
4211         }
4212
4213         if (IS_BROXTON(dev_priv->dev)) {
4214                 /* PLL is attached to port in bxt */
4215                 struct intel_encoder *encoder;
4216                 struct intel_digital_port *intel_dig_port;
4217
4218                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4219                 if (WARN_ON(!encoder))
4220                         return NULL;
4221
4222                 intel_dig_port = enc_to_dig_port(&encoder->base);
4223                 /* 1:1 mapping between ports and PLLs */
4224                 i = (enum intel_dpll_id)intel_dig_port->port;
4225                 pll = &dev_priv->shared_dplls[i];
4226                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4227                         crtc->base.base.id, pll->name);
4228                 WARN_ON(shared_dpll[i].crtc_mask);
4229
4230                 goto found;
4231         }
4232
4233         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4234                 pll = &dev_priv->shared_dplls[i];
4235
4236                 /* Only want to check enabled timings first */
4237                 if (shared_dpll[i].crtc_mask == 0)
4238                         continue;
4239
4240                 if (memcmp(&crtc_state->dpll_hw_state,
4241                            &shared_dpll[i].hw_state,
4242                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4243                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4244                                       crtc->base.base.id, pll->name,
4245                                       shared_dpll[i].crtc_mask,
4246                                       pll->active);
4247                         goto found;
4248                 }
4249         }
4250
4251         /* Ok no matching timings, maybe there's a free one? */
4252         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4253                 pll = &dev_priv->shared_dplls[i];
4254                 if (shared_dpll[i].crtc_mask == 0) {
4255                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4256                                       crtc->base.base.id, pll->name);
4257                         goto found;
4258                 }
4259         }
4260
4261         return NULL;
4262
4263 found:
4264         if (shared_dpll[i].crtc_mask == 0)
4265                 shared_dpll[i].hw_state =
4266                         crtc_state->dpll_hw_state;
4267
4268         crtc_state->shared_dpll = i;
4269         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4270                          pipe_name(crtc->pipe));
4271
4272         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4273
4274         return pll;
4275 }
4276
4277 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4278 {
4279         struct drm_i915_private *dev_priv = to_i915(state->dev);
4280         struct intel_shared_dpll_config *shared_dpll;
4281         struct intel_shared_dpll *pll;
4282         enum intel_dpll_id i;
4283
4284         if (!to_intel_atomic_state(state)->dpll_set)
4285                 return;
4286
4287         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4288         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4289                 pll = &dev_priv->shared_dplls[i];
4290                 pll->config = shared_dpll[i];
4291         }
4292 }
4293
4294 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4295 {
4296         struct drm_i915_private *dev_priv = dev->dev_private;
4297         int dslreg = PIPEDSL(pipe);
4298         u32 temp;
4299
4300         temp = I915_READ(dslreg);
4301         udelay(500);
4302         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4303                 if (wait_for(I915_READ(dslreg) != temp, 5))
4304                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4305         }
4306 }
4307
4308 static int
4309 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4310                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4311                   int src_w, int src_h, int dst_w, int dst_h)
4312 {
4313         struct intel_crtc_scaler_state *scaler_state =
4314                 &crtc_state->scaler_state;
4315         struct intel_crtc *intel_crtc =
4316                 to_intel_crtc(crtc_state->base.crtc);
4317         int need_scaling;
4318
4319         need_scaling = intel_rotation_90_or_270(rotation) ?
4320                 (src_h != dst_w || src_w != dst_h):
4321                 (src_w != dst_w || src_h != dst_h);
4322
4323         /*
4324          * if plane is being disabled or scaler is no more required or force detach
4325          *  - free scaler binded to this plane/crtc
4326          *  - in order to do this, update crtc->scaler_usage
4327          *
4328          * Here scaler state in crtc_state is set free so that
4329          * scaler can be assigned to other user. Actual register
4330          * update to free the scaler is done in plane/panel-fit programming.
4331          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4332          */
4333         if (force_detach || !need_scaling) {
4334                 if (*scaler_id >= 0) {
4335                         scaler_state->scaler_users &= ~(1 << scaler_user);
4336                         scaler_state->scalers[*scaler_id].in_use = 0;
4337
4338                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4339                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4340                                 intel_crtc->pipe, scaler_user, *scaler_id,
4341                                 scaler_state->scaler_users);
4342                         *scaler_id = -1;
4343                 }
4344                 return 0;
4345         }
4346
4347         /* range checks */
4348         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4349                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4350
4351                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4352                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4353                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4354                         "size is out of scaler range\n",
4355                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4356                 return -EINVAL;
4357         }
4358
4359         /* mark this plane as a scaler user in crtc_state */
4360         scaler_state->scaler_users |= (1 << scaler_user);
4361         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4362                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4363                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4364                 scaler_state->scaler_users);
4365
4366         return 0;
4367 }
4368
4369 /**
4370  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4371  *
4372  * @state: crtc's scaler state
4373  *
4374  * Return
4375  *     0 - scaler_usage updated successfully
4376  *    error - requested scaling cannot be supported or other error condition
4377  */
4378 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4379 {
4380         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4381         struct drm_display_mode *adjusted_mode =
4382                 &state->base.adjusted_mode;
4383
4384         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4385                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4386
4387         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4388                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4389                 state->pipe_src_w, state->pipe_src_h,
4390                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4391 }
4392
4393 /**
4394  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4395  *
4396  * @state: crtc's scaler state
4397  * @plane_state: atomic plane state to update
4398  *
4399  * Return
4400  *     0 - scaler_usage updated successfully
4401  *    error - requested scaling cannot be supported or other error condition
4402  */
4403 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4404                                    struct intel_plane_state *plane_state)
4405 {
4406
4407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4408         struct intel_plane *intel_plane =
4409                 to_intel_plane(plane_state->base.plane);
4410         struct drm_framebuffer *fb = plane_state->base.fb;
4411         int ret;
4412
4413         bool force_detach = !fb || !plane_state->visible;
4414
4415         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4416                       intel_plane->base.base.id, intel_crtc->pipe,
4417                       drm_plane_index(&intel_plane->base));
4418
4419         ret = skl_update_scaler(crtc_state, force_detach,
4420                                 drm_plane_index(&intel_plane->base),
4421                                 &plane_state->scaler_id,
4422                                 plane_state->base.rotation,
4423                                 drm_rect_width(&plane_state->src) >> 16,
4424                                 drm_rect_height(&plane_state->src) >> 16,
4425                                 drm_rect_width(&plane_state->dst),
4426                                 drm_rect_height(&plane_state->dst));
4427
4428         if (ret || plane_state->scaler_id < 0)
4429                 return ret;
4430
4431         /* check colorkey */
4432         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4433                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4434                               intel_plane->base.base.id);
4435                 return -EINVAL;
4436         }
4437
4438         /* Check src format */
4439         switch (fb->pixel_format) {
4440         case DRM_FORMAT_RGB565:
4441         case DRM_FORMAT_XBGR8888:
4442         case DRM_FORMAT_XRGB8888:
4443         case DRM_FORMAT_ABGR8888:
4444         case DRM_FORMAT_ARGB8888:
4445         case DRM_FORMAT_XRGB2101010:
4446         case DRM_FORMAT_XBGR2101010:
4447         case DRM_FORMAT_YUYV:
4448         case DRM_FORMAT_YVYU:
4449         case DRM_FORMAT_UYVY:
4450         case DRM_FORMAT_VYUY:
4451                 break;
4452         default:
4453                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4454                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4455                 return -EINVAL;
4456         }
4457
4458         return 0;
4459 }
4460
4461 static void skylake_scaler_disable(struct intel_crtc *crtc)
4462 {
4463         int i;
4464
4465         for (i = 0; i < crtc->num_scalers; i++)
4466                 skl_detach_scaler(crtc, i);
4467 }
4468
4469 static void skylake_pfit_enable(struct intel_crtc *crtc)
4470 {
4471         struct drm_device *dev = crtc->base.dev;
4472         struct drm_i915_private *dev_priv = dev->dev_private;
4473         int pipe = crtc->pipe;
4474         struct intel_crtc_scaler_state *scaler_state =
4475                 &crtc->config->scaler_state;
4476
4477         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4478
4479         if (crtc->config->pch_pfit.enabled) {
4480                 int id;
4481
4482                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4483                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4484                         return;
4485                 }
4486
4487                 id = scaler_state->scaler_id;
4488                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4489                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4490                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4491                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4492
4493                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4494         }
4495 }
4496
4497 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4498 {
4499         struct drm_device *dev = crtc->base.dev;
4500         struct drm_i915_private *dev_priv = dev->dev_private;
4501         int pipe = crtc->pipe;
4502
4503         if (crtc->config->pch_pfit.enabled) {
4504                 /* Force use of hard-coded filter coefficients
4505                  * as some pre-programmed values are broken,
4506                  * e.g. x201.
4507                  */
4508                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4509                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4510                                                  PF_PIPE_SEL_IVB(pipe));
4511                 else
4512                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4513                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4514                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4515         }
4516 }
4517
4518 void hsw_enable_ips(struct intel_crtc *crtc)
4519 {
4520         struct drm_device *dev = crtc->base.dev;
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522
4523         if (!crtc->config->ips_enabled)
4524                 return;
4525
4526         /* We can only enable IPS after we enable a plane and wait for a vblank */
4527         intel_wait_for_vblank(dev, crtc->pipe);
4528
4529         assert_plane_enabled(dev_priv, crtc->plane);
4530         if (IS_BROADWELL(dev)) {
4531                 mutex_lock(&dev_priv->rps.hw_lock);
4532                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4533                 mutex_unlock(&dev_priv->rps.hw_lock);
4534                 /* Quoting Art Runyan: "its not safe to expect any particular
4535                  * value in IPS_CTL bit 31 after enabling IPS through the
4536                  * mailbox." Moreover, the mailbox may return a bogus state,
4537                  * so we need to just enable it and continue on.
4538                  */
4539         } else {
4540                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4541                 /* The bit only becomes 1 in the next vblank, so this wait here
4542                  * is essentially intel_wait_for_vblank. If we don't have this
4543                  * and don't wait for vblanks until the end of crtc_enable, then
4544                  * the HW state readout code will complain that the expected
4545                  * IPS_CTL value is not the one we read. */
4546                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4547                         DRM_ERROR("Timed out waiting for IPS enable\n");
4548         }
4549 }
4550
4551 void hsw_disable_ips(struct intel_crtc *crtc)
4552 {
4553         struct drm_device *dev = crtc->base.dev;
4554         struct drm_i915_private *dev_priv = dev->dev_private;
4555
4556         if (!crtc->config->ips_enabled)
4557                 return;
4558
4559         assert_plane_enabled(dev_priv, crtc->plane);
4560         if (IS_BROADWELL(dev)) {
4561                 mutex_lock(&dev_priv->rps.hw_lock);
4562                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4563                 mutex_unlock(&dev_priv->rps.hw_lock);
4564                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4565                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4566                         DRM_ERROR("Timed out waiting for IPS disable\n");
4567         } else {
4568                 I915_WRITE(IPS_CTL, 0);
4569                 POSTING_READ(IPS_CTL);
4570         }
4571
4572         /* We need to wait for a vblank before we can disable the plane. */
4573         intel_wait_for_vblank(dev, crtc->pipe);
4574 }
4575
4576 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4577 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4578 {
4579         struct drm_device *dev = crtc->dev;
4580         struct drm_i915_private *dev_priv = dev->dev_private;
4581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582         enum pipe pipe = intel_crtc->pipe;
4583         int palreg = PALETTE(pipe);
4584         int i;
4585         bool reenable_ips = false;
4586
4587         /* The clocks have to be on to load the palette. */
4588         if (!crtc->state->active)
4589                 return;
4590
4591         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4592                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4593                         assert_dsi_pll_enabled(dev_priv);
4594                 else
4595                         assert_pll_enabled(dev_priv, pipe);
4596         }
4597
4598         /* use legacy palette for Ironlake */
4599         if (!HAS_GMCH_DISPLAY(dev))
4600                 palreg = LGC_PALETTE(pipe);
4601
4602         /* Workaround : Do not read or write the pipe palette/gamma data while
4603          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4604          */
4605         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4606             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4607              GAMMA_MODE_MODE_SPLIT)) {
4608                 hsw_disable_ips(intel_crtc);
4609                 reenable_ips = true;
4610         }
4611
4612         for (i = 0; i < 256; i++) {
4613                 I915_WRITE(palreg + 4 * i,
4614                            (intel_crtc->lut_r[i] << 16) |
4615                            (intel_crtc->lut_g[i] << 8) |
4616                            intel_crtc->lut_b[i]);
4617         }
4618
4619         if (reenable_ips)
4620                 hsw_enable_ips(intel_crtc);
4621 }
4622
4623 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4624 {
4625         if (intel_crtc->overlay) {
4626                 struct drm_device *dev = intel_crtc->base.dev;
4627                 struct drm_i915_private *dev_priv = dev->dev_private;
4628
4629                 mutex_lock(&dev->struct_mutex);
4630                 dev_priv->mm.interruptible = false;
4631                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4632                 dev_priv->mm.interruptible = true;
4633                 mutex_unlock(&dev->struct_mutex);
4634         }
4635
4636         /* Let userspace switch the overlay on again. In most cases userspace
4637          * has to recompute where to put it anyway.
4638          */
4639 }
4640
4641 /**
4642  * intel_post_enable_primary - Perform operations after enabling primary plane
4643  * @crtc: the CRTC whose primary plane was just enabled
4644  *
4645  * Performs potentially sleeping operations that must be done after the primary
4646  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4647  * called due to an explicit primary plane update, or due to an implicit
4648  * re-enable that is caused when a sprite plane is updated to no longer
4649  * completely hide the primary plane.
4650  */
4651 static void
4652 intel_post_enable_primary(struct drm_crtc *crtc)
4653 {
4654         struct drm_device *dev = crtc->dev;
4655         struct drm_i915_private *dev_priv = dev->dev_private;
4656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4657         int pipe = intel_crtc->pipe;
4658
4659         /*
4660          * BDW signals flip done immediately if the plane
4661          * is disabled, even if the plane enable is already
4662          * armed to occur at the next vblank :(
4663          */
4664         if (IS_BROADWELL(dev))
4665                 intel_wait_for_vblank(dev, pipe);
4666
4667         /*
4668          * FIXME IPS should be fine as long as one plane is
4669          * enabled, but in practice it seems to have problems
4670          * when going from primary only to sprite only and vice
4671          * versa.
4672          */
4673         hsw_enable_ips(intel_crtc);
4674
4675         /*
4676          * Gen2 reports pipe underruns whenever all planes are disabled.
4677          * So don't enable underrun reporting before at least some planes
4678          * are enabled.
4679          * FIXME: Need to fix the logic to work when we turn off all planes
4680          * but leave the pipe running.
4681          */
4682         if (IS_GEN2(dev))
4683                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4684
4685         /* Underruns don't raise interrupts, so check manually. */
4686         if (HAS_GMCH_DISPLAY(dev))
4687                 i9xx_check_fifo_underruns(dev_priv);
4688 }
4689
4690 /**
4691  * intel_pre_disable_primary - Perform operations before disabling primary plane
4692  * @crtc: the CRTC whose primary plane is to be disabled
4693  *
4694  * Performs potentially sleeping operations that must be done before the
4695  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4696  * be called due to an explicit primary plane update, or due to an implicit
4697  * disable that is caused when a sprite plane completely hides the primary
4698  * plane.
4699  */
4700 static void
4701 intel_pre_disable_primary(struct drm_crtc *crtc)
4702 {
4703         struct drm_device *dev = crtc->dev;
4704         struct drm_i915_private *dev_priv = dev->dev_private;
4705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706         int pipe = intel_crtc->pipe;
4707
4708         /*
4709          * Gen2 reports pipe underruns whenever all planes are disabled.
4710          * So diasble underrun reporting before all the planes get disabled.
4711          * FIXME: Need to fix the logic to work when we turn off all planes
4712          * but leave the pipe running.
4713          */
4714         if (IS_GEN2(dev))
4715                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4716
4717         /*
4718          * Vblank time updates from the shadow to live plane control register
4719          * are blocked if the memory self-refresh mode is active at that
4720          * moment. So to make sure the plane gets truly disabled, disable
4721          * first the self-refresh mode. The self-refresh enable bit in turn
4722          * will be checked/applied by the HW only at the next frame start
4723          * event which is after the vblank start event, so we need to have a
4724          * wait-for-vblank between disabling the plane and the pipe.
4725          */
4726         if (HAS_GMCH_DISPLAY(dev)) {
4727                 intel_set_memory_cxsr(dev_priv, false);
4728                 dev_priv->wm.vlv.cxsr = false;
4729                 intel_wait_for_vblank(dev, pipe);
4730         }
4731
4732         /*
4733          * FIXME IPS should be fine as long as one plane is
4734          * enabled, but in practice it seems to have problems
4735          * when going from primary only to sprite only and vice
4736          * versa.
4737          */
4738         hsw_disable_ips(intel_crtc);
4739 }
4740
4741 static void intel_post_plane_update(struct intel_crtc *crtc)
4742 {
4743         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4744         struct drm_device *dev = crtc->base.dev;
4745         struct drm_i915_private *dev_priv = dev->dev_private;
4746         struct drm_plane *plane;
4747
4748         if (atomic->wait_vblank)
4749                 intel_wait_for_vblank(dev, crtc->pipe);
4750
4751         intel_frontbuffer_flip(dev, atomic->fb_bits);
4752
4753         if (atomic->disable_cxsr)
4754                 crtc->wm.cxsr_allowed = true;
4755
4756         if (crtc->atomic.update_wm_post)
4757                 intel_update_watermarks(&crtc->base);
4758
4759         if (atomic->update_fbc)
4760                 intel_fbc_update(dev_priv);
4761
4762         if (atomic->post_enable_primary)
4763                 intel_post_enable_primary(&crtc->base);
4764
4765         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4766                 intel_update_sprite_watermarks(plane, &crtc->base,
4767                                                0, 0, 0, false, false);
4768
4769         memset(atomic, 0, sizeof(*atomic));
4770 }
4771
4772 static void intel_pre_plane_update(struct intel_crtc *crtc)
4773 {
4774         struct drm_device *dev = crtc->base.dev;
4775         struct drm_i915_private *dev_priv = dev->dev_private;
4776         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4777         struct drm_plane *p;
4778
4779         /* Track fb's for any planes being disabled */
4780         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4781                 struct intel_plane *plane = to_intel_plane(p);
4782
4783                 mutex_lock(&dev->struct_mutex);
4784                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4785                                   plane->frontbuffer_bit);
4786                 mutex_unlock(&dev->struct_mutex);
4787         }
4788
4789         if (atomic->wait_for_flips)
4790                 intel_crtc_wait_for_pending_flips(&crtc->base);
4791
4792         if (atomic->disable_fbc)
4793                 intel_fbc_disable_crtc(crtc);
4794
4795         if (crtc->atomic.disable_ips)
4796                 hsw_disable_ips(crtc);
4797
4798         if (atomic->pre_disable_primary)
4799                 intel_pre_disable_primary(&crtc->base);
4800
4801         if (atomic->disable_cxsr) {
4802                 crtc->wm.cxsr_allowed = false;
4803                 intel_set_memory_cxsr(dev_priv, false);
4804         }
4805 }
4806
4807 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4808 {
4809         struct drm_device *dev = crtc->dev;
4810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4811         struct drm_plane *p;
4812         int pipe = intel_crtc->pipe;
4813
4814         intel_crtc_dpms_overlay_disable(intel_crtc);
4815
4816         drm_for_each_plane_mask(p, dev, plane_mask)
4817                 to_intel_plane(p)->disable_plane(p, crtc);
4818
4819         /*
4820          * FIXME: Once we grow proper nuclear flip support out of this we need
4821          * to compute the mask of flip planes precisely. For the time being
4822          * consider this a flip to a NULL plane.
4823          */
4824         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4825 }
4826
4827 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4828 {
4829         struct drm_device *dev = crtc->dev;
4830         struct drm_i915_private *dev_priv = dev->dev_private;
4831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832         struct intel_encoder *encoder;
4833         int pipe = intel_crtc->pipe;
4834
4835         if (WARN_ON(intel_crtc->active))
4836                 return;
4837
4838         if (intel_crtc->config->has_pch_encoder)
4839                 intel_prepare_shared_dpll(intel_crtc);
4840
4841         if (intel_crtc->config->has_dp_encoder)
4842                 intel_dp_set_m_n(intel_crtc, M1_N1);
4843
4844         intel_set_pipe_timings(intel_crtc);
4845
4846         if (intel_crtc->config->has_pch_encoder) {
4847                 intel_cpu_transcoder_set_m_n(intel_crtc,
4848                                      &intel_crtc->config->fdi_m_n, NULL);
4849         }
4850
4851         ironlake_set_pipeconf(crtc);
4852
4853         intel_crtc->active = true;
4854
4855         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4856         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4857
4858         for_each_encoder_on_crtc(dev, crtc, encoder)
4859                 if (encoder->pre_enable)
4860                         encoder->pre_enable(encoder);
4861
4862         if (intel_crtc->config->has_pch_encoder) {
4863                 /* Note: FDI PLL enabling _must_ be done before we enable the
4864                  * cpu pipes, hence this is separate from all the other fdi/pch
4865                  * enabling. */
4866                 ironlake_fdi_pll_enable(intel_crtc);
4867         } else {
4868                 assert_fdi_tx_disabled(dev_priv, pipe);
4869                 assert_fdi_rx_disabled(dev_priv, pipe);
4870         }
4871
4872         ironlake_pfit_enable(intel_crtc);
4873
4874         /*
4875          * On ILK+ LUT must be loaded before the pipe is running but with
4876          * clocks enabled
4877          */
4878         intel_crtc_load_lut(crtc);
4879
4880         intel_update_watermarks(crtc);
4881         intel_enable_pipe(intel_crtc);
4882
4883         if (intel_crtc->config->has_pch_encoder)
4884                 ironlake_pch_enable(crtc);
4885
4886         assert_vblank_disabled(crtc);
4887         drm_crtc_vblank_on(crtc);
4888
4889         for_each_encoder_on_crtc(dev, crtc, encoder)
4890                 encoder->enable(encoder);
4891
4892         if (HAS_PCH_CPT(dev))
4893                 cpt_verify_modeset(dev, intel_crtc->pipe);
4894 }
4895
4896 /* IPS only exists on ULT machines and is tied to pipe A. */
4897 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4898 {
4899         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4900 }
4901
4902 static void haswell_crtc_enable(struct drm_crtc *crtc)
4903 {
4904         struct drm_device *dev = crtc->dev;
4905         struct drm_i915_private *dev_priv = dev->dev_private;
4906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4907         struct intel_encoder *encoder;
4908         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4909         struct intel_crtc_state *pipe_config =
4910                 to_intel_crtc_state(crtc->state);
4911
4912         if (WARN_ON(intel_crtc->active))
4913                 return;
4914
4915         if (intel_crtc_to_shared_dpll(intel_crtc))
4916                 intel_enable_shared_dpll(intel_crtc);
4917
4918         if (intel_crtc->config->has_dp_encoder)
4919                 intel_dp_set_m_n(intel_crtc, M1_N1);
4920
4921         intel_set_pipe_timings(intel_crtc);
4922
4923         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4924                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4925                            intel_crtc->config->pixel_multiplier - 1);
4926         }
4927
4928         if (intel_crtc->config->has_pch_encoder) {
4929                 intel_cpu_transcoder_set_m_n(intel_crtc,
4930                                      &intel_crtc->config->fdi_m_n, NULL);
4931         }
4932
4933         haswell_set_pipeconf(crtc);
4934
4935         intel_set_pipe_csc(crtc);
4936
4937         intel_crtc->active = true;
4938
4939         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4940         for_each_encoder_on_crtc(dev, crtc, encoder)
4941                 if (encoder->pre_enable)
4942                         encoder->pre_enable(encoder);
4943
4944         if (intel_crtc->config->has_pch_encoder) {
4945                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4946                                                       true);
4947                 dev_priv->display.fdi_link_train(crtc);
4948         }
4949
4950         intel_ddi_enable_pipe_clock(intel_crtc);
4951
4952         if (INTEL_INFO(dev)->gen == 9)
4953                 skylake_pfit_enable(intel_crtc);
4954         else if (INTEL_INFO(dev)->gen < 9)
4955                 ironlake_pfit_enable(intel_crtc);
4956         else
4957                 MISSING_CASE(INTEL_INFO(dev)->gen);
4958
4959         /*
4960          * On ILK+ LUT must be loaded before the pipe is running but with
4961          * clocks enabled
4962          */
4963         intel_crtc_load_lut(crtc);
4964
4965         intel_ddi_set_pipe_settings(crtc);
4966         intel_ddi_enable_transcoder_func(crtc);
4967
4968         intel_update_watermarks(crtc);
4969         intel_enable_pipe(intel_crtc);
4970
4971         if (intel_crtc->config->has_pch_encoder)
4972                 lpt_pch_enable(crtc);
4973
4974         if (intel_crtc->config->dp_encoder_is_mst)
4975                 intel_ddi_set_vc_payload_alloc(crtc, true);
4976
4977         assert_vblank_disabled(crtc);
4978         drm_crtc_vblank_on(crtc);
4979
4980         for_each_encoder_on_crtc(dev, crtc, encoder) {
4981                 encoder->enable(encoder);
4982                 intel_opregion_notify_encoder(encoder, true);
4983         }
4984
4985         /* If we change the relative order between pipe/planes enabling, we need
4986          * to change the workaround. */
4987         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4988         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4989                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4990                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4991         }
4992 }
4993
4994 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4995 {
4996         struct drm_device *dev = crtc->base.dev;
4997         struct drm_i915_private *dev_priv = dev->dev_private;
4998         int pipe = crtc->pipe;
4999
5000         /* To avoid upsetting the power well on haswell only disable the pfit if
5001          * it's in use. The hw state code will make sure we get this right. */
5002         if (crtc->config->pch_pfit.enabled) {
5003                 I915_WRITE(PF_CTL(pipe), 0);
5004                 I915_WRITE(PF_WIN_POS(pipe), 0);
5005                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5006         }
5007 }
5008
5009 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5010 {
5011         struct drm_device *dev = crtc->dev;
5012         struct drm_i915_private *dev_priv = dev->dev_private;
5013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014         struct intel_encoder *encoder;
5015         int pipe = intel_crtc->pipe;
5016         u32 reg, temp;
5017
5018         for_each_encoder_on_crtc(dev, crtc, encoder)
5019                 encoder->disable(encoder);
5020
5021         drm_crtc_vblank_off(crtc);
5022         assert_vblank_disabled(crtc);
5023
5024         if (intel_crtc->config->has_pch_encoder)
5025                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5026
5027         intel_disable_pipe(intel_crtc);
5028
5029         ironlake_pfit_disable(intel_crtc);
5030
5031         if (intel_crtc->config->has_pch_encoder)
5032                 ironlake_fdi_disable(crtc);
5033
5034         for_each_encoder_on_crtc(dev, crtc, encoder)
5035                 if (encoder->post_disable)
5036                         encoder->post_disable(encoder);
5037
5038         if (intel_crtc->config->has_pch_encoder) {
5039                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5040
5041                 if (HAS_PCH_CPT(dev)) {
5042                         /* disable TRANS_DP_CTL */
5043                         reg = TRANS_DP_CTL(pipe);
5044                         temp = I915_READ(reg);
5045                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5046                                   TRANS_DP_PORT_SEL_MASK);
5047                         temp |= TRANS_DP_PORT_SEL_NONE;
5048                         I915_WRITE(reg, temp);
5049
5050                         /* disable DPLL_SEL */
5051                         temp = I915_READ(PCH_DPLL_SEL);
5052                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5053                         I915_WRITE(PCH_DPLL_SEL, temp);
5054                 }
5055
5056                 ironlake_fdi_pll_disable(intel_crtc);
5057         }
5058
5059         intel_crtc->active = false;
5060         intel_update_watermarks(crtc);
5061 }
5062
5063 static void haswell_crtc_disable(struct drm_crtc *crtc)
5064 {
5065         struct drm_device *dev = crtc->dev;
5066         struct drm_i915_private *dev_priv = dev->dev_private;
5067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068         struct intel_encoder *encoder;
5069         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5070
5071         for_each_encoder_on_crtc(dev, crtc, encoder) {
5072                 intel_opregion_notify_encoder(encoder, false);
5073                 encoder->disable(encoder);
5074         }
5075
5076         drm_crtc_vblank_off(crtc);
5077         assert_vblank_disabled(crtc);
5078
5079         if (intel_crtc->config->has_pch_encoder)
5080                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5081                                                       false);
5082         intel_disable_pipe(intel_crtc);
5083
5084         if (intel_crtc->config->dp_encoder_is_mst)
5085                 intel_ddi_set_vc_payload_alloc(crtc, false);
5086
5087         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5088
5089         if (INTEL_INFO(dev)->gen == 9)
5090                 skylake_scaler_disable(intel_crtc);
5091         else if (INTEL_INFO(dev)->gen < 9)
5092                 ironlake_pfit_disable(intel_crtc);
5093         else
5094                 MISSING_CASE(INTEL_INFO(dev)->gen);
5095
5096         intel_ddi_disable_pipe_clock(intel_crtc);
5097
5098         if (intel_crtc->config->has_pch_encoder) {
5099                 lpt_disable_pch_transcoder(dev_priv);
5100                 intel_ddi_fdi_disable(crtc);
5101         }
5102
5103         for_each_encoder_on_crtc(dev, crtc, encoder)
5104                 if (encoder->post_disable)
5105                         encoder->post_disable(encoder);
5106
5107         intel_crtc->active = false;
5108         intel_update_watermarks(crtc);
5109 }
5110
5111 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5112 {
5113         struct drm_device *dev = crtc->base.dev;
5114         struct drm_i915_private *dev_priv = dev->dev_private;
5115         struct intel_crtc_state *pipe_config = crtc->config;
5116
5117         if (!pipe_config->gmch_pfit.control)
5118                 return;
5119
5120         /*
5121          * The panel fitter should only be adjusted whilst the pipe is disabled,
5122          * according to register description and PRM.
5123          */
5124         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5125         assert_pipe_disabled(dev_priv, crtc->pipe);
5126
5127         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5128         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5129
5130         /* Border color in case we don't scale up to the full screen. Black by
5131          * default, change to something else for debugging. */
5132         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5133 }
5134
5135 static enum intel_display_power_domain port_to_power_domain(enum port port)
5136 {
5137         switch (port) {
5138         case PORT_A:
5139                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5140         case PORT_B:
5141                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5142         case PORT_C:
5143                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5144         case PORT_D:
5145                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5146         default:
5147                 WARN_ON_ONCE(1);
5148                 return POWER_DOMAIN_PORT_OTHER;
5149         }
5150 }
5151
5152 #define for_each_power_domain(domain, mask)                             \
5153         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5154                 if ((1 << (domain)) & (mask))
5155
5156 enum intel_display_power_domain
5157 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5158 {
5159         struct drm_device *dev = intel_encoder->base.dev;
5160         struct intel_digital_port *intel_dig_port;
5161
5162         switch (intel_encoder->type) {
5163         case INTEL_OUTPUT_UNKNOWN:
5164                 /* Only DDI platforms should ever use this output type */
5165                 WARN_ON_ONCE(!HAS_DDI(dev));
5166         case INTEL_OUTPUT_DISPLAYPORT:
5167         case INTEL_OUTPUT_HDMI:
5168         case INTEL_OUTPUT_EDP:
5169                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170                 return port_to_power_domain(intel_dig_port->port);
5171         case INTEL_OUTPUT_DP_MST:
5172                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173                 return port_to_power_domain(intel_dig_port->port);
5174         case INTEL_OUTPUT_ANALOG:
5175                 return POWER_DOMAIN_PORT_CRT;
5176         case INTEL_OUTPUT_DSI:
5177                 return POWER_DOMAIN_PORT_DSI;
5178         default:
5179                 return POWER_DOMAIN_PORT_OTHER;
5180         }
5181 }
5182
5183 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5184 {
5185         struct drm_device *dev = crtc->dev;
5186         struct intel_encoder *intel_encoder;
5187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188         enum pipe pipe = intel_crtc->pipe;
5189         unsigned long mask;
5190         enum transcoder transcoder;
5191
5192         if (!crtc->state->active)
5193                 return 0;
5194
5195         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5196
5197         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5198         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5199         if (intel_crtc->config->pch_pfit.enabled ||
5200             intel_crtc->config->pch_pfit.force_thru)
5201                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5202
5203         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5204                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5205
5206         return mask;
5207 }
5208
5209 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5210 {
5211         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5213         enum intel_display_power_domain domain;
5214         unsigned long domains, new_domains, old_domains;
5215
5216         old_domains = intel_crtc->enabled_power_domains;
5217         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5218
5219         domains = new_domains & ~old_domains;
5220
5221         for_each_power_domain(domain, domains)
5222                 intel_display_power_get(dev_priv, domain);
5223
5224         return old_domains & ~new_domains;
5225 }
5226
5227 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5228                                       unsigned long domains)
5229 {
5230         enum intel_display_power_domain domain;
5231
5232         for_each_power_domain(domain, domains)
5233                 intel_display_power_put(dev_priv, domain);
5234 }
5235
5236 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5237 {
5238         struct drm_device *dev = state->dev;
5239         struct drm_i915_private *dev_priv = dev->dev_private;
5240         unsigned long put_domains[I915_MAX_PIPES] = {};
5241         struct drm_crtc_state *crtc_state;
5242         struct drm_crtc *crtc;
5243         int i;
5244
5245         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5246                 if (needs_modeset(crtc->state))
5247                         put_domains[to_intel_crtc(crtc)->pipe] =
5248                                 modeset_get_crtc_power_domains(crtc);
5249         }
5250
5251         if (dev_priv->display.modeset_commit_cdclk) {
5252                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5253
5254                 if (cdclk != dev_priv->cdclk_freq &&
5255                     !WARN_ON(!state->allow_modeset))
5256                         dev_priv->display.modeset_commit_cdclk(state);
5257         }
5258
5259         for (i = 0; i < I915_MAX_PIPES; i++)
5260                 if (put_domains[i])
5261                         modeset_put_power_domains(dev_priv, put_domains[i]);
5262 }
5263
5264 static void intel_update_max_cdclk(struct drm_device *dev)
5265 {
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267
5268         if (IS_SKYLAKE(dev)) {
5269                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5270
5271                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5272                         dev_priv->max_cdclk_freq = 675000;
5273                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5274                         dev_priv->max_cdclk_freq = 540000;
5275                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5276                         dev_priv->max_cdclk_freq = 450000;
5277                 else
5278                         dev_priv->max_cdclk_freq = 337500;
5279         } else if (IS_BROADWELL(dev))  {
5280                 /*
5281                  * FIXME with extra cooling we can allow
5282                  * 540 MHz for ULX and 675 Mhz for ULT.
5283                  * How can we know if extra cooling is
5284                  * available? PCI ID, VTB, something else?
5285                  */
5286                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5287                         dev_priv->max_cdclk_freq = 450000;
5288                 else if (IS_BDW_ULX(dev))
5289                         dev_priv->max_cdclk_freq = 450000;
5290                 else if (IS_BDW_ULT(dev))
5291                         dev_priv->max_cdclk_freq = 540000;
5292                 else
5293                         dev_priv->max_cdclk_freq = 675000;
5294         } else if (IS_CHERRYVIEW(dev)) {
5295                 dev_priv->max_cdclk_freq = 320000;
5296         } else if (IS_VALLEYVIEW(dev)) {
5297                 dev_priv->max_cdclk_freq = 400000;
5298         } else {
5299                 /* otherwise assume cdclk is fixed */
5300                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5301         }
5302
5303         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5304                          dev_priv->max_cdclk_freq);
5305 }
5306
5307 static void intel_update_cdclk(struct drm_device *dev)
5308 {
5309         struct drm_i915_private *dev_priv = dev->dev_private;
5310
5311         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5312         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5313                          dev_priv->cdclk_freq);
5314
5315         /*
5316          * Program the gmbus_freq based on the cdclk frequency.
5317          * BSpec erroneously claims we should aim for 4MHz, but
5318          * in fact 1MHz is the correct frequency.
5319          */
5320         if (IS_VALLEYVIEW(dev)) {
5321                 /*
5322                  * Program the gmbus_freq based on the cdclk frequency.
5323                  * BSpec erroneously claims we should aim for 4MHz, but
5324                  * in fact 1MHz is the correct frequency.
5325                  */
5326                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5327         }
5328
5329         if (dev_priv->max_cdclk_freq == 0)
5330                 intel_update_max_cdclk(dev);
5331 }
5332
5333 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5334 {
5335         struct drm_i915_private *dev_priv = dev->dev_private;
5336         uint32_t divider;
5337         uint32_t ratio;
5338         uint32_t current_freq;
5339         int ret;
5340
5341         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5342         switch (frequency) {
5343         case 144000:
5344                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5345                 ratio = BXT_DE_PLL_RATIO(60);
5346                 break;
5347         case 288000:
5348                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5349                 ratio = BXT_DE_PLL_RATIO(60);
5350                 break;
5351         case 384000:
5352                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5353                 ratio = BXT_DE_PLL_RATIO(60);
5354                 break;
5355         case 576000:
5356                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5357                 ratio = BXT_DE_PLL_RATIO(60);
5358                 break;
5359         case 624000:
5360                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5361                 ratio = BXT_DE_PLL_RATIO(65);
5362                 break;
5363         case 19200:
5364                 /*
5365                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5366                  * to suppress GCC warning.
5367                  */
5368                 ratio = 0;
5369                 divider = 0;
5370                 break;
5371         default:
5372                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5373
5374                 return;
5375         }
5376
5377         mutex_lock(&dev_priv->rps.hw_lock);
5378         /* Inform power controller of upcoming frequency change */
5379         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5380                                       0x80000000);
5381         mutex_unlock(&dev_priv->rps.hw_lock);
5382
5383         if (ret) {
5384                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5385                           ret, frequency);
5386                 return;
5387         }
5388
5389         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5390         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5391         current_freq = current_freq * 500 + 1000;
5392
5393         /*
5394          * DE PLL has to be disabled when
5395          * - setting to 19.2MHz (bypass, PLL isn't used)
5396          * - before setting to 624MHz (PLL needs toggling)
5397          * - before setting to any frequency from 624MHz (PLL needs toggling)
5398          */
5399         if (frequency == 19200 || frequency == 624000 ||
5400             current_freq == 624000) {
5401                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5402                 /* Timeout 200us */
5403                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5404                              1))
5405                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5406         }
5407
5408         if (frequency != 19200) {
5409                 uint32_t val;
5410
5411                 val = I915_READ(BXT_DE_PLL_CTL);
5412                 val &= ~BXT_DE_PLL_RATIO_MASK;
5413                 val |= ratio;
5414                 I915_WRITE(BXT_DE_PLL_CTL, val);
5415
5416                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5417                 /* Timeout 200us */
5418                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5419                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5420
5421                 val = I915_READ(CDCLK_CTL);
5422                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5423                 val |= divider;
5424                 /*
5425                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5426                  * enable otherwise.
5427                  */
5428                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429                 if (frequency >= 500000)
5430                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5431
5432                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5433                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5434                 val |= (frequency - 1000) / 500;
5435                 I915_WRITE(CDCLK_CTL, val);
5436         }
5437
5438         mutex_lock(&dev_priv->rps.hw_lock);
5439         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5440                                       DIV_ROUND_UP(frequency, 25000));
5441         mutex_unlock(&dev_priv->rps.hw_lock);
5442
5443         if (ret) {
5444                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5445                           ret, frequency);
5446                 return;
5447         }
5448
5449         intel_update_cdclk(dev);
5450 }
5451
5452 void broxton_init_cdclk(struct drm_device *dev)
5453 {
5454         struct drm_i915_private *dev_priv = dev->dev_private;
5455         uint32_t val;
5456
5457         /*
5458          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5459          * or else the reset will hang because there is no PCH to respond.
5460          * Move the handshake programming to initialization sequence.
5461          * Previously was left up to BIOS.
5462          */
5463         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5464         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5465         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5466
5467         /* Enable PG1 for cdclk */
5468         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5469
5470         /* check if cd clock is enabled */
5471         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5472                 DRM_DEBUG_KMS("Display already initialized\n");
5473                 return;
5474         }
5475
5476         /*
5477          * FIXME:
5478          * - The initial CDCLK needs to be read from VBT.
5479          *   Need to make this change after VBT has changes for BXT.
5480          * - check if setting the max (or any) cdclk freq is really necessary
5481          *   here, it belongs to modeset time
5482          */
5483         broxton_set_cdclk(dev, 624000);
5484
5485         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5486         POSTING_READ(DBUF_CTL);
5487
5488         udelay(10);
5489
5490         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5491                 DRM_ERROR("DBuf power enable timeout!\n");
5492 }
5493
5494 void broxton_uninit_cdclk(struct drm_device *dev)
5495 {
5496         struct drm_i915_private *dev_priv = dev->dev_private;
5497
5498         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5499         POSTING_READ(DBUF_CTL);
5500
5501         udelay(10);
5502
5503         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5504                 DRM_ERROR("DBuf power disable timeout!\n");
5505
5506         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5507         broxton_set_cdclk(dev, 19200);
5508
5509         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5510 }
5511
5512 static const struct skl_cdclk_entry {
5513         unsigned int freq;
5514         unsigned int vco;
5515 } skl_cdclk_frequencies[] = {
5516         { .freq = 308570, .vco = 8640 },
5517         { .freq = 337500, .vco = 8100 },
5518         { .freq = 432000, .vco = 8640 },
5519         { .freq = 450000, .vco = 8100 },
5520         { .freq = 540000, .vco = 8100 },
5521         { .freq = 617140, .vco = 8640 },
5522         { .freq = 675000, .vco = 8100 },
5523 };
5524
5525 static unsigned int skl_cdclk_decimal(unsigned int freq)
5526 {
5527         return (freq - 1000) / 500;
5528 }
5529
5530 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5531 {
5532         unsigned int i;
5533
5534         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5535                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5536
5537                 if (e->freq == freq)
5538                         return e->vco;
5539         }
5540
5541         return 8100;
5542 }
5543
5544 static void
5545 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5546 {
5547         unsigned int min_freq;
5548         u32 val;
5549
5550         /* select the minimum CDCLK before enabling DPLL 0 */
5551         val = I915_READ(CDCLK_CTL);
5552         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5553         val |= CDCLK_FREQ_337_308;
5554
5555         if (required_vco == 8640)
5556                 min_freq = 308570;
5557         else
5558                 min_freq = 337500;
5559
5560         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5561
5562         I915_WRITE(CDCLK_CTL, val);
5563         POSTING_READ(CDCLK_CTL);
5564
5565         /*
5566          * We always enable DPLL0 with the lowest link rate possible, but still
5567          * taking into account the VCO required to operate the eDP panel at the
5568          * desired frequency. The usual DP link rates operate with a VCO of
5569          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5570          * The modeset code is responsible for the selection of the exact link
5571          * rate later on, with the constraint of choosing a frequency that
5572          * works with required_vco.
5573          */
5574         val = I915_READ(DPLL_CTRL1);
5575
5576         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5577                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5578         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5579         if (required_vco == 8640)
5580                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5581                                             SKL_DPLL0);
5582         else
5583                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5584                                             SKL_DPLL0);
5585
5586         I915_WRITE(DPLL_CTRL1, val);
5587         POSTING_READ(DPLL_CTRL1);
5588
5589         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5590
5591         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5592                 DRM_ERROR("DPLL0 not locked\n");
5593 }
5594
5595 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5596 {
5597         int ret;
5598         u32 val;
5599
5600         /* inform PCU we want to change CDCLK */
5601         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5602         mutex_lock(&dev_priv->rps.hw_lock);
5603         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5604         mutex_unlock(&dev_priv->rps.hw_lock);
5605
5606         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5607 }
5608
5609 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5610 {
5611         unsigned int i;
5612
5613         for (i = 0; i < 15; i++) {
5614                 if (skl_cdclk_pcu_ready(dev_priv))
5615                         return true;
5616                 udelay(10);
5617         }
5618
5619         return false;
5620 }
5621
5622 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5623 {
5624         struct drm_device *dev = dev_priv->dev;
5625         u32 freq_select, pcu_ack;
5626
5627         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5628
5629         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5630                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5631                 return;
5632         }
5633
5634         /* set CDCLK_CTL */
5635         switch(freq) {
5636         case 450000:
5637         case 432000:
5638                 freq_select = CDCLK_FREQ_450_432;
5639                 pcu_ack = 1;
5640                 break;
5641         case 540000:
5642                 freq_select = CDCLK_FREQ_540;
5643                 pcu_ack = 2;
5644                 break;
5645         case 308570:
5646         case 337500:
5647         default:
5648                 freq_select = CDCLK_FREQ_337_308;
5649                 pcu_ack = 0;
5650                 break;
5651         case 617140:
5652         case 675000:
5653                 freq_select = CDCLK_FREQ_675_617;
5654                 pcu_ack = 3;
5655                 break;
5656         }
5657
5658         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5659         POSTING_READ(CDCLK_CTL);
5660
5661         /* inform PCU of the change */
5662         mutex_lock(&dev_priv->rps.hw_lock);
5663         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5664         mutex_unlock(&dev_priv->rps.hw_lock);
5665
5666         intel_update_cdclk(dev);
5667 }
5668
5669 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5670 {
5671         /* disable DBUF power */
5672         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5673         POSTING_READ(DBUF_CTL);
5674
5675         udelay(10);
5676
5677         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5678                 DRM_ERROR("DBuf power disable timeout\n");
5679
5680         /* disable DPLL0 */
5681         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5682         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5683                 DRM_ERROR("Couldn't disable DPLL0\n");
5684
5685         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5686 }
5687
5688 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5689 {
5690         u32 val;
5691         unsigned int required_vco;
5692
5693         /* enable PCH reset handshake */
5694         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5695         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5696
5697         /* enable PG1 and Misc I/O */
5698         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5699
5700         /* DPLL0 already enabed !? */
5701         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5702                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5703                 return;
5704         }
5705
5706         /* enable DPLL0 */
5707         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5708         skl_dpll0_enable(dev_priv, required_vco);
5709
5710         /* set CDCLK to the frequency the BIOS chose */
5711         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5712
5713         /* enable DBUF power */
5714         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5715         POSTING_READ(DBUF_CTL);
5716
5717         udelay(10);
5718
5719         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5720                 DRM_ERROR("DBuf power enable timeout\n");
5721 }
5722
5723 /* returns HPLL frequency in kHz */
5724 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5725 {
5726         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5727
5728         /* Obtain SKU information */
5729         mutex_lock(&dev_priv->sb_lock);
5730         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5731                 CCK_FUSE_HPLL_FREQ_MASK;
5732         mutex_unlock(&dev_priv->sb_lock);
5733
5734         return vco_freq[hpll_freq] * 1000;
5735 }
5736
5737 /* Adjust CDclk dividers to allow high res or save power if possible */
5738 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5739 {
5740         struct drm_i915_private *dev_priv = dev->dev_private;
5741         u32 val, cmd;
5742
5743         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5744                                         != dev_priv->cdclk_freq);
5745
5746         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5747                 cmd = 2;
5748         else if (cdclk == 266667)
5749                 cmd = 1;
5750         else
5751                 cmd = 0;
5752
5753         mutex_lock(&dev_priv->rps.hw_lock);
5754         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5755         val &= ~DSPFREQGUAR_MASK;
5756         val |= (cmd << DSPFREQGUAR_SHIFT);
5757         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5758         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5759                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5760                      50)) {
5761                 DRM_ERROR("timed out waiting for CDclk change\n");
5762         }
5763         mutex_unlock(&dev_priv->rps.hw_lock);
5764
5765         mutex_lock(&dev_priv->sb_lock);
5766
5767         if (cdclk == 400000) {
5768                 u32 divider;
5769
5770                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5771
5772                 /* adjust cdclk divider */
5773                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5774                 val &= ~DISPLAY_FREQUENCY_VALUES;
5775                 val |= divider;
5776                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5777
5778                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5779                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5780                              50))
5781                         DRM_ERROR("timed out waiting for CDclk change\n");
5782         }
5783
5784         /* adjust self-refresh exit latency value */
5785         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5786         val &= ~0x7f;
5787
5788         /*
5789          * For high bandwidth configs, we set a higher latency in the bunit
5790          * so that the core display fetch happens in time to avoid underruns.
5791          */
5792         if (cdclk == 400000)
5793                 val |= 4500 / 250; /* 4.5 usec */
5794         else
5795                 val |= 3000 / 250; /* 3.0 usec */
5796         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5797
5798         mutex_unlock(&dev_priv->sb_lock);
5799
5800         intel_update_cdclk(dev);
5801 }
5802
5803 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5804 {
5805         struct drm_i915_private *dev_priv = dev->dev_private;
5806         u32 val, cmd;
5807
5808         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5809                                                 != dev_priv->cdclk_freq);
5810
5811         switch (cdclk) {
5812         case 333333:
5813         case 320000:
5814         case 266667:
5815         case 200000:
5816                 break;
5817         default:
5818                 MISSING_CASE(cdclk);
5819                 return;
5820         }
5821
5822         /*
5823          * Specs are full of misinformation, but testing on actual
5824          * hardware has shown that we just need to write the desired
5825          * CCK divider into the Punit register.
5826          */
5827         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5828
5829         mutex_lock(&dev_priv->rps.hw_lock);
5830         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5831         val &= ~DSPFREQGUAR_MASK_CHV;
5832         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5833         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5834         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5835                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5836                      50)) {
5837                 DRM_ERROR("timed out waiting for CDclk change\n");
5838         }
5839         mutex_unlock(&dev_priv->rps.hw_lock);
5840
5841         intel_update_cdclk(dev);
5842 }
5843
5844 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5845                                  int max_pixclk)
5846 {
5847         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5848         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5849
5850         /*
5851          * Really only a few cases to deal with, as only 4 CDclks are supported:
5852          *   200MHz
5853          *   267MHz
5854          *   320/333MHz (depends on HPLL freq)
5855          *   400MHz (VLV only)
5856          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5857          * of the lower bin and adjust if needed.
5858          *
5859          * We seem to get an unstable or solid color picture at 200MHz.
5860          * Not sure what's wrong. For now use 200MHz only when all pipes
5861          * are off.
5862          */
5863         if (!IS_CHERRYVIEW(dev_priv) &&
5864             max_pixclk > freq_320*limit/100)
5865                 return 400000;
5866         else if (max_pixclk > 266667*limit/100)
5867                 return freq_320;
5868         else if (max_pixclk > 0)
5869                 return 266667;
5870         else
5871                 return 200000;
5872 }
5873
5874 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5875                               int max_pixclk)
5876 {
5877         /*
5878          * FIXME:
5879          * - remove the guardband, it's not needed on BXT
5880          * - set 19.2MHz bypass frequency if there are no active pipes
5881          */
5882         if (max_pixclk > 576000*9/10)
5883                 return 624000;
5884         else if (max_pixclk > 384000*9/10)
5885                 return 576000;
5886         else if (max_pixclk > 288000*9/10)
5887                 return 384000;
5888         else if (max_pixclk > 144000*9/10)
5889                 return 288000;
5890         else
5891                 return 144000;
5892 }
5893
5894 /* Compute the max pixel clock for new configuration. Uses atomic state if
5895  * that's non-NULL, look at current state otherwise. */
5896 static int intel_mode_max_pixclk(struct drm_device *dev,
5897                                  struct drm_atomic_state *state)
5898 {
5899         struct intel_crtc *intel_crtc;
5900         struct intel_crtc_state *crtc_state;
5901         int max_pixclk = 0;
5902
5903         for_each_intel_crtc(dev, intel_crtc) {
5904                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5905                 if (IS_ERR(crtc_state))
5906                         return PTR_ERR(crtc_state);
5907
5908                 if (!crtc_state->base.enable)
5909                         continue;
5910
5911                 max_pixclk = max(max_pixclk,
5912                                  crtc_state->base.adjusted_mode.crtc_clock);
5913         }
5914
5915         return max_pixclk;
5916 }
5917
5918 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5919 {
5920         struct drm_device *dev = state->dev;
5921         struct drm_i915_private *dev_priv = dev->dev_private;
5922         int max_pixclk = intel_mode_max_pixclk(dev, state);
5923
5924         if (max_pixclk < 0)
5925                 return max_pixclk;
5926
5927         to_intel_atomic_state(state)->cdclk =
5928                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5929
5930         return 0;
5931 }
5932
5933 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5934 {
5935         struct drm_device *dev = state->dev;
5936         struct drm_i915_private *dev_priv = dev->dev_private;
5937         int max_pixclk = intel_mode_max_pixclk(dev, state);
5938
5939         if (max_pixclk < 0)
5940                 return max_pixclk;
5941
5942         to_intel_atomic_state(state)->cdclk =
5943                 broxton_calc_cdclk(dev_priv, max_pixclk);
5944
5945         return 0;
5946 }
5947
5948 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5949 {
5950         unsigned int credits, default_credits;
5951
5952         if (IS_CHERRYVIEW(dev_priv))
5953                 default_credits = PFI_CREDIT(12);
5954         else
5955                 default_credits = PFI_CREDIT(8);
5956
5957         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5958                 /* CHV suggested value is 31 or 63 */
5959                 if (IS_CHERRYVIEW(dev_priv))
5960                         credits = PFI_CREDIT_63;
5961                 else
5962                         credits = PFI_CREDIT(15);
5963         } else {
5964                 credits = default_credits;
5965         }
5966
5967         /*
5968          * WA - write default credits before re-programming
5969          * FIXME: should we also set the resend bit here?
5970          */
5971         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5972                    default_credits);
5973
5974         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5975                    credits | PFI_CREDIT_RESEND);
5976
5977         /*
5978          * FIXME is this guaranteed to clear
5979          * immediately or should we poll for it?
5980          */
5981         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5982 }
5983
5984 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5985 {
5986         struct drm_device *dev = old_state->dev;
5987         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5988         struct drm_i915_private *dev_priv = dev->dev_private;
5989
5990         /*
5991          * FIXME: We can end up here with all power domains off, yet
5992          * with a CDCLK frequency other than the minimum. To account
5993          * for this take the PIPE-A power domain, which covers the HW
5994          * blocks needed for the following programming. This can be
5995          * removed once it's guaranteed that we get here either with
5996          * the minimum CDCLK set, or the required power domains
5997          * enabled.
5998          */
5999         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6000
6001         if (IS_CHERRYVIEW(dev))
6002                 cherryview_set_cdclk(dev, req_cdclk);
6003         else
6004                 valleyview_set_cdclk(dev, req_cdclk);
6005
6006         vlv_program_pfi_credits(dev_priv);
6007
6008         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6009 }
6010
6011 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6012 {
6013         struct drm_device *dev = crtc->dev;
6014         struct drm_i915_private *dev_priv = to_i915(dev);
6015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6016         struct intel_encoder *encoder;
6017         int pipe = intel_crtc->pipe;
6018         bool is_dsi;
6019
6020         if (WARN_ON(intel_crtc->active))
6021                 return;
6022
6023         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6024
6025         if (!is_dsi) {
6026                 if (IS_CHERRYVIEW(dev))
6027                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6028                 else
6029                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6030         }
6031
6032         if (intel_crtc->config->has_dp_encoder)
6033                 intel_dp_set_m_n(intel_crtc, M1_N1);
6034
6035         intel_set_pipe_timings(intel_crtc);
6036
6037         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6038                 struct drm_i915_private *dev_priv = dev->dev_private;
6039
6040                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6041                 I915_WRITE(CHV_CANVAS(pipe), 0);
6042         }
6043
6044         i9xx_set_pipeconf(intel_crtc);
6045
6046         intel_crtc->active = true;
6047
6048         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6049
6050         for_each_encoder_on_crtc(dev, crtc, encoder)
6051                 if (encoder->pre_pll_enable)
6052                         encoder->pre_pll_enable(encoder);
6053
6054         if (!is_dsi) {
6055                 if (IS_CHERRYVIEW(dev))
6056                         chv_enable_pll(intel_crtc, intel_crtc->config);
6057                 else
6058                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6059         }
6060
6061         for_each_encoder_on_crtc(dev, crtc, encoder)
6062                 if (encoder->pre_enable)
6063                         encoder->pre_enable(encoder);
6064
6065         i9xx_pfit_enable(intel_crtc);
6066
6067         intel_crtc_load_lut(crtc);
6068
6069         intel_enable_pipe(intel_crtc);
6070
6071         assert_vblank_disabled(crtc);
6072         drm_crtc_vblank_on(crtc);
6073
6074         for_each_encoder_on_crtc(dev, crtc, encoder)
6075                 encoder->enable(encoder);
6076 }
6077
6078 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6079 {
6080         struct drm_device *dev = crtc->base.dev;
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082
6083         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6084         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6085 }
6086
6087 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6088 {
6089         struct drm_device *dev = crtc->dev;
6090         struct drm_i915_private *dev_priv = to_i915(dev);
6091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6092         struct intel_encoder *encoder;
6093         int pipe = intel_crtc->pipe;
6094
6095         if (WARN_ON(intel_crtc->active))
6096                 return;
6097
6098         i9xx_set_pll_dividers(intel_crtc);
6099
6100         if (intel_crtc->config->has_dp_encoder)
6101                 intel_dp_set_m_n(intel_crtc, M1_N1);
6102
6103         intel_set_pipe_timings(intel_crtc);
6104
6105         i9xx_set_pipeconf(intel_crtc);
6106
6107         intel_crtc->active = true;
6108
6109         if (!IS_GEN2(dev))
6110                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6111
6112         for_each_encoder_on_crtc(dev, crtc, encoder)
6113                 if (encoder->pre_enable)
6114                         encoder->pre_enable(encoder);
6115
6116         i9xx_enable_pll(intel_crtc);
6117
6118         i9xx_pfit_enable(intel_crtc);
6119
6120         intel_crtc_load_lut(crtc);
6121
6122         intel_update_watermarks(crtc);
6123         intel_enable_pipe(intel_crtc);
6124
6125         assert_vblank_disabled(crtc);
6126         drm_crtc_vblank_on(crtc);
6127
6128         for_each_encoder_on_crtc(dev, crtc, encoder)
6129                 encoder->enable(encoder);
6130 }
6131
6132 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6133 {
6134         struct drm_device *dev = crtc->base.dev;
6135         struct drm_i915_private *dev_priv = dev->dev_private;
6136
6137         if (!crtc->config->gmch_pfit.control)
6138                 return;
6139
6140         assert_pipe_disabled(dev_priv, crtc->pipe);
6141
6142         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6143                          I915_READ(PFIT_CONTROL));
6144         I915_WRITE(PFIT_CONTROL, 0);
6145 }
6146
6147 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6148 {
6149         struct drm_device *dev = crtc->dev;
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152         struct intel_encoder *encoder;
6153         int pipe = intel_crtc->pipe;
6154
6155         /*
6156          * On gen2 planes are double buffered but the pipe isn't, so we must
6157          * wait for planes to fully turn off before disabling the pipe.
6158          * We also need to wait on all gmch platforms because of the
6159          * self-refresh mode constraint explained above.
6160          */
6161         intel_wait_for_vblank(dev, pipe);
6162
6163         for_each_encoder_on_crtc(dev, crtc, encoder)
6164                 encoder->disable(encoder);
6165
6166         drm_crtc_vblank_off(crtc);
6167         assert_vblank_disabled(crtc);
6168
6169         intel_disable_pipe(intel_crtc);
6170
6171         i9xx_pfit_disable(intel_crtc);
6172
6173         for_each_encoder_on_crtc(dev, crtc, encoder)
6174                 if (encoder->post_disable)
6175                         encoder->post_disable(encoder);
6176
6177         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6178                 if (IS_CHERRYVIEW(dev))
6179                         chv_disable_pll(dev_priv, pipe);
6180                 else if (IS_VALLEYVIEW(dev))
6181                         vlv_disable_pll(dev_priv, pipe);
6182                 else
6183                         i9xx_disable_pll(intel_crtc);
6184         }
6185
6186         if (!IS_GEN2(dev))
6187                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6188
6189         intel_crtc->active = false;
6190         intel_update_watermarks(crtc);
6191 }
6192
6193 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6194 {
6195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6197         enum intel_display_power_domain domain;
6198         unsigned long domains;
6199
6200         if (!intel_crtc->active)
6201                 return;
6202
6203         if (to_intel_plane_state(crtc->primary->state)->visible) {
6204                 intel_crtc_wait_for_pending_flips(crtc);
6205                 intel_pre_disable_primary(crtc);
6206         }
6207
6208         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6209         dev_priv->display.crtc_disable(crtc);
6210         intel_disable_shared_dpll(intel_crtc);
6211
6212         domains = intel_crtc->enabled_power_domains;
6213         for_each_power_domain(domain, domains)
6214                 intel_display_power_put(dev_priv, domain);
6215         intel_crtc->enabled_power_domains = 0;
6216 }
6217
6218 /*
6219  * turn all crtc's off, but do not adjust state
6220  * This has to be paired with a call to intel_modeset_setup_hw_state.
6221  */
6222 int intel_display_suspend(struct drm_device *dev)
6223 {
6224         struct drm_mode_config *config = &dev->mode_config;
6225         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6226         struct drm_atomic_state *state;
6227         struct drm_crtc *crtc;
6228         unsigned crtc_mask = 0;
6229         int ret = 0;
6230
6231         if (WARN_ON(!ctx))
6232                 return 0;
6233
6234         lockdep_assert_held(&ctx->ww_ctx);
6235         state = drm_atomic_state_alloc(dev);
6236         if (WARN_ON(!state))
6237                 return -ENOMEM;
6238
6239         state->acquire_ctx = ctx;
6240         state->allow_modeset = true;
6241
6242         for_each_crtc(dev, crtc) {
6243                 struct drm_crtc_state *crtc_state =
6244                         drm_atomic_get_crtc_state(state, crtc);
6245
6246                 ret = PTR_ERR_OR_ZERO(crtc_state);
6247                 if (ret)
6248                         goto free;
6249
6250                 if (!crtc_state->active)
6251                         continue;
6252
6253                 crtc_state->active = false;
6254                 crtc_mask |= 1 << drm_crtc_index(crtc);
6255         }
6256
6257         if (crtc_mask) {
6258                 ret = drm_atomic_commit(state);
6259
6260                 if (!ret) {
6261                         for_each_crtc(dev, crtc)
6262                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6263                                         crtc->state->active = true;
6264
6265                         return ret;
6266                 }
6267         }
6268
6269 free:
6270         if (ret)
6271                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6272         drm_atomic_state_free(state);
6273         return ret;
6274 }
6275
6276 /* Master function to enable/disable CRTC and corresponding power wells */
6277 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6278 {
6279         struct drm_device *dev = crtc->dev;
6280         struct drm_mode_config *config = &dev->mode_config;
6281         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6283         struct intel_crtc_state *pipe_config;
6284         struct drm_atomic_state *state;
6285         int ret;
6286
6287         if (enable == intel_crtc->active)
6288                 return 0;
6289
6290         if (enable && !crtc->state->enable)
6291                 return 0;
6292
6293         /* this function should be called with drm_modeset_lock_all for now */
6294         if (WARN_ON(!ctx))
6295                 return -EIO;
6296         lockdep_assert_held(&ctx->ww_ctx);
6297
6298         state = drm_atomic_state_alloc(dev);
6299         if (WARN_ON(!state))
6300                 return -ENOMEM;
6301
6302         state->acquire_ctx = ctx;
6303         state->allow_modeset = true;
6304
6305         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6306         if (IS_ERR(pipe_config)) {
6307                 ret = PTR_ERR(pipe_config);
6308                 goto err;
6309         }
6310         pipe_config->base.active = enable;
6311
6312         ret = drm_atomic_commit(state);
6313         if (!ret)
6314                 return ret;
6315
6316 err:
6317         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6318         drm_atomic_state_free(state);
6319         return ret;
6320 }
6321
6322 /**
6323  * Sets the power management mode of the pipe and plane.
6324  */
6325 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6326 {
6327         struct drm_device *dev = crtc->dev;
6328         struct intel_encoder *intel_encoder;
6329         bool enable = false;
6330
6331         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6332                 enable |= intel_encoder->connectors_active;
6333
6334         intel_crtc_control(crtc, enable);
6335 }
6336
6337 void intel_encoder_destroy(struct drm_encoder *encoder)
6338 {
6339         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6340
6341         drm_encoder_cleanup(encoder);
6342         kfree(intel_encoder);
6343 }
6344
6345 /* Simple dpms helper for encoders with just one connector, no cloning and only
6346  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6347  * state of the entire output pipe. */
6348 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6349 {
6350         if (mode == DRM_MODE_DPMS_ON) {
6351                 encoder->connectors_active = true;
6352
6353                 intel_crtc_update_dpms(encoder->base.crtc);
6354         } else {
6355                 encoder->connectors_active = false;
6356
6357                 intel_crtc_update_dpms(encoder->base.crtc);
6358         }
6359 }
6360
6361 /* Cross check the actual hw state with our own modeset state tracking (and it's
6362  * internal consistency). */
6363 static void intel_connector_check_state(struct intel_connector *connector)
6364 {
6365         if (connector->get_hw_state(connector)) {
6366                 struct intel_encoder *encoder = connector->encoder;
6367                 struct drm_crtc *crtc;
6368                 bool encoder_enabled;
6369                 enum pipe pipe;
6370
6371                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6372                               connector->base.base.id,
6373                               connector->base.name);
6374
6375                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6376                      "wrong connector dpms state\n");
6377                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6378                      "active connector not linked to encoder\n");
6379
6380                 if (encoder) {
6381                         I915_STATE_WARN(!encoder->connectors_active,
6382                              "encoder->connectors_active not set\n");
6383
6384                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6385                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6386                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6387                                 return;
6388
6389                         crtc = encoder->base.crtc;
6390
6391                         I915_STATE_WARN(!crtc->state->enable,
6392                                         "crtc not enabled\n");
6393                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6394                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6395                              "encoder active on the wrong pipe\n");
6396                 }
6397         }
6398 }
6399
6400 int intel_connector_init(struct intel_connector *connector)
6401 {
6402         struct drm_connector_state *connector_state;
6403
6404         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6405         if (!connector_state)
6406                 return -ENOMEM;
6407
6408         connector->base.state = connector_state;
6409         return 0;
6410 }
6411
6412 struct intel_connector *intel_connector_alloc(void)
6413 {
6414         struct intel_connector *connector;
6415
6416         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6417         if (!connector)
6418                 return NULL;
6419
6420         if (intel_connector_init(connector) < 0) {
6421                 kfree(connector);
6422                 return NULL;
6423         }
6424
6425         return connector;
6426 }
6427
6428 /* Even simpler default implementation, if there's really no special case to
6429  * consider. */
6430 int intel_connector_dpms(struct drm_connector *connector, int mode)
6431 {
6432         /* All the simple cases only support two dpms states. */
6433         if (mode != DRM_MODE_DPMS_ON)
6434                 mode = DRM_MODE_DPMS_OFF;
6435
6436         if (mode == connector->dpms)
6437                 return 0;
6438
6439         connector->dpms = mode;
6440
6441         /* Only need to change hw state when actually enabled */
6442         if (connector->encoder)
6443                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6444
6445         return 0;
6446 }
6447
6448 /* Simple connector->get_hw_state implementation for encoders that support only
6449  * one connector and no cloning and hence the encoder state determines the state
6450  * of the connector. */
6451 bool intel_connector_get_hw_state(struct intel_connector *connector)
6452 {
6453         enum pipe pipe = 0;
6454         struct intel_encoder *encoder = connector->encoder;
6455
6456         return encoder->get_hw_state(encoder, &pipe);
6457 }
6458
6459 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6460 {
6461         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6462                 return crtc_state->fdi_lanes;
6463
6464         return 0;
6465 }
6466
6467 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6468                                      struct intel_crtc_state *pipe_config)
6469 {
6470         struct drm_atomic_state *state = pipe_config->base.state;
6471         struct intel_crtc *other_crtc;
6472         struct intel_crtc_state *other_crtc_state;
6473
6474         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6475                       pipe_name(pipe), pipe_config->fdi_lanes);
6476         if (pipe_config->fdi_lanes > 4) {
6477                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6478                               pipe_name(pipe), pipe_config->fdi_lanes);
6479                 return -EINVAL;
6480         }
6481
6482         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6483                 if (pipe_config->fdi_lanes > 2) {
6484                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6485                                       pipe_config->fdi_lanes);
6486                         return -EINVAL;
6487                 } else {
6488                         return 0;
6489                 }
6490         }
6491
6492         if (INTEL_INFO(dev)->num_pipes == 2)
6493                 return 0;
6494
6495         /* Ivybridge 3 pipe is really complicated */
6496         switch (pipe) {
6497         case PIPE_A:
6498                 return 0;
6499         case PIPE_B:
6500                 if (pipe_config->fdi_lanes <= 2)
6501                         return 0;
6502
6503                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6504                 other_crtc_state =
6505                         intel_atomic_get_crtc_state(state, other_crtc);
6506                 if (IS_ERR(other_crtc_state))
6507                         return PTR_ERR(other_crtc_state);
6508
6509                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6510                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6511                                       pipe_name(pipe), pipe_config->fdi_lanes);
6512                         return -EINVAL;
6513                 }
6514                 return 0;
6515         case PIPE_C:
6516                 if (pipe_config->fdi_lanes > 2) {
6517                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6518                                       pipe_name(pipe), pipe_config->fdi_lanes);
6519                         return -EINVAL;
6520                 }
6521
6522                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6523                 other_crtc_state =
6524                         intel_atomic_get_crtc_state(state, other_crtc);
6525                 if (IS_ERR(other_crtc_state))
6526                         return PTR_ERR(other_crtc_state);
6527
6528                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6529                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6530                         return -EINVAL;
6531                 }
6532                 return 0;
6533         default:
6534                 BUG();
6535         }
6536 }
6537
6538 #define RETRY 1
6539 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6540                                        struct intel_crtc_state *pipe_config)
6541 {
6542         struct drm_device *dev = intel_crtc->base.dev;
6543         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6544         int lane, link_bw, fdi_dotclock, ret;
6545         bool needs_recompute = false;
6546
6547 retry:
6548         /* FDI is a binary signal running at ~2.7GHz, encoding
6549          * each output octet as 10 bits. The actual frequency
6550          * is stored as a divider into a 100MHz clock, and the
6551          * mode pixel clock is stored in units of 1KHz.
6552          * Hence the bw of each lane in terms of the mode signal
6553          * is:
6554          */
6555         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6556
6557         fdi_dotclock = adjusted_mode->crtc_clock;
6558
6559         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6560                                            pipe_config->pipe_bpp);
6561
6562         pipe_config->fdi_lanes = lane;
6563
6564         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6565                                link_bw, &pipe_config->fdi_m_n);
6566
6567         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6568                                        intel_crtc->pipe, pipe_config);
6569         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6570                 pipe_config->pipe_bpp -= 2*3;
6571                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6572                               pipe_config->pipe_bpp);
6573                 needs_recompute = true;
6574                 pipe_config->bw_constrained = true;
6575
6576                 goto retry;
6577         }
6578
6579         if (needs_recompute)
6580                 return RETRY;
6581
6582         return ret;
6583 }
6584
6585 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6586                                      struct intel_crtc_state *pipe_config)
6587 {
6588         if (pipe_config->pipe_bpp > 24)
6589                 return false;
6590
6591         /* HSW can handle pixel rate up to cdclk? */
6592         if (IS_HASWELL(dev_priv->dev))
6593                 return true;
6594
6595         /*
6596          * We compare against max which means we must take
6597          * the increased cdclk requirement into account when
6598          * calculating the new cdclk.
6599          *
6600          * Should measure whether using a lower cdclk w/o IPS
6601          */
6602         return ilk_pipe_pixel_rate(pipe_config) <=
6603                 dev_priv->max_cdclk_freq * 95 / 100;
6604 }
6605
6606 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6607                                    struct intel_crtc_state *pipe_config)
6608 {
6609         struct drm_device *dev = crtc->base.dev;
6610         struct drm_i915_private *dev_priv = dev->dev_private;
6611
6612         pipe_config->ips_enabled = i915.enable_ips &&
6613                 hsw_crtc_supports_ips(crtc) &&
6614                 pipe_config_supports_ips(dev_priv, pipe_config);
6615 }
6616
6617 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6618                                      struct intel_crtc_state *pipe_config)
6619 {
6620         struct drm_device *dev = crtc->base.dev;
6621         struct drm_i915_private *dev_priv = dev->dev_private;
6622         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6623
6624         /* FIXME should check pixel clock limits on all platforms */
6625         if (INTEL_INFO(dev)->gen < 4) {
6626                 int clock_limit = dev_priv->max_cdclk_freq;
6627
6628                 /*
6629                  * Enable pixel doubling when the dot clock
6630                  * is > 90% of the (display) core speed.
6631                  *
6632                  * GDG double wide on either pipe,
6633                  * otherwise pipe A only.
6634                  */
6635                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6636                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6637                         clock_limit *= 2;
6638                         pipe_config->double_wide = true;
6639                 }
6640
6641                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6642                         return -EINVAL;
6643         }
6644
6645         /*
6646          * Pipe horizontal size must be even in:
6647          * - DVO ganged mode
6648          * - LVDS dual channel mode
6649          * - Double wide pipe
6650          */
6651         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6652              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6653                 pipe_config->pipe_src_w &= ~1;
6654
6655         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6656          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6657          */
6658         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6659                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6660                 return -EINVAL;
6661
6662         if (HAS_IPS(dev))
6663                 hsw_compute_ips_config(crtc, pipe_config);
6664
6665         if (pipe_config->has_pch_encoder)
6666                 return ironlake_fdi_compute_config(crtc, pipe_config);
6667
6668         return 0;
6669 }
6670
6671 static int skylake_get_display_clock_speed(struct drm_device *dev)
6672 {
6673         struct drm_i915_private *dev_priv = to_i915(dev);
6674         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6675         uint32_t cdctl = I915_READ(CDCLK_CTL);
6676         uint32_t linkrate;
6677
6678         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6679                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6680
6681         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6682                 return 540000;
6683
6684         linkrate = (I915_READ(DPLL_CTRL1) &
6685                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6686
6687         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6688             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6689                 /* vco 8640 */
6690                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6691                 case CDCLK_FREQ_450_432:
6692                         return 432000;
6693                 case CDCLK_FREQ_337_308:
6694                         return 308570;
6695                 case CDCLK_FREQ_675_617:
6696                         return 617140;
6697                 default:
6698                         WARN(1, "Unknown cd freq selection\n");
6699                 }
6700         } else {
6701                 /* vco 8100 */
6702                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6703                 case CDCLK_FREQ_450_432:
6704                         return 450000;
6705                 case CDCLK_FREQ_337_308:
6706                         return 337500;
6707                 case CDCLK_FREQ_675_617:
6708                         return 675000;
6709                 default:
6710                         WARN(1, "Unknown cd freq selection\n");
6711                 }
6712         }
6713
6714         /* error case, do as if DPLL0 isn't enabled */
6715         return 24000;
6716 }
6717
6718 static int broxton_get_display_clock_speed(struct drm_device *dev)
6719 {
6720         struct drm_i915_private *dev_priv = to_i915(dev);
6721         uint32_t cdctl = I915_READ(CDCLK_CTL);
6722         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6723         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6724         int cdclk;
6725
6726         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6727                 return 19200;
6728
6729         cdclk = 19200 * pll_ratio / 2;
6730
6731         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6732         case BXT_CDCLK_CD2X_DIV_SEL_1:
6733                 return cdclk;  /* 576MHz or 624MHz */
6734         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6735                 return cdclk * 2 / 3; /* 384MHz */
6736         case BXT_CDCLK_CD2X_DIV_SEL_2:
6737                 return cdclk / 2; /* 288MHz */
6738         case BXT_CDCLK_CD2X_DIV_SEL_4:
6739                 return cdclk / 4; /* 144MHz */
6740         }
6741
6742         /* error case, do as if DE PLL isn't enabled */
6743         return 19200;
6744 }
6745
6746 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6747 {
6748         struct drm_i915_private *dev_priv = dev->dev_private;
6749         uint32_t lcpll = I915_READ(LCPLL_CTL);
6750         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6751
6752         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6753                 return 800000;
6754         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6755                 return 450000;
6756         else if (freq == LCPLL_CLK_FREQ_450)
6757                 return 450000;
6758         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6759                 return 540000;
6760         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6761                 return 337500;
6762         else
6763                 return 675000;
6764 }
6765
6766 static int haswell_get_display_clock_speed(struct drm_device *dev)
6767 {
6768         struct drm_i915_private *dev_priv = dev->dev_private;
6769         uint32_t lcpll = I915_READ(LCPLL_CTL);
6770         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6771
6772         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6773                 return 800000;
6774         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6775                 return 450000;
6776         else if (freq == LCPLL_CLK_FREQ_450)
6777                 return 450000;
6778         else if (IS_HSW_ULT(dev))
6779                 return 337500;
6780         else
6781                 return 540000;
6782 }
6783
6784 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6785 {
6786         struct drm_i915_private *dev_priv = dev->dev_private;
6787         u32 val;
6788         int divider;
6789
6790         if (dev_priv->hpll_freq == 0)
6791                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6792
6793         mutex_lock(&dev_priv->sb_lock);
6794         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6795         mutex_unlock(&dev_priv->sb_lock);
6796
6797         divider = val & DISPLAY_FREQUENCY_VALUES;
6798
6799         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6800              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6801              "cdclk change in progress\n");
6802
6803         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6804 }
6805
6806 static int ilk_get_display_clock_speed(struct drm_device *dev)
6807 {
6808         return 450000;
6809 }
6810
6811 static int i945_get_display_clock_speed(struct drm_device *dev)
6812 {
6813         return 400000;
6814 }
6815
6816 static int i915_get_display_clock_speed(struct drm_device *dev)
6817 {
6818         return 333333;
6819 }
6820
6821 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6822 {
6823         return 200000;
6824 }
6825
6826 static int pnv_get_display_clock_speed(struct drm_device *dev)
6827 {
6828         u16 gcfgc = 0;
6829
6830         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6831
6832         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6833         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6834                 return 266667;
6835         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6836                 return 333333;
6837         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6838                 return 444444;
6839         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6840                 return 200000;
6841         default:
6842                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6843         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6844                 return 133333;
6845         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6846                 return 166667;
6847         }
6848 }
6849
6850 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6851 {
6852         u16 gcfgc = 0;
6853
6854         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6855
6856         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6857                 return 133333;
6858         else {
6859                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6860                 case GC_DISPLAY_CLOCK_333_MHZ:
6861                         return 333333;
6862                 default:
6863                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6864                         return 190000;
6865                 }
6866         }
6867 }
6868
6869 static int i865_get_display_clock_speed(struct drm_device *dev)
6870 {
6871         return 266667;
6872 }
6873
6874 static int i85x_get_display_clock_speed(struct drm_device *dev)
6875 {
6876         u16 hpllcc = 0;
6877
6878         /*
6879          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6880          * encoding is different :(
6881          * FIXME is this the right way to detect 852GM/852GMV?
6882          */
6883         if (dev->pdev->revision == 0x1)
6884                 return 133333;
6885
6886         pci_bus_read_config_word(dev->pdev->bus,
6887                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6888
6889         /* Assume that the hardware is in the high speed state.  This
6890          * should be the default.
6891          */
6892         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6893         case GC_CLOCK_133_200:
6894         case GC_CLOCK_133_200_2:
6895         case GC_CLOCK_100_200:
6896                 return 200000;
6897         case GC_CLOCK_166_250:
6898                 return 250000;
6899         case GC_CLOCK_100_133:
6900                 return 133333;
6901         case GC_CLOCK_133_266:
6902         case GC_CLOCK_133_266_2:
6903         case GC_CLOCK_166_266:
6904                 return 266667;
6905         }
6906
6907         /* Shouldn't happen */
6908         return 0;
6909 }
6910
6911 static int i830_get_display_clock_speed(struct drm_device *dev)
6912 {
6913         return 133333;
6914 }
6915
6916 static unsigned int intel_hpll_vco(struct drm_device *dev)
6917 {
6918         struct drm_i915_private *dev_priv = dev->dev_private;
6919         static const unsigned int blb_vco[8] = {
6920                 [0] = 3200000,
6921                 [1] = 4000000,
6922                 [2] = 5333333,
6923                 [3] = 4800000,
6924                 [4] = 6400000,
6925         };
6926         static const unsigned int pnv_vco[8] = {
6927                 [0] = 3200000,
6928                 [1] = 4000000,
6929                 [2] = 5333333,
6930                 [3] = 4800000,
6931                 [4] = 2666667,
6932         };
6933         static const unsigned int cl_vco[8] = {
6934                 [0] = 3200000,
6935                 [1] = 4000000,
6936                 [2] = 5333333,
6937                 [3] = 6400000,
6938                 [4] = 3333333,
6939                 [5] = 3566667,
6940                 [6] = 4266667,
6941         };
6942         static const unsigned int elk_vco[8] = {
6943                 [0] = 3200000,
6944                 [1] = 4000000,
6945                 [2] = 5333333,
6946                 [3] = 4800000,
6947         };
6948         static const unsigned int ctg_vco[8] = {
6949                 [0] = 3200000,
6950                 [1] = 4000000,
6951                 [2] = 5333333,
6952                 [3] = 6400000,
6953                 [4] = 2666667,
6954                 [5] = 4266667,
6955         };
6956         const unsigned int *vco_table;
6957         unsigned int vco;
6958         uint8_t tmp = 0;
6959
6960         /* FIXME other chipsets? */
6961         if (IS_GM45(dev))
6962                 vco_table = ctg_vco;
6963         else if (IS_G4X(dev))
6964                 vco_table = elk_vco;
6965         else if (IS_CRESTLINE(dev))
6966                 vco_table = cl_vco;
6967         else if (IS_PINEVIEW(dev))
6968                 vco_table = pnv_vco;
6969         else if (IS_G33(dev))
6970                 vco_table = blb_vco;
6971         else
6972                 return 0;
6973
6974         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6975
6976         vco = vco_table[tmp & 0x7];
6977         if (vco == 0)
6978                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6979         else
6980                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6981
6982         return vco;
6983 }
6984
6985 static int gm45_get_display_clock_speed(struct drm_device *dev)
6986 {
6987         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6988         uint16_t tmp = 0;
6989
6990         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6991
6992         cdclk_sel = (tmp >> 12) & 0x1;
6993
6994         switch (vco) {
6995         case 2666667:
6996         case 4000000:
6997         case 5333333:
6998                 return cdclk_sel ? 333333 : 222222;
6999         case 3200000:
7000                 return cdclk_sel ? 320000 : 228571;
7001         default:
7002                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7003                 return 222222;
7004         }
7005 }
7006
7007 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7008 {
7009         static const uint8_t div_3200[] = { 16, 10,  8 };
7010         static const uint8_t div_4000[] = { 20, 12, 10 };
7011         static const uint8_t div_5333[] = { 24, 16, 14 };
7012         const uint8_t *div_table;
7013         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7014         uint16_t tmp = 0;
7015
7016         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7017
7018         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7019
7020         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7021                 goto fail;
7022
7023         switch (vco) {
7024         case 3200000:
7025                 div_table = div_3200;
7026                 break;
7027         case 4000000:
7028                 div_table = div_4000;
7029                 break;
7030         case 5333333:
7031                 div_table = div_5333;
7032                 break;
7033         default:
7034                 goto fail;
7035         }
7036
7037         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7038
7039 fail:
7040         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7041         return 200000;
7042 }
7043
7044 static int g33_get_display_clock_speed(struct drm_device *dev)
7045 {
7046         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7047         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7048         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7049         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7050         const uint8_t *div_table;
7051         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7052         uint16_t tmp = 0;
7053
7054         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7055
7056         cdclk_sel = (tmp >> 4) & 0x7;
7057
7058         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7059                 goto fail;
7060
7061         switch (vco) {
7062         case 3200000:
7063                 div_table = div_3200;
7064                 break;
7065         case 4000000:
7066                 div_table = div_4000;
7067                 break;
7068         case 4800000:
7069                 div_table = div_4800;
7070                 break;
7071         case 5333333:
7072                 div_table = div_5333;
7073                 break;
7074         default:
7075                 goto fail;
7076         }
7077
7078         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7079
7080 fail:
7081         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7082         return 190476;
7083 }
7084
7085 static void
7086 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7087 {
7088         while (*num > DATA_LINK_M_N_MASK ||
7089                *den > DATA_LINK_M_N_MASK) {
7090                 *num >>= 1;
7091                 *den >>= 1;
7092         }
7093 }
7094
7095 static void compute_m_n(unsigned int m, unsigned int n,
7096                         uint32_t *ret_m, uint32_t *ret_n)
7097 {
7098         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7099         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7100         intel_reduce_m_n_ratio(ret_m, ret_n);
7101 }
7102
7103 void
7104 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7105                        int pixel_clock, int link_clock,
7106                        struct intel_link_m_n *m_n)
7107 {
7108         m_n->tu = 64;
7109
7110         compute_m_n(bits_per_pixel * pixel_clock,
7111                     link_clock * nlanes * 8,
7112                     &m_n->gmch_m, &m_n->gmch_n);
7113
7114         compute_m_n(pixel_clock, link_clock,
7115                     &m_n->link_m, &m_n->link_n);
7116 }
7117
7118 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7119 {
7120         if (i915.panel_use_ssc >= 0)
7121                 return i915.panel_use_ssc != 0;
7122         return dev_priv->vbt.lvds_use_ssc
7123                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7124 }
7125
7126 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7127                            int num_connectors)
7128 {
7129         struct drm_device *dev = crtc_state->base.crtc->dev;
7130         struct drm_i915_private *dev_priv = dev->dev_private;
7131         int refclk;
7132
7133         WARN_ON(!crtc_state->base.state);
7134
7135         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7136                 refclk = 100000;
7137         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7138             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7139                 refclk = dev_priv->vbt.lvds_ssc_freq;
7140                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7141         } else if (!IS_GEN2(dev)) {
7142                 refclk = 96000;
7143         } else {
7144                 refclk = 48000;
7145         }
7146
7147         return refclk;
7148 }
7149
7150 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7151 {
7152         return (1 << dpll->n) << 16 | dpll->m2;
7153 }
7154
7155 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7156 {
7157         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7158 }
7159
7160 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7161                                      struct intel_crtc_state *crtc_state,
7162                                      intel_clock_t *reduced_clock)
7163 {
7164         struct drm_device *dev = crtc->base.dev;
7165         u32 fp, fp2 = 0;
7166
7167         if (IS_PINEVIEW(dev)) {
7168                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7169                 if (reduced_clock)
7170                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7171         } else {
7172                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7173                 if (reduced_clock)
7174                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7175         }
7176
7177         crtc_state->dpll_hw_state.fp0 = fp;
7178
7179         crtc->lowfreq_avail = false;
7180         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7181             reduced_clock) {
7182                 crtc_state->dpll_hw_state.fp1 = fp2;
7183                 crtc->lowfreq_avail = true;
7184         } else {
7185                 crtc_state->dpll_hw_state.fp1 = fp;
7186         }
7187 }
7188
7189 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7190                 pipe)
7191 {
7192         u32 reg_val;
7193
7194         /*
7195          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7196          * and set it to a reasonable value instead.
7197          */
7198         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7199         reg_val &= 0xffffff00;
7200         reg_val |= 0x00000030;
7201         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7202
7203         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7204         reg_val &= 0x8cffffff;
7205         reg_val = 0x8c000000;
7206         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7207
7208         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7209         reg_val &= 0xffffff00;
7210         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7211
7212         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7213         reg_val &= 0x00ffffff;
7214         reg_val |= 0xb0000000;
7215         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7216 }
7217
7218 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7219                                          struct intel_link_m_n *m_n)
7220 {
7221         struct drm_device *dev = crtc->base.dev;
7222         struct drm_i915_private *dev_priv = dev->dev_private;
7223         int pipe = crtc->pipe;
7224
7225         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7226         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7227         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7228         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7229 }
7230
7231 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7232                                          struct intel_link_m_n *m_n,
7233                                          struct intel_link_m_n *m2_n2)
7234 {
7235         struct drm_device *dev = crtc->base.dev;
7236         struct drm_i915_private *dev_priv = dev->dev_private;
7237         int pipe = crtc->pipe;
7238         enum transcoder transcoder = crtc->config->cpu_transcoder;
7239
7240         if (INTEL_INFO(dev)->gen >= 5) {
7241                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7242                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7243                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7244                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7245                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7246                  * for gen < 8) and if DRRS is supported (to make sure the
7247                  * registers are not unnecessarily accessed).
7248                  */
7249                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7250                         crtc->config->has_drrs) {
7251                         I915_WRITE(PIPE_DATA_M2(transcoder),
7252                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7253                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7254                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7255                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7256                 }
7257         } else {
7258                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7259                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7260                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7261                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7262         }
7263 }
7264
7265 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7266 {
7267         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7268
7269         if (m_n == M1_N1) {
7270                 dp_m_n = &crtc->config->dp_m_n;
7271                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7272         } else if (m_n == M2_N2) {
7273
7274                 /*
7275                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7276                  * needs to be programmed into M1_N1.
7277                  */
7278                 dp_m_n = &crtc->config->dp_m2_n2;
7279         } else {
7280                 DRM_ERROR("Unsupported divider value\n");
7281                 return;
7282         }
7283
7284         if (crtc->config->has_pch_encoder)
7285                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7286         else
7287                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7288 }
7289
7290 static void vlv_compute_dpll(struct intel_crtc *crtc,
7291                              struct intel_crtc_state *pipe_config)
7292 {
7293         u32 dpll, dpll_md;
7294
7295         /*
7296          * Enable DPIO clock input. We should never disable the reference
7297          * clock for pipe B, since VGA hotplug / manual detection depends
7298          * on it.
7299          */
7300         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7301                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7302         /* We should never disable this, set it here for state tracking */
7303         if (crtc->pipe == PIPE_B)
7304                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7305         dpll |= DPLL_VCO_ENABLE;
7306         pipe_config->dpll_hw_state.dpll = dpll;
7307
7308         dpll_md = (pipe_config->pixel_multiplier - 1)
7309                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7310         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7311 }
7312
7313 static void vlv_prepare_pll(struct intel_crtc *crtc,
7314                             const struct intel_crtc_state *pipe_config)
7315 {
7316         struct drm_device *dev = crtc->base.dev;
7317         struct drm_i915_private *dev_priv = dev->dev_private;
7318         int pipe = crtc->pipe;
7319         u32 mdiv;
7320         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7321         u32 coreclk, reg_val;
7322
7323         mutex_lock(&dev_priv->sb_lock);
7324
7325         bestn = pipe_config->dpll.n;
7326         bestm1 = pipe_config->dpll.m1;
7327         bestm2 = pipe_config->dpll.m2;
7328         bestp1 = pipe_config->dpll.p1;
7329         bestp2 = pipe_config->dpll.p2;
7330
7331         /* See eDP HDMI DPIO driver vbios notes doc */
7332
7333         /* PLL B needs special handling */
7334         if (pipe == PIPE_B)
7335                 vlv_pllb_recal_opamp(dev_priv, pipe);
7336
7337         /* Set up Tx target for periodic Rcomp update */
7338         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7339
7340         /* Disable target IRef on PLL */
7341         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7342         reg_val &= 0x00ffffff;
7343         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7344
7345         /* Disable fast lock */
7346         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7347
7348         /* Set idtafcrecal before PLL is enabled */
7349         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7350         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7351         mdiv |= ((bestn << DPIO_N_SHIFT));
7352         mdiv |= (1 << DPIO_K_SHIFT);
7353
7354         /*
7355          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7356          * but we don't support that).
7357          * Note: don't use the DAC post divider as it seems unstable.
7358          */
7359         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7360         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7361
7362         mdiv |= DPIO_ENABLE_CALIBRATION;
7363         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7364
7365         /* Set HBR and RBR LPF coefficients */
7366         if (pipe_config->port_clock == 162000 ||
7367             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7368             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7369                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7370                                  0x009f0003);
7371         else
7372                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7373                                  0x00d0000f);
7374
7375         if (pipe_config->has_dp_encoder) {
7376                 /* Use SSC source */
7377                 if (pipe == PIPE_A)
7378                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7379                                          0x0df40000);
7380                 else
7381                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7382                                          0x0df70000);
7383         } else { /* HDMI or VGA */
7384                 /* Use bend source */
7385                 if (pipe == PIPE_A)
7386                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7387                                          0x0df70000);
7388                 else
7389                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7390                                          0x0df40000);
7391         }
7392
7393         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7394         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7396             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7397                 coreclk |= 0x01000000;
7398         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7399
7400         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7401         mutex_unlock(&dev_priv->sb_lock);
7402 }
7403
7404 static void chv_compute_dpll(struct intel_crtc *crtc,
7405                              struct intel_crtc_state *pipe_config)
7406 {
7407         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7408                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7409                 DPLL_VCO_ENABLE;
7410         if (crtc->pipe != PIPE_A)
7411                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7412
7413         pipe_config->dpll_hw_state.dpll_md =
7414                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7415 }
7416
7417 static void chv_prepare_pll(struct intel_crtc *crtc,
7418                             const struct intel_crtc_state *pipe_config)
7419 {
7420         struct drm_device *dev = crtc->base.dev;
7421         struct drm_i915_private *dev_priv = dev->dev_private;
7422         int pipe = crtc->pipe;
7423         int dpll_reg = DPLL(crtc->pipe);
7424         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7425         u32 loopfilter, tribuf_calcntr;
7426         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7427         u32 dpio_val;
7428         int vco;
7429
7430         bestn = pipe_config->dpll.n;
7431         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7432         bestm1 = pipe_config->dpll.m1;
7433         bestm2 = pipe_config->dpll.m2 >> 22;
7434         bestp1 = pipe_config->dpll.p1;
7435         bestp2 = pipe_config->dpll.p2;
7436         vco = pipe_config->dpll.vco;
7437         dpio_val = 0;
7438         loopfilter = 0;
7439
7440         /*
7441          * Enable Refclk and SSC
7442          */
7443         I915_WRITE(dpll_reg,
7444                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7445
7446         mutex_lock(&dev_priv->sb_lock);
7447
7448         /* p1 and p2 divider */
7449         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7450                         5 << DPIO_CHV_S1_DIV_SHIFT |
7451                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7452                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7453                         1 << DPIO_CHV_K_DIV_SHIFT);
7454
7455         /* Feedback post-divider - m2 */
7456         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7457
7458         /* Feedback refclk divider - n and m1 */
7459         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7460                         DPIO_CHV_M1_DIV_BY_2 |
7461                         1 << DPIO_CHV_N_DIV_SHIFT);
7462
7463         /* M2 fraction division */
7464         if (bestm2_frac)
7465                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7466
7467         /* M2 fraction division enable */
7468         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7469         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7470         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7471         if (bestm2_frac)
7472                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7473         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7474
7475         /* Program digital lock detect threshold */
7476         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7477         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7478                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7479         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7480         if (!bestm2_frac)
7481                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7482         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7483
7484         /* Loop filter */
7485         if (vco == 5400000) {
7486                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7487                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7488                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7489                 tribuf_calcntr = 0x9;
7490         } else if (vco <= 6200000) {
7491                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7492                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7493                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7494                 tribuf_calcntr = 0x9;
7495         } else if (vco <= 6480000) {
7496                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7497                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7498                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7499                 tribuf_calcntr = 0x8;
7500         } else {
7501                 /* Not supported. Apply the same limits as in the max case */
7502                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7503                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7504                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7505                 tribuf_calcntr = 0;
7506         }
7507         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7508
7509         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7510         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7511         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7512         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7513
7514         /* AFC Recal */
7515         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7516                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7517                         DPIO_AFC_RECAL);
7518
7519         mutex_unlock(&dev_priv->sb_lock);
7520 }
7521
7522 /**
7523  * vlv_force_pll_on - forcibly enable just the PLL
7524  * @dev_priv: i915 private structure
7525  * @pipe: pipe PLL to enable
7526  * @dpll: PLL configuration
7527  *
7528  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7529  * in cases where we need the PLL enabled even when @pipe is not going to
7530  * be enabled.
7531  */
7532 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7533                       const struct dpll *dpll)
7534 {
7535         struct intel_crtc *crtc =
7536                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7537         struct intel_crtc_state pipe_config = {
7538                 .base.crtc = &crtc->base,
7539                 .pixel_multiplier = 1,
7540                 .dpll = *dpll,
7541         };
7542
7543         if (IS_CHERRYVIEW(dev)) {
7544                 chv_compute_dpll(crtc, &pipe_config);
7545                 chv_prepare_pll(crtc, &pipe_config);
7546                 chv_enable_pll(crtc, &pipe_config);
7547         } else {
7548                 vlv_compute_dpll(crtc, &pipe_config);
7549                 vlv_prepare_pll(crtc, &pipe_config);
7550                 vlv_enable_pll(crtc, &pipe_config);
7551         }
7552 }
7553
7554 /**
7555  * vlv_force_pll_off - forcibly disable just the PLL
7556  * @dev_priv: i915 private structure
7557  * @pipe: pipe PLL to disable
7558  *
7559  * Disable the PLL for @pipe. To be used in cases where we need
7560  * the PLL enabled even when @pipe is not going to be enabled.
7561  */
7562 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7563 {
7564         if (IS_CHERRYVIEW(dev))
7565                 chv_disable_pll(to_i915(dev), pipe);
7566         else
7567                 vlv_disable_pll(to_i915(dev), pipe);
7568 }
7569
7570 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7571                               struct intel_crtc_state *crtc_state,
7572                               intel_clock_t *reduced_clock,
7573                               int num_connectors)
7574 {
7575         struct drm_device *dev = crtc->base.dev;
7576         struct drm_i915_private *dev_priv = dev->dev_private;
7577         u32 dpll;
7578         bool is_sdvo;
7579         struct dpll *clock = &crtc_state->dpll;
7580
7581         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7582
7583         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7584                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7585
7586         dpll = DPLL_VGA_MODE_DIS;
7587
7588         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7589                 dpll |= DPLLB_MODE_LVDS;
7590         else
7591                 dpll |= DPLLB_MODE_DAC_SERIAL;
7592
7593         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7594                 dpll |= (crtc_state->pixel_multiplier - 1)
7595                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7596         }
7597
7598         if (is_sdvo)
7599                 dpll |= DPLL_SDVO_HIGH_SPEED;
7600
7601         if (crtc_state->has_dp_encoder)
7602                 dpll |= DPLL_SDVO_HIGH_SPEED;
7603
7604         /* compute bitmask from p1 value */
7605         if (IS_PINEVIEW(dev))
7606                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7607         else {
7608                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7609                 if (IS_G4X(dev) && reduced_clock)
7610                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7611         }
7612         switch (clock->p2) {
7613         case 5:
7614                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7615                 break;
7616         case 7:
7617                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7618                 break;
7619         case 10:
7620                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7621                 break;
7622         case 14:
7623                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7624                 break;
7625         }
7626         if (INTEL_INFO(dev)->gen >= 4)
7627                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7628
7629         if (crtc_state->sdvo_tv_clock)
7630                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7631         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7632                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7633                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7634         else
7635                 dpll |= PLL_REF_INPUT_DREFCLK;
7636
7637         dpll |= DPLL_VCO_ENABLE;
7638         crtc_state->dpll_hw_state.dpll = dpll;
7639
7640         if (INTEL_INFO(dev)->gen >= 4) {
7641                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7642                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7643                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7644         }
7645 }
7646
7647 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7648                               struct intel_crtc_state *crtc_state,
7649                               intel_clock_t *reduced_clock,
7650                               int num_connectors)
7651 {
7652         struct drm_device *dev = crtc->base.dev;
7653         struct drm_i915_private *dev_priv = dev->dev_private;
7654         u32 dpll;
7655         struct dpll *clock = &crtc_state->dpll;
7656
7657         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7658
7659         dpll = DPLL_VGA_MODE_DIS;
7660
7661         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7662                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7663         } else {
7664                 if (clock->p1 == 2)
7665                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7666                 else
7667                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7668                 if (clock->p2 == 4)
7669                         dpll |= PLL_P2_DIVIDE_BY_4;
7670         }
7671
7672         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7673                 dpll |= DPLL_DVO_2X_MODE;
7674
7675         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7676                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7677                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7678         else
7679                 dpll |= PLL_REF_INPUT_DREFCLK;
7680
7681         dpll |= DPLL_VCO_ENABLE;
7682         crtc_state->dpll_hw_state.dpll = dpll;
7683 }
7684
7685 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7686 {
7687         struct drm_device *dev = intel_crtc->base.dev;
7688         struct drm_i915_private *dev_priv = dev->dev_private;
7689         enum pipe pipe = intel_crtc->pipe;
7690         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7691         struct drm_display_mode *adjusted_mode =
7692                 &intel_crtc->config->base.adjusted_mode;
7693         uint32_t crtc_vtotal, crtc_vblank_end;
7694         int vsyncshift = 0;
7695
7696         /* We need to be careful not to changed the adjusted mode, for otherwise
7697          * the hw state checker will get angry at the mismatch. */
7698         crtc_vtotal = adjusted_mode->crtc_vtotal;
7699         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7700
7701         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7702                 /* the chip adds 2 halflines automatically */
7703                 crtc_vtotal -= 1;
7704                 crtc_vblank_end -= 1;
7705
7706                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7707                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7708                 else
7709                         vsyncshift = adjusted_mode->crtc_hsync_start -
7710                                 adjusted_mode->crtc_htotal / 2;
7711                 if (vsyncshift < 0)
7712                         vsyncshift += adjusted_mode->crtc_htotal;
7713         }
7714
7715         if (INTEL_INFO(dev)->gen > 3)
7716                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7717
7718         I915_WRITE(HTOTAL(cpu_transcoder),
7719                    (adjusted_mode->crtc_hdisplay - 1) |
7720                    ((adjusted_mode->crtc_htotal - 1) << 16));
7721         I915_WRITE(HBLANK(cpu_transcoder),
7722                    (adjusted_mode->crtc_hblank_start - 1) |
7723                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7724         I915_WRITE(HSYNC(cpu_transcoder),
7725                    (adjusted_mode->crtc_hsync_start - 1) |
7726                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7727
7728         I915_WRITE(VTOTAL(cpu_transcoder),
7729                    (adjusted_mode->crtc_vdisplay - 1) |
7730                    ((crtc_vtotal - 1) << 16));
7731         I915_WRITE(VBLANK(cpu_transcoder),
7732                    (adjusted_mode->crtc_vblank_start - 1) |
7733                    ((crtc_vblank_end - 1) << 16));
7734         I915_WRITE(VSYNC(cpu_transcoder),
7735                    (adjusted_mode->crtc_vsync_start - 1) |
7736                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7737
7738         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7739          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7740          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7741          * bits. */
7742         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7743             (pipe == PIPE_B || pipe == PIPE_C))
7744                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7745
7746         /* pipesrc controls the size that is scaled from, which should
7747          * always be the user's requested size.
7748          */
7749         I915_WRITE(PIPESRC(pipe),
7750                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7751                    (intel_crtc->config->pipe_src_h - 1));
7752 }
7753
7754 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7755                                    struct intel_crtc_state *pipe_config)
7756 {
7757         struct drm_device *dev = crtc->base.dev;
7758         struct drm_i915_private *dev_priv = dev->dev_private;
7759         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7760         uint32_t tmp;
7761
7762         tmp = I915_READ(HTOTAL(cpu_transcoder));
7763         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7764         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7765         tmp = I915_READ(HBLANK(cpu_transcoder));
7766         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7767         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7768         tmp = I915_READ(HSYNC(cpu_transcoder));
7769         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7770         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7771
7772         tmp = I915_READ(VTOTAL(cpu_transcoder));
7773         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7774         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7775         tmp = I915_READ(VBLANK(cpu_transcoder));
7776         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7777         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7778         tmp = I915_READ(VSYNC(cpu_transcoder));
7779         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7780         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7781
7782         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7783                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7784                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7785                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7786         }
7787
7788         tmp = I915_READ(PIPESRC(crtc->pipe));
7789         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7790         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7791
7792         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7793         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7794 }
7795
7796 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7797                                  struct intel_crtc_state *pipe_config)
7798 {
7799         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7800         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7801         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7802         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7803
7804         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7805         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7806         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7807         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7808
7809         mode->flags = pipe_config->base.adjusted_mode.flags;
7810         mode->type = DRM_MODE_TYPE_DRIVER;
7811
7812         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7813         mode->flags |= pipe_config->base.adjusted_mode.flags;
7814
7815         mode->hsync = drm_mode_hsync(mode);
7816         mode->vrefresh = drm_mode_vrefresh(mode);
7817         drm_mode_set_name(mode);
7818 }
7819
7820 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7821 {
7822         struct drm_device *dev = intel_crtc->base.dev;
7823         struct drm_i915_private *dev_priv = dev->dev_private;
7824         uint32_t pipeconf;
7825
7826         pipeconf = 0;
7827
7828         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7829             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7830                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7831
7832         if (intel_crtc->config->double_wide)
7833                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7834
7835         /* only g4x and later have fancy bpc/dither controls */
7836         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7837                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7838                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7839                         pipeconf |= PIPECONF_DITHER_EN |
7840                                     PIPECONF_DITHER_TYPE_SP;
7841
7842                 switch (intel_crtc->config->pipe_bpp) {
7843                 case 18:
7844                         pipeconf |= PIPECONF_6BPC;
7845                         break;
7846                 case 24:
7847                         pipeconf |= PIPECONF_8BPC;
7848                         break;
7849                 case 30:
7850                         pipeconf |= PIPECONF_10BPC;
7851                         break;
7852                 default:
7853                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7854                         BUG();
7855                 }
7856         }
7857
7858         if (HAS_PIPE_CXSR(dev)) {
7859                 if (intel_crtc->lowfreq_avail) {
7860                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7861                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7862                 } else {
7863                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7864                 }
7865         }
7866
7867         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7868                 if (INTEL_INFO(dev)->gen < 4 ||
7869                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7870                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7871                 else
7872                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7873         } else
7874                 pipeconf |= PIPECONF_PROGRESSIVE;
7875
7876         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7877                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7878
7879         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7880         POSTING_READ(PIPECONF(intel_crtc->pipe));
7881 }
7882
7883 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7884                                    struct intel_crtc_state *crtc_state)
7885 {
7886         struct drm_device *dev = crtc->base.dev;
7887         struct drm_i915_private *dev_priv = dev->dev_private;
7888         int refclk, num_connectors = 0;
7889         intel_clock_t clock;
7890         bool ok;
7891         bool is_dsi = false;
7892         struct intel_encoder *encoder;
7893         const intel_limit_t *limit;
7894         struct drm_atomic_state *state = crtc_state->base.state;
7895         struct drm_connector *connector;
7896         struct drm_connector_state *connector_state;
7897         int i;
7898
7899         memset(&crtc_state->dpll_hw_state, 0,
7900                sizeof(crtc_state->dpll_hw_state));
7901
7902         for_each_connector_in_state(state, connector, connector_state, i) {
7903                 if (connector_state->crtc != &crtc->base)
7904                         continue;
7905
7906                 encoder = to_intel_encoder(connector_state->best_encoder);
7907
7908                 switch (encoder->type) {
7909                 case INTEL_OUTPUT_DSI:
7910                         is_dsi = true;
7911                         break;
7912                 default:
7913                         break;
7914                 }
7915
7916                 num_connectors++;
7917         }
7918
7919         if (is_dsi)
7920                 return 0;
7921
7922         if (!crtc_state->clock_set) {
7923                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7924
7925                 /*
7926                  * Returns a set of divisors for the desired target clock with
7927                  * the given refclk, or FALSE.  The returned values represent
7928                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7929                  * 2) / p1 / p2.
7930                  */
7931                 limit = intel_limit(crtc_state, refclk);
7932                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7933                                                  crtc_state->port_clock,
7934                                                  refclk, NULL, &clock);
7935                 if (!ok) {
7936                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7937                         return -EINVAL;
7938                 }
7939
7940                 /* Compat-code for transition, will disappear. */
7941                 crtc_state->dpll.n = clock.n;
7942                 crtc_state->dpll.m1 = clock.m1;
7943                 crtc_state->dpll.m2 = clock.m2;
7944                 crtc_state->dpll.p1 = clock.p1;
7945                 crtc_state->dpll.p2 = clock.p2;
7946         }
7947
7948         if (IS_GEN2(dev)) {
7949                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7950                                   num_connectors);
7951         } else if (IS_CHERRYVIEW(dev)) {
7952                 chv_compute_dpll(crtc, crtc_state);
7953         } else if (IS_VALLEYVIEW(dev)) {
7954                 vlv_compute_dpll(crtc, crtc_state);
7955         } else {
7956                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7957                                   num_connectors);
7958         }
7959
7960         return 0;
7961 }
7962
7963 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7964                                  struct intel_crtc_state *pipe_config)
7965 {
7966         struct drm_device *dev = crtc->base.dev;
7967         struct drm_i915_private *dev_priv = dev->dev_private;
7968         uint32_t tmp;
7969
7970         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7971                 return;
7972
7973         tmp = I915_READ(PFIT_CONTROL);
7974         if (!(tmp & PFIT_ENABLE))
7975                 return;
7976
7977         /* Check whether the pfit is attached to our pipe. */
7978         if (INTEL_INFO(dev)->gen < 4) {
7979                 if (crtc->pipe != PIPE_B)
7980                         return;
7981         } else {
7982                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7983                         return;
7984         }
7985
7986         pipe_config->gmch_pfit.control = tmp;
7987         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7988         if (INTEL_INFO(dev)->gen < 5)
7989                 pipe_config->gmch_pfit.lvds_border_bits =
7990                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7991 }
7992
7993 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7994                                struct intel_crtc_state *pipe_config)
7995 {
7996         struct drm_device *dev = crtc->base.dev;
7997         struct drm_i915_private *dev_priv = dev->dev_private;
7998         int pipe = pipe_config->cpu_transcoder;
7999         intel_clock_t clock;
8000         u32 mdiv;
8001         int refclk = 100000;
8002
8003         /* In case of MIPI DPLL will not even be used */
8004         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8005                 return;
8006
8007         mutex_lock(&dev_priv->sb_lock);
8008         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8009         mutex_unlock(&dev_priv->sb_lock);
8010
8011         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8012         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8013         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8014         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8015         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8016
8017         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8018 }
8019
8020 static void
8021 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8022                               struct intel_initial_plane_config *plane_config)
8023 {
8024         struct drm_device *dev = crtc->base.dev;
8025         struct drm_i915_private *dev_priv = dev->dev_private;
8026         u32 val, base, offset;
8027         int pipe = crtc->pipe, plane = crtc->plane;
8028         int fourcc, pixel_format;
8029         unsigned int aligned_height;
8030         struct drm_framebuffer *fb;
8031         struct intel_framebuffer *intel_fb;
8032
8033         val = I915_READ(DSPCNTR(plane));
8034         if (!(val & DISPLAY_PLANE_ENABLE))
8035                 return;
8036
8037         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8038         if (!intel_fb) {
8039                 DRM_DEBUG_KMS("failed to alloc fb\n");
8040                 return;
8041         }
8042
8043         fb = &intel_fb->base;
8044
8045         if (INTEL_INFO(dev)->gen >= 4) {
8046                 if (val & DISPPLANE_TILED) {
8047                         plane_config->tiling = I915_TILING_X;
8048                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8049                 }
8050         }
8051
8052         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8053         fourcc = i9xx_format_to_fourcc(pixel_format);
8054         fb->pixel_format = fourcc;
8055         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8056
8057         if (INTEL_INFO(dev)->gen >= 4) {
8058                 if (plane_config->tiling)
8059                         offset = I915_READ(DSPTILEOFF(plane));
8060                 else
8061                         offset = I915_READ(DSPLINOFF(plane));
8062                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8063         } else {
8064                 base = I915_READ(DSPADDR(plane));
8065         }
8066         plane_config->base = base;
8067
8068         val = I915_READ(PIPESRC(pipe));
8069         fb->width = ((val >> 16) & 0xfff) + 1;
8070         fb->height = ((val >> 0) & 0xfff) + 1;
8071
8072         val = I915_READ(DSPSTRIDE(pipe));
8073         fb->pitches[0] = val & 0xffffffc0;
8074
8075         aligned_height = intel_fb_align_height(dev, fb->height,
8076                                                fb->pixel_format,
8077                                                fb->modifier[0]);
8078
8079         plane_config->size = fb->pitches[0] * aligned_height;
8080
8081         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8082                       pipe_name(pipe), plane, fb->width, fb->height,
8083                       fb->bits_per_pixel, base, fb->pitches[0],
8084                       plane_config->size);
8085
8086         plane_config->fb = intel_fb;
8087 }
8088
8089 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8090                                struct intel_crtc_state *pipe_config)
8091 {
8092         struct drm_device *dev = crtc->base.dev;
8093         struct drm_i915_private *dev_priv = dev->dev_private;
8094         int pipe = pipe_config->cpu_transcoder;
8095         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8096         intel_clock_t clock;
8097         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8098         int refclk = 100000;
8099
8100         mutex_lock(&dev_priv->sb_lock);
8101         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8102         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8103         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8104         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8105         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8106         mutex_unlock(&dev_priv->sb_lock);
8107
8108         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8109         clock.m2 = (pll_dw0 & 0xff) << 22;
8110         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8111                 clock.m2 |= pll_dw2 & 0x3fffff;
8112         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8113         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8114         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8115
8116         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8117 }
8118
8119 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8120                                  struct intel_crtc_state *pipe_config)
8121 {
8122         struct drm_device *dev = crtc->base.dev;
8123         struct drm_i915_private *dev_priv = dev->dev_private;
8124         uint32_t tmp;
8125
8126         if (!intel_display_power_is_enabled(dev_priv,
8127                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8128                 return false;
8129
8130         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8131         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8132
8133         tmp = I915_READ(PIPECONF(crtc->pipe));
8134         if (!(tmp & PIPECONF_ENABLE))
8135                 return false;
8136
8137         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8138                 switch (tmp & PIPECONF_BPC_MASK) {
8139                 case PIPECONF_6BPC:
8140                         pipe_config->pipe_bpp = 18;
8141                         break;
8142                 case PIPECONF_8BPC:
8143                         pipe_config->pipe_bpp = 24;
8144                         break;
8145                 case PIPECONF_10BPC:
8146                         pipe_config->pipe_bpp = 30;
8147                         break;
8148                 default:
8149                         break;
8150                 }
8151         }
8152
8153         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8154                 pipe_config->limited_color_range = true;
8155
8156         if (INTEL_INFO(dev)->gen < 4)
8157                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8158
8159         intel_get_pipe_timings(crtc, pipe_config);
8160
8161         i9xx_get_pfit_config(crtc, pipe_config);
8162
8163         if (INTEL_INFO(dev)->gen >= 4) {
8164                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8165                 pipe_config->pixel_multiplier =
8166                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8167                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8168                 pipe_config->dpll_hw_state.dpll_md = tmp;
8169         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8170                 tmp = I915_READ(DPLL(crtc->pipe));
8171                 pipe_config->pixel_multiplier =
8172                         ((tmp & SDVO_MULTIPLIER_MASK)
8173                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8174         } else {
8175                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8176                  * port and will be fixed up in the encoder->get_config
8177                  * function. */
8178                 pipe_config->pixel_multiplier = 1;
8179         }
8180         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8181         if (!IS_VALLEYVIEW(dev)) {
8182                 /*
8183                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8184                  * on 830. Filter it out here so that we don't
8185                  * report errors due to that.
8186                  */
8187                 if (IS_I830(dev))
8188                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8189
8190                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8191                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8192         } else {
8193                 /* Mask out read-only status bits. */
8194                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8195                                                      DPLL_PORTC_READY_MASK |
8196                                                      DPLL_PORTB_READY_MASK);
8197         }
8198
8199         if (IS_CHERRYVIEW(dev))
8200                 chv_crtc_clock_get(crtc, pipe_config);
8201         else if (IS_VALLEYVIEW(dev))
8202                 vlv_crtc_clock_get(crtc, pipe_config);
8203         else
8204                 i9xx_crtc_clock_get(crtc, pipe_config);
8205
8206         return true;
8207 }
8208
8209 static void ironlake_init_pch_refclk(struct drm_device *dev)
8210 {
8211         struct drm_i915_private *dev_priv = dev->dev_private;
8212         struct intel_encoder *encoder;
8213         u32 val, final;
8214         bool has_lvds = false;
8215         bool has_cpu_edp = false;
8216         bool has_panel = false;
8217         bool has_ck505 = false;
8218         bool can_ssc = false;
8219
8220         /* We need to take the global config into account */
8221         for_each_intel_encoder(dev, encoder) {
8222                 switch (encoder->type) {
8223                 case INTEL_OUTPUT_LVDS:
8224                         has_panel = true;
8225                         has_lvds = true;
8226                         break;
8227                 case INTEL_OUTPUT_EDP:
8228                         has_panel = true;
8229                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8230                                 has_cpu_edp = true;
8231                         break;
8232                 default:
8233                         break;
8234                 }
8235         }
8236
8237         if (HAS_PCH_IBX(dev)) {
8238                 has_ck505 = dev_priv->vbt.display_clock_mode;
8239                 can_ssc = has_ck505;
8240         } else {
8241                 has_ck505 = false;
8242                 can_ssc = true;
8243         }
8244
8245         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8246                       has_panel, has_lvds, has_ck505);
8247
8248         /* Ironlake: try to setup display ref clock before DPLL
8249          * enabling. This is only under driver's control after
8250          * PCH B stepping, previous chipset stepping should be
8251          * ignoring this setting.
8252          */
8253         val = I915_READ(PCH_DREF_CONTROL);
8254
8255         /* As we must carefully and slowly disable/enable each source in turn,
8256          * compute the final state we want first and check if we need to
8257          * make any changes at all.
8258          */
8259         final = val;
8260         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8261         if (has_ck505)
8262                 final |= DREF_NONSPREAD_CK505_ENABLE;
8263         else
8264                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8265
8266         final &= ~DREF_SSC_SOURCE_MASK;
8267         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8268         final &= ~DREF_SSC1_ENABLE;
8269
8270         if (has_panel) {
8271                 final |= DREF_SSC_SOURCE_ENABLE;
8272
8273                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8274                         final |= DREF_SSC1_ENABLE;
8275
8276                 if (has_cpu_edp) {
8277                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8278                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8279                         else
8280                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8281                 } else
8282                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8283         } else {
8284                 final |= DREF_SSC_SOURCE_DISABLE;
8285                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8286         }
8287
8288         if (final == val)
8289                 return;
8290
8291         /* Always enable nonspread source */
8292         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8293
8294         if (has_ck505)
8295                 val |= DREF_NONSPREAD_CK505_ENABLE;
8296         else
8297                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8298
8299         if (has_panel) {
8300                 val &= ~DREF_SSC_SOURCE_MASK;
8301                 val |= DREF_SSC_SOURCE_ENABLE;
8302
8303                 /* SSC must be turned on before enabling the CPU output  */
8304                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8305                         DRM_DEBUG_KMS("Using SSC on panel\n");
8306                         val |= DREF_SSC1_ENABLE;
8307                 } else
8308                         val &= ~DREF_SSC1_ENABLE;
8309
8310                 /* Get SSC going before enabling the outputs */
8311                 I915_WRITE(PCH_DREF_CONTROL, val);
8312                 POSTING_READ(PCH_DREF_CONTROL);
8313                 udelay(200);
8314
8315                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8316
8317                 /* Enable CPU source on CPU attached eDP */
8318                 if (has_cpu_edp) {
8319                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8320                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8321                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8322                         } else
8323                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8324                 } else
8325                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8326
8327                 I915_WRITE(PCH_DREF_CONTROL, val);
8328                 POSTING_READ(PCH_DREF_CONTROL);
8329                 udelay(200);
8330         } else {
8331                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8332
8333                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8334
8335                 /* Turn off CPU output */
8336                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8337
8338                 I915_WRITE(PCH_DREF_CONTROL, val);
8339                 POSTING_READ(PCH_DREF_CONTROL);
8340                 udelay(200);
8341
8342                 /* Turn off the SSC source */
8343                 val &= ~DREF_SSC_SOURCE_MASK;
8344                 val |= DREF_SSC_SOURCE_DISABLE;
8345
8346                 /* Turn off SSC1 */
8347                 val &= ~DREF_SSC1_ENABLE;
8348
8349                 I915_WRITE(PCH_DREF_CONTROL, val);
8350                 POSTING_READ(PCH_DREF_CONTROL);
8351                 udelay(200);
8352         }
8353
8354         BUG_ON(val != final);
8355 }
8356
8357 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8358 {
8359         uint32_t tmp;
8360
8361         tmp = I915_READ(SOUTH_CHICKEN2);
8362         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8363         I915_WRITE(SOUTH_CHICKEN2, tmp);
8364
8365         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8366                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8367                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8368
8369         tmp = I915_READ(SOUTH_CHICKEN2);
8370         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8371         I915_WRITE(SOUTH_CHICKEN2, tmp);
8372
8373         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8374                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8375                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8376 }
8377
8378 /* WaMPhyProgramming:hsw */
8379 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8380 {
8381         uint32_t tmp;
8382
8383         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8384         tmp &= ~(0xFF << 24);
8385         tmp |= (0x12 << 24);
8386         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8387
8388         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8389         tmp |= (1 << 11);
8390         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8391
8392         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8393         tmp |= (1 << 11);
8394         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8395
8396         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8397         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8398         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8399
8400         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8401         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8402         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8403
8404         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8405         tmp &= ~(7 << 13);
8406         tmp |= (5 << 13);
8407         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8408
8409         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8410         tmp &= ~(7 << 13);
8411         tmp |= (5 << 13);
8412         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8413
8414         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8415         tmp &= ~0xFF;
8416         tmp |= 0x1C;
8417         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8418
8419         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8420         tmp &= ~0xFF;
8421         tmp |= 0x1C;
8422         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8423
8424         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8425         tmp &= ~(0xFF << 16);
8426         tmp |= (0x1C << 16);
8427         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8428
8429         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8430         tmp &= ~(0xFF << 16);
8431         tmp |= (0x1C << 16);
8432         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8433
8434         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8435         tmp |= (1 << 27);
8436         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8439         tmp |= (1 << 27);
8440         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8441
8442         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8443         tmp &= ~(0xF << 28);
8444         tmp |= (4 << 28);
8445         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8446
8447         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8448         tmp &= ~(0xF << 28);
8449         tmp |= (4 << 28);
8450         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8451 }
8452
8453 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8454  * Programming" based on the parameters passed:
8455  * - Sequence to enable CLKOUT_DP
8456  * - Sequence to enable CLKOUT_DP without spread
8457  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8458  */
8459 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8460                                  bool with_fdi)
8461 {
8462         struct drm_i915_private *dev_priv = dev->dev_private;
8463         uint32_t reg, tmp;
8464
8465         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8466                 with_spread = true;
8467         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8468                  with_fdi, "LP PCH doesn't have FDI\n"))
8469                 with_fdi = false;
8470
8471         mutex_lock(&dev_priv->sb_lock);
8472
8473         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8474         tmp &= ~SBI_SSCCTL_DISABLE;
8475         tmp |= SBI_SSCCTL_PATHALT;
8476         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8477
8478         udelay(24);
8479
8480         if (with_spread) {
8481                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8482                 tmp &= ~SBI_SSCCTL_PATHALT;
8483                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8484
8485                 if (with_fdi) {
8486                         lpt_reset_fdi_mphy(dev_priv);
8487                         lpt_program_fdi_mphy(dev_priv);
8488                 }
8489         }
8490
8491         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8492                SBI_GEN0 : SBI_DBUFF0;
8493         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8494         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8495         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8496
8497         mutex_unlock(&dev_priv->sb_lock);
8498 }
8499
8500 /* Sequence to disable CLKOUT_DP */
8501 static void lpt_disable_clkout_dp(struct drm_device *dev)
8502 {
8503         struct drm_i915_private *dev_priv = dev->dev_private;
8504         uint32_t reg, tmp;
8505
8506         mutex_lock(&dev_priv->sb_lock);
8507
8508         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8509                SBI_GEN0 : SBI_DBUFF0;
8510         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8511         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8512         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8513
8514         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8515         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8516                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8517                         tmp |= SBI_SSCCTL_PATHALT;
8518                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8519                         udelay(32);
8520                 }
8521                 tmp |= SBI_SSCCTL_DISABLE;
8522                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8523         }
8524
8525         mutex_unlock(&dev_priv->sb_lock);
8526 }
8527
8528 static void lpt_init_pch_refclk(struct drm_device *dev)
8529 {
8530         struct intel_encoder *encoder;
8531         bool has_vga = false;
8532
8533         for_each_intel_encoder(dev, encoder) {
8534                 switch (encoder->type) {
8535                 case INTEL_OUTPUT_ANALOG:
8536                         has_vga = true;
8537                         break;
8538                 default:
8539                         break;
8540                 }
8541         }
8542
8543         if (has_vga)
8544                 lpt_enable_clkout_dp(dev, true, true);
8545         else
8546                 lpt_disable_clkout_dp(dev);
8547 }
8548
8549 /*
8550  * Initialize reference clocks when the driver loads
8551  */
8552 void intel_init_pch_refclk(struct drm_device *dev)
8553 {
8554         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8555                 ironlake_init_pch_refclk(dev);
8556         else if (HAS_PCH_LPT(dev))
8557                 lpt_init_pch_refclk(dev);
8558 }
8559
8560 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8561 {
8562         struct drm_device *dev = crtc_state->base.crtc->dev;
8563         struct drm_i915_private *dev_priv = dev->dev_private;
8564         struct drm_atomic_state *state = crtc_state->base.state;
8565         struct drm_connector *connector;
8566         struct drm_connector_state *connector_state;
8567         struct intel_encoder *encoder;
8568         int num_connectors = 0, i;
8569         bool is_lvds = false;
8570
8571         for_each_connector_in_state(state, connector, connector_state, i) {
8572                 if (connector_state->crtc != crtc_state->base.crtc)
8573                         continue;
8574
8575                 encoder = to_intel_encoder(connector_state->best_encoder);
8576
8577                 switch (encoder->type) {
8578                 case INTEL_OUTPUT_LVDS:
8579                         is_lvds = true;
8580                         break;
8581                 default:
8582                         break;
8583                 }
8584                 num_connectors++;
8585         }
8586
8587         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8588                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8589                               dev_priv->vbt.lvds_ssc_freq);
8590                 return dev_priv->vbt.lvds_ssc_freq;
8591         }
8592
8593         return 120000;
8594 }
8595
8596 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8597 {
8598         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8600         int pipe = intel_crtc->pipe;
8601         uint32_t val;
8602
8603         val = 0;
8604
8605         switch (intel_crtc->config->pipe_bpp) {
8606         case 18:
8607                 val |= PIPECONF_6BPC;
8608                 break;
8609         case 24:
8610                 val |= PIPECONF_8BPC;
8611                 break;
8612         case 30:
8613                 val |= PIPECONF_10BPC;
8614                 break;
8615         case 36:
8616                 val |= PIPECONF_12BPC;
8617                 break;
8618         default:
8619                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8620                 BUG();
8621         }
8622
8623         if (intel_crtc->config->dither)
8624                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8625
8626         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8627                 val |= PIPECONF_INTERLACED_ILK;
8628         else
8629                 val |= PIPECONF_PROGRESSIVE;
8630
8631         if (intel_crtc->config->limited_color_range)
8632                 val |= PIPECONF_COLOR_RANGE_SELECT;
8633
8634         I915_WRITE(PIPECONF(pipe), val);
8635         POSTING_READ(PIPECONF(pipe));
8636 }
8637
8638 /*
8639  * Set up the pipe CSC unit.
8640  *
8641  * Currently only full range RGB to limited range RGB conversion
8642  * is supported, but eventually this should handle various
8643  * RGB<->YCbCr scenarios as well.
8644  */
8645 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8646 {
8647         struct drm_device *dev = crtc->dev;
8648         struct drm_i915_private *dev_priv = dev->dev_private;
8649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8650         int pipe = intel_crtc->pipe;
8651         uint16_t coeff = 0x7800; /* 1.0 */
8652
8653         /*
8654          * TODO: Check what kind of values actually come out of the pipe
8655          * with these coeff/postoff values and adjust to get the best
8656          * accuracy. Perhaps we even need to take the bpc value into
8657          * consideration.
8658          */
8659
8660         if (intel_crtc->config->limited_color_range)
8661                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8662
8663         /*
8664          * GY/GU and RY/RU should be the other way around according
8665          * to BSpec, but reality doesn't agree. Just set them up in
8666          * a way that results in the correct picture.
8667          */
8668         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8669         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8670
8671         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8672         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8673
8674         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8675         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8676
8677         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8678         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8679         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8680
8681         if (INTEL_INFO(dev)->gen > 6) {
8682                 uint16_t postoff = 0;
8683
8684                 if (intel_crtc->config->limited_color_range)
8685                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8686
8687                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8688                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8689                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8690
8691                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8692         } else {
8693                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8694
8695                 if (intel_crtc->config->limited_color_range)
8696                         mode |= CSC_BLACK_SCREEN_OFFSET;
8697
8698                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8699         }
8700 }
8701
8702 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8703 {
8704         struct drm_device *dev = crtc->dev;
8705         struct drm_i915_private *dev_priv = dev->dev_private;
8706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8707         enum pipe pipe = intel_crtc->pipe;
8708         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8709         uint32_t val;
8710
8711         val = 0;
8712
8713         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8714                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8715
8716         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8717                 val |= PIPECONF_INTERLACED_ILK;
8718         else
8719                 val |= PIPECONF_PROGRESSIVE;
8720
8721         I915_WRITE(PIPECONF(cpu_transcoder), val);
8722         POSTING_READ(PIPECONF(cpu_transcoder));
8723
8724         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8725         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8726
8727         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8728                 val = 0;
8729
8730                 switch (intel_crtc->config->pipe_bpp) {
8731                 case 18:
8732                         val |= PIPEMISC_DITHER_6_BPC;
8733                         break;
8734                 case 24:
8735                         val |= PIPEMISC_DITHER_8_BPC;
8736                         break;
8737                 case 30:
8738                         val |= PIPEMISC_DITHER_10_BPC;
8739                         break;
8740                 case 36:
8741                         val |= PIPEMISC_DITHER_12_BPC;
8742                         break;
8743                 default:
8744                         /* Case prevented by pipe_config_set_bpp. */
8745                         BUG();
8746                 }
8747
8748                 if (intel_crtc->config->dither)
8749                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8750
8751                 I915_WRITE(PIPEMISC(pipe), val);
8752         }
8753 }
8754
8755 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8756                                     struct intel_crtc_state *crtc_state,
8757                                     intel_clock_t *clock,
8758                                     bool *has_reduced_clock,
8759                                     intel_clock_t *reduced_clock)
8760 {
8761         struct drm_device *dev = crtc->dev;
8762         struct drm_i915_private *dev_priv = dev->dev_private;
8763         int refclk;
8764         const intel_limit_t *limit;
8765         bool ret;
8766
8767         refclk = ironlake_get_refclk(crtc_state);
8768
8769         /*
8770          * Returns a set of divisors for the desired target clock with the given
8771          * refclk, or FALSE.  The returned values represent the clock equation:
8772          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8773          */
8774         limit = intel_limit(crtc_state, refclk);
8775         ret = dev_priv->display.find_dpll(limit, crtc_state,
8776                                           crtc_state->port_clock,
8777                                           refclk, NULL, clock);
8778         if (!ret)
8779                 return false;
8780
8781         return true;
8782 }
8783
8784 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8785 {
8786         /*
8787          * Account for spread spectrum to avoid
8788          * oversubscribing the link. Max center spread
8789          * is 2.5%; use 5% for safety's sake.
8790          */
8791         u32 bps = target_clock * bpp * 21 / 20;
8792         return DIV_ROUND_UP(bps, link_bw * 8);
8793 }
8794
8795 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8796 {
8797         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8798 }
8799
8800 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8801                                       struct intel_crtc_state *crtc_state,
8802                                       u32 *fp,
8803                                       intel_clock_t *reduced_clock, u32 *fp2)
8804 {
8805         struct drm_crtc *crtc = &intel_crtc->base;
8806         struct drm_device *dev = crtc->dev;
8807         struct drm_i915_private *dev_priv = dev->dev_private;
8808         struct drm_atomic_state *state = crtc_state->base.state;
8809         struct drm_connector *connector;
8810         struct drm_connector_state *connector_state;
8811         struct intel_encoder *encoder;
8812         uint32_t dpll;
8813         int factor, num_connectors = 0, i;
8814         bool is_lvds = false, is_sdvo = false;
8815
8816         for_each_connector_in_state(state, connector, connector_state, i) {
8817                 if (connector_state->crtc != crtc_state->base.crtc)
8818                         continue;
8819
8820                 encoder = to_intel_encoder(connector_state->best_encoder);
8821
8822                 switch (encoder->type) {
8823                 case INTEL_OUTPUT_LVDS:
8824                         is_lvds = true;
8825                         break;
8826                 case INTEL_OUTPUT_SDVO:
8827                 case INTEL_OUTPUT_HDMI:
8828                         is_sdvo = true;
8829                         break;
8830                 default:
8831                         break;
8832                 }
8833
8834                 num_connectors++;
8835         }
8836
8837         /* Enable autotuning of the PLL clock (if permissible) */
8838         factor = 21;
8839         if (is_lvds) {
8840                 if ((intel_panel_use_ssc(dev_priv) &&
8841                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8842                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8843                         factor = 25;
8844         } else if (crtc_state->sdvo_tv_clock)
8845                 factor = 20;
8846
8847         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8848                 *fp |= FP_CB_TUNE;
8849
8850         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8851                 *fp2 |= FP_CB_TUNE;
8852
8853         dpll = 0;
8854
8855         if (is_lvds)
8856                 dpll |= DPLLB_MODE_LVDS;
8857         else
8858                 dpll |= DPLLB_MODE_DAC_SERIAL;
8859
8860         dpll |= (crtc_state->pixel_multiplier - 1)
8861                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8862
8863         if (is_sdvo)
8864                 dpll |= DPLL_SDVO_HIGH_SPEED;
8865         if (crtc_state->has_dp_encoder)
8866                 dpll |= DPLL_SDVO_HIGH_SPEED;
8867
8868         /* compute bitmask from p1 value */
8869         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8870         /* also FPA1 */
8871         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8872
8873         switch (crtc_state->dpll.p2) {
8874         case 5:
8875                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8876                 break;
8877         case 7:
8878                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8879                 break;
8880         case 10:
8881                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8882                 break;
8883         case 14:
8884                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8885                 break;
8886         }
8887
8888         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8889                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8890         else
8891                 dpll |= PLL_REF_INPUT_DREFCLK;
8892
8893         return dpll | DPLL_VCO_ENABLE;
8894 }
8895
8896 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8897                                        struct intel_crtc_state *crtc_state)
8898 {
8899         struct drm_device *dev = crtc->base.dev;
8900         intel_clock_t clock, reduced_clock;
8901         u32 dpll = 0, fp = 0, fp2 = 0;
8902         bool ok, has_reduced_clock = false;
8903         bool is_lvds = false;
8904         struct intel_shared_dpll *pll;
8905
8906         memset(&crtc_state->dpll_hw_state, 0,
8907                sizeof(crtc_state->dpll_hw_state));
8908
8909         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8910
8911         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8912              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8913
8914         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8915                                      &has_reduced_clock, &reduced_clock);
8916         if (!ok && !crtc_state->clock_set) {
8917                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8918                 return -EINVAL;
8919         }
8920         /* Compat-code for transition, will disappear. */
8921         if (!crtc_state->clock_set) {
8922                 crtc_state->dpll.n = clock.n;
8923                 crtc_state->dpll.m1 = clock.m1;
8924                 crtc_state->dpll.m2 = clock.m2;
8925                 crtc_state->dpll.p1 = clock.p1;
8926                 crtc_state->dpll.p2 = clock.p2;
8927         }
8928
8929         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8930         if (crtc_state->has_pch_encoder) {
8931                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8932                 if (has_reduced_clock)
8933                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8934
8935                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8936                                              &fp, &reduced_clock,
8937                                              has_reduced_clock ? &fp2 : NULL);
8938
8939                 crtc_state->dpll_hw_state.dpll = dpll;
8940                 crtc_state->dpll_hw_state.fp0 = fp;
8941                 if (has_reduced_clock)
8942                         crtc_state->dpll_hw_state.fp1 = fp2;
8943                 else
8944                         crtc_state->dpll_hw_state.fp1 = fp;
8945
8946                 pll = intel_get_shared_dpll(crtc, crtc_state);
8947                 if (pll == NULL) {
8948                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8949                                          pipe_name(crtc->pipe));
8950                         return -EINVAL;
8951                 }
8952         }
8953
8954         if (is_lvds && has_reduced_clock)
8955                 crtc->lowfreq_avail = true;
8956         else
8957                 crtc->lowfreq_avail = false;
8958
8959         return 0;
8960 }
8961
8962 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8963                                          struct intel_link_m_n *m_n)
8964 {
8965         struct drm_device *dev = crtc->base.dev;
8966         struct drm_i915_private *dev_priv = dev->dev_private;
8967         enum pipe pipe = crtc->pipe;
8968
8969         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8970         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8971         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8972                 & ~TU_SIZE_MASK;
8973         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8974         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8975                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976 }
8977
8978 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8979                                          enum transcoder transcoder,
8980                                          struct intel_link_m_n *m_n,
8981                                          struct intel_link_m_n *m2_n2)
8982 {
8983         struct drm_device *dev = crtc->base.dev;
8984         struct drm_i915_private *dev_priv = dev->dev_private;
8985         enum pipe pipe = crtc->pipe;
8986
8987         if (INTEL_INFO(dev)->gen >= 5) {
8988                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8989                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8990                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8991                         & ~TU_SIZE_MASK;
8992                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8993                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8994                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8995                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8996                  * gen < 8) and if DRRS is supported (to make sure the
8997                  * registers are not unnecessarily read).
8998                  */
8999                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9000                         crtc->config->has_drrs) {
9001                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9002                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9003                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9004                                         & ~TU_SIZE_MASK;
9005                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9006                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9007                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9008                 }
9009         } else {
9010                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9011                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9012                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9013                         & ~TU_SIZE_MASK;
9014                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9015                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9016                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9017         }
9018 }
9019
9020 void intel_dp_get_m_n(struct intel_crtc *crtc,
9021                       struct intel_crtc_state *pipe_config)
9022 {
9023         if (pipe_config->has_pch_encoder)
9024                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9025         else
9026                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9027                                              &pipe_config->dp_m_n,
9028                                              &pipe_config->dp_m2_n2);
9029 }
9030
9031 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9032                                         struct intel_crtc_state *pipe_config)
9033 {
9034         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9035                                      &pipe_config->fdi_m_n, NULL);
9036 }
9037
9038 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9039                                     struct intel_crtc_state *pipe_config)
9040 {
9041         struct drm_device *dev = crtc->base.dev;
9042         struct drm_i915_private *dev_priv = dev->dev_private;
9043         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9044         uint32_t ps_ctrl = 0;
9045         int id = -1;
9046         int i;
9047
9048         /* find scaler attached to this pipe */
9049         for (i = 0; i < crtc->num_scalers; i++) {
9050                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9051                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9052                         id = i;
9053                         pipe_config->pch_pfit.enabled = true;
9054                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9055                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9056                         break;
9057                 }
9058         }
9059
9060         scaler_state->scaler_id = id;
9061         if (id >= 0) {
9062                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9063         } else {
9064                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9065         }
9066 }
9067
9068 static void
9069 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9070                                  struct intel_initial_plane_config *plane_config)
9071 {
9072         struct drm_device *dev = crtc->base.dev;
9073         struct drm_i915_private *dev_priv = dev->dev_private;
9074         u32 val, base, offset, stride_mult, tiling;
9075         int pipe = crtc->pipe;
9076         int fourcc, pixel_format;
9077         unsigned int aligned_height;
9078         struct drm_framebuffer *fb;
9079         struct intel_framebuffer *intel_fb;
9080
9081         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9082         if (!intel_fb) {
9083                 DRM_DEBUG_KMS("failed to alloc fb\n");
9084                 return;
9085         }
9086
9087         fb = &intel_fb->base;
9088
9089         val = I915_READ(PLANE_CTL(pipe, 0));
9090         if (!(val & PLANE_CTL_ENABLE))
9091                 goto error;
9092
9093         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9094         fourcc = skl_format_to_fourcc(pixel_format,
9095                                       val & PLANE_CTL_ORDER_RGBX,
9096                                       val & PLANE_CTL_ALPHA_MASK);
9097         fb->pixel_format = fourcc;
9098         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9099
9100         tiling = val & PLANE_CTL_TILED_MASK;
9101         switch (tiling) {
9102         case PLANE_CTL_TILED_LINEAR:
9103                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9104                 break;
9105         case PLANE_CTL_TILED_X:
9106                 plane_config->tiling = I915_TILING_X;
9107                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9108                 break;
9109         case PLANE_CTL_TILED_Y:
9110                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9111                 break;
9112         case PLANE_CTL_TILED_YF:
9113                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9114                 break;
9115         default:
9116                 MISSING_CASE(tiling);
9117                 goto error;
9118         }
9119
9120         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9121         plane_config->base = base;
9122
9123         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9124
9125         val = I915_READ(PLANE_SIZE(pipe, 0));
9126         fb->height = ((val >> 16) & 0xfff) + 1;
9127         fb->width = ((val >> 0) & 0x1fff) + 1;
9128
9129         val = I915_READ(PLANE_STRIDE(pipe, 0));
9130         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9131                                                 fb->pixel_format);
9132         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9133
9134         aligned_height = intel_fb_align_height(dev, fb->height,
9135                                                fb->pixel_format,
9136                                                fb->modifier[0]);
9137
9138         plane_config->size = fb->pitches[0] * aligned_height;
9139
9140         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9141                       pipe_name(pipe), fb->width, fb->height,
9142                       fb->bits_per_pixel, base, fb->pitches[0],
9143                       plane_config->size);
9144
9145         plane_config->fb = intel_fb;
9146         return;
9147
9148 error:
9149         kfree(fb);
9150 }
9151
9152 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9153                                      struct intel_crtc_state *pipe_config)
9154 {
9155         struct drm_device *dev = crtc->base.dev;
9156         struct drm_i915_private *dev_priv = dev->dev_private;
9157         uint32_t tmp;
9158
9159         tmp = I915_READ(PF_CTL(crtc->pipe));
9160
9161         if (tmp & PF_ENABLE) {
9162                 pipe_config->pch_pfit.enabled = true;
9163                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9164                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9165
9166                 /* We currently do not free assignements of panel fitters on
9167                  * ivb/hsw (since we don't use the higher upscaling modes which
9168                  * differentiates them) so just WARN about this case for now. */
9169                 if (IS_GEN7(dev)) {
9170                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9171                                 PF_PIPE_SEL_IVB(crtc->pipe));
9172                 }
9173         }
9174 }
9175
9176 static void
9177 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9178                                   struct intel_initial_plane_config *plane_config)
9179 {
9180         struct drm_device *dev = crtc->base.dev;
9181         struct drm_i915_private *dev_priv = dev->dev_private;
9182         u32 val, base, offset;
9183         int pipe = crtc->pipe;
9184         int fourcc, pixel_format;
9185         unsigned int aligned_height;
9186         struct drm_framebuffer *fb;
9187         struct intel_framebuffer *intel_fb;
9188
9189         val = I915_READ(DSPCNTR(pipe));
9190         if (!(val & DISPLAY_PLANE_ENABLE))
9191                 return;
9192
9193         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9194         if (!intel_fb) {
9195                 DRM_DEBUG_KMS("failed to alloc fb\n");
9196                 return;
9197         }
9198
9199         fb = &intel_fb->base;
9200
9201         if (INTEL_INFO(dev)->gen >= 4) {
9202                 if (val & DISPPLANE_TILED) {
9203                         plane_config->tiling = I915_TILING_X;
9204                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9205                 }
9206         }
9207
9208         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9209         fourcc = i9xx_format_to_fourcc(pixel_format);
9210         fb->pixel_format = fourcc;
9211         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9212
9213         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9214         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9215                 offset = I915_READ(DSPOFFSET(pipe));
9216         } else {
9217                 if (plane_config->tiling)
9218                         offset = I915_READ(DSPTILEOFF(pipe));
9219                 else
9220                         offset = I915_READ(DSPLINOFF(pipe));
9221         }
9222         plane_config->base = base;
9223
9224         val = I915_READ(PIPESRC(pipe));
9225         fb->width = ((val >> 16) & 0xfff) + 1;
9226         fb->height = ((val >> 0) & 0xfff) + 1;
9227
9228         val = I915_READ(DSPSTRIDE(pipe));
9229         fb->pitches[0] = val & 0xffffffc0;
9230
9231         aligned_height = intel_fb_align_height(dev, fb->height,
9232                                                fb->pixel_format,
9233                                                fb->modifier[0]);
9234
9235         plane_config->size = fb->pitches[0] * aligned_height;
9236
9237         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9238                       pipe_name(pipe), fb->width, fb->height,
9239                       fb->bits_per_pixel, base, fb->pitches[0],
9240                       plane_config->size);
9241
9242         plane_config->fb = intel_fb;
9243 }
9244
9245 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9246                                      struct intel_crtc_state *pipe_config)
9247 {
9248         struct drm_device *dev = crtc->base.dev;
9249         struct drm_i915_private *dev_priv = dev->dev_private;
9250         uint32_t tmp;
9251
9252         if (!intel_display_power_is_enabled(dev_priv,
9253                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9254                 return false;
9255
9256         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9257         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9258
9259         tmp = I915_READ(PIPECONF(crtc->pipe));
9260         if (!(tmp & PIPECONF_ENABLE))
9261                 return false;
9262
9263         switch (tmp & PIPECONF_BPC_MASK) {
9264         case PIPECONF_6BPC:
9265                 pipe_config->pipe_bpp = 18;
9266                 break;
9267         case PIPECONF_8BPC:
9268                 pipe_config->pipe_bpp = 24;
9269                 break;
9270         case PIPECONF_10BPC:
9271                 pipe_config->pipe_bpp = 30;
9272                 break;
9273         case PIPECONF_12BPC:
9274                 pipe_config->pipe_bpp = 36;
9275                 break;
9276         default:
9277                 break;
9278         }
9279
9280         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9281                 pipe_config->limited_color_range = true;
9282
9283         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9284                 struct intel_shared_dpll *pll;
9285
9286                 pipe_config->has_pch_encoder = true;
9287
9288                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9289                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9290                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9291
9292                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9293
9294                 if (HAS_PCH_IBX(dev_priv->dev)) {
9295                         pipe_config->shared_dpll =
9296                                 (enum intel_dpll_id) crtc->pipe;
9297                 } else {
9298                         tmp = I915_READ(PCH_DPLL_SEL);
9299                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9300                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9301                         else
9302                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9303                 }
9304
9305                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9306
9307                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9308                                            &pipe_config->dpll_hw_state));
9309
9310                 tmp = pipe_config->dpll_hw_state.dpll;
9311                 pipe_config->pixel_multiplier =
9312                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9313                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9314
9315                 ironlake_pch_clock_get(crtc, pipe_config);
9316         } else {
9317                 pipe_config->pixel_multiplier = 1;
9318         }
9319
9320         intel_get_pipe_timings(crtc, pipe_config);
9321
9322         ironlake_get_pfit_config(crtc, pipe_config);
9323
9324         return true;
9325 }
9326
9327 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9328 {
9329         struct drm_device *dev = dev_priv->dev;
9330         struct intel_crtc *crtc;
9331
9332         for_each_intel_crtc(dev, crtc)
9333                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9334                      pipe_name(crtc->pipe));
9335
9336         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9337         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9338         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9339         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9340         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9341         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9342              "CPU PWM1 enabled\n");
9343         if (IS_HASWELL(dev))
9344                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9345                      "CPU PWM2 enabled\n");
9346         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9347              "PCH PWM1 enabled\n");
9348         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9349              "Utility pin enabled\n");
9350         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9351
9352         /*
9353          * In theory we can still leave IRQs enabled, as long as only the HPD
9354          * interrupts remain enabled. We used to check for that, but since it's
9355          * gen-specific and since we only disable LCPLL after we fully disable
9356          * the interrupts, the check below should be enough.
9357          */
9358         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9359 }
9360
9361 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9362 {
9363         struct drm_device *dev = dev_priv->dev;
9364
9365         if (IS_HASWELL(dev))
9366                 return I915_READ(D_COMP_HSW);
9367         else
9368                 return I915_READ(D_COMP_BDW);
9369 }
9370
9371 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9372 {
9373         struct drm_device *dev = dev_priv->dev;
9374
9375         if (IS_HASWELL(dev)) {
9376                 mutex_lock(&dev_priv->rps.hw_lock);
9377                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9378                                             val))
9379                         DRM_ERROR("Failed to write to D_COMP\n");
9380                 mutex_unlock(&dev_priv->rps.hw_lock);
9381         } else {
9382                 I915_WRITE(D_COMP_BDW, val);
9383                 POSTING_READ(D_COMP_BDW);
9384         }
9385 }
9386
9387 /*
9388  * This function implements pieces of two sequences from BSpec:
9389  * - Sequence for display software to disable LCPLL
9390  * - Sequence for display software to allow package C8+
9391  * The steps implemented here are just the steps that actually touch the LCPLL
9392  * register. Callers should take care of disabling all the display engine
9393  * functions, doing the mode unset, fixing interrupts, etc.
9394  */
9395 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9396                               bool switch_to_fclk, bool allow_power_down)
9397 {
9398         uint32_t val;
9399
9400         assert_can_disable_lcpll(dev_priv);
9401
9402         val = I915_READ(LCPLL_CTL);
9403
9404         if (switch_to_fclk) {
9405                 val |= LCPLL_CD_SOURCE_FCLK;
9406                 I915_WRITE(LCPLL_CTL, val);
9407
9408                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9409                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9410                         DRM_ERROR("Switching to FCLK failed\n");
9411
9412                 val = I915_READ(LCPLL_CTL);
9413         }
9414
9415         val |= LCPLL_PLL_DISABLE;
9416         I915_WRITE(LCPLL_CTL, val);
9417         POSTING_READ(LCPLL_CTL);
9418
9419         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9420                 DRM_ERROR("LCPLL still locked\n");
9421
9422         val = hsw_read_dcomp(dev_priv);
9423         val |= D_COMP_COMP_DISABLE;
9424         hsw_write_dcomp(dev_priv, val);
9425         ndelay(100);
9426
9427         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9428                      1))
9429                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9430
9431         if (allow_power_down) {
9432                 val = I915_READ(LCPLL_CTL);
9433                 val |= LCPLL_POWER_DOWN_ALLOW;
9434                 I915_WRITE(LCPLL_CTL, val);
9435                 POSTING_READ(LCPLL_CTL);
9436         }
9437 }
9438
9439 /*
9440  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9441  * source.
9442  */
9443 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9444 {
9445         uint32_t val;
9446
9447         val = I915_READ(LCPLL_CTL);
9448
9449         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9450                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9451                 return;
9452
9453         /*
9454          * Make sure we're not on PC8 state before disabling PC8, otherwise
9455          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9456          */
9457         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9458
9459         if (val & LCPLL_POWER_DOWN_ALLOW) {
9460                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9461                 I915_WRITE(LCPLL_CTL, val);
9462                 POSTING_READ(LCPLL_CTL);
9463         }
9464
9465         val = hsw_read_dcomp(dev_priv);
9466         val |= D_COMP_COMP_FORCE;
9467         val &= ~D_COMP_COMP_DISABLE;
9468         hsw_write_dcomp(dev_priv, val);
9469
9470         val = I915_READ(LCPLL_CTL);
9471         val &= ~LCPLL_PLL_DISABLE;
9472         I915_WRITE(LCPLL_CTL, val);
9473
9474         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9475                 DRM_ERROR("LCPLL not locked yet\n");
9476
9477         if (val & LCPLL_CD_SOURCE_FCLK) {
9478                 val = I915_READ(LCPLL_CTL);
9479                 val &= ~LCPLL_CD_SOURCE_FCLK;
9480                 I915_WRITE(LCPLL_CTL, val);
9481
9482                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9483                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9484                         DRM_ERROR("Switching back to LCPLL failed\n");
9485         }
9486
9487         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9488         intel_update_cdclk(dev_priv->dev);
9489 }
9490
9491 /*
9492  * Package states C8 and deeper are really deep PC states that can only be
9493  * reached when all the devices on the system allow it, so even if the graphics
9494  * device allows PC8+, it doesn't mean the system will actually get to these
9495  * states. Our driver only allows PC8+ when going into runtime PM.
9496  *
9497  * The requirements for PC8+ are that all the outputs are disabled, the power
9498  * well is disabled and most interrupts are disabled, and these are also
9499  * requirements for runtime PM. When these conditions are met, we manually do
9500  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9501  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9502  * hang the machine.
9503  *
9504  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9505  * the state of some registers, so when we come back from PC8+ we need to
9506  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9507  * need to take care of the registers kept by RC6. Notice that this happens even
9508  * if we don't put the device in PCI D3 state (which is what currently happens
9509  * because of the runtime PM support).
9510  *
9511  * For more, read "Display Sequences for Package C8" on the hardware
9512  * documentation.
9513  */
9514 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9515 {
9516         struct drm_device *dev = dev_priv->dev;
9517         uint32_t val;
9518
9519         DRM_DEBUG_KMS("Enabling package C8+\n");
9520
9521         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9522                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9523                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9524                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9525         }
9526
9527         lpt_disable_clkout_dp(dev);
9528         hsw_disable_lcpll(dev_priv, true, true);
9529 }
9530
9531 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9532 {
9533         struct drm_device *dev = dev_priv->dev;
9534         uint32_t val;
9535
9536         DRM_DEBUG_KMS("Disabling package C8+\n");
9537
9538         hsw_restore_lcpll(dev_priv);
9539         lpt_init_pch_refclk(dev);
9540
9541         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9542                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9543                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9544                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9545         }
9546
9547         intel_prepare_ddi(dev);
9548 }
9549
9550 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9551 {
9552         struct drm_device *dev = old_state->dev;
9553         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9554
9555         broxton_set_cdclk(dev, req_cdclk);
9556 }
9557
9558 /* compute the max rate for new configuration */
9559 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9560 {
9561         struct intel_crtc *intel_crtc;
9562         struct intel_crtc_state *crtc_state;
9563         int max_pixel_rate = 0;
9564
9565         for_each_intel_crtc(state->dev, intel_crtc) {
9566                 int pixel_rate;
9567
9568                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9569                 if (IS_ERR(crtc_state))
9570                         return PTR_ERR(crtc_state);
9571
9572                 if (!crtc_state->base.enable)
9573                         continue;
9574
9575                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9576
9577                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9578                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9579                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9580
9581                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9582         }
9583
9584         return max_pixel_rate;
9585 }
9586
9587 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9588 {
9589         struct drm_i915_private *dev_priv = dev->dev_private;
9590         uint32_t val, data;
9591         int ret;
9592
9593         if (WARN((I915_READ(LCPLL_CTL) &
9594                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9595                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9596                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9597                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9598                  "trying to change cdclk frequency with cdclk not enabled\n"))
9599                 return;
9600
9601         mutex_lock(&dev_priv->rps.hw_lock);
9602         ret = sandybridge_pcode_write(dev_priv,
9603                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9604         mutex_unlock(&dev_priv->rps.hw_lock);
9605         if (ret) {
9606                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9607                 return;
9608         }
9609
9610         val = I915_READ(LCPLL_CTL);
9611         val |= LCPLL_CD_SOURCE_FCLK;
9612         I915_WRITE(LCPLL_CTL, val);
9613
9614         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9615                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9616                 DRM_ERROR("Switching to FCLK failed\n");
9617
9618         val = I915_READ(LCPLL_CTL);
9619         val &= ~LCPLL_CLK_FREQ_MASK;
9620
9621         switch (cdclk) {
9622         case 450000:
9623                 val |= LCPLL_CLK_FREQ_450;
9624                 data = 0;
9625                 break;
9626         case 540000:
9627                 val |= LCPLL_CLK_FREQ_54O_BDW;
9628                 data = 1;
9629                 break;
9630         case 337500:
9631                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9632                 data = 2;
9633                 break;
9634         case 675000:
9635                 val |= LCPLL_CLK_FREQ_675_BDW;
9636                 data = 3;
9637                 break;
9638         default:
9639                 WARN(1, "invalid cdclk frequency\n");
9640                 return;
9641         }
9642
9643         I915_WRITE(LCPLL_CTL, val);
9644
9645         val = I915_READ(LCPLL_CTL);
9646         val &= ~LCPLL_CD_SOURCE_FCLK;
9647         I915_WRITE(LCPLL_CTL, val);
9648
9649         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9650                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9651                 DRM_ERROR("Switching back to LCPLL failed\n");
9652
9653         mutex_lock(&dev_priv->rps.hw_lock);
9654         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9655         mutex_unlock(&dev_priv->rps.hw_lock);
9656
9657         intel_update_cdclk(dev);
9658
9659         WARN(cdclk != dev_priv->cdclk_freq,
9660              "cdclk requested %d kHz but got %d kHz\n",
9661              cdclk, dev_priv->cdclk_freq);
9662 }
9663
9664 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9665 {
9666         struct drm_i915_private *dev_priv = to_i915(state->dev);
9667         int max_pixclk = ilk_max_pixel_rate(state);
9668         int cdclk;
9669
9670         /*
9671          * FIXME should also account for plane ratio
9672          * once 64bpp pixel formats are supported.
9673          */
9674         if (max_pixclk > 540000)
9675                 cdclk = 675000;
9676         else if (max_pixclk > 450000)
9677                 cdclk = 540000;
9678         else if (max_pixclk > 337500)
9679                 cdclk = 450000;
9680         else
9681                 cdclk = 337500;
9682
9683         /*
9684          * FIXME move the cdclk caclulation to
9685          * compute_config() so we can fail gracegully.
9686          */
9687         if (cdclk > dev_priv->max_cdclk_freq) {
9688                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9689                           cdclk, dev_priv->max_cdclk_freq);
9690                 cdclk = dev_priv->max_cdclk_freq;
9691         }
9692
9693         to_intel_atomic_state(state)->cdclk = cdclk;
9694
9695         return 0;
9696 }
9697
9698 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9699 {
9700         struct drm_device *dev = old_state->dev;
9701         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9702
9703         broadwell_set_cdclk(dev, req_cdclk);
9704 }
9705
9706 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9707                                       struct intel_crtc_state *crtc_state)
9708 {
9709         if (!intel_ddi_pll_select(crtc, crtc_state))
9710                 return -EINVAL;
9711
9712         crtc->lowfreq_avail = false;
9713
9714         return 0;
9715 }
9716
9717 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9718                                 enum port port,
9719                                 struct intel_crtc_state *pipe_config)
9720 {
9721         switch (port) {
9722         case PORT_A:
9723                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9724                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9725                 break;
9726         case PORT_B:
9727                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9728                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9729                 break;
9730         case PORT_C:
9731                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9732                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9733                 break;
9734         default:
9735                 DRM_ERROR("Incorrect port type\n");
9736         }
9737 }
9738
9739 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9740                                 enum port port,
9741                                 struct intel_crtc_state *pipe_config)
9742 {
9743         u32 temp, dpll_ctl1;
9744
9745         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9746         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9747
9748         switch (pipe_config->ddi_pll_sel) {
9749         case SKL_DPLL0:
9750                 /*
9751                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9752                  * of the shared DPLL framework and thus needs to be read out
9753                  * separately
9754                  */
9755                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9756                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9757                 break;
9758         case SKL_DPLL1:
9759                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9760                 break;
9761         case SKL_DPLL2:
9762                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9763                 break;
9764         case SKL_DPLL3:
9765                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9766                 break;
9767         }
9768 }
9769
9770 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9771                                 enum port port,
9772                                 struct intel_crtc_state *pipe_config)
9773 {
9774         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9775
9776         switch (pipe_config->ddi_pll_sel) {
9777         case PORT_CLK_SEL_WRPLL1:
9778                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9779                 break;
9780         case PORT_CLK_SEL_WRPLL2:
9781                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9782                 break;
9783         }
9784 }
9785
9786 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9787                                        struct intel_crtc_state *pipe_config)
9788 {
9789         struct drm_device *dev = crtc->base.dev;
9790         struct drm_i915_private *dev_priv = dev->dev_private;
9791         struct intel_shared_dpll *pll;
9792         enum port port;
9793         uint32_t tmp;
9794
9795         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9796
9797         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9798
9799         if (IS_SKYLAKE(dev))
9800                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9801         else if (IS_BROXTON(dev))
9802                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9803         else
9804                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9805
9806         if (pipe_config->shared_dpll >= 0) {
9807                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9808
9809                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9810                                            &pipe_config->dpll_hw_state));
9811         }
9812
9813         /*
9814          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9815          * DDI E. So just check whether this pipe is wired to DDI E and whether
9816          * the PCH transcoder is on.
9817          */
9818         if (INTEL_INFO(dev)->gen < 9 &&
9819             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9820                 pipe_config->has_pch_encoder = true;
9821
9822                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9823                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9824                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9825
9826                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9827         }
9828 }
9829
9830 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9831                                     struct intel_crtc_state *pipe_config)
9832 {
9833         struct drm_device *dev = crtc->base.dev;
9834         struct drm_i915_private *dev_priv = dev->dev_private;
9835         enum intel_display_power_domain pfit_domain;
9836         uint32_t tmp;
9837
9838         if (!intel_display_power_is_enabled(dev_priv,
9839                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9840                 return false;
9841
9842         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9843         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9844
9845         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9846         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9847                 enum pipe trans_edp_pipe;
9848                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9849                 default:
9850                         WARN(1, "unknown pipe linked to edp transcoder\n");
9851                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9852                 case TRANS_DDI_EDP_INPUT_A_ON:
9853                         trans_edp_pipe = PIPE_A;
9854                         break;
9855                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9856                         trans_edp_pipe = PIPE_B;
9857                         break;
9858                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9859                         trans_edp_pipe = PIPE_C;
9860                         break;
9861                 }
9862
9863                 if (trans_edp_pipe == crtc->pipe)
9864                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9865         }
9866
9867         if (!intel_display_power_is_enabled(dev_priv,
9868                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9869                 return false;
9870
9871         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9872         if (!(tmp & PIPECONF_ENABLE))
9873                 return false;
9874
9875         haswell_get_ddi_port_state(crtc, pipe_config);
9876
9877         intel_get_pipe_timings(crtc, pipe_config);
9878
9879         if (INTEL_INFO(dev)->gen >= 9) {
9880                 skl_init_scalers(dev, crtc, pipe_config);
9881         }
9882
9883         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9884
9885         if (INTEL_INFO(dev)->gen >= 9) {
9886                 pipe_config->scaler_state.scaler_id = -1;
9887                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9888         }
9889
9890         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9891                 if (INTEL_INFO(dev)->gen == 9)
9892                         skylake_get_pfit_config(crtc, pipe_config);
9893                 else if (INTEL_INFO(dev)->gen < 9)
9894                         ironlake_get_pfit_config(crtc, pipe_config);
9895                 else
9896                         MISSING_CASE(INTEL_INFO(dev)->gen);
9897         }
9898
9899         if (IS_HASWELL(dev))
9900                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9901                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9902
9903         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9904                 pipe_config->pixel_multiplier =
9905                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9906         } else {
9907                 pipe_config->pixel_multiplier = 1;
9908         }
9909
9910         return true;
9911 }
9912
9913 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9914 {
9915         struct drm_device *dev = crtc->dev;
9916         struct drm_i915_private *dev_priv = dev->dev_private;
9917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9918         uint32_t cntl = 0, size = 0;
9919
9920         if (base) {
9921                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9922                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9923                 unsigned int stride = roundup_pow_of_two(width) * 4;
9924
9925                 switch (stride) {
9926                 default:
9927                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9928                                   width, stride);
9929                         stride = 256;
9930                         /* fallthrough */
9931                 case 256:
9932                 case 512:
9933                 case 1024:
9934                 case 2048:
9935                         break;
9936                 }
9937
9938                 cntl |= CURSOR_ENABLE |
9939                         CURSOR_GAMMA_ENABLE |
9940                         CURSOR_FORMAT_ARGB |
9941                         CURSOR_STRIDE(stride);
9942
9943                 size = (height << 12) | width;
9944         }
9945
9946         if (intel_crtc->cursor_cntl != 0 &&
9947             (intel_crtc->cursor_base != base ||
9948              intel_crtc->cursor_size != size ||
9949              intel_crtc->cursor_cntl != cntl)) {
9950                 /* On these chipsets we can only modify the base/size/stride
9951                  * whilst the cursor is disabled.
9952                  */
9953                 I915_WRITE(_CURACNTR, 0);
9954                 POSTING_READ(_CURACNTR);
9955                 intel_crtc->cursor_cntl = 0;
9956         }
9957
9958         if (intel_crtc->cursor_base != base) {
9959                 I915_WRITE(_CURABASE, base);
9960                 intel_crtc->cursor_base = base;
9961         }
9962
9963         if (intel_crtc->cursor_size != size) {
9964                 I915_WRITE(CURSIZE, size);
9965                 intel_crtc->cursor_size = size;
9966         }
9967
9968         if (intel_crtc->cursor_cntl != cntl) {
9969                 I915_WRITE(_CURACNTR, cntl);
9970                 POSTING_READ(_CURACNTR);
9971                 intel_crtc->cursor_cntl = cntl;
9972         }
9973 }
9974
9975 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9976 {
9977         struct drm_device *dev = crtc->dev;
9978         struct drm_i915_private *dev_priv = dev->dev_private;
9979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9980         int pipe = intel_crtc->pipe;
9981         uint32_t cntl;
9982
9983         cntl = 0;
9984         if (base) {
9985                 cntl = MCURSOR_GAMMA_ENABLE;
9986                 switch (intel_crtc->base.cursor->state->crtc_w) {
9987                         case 64:
9988                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9989                                 break;
9990                         case 128:
9991                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9992                                 break;
9993                         case 256:
9994                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9995                                 break;
9996                         default:
9997                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9998                                 return;
9999                 }
10000                 cntl |= pipe << 28; /* Connect to correct pipe */
10001
10002                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10003                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10004         }
10005
10006         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10007                 cntl |= CURSOR_ROTATE_180;
10008
10009         if (intel_crtc->cursor_cntl != cntl) {
10010                 I915_WRITE(CURCNTR(pipe), cntl);
10011                 POSTING_READ(CURCNTR(pipe));
10012                 intel_crtc->cursor_cntl = cntl;
10013         }
10014
10015         /* and commit changes on next vblank */
10016         I915_WRITE(CURBASE(pipe), base);
10017         POSTING_READ(CURBASE(pipe));
10018
10019         intel_crtc->cursor_base = base;
10020 }
10021
10022 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10023 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10024                                      bool on)
10025 {
10026         struct drm_device *dev = crtc->dev;
10027         struct drm_i915_private *dev_priv = dev->dev_private;
10028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10029         int pipe = intel_crtc->pipe;
10030         int x = crtc->cursor_x;
10031         int y = crtc->cursor_y;
10032         u32 base = 0, pos = 0;
10033
10034         if (on)
10035                 base = intel_crtc->cursor_addr;
10036
10037         if (x >= intel_crtc->config->pipe_src_w)
10038                 base = 0;
10039
10040         if (y >= intel_crtc->config->pipe_src_h)
10041                 base = 0;
10042
10043         if (x < 0) {
10044                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10045                         base = 0;
10046
10047                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10048                 x = -x;
10049         }
10050         pos |= x << CURSOR_X_SHIFT;
10051
10052         if (y < 0) {
10053                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10054                         base = 0;
10055
10056                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10057                 y = -y;
10058         }
10059         pos |= y << CURSOR_Y_SHIFT;
10060
10061         if (base == 0 && intel_crtc->cursor_base == 0)
10062                 return;
10063
10064         I915_WRITE(CURPOS(pipe), pos);
10065
10066         /* ILK+ do this automagically */
10067         if (HAS_GMCH_DISPLAY(dev) &&
10068             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10069                 base += (intel_crtc->base.cursor->state->crtc_h *
10070                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10071         }
10072
10073         if (IS_845G(dev) || IS_I865G(dev))
10074                 i845_update_cursor(crtc, base);
10075         else
10076                 i9xx_update_cursor(crtc, base);
10077 }
10078
10079 static bool cursor_size_ok(struct drm_device *dev,
10080                            uint32_t width, uint32_t height)
10081 {
10082         if (width == 0 || height == 0)
10083                 return false;
10084
10085         /*
10086          * 845g/865g are special in that they are only limited by
10087          * the width of their cursors, the height is arbitrary up to
10088          * the precision of the register. Everything else requires
10089          * square cursors, limited to a few power-of-two sizes.
10090          */
10091         if (IS_845G(dev) || IS_I865G(dev)) {
10092                 if ((width & 63) != 0)
10093                         return false;
10094
10095                 if (width > (IS_845G(dev) ? 64 : 512))
10096                         return false;
10097
10098                 if (height > 1023)
10099                         return false;
10100         } else {
10101                 switch (width | height) {
10102                 case 256:
10103                 case 128:
10104                         if (IS_GEN2(dev))
10105                                 return false;
10106                 case 64:
10107                         break;
10108                 default:
10109                         return false;
10110                 }
10111         }
10112
10113         return true;
10114 }
10115
10116 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10117                                  u16 *blue, uint32_t start, uint32_t size)
10118 {
10119         int end = (start + size > 256) ? 256 : start + size, i;
10120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10121
10122         for (i = start; i < end; i++) {
10123                 intel_crtc->lut_r[i] = red[i] >> 8;
10124                 intel_crtc->lut_g[i] = green[i] >> 8;
10125                 intel_crtc->lut_b[i] = blue[i] >> 8;
10126         }
10127
10128         intel_crtc_load_lut(crtc);
10129 }
10130
10131 /* VESA 640x480x72Hz mode to set on the pipe */
10132 static struct drm_display_mode load_detect_mode = {
10133         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10134                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10135 };
10136
10137 struct drm_framebuffer *
10138 __intel_framebuffer_create(struct drm_device *dev,
10139                            struct drm_mode_fb_cmd2 *mode_cmd,
10140                            struct drm_i915_gem_object *obj)
10141 {
10142         struct intel_framebuffer *intel_fb;
10143         int ret;
10144
10145         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10146         if (!intel_fb) {
10147                 drm_gem_object_unreference(&obj->base);
10148                 return ERR_PTR(-ENOMEM);
10149         }
10150
10151         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10152         if (ret)
10153                 goto err;
10154
10155         return &intel_fb->base;
10156 err:
10157         drm_gem_object_unreference(&obj->base);
10158         kfree(intel_fb);
10159
10160         return ERR_PTR(ret);
10161 }
10162
10163 static struct drm_framebuffer *
10164 intel_framebuffer_create(struct drm_device *dev,
10165                          struct drm_mode_fb_cmd2 *mode_cmd,
10166                          struct drm_i915_gem_object *obj)
10167 {
10168         struct drm_framebuffer *fb;
10169         int ret;
10170
10171         ret = i915_mutex_lock_interruptible(dev);
10172         if (ret)
10173                 return ERR_PTR(ret);
10174         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10175         mutex_unlock(&dev->struct_mutex);
10176
10177         return fb;
10178 }
10179
10180 static u32
10181 intel_framebuffer_pitch_for_width(int width, int bpp)
10182 {
10183         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10184         return ALIGN(pitch, 64);
10185 }
10186
10187 static u32
10188 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10189 {
10190         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10191         return PAGE_ALIGN(pitch * mode->vdisplay);
10192 }
10193
10194 static struct drm_framebuffer *
10195 intel_framebuffer_create_for_mode(struct drm_device *dev,
10196                                   struct drm_display_mode *mode,
10197                                   int depth, int bpp)
10198 {
10199         struct drm_i915_gem_object *obj;
10200         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10201
10202         obj = i915_gem_alloc_object(dev,
10203                                     intel_framebuffer_size_for_mode(mode, bpp));
10204         if (obj == NULL)
10205                 return ERR_PTR(-ENOMEM);
10206
10207         mode_cmd.width = mode->hdisplay;
10208         mode_cmd.height = mode->vdisplay;
10209         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10210                                                                 bpp);
10211         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10212
10213         return intel_framebuffer_create(dev, &mode_cmd, obj);
10214 }
10215
10216 static struct drm_framebuffer *
10217 mode_fits_in_fbdev(struct drm_device *dev,
10218                    struct drm_display_mode *mode)
10219 {
10220 #ifdef CONFIG_DRM_I915_FBDEV
10221         struct drm_i915_private *dev_priv = dev->dev_private;
10222         struct drm_i915_gem_object *obj;
10223         struct drm_framebuffer *fb;
10224
10225         if (!dev_priv->fbdev)
10226                 return NULL;
10227
10228         if (!dev_priv->fbdev->fb)
10229                 return NULL;
10230
10231         obj = dev_priv->fbdev->fb->obj;
10232         BUG_ON(!obj);
10233
10234         fb = &dev_priv->fbdev->fb->base;
10235         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10236                                                                fb->bits_per_pixel))
10237                 return NULL;
10238
10239         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10240                 return NULL;
10241
10242         return fb;
10243 #else
10244         return NULL;
10245 #endif
10246 }
10247
10248 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10249                                            struct drm_crtc *crtc,
10250                                            struct drm_display_mode *mode,
10251                                            struct drm_framebuffer *fb,
10252                                            int x, int y)
10253 {
10254         struct drm_plane_state *plane_state;
10255         int hdisplay, vdisplay;
10256         int ret;
10257
10258         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10259         if (IS_ERR(plane_state))
10260                 return PTR_ERR(plane_state);
10261
10262         if (mode)
10263                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10264         else
10265                 hdisplay = vdisplay = 0;
10266
10267         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10268         if (ret)
10269                 return ret;
10270         drm_atomic_set_fb_for_plane(plane_state, fb);
10271         plane_state->crtc_x = 0;
10272         plane_state->crtc_y = 0;
10273         plane_state->crtc_w = hdisplay;
10274         plane_state->crtc_h = vdisplay;
10275         plane_state->src_x = x << 16;
10276         plane_state->src_y = y << 16;
10277         plane_state->src_w = hdisplay << 16;
10278         plane_state->src_h = vdisplay << 16;
10279
10280         return 0;
10281 }
10282
10283 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10284                                 struct drm_display_mode *mode,
10285                                 struct intel_load_detect_pipe *old,
10286                                 struct drm_modeset_acquire_ctx *ctx)
10287 {
10288         struct intel_crtc *intel_crtc;
10289         struct intel_encoder *intel_encoder =
10290                 intel_attached_encoder(connector);
10291         struct drm_crtc *possible_crtc;
10292         struct drm_encoder *encoder = &intel_encoder->base;
10293         struct drm_crtc *crtc = NULL;
10294         struct drm_device *dev = encoder->dev;
10295         struct drm_framebuffer *fb;
10296         struct drm_mode_config *config = &dev->mode_config;
10297         struct drm_atomic_state *state = NULL;
10298         struct drm_connector_state *connector_state;
10299         struct intel_crtc_state *crtc_state;
10300         int ret, i = -1;
10301
10302         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10303                       connector->base.id, connector->name,
10304                       encoder->base.id, encoder->name);
10305
10306 retry:
10307         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10308         if (ret)
10309                 goto fail;
10310
10311         /*
10312          * Algorithm gets a little messy:
10313          *
10314          *   - if the connector already has an assigned crtc, use it (but make
10315          *     sure it's on first)
10316          *
10317          *   - try to find the first unused crtc that can drive this connector,
10318          *     and use that if we find one
10319          */
10320
10321         /* See if we already have a CRTC for this connector */
10322         if (encoder->crtc) {
10323                 crtc = encoder->crtc;
10324
10325                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10326                 if (ret)
10327                         goto fail;
10328                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10329                 if (ret)
10330                         goto fail;
10331
10332                 old->dpms_mode = connector->dpms;
10333                 old->load_detect_temp = false;
10334
10335                 /* Make sure the crtc and connector are running */
10336                 if (connector->dpms != DRM_MODE_DPMS_ON)
10337                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10338
10339                 return true;
10340         }
10341
10342         /* Find an unused one (if possible) */
10343         for_each_crtc(dev, possible_crtc) {
10344                 i++;
10345                 if (!(encoder->possible_crtcs & (1 << i)))
10346                         continue;
10347                 if (possible_crtc->state->enable)
10348                         continue;
10349
10350                 crtc = possible_crtc;
10351                 break;
10352         }
10353
10354         /*
10355          * If we didn't find an unused CRTC, don't use any.
10356          */
10357         if (!crtc) {
10358                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10359                 goto fail;
10360         }
10361
10362         ret = drm_modeset_lock(&crtc->mutex, ctx);
10363         if (ret)
10364                 goto fail;
10365         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10366         if (ret)
10367                 goto fail;
10368
10369         intel_crtc = to_intel_crtc(crtc);
10370         old->dpms_mode = connector->dpms;
10371         old->load_detect_temp = true;
10372         old->release_fb = NULL;
10373
10374         state = drm_atomic_state_alloc(dev);
10375         if (!state)
10376                 return false;
10377
10378         state->acquire_ctx = ctx;
10379
10380         connector_state = drm_atomic_get_connector_state(state, connector);
10381         if (IS_ERR(connector_state)) {
10382                 ret = PTR_ERR(connector_state);
10383                 goto fail;
10384         }
10385
10386         connector_state->crtc = crtc;
10387         connector_state->best_encoder = &intel_encoder->base;
10388
10389         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10390         if (IS_ERR(crtc_state)) {
10391                 ret = PTR_ERR(crtc_state);
10392                 goto fail;
10393         }
10394
10395         crtc_state->base.active = crtc_state->base.enable = true;
10396
10397         if (!mode)
10398                 mode = &load_detect_mode;
10399
10400         /* We need a framebuffer large enough to accommodate all accesses
10401          * that the plane may generate whilst we perform load detection.
10402          * We can not rely on the fbcon either being present (we get called
10403          * during its initialisation to detect all boot displays, or it may
10404          * not even exist) or that it is large enough to satisfy the
10405          * requested mode.
10406          */
10407         fb = mode_fits_in_fbdev(dev, mode);
10408         if (fb == NULL) {
10409                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10410                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10411                 old->release_fb = fb;
10412         } else
10413                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10414         if (IS_ERR(fb)) {
10415                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10416                 goto fail;
10417         }
10418
10419         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10420         if (ret)
10421                 goto fail;
10422
10423         drm_mode_copy(&crtc_state->base.mode, mode);
10424
10425         if (drm_atomic_commit(state)) {
10426                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10427                 if (old->release_fb)
10428                         old->release_fb->funcs->destroy(old->release_fb);
10429                 goto fail;
10430         }
10431         crtc->primary->crtc = crtc;
10432
10433         /* let the connector get through one full cycle before testing */
10434         intel_wait_for_vblank(dev, intel_crtc->pipe);
10435         return true;
10436
10437 fail:
10438         drm_atomic_state_free(state);
10439         state = NULL;
10440
10441         if (ret == -EDEADLK) {
10442                 drm_modeset_backoff(ctx);
10443                 goto retry;
10444         }
10445
10446         return false;
10447 }
10448
10449 void intel_release_load_detect_pipe(struct drm_connector *connector,
10450                                     struct intel_load_detect_pipe *old,
10451                                     struct drm_modeset_acquire_ctx *ctx)
10452 {
10453         struct drm_device *dev = connector->dev;
10454         struct intel_encoder *intel_encoder =
10455                 intel_attached_encoder(connector);
10456         struct drm_encoder *encoder = &intel_encoder->base;
10457         struct drm_crtc *crtc = encoder->crtc;
10458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10459         struct drm_atomic_state *state;
10460         struct drm_connector_state *connector_state;
10461         struct intel_crtc_state *crtc_state;
10462         int ret;
10463
10464         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10465                       connector->base.id, connector->name,
10466                       encoder->base.id, encoder->name);
10467
10468         if (old->load_detect_temp) {
10469                 state = drm_atomic_state_alloc(dev);
10470                 if (!state)
10471                         goto fail;
10472
10473                 state->acquire_ctx = ctx;
10474
10475                 connector_state = drm_atomic_get_connector_state(state, connector);
10476                 if (IS_ERR(connector_state))
10477                         goto fail;
10478
10479                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10480                 if (IS_ERR(crtc_state))
10481                         goto fail;
10482
10483                 connector_state->best_encoder = NULL;
10484                 connector_state->crtc = NULL;
10485
10486                 crtc_state->base.enable = crtc_state->base.active = false;
10487
10488                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10489                                                       0, 0);
10490                 if (ret)
10491                         goto fail;
10492
10493                 ret = drm_atomic_commit(state);
10494                 if (ret)
10495                         goto fail;
10496
10497                 if (old->release_fb) {
10498                         drm_framebuffer_unregister_private(old->release_fb);
10499                         drm_framebuffer_unreference(old->release_fb);
10500                 }
10501
10502                 return;
10503         }
10504
10505         /* Switch crtc and encoder back off if necessary */
10506         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10507                 connector->funcs->dpms(connector, old->dpms_mode);
10508
10509         return;
10510 fail:
10511         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10512         drm_atomic_state_free(state);
10513 }
10514
10515 static int i9xx_pll_refclk(struct drm_device *dev,
10516                            const struct intel_crtc_state *pipe_config)
10517 {
10518         struct drm_i915_private *dev_priv = dev->dev_private;
10519         u32 dpll = pipe_config->dpll_hw_state.dpll;
10520
10521         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10522                 return dev_priv->vbt.lvds_ssc_freq;
10523         else if (HAS_PCH_SPLIT(dev))
10524                 return 120000;
10525         else if (!IS_GEN2(dev))
10526                 return 96000;
10527         else
10528                 return 48000;
10529 }
10530
10531 /* Returns the clock of the currently programmed mode of the given pipe. */
10532 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10533                                 struct intel_crtc_state *pipe_config)
10534 {
10535         struct drm_device *dev = crtc->base.dev;
10536         struct drm_i915_private *dev_priv = dev->dev_private;
10537         int pipe = pipe_config->cpu_transcoder;
10538         u32 dpll = pipe_config->dpll_hw_state.dpll;
10539         u32 fp;
10540         intel_clock_t clock;
10541         int port_clock;
10542         int refclk = i9xx_pll_refclk(dev, pipe_config);
10543
10544         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10545                 fp = pipe_config->dpll_hw_state.fp0;
10546         else
10547                 fp = pipe_config->dpll_hw_state.fp1;
10548
10549         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10550         if (IS_PINEVIEW(dev)) {
10551                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10552                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10553         } else {
10554                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10555                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10556         }
10557
10558         if (!IS_GEN2(dev)) {
10559                 if (IS_PINEVIEW(dev))
10560                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10561                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10562                 else
10563                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10564                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10565
10566                 switch (dpll & DPLL_MODE_MASK) {
10567                 case DPLLB_MODE_DAC_SERIAL:
10568                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10569                                 5 : 10;
10570                         break;
10571                 case DPLLB_MODE_LVDS:
10572                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10573                                 7 : 14;
10574                         break;
10575                 default:
10576                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10577                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10578                         return;
10579                 }
10580
10581                 if (IS_PINEVIEW(dev))
10582                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10583                 else
10584                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10585         } else {
10586                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10587                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10588
10589                 if (is_lvds) {
10590                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10591                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10592
10593                         if (lvds & LVDS_CLKB_POWER_UP)
10594                                 clock.p2 = 7;
10595                         else
10596                                 clock.p2 = 14;
10597                 } else {
10598                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10599                                 clock.p1 = 2;
10600                         else {
10601                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10602                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10603                         }
10604                         if (dpll & PLL_P2_DIVIDE_BY_4)
10605                                 clock.p2 = 4;
10606                         else
10607                                 clock.p2 = 2;
10608                 }
10609
10610                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10611         }
10612
10613         /*
10614          * This value includes pixel_multiplier. We will use
10615          * port_clock to compute adjusted_mode.crtc_clock in the
10616          * encoder's get_config() function.
10617          */
10618         pipe_config->port_clock = port_clock;
10619 }
10620
10621 int intel_dotclock_calculate(int link_freq,
10622                              const struct intel_link_m_n *m_n)
10623 {
10624         /*
10625          * The calculation for the data clock is:
10626          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10627          * But we want to avoid losing precison if possible, so:
10628          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10629          *
10630          * and the link clock is simpler:
10631          * link_clock = (m * link_clock) / n
10632          */
10633
10634         if (!m_n->link_n)
10635                 return 0;
10636
10637         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10638 }
10639
10640 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10641                                    struct intel_crtc_state *pipe_config)
10642 {
10643         struct drm_device *dev = crtc->base.dev;
10644
10645         /* read out port_clock from the DPLL */
10646         i9xx_crtc_clock_get(crtc, pipe_config);
10647
10648         /*
10649          * This value does not include pixel_multiplier.
10650          * We will check that port_clock and adjusted_mode.crtc_clock
10651          * agree once we know their relationship in the encoder's
10652          * get_config() function.
10653          */
10654         pipe_config->base.adjusted_mode.crtc_clock =
10655                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10656                                          &pipe_config->fdi_m_n);
10657 }
10658
10659 /** Returns the currently programmed mode of the given pipe. */
10660 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10661                                              struct drm_crtc *crtc)
10662 {
10663         struct drm_i915_private *dev_priv = dev->dev_private;
10664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10665         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10666         struct drm_display_mode *mode;
10667         struct intel_crtc_state pipe_config;
10668         int htot = I915_READ(HTOTAL(cpu_transcoder));
10669         int hsync = I915_READ(HSYNC(cpu_transcoder));
10670         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10671         int vsync = I915_READ(VSYNC(cpu_transcoder));
10672         enum pipe pipe = intel_crtc->pipe;
10673
10674         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10675         if (!mode)
10676                 return NULL;
10677
10678         /*
10679          * Construct a pipe_config sufficient for getting the clock info
10680          * back out of crtc_clock_get.
10681          *
10682          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10683          * to use a real value here instead.
10684          */
10685         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10686         pipe_config.pixel_multiplier = 1;
10687         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10688         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10689         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10690         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10691
10692         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10693         mode->hdisplay = (htot & 0xffff) + 1;
10694         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10695         mode->hsync_start = (hsync & 0xffff) + 1;
10696         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10697         mode->vdisplay = (vtot & 0xffff) + 1;
10698         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10699         mode->vsync_start = (vsync & 0xffff) + 1;
10700         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10701
10702         drm_mode_set_name(mode);
10703
10704         return mode;
10705 }
10706
10707 void intel_mark_busy(struct drm_device *dev)
10708 {
10709         struct drm_i915_private *dev_priv = dev->dev_private;
10710
10711         if (dev_priv->mm.busy)
10712                 return;
10713
10714         intel_runtime_pm_get(dev_priv);
10715         i915_update_gfx_val(dev_priv);
10716         if (INTEL_INFO(dev)->gen >= 6)
10717                 gen6_rps_busy(dev_priv);
10718         dev_priv->mm.busy = true;
10719 }
10720
10721 void intel_mark_idle(struct drm_device *dev)
10722 {
10723         struct drm_i915_private *dev_priv = dev->dev_private;
10724
10725         if (!dev_priv->mm.busy)
10726                 return;
10727
10728         dev_priv->mm.busy = false;
10729
10730         if (INTEL_INFO(dev)->gen >= 6)
10731                 gen6_rps_idle(dev->dev_private);
10732
10733         intel_runtime_pm_put(dev_priv);
10734 }
10735
10736 static void intel_crtc_destroy(struct drm_crtc *crtc)
10737 {
10738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10739         struct drm_device *dev = crtc->dev;
10740         struct intel_unpin_work *work;
10741
10742         spin_lock_irq(&dev->event_lock);
10743         work = intel_crtc->unpin_work;
10744         intel_crtc->unpin_work = NULL;
10745         spin_unlock_irq(&dev->event_lock);
10746
10747         if (work) {
10748                 cancel_work_sync(&work->work);
10749                 kfree(work);
10750         }
10751
10752         drm_crtc_cleanup(crtc);
10753
10754         kfree(intel_crtc);
10755 }
10756
10757 static void intel_unpin_work_fn(struct work_struct *__work)
10758 {
10759         struct intel_unpin_work *work =
10760                 container_of(__work, struct intel_unpin_work, work);
10761         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10762         struct drm_device *dev = crtc->base.dev;
10763         struct drm_plane *primary = crtc->base.primary;
10764
10765         mutex_lock(&dev->struct_mutex);
10766         intel_unpin_fb_obj(work->old_fb, primary->state);
10767         drm_gem_object_unreference(&work->pending_flip_obj->base);
10768
10769         if (work->flip_queued_req)
10770                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10771         mutex_unlock(&dev->struct_mutex);
10772
10773         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10774         drm_framebuffer_unreference(work->old_fb);
10775
10776         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10777         atomic_dec(&crtc->unpin_work_count);
10778
10779         kfree(work);
10780 }
10781
10782 static void do_intel_finish_page_flip(struct drm_device *dev,
10783                                       struct drm_crtc *crtc)
10784 {
10785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10786         struct intel_unpin_work *work;
10787         unsigned long flags;
10788
10789         /* Ignore early vblank irqs */
10790         if (intel_crtc == NULL)
10791                 return;
10792
10793         /*
10794          * This is called both by irq handlers and the reset code (to complete
10795          * lost pageflips) so needs the full irqsave spinlocks.
10796          */
10797         spin_lock_irqsave(&dev->event_lock, flags);
10798         work = intel_crtc->unpin_work;
10799
10800         /* Ensure we don't miss a work->pending update ... */
10801         smp_rmb();
10802
10803         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10804                 spin_unlock_irqrestore(&dev->event_lock, flags);
10805                 return;
10806         }
10807
10808         page_flip_completed(intel_crtc);
10809
10810         spin_unlock_irqrestore(&dev->event_lock, flags);
10811 }
10812
10813 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10814 {
10815         struct drm_i915_private *dev_priv = dev->dev_private;
10816         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10817
10818         do_intel_finish_page_flip(dev, crtc);
10819 }
10820
10821 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10822 {
10823         struct drm_i915_private *dev_priv = dev->dev_private;
10824         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10825
10826         do_intel_finish_page_flip(dev, crtc);
10827 }
10828
10829 /* Is 'a' after or equal to 'b'? */
10830 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10831 {
10832         return !((a - b) & 0x80000000);
10833 }
10834
10835 static bool page_flip_finished(struct intel_crtc *crtc)
10836 {
10837         struct drm_device *dev = crtc->base.dev;
10838         struct drm_i915_private *dev_priv = dev->dev_private;
10839
10840         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10841             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10842                 return true;
10843
10844         /*
10845          * The relevant registers doen't exist on pre-ctg.
10846          * As the flip done interrupt doesn't trigger for mmio
10847          * flips on gmch platforms, a flip count check isn't
10848          * really needed there. But since ctg has the registers,
10849          * include it in the check anyway.
10850          */
10851         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10852                 return true;
10853
10854         /*
10855          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10856          * used the same base address. In that case the mmio flip might
10857          * have completed, but the CS hasn't even executed the flip yet.
10858          *
10859          * A flip count check isn't enough as the CS might have updated
10860          * the base address just after start of vblank, but before we
10861          * managed to process the interrupt. This means we'd complete the
10862          * CS flip too soon.
10863          *
10864          * Combining both checks should get us a good enough result. It may
10865          * still happen that the CS flip has been executed, but has not
10866          * yet actually completed. But in case the base address is the same
10867          * anyway, we don't really care.
10868          */
10869         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10870                 crtc->unpin_work->gtt_offset &&
10871                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10872                                     crtc->unpin_work->flip_count);
10873 }
10874
10875 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10876 {
10877         struct drm_i915_private *dev_priv = dev->dev_private;
10878         struct intel_crtc *intel_crtc =
10879                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10880         unsigned long flags;
10881
10882
10883         /*
10884          * This is called both by irq handlers and the reset code (to complete
10885          * lost pageflips) so needs the full irqsave spinlocks.
10886          *
10887          * NB: An MMIO update of the plane base pointer will also
10888          * generate a page-flip completion irq, i.e. every modeset
10889          * is also accompanied by a spurious intel_prepare_page_flip().
10890          */
10891         spin_lock_irqsave(&dev->event_lock, flags);
10892         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10893                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10894         spin_unlock_irqrestore(&dev->event_lock, flags);
10895 }
10896
10897 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10898 {
10899         /* Ensure that the work item is consistent when activating it ... */
10900         smp_wmb();
10901         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10902         /* and that it is marked active as soon as the irq could fire. */
10903         smp_wmb();
10904 }
10905
10906 static int intel_gen2_queue_flip(struct drm_device *dev,
10907                                  struct drm_crtc *crtc,
10908                                  struct drm_framebuffer *fb,
10909                                  struct drm_i915_gem_object *obj,
10910                                  struct drm_i915_gem_request *req,
10911                                  uint32_t flags)
10912 {
10913         struct intel_engine_cs *ring = req->ring;
10914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10915         u32 flip_mask;
10916         int ret;
10917
10918         ret = intel_ring_begin(req, 6);
10919         if (ret)
10920                 return ret;
10921
10922         /* Can't queue multiple flips, so wait for the previous
10923          * one to finish before executing the next.
10924          */
10925         if (intel_crtc->plane)
10926                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10927         else
10928                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10929         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10930         intel_ring_emit(ring, MI_NOOP);
10931         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10932                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10933         intel_ring_emit(ring, fb->pitches[0]);
10934         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10935         intel_ring_emit(ring, 0); /* aux display base address, unused */
10936
10937         intel_mark_page_flip_active(intel_crtc);
10938         return 0;
10939 }
10940
10941 static int intel_gen3_queue_flip(struct drm_device *dev,
10942                                  struct drm_crtc *crtc,
10943                                  struct drm_framebuffer *fb,
10944                                  struct drm_i915_gem_object *obj,
10945                                  struct drm_i915_gem_request *req,
10946                                  uint32_t flags)
10947 {
10948         struct intel_engine_cs *ring = req->ring;
10949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10950         u32 flip_mask;
10951         int ret;
10952
10953         ret = intel_ring_begin(req, 6);
10954         if (ret)
10955                 return ret;
10956
10957         if (intel_crtc->plane)
10958                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10959         else
10960                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10961         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10962         intel_ring_emit(ring, MI_NOOP);
10963         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10964                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10965         intel_ring_emit(ring, fb->pitches[0]);
10966         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10967         intel_ring_emit(ring, MI_NOOP);
10968
10969         intel_mark_page_flip_active(intel_crtc);
10970         return 0;
10971 }
10972
10973 static int intel_gen4_queue_flip(struct drm_device *dev,
10974                                  struct drm_crtc *crtc,
10975                                  struct drm_framebuffer *fb,
10976                                  struct drm_i915_gem_object *obj,
10977                                  struct drm_i915_gem_request *req,
10978                                  uint32_t flags)
10979 {
10980         struct intel_engine_cs *ring = req->ring;
10981         struct drm_i915_private *dev_priv = dev->dev_private;
10982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10983         uint32_t pf, pipesrc;
10984         int ret;
10985
10986         ret = intel_ring_begin(req, 4);
10987         if (ret)
10988                 return ret;
10989
10990         /* i965+ uses the linear or tiled offsets from the
10991          * Display Registers (which do not change across a page-flip)
10992          * so we need only reprogram the base address.
10993          */
10994         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10995                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10996         intel_ring_emit(ring, fb->pitches[0]);
10997         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10998                         obj->tiling_mode);
10999
11000         /* XXX Enabling the panel-fitter across page-flip is so far
11001          * untested on non-native modes, so ignore it for now.
11002          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11003          */
11004         pf = 0;
11005         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11006         intel_ring_emit(ring, pf | pipesrc);
11007
11008         intel_mark_page_flip_active(intel_crtc);
11009         return 0;
11010 }
11011
11012 static int intel_gen6_queue_flip(struct drm_device *dev,
11013                                  struct drm_crtc *crtc,
11014                                  struct drm_framebuffer *fb,
11015                                  struct drm_i915_gem_object *obj,
11016                                  struct drm_i915_gem_request *req,
11017                                  uint32_t flags)
11018 {
11019         struct intel_engine_cs *ring = req->ring;
11020         struct drm_i915_private *dev_priv = dev->dev_private;
11021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11022         uint32_t pf, pipesrc;
11023         int ret;
11024
11025         ret = intel_ring_begin(req, 4);
11026         if (ret)
11027                 return ret;
11028
11029         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11030                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11031         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11032         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11033
11034         /* Contrary to the suggestions in the documentation,
11035          * "Enable Panel Fitter" does not seem to be required when page
11036          * flipping with a non-native mode, and worse causes a normal
11037          * modeset to fail.
11038          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11039          */
11040         pf = 0;
11041         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11042         intel_ring_emit(ring, pf | pipesrc);
11043
11044         intel_mark_page_flip_active(intel_crtc);
11045         return 0;
11046 }
11047
11048 static int intel_gen7_queue_flip(struct drm_device *dev,
11049                                  struct drm_crtc *crtc,
11050                                  struct drm_framebuffer *fb,
11051                                  struct drm_i915_gem_object *obj,
11052                                  struct drm_i915_gem_request *req,
11053                                  uint32_t flags)
11054 {
11055         struct intel_engine_cs *ring = req->ring;
11056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11057         uint32_t plane_bit = 0;
11058         int len, ret;
11059
11060         switch (intel_crtc->plane) {
11061         case PLANE_A:
11062                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11063                 break;
11064         case PLANE_B:
11065                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11066                 break;
11067         case PLANE_C:
11068                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11069                 break;
11070         default:
11071                 WARN_ONCE(1, "unknown plane in flip command\n");
11072                 return -ENODEV;
11073         }
11074
11075         len = 4;
11076         if (ring->id == RCS) {
11077                 len += 6;
11078                 /*
11079                  * On Gen 8, SRM is now taking an extra dword to accommodate
11080                  * 48bits addresses, and we need a NOOP for the batch size to
11081                  * stay even.
11082                  */
11083                 if (IS_GEN8(dev))
11084                         len += 2;
11085         }
11086
11087         /*
11088          * BSpec MI_DISPLAY_FLIP for IVB:
11089          * "The full packet must be contained within the same cache line."
11090          *
11091          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11092          * cacheline, if we ever start emitting more commands before
11093          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11094          * then do the cacheline alignment, and finally emit the
11095          * MI_DISPLAY_FLIP.
11096          */
11097         ret = intel_ring_cacheline_align(req);
11098         if (ret)
11099                 return ret;
11100
11101         ret = intel_ring_begin(req, len);
11102         if (ret)
11103                 return ret;
11104
11105         /* Unmask the flip-done completion message. Note that the bspec says that
11106          * we should do this for both the BCS and RCS, and that we must not unmask
11107          * more than one flip event at any time (or ensure that one flip message
11108          * can be sent by waiting for flip-done prior to queueing new flips).
11109          * Experimentation says that BCS works despite DERRMR masking all
11110          * flip-done completion events and that unmasking all planes at once
11111          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11112          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11113          */
11114         if (ring->id == RCS) {
11115                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11116                 intel_ring_emit(ring, DERRMR);
11117                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11118                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11119                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11120                 if (IS_GEN8(dev))
11121                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11122                                               MI_SRM_LRM_GLOBAL_GTT);
11123                 else
11124                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11125                                               MI_SRM_LRM_GLOBAL_GTT);
11126                 intel_ring_emit(ring, DERRMR);
11127                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11128                 if (IS_GEN8(dev)) {
11129                         intel_ring_emit(ring, 0);
11130                         intel_ring_emit(ring, MI_NOOP);
11131                 }
11132         }
11133
11134         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11135         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11136         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11137         intel_ring_emit(ring, (MI_NOOP));
11138
11139         intel_mark_page_flip_active(intel_crtc);
11140         return 0;
11141 }
11142
11143 static bool use_mmio_flip(struct intel_engine_cs *ring,
11144                           struct drm_i915_gem_object *obj)
11145 {
11146         /*
11147          * This is not being used for older platforms, because
11148          * non-availability of flip done interrupt forces us to use
11149          * CS flips. Older platforms derive flip done using some clever
11150          * tricks involving the flip_pending status bits and vblank irqs.
11151          * So using MMIO flips there would disrupt this mechanism.
11152          */
11153
11154         if (ring == NULL)
11155                 return true;
11156
11157         if (INTEL_INFO(ring->dev)->gen < 5)
11158                 return false;
11159
11160         if (i915.use_mmio_flip < 0)
11161                 return false;
11162         else if (i915.use_mmio_flip > 0)
11163                 return true;
11164         else if (i915.enable_execlists)
11165                 return true;
11166         else
11167                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11168 }
11169
11170 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11171 {
11172         struct drm_device *dev = intel_crtc->base.dev;
11173         struct drm_i915_private *dev_priv = dev->dev_private;
11174         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11175         const enum pipe pipe = intel_crtc->pipe;
11176         u32 ctl, stride;
11177
11178         ctl = I915_READ(PLANE_CTL(pipe, 0));
11179         ctl &= ~PLANE_CTL_TILED_MASK;
11180         switch (fb->modifier[0]) {
11181         case DRM_FORMAT_MOD_NONE:
11182                 break;
11183         case I915_FORMAT_MOD_X_TILED:
11184                 ctl |= PLANE_CTL_TILED_X;
11185                 break;
11186         case I915_FORMAT_MOD_Y_TILED:
11187                 ctl |= PLANE_CTL_TILED_Y;
11188                 break;
11189         case I915_FORMAT_MOD_Yf_TILED:
11190                 ctl |= PLANE_CTL_TILED_YF;
11191                 break;
11192         default:
11193                 MISSING_CASE(fb->modifier[0]);
11194         }
11195
11196         /*
11197          * The stride is either expressed as a multiple of 64 bytes chunks for
11198          * linear buffers or in number of tiles for tiled buffers.
11199          */
11200         stride = fb->pitches[0] /
11201                  intel_fb_stride_alignment(dev, fb->modifier[0],
11202                                            fb->pixel_format);
11203
11204         /*
11205          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11206          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11207          */
11208         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11209         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11210
11211         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11212         POSTING_READ(PLANE_SURF(pipe, 0));
11213 }
11214
11215 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11216 {
11217         struct drm_device *dev = intel_crtc->base.dev;
11218         struct drm_i915_private *dev_priv = dev->dev_private;
11219         struct intel_framebuffer *intel_fb =
11220                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11221         struct drm_i915_gem_object *obj = intel_fb->obj;
11222         u32 dspcntr;
11223         u32 reg;
11224
11225         reg = DSPCNTR(intel_crtc->plane);
11226         dspcntr = I915_READ(reg);
11227
11228         if (obj->tiling_mode != I915_TILING_NONE)
11229                 dspcntr |= DISPPLANE_TILED;
11230         else
11231                 dspcntr &= ~DISPPLANE_TILED;
11232
11233         I915_WRITE(reg, dspcntr);
11234
11235         I915_WRITE(DSPSURF(intel_crtc->plane),
11236                    intel_crtc->unpin_work->gtt_offset);
11237         POSTING_READ(DSPSURF(intel_crtc->plane));
11238
11239 }
11240
11241 /*
11242  * XXX: This is the temporary way to update the plane registers until we get
11243  * around to using the usual plane update functions for MMIO flips
11244  */
11245 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11246 {
11247         struct drm_device *dev = intel_crtc->base.dev;
11248         u32 start_vbl_count;
11249
11250         intel_mark_page_flip_active(intel_crtc);
11251
11252         intel_pipe_update_start(intel_crtc, &start_vbl_count);
11253
11254         if (INTEL_INFO(dev)->gen >= 9)
11255                 skl_do_mmio_flip(intel_crtc);
11256         else
11257                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11258                 ilk_do_mmio_flip(intel_crtc);
11259
11260         intel_pipe_update_end(intel_crtc, start_vbl_count);
11261 }
11262
11263 static void intel_mmio_flip_work_func(struct work_struct *work)
11264 {
11265         struct intel_mmio_flip *mmio_flip =
11266                 container_of(work, struct intel_mmio_flip, work);
11267
11268         if (mmio_flip->req)
11269                 WARN_ON(__i915_wait_request(mmio_flip->req,
11270                                             mmio_flip->crtc->reset_counter,
11271                                             false, NULL,
11272                                             &mmio_flip->i915->rps.mmioflips));
11273
11274         intel_do_mmio_flip(mmio_flip->crtc);
11275
11276         i915_gem_request_unreference__unlocked(mmio_flip->req);
11277         kfree(mmio_flip);
11278 }
11279
11280 static int intel_queue_mmio_flip(struct drm_device *dev,
11281                                  struct drm_crtc *crtc,
11282                                  struct drm_framebuffer *fb,
11283                                  struct drm_i915_gem_object *obj,
11284                                  struct intel_engine_cs *ring,
11285                                  uint32_t flags)
11286 {
11287         struct intel_mmio_flip *mmio_flip;
11288
11289         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11290         if (mmio_flip == NULL)
11291                 return -ENOMEM;
11292
11293         mmio_flip->i915 = to_i915(dev);
11294         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11295         mmio_flip->crtc = to_intel_crtc(crtc);
11296
11297         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11298         schedule_work(&mmio_flip->work);
11299
11300         return 0;
11301 }
11302
11303 static int intel_default_queue_flip(struct drm_device *dev,
11304                                     struct drm_crtc *crtc,
11305                                     struct drm_framebuffer *fb,
11306                                     struct drm_i915_gem_object *obj,
11307                                     struct drm_i915_gem_request *req,
11308                                     uint32_t flags)
11309 {
11310         return -ENODEV;
11311 }
11312
11313 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11314                                          struct drm_crtc *crtc)
11315 {
11316         struct drm_i915_private *dev_priv = dev->dev_private;
11317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11318         struct intel_unpin_work *work = intel_crtc->unpin_work;
11319         u32 addr;
11320
11321         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11322                 return true;
11323
11324         if (!work->enable_stall_check)
11325                 return false;
11326
11327         if (work->flip_ready_vblank == 0) {
11328                 if (work->flip_queued_req &&
11329                     !i915_gem_request_completed(work->flip_queued_req, true))
11330                         return false;
11331
11332                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11333         }
11334
11335         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11336                 return false;
11337
11338         /* Potential stall - if we see that the flip has happened,
11339          * assume a missed interrupt. */
11340         if (INTEL_INFO(dev)->gen >= 4)
11341                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11342         else
11343                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11344
11345         /* There is a potential issue here with a false positive after a flip
11346          * to the same address. We could address this by checking for a
11347          * non-incrementing frame counter.
11348          */
11349         return addr == work->gtt_offset;
11350 }
11351
11352 void intel_check_page_flip(struct drm_device *dev, int pipe)
11353 {
11354         struct drm_i915_private *dev_priv = dev->dev_private;
11355         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11357         struct intel_unpin_work *work;
11358
11359         WARN_ON(!in_interrupt());
11360
11361         if (crtc == NULL)
11362                 return;
11363
11364         spin_lock(&dev->event_lock);
11365         work = intel_crtc->unpin_work;
11366         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11367                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11368                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11369                 page_flip_completed(intel_crtc);
11370                 work = NULL;
11371         }
11372         if (work != NULL &&
11373             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11374                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11375         spin_unlock(&dev->event_lock);
11376 }
11377
11378 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11379                                 struct drm_framebuffer *fb,
11380                                 struct drm_pending_vblank_event *event,
11381                                 uint32_t page_flip_flags)
11382 {
11383         struct drm_device *dev = crtc->dev;
11384         struct drm_i915_private *dev_priv = dev->dev_private;
11385         struct drm_framebuffer *old_fb = crtc->primary->fb;
11386         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11388         struct drm_plane *primary = crtc->primary;
11389         enum pipe pipe = intel_crtc->pipe;
11390         struct intel_unpin_work *work;
11391         struct intel_engine_cs *ring;
11392         bool mmio_flip;
11393         struct drm_i915_gem_request *request = NULL;
11394         int ret;
11395
11396         /*
11397          * drm_mode_page_flip_ioctl() should already catch this, but double
11398          * check to be safe.  In the future we may enable pageflipping from
11399          * a disabled primary plane.
11400          */
11401         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11402                 return -EBUSY;
11403
11404         /* Can't change pixel format via MI display flips. */
11405         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11406                 return -EINVAL;
11407
11408         /*
11409          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11410          * Note that pitch changes could also affect these register.
11411          */
11412         if (INTEL_INFO(dev)->gen > 3 &&
11413             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11414              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11415                 return -EINVAL;
11416
11417         if (i915_terminally_wedged(&dev_priv->gpu_error))
11418                 goto out_hang;
11419
11420         work = kzalloc(sizeof(*work), GFP_KERNEL);
11421         if (work == NULL)
11422                 return -ENOMEM;
11423
11424         work->event = event;
11425         work->crtc = crtc;
11426         work->old_fb = old_fb;
11427         INIT_WORK(&work->work, intel_unpin_work_fn);
11428
11429         ret = drm_crtc_vblank_get(crtc);
11430         if (ret)
11431                 goto free_work;
11432
11433         /* We borrow the event spin lock for protecting unpin_work */
11434         spin_lock_irq(&dev->event_lock);
11435         if (intel_crtc->unpin_work) {
11436                 /* Before declaring the flip queue wedged, check if
11437                  * the hardware completed the operation behind our backs.
11438                  */
11439                 if (__intel_pageflip_stall_check(dev, crtc)) {
11440                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11441                         page_flip_completed(intel_crtc);
11442                 } else {
11443                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11444                         spin_unlock_irq(&dev->event_lock);
11445
11446                         drm_crtc_vblank_put(crtc);
11447                         kfree(work);
11448                         return -EBUSY;
11449                 }
11450         }
11451         intel_crtc->unpin_work = work;
11452         spin_unlock_irq(&dev->event_lock);
11453
11454         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11455                 flush_workqueue(dev_priv->wq);
11456
11457         /* Reference the objects for the scheduled work. */
11458         drm_framebuffer_reference(work->old_fb);
11459         drm_gem_object_reference(&obj->base);
11460
11461         crtc->primary->fb = fb;
11462         update_state_fb(crtc->primary);
11463
11464         work->pending_flip_obj = obj;
11465
11466         ret = i915_mutex_lock_interruptible(dev);
11467         if (ret)
11468                 goto cleanup;
11469
11470         atomic_inc(&intel_crtc->unpin_work_count);
11471         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11472
11473         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11474                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11475
11476         if (IS_VALLEYVIEW(dev)) {
11477                 ring = &dev_priv->ring[BCS];
11478                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11479                         /* vlv: DISPLAY_FLIP fails to change tiling */
11480                         ring = NULL;
11481         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11482                 ring = &dev_priv->ring[BCS];
11483         } else if (INTEL_INFO(dev)->gen >= 7) {
11484                 ring = i915_gem_request_get_ring(obj->last_write_req);
11485                 if (ring == NULL || ring->id != RCS)
11486                         ring = &dev_priv->ring[BCS];
11487         } else {
11488                 ring = &dev_priv->ring[RCS];
11489         }
11490
11491         mmio_flip = use_mmio_flip(ring, obj);
11492
11493         /* When using CS flips, we want to emit semaphores between rings.
11494          * However, when using mmio flips we will create a task to do the
11495          * synchronisation, so all we want here is to pin the framebuffer
11496          * into the display plane and skip any waits.
11497          */
11498         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11499                                          crtc->primary->state,
11500                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11501         if (ret)
11502                 goto cleanup_pending;
11503
11504         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11505                                                   + intel_crtc->dspaddr_offset;
11506
11507         if (mmio_flip) {
11508                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11509                                             page_flip_flags);
11510                 if (ret)
11511                         goto cleanup_unpin;
11512
11513                 i915_gem_request_assign(&work->flip_queued_req,
11514                                         obj->last_write_req);
11515         } else {
11516                 if (!request) {
11517                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11518                         if (ret)
11519                                 goto cleanup_unpin;
11520                 }
11521
11522                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11523                                                    page_flip_flags);
11524                 if (ret)
11525                         goto cleanup_unpin;
11526
11527                 i915_gem_request_assign(&work->flip_queued_req, request);
11528         }
11529
11530         if (request)
11531                 i915_add_request_no_flush(request);
11532
11533         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11534         work->enable_stall_check = true;
11535
11536         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11537                           to_intel_plane(primary)->frontbuffer_bit);
11538         mutex_unlock(&dev->struct_mutex);
11539
11540         intel_fbc_disable_crtc(intel_crtc);
11541         intel_frontbuffer_flip_prepare(dev,
11542                                        to_intel_plane(primary)->frontbuffer_bit);
11543
11544         trace_i915_flip_request(intel_crtc->plane, obj);
11545
11546         return 0;
11547
11548 cleanup_unpin:
11549         intel_unpin_fb_obj(fb, crtc->primary->state);
11550 cleanup_pending:
11551         if (request)
11552                 i915_gem_request_cancel(request);
11553         atomic_dec(&intel_crtc->unpin_work_count);
11554         mutex_unlock(&dev->struct_mutex);
11555 cleanup:
11556         crtc->primary->fb = old_fb;
11557         update_state_fb(crtc->primary);
11558
11559         drm_gem_object_unreference_unlocked(&obj->base);
11560         drm_framebuffer_unreference(work->old_fb);
11561
11562         spin_lock_irq(&dev->event_lock);
11563         intel_crtc->unpin_work = NULL;
11564         spin_unlock_irq(&dev->event_lock);
11565
11566         drm_crtc_vblank_put(crtc);
11567 free_work:
11568         kfree(work);
11569
11570         if (ret == -EIO) {
11571                 struct drm_atomic_state *state;
11572                 struct drm_plane_state *plane_state;
11573
11574 out_hang:
11575                 state = drm_atomic_state_alloc(dev);
11576                 if (!state)
11577                         return -ENOMEM;
11578                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11579
11580 retry:
11581                 plane_state = drm_atomic_get_plane_state(state, primary);
11582                 ret = PTR_ERR_OR_ZERO(plane_state);
11583                 if (!ret) {
11584                         drm_atomic_set_fb_for_plane(plane_state, fb);
11585
11586                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11587                         if (!ret)
11588                                 ret = drm_atomic_commit(state);
11589                 }
11590
11591                 if (ret == -EDEADLK) {
11592                         drm_modeset_backoff(state->acquire_ctx);
11593                         drm_atomic_state_clear(state);
11594                         goto retry;
11595                 }
11596
11597                 if (ret)
11598                         drm_atomic_state_free(state);
11599
11600                 if (ret == 0 && event) {
11601                         spin_lock_irq(&dev->event_lock);
11602                         drm_send_vblank_event(dev, pipe, event);
11603                         spin_unlock_irq(&dev->event_lock);
11604                 }
11605         }
11606         return ret;
11607 }
11608
11609
11610 /**
11611  * intel_wm_need_update - Check whether watermarks need updating
11612  * @plane: drm plane
11613  * @state: new plane state
11614  *
11615  * Check current plane state versus the new one to determine whether
11616  * watermarks need to be recalculated.
11617  *
11618  * Returns true or false.
11619  */
11620 static bool intel_wm_need_update(struct drm_plane *plane,
11621                                  struct drm_plane_state *state)
11622 {
11623         /* Update watermarks on tiling changes. */
11624         if (!plane->state->fb || !state->fb ||
11625             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11626             plane->state->rotation != state->rotation)
11627                 return true;
11628
11629         if (plane->state->crtc_w != state->crtc_w)
11630                 return true;
11631
11632         return false;
11633 }
11634
11635 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11636                                     struct drm_plane_state *plane_state)
11637 {
11638         struct drm_crtc *crtc = crtc_state->crtc;
11639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11640         struct drm_plane *plane = plane_state->plane;
11641         struct drm_device *dev = crtc->dev;
11642         struct drm_i915_private *dev_priv = dev->dev_private;
11643         struct intel_plane_state *old_plane_state =
11644                 to_intel_plane_state(plane->state);
11645         int idx = intel_crtc->base.base.id, ret;
11646         int i = drm_plane_index(plane);
11647         bool mode_changed = needs_modeset(crtc_state);
11648         bool was_crtc_enabled = crtc->state->active;
11649         bool is_crtc_enabled = crtc_state->active;
11650
11651         bool turn_off, turn_on, visible, was_visible;
11652         struct drm_framebuffer *fb = plane_state->fb;
11653
11654         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11655             plane->type != DRM_PLANE_TYPE_CURSOR) {
11656                 ret = skl_update_scaler_plane(
11657                         to_intel_crtc_state(crtc_state),
11658                         to_intel_plane_state(plane_state));
11659                 if (ret)
11660                         return ret;
11661         }
11662
11663         /*
11664          * Disabling a plane is always okay; we just need to update
11665          * fb tracking in a special way since cleanup_fb() won't
11666          * get called by the plane helpers.
11667          */
11668         if (old_plane_state->base.fb && !fb)
11669                 intel_crtc->atomic.disabled_planes |= 1 << i;
11670
11671         was_visible = old_plane_state->visible;
11672         visible = to_intel_plane_state(plane_state)->visible;
11673
11674         if (!was_crtc_enabled && WARN_ON(was_visible))
11675                 was_visible = false;
11676
11677         if (!is_crtc_enabled && WARN_ON(visible))
11678                 visible = false;
11679
11680         if (!was_visible && !visible)
11681                 return 0;
11682
11683         turn_off = was_visible && (!visible || mode_changed);
11684         turn_on = visible && (!was_visible || mode_changed);
11685
11686         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11687                          plane->base.id, fb ? fb->base.id : -1);
11688
11689         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11690                          plane->base.id, was_visible, visible,
11691                          turn_off, turn_on, mode_changed);
11692
11693         if (turn_on) {
11694                 intel_crtc->atomic.update_wm_pre = true;
11695                 /* must disable cxsr around plane enable/disable */
11696                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11697                         intel_crtc->atomic.disable_cxsr = true;
11698                         /* to potentially re-enable cxsr */
11699                         intel_crtc->atomic.wait_vblank = true;
11700                         intel_crtc->atomic.update_wm_post = true;
11701                 }
11702         } else if (turn_off) {
11703                 intel_crtc->atomic.update_wm_post = true;
11704                 /* must disable cxsr around plane enable/disable */
11705                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11706                         if (is_crtc_enabled)
11707                                 intel_crtc->atomic.wait_vblank = true;
11708                         intel_crtc->atomic.disable_cxsr = true;
11709                 }
11710         } else if (intel_wm_need_update(plane, plane_state)) {
11711                 intel_crtc->atomic.update_wm_pre = true;
11712         }
11713
11714         if (visible)
11715                 intel_crtc->atomic.fb_bits |=
11716                         to_intel_plane(plane)->frontbuffer_bit;
11717
11718         switch (plane->type) {
11719         case DRM_PLANE_TYPE_PRIMARY:
11720                 intel_crtc->atomic.wait_for_flips = true;
11721                 intel_crtc->atomic.pre_disable_primary = turn_off;
11722                 intel_crtc->atomic.post_enable_primary = turn_on;
11723
11724                 if (turn_off) {
11725                         /*
11726                          * FIXME: Actually if we will still have any other
11727                          * plane enabled on the pipe we could let IPS enabled
11728                          * still, but for now lets consider that when we make
11729                          * primary invisible by setting DSPCNTR to 0 on
11730                          * update_primary_plane function IPS needs to be
11731                          * disable.
11732                          */
11733                         intel_crtc->atomic.disable_ips = true;
11734
11735                         intel_crtc->atomic.disable_fbc = true;
11736                 }
11737
11738                 /*
11739                  * FBC does not work on some platforms for rotated
11740                  * planes, so disable it when rotation is not 0 and
11741                  * update it when rotation is set back to 0.
11742                  *
11743                  * FIXME: This is redundant with the fbc update done in
11744                  * the primary plane enable function except that that
11745                  * one is done too late. We eventually need to unify
11746                  * this.
11747                  */
11748
11749                 if (visible &&
11750                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11751                     dev_priv->fbc.crtc == intel_crtc &&
11752                     plane_state->rotation != BIT(DRM_ROTATE_0))
11753                         intel_crtc->atomic.disable_fbc = true;
11754
11755                 /*
11756                  * BDW signals flip done immediately if the plane
11757                  * is disabled, even if the plane enable is already
11758                  * armed to occur at the next vblank :(
11759                  */
11760                 if (turn_on && IS_BROADWELL(dev))
11761                         intel_crtc->atomic.wait_vblank = true;
11762
11763                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11764                 break;
11765         case DRM_PLANE_TYPE_CURSOR:
11766                 break;
11767         case DRM_PLANE_TYPE_OVERLAY:
11768                 if (turn_off && !mode_changed) {
11769                         intel_crtc->atomic.wait_vblank = true;
11770                         intel_crtc->atomic.update_sprite_watermarks |=
11771                                 1 << i;
11772                 }
11773         }
11774         return 0;
11775 }
11776
11777 static bool encoders_cloneable(const struct intel_encoder *a,
11778                                const struct intel_encoder *b)
11779 {
11780         /* masks could be asymmetric, so check both ways */
11781         return a == b || (a->cloneable & (1 << b->type) &&
11782                           b->cloneable & (1 << a->type));
11783 }
11784
11785 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11786                                          struct intel_crtc *crtc,
11787                                          struct intel_encoder *encoder)
11788 {
11789         struct intel_encoder *source_encoder;
11790         struct drm_connector *connector;
11791         struct drm_connector_state *connector_state;
11792         int i;
11793
11794         for_each_connector_in_state(state, connector, connector_state, i) {
11795                 if (connector_state->crtc != &crtc->base)
11796                         continue;
11797
11798                 source_encoder =
11799                         to_intel_encoder(connector_state->best_encoder);
11800                 if (!encoders_cloneable(encoder, source_encoder))
11801                         return false;
11802         }
11803
11804         return true;
11805 }
11806
11807 static bool check_encoder_cloning(struct drm_atomic_state *state,
11808                                   struct intel_crtc *crtc)
11809 {
11810         struct intel_encoder *encoder;
11811         struct drm_connector *connector;
11812         struct drm_connector_state *connector_state;
11813         int i;
11814
11815         for_each_connector_in_state(state, connector, connector_state, i) {
11816                 if (connector_state->crtc != &crtc->base)
11817                         continue;
11818
11819                 encoder = to_intel_encoder(connector_state->best_encoder);
11820                 if (!check_single_encoder_cloning(state, crtc, encoder))
11821                         return false;
11822         }
11823
11824         return true;
11825 }
11826
11827 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11828                                    struct drm_crtc_state *crtc_state)
11829 {
11830         struct drm_device *dev = crtc->dev;
11831         struct drm_i915_private *dev_priv = dev->dev_private;
11832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11833         struct intel_crtc_state *pipe_config =
11834                 to_intel_crtc_state(crtc_state);
11835         struct drm_atomic_state *state = crtc_state->state;
11836         int ret, idx = crtc->base.id;
11837         bool mode_changed = needs_modeset(crtc_state);
11838
11839         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11840                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11841                 return -EINVAL;
11842         }
11843
11844         I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11845                 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11846                 idx, crtc->state->active, intel_crtc->active);
11847
11848         if (mode_changed && !crtc_state->active)
11849                 intel_crtc->atomic.update_wm_post = true;
11850
11851         if (mode_changed && crtc_state->enable &&
11852             dev_priv->display.crtc_compute_clock &&
11853             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11854                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11855                                                            pipe_config);
11856                 if (ret)
11857                         return ret;
11858         }
11859
11860         ret = 0;
11861         if (INTEL_INFO(dev)->gen >= 9) {
11862                 if (mode_changed)
11863                         ret = skl_update_scaler_crtc(pipe_config);
11864
11865                 if (!ret)
11866                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11867                                                          pipe_config);
11868         }
11869
11870         return ret;
11871 }
11872
11873 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11874         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11875         .load_lut = intel_crtc_load_lut,
11876         .atomic_begin = intel_begin_crtc_commit,
11877         .atomic_flush = intel_finish_crtc_commit,
11878         .atomic_check = intel_crtc_atomic_check,
11879 };
11880
11881 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11882 {
11883         struct intel_connector *connector;
11884
11885         for_each_intel_connector(dev, connector) {
11886                 if (connector->base.encoder) {
11887                         connector->base.state->best_encoder =
11888                                 connector->base.encoder;
11889                         connector->base.state->crtc =
11890                                 connector->base.encoder->crtc;
11891                 } else {
11892                         connector->base.state->best_encoder = NULL;
11893                         connector->base.state->crtc = NULL;
11894                 }
11895         }
11896 }
11897
11898 static void
11899 connected_sink_compute_bpp(struct intel_connector *connector,
11900                            struct intel_crtc_state *pipe_config)
11901 {
11902         int bpp = pipe_config->pipe_bpp;
11903
11904         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11905                 connector->base.base.id,
11906                 connector->base.name);
11907
11908         /* Don't use an invalid EDID bpc value */
11909         if (connector->base.display_info.bpc &&
11910             connector->base.display_info.bpc * 3 < bpp) {
11911                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11912                               bpp, connector->base.display_info.bpc*3);
11913                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11914         }
11915
11916         /* Clamp bpp to 8 on screens without EDID 1.4 */
11917         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11918                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11919                               bpp);
11920                 pipe_config->pipe_bpp = 24;
11921         }
11922 }
11923
11924 static int
11925 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11926                           struct intel_crtc_state *pipe_config)
11927 {
11928         struct drm_device *dev = crtc->base.dev;
11929         struct drm_atomic_state *state;
11930         struct drm_connector *connector;
11931         struct drm_connector_state *connector_state;
11932         int bpp, i;
11933
11934         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11935                 bpp = 10*3;
11936         else if (INTEL_INFO(dev)->gen >= 5)
11937                 bpp = 12*3;
11938         else
11939                 bpp = 8*3;
11940
11941
11942         pipe_config->pipe_bpp = bpp;
11943
11944         state = pipe_config->base.state;
11945
11946         /* Clamp display bpp to EDID value */
11947         for_each_connector_in_state(state, connector, connector_state, i) {
11948                 if (connector_state->crtc != &crtc->base)
11949                         continue;
11950
11951                 connected_sink_compute_bpp(to_intel_connector(connector),
11952                                            pipe_config);
11953         }
11954
11955         return bpp;
11956 }
11957
11958 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11959 {
11960         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11961                         "type: 0x%x flags: 0x%x\n",
11962                 mode->crtc_clock,
11963                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11964                 mode->crtc_hsync_end, mode->crtc_htotal,
11965                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11966                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11967 }
11968
11969 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11970                                    struct intel_crtc_state *pipe_config,
11971                                    const char *context)
11972 {
11973         struct drm_device *dev = crtc->base.dev;
11974         struct drm_plane *plane;
11975         struct intel_plane *intel_plane;
11976         struct intel_plane_state *state;
11977         struct drm_framebuffer *fb;
11978
11979         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11980                       context, pipe_config, pipe_name(crtc->pipe));
11981
11982         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11983         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11984                       pipe_config->pipe_bpp, pipe_config->dither);
11985         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11986                       pipe_config->has_pch_encoder,
11987                       pipe_config->fdi_lanes,
11988                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11989                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11990                       pipe_config->fdi_m_n.tu);
11991         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11992                       pipe_config->has_dp_encoder,
11993                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11994                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11995                       pipe_config->dp_m_n.tu);
11996
11997         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11998                       pipe_config->has_dp_encoder,
11999                       pipe_config->dp_m2_n2.gmch_m,
12000                       pipe_config->dp_m2_n2.gmch_n,
12001                       pipe_config->dp_m2_n2.link_m,
12002                       pipe_config->dp_m2_n2.link_n,
12003                       pipe_config->dp_m2_n2.tu);
12004
12005         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12006                       pipe_config->has_audio,
12007                       pipe_config->has_infoframe);
12008
12009         DRM_DEBUG_KMS("requested mode:\n");
12010         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12011         DRM_DEBUG_KMS("adjusted mode:\n");
12012         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12013         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12014         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12015         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12016                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12017         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12018                       crtc->num_scalers,
12019                       pipe_config->scaler_state.scaler_users,
12020                       pipe_config->scaler_state.scaler_id);
12021         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12022                       pipe_config->gmch_pfit.control,
12023                       pipe_config->gmch_pfit.pgm_ratios,
12024                       pipe_config->gmch_pfit.lvds_border_bits);
12025         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12026                       pipe_config->pch_pfit.pos,
12027                       pipe_config->pch_pfit.size,
12028                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12029         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12030         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12031
12032         if (IS_BROXTON(dev)) {
12033                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12034                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12035                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12036                               pipe_config->ddi_pll_sel,
12037                               pipe_config->dpll_hw_state.ebb0,
12038                               pipe_config->dpll_hw_state.ebb4,
12039                               pipe_config->dpll_hw_state.pll0,
12040                               pipe_config->dpll_hw_state.pll1,
12041                               pipe_config->dpll_hw_state.pll2,
12042                               pipe_config->dpll_hw_state.pll3,
12043                               pipe_config->dpll_hw_state.pll6,
12044                               pipe_config->dpll_hw_state.pll8,
12045                               pipe_config->dpll_hw_state.pll9,
12046                               pipe_config->dpll_hw_state.pll10,
12047                               pipe_config->dpll_hw_state.pcsdw12);
12048         } else if (IS_SKYLAKE(dev)) {
12049                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12050                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12051                               pipe_config->ddi_pll_sel,
12052                               pipe_config->dpll_hw_state.ctrl1,
12053                               pipe_config->dpll_hw_state.cfgcr1,
12054                               pipe_config->dpll_hw_state.cfgcr2);
12055         } else if (HAS_DDI(dev)) {
12056                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12057                               pipe_config->ddi_pll_sel,
12058                               pipe_config->dpll_hw_state.wrpll);
12059         } else {
12060                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12061                               "fp0: 0x%x, fp1: 0x%x\n",
12062                               pipe_config->dpll_hw_state.dpll,
12063                               pipe_config->dpll_hw_state.dpll_md,
12064                               pipe_config->dpll_hw_state.fp0,
12065                               pipe_config->dpll_hw_state.fp1);
12066         }
12067
12068         DRM_DEBUG_KMS("planes on this crtc\n");
12069         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12070                 intel_plane = to_intel_plane(plane);
12071                 if (intel_plane->pipe != crtc->pipe)
12072                         continue;
12073
12074                 state = to_intel_plane_state(plane->state);
12075                 fb = state->base.fb;
12076                 if (!fb) {
12077                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12078                                 "disabled, scaler_id = %d\n",
12079                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12080                                 plane->base.id, intel_plane->pipe,
12081                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12082                                 drm_plane_index(plane), state->scaler_id);
12083                         continue;
12084                 }
12085
12086                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12087                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12088                         plane->base.id, intel_plane->pipe,
12089                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12090                         drm_plane_index(plane));
12091                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12092                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12093                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12094                         state->scaler_id,
12095                         state->src.x1 >> 16, state->src.y1 >> 16,
12096                         drm_rect_width(&state->src) >> 16,
12097                         drm_rect_height(&state->src) >> 16,
12098                         state->dst.x1, state->dst.y1,
12099                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12100         }
12101 }
12102
12103 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12104 {
12105         struct drm_device *dev = state->dev;
12106         struct intel_encoder *encoder;
12107         struct drm_connector *connector;
12108         struct drm_connector_state *connector_state;
12109         unsigned int used_ports = 0;
12110         int i;
12111
12112         /*
12113          * Walk the connector list instead of the encoder
12114          * list to detect the problem on ddi platforms
12115          * where there's just one encoder per digital port.
12116          */
12117         for_each_connector_in_state(state, connector, connector_state, i) {
12118                 if (!connector_state->best_encoder)
12119                         continue;
12120
12121                 encoder = to_intel_encoder(connector_state->best_encoder);
12122
12123                 WARN_ON(!connector_state->crtc);
12124
12125                 switch (encoder->type) {
12126                         unsigned int port_mask;
12127                 case INTEL_OUTPUT_UNKNOWN:
12128                         if (WARN_ON(!HAS_DDI(dev)))
12129                                 break;
12130                 case INTEL_OUTPUT_DISPLAYPORT:
12131                 case INTEL_OUTPUT_HDMI:
12132                 case INTEL_OUTPUT_EDP:
12133                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12134
12135                         /* the same port mustn't appear more than once */
12136                         if (used_ports & port_mask)
12137                                 return false;
12138
12139                         used_ports |= port_mask;
12140                 default:
12141                         break;
12142                 }
12143         }
12144
12145         return true;
12146 }
12147
12148 static void
12149 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12150 {
12151         struct drm_crtc_state tmp_state;
12152         struct intel_crtc_scaler_state scaler_state;
12153         struct intel_dpll_hw_state dpll_hw_state;
12154         enum intel_dpll_id shared_dpll;
12155         uint32_t ddi_pll_sel;
12156         bool force_thru;
12157
12158         /* FIXME: before the switch to atomic started, a new pipe_config was
12159          * kzalloc'd. Code that depends on any field being zero should be
12160          * fixed, so that the crtc_state can be safely duplicated. For now,
12161          * only fields that are know to not cause problems are preserved. */
12162
12163         tmp_state = crtc_state->base;
12164         scaler_state = crtc_state->scaler_state;
12165         shared_dpll = crtc_state->shared_dpll;
12166         dpll_hw_state = crtc_state->dpll_hw_state;
12167         ddi_pll_sel = crtc_state->ddi_pll_sel;
12168         force_thru = crtc_state->pch_pfit.force_thru;
12169
12170         memset(crtc_state, 0, sizeof *crtc_state);
12171
12172         crtc_state->base = tmp_state;
12173         crtc_state->scaler_state = scaler_state;
12174         crtc_state->shared_dpll = shared_dpll;
12175         crtc_state->dpll_hw_state = dpll_hw_state;
12176         crtc_state->ddi_pll_sel = ddi_pll_sel;
12177         crtc_state->pch_pfit.force_thru = force_thru;
12178 }
12179
12180 static int
12181 intel_modeset_pipe_config(struct drm_crtc *crtc,
12182                           struct intel_crtc_state *pipe_config)
12183 {
12184         struct drm_atomic_state *state = pipe_config->base.state;
12185         struct intel_encoder *encoder;
12186         struct drm_connector *connector;
12187         struct drm_connector_state *connector_state;
12188         int base_bpp, ret = -EINVAL;
12189         int i;
12190         bool retry = true;
12191
12192         clear_intel_crtc_state(pipe_config);
12193
12194         pipe_config->cpu_transcoder =
12195                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12196
12197         /*
12198          * Sanitize sync polarity flags based on requested ones. If neither
12199          * positive or negative polarity is requested, treat this as meaning
12200          * negative polarity.
12201          */
12202         if (!(pipe_config->base.adjusted_mode.flags &
12203               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12204                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12205
12206         if (!(pipe_config->base.adjusted_mode.flags &
12207               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12208                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12209
12210         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12211          * plane pixel format and any sink constraints into account. Returns the
12212          * source plane bpp so that dithering can be selected on mismatches
12213          * after encoders and crtc also have had their say. */
12214         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12215                                              pipe_config);
12216         if (base_bpp < 0)
12217                 goto fail;
12218
12219         /*
12220          * Determine the real pipe dimensions. Note that stereo modes can
12221          * increase the actual pipe size due to the frame doubling and
12222          * insertion of additional space for blanks between the frame. This
12223          * is stored in the crtc timings. We use the requested mode to do this
12224          * computation to clearly distinguish it from the adjusted mode, which
12225          * can be changed by the connectors in the below retry loop.
12226          */
12227         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12228                                &pipe_config->pipe_src_w,
12229                                &pipe_config->pipe_src_h);
12230
12231 encoder_retry:
12232         /* Ensure the port clock defaults are reset when retrying. */
12233         pipe_config->port_clock = 0;
12234         pipe_config->pixel_multiplier = 1;
12235
12236         /* Fill in default crtc timings, allow encoders to overwrite them. */
12237         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12238                               CRTC_STEREO_DOUBLE);
12239
12240         /* Pass our mode to the connectors and the CRTC to give them a chance to
12241          * adjust it according to limitations or connector properties, and also
12242          * a chance to reject the mode entirely.
12243          */
12244         for_each_connector_in_state(state, connector, connector_state, i) {
12245                 if (connector_state->crtc != crtc)
12246                         continue;
12247
12248                 encoder = to_intel_encoder(connector_state->best_encoder);
12249
12250                 if (!(encoder->compute_config(encoder, pipe_config))) {
12251                         DRM_DEBUG_KMS("Encoder config failure\n");
12252                         goto fail;
12253                 }
12254         }
12255
12256         /* Set default port clock if not overwritten by the encoder. Needs to be
12257          * done afterwards in case the encoder adjusts the mode. */
12258         if (!pipe_config->port_clock)
12259                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12260                         * pipe_config->pixel_multiplier;
12261
12262         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12263         if (ret < 0) {
12264                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12265                 goto fail;
12266         }
12267
12268         if (ret == RETRY) {
12269                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12270                         ret = -EINVAL;
12271                         goto fail;
12272                 }
12273
12274                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12275                 retry = false;
12276                 goto encoder_retry;
12277         }
12278
12279         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12280         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12281                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12282
12283 fail:
12284         return ret;
12285 }
12286
12287 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12288 {
12289         struct drm_encoder *encoder;
12290         struct drm_device *dev = crtc->dev;
12291
12292         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12293                 if (encoder->crtc == crtc)
12294                         return true;
12295
12296         return false;
12297 }
12298
12299 static void
12300 intel_modeset_update_state(struct drm_atomic_state *state)
12301 {
12302         struct drm_device *dev = state->dev;
12303         struct intel_encoder *intel_encoder;
12304         struct drm_crtc *crtc;
12305         struct drm_crtc_state *crtc_state;
12306         struct drm_connector *connector;
12307         int i;
12308
12309         intel_shared_dpll_commit(state);
12310
12311         for_each_intel_encoder(dev, intel_encoder) {
12312                 if (!intel_encoder->base.crtc)
12313                         continue;
12314
12315                 crtc = intel_encoder->base.crtc;
12316                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12317                 if (!crtc_state || !needs_modeset(crtc->state))
12318                         continue;
12319
12320                 intel_encoder->connectors_active = false;
12321         }
12322
12323         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12324
12325         /* Double check state. */
12326         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12327                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12328
12329                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12330
12331                 /* Update hwmode for vblank functions */
12332                 if (crtc->state->active)
12333                         crtc->hwmode = crtc->state->adjusted_mode;
12334                 else
12335                         crtc->hwmode.crtc_clock = 0;
12336         }
12337
12338         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12339                 if (!connector->encoder || !connector->encoder->crtc)
12340                         continue;
12341
12342                 crtc = connector->encoder->crtc;
12343                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12344                 if (!crtc_state || !needs_modeset(crtc->state))
12345                         continue;
12346
12347                 if (crtc->state->active) {
12348                         intel_encoder = to_intel_encoder(connector->encoder);
12349                         intel_encoder->connectors_active = true;
12350                 }
12351         }
12352 }
12353
12354 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12355 {
12356         int diff;
12357
12358         if (clock1 == clock2)
12359                 return true;
12360
12361         if (!clock1 || !clock2)
12362                 return false;
12363
12364         diff = abs(clock1 - clock2);
12365
12366         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12367                 return true;
12368
12369         return false;
12370 }
12371
12372 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12373         list_for_each_entry((intel_crtc), \
12374                             &(dev)->mode_config.crtc_list, \
12375                             base.head) \
12376                 if (mask & (1 <<(intel_crtc)->pipe))
12377
12378
12379 static bool
12380 intel_compare_m_n(unsigned int m, unsigned int n,
12381                   unsigned int m2, unsigned int n2,
12382                   bool exact)
12383 {
12384         if (m == m2 && n == n2)
12385                 return true;
12386
12387         if (exact || !m || !n || !m2 || !n2)
12388                 return false;
12389
12390         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12391
12392         if (m > m2) {
12393                 while (m > m2) {
12394                         m2 <<= 1;
12395                         n2 <<= 1;
12396                 }
12397         } else if (m < m2) {
12398                 while (m < m2) {
12399                         m <<= 1;
12400                         n <<= 1;
12401                 }
12402         }
12403
12404         return m == m2 && n == n2;
12405 }
12406
12407 static bool
12408 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12409                        struct intel_link_m_n *m2_n2,
12410                        bool adjust)
12411 {
12412         if (m_n->tu == m2_n2->tu &&
12413             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12414                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12415             intel_compare_m_n(m_n->link_m, m_n->link_n,
12416                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12417                 if (adjust)
12418                         *m2_n2 = *m_n;
12419
12420                 return true;
12421         }
12422
12423         return false;
12424 }
12425
12426 static bool
12427 intel_pipe_config_compare(struct drm_device *dev,
12428                           struct intel_crtc_state *current_config,
12429                           struct intel_crtc_state *pipe_config,
12430                           bool adjust)
12431 {
12432         bool ret = true;
12433
12434 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12435         do { \
12436                 if (!adjust) \
12437                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12438                 else \
12439                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12440         } while (0)
12441
12442 #define PIPE_CONF_CHECK_X(name) \
12443         if (current_config->name != pipe_config->name) { \
12444                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12445                           "(expected 0x%08x, found 0x%08x)\n", \
12446                           current_config->name, \
12447                           pipe_config->name); \
12448                 ret = false; \
12449         }
12450
12451 #define PIPE_CONF_CHECK_I(name) \
12452         if (current_config->name != pipe_config->name) { \
12453                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12454                           "(expected %i, found %i)\n", \
12455                           current_config->name, \
12456                           pipe_config->name); \
12457                 ret = false; \
12458         }
12459
12460 #define PIPE_CONF_CHECK_M_N(name) \
12461         if (!intel_compare_link_m_n(&current_config->name, \
12462                                     &pipe_config->name,\
12463                                     adjust)) { \
12464                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12465                           "(expected tu %i gmch %i/%i link %i/%i, " \
12466                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12467                           current_config->name.tu, \
12468                           current_config->name.gmch_m, \
12469                           current_config->name.gmch_n, \
12470                           current_config->name.link_m, \
12471                           current_config->name.link_n, \
12472                           pipe_config->name.tu, \
12473                           pipe_config->name.gmch_m, \
12474                           pipe_config->name.gmch_n, \
12475                           pipe_config->name.link_m, \
12476                           pipe_config->name.link_n); \
12477                 ret = false; \
12478         }
12479
12480 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12481         if (!intel_compare_link_m_n(&current_config->name, \
12482                                     &pipe_config->name, adjust) && \
12483             !intel_compare_link_m_n(&current_config->alt_name, \
12484                                     &pipe_config->name, adjust)) { \
12485                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12486                           "(expected tu %i gmch %i/%i link %i/%i, " \
12487                           "or tu %i gmch %i/%i link %i/%i, " \
12488                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12489                           current_config->name.tu, \
12490                           current_config->name.gmch_m, \
12491                           current_config->name.gmch_n, \
12492                           current_config->name.link_m, \
12493                           current_config->name.link_n, \
12494                           current_config->alt_name.tu, \
12495                           current_config->alt_name.gmch_m, \
12496                           current_config->alt_name.gmch_n, \
12497                           current_config->alt_name.link_m, \
12498                           current_config->alt_name.link_n, \
12499                           pipe_config->name.tu, \
12500                           pipe_config->name.gmch_m, \
12501                           pipe_config->name.gmch_n, \
12502                           pipe_config->name.link_m, \
12503                           pipe_config->name.link_n); \
12504                 ret = false; \
12505         }
12506
12507 /* This is required for BDW+ where there is only one set of registers for
12508  * switching between high and low RR.
12509  * This macro can be used whenever a comparison has to be made between one
12510  * hw state and multiple sw state variables.
12511  */
12512 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12513         if ((current_config->name != pipe_config->name) && \
12514                 (current_config->alt_name != pipe_config->name)) { \
12515                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12516                                   "(expected %i or %i, found %i)\n", \
12517                                   current_config->name, \
12518                                   current_config->alt_name, \
12519                                   pipe_config->name); \
12520                         ret = false; \
12521         }
12522
12523 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12524         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12525                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12526                           "(expected %i, found %i)\n", \
12527                           current_config->name & (mask), \
12528                           pipe_config->name & (mask)); \
12529                 ret = false; \
12530         }
12531
12532 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12533         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12534                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12535                           "(expected %i, found %i)\n", \
12536                           current_config->name, \
12537                           pipe_config->name); \
12538                 ret = false; \
12539         }
12540
12541 #define PIPE_CONF_QUIRK(quirk)  \
12542         ((current_config->quirks | pipe_config->quirks) & (quirk))
12543
12544         PIPE_CONF_CHECK_I(cpu_transcoder);
12545
12546         PIPE_CONF_CHECK_I(has_pch_encoder);
12547         PIPE_CONF_CHECK_I(fdi_lanes);
12548         PIPE_CONF_CHECK_M_N(fdi_m_n);
12549
12550         PIPE_CONF_CHECK_I(has_dp_encoder);
12551
12552         if (INTEL_INFO(dev)->gen < 8) {
12553                 PIPE_CONF_CHECK_M_N(dp_m_n);
12554
12555                 PIPE_CONF_CHECK_I(has_drrs);
12556                 if (current_config->has_drrs)
12557                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12558         } else
12559                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12560
12561         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12562         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12563         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12564         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12565         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12566         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12567
12568         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12569         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12570         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12571         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12572         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12573         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12574
12575         PIPE_CONF_CHECK_I(pixel_multiplier);
12576         PIPE_CONF_CHECK_I(has_hdmi_sink);
12577         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12578             IS_VALLEYVIEW(dev))
12579                 PIPE_CONF_CHECK_I(limited_color_range);
12580         PIPE_CONF_CHECK_I(has_infoframe);
12581
12582         PIPE_CONF_CHECK_I(has_audio);
12583
12584         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12585                               DRM_MODE_FLAG_INTERLACE);
12586
12587         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12588                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12589                                       DRM_MODE_FLAG_PHSYNC);
12590                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12591                                       DRM_MODE_FLAG_NHSYNC);
12592                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12593                                       DRM_MODE_FLAG_PVSYNC);
12594                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12595                                       DRM_MODE_FLAG_NVSYNC);
12596         }
12597
12598         PIPE_CONF_CHECK_I(pipe_src_w);
12599         PIPE_CONF_CHECK_I(pipe_src_h);
12600
12601         PIPE_CONF_CHECK_I(gmch_pfit.control);
12602         /* pfit ratios are autocomputed by the hw on gen4+ */
12603         if (INTEL_INFO(dev)->gen < 4)
12604                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12605         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12606
12607         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12608         if (current_config->pch_pfit.enabled) {
12609                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12610                 PIPE_CONF_CHECK_I(pch_pfit.size);
12611         }
12612
12613         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12614
12615         /* BDW+ don't expose a synchronous way to read the state */
12616         if (IS_HASWELL(dev))
12617                 PIPE_CONF_CHECK_I(ips_enabled);
12618
12619         PIPE_CONF_CHECK_I(double_wide);
12620
12621         PIPE_CONF_CHECK_X(ddi_pll_sel);
12622
12623         PIPE_CONF_CHECK_I(shared_dpll);
12624         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12625         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12626         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12627         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12628         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12629         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12630         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12631         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12632
12633         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12634                 PIPE_CONF_CHECK_I(pipe_bpp);
12635
12636         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12637         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12638
12639 #undef PIPE_CONF_CHECK_X
12640 #undef PIPE_CONF_CHECK_I
12641 #undef PIPE_CONF_CHECK_I_ALT
12642 #undef PIPE_CONF_CHECK_FLAGS
12643 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12644 #undef PIPE_CONF_QUIRK
12645 #undef INTEL_ERR_OR_DBG_KMS
12646
12647         return ret;
12648 }
12649
12650 static void check_wm_state(struct drm_device *dev)
12651 {
12652         struct drm_i915_private *dev_priv = dev->dev_private;
12653         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12654         struct intel_crtc *intel_crtc;
12655         int plane;
12656
12657         if (INTEL_INFO(dev)->gen < 9)
12658                 return;
12659
12660         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12661         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12662
12663         for_each_intel_crtc(dev, intel_crtc) {
12664                 struct skl_ddb_entry *hw_entry, *sw_entry;
12665                 const enum pipe pipe = intel_crtc->pipe;
12666
12667                 if (!intel_crtc->active)
12668                         continue;
12669
12670                 /* planes */
12671                 for_each_plane(dev_priv, pipe, plane) {
12672                         hw_entry = &hw_ddb.plane[pipe][plane];
12673                         sw_entry = &sw_ddb->plane[pipe][plane];
12674
12675                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12676                                 continue;
12677
12678                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12679                                   "(expected (%u,%u), found (%u,%u))\n",
12680                                   pipe_name(pipe), plane + 1,
12681                                   sw_entry->start, sw_entry->end,
12682                                   hw_entry->start, hw_entry->end);
12683                 }
12684
12685                 /* cursor */
12686                 hw_entry = &hw_ddb.cursor[pipe];
12687                 sw_entry = &sw_ddb->cursor[pipe];
12688
12689                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12690                         continue;
12691
12692                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12693                           "(expected (%u,%u), found (%u,%u))\n",
12694                           pipe_name(pipe),
12695                           sw_entry->start, sw_entry->end,
12696                           hw_entry->start, hw_entry->end);
12697         }
12698 }
12699
12700 static void
12701 check_connector_state(struct drm_device *dev)
12702 {
12703         struct intel_connector *connector;
12704
12705         for_each_intel_connector(dev, connector) {
12706                 struct drm_encoder *encoder = connector->base.encoder;
12707                 struct drm_connector_state *state = connector->base.state;
12708
12709                 /* This also checks the encoder/connector hw state with the
12710                  * ->get_hw_state callbacks. */
12711                 intel_connector_check_state(connector);
12712
12713                 I915_STATE_WARN(state->best_encoder != encoder,
12714                      "connector's staged encoder doesn't match current encoder\n");
12715         }
12716 }
12717
12718 static void
12719 check_encoder_state(struct drm_device *dev)
12720 {
12721         struct intel_encoder *encoder;
12722         struct intel_connector *connector;
12723
12724         for_each_intel_encoder(dev, encoder) {
12725                 bool enabled = false;
12726                 bool active = false;
12727                 enum pipe pipe, tracked_pipe;
12728
12729                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12730                               encoder->base.base.id,
12731                               encoder->base.name);
12732
12733                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12734                      "encoder's active_connectors set, but no crtc\n");
12735
12736                 for_each_intel_connector(dev, connector) {
12737                         if (connector->base.encoder != &encoder->base)
12738                                 continue;
12739                         enabled = true;
12740                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12741                                 active = true;
12742
12743                         I915_STATE_WARN(connector->base.state->crtc !=
12744                                         encoder->base.crtc,
12745                              "connector's crtc doesn't match encoder crtc\n");
12746                 }
12747
12748                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12749                      "encoder's enabled state mismatch "
12750                      "(expected %i, found %i)\n",
12751                      !!encoder->base.crtc, enabled);
12752                 I915_STATE_WARN(active && !encoder->base.crtc,
12753                      "active encoder with no crtc\n");
12754
12755                 I915_STATE_WARN(encoder->connectors_active != active,
12756                      "encoder's computed active state doesn't match tracked active state "
12757                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12758
12759                 active = encoder->get_hw_state(encoder, &pipe);
12760                 I915_STATE_WARN(active != encoder->connectors_active,
12761                      "encoder's hw state doesn't match sw tracking "
12762                      "(expected %i, found %i)\n",
12763                      encoder->connectors_active, active);
12764
12765                 if (!encoder->base.crtc)
12766                         continue;
12767
12768                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12769                 I915_STATE_WARN(active && pipe != tracked_pipe,
12770                      "active encoder's pipe doesn't match"
12771                      "(expected %i, found %i)\n",
12772                      tracked_pipe, pipe);
12773
12774         }
12775 }
12776
12777 static void
12778 check_crtc_state(struct drm_device *dev)
12779 {
12780         struct drm_i915_private *dev_priv = dev->dev_private;
12781         struct intel_crtc *crtc;
12782         struct intel_encoder *encoder;
12783         struct intel_crtc_state pipe_config;
12784
12785         for_each_intel_crtc(dev, crtc) {
12786                 bool enabled = false;
12787                 bool active = false;
12788
12789                 memset(&pipe_config, 0, sizeof(pipe_config));
12790
12791                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12792                               crtc->base.base.id);
12793
12794                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12795                      "active crtc, but not enabled in sw tracking\n");
12796
12797                 for_each_intel_encoder(dev, encoder) {
12798                         if (encoder->base.crtc != &crtc->base)
12799                                 continue;
12800                         enabled = true;
12801                         if (encoder->connectors_active)
12802                                 active = true;
12803                 }
12804
12805                 I915_STATE_WARN(active != crtc->active,
12806                      "crtc's computed active state doesn't match tracked active state "
12807                      "(expected %i, found %i)\n", active, crtc->active);
12808                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12809                      "crtc's computed enabled state doesn't match tracked enabled state "
12810                      "(expected %i, found %i)\n", enabled,
12811                                 crtc->base.state->enable);
12812
12813                 active = dev_priv->display.get_pipe_config(crtc,
12814                                                            &pipe_config);
12815
12816                 /* hw state is inconsistent with the pipe quirk */
12817                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12818                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12819                         active = crtc->active;
12820
12821                 for_each_intel_encoder(dev, encoder) {
12822                         enum pipe pipe;
12823                         if (encoder->base.crtc != &crtc->base)
12824                                 continue;
12825                         if (encoder->get_hw_state(encoder, &pipe))
12826                                 encoder->get_config(encoder, &pipe_config);
12827                 }
12828
12829                 I915_STATE_WARN(crtc->active != active,
12830                      "crtc active state doesn't match with hw state "
12831                      "(expected %i, found %i)\n", crtc->active, active);
12832
12833                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12834                      "transitional active state does not match atomic hw state "
12835                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12836
12837                 if (!active)
12838                         continue;
12839
12840                 if (!intel_pipe_config_compare(dev, crtc->config,
12841                                                &pipe_config, false)) {
12842                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12843                         intel_dump_pipe_config(crtc, &pipe_config,
12844                                                "[hw state]");
12845                         intel_dump_pipe_config(crtc, crtc->config,
12846                                                "[sw state]");
12847                 }
12848         }
12849 }
12850
12851 static void
12852 check_shared_dpll_state(struct drm_device *dev)
12853 {
12854         struct drm_i915_private *dev_priv = dev->dev_private;
12855         struct intel_crtc *crtc;
12856         struct intel_dpll_hw_state dpll_hw_state;
12857         int i;
12858
12859         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12860                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12861                 int enabled_crtcs = 0, active_crtcs = 0;
12862                 bool active;
12863
12864                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12865
12866                 DRM_DEBUG_KMS("%s\n", pll->name);
12867
12868                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12869
12870                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12871                      "more active pll users than references: %i vs %i\n",
12872                      pll->active, hweight32(pll->config.crtc_mask));
12873                 I915_STATE_WARN(pll->active && !pll->on,
12874                      "pll in active use but not on in sw tracking\n");
12875                 I915_STATE_WARN(pll->on && !pll->active,
12876                      "pll in on but not on in use in sw tracking\n");
12877                 I915_STATE_WARN(pll->on != active,
12878                      "pll on state mismatch (expected %i, found %i)\n",
12879                      pll->on, active);
12880
12881                 for_each_intel_crtc(dev, crtc) {
12882                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12883                                 enabled_crtcs++;
12884                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12885                                 active_crtcs++;
12886                 }
12887                 I915_STATE_WARN(pll->active != active_crtcs,
12888                      "pll active crtcs mismatch (expected %i, found %i)\n",
12889                      pll->active, active_crtcs);
12890                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12891                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12892                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12893
12894                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12895                                        sizeof(dpll_hw_state)),
12896                      "pll hw state mismatch\n");
12897         }
12898 }
12899
12900 static void
12901 intel_modeset_check_state(struct drm_device *dev,
12902                           struct drm_atomic_state *old_state)
12903 {
12904         check_wm_state(dev);
12905         check_connector_state(dev);
12906         check_encoder_state(dev);
12907         check_crtc_state(dev);
12908         check_shared_dpll_state(dev);
12909 }
12910
12911 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12912                                      int dotclock)
12913 {
12914         /*
12915          * FDI already provided one idea for the dotclock.
12916          * Yell if the encoder disagrees.
12917          */
12918         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12919              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12920              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12921 }
12922
12923 static void update_scanline_offset(struct intel_crtc *crtc)
12924 {
12925         struct drm_device *dev = crtc->base.dev;
12926
12927         /*
12928          * The scanline counter increments at the leading edge of hsync.
12929          *
12930          * On most platforms it starts counting from vtotal-1 on the
12931          * first active line. That means the scanline counter value is
12932          * always one less than what we would expect. Ie. just after
12933          * start of vblank, which also occurs at start of hsync (on the
12934          * last active line), the scanline counter will read vblank_start-1.
12935          *
12936          * On gen2 the scanline counter starts counting from 1 instead
12937          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12938          * to keep the value positive), instead of adding one.
12939          *
12940          * On HSW+ the behaviour of the scanline counter depends on the output
12941          * type. For DP ports it behaves like most other platforms, but on HDMI
12942          * there's an extra 1 line difference. So we need to add two instead of
12943          * one to the value.
12944          */
12945         if (IS_GEN2(dev)) {
12946                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12947                 int vtotal;
12948
12949                 vtotal = mode->crtc_vtotal;
12950                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12951                         vtotal /= 2;
12952
12953                 crtc->scanline_offset = vtotal - 1;
12954         } else if (HAS_DDI(dev) &&
12955                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12956                 crtc->scanline_offset = 2;
12957         } else
12958                 crtc->scanline_offset = 1;
12959 }
12960
12961 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12962 {
12963         struct drm_device *dev = state->dev;
12964         struct drm_i915_private *dev_priv = to_i915(dev);
12965         struct intel_shared_dpll_config *shared_dpll = NULL;
12966         struct intel_crtc *intel_crtc;
12967         struct intel_crtc_state *intel_crtc_state;
12968         struct drm_crtc *crtc;
12969         struct drm_crtc_state *crtc_state;
12970         int i;
12971
12972         if (!dev_priv->display.crtc_compute_clock)
12973                 return;
12974
12975         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12976                 int dpll;
12977
12978                 intel_crtc = to_intel_crtc(crtc);
12979                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12980                 dpll = intel_crtc_state->shared_dpll;
12981
12982                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12983                         continue;
12984
12985                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12986
12987                 if (!shared_dpll)
12988                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12989
12990                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12991         }
12992 }
12993
12994 /*
12995  * This implements the workaround described in the "notes" section of the mode
12996  * set sequence documentation. When going from no pipes or single pipe to
12997  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12998  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12999  */
13000 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13001 {
13002         struct drm_crtc_state *crtc_state;
13003         struct intel_crtc *intel_crtc;
13004         struct drm_crtc *crtc;
13005         struct intel_crtc_state *first_crtc_state = NULL;
13006         struct intel_crtc_state *other_crtc_state = NULL;
13007         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13008         int i;
13009
13010         /* look at all crtc's that are going to be enabled in during modeset */
13011         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13012                 intel_crtc = to_intel_crtc(crtc);
13013
13014                 if (!crtc_state->active || !needs_modeset(crtc_state))
13015                         continue;
13016
13017                 if (first_crtc_state) {
13018                         other_crtc_state = to_intel_crtc_state(crtc_state);
13019                         break;
13020                 } else {
13021                         first_crtc_state = to_intel_crtc_state(crtc_state);
13022                         first_pipe = intel_crtc->pipe;
13023                 }
13024         }
13025
13026         /* No workaround needed? */
13027         if (!first_crtc_state)
13028                 return 0;
13029
13030         /* w/a possibly needed, check how many crtc's are already enabled. */
13031         for_each_intel_crtc(state->dev, intel_crtc) {
13032                 struct intel_crtc_state *pipe_config;
13033
13034                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13035                 if (IS_ERR(pipe_config))
13036                         return PTR_ERR(pipe_config);
13037
13038                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13039
13040                 if (!pipe_config->base.active ||
13041                     needs_modeset(&pipe_config->base))
13042                         continue;
13043
13044                 /* 2 or more enabled crtcs means no need for w/a */
13045                 if (enabled_pipe != INVALID_PIPE)
13046                         return 0;
13047
13048                 enabled_pipe = intel_crtc->pipe;
13049         }
13050
13051         if (enabled_pipe != INVALID_PIPE)
13052                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13053         else if (other_crtc_state)
13054                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13055
13056         return 0;
13057 }
13058
13059 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13060 {
13061         struct drm_crtc *crtc;
13062         struct drm_crtc_state *crtc_state;
13063         int ret = 0;
13064
13065         /* add all active pipes to the state */
13066         for_each_crtc(state->dev, crtc) {
13067                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13068                 if (IS_ERR(crtc_state))
13069                         return PTR_ERR(crtc_state);
13070
13071                 if (!crtc_state->active || needs_modeset(crtc_state))
13072                         continue;
13073
13074                 crtc_state->mode_changed = true;
13075
13076                 ret = drm_atomic_add_affected_connectors(state, crtc);
13077                 if (ret)
13078                         break;
13079
13080                 ret = drm_atomic_add_affected_planes(state, crtc);
13081                 if (ret)
13082                         break;
13083         }
13084
13085         return ret;
13086 }
13087
13088
13089 static int intel_modeset_checks(struct drm_atomic_state *state)
13090 {
13091         struct drm_device *dev = state->dev;
13092         struct drm_i915_private *dev_priv = dev->dev_private;
13093         int ret;
13094
13095         if (!check_digital_port_conflicts(state)) {
13096                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13097                 return -EINVAL;
13098         }
13099
13100         /*
13101          * See if the config requires any additional preparation, e.g.
13102          * to adjust global state with pipes off.  We need to do this
13103          * here so we can get the modeset_pipe updated config for the new
13104          * mode set on this crtc.  For other crtcs we need to use the
13105          * adjusted_mode bits in the crtc directly.
13106          */
13107         if (dev_priv->display.modeset_calc_cdclk) {
13108                 unsigned int cdclk;
13109
13110                 ret = dev_priv->display.modeset_calc_cdclk(state);
13111
13112                 cdclk = to_intel_atomic_state(state)->cdclk;
13113                 if (!ret && cdclk != dev_priv->cdclk_freq)
13114                         ret = intel_modeset_all_pipes(state);
13115
13116                 if (ret < 0)
13117                         return ret;
13118         } else
13119                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13120
13121         intel_modeset_clear_plls(state);
13122
13123         if (IS_HASWELL(dev))
13124                 return haswell_mode_set_planes_workaround(state);
13125
13126         return 0;
13127 }
13128
13129 /**
13130  * intel_atomic_check - validate state object
13131  * @dev: drm device
13132  * @state: state to validate
13133  */
13134 static int intel_atomic_check(struct drm_device *dev,
13135                               struct drm_atomic_state *state)
13136 {
13137         struct drm_crtc *crtc;
13138         struct drm_crtc_state *crtc_state;
13139         int ret, i;
13140         bool any_ms = false;
13141
13142         ret = drm_atomic_helper_check_modeset(dev, state);
13143         if (ret)
13144                 return ret;
13145
13146         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13147                 struct intel_crtc_state *pipe_config =
13148                         to_intel_crtc_state(crtc_state);
13149
13150                 /* Catch I915_MODE_FLAG_INHERITED */
13151                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13152                         crtc_state->mode_changed = true;
13153
13154                 if (!crtc_state->enable) {
13155                         if (needs_modeset(crtc_state))
13156                                 any_ms = true;
13157                         continue;
13158                 }
13159
13160                 if (!needs_modeset(crtc_state))
13161                         continue;
13162
13163                 /* FIXME: For only active_changed we shouldn't need to do any
13164                  * state recomputation at all. */
13165
13166                 ret = drm_atomic_add_affected_connectors(state, crtc);
13167                 if (ret)
13168                         return ret;
13169
13170                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13171                 if (ret)
13172                         return ret;
13173
13174                 if (i915.fastboot &&
13175                     intel_pipe_config_compare(state->dev,
13176                                         to_intel_crtc_state(crtc->state),
13177                                         pipe_config, true)) {
13178                         crtc_state->mode_changed = false;
13179                 }
13180
13181                 if (needs_modeset(crtc_state)) {
13182                         any_ms = true;
13183
13184                         ret = drm_atomic_add_affected_planes(state, crtc);
13185                         if (ret)
13186                                 return ret;
13187                 }
13188
13189                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13190                                        needs_modeset(crtc_state) ?
13191                                        "[modeset]" : "[fastset]");
13192         }
13193
13194         if (any_ms) {
13195                 ret = intel_modeset_checks(state);
13196
13197                 if (ret)
13198                         return ret;
13199         } else
13200                 to_intel_atomic_state(state)->cdclk =
13201                         to_i915(state->dev)->cdclk_freq;
13202
13203         return drm_atomic_helper_check_planes(state->dev, state);
13204 }
13205
13206 /**
13207  * intel_atomic_commit - commit validated state object
13208  * @dev: DRM device
13209  * @state: the top-level driver state object
13210  * @async: asynchronous commit
13211  *
13212  * This function commits a top-level state object that has been validated
13213  * with drm_atomic_helper_check().
13214  *
13215  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13216  * we can only handle plane-related operations and do not yet support
13217  * asynchronous commit.
13218  *
13219  * RETURNS
13220  * Zero for success or -errno.
13221  */
13222 static int intel_atomic_commit(struct drm_device *dev,
13223                                struct drm_atomic_state *state,
13224                                bool async)
13225 {
13226         struct drm_i915_private *dev_priv = dev->dev_private;
13227         struct drm_crtc *crtc;
13228         struct drm_crtc_state *crtc_state;
13229         int ret = 0;
13230         int i;
13231         bool any_ms = false;
13232
13233         if (async) {
13234                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13235                 return -EINVAL;
13236         }
13237
13238         ret = drm_atomic_helper_prepare_planes(dev, state);
13239         if (ret)
13240                 return ret;
13241
13242         drm_atomic_helper_swap_state(dev, state);
13243
13244         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13245                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13246
13247                 if (!needs_modeset(crtc->state))
13248                         continue;
13249
13250                 any_ms = true;
13251                 intel_pre_plane_update(intel_crtc);
13252
13253                 if (crtc_state->active) {
13254                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13255                         dev_priv->display.crtc_disable(crtc);
13256                         intel_crtc->active = false;
13257                         intel_disable_shared_dpll(intel_crtc);
13258                 }
13259         }
13260
13261         /* Only after disabling all output pipelines that will be changed can we
13262          * update the the output configuration. */
13263         intel_modeset_update_state(state);
13264
13265         /* The state has been swaped above, so state actually contains the
13266          * old state now. */
13267         if (any_ms)
13268                 modeset_update_crtc_power_domains(state);
13269
13270         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13271         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13272                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13273                 bool modeset = needs_modeset(crtc->state);
13274
13275                 if (modeset && crtc->state->active) {
13276                         update_scanline_offset(to_intel_crtc(crtc));
13277                         dev_priv->display.crtc_enable(crtc);
13278                 }
13279
13280                 if (!modeset)
13281                         intel_pre_plane_update(intel_crtc);
13282
13283                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13284                 intel_post_plane_update(intel_crtc);
13285         }
13286
13287         /* FIXME: add subpixel order */
13288
13289         drm_atomic_helper_wait_for_vblanks(dev, state);
13290         drm_atomic_helper_cleanup_planes(dev, state);
13291
13292         if (any_ms)
13293                 intel_modeset_check_state(dev, state);
13294
13295         drm_atomic_state_free(state);
13296
13297         return 0;
13298 }
13299
13300 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13301 {
13302         struct drm_device *dev = crtc->dev;
13303         struct drm_atomic_state *state;
13304         struct drm_crtc_state *crtc_state;
13305         int ret;
13306
13307         state = drm_atomic_state_alloc(dev);
13308         if (!state) {
13309                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13310                               crtc->base.id);
13311                 return;
13312         }
13313
13314         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13315
13316 retry:
13317         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13318         ret = PTR_ERR_OR_ZERO(crtc_state);
13319         if (!ret) {
13320                 if (!crtc_state->active)
13321                         goto out;
13322
13323                 crtc_state->mode_changed = true;
13324                 ret = drm_atomic_commit(state);
13325         }
13326
13327         if (ret == -EDEADLK) {
13328                 drm_atomic_state_clear(state);
13329                 drm_modeset_backoff(state->acquire_ctx);
13330                 goto retry;
13331         }
13332
13333         if (ret)
13334 out:
13335                 drm_atomic_state_free(state);
13336 }
13337
13338 #undef for_each_intel_crtc_masked
13339
13340 static const struct drm_crtc_funcs intel_crtc_funcs = {
13341         .gamma_set = intel_crtc_gamma_set,
13342         .set_config = drm_atomic_helper_set_config,
13343         .destroy = intel_crtc_destroy,
13344         .page_flip = intel_crtc_page_flip,
13345         .atomic_duplicate_state = intel_crtc_duplicate_state,
13346         .atomic_destroy_state = intel_crtc_destroy_state,
13347 };
13348
13349 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13350                                       struct intel_shared_dpll *pll,
13351                                       struct intel_dpll_hw_state *hw_state)
13352 {
13353         uint32_t val;
13354
13355         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13356                 return false;
13357
13358         val = I915_READ(PCH_DPLL(pll->id));
13359         hw_state->dpll = val;
13360         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13361         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13362
13363         return val & DPLL_VCO_ENABLE;
13364 }
13365
13366 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13367                                   struct intel_shared_dpll *pll)
13368 {
13369         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13370         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13371 }
13372
13373 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13374                                 struct intel_shared_dpll *pll)
13375 {
13376         /* PCH refclock must be enabled first */
13377         ibx_assert_pch_refclk_enabled(dev_priv);
13378
13379         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13380
13381         /* Wait for the clocks to stabilize. */
13382         POSTING_READ(PCH_DPLL(pll->id));
13383         udelay(150);
13384
13385         /* The pixel multiplier can only be updated once the
13386          * DPLL is enabled and the clocks are stable.
13387          *
13388          * So write it again.
13389          */
13390         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13391         POSTING_READ(PCH_DPLL(pll->id));
13392         udelay(200);
13393 }
13394
13395 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13396                                  struct intel_shared_dpll *pll)
13397 {
13398         struct drm_device *dev = dev_priv->dev;
13399         struct intel_crtc *crtc;
13400
13401         /* Make sure no transcoder isn't still depending on us. */
13402         for_each_intel_crtc(dev, crtc) {
13403                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13404                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13405         }
13406
13407         I915_WRITE(PCH_DPLL(pll->id), 0);
13408         POSTING_READ(PCH_DPLL(pll->id));
13409         udelay(200);
13410 }
13411
13412 static char *ibx_pch_dpll_names[] = {
13413         "PCH DPLL A",
13414         "PCH DPLL B",
13415 };
13416
13417 static void ibx_pch_dpll_init(struct drm_device *dev)
13418 {
13419         struct drm_i915_private *dev_priv = dev->dev_private;
13420         int i;
13421
13422         dev_priv->num_shared_dpll = 2;
13423
13424         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13425                 dev_priv->shared_dplls[i].id = i;
13426                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13427                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13428                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13429                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13430                 dev_priv->shared_dplls[i].get_hw_state =
13431                         ibx_pch_dpll_get_hw_state;
13432         }
13433 }
13434
13435 static void intel_shared_dpll_init(struct drm_device *dev)
13436 {
13437         struct drm_i915_private *dev_priv = dev->dev_private;
13438
13439         intel_update_cdclk(dev);
13440
13441         if (HAS_DDI(dev))
13442                 intel_ddi_pll_init(dev);
13443         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13444                 ibx_pch_dpll_init(dev);
13445         else
13446                 dev_priv->num_shared_dpll = 0;
13447
13448         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13449 }
13450
13451 /**
13452  * intel_prepare_plane_fb - Prepare fb for usage on plane
13453  * @plane: drm plane to prepare for
13454  * @fb: framebuffer to prepare for presentation
13455  *
13456  * Prepares a framebuffer for usage on a display plane.  Generally this
13457  * involves pinning the underlying object and updating the frontbuffer tracking
13458  * bits.  Some older platforms need special physical address handling for
13459  * cursor planes.
13460  *
13461  * Returns 0 on success, negative error code on failure.
13462  */
13463 int
13464 intel_prepare_plane_fb(struct drm_plane *plane,
13465                        struct drm_framebuffer *fb,
13466                        const struct drm_plane_state *new_state)
13467 {
13468         struct drm_device *dev = plane->dev;
13469         struct intel_plane *intel_plane = to_intel_plane(plane);
13470         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13471         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13472         int ret = 0;
13473
13474         if (!obj)
13475                 return 0;
13476
13477         mutex_lock(&dev->struct_mutex);
13478
13479         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13480             INTEL_INFO(dev)->cursor_needs_physical) {
13481                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13482                 ret = i915_gem_object_attach_phys(obj, align);
13483                 if (ret)
13484                         DRM_DEBUG_KMS("failed to attach phys object\n");
13485         } else {
13486                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13487         }
13488
13489         if (ret == 0)
13490                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13491
13492         mutex_unlock(&dev->struct_mutex);
13493
13494         return ret;
13495 }
13496
13497 /**
13498  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13499  * @plane: drm plane to clean up for
13500  * @fb: old framebuffer that was on plane
13501  *
13502  * Cleans up a framebuffer that has just been removed from a plane.
13503  */
13504 void
13505 intel_cleanup_plane_fb(struct drm_plane *plane,
13506                        struct drm_framebuffer *fb,
13507                        const struct drm_plane_state *old_state)
13508 {
13509         struct drm_device *dev = plane->dev;
13510         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13511
13512         if (WARN_ON(!obj))
13513                 return;
13514
13515         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13516             !INTEL_INFO(dev)->cursor_needs_physical) {
13517                 mutex_lock(&dev->struct_mutex);
13518                 intel_unpin_fb_obj(fb, old_state);
13519                 mutex_unlock(&dev->struct_mutex);
13520         }
13521 }
13522
13523 int
13524 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13525 {
13526         int max_scale;
13527         struct drm_device *dev;
13528         struct drm_i915_private *dev_priv;
13529         int crtc_clock, cdclk;
13530
13531         if (!intel_crtc || !crtc_state)
13532                 return DRM_PLANE_HELPER_NO_SCALING;
13533
13534         dev = intel_crtc->base.dev;
13535         dev_priv = dev->dev_private;
13536         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13537         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13538
13539         if (!crtc_clock || !cdclk)
13540                 return DRM_PLANE_HELPER_NO_SCALING;
13541
13542         /*
13543          * skl max scale is lower of:
13544          *    close to 3 but not 3, -1 is for that purpose
13545          *            or
13546          *    cdclk/crtc_clock
13547          */
13548         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13549
13550         return max_scale;
13551 }
13552
13553 static int
13554 intel_check_primary_plane(struct drm_plane *plane,
13555                           struct intel_crtc_state *crtc_state,
13556                           struct intel_plane_state *state)
13557 {
13558         struct drm_crtc *crtc = state->base.crtc;
13559         struct drm_framebuffer *fb = state->base.fb;
13560         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13561         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13562         bool can_position = false;
13563
13564         /* use scaler when colorkey is not required */
13565         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13566             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13567                 min_scale = 1;
13568                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13569                 can_position = true;
13570         }
13571
13572         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13573                                              &state->dst, &state->clip,
13574                                              min_scale, max_scale,
13575                                              can_position, true,
13576                                              &state->visible);
13577 }
13578
13579 static void
13580 intel_commit_primary_plane(struct drm_plane *plane,
13581                            struct intel_plane_state *state)
13582 {
13583         struct drm_crtc *crtc = state->base.crtc;
13584         struct drm_framebuffer *fb = state->base.fb;
13585         struct drm_device *dev = plane->dev;
13586         struct drm_i915_private *dev_priv = dev->dev_private;
13587         struct intel_crtc *intel_crtc;
13588         struct drm_rect *src = &state->src;
13589
13590         crtc = crtc ? crtc : plane->crtc;
13591         intel_crtc = to_intel_crtc(crtc);
13592
13593         plane->fb = fb;
13594         crtc->x = src->x1 >> 16;
13595         crtc->y = src->y1 >> 16;
13596
13597         if (!crtc->state->active)
13598                 return;
13599
13600         if (state->visible)
13601                 /* FIXME: kill this fastboot hack */
13602                 intel_update_pipe_size(intel_crtc);
13603
13604         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13605 }
13606
13607 static void
13608 intel_disable_primary_plane(struct drm_plane *plane,
13609                             struct drm_crtc *crtc)
13610 {
13611         struct drm_device *dev = plane->dev;
13612         struct drm_i915_private *dev_priv = dev->dev_private;
13613
13614         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13615 }
13616
13617 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13618                                     struct drm_crtc_state *old_crtc_state)
13619 {
13620         struct drm_device *dev = crtc->dev;
13621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13622
13623         if (intel_crtc->atomic.update_wm_pre)
13624                 intel_update_watermarks(crtc);
13625
13626         /* Perform vblank evasion around commit operation */
13627         if (crtc->state->active)
13628                 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13629
13630         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13631                 skl_detach_scalers(intel_crtc);
13632 }
13633
13634 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13635                                      struct drm_crtc_state *old_crtc_state)
13636 {
13637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13638
13639         if (crtc->state->active)
13640                 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13641 }
13642
13643 /**
13644  * intel_plane_destroy - destroy a plane
13645  * @plane: plane to destroy
13646  *
13647  * Common destruction function for all types of planes (primary, cursor,
13648  * sprite).
13649  */
13650 void intel_plane_destroy(struct drm_plane *plane)
13651 {
13652         struct intel_plane *intel_plane = to_intel_plane(plane);
13653         drm_plane_cleanup(plane);
13654         kfree(intel_plane);
13655 }
13656
13657 const struct drm_plane_funcs intel_plane_funcs = {
13658         .update_plane = drm_atomic_helper_update_plane,
13659         .disable_plane = drm_atomic_helper_disable_plane,
13660         .destroy = intel_plane_destroy,
13661         .set_property = drm_atomic_helper_plane_set_property,
13662         .atomic_get_property = intel_plane_atomic_get_property,
13663         .atomic_set_property = intel_plane_atomic_set_property,
13664         .atomic_duplicate_state = intel_plane_duplicate_state,
13665         .atomic_destroy_state = intel_plane_destroy_state,
13666
13667 };
13668
13669 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13670                                                     int pipe)
13671 {
13672         struct intel_plane *primary;
13673         struct intel_plane_state *state;
13674         const uint32_t *intel_primary_formats;
13675         int num_formats;
13676
13677         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13678         if (primary == NULL)
13679                 return NULL;
13680
13681         state = intel_create_plane_state(&primary->base);
13682         if (!state) {
13683                 kfree(primary);
13684                 return NULL;
13685         }
13686         primary->base.state = &state->base;
13687
13688         primary->can_scale = false;
13689         primary->max_downscale = 1;
13690         if (INTEL_INFO(dev)->gen >= 9) {
13691                 primary->can_scale = true;
13692                 state->scaler_id = -1;
13693         }
13694         primary->pipe = pipe;
13695         primary->plane = pipe;
13696         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13697         primary->check_plane = intel_check_primary_plane;
13698         primary->commit_plane = intel_commit_primary_plane;
13699         primary->disable_plane = intel_disable_primary_plane;
13700         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13701                 primary->plane = !pipe;
13702
13703         if (INTEL_INFO(dev)->gen >= 9) {
13704                 intel_primary_formats = skl_primary_formats;
13705                 num_formats = ARRAY_SIZE(skl_primary_formats);
13706         } else if (INTEL_INFO(dev)->gen >= 4) {
13707                 intel_primary_formats = i965_primary_formats;
13708                 num_formats = ARRAY_SIZE(i965_primary_formats);
13709         } else {
13710                 intel_primary_formats = i8xx_primary_formats;
13711                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13712         }
13713
13714         drm_universal_plane_init(dev, &primary->base, 0,
13715                                  &intel_plane_funcs,
13716                                  intel_primary_formats, num_formats,
13717                                  DRM_PLANE_TYPE_PRIMARY);
13718
13719         if (INTEL_INFO(dev)->gen >= 4)
13720                 intel_create_rotation_property(dev, primary);
13721
13722         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13723
13724         return &primary->base;
13725 }
13726
13727 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13728 {
13729         if (!dev->mode_config.rotation_property) {
13730                 unsigned long flags = BIT(DRM_ROTATE_0) |
13731                         BIT(DRM_ROTATE_180);
13732
13733                 if (INTEL_INFO(dev)->gen >= 9)
13734                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13735
13736                 dev->mode_config.rotation_property =
13737                         drm_mode_create_rotation_property(dev, flags);
13738         }
13739         if (dev->mode_config.rotation_property)
13740                 drm_object_attach_property(&plane->base.base,
13741                                 dev->mode_config.rotation_property,
13742                                 plane->base.state->rotation);
13743 }
13744
13745 static int
13746 intel_check_cursor_plane(struct drm_plane *plane,
13747                          struct intel_crtc_state *crtc_state,
13748                          struct intel_plane_state *state)
13749 {
13750         struct drm_crtc *crtc = crtc_state->base.crtc;
13751         struct drm_framebuffer *fb = state->base.fb;
13752         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13753         unsigned stride;
13754         int ret;
13755
13756         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13757                                             &state->dst, &state->clip,
13758                                             DRM_PLANE_HELPER_NO_SCALING,
13759                                             DRM_PLANE_HELPER_NO_SCALING,
13760                                             true, true, &state->visible);
13761         if (ret)
13762                 return ret;
13763
13764         /* if we want to turn off the cursor ignore width and height */
13765         if (!obj)
13766                 return 0;
13767
13768         /* Check for which cursor types we support */
13769         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13770                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13771                           state->base.crtc_w, state->base.crtc_h);
13772                 return -EINVAL;
13773         }
13774
13775         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13776         if (obj->base.size < stride * state->base.crtc_h) {
13777                 DRM_DEBUG_KMS("buffer is too small\n");
13778                 return -ENOMEM;
13779         }
13780
13781         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13782                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13783                 return -EINVAL;
13784         }
13785
13786         return 0;
13787 }
13788
13789 static void
13790 intel_disable_cursor_plane(struct drm_plane *plane,
13791                            struct drm_crtc *crtc)
13792 {
13793         intel_crtc_update_cursor(crtc, false);
13794 }
13795
13796 static void
13797 intel_commit_cursor_plane(struct drm_plane *plane,
13798                           struct intel_plane_state *state)
13799 {
13800         struct drm_crtc *crtc = state->base.crtc;
13801         struct drm_device *dev = plane->dev;
13802         struct intel_crtc *intel_crtc;
13803         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13804         uint32_t addr;
13805
13806         crtc = crtc ? crtc : plane->crtc;
13807         intel_crtc = to_intel_crtc(crtc);
13808
13809         plane->fb = state->base.fb;
13810         crtc->cursor_x = state->base.crtc_x;
13811         crtc->cursor_y = state->base.crtc_y;
13812
13813         if (intel_crtc->cursor_bo == obj)
13814                 goto update;
13815
13816         if (!obj)
13817                 addr = 0;
13818         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13819                 addr = i915_gem_obj_ggtt_offset(obj);
13820         else
13821                 addr = obj->phys_handle->busaddr;
13822
13823         intel_crtc->cursor_addr = addr;
13824         intel_crtc->cursor_bo = obj;
13825
13826 update:
13827         if (crtc->state->active)
13828                 intel_crtc_update_cursor(crtc, state->visible);
13829 }
13830
13831 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13832                                                    int pipe)
13833 {
13834         struct intel_plane *cursor;
13835         struct intel_plane_state *state;
13836
13837         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13838         if (cursor == NULL)
13839                 return NULL;
13840
13841         state = intel_create_plane_state(&cursor->base);
13842         if (!state) {
13843                 kfree(cursor);
13844                 return NULL;
13845         }
13846         cursor->base.state = &state->base;
13847
13848         cursor->can_scale = false;
13849         cursor->max_downscale = 1;
13850         cursor->pipe = pipe;
13851         cursor->plane = pipe;
13852         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13853         cursor->check_plane = intel_check_cursor_plane;
13854         cursor->commit_plane = intel_commit_cursor_plane;
13855         cursor->disable_plane = intel_disable_cursor_plane;
13856
13857         drm_universal_plane_init(dev, &cursor->base, 0,
13858                                  &intel_plane_funcs,
13859                                  intel_cursor_formats,
13860                                  ARRAY_SIZE(intel_cursor_formats),
13861                                  DRM_PLANE_TYPE_CURSOR);
13862
13863         if (INTEL_INFO(dev)->gen >= 4) {
13864                 if (!dev->mode_config.rotation_property)
13865                         dev->mode_config.rotation_property =
13866                                 drm_mode_create_rotation_property(dev,
13867                                                         BIT(DRM_ROTATE_0) |
13868                                                         BIT(DRM_ROTATE_180));
13869                 if (dev->mode_config.rotation_property)
13870                         drm_object_attach_property(&cursor->base.base,
13871                                 dev->mode_config.rotation_property,
13872                                 state->base.rotation);
13873         }
13874
13875         if (INTEL_INFO(dev)->gen >=9)
13876                 state->scaler_id = -1;
13877
13878         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13879
13880         return &cursor->base;
13881 }
13882
13883 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13884         struct intel_crtc_state *crtc_state)
13885 {
13886         int i;
13887         struct intel_scaler *intel_scaler;
13888         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13889
13890         for (i = 0; i < intel_crtc->num_scalers; i++) {
13891                 intel_scaler = &scaler_state->scalers[i];
13892                 intel_scaler->in_use = 0;
13893                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13894         }
13895
13896         scaler_state->scaler_id = -1;
13897 }
13898
13899 static void intel_crtc_init(struct drm_device *dev, int pipe)
13900 {
13901         struct drm_i915_private *dev_priv = dev->dev_private;
13902         struct intel_crtc *intel_crtc;
13903         struct intel_crtc_state *crtc_state = NULL;
13904         struct drm_plane *primary = NULL;
13905         struct drm_plane *cursor = NULL;
13906         int i, ret;
13907
13908         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13909         if (intel_crtc == NULL)
13910                 return;
13911
13912         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13913         if (!crtc_state)
13914                 goto fail;
13915         intel_crtc->config = crtc_state;
13916         intel_crtc->base.state = &crtc_state->base;
13917         crtc_state->base.crtc = &intel_crtc->base;
13918
13919         /* initialize shared scalers */
13920         if (INTEL_INFO(dev)->gen >= 9) {
13921                 if (pipe == PIPE_C)
13922                         intel_crtc->num_scalers = 1;
13923                 else
13924                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13925
13926                 skl_init_scalers(dev, intel_crtc, crtc_state);
13927         }
13928
13929         primary = intel_primary_plane_create(dev, pipe);
13930         if (!primary)
13931                 goto fail;
13932
13933         cursor = intel_cursor_plane_create(dev, pipe);
13934         if (!cursor)
13935                 goto fail;
13936
13937         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13938                                         cursor, &intel_crtc_funcs);
13939         if (ret)
13940                 goto fail;
13941
13942         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13943         for (i = 0; i < 256; i++) {
13944                 intel_crtc->lut_r[i] = i;
13945                 intel_crtc->lut_g[i] = i;
13946                 intel_crtc->lut_b[i] = i;
13947         }
13948
13949         /*
13950          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13951          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13952          */
13953         intel_crtc->pipe = pipe;
13954         intel_crtc->plane = pipe;
13955         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13956                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13957                 intel_crtc->plane = !pipe;
13958         }
13959
13960         intel_crtc->cursor_base = ~0;
13961         intel_crtc->cursor_cntl = ~0;
13962         intel_crtc->cursor_size = ~0;
13963
13964         intel_crtc->wm.cxsr_allowed = true;
13965
13966         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13967                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13968         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13969         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13970
13971         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13972
13973         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13974         return;
13975
13976 fail:
13977         if (primary)
13978                 drm_plane_cleanup(primary);
13979         if (cursor)
13980                 drm_plane_cleanup(cursor);
13981         kfree(crtc_state);
13982         kfree(intel_crtc);
13983 }
13984
13985 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13986 {
13987         struct drm_encoder *encoder = connector->base.encoder;
13988         struct drm_device *dev = connector->base.dev;
13989
13990         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13991
13992         if (!encoder || WARN_ON(!encoder->crtc))
13993                 return INVALID_PIPE;
13994
13995         return to_intel_crtc(encoder->crtc)->pipe;
13996 }
13997
13998 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13999                                 struct drm_file *file)
14000 {
14001         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14002         struct drm_crtc *drmmode_crtc;
14003         struct intel_crtc *crtc;
14004
14005         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14006
14007         if (!drmmode_crtc) {
14008                 DRM_ERROR("no such CRTC id\n");
14009                 return -ENOENT;
14010         }
14011
14012         crtc = to_intel_crtc(drmmode_crtc);
14013         pipe_from_crtc_id->pipe = crtc->pipe;
14014
14015         return 0;
14016 }
14017
14018 static int intel_encoder_clones(struct intel_encoder *encoder)
14019 {
14020         struct drm_device *dev = encoder->base.dev;
14021         struct intel_encoder *source_encoder;
14022         int index_mask = 0;
14023         int entry = 0;
14024
14025         for_each_intel_encoder(dev, source_encoder) {
14026                 if (encoders_cloneable(encoder, source_encoder))
14027                         index_mask |= (1 << entry);
14028
14029                 entry++;
14030         }
14031
14032         return index_mask;
14033 }
14034
14035 static bool has_edp_a(struct drm_device *dev)
14036 {
14037         struct drm_i915_private *dev_priv = dev->dev_private;
14038
14039         if (!IS_MOBILE(dev))
14040                 return false;
14041
14042         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14043                 return false;
14044
14045         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14046                 return false;
14047
14048         return true;
14049 }
14050
14051 static bool intel_crt_present(struct drm_device *dev)
14052 {
14053         struct drm_i915_private *dev_priv = dev->dev_private;
14054
14055         if (INTEL_INFO(dev)->gen >= 9)
14056                 return false;
14057
14058         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14059                 return false;
14060
14061         if (IS_CHERRYVIEW(dev))
14062                 return false;
14063
14064         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14065                 return false;
14066
14067         return true;
14068 }
14069
14070 static void intel_setup_outputs(struct drm_device *dev)
14071 {
14072         struct drm_i915_private *dev_priv = dev->dev_private;
14073         struct intel_encoder *encoder;
14074         bool dpd_is_edp = false;
14075
14076         intel_lvds_init(dev);
14077
14078         if (intel_crt_present(dev))
14079                 intel_crt_init(dev);
14080
14081         if (IS_BROXTON(dev)) {
14082                 /*
14083                  * FIXME: Broxton doesn't support port detection via the
14084                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14085                  * detect the ports.
14086                  */
14087                 intel_ddi_init(dev, PORT_A);
14088                 intel_ddi_init(dev, PORT_B);
14089                 intel_ddi_init(dev, PORT_C);
14090         } else if (HAS_DDI(dev)) {
14091                 int found;
14092
14093                 /*
14094                  * Haswell uses DDI functions to detect digital outputs.
14095                  * On SKL pre-D0 the strap isn't connected, so we assume
14096                  * it's there.
14097                  */
14098                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14099                 /* WaIgnoreDDIAStrap: skl */
14100                 if (found ||
14101                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14102                         intel_ddi_init(dev, PORT_A);
14103
14104                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14105                  * register */
14106                 found = I915_READ(SFUSE_STRAP);
14107
14108                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14109                         intel_ddi_init(dev, PORT_B);
14110                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14111                         intel_ddi_init(dev, PORT_C);
14112                 if (found & SFUSE_STRAP_DDID_DETECTED)
14113                         intel_ddi_init(dev, PORT_D);
14114         } else if (HAS_PCH_SPLIT(dev)) {
14115                 int found;
14116                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14117
14118                 if (has_edp_a(dev))
14119                         intel_dp_init(dev, DP_A, PORT_A);
14120
14121                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14122                         /* PCH SDVOB multiplex with HDMIB */
14123                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14124                         if (!found)
14125                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14126                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14127                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14128                 }
14129
14130                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14131                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14132
14133                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14134                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14135
14136                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14137                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14138
14139                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14140                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14141         } else if (IS_VALLEYVIEW(dev)) {
14142                 /*
14143                  * The DP_DETECTED bit is the latched state of the DDC
14144                  * SDA pin at boot. However since eDP doesn't require DDC
14145                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14146                  * eDP ports may have been muxed to an alternate function.
14147                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14148                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14149                  * detect eDP ports.
14150                  */
14151                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14152                     !intel_dp_is_edp(dev, PORT_B))
14153                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14154                                         PORT_B);
14155                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14156                     intel_dp_is_edp(dev, PORT_B))
14157                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14158
14159                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14160                     !intel_dp_is_edp(dev, PORT_C))
14161                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14162                                         PORT_C);
14163                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14164                     intel_dp_is_edp(dev, PORT_C))
14165                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14166
14167                 if (IS_CHERRYVIEW(dev)) {
14168                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14169                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14170                                                 PORT_D);
14171                         /* eDP not supported on port D, so don't check VBT */
14172                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14173                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14174                 }
14175
14176                 intel_dsi_init(dev);
14177         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14178                 bool found = false;
14179
14180                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14181                         DRM_DEBUG_KMS("probing SDVOB\n");
14182                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14183                         if (!found && IS_G4X(dev)) {
14184                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14185                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14186                         }
14187
14188                         if (!found && IS_G4X(dev))
14189                                 intel_dp_init(dev, DP_B, PORT_B);
14190                 }
14191
14192                 /* Before G4X SDVOC doesn't have its own detect register */
14193
14194                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14195                         DRM_DEBUG_KMS("probing SDVOC\n");
14196                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14197                 }
14198
14199                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14200
14201                         if (IS_G4X(dev)) {
14202                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14203                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14204                         }
14205                         if (IS_G4X(dev))
14206                                 intel_dp_init(dev, DP_C, PORT_C);
14207                 }
14208
14209                 if (IS_G4X(dev) &&
14210                     (I915_READ(DP_D) & DP_DETECTED))
14211                         intel_dp_init(dev, DP_D, PORT_D);
14212         } else if (IS_GEN2(dev))
14213                 intel_dvo_init(dev);
14214
14215         if (SUPPORTS_TV(dev))
14216                 intel_tv_init(dev);
14217
14218         intel_psr_init(dev);
14219
14220         for_each_intel_encoder(dev, encoder) {
14221                 encoder->base.possible_crtcs = encoder->crtc_mask;
14222                 encoder->base.possible_clones =
14223                         intel_encoder_clones(encoder);
14224         }
14225
14226         intel_init_pch_refclk(dev);
14227
14228         drm_helper_move_panel_connectors_to_head(dev);
14229 }
14230
14231 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14232 {
14233         struct drm_device *dev = fb->dev;
14234         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14235
14236         drm_framebuffer_cleanup(fb);
14237         mutex_lock(&dev->struct_mutex);
14238         WARN_ON(!intel_fb->obj->framebuffer_references--);
14239         drm_gem_object_unreference(&intel_fb->obj->base);
14240         mutex_unlock(&dev->struct_mutex);
14241         kfree(intel_fb);
14242 }
14243
14244 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14245                                                 struct drm_file *file,
14246                                                 unsigned int *handle)
14247 {
14248         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14249         struct drm_i915_gem_object *obj = intel_fb->obj;
14250
14251         return drm_gem_handle_create(file, &obj->base, handle);
14252 }
14253
14254 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14255                                         struct drm_file *file,
14256                                         unsigned flags, unsigned color,
14257                                         struct drm_clip_rect *clips,
14258                                         unsigned num_clips)
14259 {
14260         struct drm_device *dev = fb->dev;
14261         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14262         struct drm_i915_gem_object *obj = intel_fb->obj;
14263
14264         mutex_lock(&dev->struct_mutex);
14265         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14266         mutex_unlock(&dev->struct_mutex);
14267
14268         return 0;
14269 }
14270
14271 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14272         .destroy = intel_user_framebuffer_destroy,
14273         .create_handle = intel_user_framebuffer_create_handle,
14274         .dirty = intel_user_framebuffer_dirty,
14275 };
14276
14277 static
14278 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14279                          uint32_t pixel_format)
14280 {
14281         u32 gen = INTEL_INFO(dev)->gen;
14282
14283         if (gen >= 9) {
14284                 /* "The stride in bytes must not exceed the of the size of 8K
14285                  *  pixels and 32K bytes."
14286                  */
14287                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14288         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14289                 return 32*1024;
14290         } else if (gen >= 4) {
14291                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14292                         return 16*1024;
14293                 else
14294                         return 32*1024;
14295         } else if (gen >= 3) {
14296                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14297                         return 8*1024;
14298                 else
14299                         return 16*1024;
14300         } else {
14301                 /* XXX DSPC is limited to 4k tiled */
14302                 return 8*1024;
14303         }
14304 }
14305
14306 static int intel_framebuffer_init(struct drm_device *dev,
14307                                   struct intel_framebuffer *intel_fb,
14308                                   struct drm_mode_fb_cmd2 *mode_cmd,
14309                                   struct drm_i915_gem_object *obj)
14310 {
14311         unsigned int aligned_height;
14312         int ret;
14313         u32 pitch_limit, stride_alignment;
14314
14315         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14316
14317         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14318                 /* Enforce that fb modifier and tiling mode match, but only for
14319                  * X-tiled. This is needed for FBC. */
14320                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14321                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14322                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14323                         return -EINVAL;
14324                 }
14325         } else {
14326                 if (obj->tiling_mode == I915_TILING_X)
14327                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14328                 else if (obj->tiling_mode == I915_TILING_Y) {
14329                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14330                         return -EINVAL;
14331                 }
14332         }
14333
14334         /* Passed in modifier sanity checking. */
14335         switch (mode_cmd->modifier[0]) {
14336         case I915_FORMAT_MOD_Y_TILED:
14337         case I915_FORMAT_MOD_Yf_TILED:
14338                 if (INTEL_INFO(dev)->gen < 9) {
14339                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14340                                   mode_cmd->modifier[0]);
14341                         return -EINVAL;
14342                 }
14343         case DRM_FORMAT_MOD_NONE:
14344         case I915_FORMAT_MOD_X_TILED:
14345                 break;
14346         default:
14347                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14348                           mode_cmd->modifier[0]);
14349                 return -EINVAL;
14350         }
14351
14352         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14353                                                      mode_cmd->pixel_format);
14354         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14355                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14356                           mode_cmd->pitches[0], stride_alignment);
14357                 return -EINVAL;
14358         }
14359
14360         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14361                                            mode_cmd->pixel_format);
14362         if (mode_cmd->pitches[0] > pitch_limit) {
14363                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14364                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14365                           "tiled" : "linear",
14366                           mode_cmd->pitches[0], pitch_limit);
14367                 return -EINVAL;
14368         }
14369
14370         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14371             mode_cmd->pitches[0] != obj->stride) {
14372                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14373                           mode_cmd->pitches[0], obj->stride);
14374                 return -EINVAL;
14375         }
14376
14377         /* Reject formats not supported by any plane early. */
14378         switch (mode_cmd->pixel_format) {
14379         case DRM_FORMAT_C8:
14380         case DRM_FORMAT_RGB565:
14381         case DRM_FORMAT_XRGB8888:
14382         case DRM_FORMAT_ARGB8888:
14383                 break;
14384         case DRM_FORMAT_XRGB1555:
14385                 if (INTEL_INFO(dev)->gen > 3) {
14386                         DRM_DEBUG("unsupported pixel format: %s\n",
14387                                   drm_get_format_name(mode_cmd->pixel_format));
14388                         return -EINVAL;
14389                 }
14390                 break;
14391         case DRM_FORMAT_ABGR8888:
14392                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14393                         DRM_DEBUG("unsupported pixel format: %s\n",
14394                                   drm_get_format_name(mode_cmd->pixel_format));
14395                         return -EINVAL;
14396                 }
14397                 break;
14398         case DRM_FORMAT_XBGR8888:
14399         case DRM_FORMAT_XRGB2101010:
14400         case DRM_FORMAT_XBGR2101010:
14401                 if (INTEL_INFO(dev)->gen < 4) {
14402                         DRM_DEBUG("unsupported pixel format: %s\n",
14403                                   drm_get_format_name(mode_cmd->pixel_format));
14404                         return -EINVAL;
14405                 }
14406                 break;
14407         case DRM_FORMAT_ABGR2101010:
14408                 if (!IS_VALLEYVIEW(dev)) {
14409                         DRM_DEBUG("unsupported pixel format: %s\n",
14410                                   drm_get_format_name(mode_cmd->pixel_format));
14411                         return -EINVAL;
14412                 }
14413                 break;
14414         case DRM_FORMAT_YUYV:
14415         case DRM_FORMAT_UYVY:
14416         case DRM_FORMAT_YVYU:
14417         case DRM_FORMAT_VYUY:
14418                 if (INTEL_INFO(dev)->gen < 5) {
14419                         DRM_DEBUG("unsupported pixel format: %s\n",
14420                                   drm_get_format_name(mode_cmd->pixel_format));
14421                         return -EINVAL;
14422                 }
14423                 break;
14424         default:
14425                 DRM_DEBUG("unsupported pixel format: %s\n",
14426                           drm_get_format_name(mode_cmd->pixel_format));
14427                 return -EINVAL;
14428         }
14429
14430         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14431         if (mode_cmd->offsets[0] != 0)
14432                 return -EINVAL;
14433
14434         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14435                                                mode_cmd->pixel_format,
14436                                                mode_cmd->modifier[0]);
14437         /* FIXME drm helper for size checks (especially planar formats)? */
14438         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14439                 return -EINVAL;
14440
14441         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14442         intel_fb->obj = obj;
14443         intel_fb->obj->framebuffer_references++;
14444
14445         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14446         if (ret) {
14447                 DRM_ERROR("framebuffer init failed %d\n", ret);
14448                 return ret;
14449         }
14450
14451         return 0;
14452 }
14453
14454 static struct drm_framebuffer *
14455 intel_user_framebuffer_create(struct drm_device *dev,
14456                               struct drm_file *filp,
14457                               struct drm_mode_fb_cmd2 *mode_cmd)
14458 {
14459         struct drm_i915_gem_object *obj;
14460
14461         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14462                                                 mode_cmd->handles[0]));
14463         if (&obj->base == NULL)
14464                 return ERR_PTR(-ENOENT);
14465
14466         return intel_framebuffer_create(dev, mode_cmd, obj);
14467 }
14468
14469 #ifndef CONFIG_DRM_I915_FBDEV
14470 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14471 {
14472 }
14473 #endif
14474
14475 static const struct drm_mode_config_funcs intel_mode_funcs = {
14476         .fb_create = intel_user_framebuffer_create,
14477         .output_poll_changed = intel_fbdev_output_poll_changed,
14478         .atomic_check = intel_atomic_check,
14479         .atomic_commit = intel_atomic_commit,
14480         .atomic_state_alloc = intel_atomic_state_alloc,
14481         .atomic_state_clear = intel_atomic_state_clear,
14482 };
14483
14484 /* Set up chip specific display functions */
14485 static void intel_init_display(struct drm_device *dev)
14486 {
14487         struct drm_i915_private *dev_priv = dev->dev_private;
14488
14489         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14490                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14491         else if (IS_CHERRYVIEW(dev))
14492                 dev_priv->display.find_dpll = chv_find_best_dpll;
14493         else if (IS_VALLEYVIEW(dev))
14494                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14495         else if (IS_PINEVIEW(dev))
14496                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14497         else
14498                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14499
14500         if (INTEL_INFO(dev)->gen >= 9) {
14501                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14502                 dev_priv->display.get_initial_plane_config =
14503                         skylake_get_initial_plane_config;
14504                 dev_priv->display.crtc_compute_clock =
14505                         haswell_crtc_compute_clock;
14506                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14507                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14508                 dev_priv->display.update_primary_plane =
14509                         skylake_update_primary_plane;
14510         } else if (HAS_DDI(dev)) {
14511                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14512                 dev_priv->display.get_initial_plane_config =
14513                         ironlake_get_initial_plane_config;
14514                 dev_priv->display.crtc_compute_clock =
14515                         haswell_crtc_compute_clock;
14516                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14517                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14518                 dev_priv->display.update_primary_plane =
14519                         ironlake_update_primary_plane;
14520         } else if (HAS_PCH_SPLIT(dev)) {
14521                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14522                 dev_priv->display.get_initial_plane_config =
14523                         ironlake_get_initial_plane_config;
14524                 dev_priv->display.crtc_compute_clock =
14525                         ironlake_crtc_compute_clock;
14526                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14527                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14528                 dev_priv->display.update_primary_plane =
14529                         ironlake_update_primary_plane;
14530         } else if (IS_VALLEYVIEW(dev)) {
14531                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14532                 dev_priv->display.get_initial_plane_config =
14533                         i9xx_get_initial_plane_config;
14534                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14535                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14536                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14537                 dev_priv->display.update_primary_plane =
14538                         i9xx_update_primary_plane;
14539         } else {
14540                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14541                 dev_priv->display.get_initial_plane_config =
14542                         i9xx_get_initial_plane_config;
14543                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14544                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14545                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14546                 dev_priv->display.update_primary_plane =
14547                         i9xx_update_primary_plane;
14548         }
14549
14550         /* Returns the core display clock speed */
14551         if (IS_SKYLAKE(dev))
14552                 dev_priv->display.get_display_clock_speed =
14553                         skylake_get_display_clock_speed;
14554         else if (IS_BROXTON(dev))
14555                 dev_priv->display.get_display_clock_speed =
14556                         broxton_get_display_clock_speed;
14557         else if (IS_BROADWELL(dev))
14558                 dev_priv->display.get_display_clock_speed =
14559                         broadwell_get_display_clock_speed;
14560         else if (IS_HASWELL(dev))
14561                 dev_priv->display.get_display_clock_speed =
14562                         haswell_get_display_clock_speed;
14563         else if (IS_VALLEYVIEW(dev))
14564                 dev_priv->display.get_display_clock_speed =
14565                         valleyview_get_display_clock_speed;
14566         else if (IS_GEN5(dev))
14567                 dev_priv->display.get_display_clock_speed =
14568                         ilk_get_display_clock_speed;
14569         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14570                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14571                 dev_priv->display.get_display_clock_speed =
14572                         i945_get_display_clock_speed;
14573         else if (IS_GM45(dev))
14574                 dev_priv->display.get_display_clock_speed =
14575                         gm45_get_display_clock_speed;
14576         else if (IS_CRESTLINE(dev))
14577                 dev_priv->display.get_display_clock_speed =
14578                         i965gm_get_display_clock_speed;
14579         else if (IS_PINEVIEW(dev))
14580                 dev_priv->display.get_display_clock_speed =
14581                         pnv_get_display_clock_speed;
14582         else if (IS_G33(dev) || IS_G4X(dev))
14583                 dev_priv->display.get_display_clock_speed =
14584                         g33_get_display_clock_speed;
14585         else if (IS_I915G(dev))
14586                 dev_priv->display.get_display_clock_speed =
14587                         i915_get_display_clock_speed;
14588         else if (IS_I945GM(dev) || IS_845G(dev))
14589                 dev_priv->display.get_display_clock_speed =
14590                         i9xx_misc_get_display_clock_speed;
14591         else if (IS_PINEVIEW(dev))
14592                 dev_priv->display.get_display_clock_speed =
14593                         pnv_get_display_clock_speed;
14594         else if (IS_I915GM(dev))
14595                 dev_priv->display.get_display_clock_speed =
14596                         i915gm_get_display_clock_speed;
14597         else if (IS_I865G(dev))
14598                 dev_priv->display.get_display_clock_speed =
14599                         i865_get_display_clock_speed;
14600         else if (IS_I85X(dev))
14601                 dev_priv->display.get_display_clock_speed =
14602                         i85x_get_display_clock_speed;
14603         else { /* 830 */
14604                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14605                 dev_priv->display.get_display_clock_speed =
14606                         i830_get_display_clock_speed;
14607         }
14608
14609         if (IS_GEN5(dev)) {
14610                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14611         } else if (IS_GEN6(dev)) {
14612                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14613         } else if (IS_IVYBRIDGE(dev)) {
14614                 /* FIXME: detect B0+ stepping and use auto training */
14615                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14616         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14617                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14618                 if (IS_BROADWELL(dev)) {
14619                         dev_priv->display.modeset_commit_cdclk =
14620                                 broadwell_modeset_commit_cdclk;
14621                         dev_priv->display.modeset_calc_cdclk =
14622                                 broadwell_modeset_calc_cdclk;
14623                 }
14624         } else if (IS_VALLEYVIEW(dev)) {
14625                 dev_priv->display.modeset_commit_cdclk =
14626                         valleyview_modeset_commit_cdclk;
14627                 dev_priv->display.modeset_calc_cdclk =
14628                         valleyview_modeset_calc_cdclk;
14629         } else if (IS_BROXTON(dev)) {
14630                 dev_priv->display.modeset_commit_cdclk =
14631                         broxton_modeset_commit_cdclk;
14632                 dev_priv->display.modeset_calc_cdclk =
14633                         broxton_modeset_calc_cdclk;
14634         }
14635
14636         switch (INTEL_INFO(dev)->gen) {
14637         case 2:
14638                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14639                 break;
14640
14641         case 3:
14642                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14643                 break;
14644
14645         case 4:
14646         case 5:
14647                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14648                 break;
14649
14650         case 6:
14651                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14652                 break;
14653         case 7:
14654         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14655                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14656                 break;
14657         case 9:
14658                 /* Drop through - unsupported since execlist only. */
14659         default:
14660                 /* Default just returns -ENODEV to indicate unsupported */
14661                 dev_priv->display.queue_flip = intel_default_queue_flip;
14662         }
14663
14664         intel_panel_init_backlight_funcs(dev);
14665
14666         mutex_init(&dev_priv->pps_mutex);
14667 }
14668
14669 /*
14670  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14671  * resume, or other times.  This quirk makes sure that's the case for
14672  * affected systems.
14673  */
14674 static void quirk_pipea_force(struct drm_device *dev)
14675 {
14676         struct drm_i915_private *dev_priv = dev->dev_private;
14677
14678         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14679         DRM_INFO("applying pipe a force quirk\n");
14680 }
14681
14682 static void quirk_pipeb_force(struct drm_device *dev)
14683 {
14684         struct drm_i915_private *dev_priv = dev->dev_private;
14685
14686         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14687         DRM_INFO("applying pipe b force quirk\n");
14688 }
14689
14690 /*
14691  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14692  */
14693 static void quirk_ssc_force_disable(struct drm_device *dev)
14694 {
14695         struct drm_i915_private *dev_priv = dev->dev_private;
14696         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14697         DRM_INFO("applying lvds SSC disable quirk\n");
14698 }
14699
14700 /*
14701  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14702  * brightness value
14703  */
14704 static void quirk_invert_brightness(struct drm_device *dev)
14705 {
14706         struct drm_i915_private *dev_priv = dev->dev_private;
14707         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14708         DRM_INFO("applying inverted panel brightness quirk\n");
14709 }
14710
14711 /* Some VBT's incorrectly indicate no backlight is present */
14712 static void quirk_backlight_present(struct drm_device *dev)
14713 {
14714         struct drm_i915_private *dev_priv = dev->dev_private;
14715         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14716         DRM_INFO("applying backlight present quirk\n");
14717 }
14718
14719 struct intel_quirk {
14720         int device;
14721         int subsystem_vendor;
14722         int subsystem_device;
14723         void (*hook)(struct drm_device *dev);
14724 };
14725
14726 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14727 struct intel_dmi_quirk {
14728         void (*hook)(struct drm_device *dev);
14729         const struct dmi_system_id (*dmi_id_list)[];
14730 };
14731
14732 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14733 {
14734         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14735         return 1;
14736 }
14737
14738 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14739         {
14740                 .dmi_id_list = &(const struct dmi_system_id[]) {
14741                         {
14742                                 .callback = intel_dmi_reverse_brightness,
14743                                 .ident = "NCR Corporation",
14744                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14745                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14746                                 },
14747                         },
14748                         { }  /* terminating entry */
14749                 },
14750                 .hook = quirk_invert_brightness,
14751         },
14752 };
14753
14754 static struct intel_quirk intel_quirks[] = {
14755         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14756         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14757
14758         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14759         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14760
14761         /* 830 needs to leave pipe A & dpll A up */
14762         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14763
14764         /* 830 needs to leave pipe B & dpll B up */
14765         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14766
14767         /* Lenovo U160 cannot use SSC on LVDS */
14768         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14769
14770         /* Sony Vaio Y cannot use SSC on LVDS */
14771         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14772
14773         /* Acer Aspire 5734Z must invert backlight brightness */
14774         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14775
14776         /* Acer/eMachines G725 */
14777         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14778
14779         /* Acer/eMachines e725 */
14780         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14781
14782         /* Acer/Packard Bell NCL20 */
14783         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14784
14785         /* Acer Aspire 4736Z */
14786         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14787
14788         /* Acer Aspire 5336 */
14789         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14790
14791         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14792         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14793
14794         /* Acer C720 Chromebook (Core i3 4005U) */
14795         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14796
14797         /* Apple Macbook 2,1 (Core 2 T7400) */
14798         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14799
14800         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14801         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14802
14803         /* HP Chromebook 14 (Celeron 2955U) */
14804         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14805
14806         /* Dell Chromebook 11 */
14807         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14808 };
14809
14810 static void intel_init_quirks(struct drm_device *dev)
14811 {
14812         struct pci_dev *d = dev->pdev;
14813         int i;
14814
14815         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14816                 struct intel_quirk *q = &intel_quirks[i];
14817
14818                 if (d->device == q->device &&
14819                     (d->subsystem_vendor == q->subsystem_vendor ||
14820                      q->subsystem_vendor == PCI_ANY_ID) &&
14821                     (d->subsystem_device == q->subsystem_device ||
14822                      q->subsystem_device == PCI_ANY_ID))
14823                         q->hook(dev);
14824         }
14825         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14826                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14827                         intel_dmi_quirks[i].hook(dev);
14828         }
14829 }
14830
14831 /* Disable the VGA plane that we never use */
14832 static void i915_disable_vga(struct drm_device *dev)
14833 {
14834         struct drm_i915_private *dev_priv = dev->dev_private;
14835         u8 sr1;
14836         u32 vga_reg = i915_vgacntrl_reg(dev);
14837
14838         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14839         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14840         outb(SR01, VGA_SR_INDEX);
14841         sr1 = inb(VGA_SR_DATA);
14842         outb(sr1 | 1<<5, VGA_SR_DATA);
14843         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14844         udelay(300);
14845
14846         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14847         POSTING_READ(vga_reg);
14848 }
14849
14850 void intel_modeset_init_hw(struct drm_device *dev)
14851 {
14852         intel_update_cdclk(dev);
14853         intel_prepare_ddi(dev);
14854         intel_init_clock_gating(dev);
14855         intel_enable_gt_powersave(dev);
14856 }
14857
14858 void intel_modeset_init(struct drm_device *dev)
14859 {
14860         struct drm_i915_private *dev_priv = dev->dev_private;
14861         int sprite, ret;
14862         enum pipe pipe;
14863         struct intel_crtc *crtc;
14864
14865         drm_mode_config_init(dev);
14866
14867         dev->mode_config.min_width = 0;
14868         dev->mode_config.min_height = 0;
14869
14870         dev->mode_config.preferred_depth = 24;
14871         dev->mode_config.prefer_shadow = 1;
14872
14873         dev->mode_config.allow_fb_modifiers = true;
14874
14875         dev->mode_config.funcs = &intel_mode_funcs;
14876
14877         intel_init_quirks(dev);
14878
14879         intel_init_pm(dev);
14880
14881         if (INTEL_INFO(dev)->num_pipes == 0)
14882                 return;
14883
14884         intel_init_display(dev);
14885         intel_init_audio(dev);
14886
14887         if (IS_GEN2(dev)) {
14888                 dev->mode_config.max_width = 2048;
14889                 dev->mode_config.max_height = 2048;
14890         } else if (IS_GEN3(dev)) {
14891                 dev->mode_config.max_width = 4096;
14892                 dev->mode_config.max_height = 4096;
14893         } else {
14894                 dev->mode_config.max_width = 8192;
14895                 dev->mode_config.max_height = 8192;
14896         }
14897
14898         if (IS_845G(dev) || IS_I865G(dev)) {
14899                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14900                 dev->mode_config.cursor_height = 1023;
14901         } else if (IS_GEN2(dev)) {
14902                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14903                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14904         } else {
14905                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14906                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14907         }
14908
14909         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14910
14911         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14912                       INTEL_INFO(dev)->num_pipes,
14913                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14914
14915         for_each_pipe(dev_priv, pipe) {
14916                 intel_crtc_init(dev, pipe);
14917                 for_each_sprite(dev_priv, pipe, sprite) {
14918                         ret = intel_plane_init(dev, pipe, sprite);
14919                         if (ret)
14920                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14921                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14922                 }
14923         }
14924
14925         intel_init_dpio(dev);
14926
14927         intel_shared_dpll_init(dev);
14928
14929         /* Just disable it once at startup */
14930         i915_disable_vga(dev);
14931         intel_setup_outputs(dev);
14932
14933         /* Just in case the BIOS is doing something questionable. */
14934         intel_fbc_disable(dev_priv);
14935
14936         drm_modeset_lock_all(dev);
14937         intel_modeset_setup_hw_state(dev);
14938         drm_modeset_unlock_all(dev);
14939
14940         for_each_intel_crtc(dev, crtc) {
14941                 struct intel_initial_plane_config plane_config = {};
14942
14943                 if (!crtc->active)
14944                         continue;
14945
14946                 /*
14947                  * Note that reserving the BIOS fb up front prevents us
14948                  * from stuffing other stolen allocations like the ring
14949                  * on top.  This prevents some ugliness at boot time, and
14950                  * can even allow for smooth boot transitions if the BIOS
14951                  * fb is large enough for the active pipe configuration.
14952                  */
14953                 dev_priv->display.get_initial_plane_config(crtc,
14954                                                            &plane_config);
14955
14956                 /*
14957                  * If the fb is shared between multiple heads, we'll
14958                  * just get the first one.
14959                  */
14960                 intel_find_initial_plane_obj(crtc, &plane_config);
14961         }
14962 }
14963
14964 static void intel_enable_pipe_a(struct drm_device *dev)
14965 {
14966         struct intel_connector *connector;
14967         struct drm_connector *crt = NULL;
14968         struct intel_load_detect_pipe load_detect_temp;
14969         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14970
14971         /* We can't just switch on the pipe A, we need to set things up with a
14972          * proper mode and output configuration. As a gross hack, enable pipe A
14973          * by enabling the load detect pipe once. */
14974         for_each_intel_connector(dev, connector) {
14975                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14976                         crt = &connector->base;
14977                         break;
14978                 }
14979         }
14980
14981         if (!crt)
14982                 return;
14983
14984         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14985                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14986 }
14987
14988 static bool
14989 intel_check_plane_mapping(struct intel_crtc *crtc)
14990 {
14991         struct drm_device *dev = crtc->base.dev;
14992         struct drm_i915_private *dev_priv = dev->dev_private;
14993         u32 reg, val;
14994
14995         if (INTEL_INFO(dev)->num_pipes == 1)
14996                 return true;
14997
14998         reg = DSPCNTR(!crtc->plane);
14999         val = I915_READ(reg);
15000
15001         if ((val & DISPLAY_PLANE_ENABLE) &&
15002             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15003                 return false;
15004
15005         return true;
15006 }
15007
15008 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15009 {
15010         struct drm_device *dev = crtc->base.dev;
15011         struct drm_i915_private *dev_priv = dev->dev_private;
15012         struct intel_encoder *encoder;
15013         u32 reg;
15014         bool enable;
15015
15016         /* Clear any frame start delays used for debugging left by the BIOS */
15017         reg = PIPECONF(crtc->config->cpu_transcoder);
15018         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15019
15020         /* restore vblank interrupts to correct state */
15021         drm_crtc_vblank_reset(&crtc->base);
15022         if (crtc->active) {
15023                 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15024                 update_scanline_offset(crtc);
15025                 drm_crtc_vblank_on(&crtc->base);
15026         }
15027
15028         /* We need to sanitize the plane -> pipe mapping first because this will
15029          * disable the crtc (and hence change the state) if it is wrong. Note
15030          * that gen4+ has a fixed plane -> pipe mapping.  */
15031         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15032                 bool plane;
15033
15034                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15035                               crtc->base.base.id);
15036
15037                 /* Pipe has the wrong plane attached and the plane is active.
15038                  * Temporarily change the plane mapping and disable everything
15039                  * ...  */
15040                 plane = crtc->plane;
15041                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15042                 crtc->plane = !plane;
15043                 intel_crtc_disable_noatomic(&crtc->base);
15044                 crtc->plane = plane;
15045         }
15046
15047         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15048             crtc->pipe == PIPE_A && !crtc->active) {
15049                 /* BIOS forgot to enable pipe A, this mostly happens after
15050                  * resume. Force-enable the pipe to fix this, the update_dpms
15051                  * call below we restore the pipe to the right state, but leave
15052                  * the required bits on. */
15053                 intel_enable_pipe_a(dev);
15054         }
15055
15056         /* Adjust the state of the output pipe according to whether we
15057          * have active connectors/encoders. */
15058         enable = false;
15059         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15060                 enable |= encoder->connectors_active;
15061
15062         if (!enable)
15063                 intel_crtc_disable_noatomic(&crtc->base);
15064
15065         if (crtc->active != crtc->base.state->active) {
15066
15067                 /* This can happen either due to bugs in the get_hw_state
15068                  * functions or because of calls to intel_crtc_disable_noatomic,
15069                  * or because the pipe is force-enabled due to the
15070                  * pipe A quirk. */
15071                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15072                               crtc->base.base.id,
15073                               crtc->base.state->enable ? "enabled" : "disabled",
15074                               crtc->active ? "enabled" : "disabled");
15075
15076                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15077                 crtc->base.state->active = crtc->active;
15078                 crtc->base.enabled = crtc->active;
15079
15080                 /* Because we only establish the connector -> encoder ->
15081                  * crtc links if something is active, this means the
15082                  * crtc is now deactivated. Break the links. connector
15083                  * -> encoder links are only establish when things are
15084                  *  actually up, hence no need to break them. */
15085                 WARN_ON(crtc->active);
15086
15087                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15088                         WARN_ON(encoder->connectors_active);
15089                         encoder->base.crtc = NULL;
15090                 }
15091         }
15092
15093         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15094                 /*
15095                  * We start out with underrun reporting disabled to avoid races.
15096                  * For correct bookkeeping mark this on active crtcs.
15097                  *
15098                  * Also on gmch platforms we dont have any hardware bits to
15099                  * disable the underrun reporting. Which means we need to start
15100                  * out with underrun reporting disabled also on inactive pipes,
15101                  * since otherwise we'll complain about the garbage we read when
15102                  * e.g. coming up after runtime pm.
15103                  *
15104                  * No protection against concurrent access is required - at
15105                  * worst a fifo underrun happens which also sets this to false.
15106                  */
15107                 crtc->cpu_fifo_underrun_disabled = true;
15108                 crtc->pch_fifo_underrun_disabled = true;
15109         }
15110 }
15111
15112 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15113 {
15114         struct intel_connector *connector;
15115         struct drm_device *dev = encoder->base.dev;
15116
15117         /* We need to check both for a crtc link (meaning that the
15118          * encoder is active and trying to read from a pipe) and the
15119          * pipe itself being active. */
15120         bool has_active_crtc = encoder->base.crtc &&
15121                 to_intel_crtc(encoder->base.crtc)->active;
15122
15123         if (encoder->connectors_active && !has_active_crtc) {
15124                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15125                               encoder->base.base.id,
15126                               encoder->base.name);
15127
15128                 /* Connector is active, but has no active pipe. This is
15129                  * fallout from our resume register restoring. Disable
15130                  * the encoder manually again. */
15131                 if (encoder->base.crtc) {
15132                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15133                                       encoder->base.base.id,
15134                                       encoder->base.name);
15135                         encoder->disable(encoder);
15136                         if (encoder->post_disable)
15137                                 encoder->post_disable(encoder);
15138                 }
15139                 encoder->base.crtc = NULL;
15140                 encoder->connectors_active = false;
15141
15142                 /* Inconsistent output/port/pipe state happens presumably due to
15143                  * a bug in one of the get_hw_state functions. Or someplace else
15144                  * in our code, like the register restore mess on resume. Clamp
15145                  * things to off as a safer default. */
15146                 for_each_intel_connector(dev, connector) {
15147                         if (connector->encoder != encoder)
15148                                 continue;
15149                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15150                         connector->base.encoder = NULL;
15151                 }
15152         }
15153         /* Enabled encoders without active connectors will be fixed in
15154          * the crtc fixup. */
15155 }
15156
15157 void i915_redisable_vga_power_on(struct drm_device *dev)
15158 {
15159         struct drm_i915_private *dev_priv = dev->dev_private;
15160         u32 vga_reg = i915_vgacntrl_reg(dev);
15161
15162         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15163                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15164                 i915_disable_vga(dev);
15165         }
15166 }
15167
15168 void i915_redisable_vga(struct drm_device *dev)
15169 {
15170         struct drm_i915_private *dev_priv = dev->dev_private;
15171
15172         /* This function can be called both from intel_modeset_setup_hw_state or
15173          * at a very early point in our resume sequence, where the power well
15174          * structures are not yet restored. Since this function is at a very
15175          * paranoid "someone might have enabled VGA while we were not looking"
15176          * level, just check if the power well is enabled instead of trying to
15177          * follow the "don't touch the power well if we don't need it" policy
15178          * the rest of the driver uses. */
15179         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15180                 return;
15181
15182         i915_redisable_vga_power_on(dev);
15183 }
15184
15185 static bool primary_get_hw_state(struct intel_crtc *crtc)
15186 {
15187         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15188
15189         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15190 }
15191
15192 static void readout_plane_state(struct intel_crtc *crtc,
15193                                 struct intel_crtc_state *crtc_state)
15194 {
15195         struct intel_plane *p;
15196         struct intel_plane_state *plane_state;
15197         bool active = crtc_state->base.active;
15198
15199         for_each_intel_plane(crtc->base.dev, p) {
15200                 if (crtc->pipe != p->pipe)
15201                         continue;
15202
15203                 plane_state = to_intel_plane_state(p->base.state);
15204
15205                 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15206                         plane_state->visible = primary_get_hw_state(crtc);
15207                 else {
15208                         if (active)
15209                                 p->disable_plane(&p->base, &crtc->base);
15210
15211                         plane_state->visible = false;
15212                 }
15213         }
15214 }
15215
15216 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15217 {
15218         struct drm_i915_private *dev_priv = dev->dev_private;
15219         enum pipe pipe;
15220         struct intel_crtc *crtc;
15221         struct intel_encoder *encoder;
15222         struct intel_connector *connector;
15223         int i;
15224
15225         for_each_intel_crtc(dev, crtc) {
15226                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15227                 memset(crtc->config, 0, sizeof(*crtc->config));
15228                 crtc->config->base.crtc = &crtc->base;
15229
15230                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15231                                                                  crtc->config);
15232
15233                 crtc->base.state->active = crtc->active;
15234                 crtc->base.enabled = crtc->active;
15235
15236                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15237                 if (crtc->base.state->active) {
15238                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15239                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15240                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15241
15242                         /*
15243                          * The initial mode needs to be set in order to keep
15244                          * the atomic core happy. It wants a valid mode if the
15245                          * crtc's enabled, so we do the above call.
15246                          *
15247                          * At this point some state updated by the connectors
15248                          * in their ->detect() callback has not run yet, so
15249                          * no recalculation can be done yet.
15250                          *
15251                          * Even if we could do a recalculation and modeset
15252                          * right now it would cause a double modeset if
15253                          * fbdev or userspace chooses a different initial mode.
15254                          *
15255                          * If that happens, someone indicated they wanted a
15256                          * mode change, which means it's safe to do a full
15257                          * recalculation.
15258                          */
15259                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15260                 }
15261
15262                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15263                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15264
15265                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15266                               crtc->base.base.id,
15267                               crtc->active ? "enabled" : "disabled");
15268         }
15269
15270         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15271                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15272
15273                 pll->on = pll->get_hw_state(dev_priv, pll,
15274                                             &pll->config.hw_state);
15275                 pll->active = 0;
15276                 pll->config.crtc_mask = 0;
15277                 for_each_intel_crtc(dev, crtc) {
15278                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15279                                 pll->active++;
15280                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15281                         }
15282                 }
15283
15284                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15285                               pll->name, pll->config.crtc_mask, pll->on);
15286
15287                 if (pll->config.crtc_mask)
15288                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15289         }
15290
15291         for_each_intel_encoder(dev, encoder) {
15292                 pipe = 0;
15293
15294                 if (encoder->get_hw_state(encoder, &pipe)) {
15295                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15296                         encoder->base.crtc = &crtc->base;
15297                         encoder->get_config(encoder, crtc->config);
15298                 } else {
15299                         encoder->base.crtc = NULL;
15300                 }
15301
15302                 encoder->connectors_active = false;
15303                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15304                               encoder->base.base.id,
15305                               encoder->base.name,
15306                               encoder->base.crtc ? "enabled" : "disabled",
15307                               pipe_name(pipe));
15308         }
15309
15310         for_each_intel_connector(dev, connector) {
15311                 if (connector->get_hw_state(connector)) {
15312                         connector->base.dpms = DRM_MODE_DPMS_ON;
15313                         connector->encoder->connectors_active = true;
15314                         connector->base.encoder = &connector->encoder->base;
15315                 } else {
15316                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15317                         connector->base.encoder = NULL;
15318                 }
15319                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15320                               connector->base.base.id,
15321                               connector->base.name,
15322                               connector->base.encoder ? "enabled" : "disabled");
15323         }
15324 }
15325
15326 /* Scan out the current hw modeset state,
15327  * and sanitizes it to the current state
15328  */
15329 static void
15330 intel_modeset_setup_hw_state(struct drm_device *dev)
15331 {
15332         struct drm_i915_private *dev_priv = dev->dev_private;
15333         enum pipe pipe;
15334         struct intel_crtc *crtc;
15335         struct intel_encoder *encoder;
15336         int i;
15337
15338         intel_modeset_readout_hw_state(dev);
15339
15340         /* HW state is read out, now we need to sanitize this mess. */
15341         for_each_intel_encoder(dev, encoder) {
15342                 intel_sanitize_encoder(encoder);
15343         }
15344
15345         for_each_pipe(dev_priv, pipe) {
15346                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15347                 intel_sanitize_crtc(crtc);
15348                 intel_dump_pipe_config(crtc, crtc->config,
15349                                        "[setup_hw_state]");
15350         }
15351
15352         intel_modeset_update_connector_atomic_state(dev);
15353
15354         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15355                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15356
15357                 if (!pll->on || pll->active)
15358                         continue;
15359
15360                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15361
15362                 pll->disable(dev_priv, pll);
15363                 pll->on = false;
15364         }
15365
15366         if (IS_VALLEYVIEW(dev))
15367                 vlv_wm_get_hw_state(dev);
15368         else if (IS_GEN9(dev))
15369                 skl_wm_get_hw_state(dev);
15370         else if (HAS_PCH_SPLIT(dev))
15371                 ilk_wm_get_hw_state(dev);
15372
15373         for_each_intel_crtc(dev, crtc) {
15374                 unsigned long put_domains;
15375
15376                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15377                 if (WARN_ON(put_domains))
15378                         modeset_put_power_domains(dev_priv, put_domains);
15379         }
15380         intel_display_set_init_power(dev_priv, false);
15381 }
15382
15383 void intel_display_resume(struct drm_device *dev)
15384 {
15385         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15386         struct intel_connector *conn;
15387         struct intel_plane *plane;
15388         struct drm_crtc *crtc;
15389         int ret;
15390
15391         if (!state)
15392                 return;
15393
15394         state->acquire_ctx = dev->mode_config.acquire_ctx;
15395
15396         /* preserve complete old state, including dpll */
15397         intel_atomic_get_shared_dpll_state(state);
15398
15399         for_each_crtc(dev, crtc) {
15400                 struct drm_crtc_state *crtc_state =
15401                         drm_atomic_get_crtc_state(state, crtc);
15402
15403                 ret = PTR_ERR_OR_ZERO(crtc_state);
15404                 if (ret)
15405                         goto err;
15406
15407                 /* force a restore */
15408                 crtc_state->mode_changed = true;
15409         }
15410
15411         for_each_intel_plane(dev, plane) {
15412                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15413                 if (ret)
15414                         goto err;
15415         }
15416
15417         for_each_intel_connector(dev, conn) {
15418                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15419                 if (ret)
15420                         goto err;
15421         }
15422
15423         intel_modeset_setup_hw_state(dev);
15424
15425         i915_redisable_vga(dev);
15426         ret = drm_atomic_commit(state);
15427         if (!ret)
15428                 return;
15429
15430 err:
15431         DRM_ERROR("Restoring old state failed with %i\n", ret);
15432         drm_atomic_state_free(state);
15433 }
15434
15435 void intel_modeset_gem_init(struct drm_device *dev)
15436 {
15437         struct drm_i915_private *dev_priv = dev->dev_private;
15438         struct drm_crtc *c;
15439         struct drm_i915_gem_object *obj;
15440         int ret;
15441
15442         mutex_lock(&dev->struct_mutex);
15443         intel_init_gt_powersave(dev);
15444         mutex_unlock(&dev->struct_mutex);
15445
15446         /*
15447          * There may be no VBT; and if the BIOS enabled SSC we can
15448          * just keep using it to avoid unnecessary flicker.  Whereas if the
15449          * BIOS isn't using it, don't assume it will work even if the VBT
15450          * indicates as much.
15451          */
15452         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15453                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15454                                                 DREF_SSC1_ENABLE);
15455
15456         intel_modeset_init_hw(dev);
15457
15458         intel_setup_overlay(dev);
15459
15460         /*
15461          * Make sure any fbs we allocated at startup are properly
15462          * pinned & fenced.  When we do the allocation it's too early
15463          * for this.
15464          */
15465         for_each_crtc(dev, c) {
15466                 obj = intel_fb_obj(c->primary->fb);
15467                 if (obj == NULL)
15468                         continue;
15469
15470                 mutex_lock(&dev->struct_mutex);
15471                 ret = intel_pin_and_fence_fb_obj(c->primary,
15472                                                  c->primary->fb,
15473                                                  c->primary->state,
15474                                                  NULL, NULL);
15475                 mutex_unlock(&dev->struct_mutex);
15476                 if (ret) {
15477                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15478                                   to_intel_crtc(c)->pipe);
15479                         drm_framebuffer_unreference(c->primary->fb);
15480                         c->primary->fb = NULL;
15481                         c->primary->crtc = c->primary->state->crtc = NULL;
15482                         update_state_fb(c->primary);
15483                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15484                 }
15485         }
15486
15487         intel_backlight_register(dev);
15488 }
15489
15490 void intel_connector_unregister(struct intel_connector *intel_connector)
15491 {
15492         struct drm_connector *connector = &intel_connector->base;
15493
15494         intel_panel_destroy_backlight(connector);
15495         drm_connector_unregister(connector);
15496 }
15497
15498 void intel_modeset_cleanup(struct drm_device *dev)
15499 {
15500         struct drm_i915_private *dev_priv = dev->dev_private;
15501         struct drm_connector *connector;
15502
15503         intel_disable_gt_powersave(dev);
15504
15505         intel_backlight_unregister(dev);
15506
15507         /*
15508          * Interrupts and polling as the first thing to avoid creating havoc.
15509          * Too much stuff here (turning of connectors, ...) would
15510          * experience fancy races otherwise.
15511          */
15512         intel_irq_uninstall(dev_priv);
15513
15514         /*
15515          * Due to the hpd irq storm handling the hotplug work can re-arm the
15516          * poll handlers. Hence disable polling after hpd handling is shut down.
15517          */
15518         drm_kms_helper_poll_fini(dev);
15519
15520         intel_unregister_dsm_handler();
15521
15522         intel_fbc_disable(dev_priv);
15523
15524         /* flush any delayed tasks or pending work */
15525         flush_scheduled_work();
15526
15527         /* destroy the backlight and sysfs files before encoders/connectors */
15528         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15529                 struct intel_connector *intel_connector;
15530
15531                 intel_connector = to_intel_connector(connector);
15532                 intel_connector->unregister(intel_connector);
15533         }
15534
15535         drm_mode_config_cleanup(dev);
15536
15537         intel_cleanup_overlay(dev);
15538
15539         mutex_lock(&dev->struct_mutex);
15540         intel_cleanup_gt_powersave(dev);
15541         mutex_unlock(&dev->struct_mutex);
15542 }
15543
15544 /*
15545  * Return which encoder is currently attached for connector.
15546  */
15547 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15548 {
15549         return &intel_attached_encoder(connector)->base;
15550 }
15551
15552 void intel_connector_attach_encoder(struct intel_connector *connector,
15553                                     struct intel_encoder *encoder)
15554 {
15555         connector->encoder = encoder;
15556         drm_mode_connector_attach_encoder(&connector->base,
15557                                           &encoder->base);
15558 }
15559
15560 /*
15561  * set vga decode state - true == enable VGA decode
15562  */
15563 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15564 {
15565         struct drm_i915_private *dev_priv = dev->dev_private;
15566         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15567         u16 gmch_ctrl;
15568
15569         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15570                 DRM_ERROR("failed to read control word\n");
15571                 return -EIO;
15572         }
15573
15574         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15575                 return 0;
15576
15577         if (state)
15578                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15579         else
15580                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15581
15582         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15583                 DRM_ERROR("failed to write control word\n");
15584                 return -EIO;
15585         }
15586
15587         return 0;
15588 }
15589
15590 struct intel_display_error_state {
15591
15592         u32 power_well_driver;
15593
15594         int num_transcoders;
15595
15596         struct intel_cursor_error_state {
15597                 u32 control;
15598                 u32 position;
15599                 u32 base;
15600                 u32 size;
15601         } cursor[I915_MAX_PIPES];
15602
15603         struct intel_pipe_error_state {
15604                 bool power_domain_on;
15605                 u32 source;
15606                 u32 stat;
15607         } pipe[I915_MAX_PIPES];
15608
15609         struct intel_plane_error_state {
15610                 u32 control;
15611                 u32 stride;
15612                 u32 size;
15613                 u32 pos;
15614                 u32 addr;
15615                 u32 surface;
15616                 u32 tile_offset;
15617         } plane[I915_MAX_PIPES];
15618
15619         struct intel_transcoder_error_state {
15620                 bool power_domain_on;
15621                 enum transcoder cpu_transcoder;
15622
15623                 u32 conf;
15624
15625                 u32 htotal;
15626                 u32 hblank;
15627                 u32 hsync;
15628                 u32 vtotal;
15629                 u32 vblank;
15630                 u32 vsync;
15631         } transcoder[4];
15632 };
15633
15634 struct intel_display_error_state *
15635 intel_display_capture_error_state(struct drm_device *dev)
15636 {
15637         struct drm_i915_private *dev_priv = dev->dev_private;
15638         struct intel_display_error_state *error;
15639         int transcoders[] = {
15640                 TRANSCODER_A,
15641                 TRANSCODER_B,
15642                 TRANSCODER_C,
15643                 TRANSCODER_EDP,
15644         };
15645         int i;
15646
15647         if (INTEL_INFO(dev)->num_pipes == 0)
15648                 return NULL;
15649
15650         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15651         if (error == NULL)
15652                 return NULL;
15653
15654         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15655                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15656
15657         for_each_pipe(dev_priv, i) {
15658                 error->pipe[i].power_domain_on =
15659                         __intel_display_power_is_enabled(dev_priv,
15660                                                          POWER_DOMAIN_PIPE(i));
15661                 if (!error->pipe[i].power_domain_on)
15662                         continue;
15663
15664                 error->cursor[i].control = I915_READ(CURCNTR(i));
15665                 error->cursor[i].position = I915_READ(CURPOS(i));
15666                 error->cursor[i].base = I915_READ(CURBASE(i));
15667
15668                 error->plane[i].control = I915_READ(DSPCNTR(i));
15669                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15670                 if (INTEL_INFO(dev)->gen <= 3) {
15671                         error->plane[i].size = I915_READ(DSPSIZE(i));
15672                         error->plane[i].pos = I915_READ(DSPPOS(i));
15673                 }
15674                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15675                         error->plane[i].addr = I915_READ(DSPADDR(i));
15676                 if (INTEL_INFO(dev)->gen >= 4) {
15677                         error->plane[i].surface = I915_READ(DSPSURF(i));
15678                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15679                 }
15680
15681                 error->pipe[i].source = I915_READ(PIPESRC(i));
15682
15683                 if (HAS_GMCH_DISPLAY(dev))
15684                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15685         }
15686
15687         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15688         if (HAS_DDI(dev_priv->dev))
15689                 error->num_transcoders++; /* Account for eDP. */
15690
15691         for (i = 0; i < error->num_transcoders; i++) {
15692                 enum transcoder cpu_transcoder = transcoders[i];
15693
15694                 error->transcoder[i].power_domain_on =
15695                         __intel_display_power_is_enabled(dev_priv,
15696                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15697                 if (!error->transcoder[i].power_domain_on)
15698                         continue;
15699
15700                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15701
15702                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15703                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15704                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15705                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15706                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15707                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15708                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15709         }
15710
15711         return error;
15712 }
15713
15714 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15715
15716 void
15717 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15718                                 struct drm_device *dev,
15719                                 struct intel_display_error_state *error)
15720 {
15721         struct drm_i915_private *dev_priv = dev->dev_private;
15722         int i;
15723
15724         if (!error)
15725                 return;
15726
15727         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15728         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15729                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15730                            error->power_well_driver);
15731         for_each_pipe(dev_priv, i) {
15732                 err_printf(m, "Pipe [%d]:\n", i);
15733                 err_printf(m, "  Power: %s\n",
15734                            error->pipe[i].power_domain_on ? "on" : "off");
15735                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15736                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15737
15738                 err_printf(m, "Plane [%d]:\n", i);
15739                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15740                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15741                 if (INTEL_INFO(dev)->gen <= 3) {
15742                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15743                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15744                 }
15745                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15746                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15747                 if (INTEL_INFO(dev)->gen >= 4) {
15748                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15749                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15750                 }
15751
15752                 err_printf(m, "Cursor [%d]:\n", i);
15753                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15754                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15755                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15756         }
15757
15758         for (i = 0; i < error->num_transcoders; i++) {
15759                 err_printf(m, "CPU transcoder: %c\n",
15760                            transcoder_name(error->transcoder[i].cpu_transcoder));
15761                 err_printf(m, "  Power: %s\n",
15762                            error->transcoder[i].power_domain_on ? "on" : "off");
15763                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15764                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15765                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15766                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15767                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15768                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15769                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15770         }
15771 }
15772
15773 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15774 {
15775         struct intel_crtc *crtc;
15776
15777         for_each_intel_crtc(dev, crtc) {
15778                 struct intel_unpin_work *work;
15779
15780                 spin_lock_irq(&dev->event_lock);
15781
15782                 work = crtc->unpin_work;
15783
15784                 if (work && work->event &&
15785                     work->event->base.file_priv == file) {
15786                         kfree(work->event);
15787                         work->event = NULL;
15788                 }
15789
15790                 spin_unlock_irq(&dev->event_lock);
15791         }
15792 }