2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
69 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
85 static const uint32_t intel_cursor_formats[] = {
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
127 int p2_slow, p2_fast;
130 typedef struct intel_limit intel_limit_t;
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
147 return vco_freq[hpll_freq] * 1000;
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg, int ref_freq)
156 mutex_lock(&dev_priv->sb_lock);
157 val = vlv_cck_read(dev_priv, reg);
158 mutex_unlock(&dev_priv->sb_lock);
160 divider = val & CCK_FREQUENCY_VALUES;
162 WARN((val & CCK_FREQUENCY_STATUS) !=
163 (divider << CCK_FREQUENCY_STATUS_SHIFT),
164 "%s change in progress\n", name);
166 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170 const char *name, u32 reg)
172 if (dev_priv->hpll_freq == 0)
173 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
175 return vlv_get_cck_clock(dev_priv, name, reg,
176 dev_priv->hpll_freq);
180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
182 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
188 /* RAWCLK_FREQ_VLV register updated from power well code */
189 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
190 CCK_DISPLAY_REF_CLOCK_CONTROL);
194 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 /* hrawclock is 1/4 the FSB frequency */
199 clkcfg = I915_READ(CLKCFG);
200 switch (clkcfg & CLKCFG_FSB_MASK) {
209 case CLKCFG_FSB_1067:
211 case CLKCFG_FSB_1333:
213 /* these two are just a guess; one of them might be right */
214 case CLKCFG_FSB_1600:
215 case CLKCFG_FSB_1600_ALT:
222 void intel_update_rawclk(struct drm_i915_private *dev_priv)
224 if (HAS_PCH_SPLIT(dev_priv))
225 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
226 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
227 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
228 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
229 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
231 return; /* no rawclk on other platforms, or no need to know it */
233 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
236 static void intel_update_czclk(struct drm_i915_private *dev_priv)
238 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
241 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
242 CCK_CZ_CLOCK_CONTROL);
244 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
247 static inline u32 /* units of 100MHz */
248 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
249 const struct intel_crtc_state *pipe_config)
251 if (HAS_DDI(dev_priv))
252 return pipe_config->port_clock; /* SPLL */
253 else if (IS_GEN5(dev_priv))
254 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 static const intel_limit_t intel_limits_i8xx_dac = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 908000, .max = 1512000 },
262 .n = { .min = 2, .max = 16 },
263 .m = { .min = 96, .max = 140 },
264 .m1 = { .min = 18, .max = 26 },
265 .m2 = { .min = 6, .max = 16 },
266 .p = { .min = 4, .max = 128 },
267 .p1 = { .min = 2, .max = 33 },
268 .p2 = { .dot_limit = 165000,
269 .p2_slow = 4, .p2_fast = 2 },
272 static const intel_limit_t intel_limits_i8xx_dvo = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 908000, .max = 1512000 },
275 .n = { .min = 2, .max = 16 },
276 .m = { .min = 96, .max = 140 },
277 .m1 = { .min = 18, .max = 26 },
278 .m2 = { .min = 6, .max = 16 },
279 .p = { .min = 4, .max = 128 },
280 .p1 = { .min = 2, .max = 33 },
281 .p2 = { .dot_limit = 165000,
282 .p2_slow = 4, .p2_fast = 4 },
285 static const intel_limit_t intel_limits_i8xx_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 908000, .max = 1512000 },
288 .n = { .min = 2, .max = 16 },
289 .m = { .min = 96, .max = 140 },
290 .m1 = { .min = 18, .max = 26 },
291 .m2 = { .min = 6, .max = 16 },
292 .p = { .min = 4, .max = 128 },
293 .p1 = { .min = 1, .max = 6 },
294 .p2 = { .dot_limit = 165000,
295 .p2_slow = 14, .p2_fast = 7 },
298 static const intel_limit_t intel_limits_i9xx_sdvo = {
299 .dot = { .min = 20000, .max = 400000 },
300 .vco = { .min = 1400000, .max = 2800000 },
301 .n = { .min = 1, .max = 6 },
302 .m = { .min = 70, .max = 120 },
303 .m1 = { .min = 8, .max = 18 },
304 .m2 = { .min = 3, .max = 7 },
305 .p = { .min = 5, .max = 80 },
306 .p1 = { .min = 1, .max = 8 },
307 .p2 = { .dot_limit = 200000,
308 .p2_slow = 10, .p2_fast = 5 },
311 static const intel_limit_t intel_limits_i9xx_lvds = {
312 .dot = { .min = 20000, .max = 400000 },
313 .vco = { .min = 1400000, .max = 2800000 },
314 .n = { .min = 1, .max = 6 },
315 .m = { .min = 70, .max = 120 },
316 .m1 = { .min = 8, .max = 18 },
317 .m2 = { .min = 3, .max = 7 },
318 .p = { .min = 7, .max = 98 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 112000,
321 .p2_slow = 14, .p2_fast = 7 },
325 static const intel_limit_t intel_limits_g4x_sdvo = {
326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 1750000, .max = 3500000},
328 .n = { .min = 1, .max = 4 },
329 .m = { .min = 104, .max = 138 },
330 .m1 = { .min = 17, .max = 23 },
331 .m2 = { .min = 5, .max = 11 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 1, .max = 3},
334 .p2 = { .dot_limit = 270000,
340 static const intel_limit_t intel_limits_g4x_hdmi = {
341 .dot = { .min = 22000, .max = 400000 },
342 .vco = { .min = 1750000, .max = 3500000},
343 .n = { .min = 1, .max = 4 },
344 .m = { .min = 104, .max = 138 },
345 .m1 = { .min = 16, .max = 23 },
346 .m2 = { .min = 5, .max = 11 },
347 .p = { .min = 5, .max = 80 },
348 .p1 = { .min = 1, .max = 8},
349 .p2 = { .dot_limit = 165000,
350 .p2_slow = 10, .p2_fast = 5 },
353 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
354 .dot = { .min = 20000, .max = 115000 },
355 .vco = { .min = 1750000, .max = 3500000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 104, .max = 138 },
358 .m1 = { .min = 17, .max = 23 },
359 .m2 = { .min = 5, .max = 11 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 14, .p2_fast = 14
367 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
368 .dot = { .min = 80000, .max = 224000 },
369 .vco = { .min = 1750000, .max = 3500000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 104, .max = 138 },
372 .m1 = { .min = 17, .max = 23 },
373 .m2 = { .min = 5, .max = 11 },
374 .p = { .min = 14, .max = 42 },
375 .p1 = { .min = 2, .max = 6 },
376 .p2 = { .dot_limit = 0,
377 .p2_slow = 7, .p2_fast = 7
381 static const intel_limit_t intel_limits_pineview_sdvo = {
382 .dot = { .min = 20000, .max = 400000},
383 .vco = { .min = 1700000, .max = 3500000 },
384 /* Pineview's Ncounter is a ring counter */
385 .n = { .min = 3, .max = 6 },
386 .m = { .min = 2, .max = 256 },
387 /* Pineview only has one combined m divider, which we treat as m2. */
388 .m1 = { .min = 0, .max = 0 },
389 .m2 = { .min = 0, .max = 254 },
390 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = 200000,
393 .p2_slow = 10, .p2_fast = 5 },
396 static const intel_limit_t intel_limits_pineview_lvds = {
397 .dot = { .min = 20000, .max = 400000 },
398 .vco = { .min = 1700000, .max = 3500000 },
399 .n = { .min = 3, .max = 6 },
400 .m = { .min = 2, .max = 256 },
401 .m1 = { .min = 0, .max = 0 },
402 .m2 = { .min = 0, .max = 254 },
403 .p = { .min = 7, .max = 112 },
404 .p1 = { .min = 1, .max = 8 },
405 .p2 = { .dot_limit = 112000,
406 .p2_slow = 14, .p2_fast = 14 },
409 /* Ironlake / Sandybridge
411 * We calculate clock using (register_value + 2) for N/M1/M2, so here
412 * the range value for them is (actual_value - 2).
414 static const intel_limit_t intel_limits_ironlake_dac = {
415 .dot = { .min = 25000, .max = 350000 },
416 .vco = { .min = 1760000, .max = 3510000 },
417 .n = { .min = 1, .max = 5 },
418 .m = { .min = 79, .max = 127 },
419 .m1 = { .min = 12, .max = 22 },
420 .m2 = { .min = 5, .max = 9 },
421 .p = { .min = 5, .max = 80 },
422 .p1 = { .min = 1, .max = 8 },
423 .p2 = { .dot_limit = 225000,
424 .p2_slow = 10, .p2_fast = 5 },
427 static const intel_limit_t intel_limits_ironlake_single_lvds = {
428 .dot = { .min = 25000, .max = 350000 },
429 .vco = { .min = 1760000, .max = 3510000 },
430 .n = { .min = 1, .max = 3 },
431 .m = { .min = 79, .max = 118 },
432 .m1 = { .min = 12, .max = 22 },
433 .m2 = { .min = 5, .max = 9 },
434 .p = { .min = 28, .max = 112 },
435 .p1 = { .min = 2, .max = 8 },
436 .p2 = { .dot_limit = 225000,
437 .p2_slow = 14, .p2_fast = 14 },
440 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
441 .dot = { .min = 25000, .max = 350000 },
442 .vco = { .min = 1760000, .max = 3510000 },
443 .n = { .min = 1, .max = 3 },
444 .m = { .min = 79, .max = 127 },
445 .m1 = { .min = 12, .max = 22 },
446 .m2 = { .min = 5, .max = 9 },
447 .p = { .min = 14, .max = 56 },
448 .p1 = { .min = 2, .max = 8 },
449 .p2 = { .dot_limit = 225000,
450 .p2_slow = 7, .p2_fast = 7 },
453 /* LVDS 100mhz refclk limits. */
454 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
455 .dot = { .min = 25000, .max = 350000 },
456 .vco = { .min = 1760000, .max = 3510000 },
457 .n = { .min = 1, .max = 2 },
458 .m = { .min = 79, .max = 126 },
459 .m1 = { .min = 12, .max = 22 },
460 .m2 = { .min = 5, .max = 9 },
461 .p = { .min = 28, .max = 112 },
462 .p1 = { .min = 2, .max = 8 },
463 .p2 = { .dot_limit = 225000,
464 .p2_slow = 14, .p2_fast = 14 },
467 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
468 .dot = { .min = 25000, .max = 350000 },
469 .vco = { .min = 1760000, .max = 3510000 },
470 .n = { .min = 1, .max = 3 },
471 .m = { .min = 79, .max = 126 },
472 .m1 = { .min = 12, .max = 22 },
473 .m2 = { .min = 5, .max = 9 },
474 .p = { .min = 14, .max = 42 },
475 .p1 = { .min = 2, .max = 6 },
476 .p2 = { .dot_limit = 225000,
477 .p2_slow = 7, .p2_fast = 7 },
480 static const intel_limit_t intel_limits_vlv = {
482 * These are the data rate limits (measured in fast clocks)
483 * since those are the strictest limits we have. The fast
484 * clock and actual rate limits are more relaxed, so checking
485 * them would make no difference.
487 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
488 .vco = { .min = 4000000, .max = 6000000 },
489 .n = { .min = 1, .max = 7 },
490 .m1 = { .min = 2, .max = 3 },
491 .m2 = { .min = 11, .max = 156 },
492 .p1 = { .min = 2, .max = 3 },
493 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
496 static const intel_limit_t intel_limits_chv = {
498 * These are the data rate limits (measured in fast clocks)
499 * since those are the strictest limits we have. The fast
500 * clock and actual rate limits are more relaxed, so checking
501 * them would make no difference.
503 .dot = { .min = 25000 * 5, .max = 540000 * 5},
504 .vco = { .min = 4800000, .max = 6480000 },
505 .n = { .min = 1, .max = 1 },
506 .m1 = { .min = 2, .max = 2 },
507 .m2 = { .min = 24 << 22, .max = 175 << 22 },
508 .p1 = { .min = 2, .max = 4 },
509 .p2 = { .p2_slow = 1, .p2_fast = 14 },
512 static const intel_limit_t intel_limits_bxt = {
513 /* FIXME: find real dot limits */
514 .dot = { .min = 0, .max = INT_MAX },
515 .vco = { .min = 4800000, .max = 6700000 },
516 .n = { .min = 1, .max = 1 },
517 .m1 = { .min = 2, .max = 2 },
518 /* FIXME: find real m2 limits */
519 .m2 = { .min = 2 << 22, .max = 255 << 22 },
520 .p1 = { .min = 2, .max = 4 },
521 .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 needs_modeset(struct drm_crtc_state *state)
527 return drm_atomic_crtc_needs_modeset(state);
531 * Returns whether any output on the specified pipe is of the specified type
533 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
535 struct drm_device *dev = crtc->base.dev;
536 struct intel_encoder *encoder;
538 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
539 if (encoder->type == type)
546 * Returns whether any output on the specified pipe will have the specified
547 * type after a staged modeset is complete, i.e., the same as
548 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
551 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
554 struct drm_atomic_state *state = crtc_state->base.state;
555 struct drm_connector *connector;
556 struct drm_connector_state *connector_state;
557 struct intel_encoder *encoder;
558 int i, num_connectors = 0;
560 for_each_connector_in_state(state, connector, connector_state, i) {
561 if (connector_state->crtc != crtc_state->base.crtc)
566 encoder = to_intel_encoder(connector_state->best_encoder);
567 if (encoder->type == type)
571 WARN_ON(num_connectors == 0);
577 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
578 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
579 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
580 * The helpers' return value is the rate of the clock that is fed to the
581 * display engine's pipe which can be the above fast dot clock rate or a
582 * divided-down version of it.
584 /* m1 is reserved as 0 in Pineview, n is a ring counter */
585 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
587 clock->m = clock->m2 + 2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
591 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
597 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
599 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
602 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
604 clock->m = i9xx_dpll_compute_m(clock);
605 clock->p = clock->p1 * clock->p2;
606 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
608 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
609 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
614 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
616 clock->m = clock->m1 * clock->m2;
617 clock->p = clock->p1 * clock->p2;
618 if (WARN_ON(clock->n == 0 || clock->p == 0))
620 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
621 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
623 return clock->dot / 5;
626 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
628 clock->m = clock->m1 * clock->m2;
629 clock->p = clock->p1 * clock->p2;
630 if (WARN_ON(clock->n == 0 || clock->p == 0))
632 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
634 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
636 return clock->dot / 5;
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
649 if (clock->n < limit->n.min || limit->n.max < clock->n)
650 INTELPllInvalid("n out of range\n");
651 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
652 INTELPllInvalid("p1 out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
658 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
659 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
660 if (clock->m1 <= clock->m2)
661 INTELPllInvalid("m1 <= m2\n");
663 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
664 if (clock->p < limit->p.min || limit->p.max < clock->p)
665 INTELPllInvalid("p out of range\n");
666 if (clock->m < limit->m.min || limit->m.max < clock->m)
667 INTELPllInvalid("m out of range\n");
670 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
671 INTELPllInvalid("vco out of range\n");
672 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
673 * connector, etc., rather than just a single range.
675 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
676 INTELPllInvalid("dot out of range\n");
682 i9xx_select_p2_div(const intel_limit_t *limit,
683 const struct intel_crtc_state *crtc_state,
686 struct drm_device *dev = crtc_state->base.crtc->dev;
688 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
690 * For LVDS just rely on its current settings for dual-channel.
691 * We haven't figured out how to reliably set up different
692 * single/dual channel state, if we even can.
694 if (intel_is_dual_link_lvds(dev))
695 return limit->p2.p2_fast;
697 return limit->p2.p2_slow;
699 if (target < limit->p2.dot_limit)
700 return limit->p2.p2_slow;
702 return limit->p2.p2_fast;
707 * Returns a set of divisors for the desired target clock with the given
708 * refclk, or FALSE. The returned values represent the clock equation:
709 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
711 * Target and reference clocks are specified in kHz.
713 * If match_clock is provided, then best_clock P divider must match the P
714 * divider from @match_clock used for LVDS downclocking.
717 i9xx_find_best_dpll(const intel_limit_t *limit,
718 struct intel_crtc_state *crtc_state,
719 int target, int refclk, intel_clock_t *match_clock,
720 intel_clock_t *best_clock)
722 struct drm_device *dev = crtc_state->base.crtc->dev;
726 memset(best_clock, 0, sizeof(*best_clock));
728 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 if (clock.m2 >= clock.m1)
736 for (clock.n = limit->n.min;
737 clock.n <= limit->n.max; clock.n++) {
738 for (clock.p1 = limit->p1.min;
739 clock.p1 <= limit->p1.max; clock.p1++) {
742 i9xx_calc_dpll_params(refclk, &clock);
743 if (!intel_PLL_is_valid(dev, limit,
747 clock.p != match_clock->p)
750 this_err = abs(clock.dot - target);
751 if (this_err < err) {
760 return (err != target);
764 * Returns a set of divisors for the desired target clock with the given
765 * refclk, or FALSE. The returned values represent the clock equation:
766 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
768 * Target and reference clocks are specified in kHz.
770 * If match_clock is provided, then best_clock P divider must match the P
771 * divider from @match_clock used for LVDS downclocking.
774 pnv_find_best_dpll(const intel_limit_t *limit,
775 struct intel_crtc_state *crtc_state,
776 int target, int refclk, intel_clock_t *match_clock,
777 intel_clock_t *best_clock)
779 struct drm_device *dev = crtc_state->base.crtc->dev;
783 memset(best_clock, 0, sizeof(*best_clock));
785 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
787 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
789 for (clock.m2 = limit->m2.min;
790 clock.m2 <= limit->m2.max; clock.m2++) {
791 for (clock.n = limit->n.min;
792 clock.n <= limit->n.max; clock.n++) {
793 for (clock.p1 = limit->p1.min;
794 clock.p1 <= limit->p1.max; clock.p1++) {
797 pnv_calc_dpll_params(refclk, &clock);
798 if (!intel_PLL_is_valid(dev, limit,
802 clock.p != match_clock->p)
805 this_err = abs(clock.dot - target);
806 if (this_err < err) {
815 return (err != target);
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
823 * Target and reference clocks are specified in kHz.
825 * If match_clock is provided, then best_clock P divider must match the P
826 * divider from @match_clock used for LVDS downclocking.
829 g4x_find_best_dpll(const intel_limit_t *limit,
830 struct intel_crtc_state *crtc_state,
831 int target, int refclk, intel_clock_t *match_clock,
832 intel_clock_t *best_clock)
834 struct drm_device *dev = crtc_state->base.crtc->dev;
838 /* approximately equals target * 0.00585 */
839 int err_most = (target >> 8) + (target >> 9);
841 memset(best_clock, 0, sizeof(*best_clock));
843 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
845 max_n = limit->n.max;
846 /* based on hardware requirement, prefer smaller n to precision */
847 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
848 /* based on hardware requirement, prefere larger m1,m2 */
849 for (clock.m1 = limit->m1.max;
850 clock.m1 >= limit->m1.min; clock.m1--) {
851 for (clock.m2 = limit->m2.max;
852 clock.m2 >= limit->m2.min; clock.m2--) {
853 for (clock.p1 = limit->p1.max;
854 clock.p1 >= limit->p1.min; clock.p1--) {
857 i9xx_calc_dpll_params(refclk, &clock);
858 if (!intel_PLL_is_valid(dev, limit,
862 this_err = abs(clock.dot - target);
863 if (this_err < err_most) {
877 * Check if the calculated PLL configuration is more optimal compared to the
878 * best configuration and error found so far. Return the calculated error.
880 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
881 const intel_clock_t *calculated_clock,
882 const intel_clock_t *best_clock,
883 unsigned int best_error_ppm,
884 unsigned int *error_ppm)
887 * For CHV ignore the error and consider only the P value.
888 * Prefer a bigger P value based on HW requirements.
890 if (IS_CHERRYVIEW(dev)) {
893 return calculated_clock->p > best_clock->p;
896 if (WARN_ON_ONCE(!target_freq))
899 *error_ppm = div_u64(1000000ULL *
900 abs(target_freq - calculated_clock->dot),
903 * Prefer a better P value over a better (smaller) error if the error
904 * is small. Ensure this preference for future configurations too by
905 * setting the error to 0.
907 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
913 return *error_ppm + 10 < best_error_ppm;
917 * Returns a set of divisors for the desired target clock with the given
918 * refclk, or FALSE. The returned values represent the clock equation:
919 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
922 vlv_find_best_dpll(const intel_limit_t *limit,
923 struct intel_crtc_state *crtc_state,
924 int target, int refclk, intel_clock_t *match_clock,
925 intel_clock_t *best_clock)
927 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
928 struct drm_device *dev = crtc->base.dev;
930 unsigned int bestppm = 1000000;
931 /* min update 19.2 MHz */
932 int max_n = min(limit->n.max, refclk / 19200);
935 target *= 5; /* fast clock */
937 memset(best_clock, 0, sizeof(*best_clock));
939 /* based on hardware requirement, prefer smaller n to precision */
940 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
941 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
942 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
943 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
944 clock.p = clock.p1 * clock.p2;
945 /* based on hardware requirement, prefer bigger m1,m2 values */
946 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
949 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
952 vlv_calc_dpll_params(refclk, &clock);
954 if (!intel_PLL_is_valid(dev, limit,
958 if (!vlv_PLL_is_optimal(dev, target,
976 * Returns a set of divisors for the desired target clock with the given
977 * refclk, or FALSE. The returned values represent the clock equation:
978 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
981 chv_find_best_dpll(const intel_limit_t *limit,
982 struct intel_crtc_state *crtc_state,
983 int target, int refclk, intel_clock_t *match_clock,
984 intel_clock_t *best_clock)
986 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
987 struct drm_device *dev = crtc->base.dev;
988 unsigned int best_error_ppm;
993 memset(best_clock, 0, sizeof(*best_clock));
994 best_error_ppm = 1000000;
997 * Based on hardware doc, the n always set to 1, and m1 always
998 * set to 2. If requires to support 200Mhz refclk, we need to
999 * revisit this because n may not 1 anymore.
1001 clock.n = 1, clock.m1 = 2;
1002 target *= 5; /* fast clock */
1004 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1005 for (clock.p2 = limit->p2.p2_fast;
1006 clock.p2 >= limit->p2.p2_slow;
1007 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1008 unsigned int error_ppm;
1010 clock.p = clock.p1 * clock.p2;
1012 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1013 clock.n) << 22, refclk * clock.m1);
1015 if (m2 > INT_MAX/clock.m1)
1020 chv_calc_dpll_params(refclk, &clock);
1022 if (!intel_PLL_is_valid(dev, limit, &clock))
1025 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1026 best_error_ppm, &error_ppm))
1029 *best_clock = clock;
1030 best_error_ppm = error_ppm;
1038 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1039 intel_clock_t *best_clock)
1041 int refclk = 100000;
1042 const intel_limit_t *limit = &intel_limits_bxt;
1044 return chv_find_best_dpll(limit, crtc_state,
1045 target_clock, refclk, NULL, best_clock);
1048 bool intel_crtc_active(struct drm_crtc *crtc)
1050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1052 /* Be paranoid as we can arrive here with only partial
1053 * state retrieved from the hardware during setup.
1055 * We can ditch the adjusted_mode.crtc_clock check as soon
1056 * as Haswell has gained clock readout/fastboot support.
1058 * We can ditch the crtc->primary->fb check as soon as we can
1059 * properly reconstruct framebuffers.
1061 * FIXME: The intel_crtc->active here should be switched to
1062 * crtc->state->active once we have proper CRTC states wired up
1065 return intel_crtc->active && crtc->primary->state->fb &&
1066 intel_crtc->config->base.adjusted_mode.crtc_clock;
1069 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1072 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075 return intel_crtc->config->cpu_transcoder;
1078 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 i915_reg_t reg = PIPEDSL(pipe);
1086 line_mask = DSL_LINEMASK_GEN2;
1088 line_mask = DSL_LINEMASK_GEN3;
1090 line1 = I915_READ(reg) & line_mask;
1092 line2 = I915_READ(reg) & line_mask;
1094 return line1 == line2;
1098 * intel_wait_for_pipe_off - wait for pipe to turn off
1099 * @crtc: crtc whose pipe to wait for
1101 * After disabling a pipe, we can't wait for vblank in the usual way,
1102 * spinning on the vblank interrupt status bit, since we won't actually
1103 * see an interrupt when the pipe is disabled.
1105 * On Gen4 and above:
1106 * wait for the pipe register state bit to turn off
1109 * wait for the display line value to settle (it usually
1110 * ends up stopping at the start of the next frame).
1113 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1115 struct drm_device *dev = crtc->base.dev;
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1117 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1118 enum pipe pipe = crtc->pipe;
1120 if (INTEL_INFO(dev)->gen >= 4) {
1121 i915_reg_t reg = PIPECONF(cpu_transcoder);
1123 /* Wait for the Pipe State to go off */
1124 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1126 WARN(1, "pipe_off wait timed out\n");
1128 /* Wait for the display line to settle */
1129 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1130 WARN(1, "pipe_off wait timed out\n");
1134 /* Only for pre-ILK configs */
1135 void assert_pll(struct drm_i915_private *dev_priv,
1136 enum pipe pipe, bool state)
1141 val = I915_READ(DPLL(pipe));
1142 cur_state = !!(val & DPLL_VCO_ENABLE);
1143 I915_STATE_WARN(cur_state != state,
1144 "PLL state assertion failure (expected %s, current %s)\n",
1145 onoff(state), onoff(cur_state));
1148 /* XXX: the dsi pll is shared between MIPI DSI ports */
1149 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1154 mutex_lock(&dev_priv->sb_lock);
1155 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1156 mutex_unlock(&dev_priv->sb_lock);
1158 cur_state = val & DSI_PLL_VCO_EN;
1159 I915_STATE_WARN(cur_state != state,
1160 "DSI PLL state assertion failure (expected %s, current %s)\n",
1161 onoff(state), onoff(cur_state));
1164 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1165 enum pipe pipe, bool state)
1168 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1171 if (HAS_DDI(dev_priv)) {
1172 /* DDI does not have a specific FDI_TX register */
1173 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1174 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1176 u32 val = I915_READ(FDI_TX_CTL(pipe));
1177 cur_state = !!(val & FDI_TX_ENABLE);
1179 I915_STATE_WARN(cur_state != state,
1180 "FDI TX state assertion failure (expected %s, current %s)\n",
1181 onoff(state), onoff(cur_state));
1183 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1184 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1186 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, bool state)
1192 val = I915_READ(FDI_RX_CTL(pipe));
1193 cur_state = !!(val & FDI_RX_ENABLE);
1194 I915_STATE_WARN(cur_state != state,
1195 "FDI RX state assertion failure (expected %s, current %s)\n",
1196 onoff(state), onoff(cur_state));
1198 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1199 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1201 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1206 /* ILK FDI PLL is always enabled */
1207 if (INTEL_INFO(dev_priv)->gen == 5)
1210 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1211 if (HAS_DDI(dev_priv))
1214 val = I915_READ(FDI_TX_CTL(pipe));
1215 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1218 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1224 val = I915_READ(FDI_RX_CTL(pipe));
1225 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1226 I915_STATE_WARN(cur_state != state,
1227 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1228 onoff(state), onoff(cur_state));
1231 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1234 struct drm_device *dev = dev_priv->dev;
1237 enum pipe panel_pipe = PIPE_A;
1240 if (WARN_ON(HAS_DDI(dev)))
1243 if (HAS_PCH_SPLIT(dev)) {
1246 pp_reg = PCH_PP_CONTROL;
1247 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1250 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1251 panel_pipe = PIPE_B;
1252 /* XXX: else fix for eDP */
1253 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1254 /* presumably write lock depends on pipe, not port select */
1255 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1258 pp_reg = PP_CONTROL;
1259 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1260 panel_pipe = PIPE_B;
1263 val = I915_READ(pp_reg);
1264 if (!(val & PANEL_POWER_ON) ||
1265 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1268 I915_STATE_WARN(panel_pipe == pipe && locked,
1269 "panel assertion failure, pipe %c regs locked\n",
1273 static void assert_cursor(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, bool state)
1276 struct drm_device *dev = dev_priv->dev;
1279 if (IS_845G(dev) || IS_I865G(dev))
1280 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1282 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1284 I915_STATE_WARN(cur_state != state,
1285 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1286 pipe_name(pipe), onoff(state), onoff(cur_state));
1288 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1289 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291 void assert_pipe(struct drm_i915_private *dev_priv,
1292 enum pipe pipe, bool state)
1295 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1297 enum intel_display_power_domain power_domain;
1299 /* if we need the pipe quirk it must be always on */
1300 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1301 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1304 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1305 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1306 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1307 cur_state = !!(val & PIPECONF_ENABLE);
1309 intel_display_power_put(dev_priv, power_domain);
1314 I915_STATE_WARN(cur_state != state,
1315 "pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), onoff(state), onoff(cur_state));
1319 static void assert_plane(struct drm_i915_private *dev_priv,
1320 enum plane plane, bool state)
1325 val = I915_READ(DSPCNTR(plane));
1326 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1327 I915_STATE_WARN(cur_state != state,
1328 "plane %c assertion failure (expected %s, current %s)\n",
1329 plane_name(plane), onoff(state), onoff(cur_state));
1332 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1333 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1335 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1338 struct drm_device *dev = dev_priv->dev;
1341 /* Primary planes are fixed to pipes on gen4+ */
1342 if (INTEL_INFO(dev)->gen >= 4) {
1343 u32 val = I915_READ(DSPCNTR(pipe));
1344 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1345 "plane %c assertion failure, should be disabled but not\n",
1350 /* Need to check both planes against the pipe */
1351 for_each_pipe(dev_priv, i) {
1352 u32 val = I915_READ(DSPCNTR(i));
1353 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1354 DISPPLANE_SEL_PIPE_SHIFT;
1355 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1356 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(i), pipe_name(pipe));
1361 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1364 struct drm_device *dev = dev_priv->dev;
1367 if (INTEL_INFO(dev)->gen >= 9) {
1368 for_each_sprite(dev_priv, pipe, sprite) {
1369 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1370 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1371 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1372 sprite, pipe_name(pipe));
1374 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1375 for_each_sprite(dev_priv, pipe, sprite) {
1376 u32 val = I915_READ(SPCNTR(pipe, sprite));
1377 I915_STATE_WARN(val & SP_ENABLE,
1378 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1379 sprite_name(pipe, sprite), pipe_name(pipe));
1381 } else if (INTEL_INFO(dev)->gen >= 7) {
1382 u32 val = I915_READ(SPRCTL(pipe));
1383 I915_STATE_WARN(val & SPRITE_ENABLE,
1384 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1385 plane_name(pipe), pipe_name(pipe));
1386 } else if (INTEL_INFO(dev)->gen >= 5) {
1387 u32 val = I915_READ(DVSCNTR(pipe));
1388 I915_STATE_WARN(val & DVS_ENABLE,
1389 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1390 plane_name(pipe), pipe_name(pipe));
1394 static void assert_vblank_disabled(struct drm_crtc *crtc)
1396 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1397 drm_crtc_vblank_put(crtc);
1400 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1406 val = I915_READ(PCH_TRANSCONF(pipe));
1407 enabled = !!(val & TRANS_ENABLE);
1408 I915_STATE_WARN(enabled,
1409 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1413 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, u32 port_sel, u32 val)
1416 if ((val & DP_PORT_EN) == 0)
1419 if (HAS_PCH_CPT(dev_priv)) {
1420 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1421 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1423 } else if (IS_CHERRYVIEW(dev_priv)) {
1424 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1427 if ((val & DP_PIPE_MASK) != (pipe << 30))
1433 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe, u32 val)
1436 if ((val & SDVO_ENABLE) == 0)
1439 if (HAS_PCH_CPT(dev_priv)) {
1440 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1442 } else if (IS_CHERRYVIEW(dev_priv)) {
1443 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1446 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1452 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1453 enum pipe pipe, u32 val)
1455 if ((val & LVDS_PORT_EN) == 0)
1458 if (HAS_PCH_CPT(dev_priv)) {
1459 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1462 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1468 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 val)
1471 if ((val & ADPA_DAC_ENABLE) == 0)
1473 if (HAS_PCH_CPT(dev_priv)) {
1474 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1477 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1483 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1484 enum pipe pipe, i915_reg_t reg,
1487 u32 val = I915_READ(reg);
1488 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1489 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1490 i915_mmio_reg_offset(reg), pipe_name(pipe));
1492 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1493 && (val & DP_PIPEB_SELECT),
1494 "IBX PCH dp port still using transcoder B\n");
1497 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, i915_reg_t reg)
1500 u32 val = I915_READ(reg);
1501 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1502 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1503 i915_mmio_reg_offset(reg), pipe_name(pipe));
1505 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1506 && (val & SDVO_PIPE_B_SELECT),
1507 "IBX PCH hdmi port still using transcoder B\n");
1510 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1516 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1517 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1519 val = I915_READ(PCH_ADPA);
1520 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1521 "PCH VGA enabled on transcoder %c, should be disabled\n",
1524 val = I915_READ(PCH_LVDS);
1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1534 static void _vlv_enable_pll(struct intel_crtc *crtc,
1535 const struct intel_crtc_state *pipe_config)
1537 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1538 enum pipe pipe = crtc->pipe;
1540 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1541 POSTING_READ(DPLL(pipe));
1544 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1545 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1548 static void vlv_enable_pll(struct intel_crtc *crtc,
1549 const struct intel_crtc_state *pipe_config)
1551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1552 enum pipe pipe = crtc->pipe;
1554 assert_pipe_disabled(dev_priv, pipe);
1556 /* PLL is protected by panel, make sure we can write it */
1557 assert_panel_unlocked(dev_priv, pipe);
1559 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1560 _vlv_enable_pll(crtc, pipe_config);
1562 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1563 POSTING_READ(DPLL_MD(pipe));
1567 static void _chv_enable_pll(struct intel_crtc *crtc,
1568 const struct intel_crtc_state *pipe_config)
1570 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1571 enum pipe pipe = crtc->pipe;
1572 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1575 mutex_lock(&dev_priv->sb_lock);
1577 /* Enable back the 10bit clock to display controller */
1578 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1579 tmp |= DPIO_DCLKP_EN;
1580 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1582 mutex_unlock(&dev_priv->sb_lock);
1585 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1592 /* Check PLL is locked */
1593 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1594 DRM_ERROR("PLL %d failed to lock\n", pipe);
1597 static void chv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1600 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1601 enum pipe pipe = crtc->pipe;
1603 assert_pipe_disabled(dev_priv, pipe);
1605 /* PLL is protected by panel, make sure we can write it */
1606 assert_panel_unlocked(dev_priv, pipe);
1608 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1609 _chv_enable_pll(crtc, pipe_config);
1611 if (pipe != PIPE_A) {
1613 * WaPixelRepeatModeFixForC0:chv
1615 * DPLLCMD is AWOL. Use chicken bits to propagate
1616 * the value from DPLLBMD to either pipe B or C.
1618 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1619 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1620 I915_WRITE(CBR4_VLV, 0);
1621 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1624 * DPLLB VGA mode also seems to cause problems.
1625 * We should always have it disabled.
1627 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1629 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1630 POSTING_READ(DPLL_MD(pipe));
1634 static int intel_num_dvo_pipes(struct drm_device *dev)
1636 struct intel_crtc *crtc;
1639 for_each_intel_crtc(dev, crtc)
1640 count += crtc->base.state->active &&
1641 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1646 static void i9xx_enable_pll(struct intel_crtc *crtc)
1648 struct drm_device *dev = crtc->base.dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 i915_reg_t reg = DPLL(crtc->pipe);
1651 u32 dpll = crtc->config->dpll_hw_state.dpll;
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1655 /* PLL is protected by panel, make sure we can write it */
1656 if (IS_MOBILE(dev) && !IS_I830(dev))
1657 assert_panel_unlocked(dev_priv, crtc->pipe);
1659 /* Enable DVO 2x clock on both PLLs if necessary */
1660 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662 * It appears to be important that we don't enable this
1663 * for the current pipe before otherwise configuring the
1664 * PLL. No idea how this should be handled if multiple
1665 * DVO outputs are enabled simultaneosly.
1667 dpll |= DPLL_DVO_2X_MODE;
1668 I915_WRITE(DPLL(!crtc->pipe),
1669 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1673 * Apparently we need to have VGA mode enabled prior to changing
1674 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1675 * dividers, even though the register value does change.
1679 I915_WRITE(reg, dpll);
1681 /* Wait for the clocks to stabilize. */
1685 if (INTEL_INFO(dev)->gen >= 4) {
1686 I915_WRITE(DPLL_MD(crtc->pipe),
1687 crtc->config->dpll_hw_state.dpll_md);
1689 /* The pixel multiplier can only be updated once the
1690 * DPLL is enabled and the clocks are stable.
1692 * So write it again.
1694 I915_WRITE(reg, dpll);
1697 /* We do this three times for luck */
1698 I915_WRITE(reg, dpll);
1700 udelay(150); /* wait for warmup */
1701 I915_WRITE(reg, dpll);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg, dpll);
1706 udelay(150); /* wait for warmup */
1710 * i9xx_disable_pll - disable a PLL
1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe PLL to disable
1714 * Disable the PLL for @pipe, making sure the pipe is off first.
1716 * Note! This is for pre-ILK only.
1718 static void i9xx_disable_pll(struct intel_crtc *crtc)
1720 struct drm_device *dev = crtc->base.dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 enum pipe pipe = crtc->pipe;
1724 /* Disable DVO 2x clock on both PLLs if necessary */
1726 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1727 !intel_num_dvo_pipes(dev)) {
1728 I915_WRITE(DPLL(PIPE_B),
1729 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1730 I915_WRITE(DPLL(PIPE_A),
1731 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1734 /* Don't disable pipe or pipe PLLs if needed */
1735 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1736 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1739 /* Make sure the pipe isn't still relying on us */
1740 assert_pipe_disabled(dev_priv, pipe);
1742 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1743 POSTING_READ(DPLL(pipe));
1746 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1750 /* Make sure the pipe isn't still relying on us */
1751 assert_pipe_disabled(dev_priv, pipe);
1753 val = DPLL_INTEGRATED_REF_CLK_VLV |
1754 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1756 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1758 I915_WRITE(DPLL(pipe), val);
1759 POSTING_READ(DPLL(pipe));
1762 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1764 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1767 /* Make sure the pipe isn't still relying on us */
1768 assert_pipe_disabled(dev_priv, pipe);
1770 val = DPLL_SSC_REF_CLK_CHV |
1771 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1773 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1775 I915_WRITE(DPLL(pipe), val);
1776 POSTING_READ(DPLL(pipe));
1778 mutex_lock(&dev_priv->sb_lock);
1780 /* Disable 10bit clock to display controller */
1781 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1782 val &= ~DPIO_DCLKP_EN;
1783 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1785 mutex_unlock(&dev_priv->sb_lock);
1788 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1789 struct intel_digital_port *dport,
1790 unsigned int expected_mask)
1793 i915_reg_t dpll_reg;
1795 switch (dport->port) {
1797 port_mask = DPLL_PORTB_READY_MASK;
1801 port_mask = DPLL_PORTC_READY_MASK;
1803 expected_mask <<= 4;
1806 port_mask = DPLL_PORTD_READY_MASK;
1807 dpll_reg = DPIO_PHY_STATUS;
1813 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1814 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1815 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1818 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1821 struct drm_device *dev = dev_priv->dev;
1822 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1825 uint32_t val, pipeconf_val;
1827 /* Make sure PCH DPLL is enabled */
1828 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1830 /* FDI must be feeding us bits for PCH ports */
1831 assert_fdi_tx_enabled(dev_priv, pipe);
1832 assert_fdi_rx_enabled(dev_priv, pipe);
1834 if (HAS_PCH_CPT(dev)) {
1835 /* Workaround: Set the timing override bit before enabling the
1836 * pch transcoder. */
1837 reg = TRANS_CHICKEN2(pipe);
1838 val = I915_READ(reg);
1839 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1840 I915_WRITE(reg, val);
1843 reg = PCH_TRANSCONF(pipe);
1844 val = I915_READ(reg);
1845 pipeconf_val = I915_READ(PIPECONF(pipe));
1847 if (HAS_PCH_IBX(dev_priv)) {
1849 * Make the BPC in transcoder be consistent with
1850 * that in pipeconf reg. For HDMI we must use 8bpc
1851 * here for both 8bpc and 12bpc.
1853 val &= ~PIPECONF_BPC_MASK;
1854 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1855 val |= PIPECONF_8BPC;
1857 val |= pipeconf_val & PIPECONF_BPC_MASK;
1860 val &= ~TRANS_INTERLACE_MASK;
1861 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1862 if (HAS_PCH_IBX(dev_priv) &&
1863 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1864 val |= TRANS_LEGACY_INTERLACED_ILK;
1866 val |= TRANS_INTERLACED;
1868 val |= TRANS_PROGRESSIVE;
1870 I915_WRITE(reg, val | TRANS_ENABLE);
1871 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1872 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1875 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1876 enum transcoder cpu_transcoder)
1878 u32 val, pipeconf_val;
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1882 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1884 /* Workaround: set timing override bit. */
1885 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1886 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1887 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1890 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1892 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1893 PIPECONF_INTERLACED_ILK)
1894 val |= TRANS_INTERLACED;
1896 val |= TRANS_PROGRESSIVE;
1898 I915_WRITE(LPT_TRANSCONF, val);
1899 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1900 DRM_ERROR("Failed to enable PCH transcoder\n");
1903 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1906 struct drm_device *dev = dev_priv->dev;
1910 /* FDI relies on the transcoder */
1911 assert_fdi_tx_disabled(dev_priv, pipe);
1912 assert_fdi_rx_disabled(dev_priv, pipe);
1914 /* Ports must be off as well */
1915 assert_pch_ports_disabled(dev_priv, pipe);
1917 reg = PCH_TRANSCONF(pipe);
1918 val = I915_READ(reg);
1919 val &= ~TRANS_ENABLE;
1920 I915_WRITE(reg, val);
1921 /* wait for PCH transcoder off, transcoder state */
1922 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1923 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1925 if (HAS_PCH_CPT(dev)) {
1926 /* Workaround: Clear the timing override chicken bit again. */
1927 reg = TRANS_CHICKEN2(pipe);
1928 val = I915_READ(reg);
1929 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1930 I915_WRITE(reg, val);
1934 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1938 val = I915_READ(LPT_TRANSCONF);
1939 val &= ~TRANS_ENABLE;
1940 I915_WRITE(LPT_TRANSCONF, val);
1941 /* wait for PCH transcoder off, transcoder state */
1942 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1943 DRM_ERROR("Failed to disable PCH transcoder\n");
1945 /* Workaround: clear timing override bit. */
1946 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1947 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1948 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1952 * intel_enable_pipe - enable a pipe, asserting requirements
1953 * @crtc: crtc responsible for the pipe
1955 * Enable @crtc's pipe, making sure that various hardware specific requirements
1956 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1958 static void intel_enable_pipe(struct intel_crtc *crtc)
1960 struct drm_device *dev = crtc->base.dev;
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962 enum pipe pipe = crtc->pipe;
1963 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1964 enum pipe pch_transcoder;
1968 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1970 assert_planes_disabled(dev_priv, pipe);
1971 assert_cursor_disabled(dev_priv, pipe);
1972 assert_sprites_disabled(dev_priv, pipe);
1974 if (HAS_PCH_LPT(dev_priv))
1975 pch_transcoder = TRANSCODER_A;
1977 pch_transcoder = pipe;
1980 * A pipe without a PLL won't actually be able to drive bits from
1981 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1984 if (HAS_GMCH_DISPLAY(dev_priv))
1985 if (crtc->config->has_dsi_encoder)
1986 assert_dsi_pll_enabled(dev_priv);
1988 assert_pll_enabled(dev_priv, pipe);
1990 if (crtc->config->has_pch_encoder) {
1991 /* if driving the PCH, we need FDI enabled */
1992 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1993 assert_fdi_tx_pll_enabled(dev_priv,
1994 (enum pipe) cpu_transcoder);
1996 /* FIXME: assert CPU port conditions for SNB+ */
1999 reg = PIPECONF(cpu_transcoder);
2000 val = I915_READ(reg);
2001 if (val & PIPECONF_ENABLE) {
2002 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2003 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2007 I915_WRITE(reg, val | PIPECONF_ENABLE);
2011 * Until the pipe starts DSL will read as 0, which would cause
2012 * an apparent vblank timestamp jump, which messes up also the
2013 * frame count when it's derived from the timestamps. So let's
2014 * wait for the pipe to start properly before we call
2015 * drm_crtc_vblank_on()
2017 if (dev->max_vblank_count == 0 &&
2018 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2019 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2023 * intel_disable_pipe - disable a pipe, asserting requirements
2024 * @crtc: crtc whose pipes is to be disabled
2026 * Disable the pipe of @crtc, making sure that various hardware
2027 * specific requirements are met, if applicable, e.g. plane
2028 * disabled, panel fitter off, etc.
2030 * Will wait until the pipe has shut down before returning.
2032 static void intel_disable_pipe(struct intel_crtc *crtc)
2034 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2035 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2036 enum pipe pipe = crtc->pipe;
2040 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2043 * Make sure planes won't keep trying to pump pixels to us,
2044 * or we might hang the display.
2046 assert_planes_disabled(dev_priv, pipe);
2047 assert_cursor_disabled(dev_priv, pipe);
2048 assert_sprites_disabled(dev_priv, pipe);
2050 reg = PIPECONF(cpu_transcoder);
2051 val = I915_READ(reg);
2052 if ((val & PIPECONF_ENABLE) == 0)
2056 * Double wide has implications for planes
2057 * so best keep it disabled when not needed.
2059 if (crtc->config->double_wide)
2060 val &= ~PIPECONF_DOUBLE_WIDE;
2062 /* Don't disable pipe or pipe PLLs if needed */
2063 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2064 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2065 val &= ~PIPECONF_ENABLE;
2067 I915_WRITE(reg, val);
2068 if ((val & PIPECONF_ENABLE) == 0)
2069 intel_wait_for_pipe_off(crtc);
2072 static bool need_vtd_wa(struct drm_device *dev)
2074 #ifdef CONFIG_INTEL_IOMMU
2075 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2081 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2083 return IS_GEN2(dev_priv) ? 2048 : 4096;
2086 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2087 uint64_t fb_modifier, unsigned int cpp)
2089 switch (fb_modifier) {
2090 case DRM_FORMAT_MOD_NONE:
2092 case I915_FORMAT_MOD_X_TILED:
2093 if (IS_GEN2(dev_priv))
2097 case I915_FORMAT_MOD_Y_TILED:
2098 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2102 case I915_FORMAT_MOD_Yf_TILED:
2118 MISSING_CASE(fb_modifier);
2123 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2124 uint64_t fb_modifier, unsigned int cpp)
2126 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2129 return intel_tile_size(dev_priv) /
2130 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2133 /* Return the tile dimensions in pixel units */
2134 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2135 unsigned int *tile_width,
2136 unsigned int *tile_height,
2137 uint64_t fb_modifier,
2140 unsigned int tile_width_bytes =
2141 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2143 *tile_width = tile_width_bytes / cpp;
2144 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2148 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2149 uint32_t pixel_format, uint64_t fb_modifier)
2151 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2152 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2154 return ALIGN(height, tile_height);
2157 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2159 unsigned int size = 0;
2162 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2163 size += rot_info->plane[i].width * rot_info->plane[i].height;
2169 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2170 const struct drm_framebuffer *fb,
2171 unsigned int rotation)
2173 if (intel_rotation_90_or_270(rotation)) {
2174 *view = i915_ggtt_view_rotated;
2175 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2177 *view = i915_ggtt_view_normal;
2182 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2183 struct drm_framebuffer *fb)
2185 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2186 unsigned int tile_size, tile_width, tile_height, cpp;
2188 tile_size = intel_tile_size(dev_priv);
2190 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2191 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2192 fb->modifier[0], cpp);
2194 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2195 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2197 if (info->pixel_format == DRM_FORMAT_NV12) {
2198 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2199 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2200 fb->modifier[1], cpp);
2202 info->uv_offset = fb->offsets[1];
2203 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2204 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2208 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2210 if (INTEL_INFO(dev_priv)->gen >= 9)
2212 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2213 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2215 else if (INTEL_INFO(dev_priv)->gen >= 4)
2221 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2222 uint64_t fb_modifier)
2224 switch (fb_modifier) {
2225 case DRM_FORMAT_MOD_NONE:
2226 return intel_linear_alignment(dev_priv);
2227 case I915_FORMAT_MOD_X_TILED:
2228 if (INTEL_INFO(dev_priv)->gen >= 9)
2231 case I915_FORMAT_MOD_Y_TILED:
2232 case I915_FORMAT_MOD_Yf_TILED:
2233 return 1 * 1024 * 1024;
2235 MISSING_CASE(fb_modifier);
2241 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2242 unsigned int rotation)
2244 struct drm_device *dev = fb->dev;
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2247 struct i915_ggtt_view view;
2251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2253 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2255 intel_fill_fb_ggtt_view(&view, fb, rotation);
2257 /* Note that the w/a also requires 64 PTE of padding following the
2258 * bo. We currently fill all unused PTE with the shadow page and so
2259 * we should always have valid PTE following the scanout preventing
2262 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2263 alignment = 256 * 1024;
2266 * Global gtt pte registers are special registers which actually forward
2267 * writes to a chunk of system memory. Which means that there is no risk
2268 * that the register values disappear as soon as we call
2269 * intel_runtime_pm_put(), so it is correct to wrap only the
2270 * pin/unpin/fence and not more.
2272 intel_runtime_pm_get(dev_priv);
2274 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2279 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always install
2282 * a fence as the cost is not that onerous.
2284 if (view.type == I915_GGTT_VIEW_NORMAL) {
2285 ret = i915_gem_object_get_fence(obj);
2286 if (ret == -EDEADLK) {
2288 * -EDEADLK means there are no free fences
2291 * This is propagated to atomic, but it uses
2292 * -EDEADLK to force a locking recovery, so
2293 * change the returned error to -EBUSY.
2300 i915_gem_object_pin_fence(obj);
2303 intel_runtime_pm_put(dev_priv);
2307 i915_gem_object_unpin_from_display_plane(obj, &view);
2309 intel_runtime_pm_put(dev_priv);
2313 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2315 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2316 struct i915_ggtt_view view;
2318 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2320 intel_fill_fb_ggtt_view(&view, fb, rotation);
2322 if (view.type == I915_GGTT_VIEW_NORMAL)
2323 i915_gem_object_unpin_fence(obj);
2325 i915_gem_object_unpin_from_display_plane(obj, &view);
2329 * Adjust the tile offset by moving the difference into
2332 * Input tile dimensions and pitch must already be
2333 * rotated to match x and y, and in pixel units.
2335 static u32 intel_adjust_tile_offset(int *x, int *y,
2336 unsigned int tile_width,
2337 unsigned int tile_height,
2338 unsigned int tile_size,
2339 unsigned int pitch_tiles,
2345 WARN_ON(old_offset & (tile_size - 1));
2346 WARN_ON(new_offset & (tile_size - 1));
2347 WARN_ON(new_offset > old_offset);
2349 tiles = (old_offset - new_offset) / tile_size;
2351 *y += tiles / pitch_tiles * tile_height;
2352 *x += tiles % pitch_tiles * tile_width;
2358 * Computes the linear offset to the base tile and adjusts
2359 * x, y. bytes per pixel is assumed to be a power-of-two.
2361 * In the 90/270 rotated case, x and y are assumed
2362 * to be already rotated to match the rotated GTT view, and
2363 * pitch is the tile_height aligned framebuffer height.
2365 u32 intel_compute_tile_offset(int *x, int *y,
2366 const struct drm_framebuffer *fb, int plane,
2368 unsigned int rotation)
2370 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2371 uint64_t fb_modifier = fb->modifier[plane];
2372 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2373 u32 offset, offset_aligned, alignment;
2375 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2379 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2380 unsigned int tile_size, tile_width, tile_height;
2381 unsigned int tile_rows, tiles, pitch_tiles;
2383 tile_size = intel_tile_size(dev_priv);
2384 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2387 if (intel_rotation_90_or_270(rotation)) {
2388 pitch_tiles = pitch / tile_height;
2389 swap(tile_width, tile_height);
2391 pitch_tiles = pitch / (tile_width * cpp);
2394 tile_rows = *y / tile_height;
2397 tiles = *x / tile_width;
2400 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2401 offset_aligned = offset & ~alignment;
2403 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2404 tile_size, pitch_tiles,
2405 offset, offset_aligned);
2407 offset = *y * pitch + *x * cpp;
2408 offset_aligned = offset & ~alignment;
2410 *y = (offset & alignment) / pitch;
2411 *x = ((offset & alignment) - *y * pitch) / cpp;
2414 return offset_aligned;
2417 static int i9xx_format_to_fourcc(int format)
2420 case DISPPLANE_8BPP:
2421 return DRM_FORMAT_C8;
2422 case DISPPLANE_BGRX555:
2423 return DRM_FORMAT_XRGB1555;
2424 case DISPPLANE_BGRX565:
2425 return DRM_FORMAT_RGB565;
2427 case DISPPLANE_BGRX888:
2428 return DRM_FORMAT_XRGB8888;
2429 case DISPPLANE_RGBX888:
2430 return DRM_FORMAT_XBGR8888;
2431 case DISPPLANE_BGRX101010:
2432 return DRM_FORMAT_XRGB2101010;
2433 case DISPPLANE_RGBX101010:
2434 return DRM_FORMAT_XBGR2101010;
2438 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2441 case PLANE_CTL_FORMAT_RGB_565:
2442 return DRM_FORMAT_RGB565;
2444 case PLANE_CTL_FORMAT_XRGB_8888:
2447 return DRM_FORMAT_ABGR8888;
2449 return DRM_FORMAT_XBGR8888;
2452 return DRM_FORMAT_ARGB8888;
2454 return DRM_FORMAT_XRGB8888;
2456 case PLANE_CTL_FORMAT_XRGB_2101010:
2458 return DRM_FORMAT_XBGR2101010;
2460 return DRM_FORMAT_XRGB2101010;
2465 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2466 struct intel_initial_plane_config *plane_config)
2468 struct drm_device *dev = crtc->base.dev;
2469 struct drm_i915_private *dev_priv = to_i915(dev);
2470 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2471 struct drm_i915_gem_object *obj = NULL;
2472 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2473 struct drm_framebuffer *fb = &plane_config->fb->base;
2474 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2475 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2478 size_aligned -= base_aligned;
2480 if (plane_config->size == 0)
2483 /* If the FB is too big, just don't use it since fbdev is not very
2484 * important and we should probably use that space with FBC or other
2486 if (size_aligned * 2 > ggtt->stolen_usable_size)
2489 mutex_lock(&dev->struct_mutex);
2491 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2496 mutex_unlock(&dev->struct_mutex);
2500 obj->tiling_mode = plane_config->tiling;
2501 if (obj->tiling_mode == I915_TILING_X)
2502 obj->stride = fb->pitches[0];
2504 mode_cmd.pixel_format = fb->pixel_format;
2505 mode_cmd.width = fb->width;
2506 mode_cmd.height = fb->height;
2507 mode_cmd.pitches[0] = fb->pitches[0];
2508 mode_cmd.modifier[0] = fb->modifier[0];
2509 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2511 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2513 DRM_DEBUG_KMS("intel fb init failed\n");
2517 mutex_unlock(&dev->struct_mutex);
2519 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2523 drm_gem_object_unreference(&obj->base);
2524 mutex_unlock(&dev->struct_mutex);
2528 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2530 update_state_fb(struct drm_plane *plane)
2532 if (plane->fb == plane->state->fb)
2535 if (plane->state->fb)
2536 drm_framebuffer_unreference(plane->state->fb);
2537 plane->state->fb = plane->fb;
2538 if (plane->state->fb)
2539 drm_framebuffer_reference(plane->state->fb);
2543 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2544 struct intel_initial_plane_config *plane_config)
2546 struct drm_device *dev = intel_crtc->base.dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2549 struct intel_crtc *i;
2550 struct drm_i915_gem_object *obj;
2551 struct drm_plane *primary = intel_crtc->base.primary;
2552 struct drm_plane_state *plane_state = primary->state;
2553 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2554 struct intel_plane *intel_plane = to_intel_plane(primary);
2555 struct intel_plane_state *intel_state =
2556 to_intel_plane_state(plane_state);
2557 struct drm_framebuffer *fb;
2559 if (!plane_config->fb)
2562 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2563 fb = &plane_config->fb->base;
2567 kfree(plane_config->fb);
2570 * Failed to alloc the obj, check to see if we should share
2571 * an fb with another CRTC instead
2573 for_each_crtc(dev, c) {
2574 i = to_intel_crtc(c);
2576 if (c == &intel_crtc->base)
2582 fb = c->primary->fb;
2586 obj = intel_fb_obj(fb);
2587 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2588 drm_framebuffer_reference(fb);
2594 * We've failed to reconstruct the BIOS FB. Current display state
2595 * indicates that the primary plane is visible, but has a NULL FB,
2596 * which will lead to problems later if we don't fix it up. The
2597 * simplest solution is to just disable the primary plane now and
2598 * pretend the BIOS never had it enabled.
2600 to_intel_plane_state(plane_state)->visible = false;
2601 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2602 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2603 intel_plane->disable_plane(primary, &intel_crtc->base);
2608 plane_state->src_x = 0;
2609 plane_state->src_y = 0;
2610 plane_state->src_w = fb->width << 16;
2611 plane_state->src_h = fb->height << 16;
2613 plane_state->crtc_x = 0;
2614 plane_state->crtc_y = 0;
2615 plane_state->crtc_w = fb->width;
2616 plane_state->crtc_h = fb->height;
2618 intel_state->src.x1 = plane_state->src_x;
2619 intel_state->src.y1 = plane_state->src_y;
2620 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2621 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2622 intel_state->dst.x1 = plane_state->crtc_x;
2623 intel_state->dst.y1 = plane_state->crtc_y;
2624 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2625 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2627 obj = intel_fb_obj(fb);
2628 if (obj->tiling_mode != I915_TILING_NONE)
2629 dev_priv->preserve_bios_swizzle = true;
2631 drm_framebuffer_reference(fb);
2632 primary->fb = primary->state->fb = fb;
2633 primary->crtc = primary->state->crtc = &intel_crtc->base;
2634 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2635 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2638 static void i9xx_update_primary_plane(struct drm_plane *primary,
2639 const struct intel_crtc_state *crtc_state,
2640 const struct intel_plane_state *plane_state)
2642 struct drm_device *dev = primary->dev;
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2645 struct drm_framebuffer *fb = plane_state->base.fb;
2646 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2647 int plane = intel_crtc->plane;
2650 i915_reg_t reg = DSPCNTR(plane);
2651 unsigned int rotation = plane_state->base.rotation;
2652 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2653 int x = plane_state->src.x1 >> 16;
2654 int y = plane_state->src.y1 >> 16;
2656 dspcntr = DISPPLANE_GAMMA_ENABLE;
2658 dspcntr |= DISPLAY_PLANE_ENABLE;
2660 if (INTEL_INFO(dev)->gen < 4) {
2661 if (intel_crtc->pipe == PIPE_B)
2662 dspcntr |= DISPPLANE_SEL_PIPE_B;
2664 /* pipesrc and dspsize control the size that is scaled from,
2665 * which should always be the user's requested size.
2667 I915_WRITE(DSPSIZE(plane),
2668 ((crtc_state->pipe_src_h - 1) << 16) |
2669 (crtc_state->pipe_src_w - 1));
2670 I915_WRITE(DSPPOS(plane), 0);
2671 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2672 I915_WRITE(PRIMSIZE(plane),
2673 ((crtc_state->pipe_src_h - 1) << 16) |
2674 (crtc_state->pipe_src_w - 1));
2675 I915_WRITE(PRIMPOS(plane), 0);
2676 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2679 switch (fb->pixel_format) {
2681 dspcntr |= DISPPLANE_8BPP;
2683 case DRM_FORMAT_XRGB1555:
2684 dspcntr |= DISPPLANE_BGRX555;
2686 case DRM_FORMAT_RGB565:
2687 dspcntr |= DISPPLANE_BGRX565;
2689 case DRM_FORMAT_XRGB8888:
2690 dspcntr |= DISPPLANE_BGRX888;
2692 case DRM_FORMAT_XBGR8888:
2693 dspcntr |= DISPPLANE_RGBX888;
2695 case DRM_FORMAT_XRGB2101010:
2696 dspcntr |= DISPPLANE_BGRX101010;
2698 case DRM_FORMAT_XBGR2101010:
2699 dspcntr |= DISPPLANE_RGBX101010;
2705 if (INTEL_INFO(dev)->gen >= 4 &&
2706 obj->tiling_mode != I915_TILING_NONE)
2707 dspcntr |= DISPPLANE_TILED;
2710 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2712 linear_offset = y * fb->pitches[0] + x * cpp;
2714 if (INTEL_INFO(dev)->gen >= 4) {
2715 intel_crtc->dspaddr_offset =
2716 intel_compute_tile_offset(&x, &y, fb, 0,
2717 fb->pitches[0], rotation);
2718 linear_offset -= intel_crtc->dspaddr_offset;
2720 intel_crtc->dspaddr_offset = linear_offset;
2723 if (rotation == BIT(DRM_ROTATE_180)) {
2724 dspcntr |= DISPPLANE_ROTATE_180;
2726 x += (crtc_state->pipe_src_w - 1);
2727 y += (crtc_state->pipe_src_h - 1);
2729 /* Finding the last pixel of the last line of the display
2730 data and adding to linear_offset*/
2732 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2733 (crtc_state->pipe_src_w - 1) * cpp;
2736 intel_crtc->adjusted_x = x;
2737 intel_crtc->adjusted_y = y;
2739 I915_WRITE(reg, dspcntr);
2741 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 I915_WRITE(DSPSURF(plane),
2744 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2745 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2746 I915_WRITE(DSPLINOFF(plane), linear_offset);
2748 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2752 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2753 struct drm_crtc *crtc)
2755 struct drm_device *dev = crtc->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2758 int plane = intel_crtc->plane;
2760 I915_WRITE(DSPCNTR(plane), 0);
2761 if (INTEL_INFO(dev_priv)->gen >= 4)
2762 I915_WRITE(DSPSURF(plane), 0);
2764 I915_WRITE(DSPADDR(plane), 0);
2765 POSTING_READ(DSPCNTR(plane));
2768 static void ironlake_update_primary_plane(struct drm_plane *primary,
2769 const struct intel_crtc_state *crtc_state,
2770 const struct intel_plane_state *plane_state)
2772 struct drm_device *dev = primary->dev;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2775 struct drm_framebuffer *fb = plane_state->base.fb;
2776 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2777 int plane = intel_crtc->plane;
2780 i915_reg_t reg = DSPCNTR(plane);
2781 unsigned int rotation = plane_state->base.rotation;
2782 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2783 int x = plane_state->src.x1 >> 16;
2784 int y = plane_state->src.y1 >> 16;
2786 dspcntr = DISPPLANE_GAMMA_ENABLE;
2787 dspcntr |= DISPLAY_PLANE_ENABLE;
2789 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2790 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2792 switch (fb->pixel_format) {
2794 dspcntr |= DISPPLANE_8BPP;
2796 case DRM_FORMAT_RGB565:
2797 dspcntr |= DISPPLANE_BGRX565;
2799 case DRM_FORMAT_XRGB8888:
2800 dspcntr |= DISPPLANE_BGRX888;
2802 case DRM_FORMAT_XBGR8888:
2803 dspcntr |= DISPPLANE_RGBX888;
2805 case DRM_FORMAT_XRGB2101010:
2806 dspcntr |= DISPPLANE_BGRX101010;
2808 case DRM_FORMAT_XBGR2101010:
2809 dspcntr |= DISPPLANE_RGBX101010;
2815 if (obj->tiling_mode != I915_TILING_NONE)
2816 dspcntr |= DISPPLANE_TILED;
2818 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2821 linear_offset = y * fb->pitches[0] + x * cpp;
2822 intel_crtc->dspaddr_offset =
2823 intel_compute_tile_offset(&x, &y, fb, 0,
2824 fb->pitches[0], rotation);
2825 linear_offset -= intel_crtc->dspaddr_offset;
2826 if (rotation == BIT(DRM_ROTATE_180)) {
2827 dspcntr |= DISPPLANE_ROTATE_180;
2829 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2830 x += (crtc_state->pipe_src_w - 1);
2831 y += (crtc_state->pipe_src_h - 1);
2833 /* Finding the last pixel of the last line of the display
2834 data and adding to linear_offset*/
2836 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2837 (crtc_state->pipe_src_w - 1) * cpp;
2841 intel_crtc->adjusted_x = x;
2842 intel_crtc->adjusted_y = y;
2844 I915_WRITE(reg, dspcntr);
2846 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2847 I915_WRITE(DSPSURF(plane),
2848 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2849 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2850 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2852 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2853 I915_WRITE(DSPLINOFF(plane), linear_offset);
2858 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2859 uint64_t fb_modifier, uint32_t pixel_format)
2861 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2864 int cpp = drm_format_plane_cpp(pixel_format, 0);
2866 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2870 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2871 struct drm_i915_gem_object *obj,
2874 struct i915_ggtt_view view;
2875 struct i915_vma *vma;
2878 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2879 intel_plane->base.state->rotation);
2881 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2882 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2886 offset = vma->node.start;
2889 offset += vma->ggtt_view.params.rotated.uv_start_page *
2893 WARN_ON(upper_32_bits(offset));
2895 return lower_32_bits(offset);
2898 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2900 struct drm_device *dev = intel_crtc->base.dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2903 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2904 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2905 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2909 * This function detaches (aka. unbinds) unused scalers in hardware
2911 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2913 struct intel_crtc_scaler_state *scaler_state;
2916 scaler_state = &intel_crtc->config->scaler_state;
2918 /* loop through and disable scalers that aren't in use */
2919 for (i = 0; i < intel_crtc->num_scalers; i++) {
2920 if (!scaler_state->scalers[i].in_use)
2921 skl_detach_scaler(intel_crtc, i);
2925 u32 skl_plane_ctl_format(uint32_t pixel_format)
2927 switch (pixel_format) {
2929 return PLANE_CTL_FORMAT_INDEXED;
2930 case DRM_FORMAT_RGB565:
2931 return PLANE_CTL_FORMAT_RGB_565;
2932 case DRM_FORMAT_XBGR8888:
2933 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2934 case DRM_FORMAT_XRGB8888:
2935 return PLANE_CTL_FORMAT_XRGB_8888;
2937 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2938 * to be already pre-multiplied. We need to add a knob (or a different
2939 * DRM_FORMAT) for user-space to configure that.
2941 case DRM_FORMAT_ABGR8888:
2942 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2943 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2944 case DRM_FORMAT_ARGB8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888 |
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2947 case DRM_FORMAT_XRGB2101010:
2948 return PLANE_CTL_FORMAT_XRGB_2101010;
2949 case DRM_FORMAT_XBGR2101010:
2950 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2951 case DRM_FORMAT_YUYV:
2952 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2953 case DRM_FORMAT_YVYU:
2954 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2955 case DRM_FORMAT_UYVY:
2956 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2957 case DRM_FORMAT_VYUY:
2958 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2960 MISSING_CASE(pixel_format);
2966 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2968 switch (fb_modifier) {
2969 case DRM_FORMAT_MOD_NONE:
2971 case I915_FORMAT_MOD_X_TILED:
2972 return PLANE_CTL_TILED_X;
2973 case I915_FORMAT_MOD_Y_TILED:
2974 return PLANE_CTL_TILED_Y;
2975 case I915_FORMAT_MOD_Yf_TILED:
2976 return PLANE_CTL_TILED_YF;
2978 MISSING_CASE(fb_modifier);
2984 u32 skl_plane_ctl_rotation(unsigned int rotation)
2987 case BIT(DRM_ROTATE_0):
2990 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2991 * while i915 HW rotation is clockwise, thats why this swapping.
2993 case BIT(DRM_ROTATE_90):
2994 return PLANE_CTL_ROTATE_270;
2995 case BIT(DRM_ROTATE_180):
2996 return PLANE_CTL_ROTATE_180;
2997 case BIT(DRM_ROTATE_270):
2998 return PLANE_CTL_ROTATE_90;
3000 MISSING_CASE(rotation);
3006 static void skylake_update_primary_plane(struct drm_plane *plane,
3007 const struct intel_crtc_state *crtc_state,
3008 const struct intel_plane_state *plane_state)
3010 struct drm_device *dev = plane->dev;
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3013 struct drm_framebuffer *fb = plane_state->base.fb;
3014 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3015 int pipe = intel_crtc->pipe;
3016 u32 plane_ctl, stride_div, stride;
3017 u32 tile_height, plane_offset, plane_size;
3018 unsigned int rotation = plane_state->base.rotation;
3019 int x_offset, y_offset;
3021 int scaler_id = plane_state->scaler_id;
3022 int src_x = plane_state->src.x1 >> 16;
3023 int src_y = plane_state->src.y1 >> 16;
3024 int src_w = drm_rect_width(&plane_state->src) >> 16;
3025 int src_h = drm_rect_height(&plane_state->src) >> 16;
3026 int dst_x = plane_state->dst.x1;
3027 int dst_y = plane_state->dst.y1;
3028 int dst_w = drm_rect_width(&plane_state->dst);
3029 int dst_h = drm_rect_height(&plane_state->dst);
3031 plane_ctl = PLANE_CTL_ENABLE |
3032 PLANE_CTL_PIPE_GAMMA_ENABLE |
3033 PLANE_CTL_PIPE_CSC_ENABLE;
3035 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3036 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3037 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3038 plane_ctl |= skl_plane_ctl_rotation(rotation);
3040 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3042 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3044 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3046 if (intel_rotation_90_or_270(rotation)) {
3047 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3049 /* stride = Surface height in tiles */
3050 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3051 stride = DIV_ROUND_UP(fb->height, tile_height);
3052 x_offset = stride * tile_height - src_y - src_h;
3054 plane_size = (src_w - 1) << 16 | (src_h - 1);
3056 stride = fb->pitches[0] / stride_div;
3059 plane_size = (src_h - 1) << 16 | (src_w - 1);
3061 plane_offset = y_offset << 16 | x_offset;
3063 intel_crtc->adjusted_x = x_offset;
3064 intel_crtc->adjusted_y = y_offset;
3066 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3067 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3068 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3069 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3071 if (scaler_id >= 0) {
3072 uint32_t ps_ctrl = 0;
3074 WARN_ON(!dst_w || !dst_h);
3075 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3076 crtc_state->scaler_state.scalers[scaler_id].mode;
3077 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3078 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3079 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3080 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3081 I915_WRITE(PLANE_POS(pipe, 0), 0);
3083 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3086 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3088 POSTING_READ(PLANE_SURF(pipe, 0));
3091 static void skylake_disable_primary_plane(struct drm_plane *primary,
3092 struct drm_crtc *crtc)
3094 struct drm_device *dev = crtc->dev;
3095 struct drm_i915_private *dev_priv = dev->dev_private;
3096 int pipe = to_intel_crtc(crtc)->pipe;
3098 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3099 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3100 POSTING_READ(PLANE_SURF(pipe, 0));
3103 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3105 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3106 int x, int y, enum mode_set_atomic state)
3108 /* Support for kgdboc is disabled, this needs a major rework. */
3109 DRM_ERROR("legacy panic handler not supported any more.\n");
3114 static void intel_complete_page_flips(struct drm_device *dev)
3116 struct drm_crtc *crtc;
3118 for_each_crtc(dev, crtc) {
3119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3120 enum plane plane = intel_crtc->plane;
3122 intel_prepare_page_flip(dev, plane);
3123 intel_finish_page_flip_plane(dev, plane);
3127 static void intel_update_primary_planes(struct drm_device *dev)
3129 struct drm_crtc *crtc;
3131 for_each_crtc(dev, crtc) {
3132 struct intel_plane *plane = to_intel_plane(crtc->primary);
3133 struct intel_plane_state *plane_state;
3135 drm_modeset_lock_crtc(crtc, &plane->base);
3136 plane_state = to_intel_plane_state(plane->base.state);
3138 if (plane_state->visible)
3139 plane->update_plane(&plane->base,
3140 to_intel_crtc_state(crtc->state),
3143 drm_modeset_unlock_crtc(crtc);
3147 void intel_prepare_reset(struct drm_device *dev)
3149 /* no reset support for gen2 */
3153 /* reset doesn't touch the display */
3154 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3157 drm_modeset_lock_all(dev);
3159 * Disabling the crtcs gracefully seems nicer. Also the
3160 * g33 docs say we should at least disable all the planes.
3162 intel_display_suspend(dev);
3165 void intel_finish_reset(struct drm_device *dev)
3167 struct drm_i915_private *dev_priv = to_i915(dev);
3170 * Flips in the rings will be nuked by the reset,
3171 * so complete all pending flips so that user space
3172 * will get its events and not get stuck.
3174 intel_complete_page_flips(dev);
3176 /* no reset support for gen2 */
3180 /* reset doesn't touch the display */
3181 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3183 * Flips in the rings have been nuked by the reset,
3184 * so update the base address of all primary
3185 * planes to the the last fb to make sure we're
3186 * showing the correct fb after a reset.
3188 * FIXME: Atomic will make this obsolete since we won't schedule
3189 * CS-based flips (which might get lost in gpu resets) any more.
3191 intel_update_primary_planes(dev);
3196 * The display has been reset as well,
3197 * so need a full re-initialization.
3199 intel_runtime_pm_disable_interrupts(dev_priv);
3200 intel_runtime_pm_enable_interrupts(dev_priv);
3202 intel_modeset_init_hw(dev);
3204 spin_lock_irq(&dev_priv->irq_lock);
3205 if (dev_priv->display.hpd_irq_setup)
3206 dev_priv->display.hpd_irq_setup(dev);
3207 spin_unlock_irq(&dev_priv->irq_lock);
3209 intel_display_resume(dev);
3211 intel_hpd_init(dev_priv);
3213 drm_modeset_unlock_all(dev);
3216 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3218 struct drm_device *dev = crtc->dev;
3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3220 unsigned reset_counter;
3223 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3224 if (intel_crtc->reset_counter != reset_counter)
3227 spin_lock_irq(&dev->event_lock);
3228 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3229 spin_unlock_irq(&dev->event_lock);
3234 static void intel_update_pipe_config(struct intel_crtc *crtc,
3235 struct intel_crtc_state *old_crtc_state)
3237 struct drm_device *dev = crtc->base.dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc_state *pipe_config =
3240 to_intel_crtc_state(crtc->base.state);
3242 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3243 crtc->base.mode = crtc->base.state->mode;
3245 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3246 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3247 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3250 * Update pipe size and adjust fitter if needed: the reason for this is
3251 * that in compute_mode_changes we check the native mode (not the pfit
3252 * mode) to see if we can flip rather than do a full mode set. In the
3253 * fastboot case, we'll flip, but if we don't update the pipesrc and
3254 * pfit state, we'll end up with a big fb scanned out into the wrong
3258 I915_WRITE(PIPESRC(crtc->pipe),
3259 ((pipe_config->pipe_src_w - 1) << 16) |
3260 (pipe_config->pipe_src_h - 1));
3262 /* on skylake this is done by detaching scalers */
3263 if (INTEL_INFO(dev)->gen >= 9) {
3264 skl_detach_scalers(crtc);
3266 if (pipe_config->pch_pfit.enabled)
3267 skylake_pfit_enable(crtc);
3268 } else if (HAS_PCH_SPLIT(dev)) {
3269 if (pipe_config->pch_pfit.enabled)
3270 ironlake_pfit_enable(crtc);
3271 else if (old_crtc_state->pch_pfit.enabled)
3272 ironlake_pfit_disable(crtc, true);
3276 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3278 struct drm_device *dev = crtc->dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3281 int pipe = intel_crtc->pipe;
3285 /* enable normal train */
3286 reg = FDI_TX_CTL(pipe);
3287 temp = I915_READ(reg);
3288 if (IS_IVYBRIDGE(dev)) {
3289 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3290 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3292 temp &= ~FDI_LINK_TRAIN_NONE;
3293 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3295 I915_WRITE(reg, temp);
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 if (HAS_PCH_CPT(dev)) {
3300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3303 temp &= ~FDI_LINK_TRAIN_NONE;
3304 temp |= FDI_LINK_TRAIN_NONE;
3306 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3308 /* wait one idle pattern time */
3312 /* IVB wants error correction enabled */
3313 if (IS_IVYBRIDGE(dev))
3314 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3315 FDI_FE_ERRC_ENABLE);
3318 /* The FDI link training functions for ILK/Ibexpeak. */
3319 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3321 struct drm_device *dev = crtc->dev;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
3323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3324 int pipe = intel_crtc->pipe;
3328 /* FDI needs bits from pipe first */
3329 assert_pipe_enabled(dev_priv, pipe);
3331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3333 reg = FDI_RX_IMR(pipe);
3334 temp = I915_READ(reg);
3335 temp &= ~FDI_RX_SYMBOL_LOCK;
3336 temp &= ~FDI_RX_BIT_LOCK;
3337 I915_WRITE(reg, temp);
3341 /* enable CPU FDI TX and PCH FDI RX */
3342 reg = FDI_TX_CTL(pipe);
3343 temp = I915_READ(reg);
3344 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3345 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3346 temp &= ~FDI_LINK_TRAIN_NONE;
3347 temp |= FDI_LINK_TRAIN_PATTERN_1;
3348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3350 reg = FDI_RX_CTL(pipe);
3351 temp = I915_READ(reg);
3352 temp &= ~FDI_LINK_TRAIN_NONE;
3353 temp |= FDI_LINK_TRAIN_PATTERN_1;
3354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3359 /* Ironlake workaround, enable clock pointer after FDI enable*/
3360 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3362 FDI_RX_PHASE_SYNC_POINTER_EN);
3364 reg = FDI_RX_IIR(pipe);
3365 for (tries = 0; tries < 5; tries++) {
3366 temp = I915_READ(reg);
3367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3369 if ((temp & FDI_RX_BIT_LOCK)) {
3370 DRM_DEBUG_KMS("FDI train 1 done.\n");
3371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3376 DRM_ERROR("FDI train 1 fail!\n");
3379 reg = FDI_TX_CTL(pipe);
3380 temp = I915_READ(reg);
3381 temp &= ~FDI_LINK_TRAIN_NONE;
3382 temp |= FDI_LINK_TRAIN_PATTERN_2;
3383 I915_WRITE(reg, temp);
3385 reg = FDI_RX_CTL(pipe);
3386 temp = I915_READ(reg);
3387 temp &= ~FDI_LINK_TRAIN_NONE;
3388 temp |= FDI_LINK_TRAIN_PATTERN_2;
3389 I915_WRITE(reg, temp);
3394 reg = FDI_RX_IIR(pipe);
3395 for (tries = 0; tries < 5; tries++) {
3396 temp = I915_READ(reg);
3397 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3399 if (temp & FDI_RX_SYMBOL_LOCK) {
3400 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3401 DRM_DEBUG_KMS("FDI train 2 done.\n");
3406 DRM_ERROR("FDI train 2 fail!\n");
3408 DRM_DEBUG_KMS("FDI train done\n");
3412 static const int snb_b_fdi_train_param[] = {
3413 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3414 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3415 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3416 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3419 /* The FDI link training functions for SNB/Cougarpoint. */
3420 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3422 struct drm_device *dev = crtc->dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425 int pipe = intel_crtc->pipe;
3429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3431 reg = FDI_RX_IMR(pipe);
3432 temp = I915_READ(reg);
3433 temp &= ~FDI_RX_SYMBOL_LOCK;
3434 temp &= ~FDI_RX_BIT_LOCK;
3435 I915_WRITE(reg, temp);
3440 /* enable CPU FDI TX and PCH FDI RX */
3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_1;
3447 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3449 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3450 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3452 I915_WRITE(FDI_RX_MISC(pipe),
3453 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 if (HAS_PCH_CPT(dev)) {
3458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3459 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3461 temp &= ~FDI_LINK_TRAIN_NONE;
3462 temp |= FDI_LINK_TRAIN_PATTERN_1;
3464 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3469 for (i = 0; i < 4; i++) {
3470 reg = FDI_TX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3473 temp |= snb_b_fdi_train_param[i];
3474 I915_WRITE(reg, temp);
3479 for (retry = 0; retry < 5; retry++) {
3480 reg = FDI_RX_IIR(pipe);
3481 temp = I915_READ(reg);
3482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3483 if (temp & FDI_RX_BIT_LOCK) {
3484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3485 DRM_DEBUG_KMS("FDI train 1 done.\n");
3494 DRM_ERROR("FDI train 1 fail!\n");
3497 reg = FDI_TX_CTL(pipe);
3498 temp = I915_READ(reg);
3499 temp &= ~FDI_LINK_TRAIN_NONE;
3500 temp |= FDI_LINK_TRAIN_PATTERN_2;
3502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3506 I915_WRITE(reg, temp);
3508 reg = FDI_RX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 if (HAS_PCH_CPT(dev)) {
3511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3512 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3514 temp &= ~FDI_LINK_TRAIN_NONE;
3515 temp |= FDI_LINK_TRAIN_PATTERN_2;
3517 I915_WRITE(reg, temp);
3522 for (i = 0; i < 4; i++) {
3523 reg = FDI_TX_CTL(pipe);
3524 temp = I915_READ(reg);
3525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526 temp |= snb_b_fdi_train_param[i];
3527 I915_WRITE(reg, temp);
3532 for (retry = 0; retry < 5; retry++) {
3533 reg = FDI_RX_IIR(pipe);
3534 temp = I915_READ(reg);
3535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3536 if (temp & FDI_RX_SYMBOL_LOCK) {
3537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3538 DRM_DEBUG_KMS("FDI train 2 done.\n");
3547 DRM_ERROR("FDI train 2 fail!\n");
3549 DRM_DEBUG_KMS("FDI train done.\n");
3552 /* Manual link training for Ivy Bridge A0 parts */
3553 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3555 struct drm_device *dev = crtc->dev;
3556 struct drm_i915_private *dev_priv = dev->dev_private;
3557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558 int pipe = intel_crtc->pipe;
3562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3564 reg = FDI_RX_IMR(pipe);
3565 temp = I915_READ(reg);
3566 temp &= ~FDI_RX_SYMBOL_LOCK;
3567 temp &= ~FDI_RX_BIT_LOCK;
3568 I915_WRITE(reg, temp);
3573 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3574 I915_READ(FDI_RX_IIR(pipe)));
3576 /* Try each vswing and preemphasis setting twice before moving on */
3577 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3578 /* disable first in case we need to retry */
3579 reg = FDI_TX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3582 temp &= ~FDI_TX_ENABLE;
3583 I915_WRITE(reg, temp);
3585 reg = FDI_RX_CTL(pipe);
3586 temp = I915_READ(reg);
3587 temp &= ~FDI_LINK_TRAIN_AUTO;
3588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3589 temp &= ~FDI_RX_ENABLE;
3590 I915_WRITE(reg, temp);
3592 /* enable CPU FDI TX and PCH FDI RX */
3593 reg = FDI_TX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3596 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3597 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599 temp |= snb_b_fdi_train_param[j/2];
3600 temp |= FDI_COMPOSITE_SYNC;
3601 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3603 I915_WRITE(FDI_RX_MISC(pipe),
3604 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3606 reg = FDI_RX_CTL(pipe);
3607 temp = I915_READ(reg);
3608 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3609 temp |= FDI_COMPOSITE_SYNC;
3610 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3613 udelay(1); /* should be 0.5us */
3615 for (i = 0; i < 4; i++) {
3616 reg = FDI_RX_IIR(pipe);
3617 temp = I915_READ(reg);
3618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3620 if (temp & FDI_RX_BIT_LOCK ||
3621 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3623 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3627 udelay(1); /* should be 0.5us */
3630 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3635 reg = FDI_TX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3638 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3639 I915_WRITE(reg, temp);
3641 reg = FDI_RX_CTL(pipe);
3642 temp = I915_READ(reg);
3643 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3644 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3645 I915_WRITE(reg, temp);
3648 udelay(2); /* should be 1.5us */
3650 for (i = 0; i < 4; i++) {
3651 reg = FDI_RX_IIR(pipe);
3652 temp = I915_READ(reg);
3653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3655 if (temp & FDI_RX_SYMBOL_LOCK ||
3656 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3657 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3658 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3662 udelay(2); /* should be 1.5us */
3665 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3669 DRM_DEBUG_KMS("FDI train done.\n");
3672 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3674 struct drm_device *dev = intel_crtc->base.dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 int pipe = intel_crtc->pipe;
3680 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3681 reg = FDI_RX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3684 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3685 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3686 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3691 /* Switch from Rawclk to PCDclk */
3692 temp = I915_READ(reg);
3693 I915_WRITE(reg, temp | FDI_PCDCLK);
3698 /* Enable CPU FDI TX PLL, always on for Ironlake */
3699 reg = FDI_TX_CTL(pipe);
3700 temp = I915_READ(reg);
3701 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3702 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3709 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3711 struct drm_device *dev = intel_crtc->base.dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 int pipe = intel_crtc->pipe;
3717 /* Switch from PCDclk to Rawclk */
3718 reg = FDI_RX_CTL(pipe);
3719 temp = I915_READ(reg);
3720 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3722 /* Disable CPU FDI TX PLL */
3723 reg = FDI_TX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3730 reg = FDI_RX_CTL(pipe);
3731 temp = I915_READ(reg);
3732 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3734 /* Wait for the clocks to turn off. */
3739 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3741 struct drm_device *dev = crtc->dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744 int pipe = intel_crtc->pipe;
3748 /* disable CPU FDI tx and PCH FDI rx */
3749 reg = FDI_TX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3754 reg = FDI_RX_CTL(pipe);
3755 temp = I915_READ(reg);
3756 temp &= ~(0x7 << 16);
3757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3763 /* Ironlake workaround, disable clock pointer after downing FDI */
3764 if (HAS_PCH_IBX(dev))
3765 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3767 /* still set train pattern 1 */
3768 reg = FDI_TX_CTL(pipe);
3769 temp = I915_READ(reg);
3770 temp &= ~FDI_LINK_TRAIN_NONE;
3771 temp |= FDI_LINK_TRAIN_PATTERN_1;
3772 I915_WRITE(reg, temp);
3774 reg = FDI_RX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 if (HAS_PCH_CPT(dev)) {
3777 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3778 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3780 temp &= ~FDI_LINK_TRAIN_NONE;
3781 temp |= FDI_LINK_TRAIN_PATTERN_1;
3783 /* BPC in FDI rx is consistent with that in PIPECONF */
3784 temp &= ~(0x07 << 16);
3785 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3786 I915_WRITE(reg, temp);
3792 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3794 struct intel_crtc *crtc;
3796 /* Note that we don't need to be called with mode_config.lock here
3797 * as our list of CRTC objects is static for the lifetime of the
3798 * device and so cannot disappear as we iterate. Similarly, we can
3799 * happily treat the predicates as racy, atomic checks as userspace
3800 * cannot claim and pin a new fb without at least acquring the
3801 * struct_mutex and so serialising with us.
3803 for_each_intel_crtc(dev, crtc) {
3804 if (atomic_read(&crtc->unpin_work_count) == 0)
3807 if (crtc->unpin_work)
3808 intel_wait_for_vblank(dev, crtc->pipe);
3816 static void page_flip_completed(struct intel_crtc *intel_crtc)
3818 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3819 struct intel_unpin_work *work = intel_crtc->unpin_work;
3821 /* ensure that the unpin work is consistent wrt ->pending. */
3823 intel_crtc->unpin_work = NULL;
3826 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3828 drm_crtc_vblank_put(&intel_crtc->base);
3830 wake_up_all(&dev_priv->pending_flip_queue);
3831 queue_work(dev_priv->wq, &work->work);
3833 trace_i915_flip_complete(intel_crtc->plane,
3834 work->pending_flip_obj);
3837 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3839 struct drm_device *dev = crtc->dev;
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3843 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3845 ret = wait_event_interruptible_timeout(
3846 dev_priv->pending_flip_queue,
3847 !intel_crtc_has_pending_flip(crtc),
3854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856 spin_lock_irq(&dev->event_lock);
3857 if (intel_crtc->unpin_work) {
3858 WARN_ONCE(1, "Removing stuck page flip\n");
3859 page_flip_completed(intel_crtc);
3861 spin_unlock_irq(&dev->event_lock);
3867 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3871 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3873 mutex_lock(&dev_priv->sb_lock);
3875 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3876 temp |= SBI_SSCCTL_DISABLE;
3877 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3879 mutex_unlock(&dev_priv->sb_lock);
3882 /* Program iCLKIP clock to the desired frequency */
3883 static void lpt_program_iclkip(struct drm_crtc *crtc)
3885 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3886 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3887 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3890 lpt_disable_iclkip(dev_priv);
3892 /* The iCLK virtual clock root frequency is in MHz,
3893 * but the adjusted_mode->crtc_clock in in KHz. To get the
3894 * divisors, it is necessary to divide one by another, so we
3895 * convert the virtual clock precision to KHz here for higher
3898 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3899 u32 iclk_virtual_root_freq = 172800 * 1000;
3900 u32 iclk_pi_range = 64;
3901 u32 desired_divisor;
3903 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3905 divsel = (desired_divisor / iclk_pi_range) - 2;
3906 phaseinc = desired_divisor % iclk_pi_range;
3909 * Near 20MHz is a corner case which is
3910 * out of range for the 7-bit divisor
3916 /* This should not happen with any sane values */
3917 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3918 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3919 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3920 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3922 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3929 mutex_lock(&dev_priv->sb_lock);
3931 /* Program SSCDIVINTPHASE6 */
3932 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3933 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3934 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3935 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3936 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3937 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3938 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3939 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3941 /* Program SSCAUXDIV */
3942 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3943 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3944 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3945 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3947 /* Enable modulator and associated divider */
3948 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3949 temp &= ~SBI_SSCCTL_DISABLE;
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3952 mutex_unlock(&dev_priv->sb_lock);
3954 /* Wait for initialization time */
3957 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3960 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3962 u32 divsel, phaseinc, auxdiv;
3963 u32 iclk_virtual_root_freq = 172800 * 1000;
3964 u32 iclk_pi_range = 64;
3965 u32 desired_divisor;
3968 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3971 mutex_lock(&dev_priv->sb_lock);
3973 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3974 if (temp & SBI_SSCCTL_DISABLE) {
3975 mutex_unlock(&dev_priv->sb_lock);
3979 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3980 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3981 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3982 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3983 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3985 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3986 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3987 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3989 mutex_unlock(&dev_priv->sb_lock);
3991 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3993 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3994 desired_divisor << auxdiv);
3997 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3998 enum pipe pch_transcoder)
4000 struct drm_device *dev = crtc->base.dev;
4001 struct drm_i915_private *dev_priv = dev->dev_private;
4002 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4004 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4005 I915_READ(HTOTAL(cpu_transcoder)));
4006 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4007 I915_READ(HBLANK(cpu_transcoder)));
4008 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4009 I915_READ(HSYNC(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4012 I915_READ(VTOTAL(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4014 I915_READ(VBLANK(cpu_transcoder)));
4015 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4016 I915_READ(VSYNC(cpu_transcoder)));
4017 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4018 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4021 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4023 struct drm_i915_private *dev_priv = dev->dev_private;
4026 temp = I915_READ(SOUTH_CHICKEN1);
4027 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4030 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4031 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4033 temp &= ~FDI_BC_BIFURCATION_SELECT;
4035 temp |= FDI_BC_BIFURCATION_SELECT;
4037 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4038 I915_WRITE(SOUTH_CHICKEN1, temp);
4039 POSTING_READ(SOUTH_CHICKEN1);
4042 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4044 struct drm_device *dev = intel_crtc->base.dev;
4046 switch (intel_crtc->pipe) {
4050 if (intel_crtc->config->fdi_lanes > 2)
4051 cpt_set_fdi_bc_bifurcation(dev, false);
4053 cpt_set_fdi_bc_bifurcation(dev, true);
4057 cpt_set_fdi_bc_bifurcation(dev, true);
4065 /* Return which DP Port should be selected for Transcoder DP control */
4067 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4069 struct drm_device *dev = crtc->dev;
4070 struct intel_encoder *encoder;
4072 for_each_encoder_on_crtc(dev, crtc, encoder) {
4073 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4074 encoder->type == INTEL_OUTPUT_EDP)
4075 return enc_to_dig_port(&encoder->base)->port;
4082 * Enable PCH resources required for PCH ports:
4084 * - FDI training & RX/TX
4085 * - update transcoder timings
4086 * - DP transcoding bits
4089 static void ironlake_pch_enable(struct drm_crtc *crtc)
4091 struct drm_device *dev = crtc->dev;
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4094 int pipe = intel_crtc->pipe;
4097 assert_pch_transcoder_disabled(dev_priv, pipe);
4099 if (IS_IVYBRIDGE(dev))
4100 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4102 /* Write the TU size bits before fdi link training, so that error
4103 * detection works. */
4104 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4105 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4107 /* For PCH output, training FDI link */
4108 dev_priv->display.fdi_link_train(crtc);
4110 /* We need to program the right clock selection before writing the pixel
4111 * mutliplier into the DPLL. */
4112 if (HAS_PCH_CPT(dev)) {
4115 temp = I915_READ(PCH_DPLL_SEL);
4116 temp |= TRANS_DPLL_ENABLE(pipe);
4117 sel = TRANS_DPLLB_SEL(pipe);
4118 if (intel_crtc->config->shared_dpll ==
4119 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4123 I915_WRITE(PCH_DPLL_SEL, temp);
4126 /* XXX: pch pll's can be enabled any time before we enable the PCH
4127 * transcoder, and we actually should do this to not upset any PCH
4128 * transcoder that already use the clock when we share it.
4130 * Note that enable_shared_dpll tries to do the right thing, but
4131 * get_shared_dpll unconditionally resets the pll - we need that to have
4132 * the right LVDS enable sequence. */
4133 intel_enable_shared_dpll(intel_crtc);
4135 /* set transcoder timing, panel must allow it */
4136 assert_panel_unlocked(dev_priv, pipe);
4137 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4139 intel_fdi_normal_train(crtc);
4141 /* For PCH DP, enable TRANS_DP_CTL */
4142 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4143 const struct drm_display_mode *adjusted_mode =
4144 &intel_crtc->config->base.adjusted_mode;
4145 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4146 i915_reg_t reg = TRANS_DP_CTL(pipe);
4147 temp = I915_READ(reg);
4148 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4149 TRANS_DP_SYNC_MASK |
4151 temp |= TRANS_DP_OUTPUT_ENABLE;
4152 temp |= bpc << 9; /* same format but at 11:9 */
4154 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4155 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4156 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4157 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4159 switch (intel_trans_dp_port_sel(crtc)) {
4161 temp |= TRANS_DP_PORT_SEL_B;
4164 temp |= TRANS_DP_PORT_SEL_C;
4167 temp |= TRANS_DP_PORT_SEL_D;
4173 I915_WRITE(reg, temp);
4176 ironlake_enable_pch_transcoder(dev_priv, pipe);
4179 static void lpt_pch_enable(struct drm_crtc *crtc)
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4186 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4188 lpt_program_iclkip(crtc);
4190 /* Set transcoder timing. */
4191 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4193 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4196 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199 i915_reg_t dslreg = PIPEDSL(pipe);
4202 temp = I915_READ(dslreg);
4204 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4205 if (wait_for(I915_READ(dslreg) != temp, 5))
4206 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4211 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4212 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4213 int src_w, int src_h, int dst_w, int dst_h)
4215 struct intel_crtc_scaler_state *scaler_state =
4216 &crtc_state->scaler_state;
4217 struct intel_crtc *intel_crtc =
4218 to_intel_crtc(crtc_state->base.crtc);
4221 need_scaling = intel_rotation_90_or_270(rotation) ?
4222 (src_h != dst_w || src_w != dst_h):
4223 (src_w != dst_w || src_h != dst_h);
4226 * if plane is being disabled or scaler is no more required or force detach
4227 * - free scaler binded to this plane/crtc
4228 * - in order to do this, update crtc->scaler_usage
4230 * Here scaler state in crtc_state is set free so that
4231 * scaler can be assigned to other user. Actual register
4232 * update to free the scaler is done in plane/panel-fit programming.
4233 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4235 if (force_detach || !need_scaling) {
4236 if (*scaler_id >= 0) {
4237 scaler_state->scaler_users &= ~(1 << scaler_user);
4238 scaler_state->scalers[*scaler_id].in_use = 0;
4240 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4241 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4242 intel_crtc->pipe, scaler_user, *scaler_id,
4243 scaler_state->scaler_users);
4250 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4251 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4253 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4254 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4255 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4256 "size is out of scaler range\n",
4257 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4261 /* mark this plane as a scaler user in crtc_state */
4262 scaler_state->scaler_users |= (1 << scaler_user);
4263 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4264 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4265 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4266 scaler_state->scaler_users);
4272 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4274 * @state: crtc's scaler state
4277 * 0 - scaler_usage updated successfully
4278 * error - requested scaling cannot be supported or other error condition
4280 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4282 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4283 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4285 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4286 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4288 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4289 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4290 state->pipe_src_w, state->pipe_src_h,
4291 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4295 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4297 * @state: crtc's scaler state
4298 * @plane_state: atomic plane state to update
4301 * 0 - scaler_usage updated successfully
4302 * error - requested scaling cannot be supported or other error condition
4304 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4305 struct intel_plane_state *plane_state)
4308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4309 struct intel_plane *intel_plane =
4310 to_intel_plane(plane_state->base.plane);
4311 struct drm_framebuffer *fb = plane_state->base.fb;
4314 bool force_detach = !fb || !plane_state->visible;
4316 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4317 intel_plane->base.base.id, intel_crtc->pipe,
4318 drm_plane_index(&intel_plane->base));
4320 ret = skl_update_scaler(crtc_state, force_detach,
4321 drm_plane_index(&intel_plane->base),
4322 &plane_state->scaler_id,
4323 plane_state->base.rotation,
4324 drm_rect_width(&plane_state->src) >> 16,
4325 drm_rect_height(&plane_state->src) >> 16,
4326 drm_rect_width(&plane_state->dst),
4327 drm_rect_height(&plane_state->dst));
4329 if (ret || plane_state->scaler_id < 0)
4332 /* check colorkey */
4333 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4334 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4335 intel_plane->base.base.id);
4339 /* Check src format */
4340 switch (fb->pixel_format) {
4341 case DRM_FORMAT_RGB565:
4342 case DRM_FORMAT_XBGR8888:
4343 case DRM_FORMAT_XRGB8888:
4344 case DRM_FORMAT_ABGR8888:
4345 case DRM_FORMAT_ARGB8888:
4346 case DRM_FORMAT_XRGB2101010:
4347 case DRM_FORMAT_XBGR2101010:
4348 case DRM_FORMAT_YUYV:
4349 case DRM_FORMAT_YVYU:
4350 case DRM_FORMAT_UYVY:
4351 case DRM_FORMAT_VYUY:
4354 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4355 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4362 static void skylake_scaler_disable(struct intel_crtc *crtc)
4366 for (i = 0; i < crtc->num_scalers; i++)
4367 skl_detach_scaler(crtc, i);
4370 static void skylake_pfit_enable(struct intel_crtc *crtc)
4372 struct drm_device *dev = crtc->base.dev;
4373 struct drm_i915_private *dev_priv = dev->dev_private;
4374 int pipe = crtc->pipe;
4375 struct intel_crtc_scaler_state *scaler_state =
4376 &crtc->config->scaler_state;
4378 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4380 if (crtc->config->pch_pfit.enabled) {
4383 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4384 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4388 id = scaler_state->scaler_id;
4389 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4390 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4391 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4392 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4394 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4398 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4400 struct drm_device *dev = crtc->base.dev;
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 int pipe = crtc->pipe;
4404 if (crtc->config->pch_pfit.enabled) {
4405 /* Force use of hard-coded filter coefficients
4406 * as some pre-programmed values are broken,
4409 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4410 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4411 PF_PIPE_SEL_IVB(pipe));
4413 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4414 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4415 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4419 void hsw_enable_ips(struct intel_crtc *crtc)
4421 struct drm_device *dev = crtc->base.dev;
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4424 if (!crtc->config->ips_enabled)
4428 * We can only enable IPS after we enable a plane and wait for a vblank
4429 * This function is called from post_plane_update, which is run after
4433 assert_plane_enabled(dev_priv, crtc->plane);
4434 if (IS_BROADWELL(dev)) {
4435 mutex_lock(&dev_priv->rps.hw_lock);
4436 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4437 mutex_unlock(&dev_priv->rps.hw_lock);
4438 /* Quoting Art Runyan: "its not safe to expect any particular
4439 * value in IPS_CTL bit 31 after enabling IPS through the
4440 * mailbox." Moreover, the mailbox may return a bogus state,
4441 * so we need to just enable it and continue on.
4444 I915_WRITE(IPS_CTL, IPS_ENABLE);
4445 /* The bit only becomes 1 in the next vblank, so this wait here
4446 * is essentially intel_wait_for_vblank. If we don't have this
4447 * and don't wait for vblanks until the end of crtc_enable, then
4448 * the HW state readout code will complain that the expected
4449 * IPS_CTL value is not the one we read. */
4450 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4451 DRM_ERROR("Timed out waiting for IPS enable\n");
4455 void hsw_disable_ips(struct intel_crtc *crtc)
4457 struct drm_device *dev = crtc->base.dev;
4458 struct drm_i915_private *dev_priv = dev->dev_private;
4460 if (!crtc->config->ips_enabled)
4463 assert_plane_enabled(dev_priv, crtc->plane);
4464 if (IS_BROADWELL(dev)) {
4465 mutex_lock(&dev_priv->rps.hw_lock);
4466 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4467 mutex_unlock(&dev_priv->rps.hw_lock);
4468 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4469 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4470 DRM_ERROR("Timed out waiting for IPS disable\n");
4472 I915_WRITE(IPS_CTL, 0);
4473 POSTING_READ(IPS_CTL);
4476 /* We need to wait for a vblank before we can disable the plane. */
4477 intel_wait_for_vblank(dev, crtc->pipe);
4480 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4482 if (intel_crtc->overlay) {
4483 struct drm_device *dev = intel_crtc->base.dev;
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4486 mutex_lock(&dev->struct_mutex);
4487 dev_priv->mm.interruptible = false;
4488 (void) intel_overlay_switch_off(intel_crtc->overlay);
4489 dev_priv->mm.interruptible = true;
4490 mutex_unlock(&dev->struct_mutex);
4493 /* Let userspace switch the overlay on again. In most cases userspace
4494 * has to recompute where to put it anyway.
4499 * intel_post_enable_primary - Perform operations after enabling primary plane
4500 * @crtc: the CRTC whose primary plane was just enabled
4502 * Performs potentially sleeping operations that must be done after the primary
4503 * plane is enabled, such as updating FBC and IPS. Note that this may be
4504 * called due to an explicit primary plane update, or due to an implicit
4505 * re-enable that is caused when a sprite plane is updated to no longer
4506 * completely hide the primary plane.
4509 intel_post_enable_primary(struct drm_crtc *crtc)
4511 struct drm_device *dev = crtc->dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514 int pipe = intel_crtc->pipe;
4517 * FIXME IPS should be fine as long as one plane is
4518 * enabled, but in practice it seems to have problems
4519 * when going from primary only to sprite only and vice
4522 hsw_enable_ips(intel_crtc);
4525 * Gen2 reports pipe underruns whenever all planes are disabled.
4526 * So don't enable underrun reporting before at least some planes
4528 * FIXME: Need to fix the logic to work when we turn off all planes
4529 * but leave the pipe running.
4532 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4534 /* Underruns don't always raise interrupts, so check manually. */
4535 intel_check_cpu_fifo_underruns(dev_priv);
4536 intel_check_pch_fifo_underruns(dev_priv);
4539 /* FIXME move all this to pre_plane_update() with proper state tracking */
4541 intel_pre_disable_primary(struct drm_crtc *crtc)
4543 struct drm_device *dev = crtc->dev;
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4546 int pipe = intel_crtc->pipe;
4549 * Gen2 reports pipe underruns whenever all planes are disabled.
4550 * So diasble underrun reporting before all the planes get disabled.
4551 * FIXME: Need to fix the logic to work when we turn off all planes
4552 * but leave the pipe running.
4555 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4558 * FIXME IPS should be fine as long as one plane is
4559 * enabled, but in practice it seems to have problems
4560 * when going from primary only to sprite only and vice
4563 hsw_disable_ips(intel_crtc);
4566 /* FIXME get rid of this and use pre_plane_update */
4568 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4570 struct drm_device *dev = crtc->dev;
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4573 int pipe = intel_crtc->pipe;
4575 intel_pre_disable_primary(crtc);
4578 * Vblank time updates from the shadow to live plane control register
4579 * are blocked if the memory self-refresh mode is active at that
4580 * moment. So to make sure the plane gets truly disabled, disable
4581 * first the self-refresh mode. The self-refresh enable bit in turn
4582 * will be checked/applied by the HW only at the next frame start
4583 * event which is after the vblank start event, so we need to have a
4584 * wait-for-vblank between disabling the plane and the pipe.
4586 if (HAS_GMCH_DISPLAY(dev)) {
4587 intel_set_memory_cxsr(dev_priv, false);
4588 dev_priv->wm.vlv.cxsr = false;
4589 intel_wait_for_vblank(dev, pipe);
4593 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4595 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4596 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4597 struct intel_crtc_state *pipe_config =
4598 to_intel_crtc_state(crtc->base.state);
4599 struct drm_device *dev = crtc->base.dev;
4600 struct drm_plane *primary = crtc->base.primary;
4601 struct drm_plane_state *old_pri_state =
4602 drm_atomic_get_existing_plane_state(old_state, primary);
4604 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4606 crtc->wm.cxsr_allowed = true;
4608 if (pipe_config->update_wm_post && pipe_config->base.active)
4609 intel_update_watermarks(&crtc->base);
4611 if (old_pri_state) {
4612 struct intel_plane_state *primary_state =
4613 to_intel_plane_state(primary->state);
4614 struct intel_plane_state *old_primary_state =
4615 to_intel_plane_state(old_pri_state);
4617 intel_fbc_post_update(crtc);
4619 if (primary_state->visible &&
4620 (needs_modeset(&pipe_config->base) ||
4621 !old_primary_state->visible))
4622 intel_post_enable_primary(&crtc->base);
4626 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4628 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4629 struct drm_device *dev = crtc->base.dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 struct intel_crtc_state *pipe_config =
4632 to_intel_crtc_state(crtc->base.state);
4633 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4634 struct drm_plane *primary = crtc->base.primary;
4635 struct drm_plane_state *old_pri_state =
4636 drm_atomic_get_existing_plane_state(old_state, primary);
4637 bool modeset = needs_modeset(&pipe_config->base);
4639 if (old_pri_state) {
4640 struct intel_plane_state *primary_state =
4641 to_intel_plane_state(primary->state);
4642 struct intel_plane_state *old_primary_state =
4643 to_intel_plane_state(old_pri_state);
4645 intel_fbc_pre_update(crtc);
4647 if (old_primary_state->visible &&
4648 (modeset || !primary_state->visible))
4649 intel_pre_disable_primary(&crtc->base);
4652 if (pipe_config->disable_cxsr) {
4653 crtc->wm.cxsr_allowed = false;
4656 * Vblank time updates from the shadow to live plane control register
4657 * are blocked if the memory self-refresh mode is active at that
4658 * moment. So to make sure the plane gets truly disabled, disable
4659 * first the self-refresh mode. The self-refresh enable bit in turn
4660 * will be checked/applied by the HW only at the next frame start
4661 * event which is after the vblank start event, so we need to have a
4662 * wait-for-vblank between disabling the plane and the pipe.
4664 if (old_crtc_state->base.active) {
4665 intel_set_memory_cxsr(dev_priv, false);
4666 dev_priv->wm.vlv.cxsr = false;
4667 intel_wait_for_vblank(dev, crtc->pipe);
4672 * IVB workaround: must disable low power watermarks for at least
4673 * one frame before enabling scaling. LP watermarks can be re-enabled
4674 * when scaling is disabled.
4676 * WaCxSRDisabledForSpriteScaling:ivb
4678 if (pipe_config->disable_lp_wm) {
4679 ilk_disable_lp_wm(dev);
4680 intel_wait_for_vblank(dev, crtc->pipe);
4684 * If we're doing a modeset, we're done. No need to do any pre-vblank
4685 * watermark programming here.
4687 if (needs_modeset(&pipe_config->base))
4691 * For platforms that support atomic watermarks, program the
4692 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4693 * will be the intermediate values that are safe for both pre- and
4694 * post- vblank; when vblank happens, the 'active' values will be set
4695 * to the final 'target' values and we'll do this again to get the
4696 * optimal watermarks. For gen9+ platforms, the values we program here
4697 * will be the final target values which will get automatically latched
4698 * at vblank time; no further programming will be necessary.
4700 * If a platform hasn't been transitioned to atomic watermarks yet,
4701 * we'll continue to update watermarks the old way, if flags tell
4704 if (dev_priv->display.initial_watermarks != NULL)
4705 dev_priv->display.initial_watermarks(pipe_config);
4706 else if (pipe_config->update_wm_pre)
4707 intel_update_watermarks(&crtc->base);
4710 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4712 struct drm_device *dev = crtc->dev;
4713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4714 struct drm_plane *p;
4715 int pipe = intel_crtc->pipe;
4717 intel_crtc_dpms_overlay_disable(intel_crtc);
4719 drm_for_each_plane_mask(p, dev, plane_mask)
4720 to_intel_plane(p)->disable_plane(p, crtc);
4723 * FIXME: Once we grow proper nuclear flip support out of this we need
4724 * to compute the mask of flip planes precisely. For the time being
4725 * consider this a flip to a NULL plane.
4727 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4730 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4732 struct drm_device *dev = crtc->dev;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4735 struct intel_encoder *encoder;
4736 int pipe = intel_crtc->pipe;
4737 struct intel_crtc_state *pipe_config =
4738 to_intel_crtc_state(crtc->state);
4740 if (WARN_ON(intel_crtc->active))
4744 * Sometimes spurious CPU pipe underruns happen during FDI
4745 * training, at least with VGA+HDMI cloning. Suppress them.
4747 * On ILK we get an occasional spurious CPU pipe underruns
4748 * between eDP port A enable and vdd enable. Also PCH port
4749 * enable seems to result in the occasional CPU pipe underrun.
4751 * Spurious PCH underruns also occur during PCH enabling.
4753 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4754 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4755 if (intel_crtc->config->has_pch_encoder)
4756 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4758 if (intel_crtc->config->has_pch_encoder)
4759 intel_prepare_shared_dpll(intel_crtc);
4761 if (intel_crtc->config->has_dp_encoder)
4762 intel_dp_set_m_n(intel_crtc, M1_N1);
4764 intel_set_pipe_timings(intel_crtc);
4765 intel_set_pipe_src_size(intel_crtc);
4767 if (intel_crtc->config->has_pch_encoder) {
4768 intel_cpu_transcoder_set_m_n(intel_crtc,
4769 &intel_crtc->config->fdi_m_n, NULL);
4772 ironlake_set_pipeconf(crtc);
4774 intel_crtc->active = true;
4776 for_each_encoder_on_crtc(dev, crtc, encoder)
4777 if (encoder->pre_enable)
4778 encoder->pre_enable(encoder);
4780 if (intel_crtc->config->has_pch_encoder) {
4781 /* Note: FDI PLL enabling _must_ be done before we enable the
4782 * cpu pipes, hence this is separate from all the other fdi/pch
4784 ironlake_fdi_pll_enable(intel_crtc);
4786 assert_fdi_tx_disabled(dev_priv, pipe);
4787 assert_fdi_rx_disabled(dev_priv, pipe);
4790 ironlake_pfit_enable(intel_crtc);
4793 * On ILK+ LUT must be loaded before the pipe is running but with
4796 intel_color_load_luts(&pipe_config->base);
4798 if (dev_priv->display.initial_watermarks != NULL)
4799 dev_priv->display.initial_watermarks(intel_crtc->config);
4800 intel_enable_pipe(intel_crtc);
4802 if (intel_crtc->config->has_pch_encoder)
4803 ironlake_pch_enable(crtc);
4805 assert_vblank_disabled(crtc);
4806 drm_crtc_vblank_on(crtc);
4808 for_each_encoder_on_crtc(dev, crtc, encoder)
4809 encoder->enable(encoder);
4811 if (HAS_PCH_CPT(dev))
4812 cpt_verify_modeset(dev, intel_crtc->pipe);
4814 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4815 if (intel_crtc->config->has_pch_encoder)
4816 intel_wait_for_vblank(dev, pipe);
4817 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4818 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4821 /* IPS only exists on ULT machines and is tied to pipe A. */
4822 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4824 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4827 static void haswell_crtc_enable(struct drm_crtc *crtc)
4829 struct drm_device *dev = crtc->dev;
4830 struct drm_i915_private *dev_priv = dev->dev_private;
4831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832 struct intel_encoder *encoder;
4833 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4834 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4835 struct intel_crtc_state *pipe_config =
4836 to_intel_crtc_state(crtc->state);
4838 if (WARN_ON(intel_crtc->active))
4841 if (intel_crtc->config->has_pch_encoder)
4842 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4845 if (intel_crtc->config->shared_dpll)
4846 intel_enable_shared_dpll(intel_crtc);
4848 if (intel_crtc->config->has_dp_encoder)
4849 intel_dp_set_m_n(intel_crtc, M1_N1);
4851 if (!intel_crtc->config->has_dsi_encoder)
4852 intel_set_pipe_timings(intel_crtc);
4854 intel_set_pipe_src_size(intel_crtc);
4856 if (cpu_transcoder != TRANSCODER_EDP &&
4857 !transcoder_is_dsi(cpu_transcoder)) {
4858 I915_WRITE(PIPE_MULT(cpu_transcoder),
4859 intel_crtc->config->pixel_multiplier - 1);
4862 if (intel_crtc->config->has_pch_encoder) {
4863 intel_cpu_transcoder_set_m_n(intel_crtc,
4864 &intel_crtc->config->fdi_m_n, NULL);
4867 if (!intel_crtc->config->has_dsi_encoder)
4868 haswell_set_pipeconf(crtc);
4870 haswell_set_pipemisc(crtc);
4872 intel_color_set_csc(&pipe_config->base);
4874 intel_crtc->active = true;
4876 if (intel_crtc->config->has_pch_encoder)
4877 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4879 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4881 for_each_encoder_on_crtc(dev, crtc, encoder) {
4882 if (encoder->pre_enable)
4883 encoder->pre_enable(encoder);
4886 if (intel_crtc->config->has_pch_encoder)
4887 dev_priv->display.fdi_link_train(crtc);
4889 if (!intel_crtc->config->has_dsi_encoder)
4890 intel_ddi_enable_pipe_clock(intel_crtc);
4892 if (INTEL_INFO(dev)->gen >= 9)
4893 skylake_pfit_enable(intel_crtc);
4895 ironlake_pfit_enable(intel_crtc);
4898 * On ILK+ LUT must be loaded before the pipe is running but with
4901 intel_color_load_luts(&pipe_config->base);
4903 intel_ddi_set_pipe_settings(crtc);
4904 if (!intel_crtc->config->has_dsi_encoder)
4905 intel_ddi_enable_transcoder_func(crtc);
4907 if (dev_priv->display.initial_watermarks != NULL)
4908 dev_priv->display.initial_watermarks(pipe_config);
4910 intel_update_watermarks(crtc);
4912 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4913 if (!intel_crtc->config->has_dsi_encoder)
4914 intel_enable_pipe(intel_crtc);
4916 if (intel_crtc->config->has_pch_encoder)
4917 lpt_pch_enable(crtc);
4919 if (intel_crtc->config->dp_encoder_is_mst)
4920 intel_ddi_set_vc_payload_alloc(crtc, true);
4922 assert_vblank_disabled(crtc);
4923 drm_crtc_vblank_on(crtc);
4925 for_each_encoder_on_crtc(dev, crtc, encoder) {
4926 encoder->enable(encoder);
4927 intel_opregion_notify_encoder(encoder, true);
4930 if (intel_crtc->config->has_pch_encoder) {
4931 intel_wait_for_vblank(dev, pipe);
4932 intel_wait_for_vblank(dev, pipe);
4933 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4938 /* If we change the relative order between pipe/planes enabling, we need
4939 * to change the workaround. */
4940 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4941 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4942 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4943 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4947 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4949 struct drm_device *dev = crtc->base.dev;
4950 struct drm_i915_private *dev_priv = dev->dev_private;
4951 int pipe = crtc->pipe;
4953 /* To avoid upsetting the power well on haswell only disable the pfit if
4954 * it's in use. The hw state code will make sure we get this right. */
4955 if (force || crtc->config->pch_pfit.enabled) {
4956 I915_WRITE(PF_CTL(pipe), 0);
4957 I915_WRITE(PF_WIN_POS(pipe), 0);
4958 I915_WRITE(PF_WIN_SZ(pipe), 0);
4962 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4964 struct drm_device *dev = crtc->dev;
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 struct intel_encoder *encoder;
4968 int pipe = intel_crtc->pipe;
4971 * Sometimes spurious CPU pipe underruns happen when the
4972 * pipe is already disabled, but FDI RX/TX is still enabled.
4973 * Happens at least with VGA+HDMI cloning. Suppress them.
4975 if (intel_crtc->config->has_pch_encoder) {
4976 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4977 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4980 for_each_encoder_on_crtc(dev, crtc, encoder)
4981 encoder->disable(encoder);
4983 drm_crtc_vblank_off(crtc);
4984 assert_vblank_disabled(crtc);
4986 intel_disable_pipe(intel_crtc);
4988 ironlake_pfit_disable(intel_crtc, false);
4990 if (intel_crtc->config->has_pch_encoder)
4991 ironlake_fdi_disable(crtc);
4993 for_each_encoder_on_crtc(dev, crtc, encoder)
4994 if (encoder->post_disable)
4995 encoder->post_disable(encoder);
4997 if (intel_crtc->config->has_pch_encoder) {
4998 ironlake_disable_pch_transcoder(dev_priv, pipe);
5000 if (HAS_PCH_CPT(dev)) {
5004 /* disable TRANS_DP_CTL */
5005 reg = TRANS_DP_CTL(pipe);
5006 temp = I915_READ(reg);
5007 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5008 TRANS_DP_PORT_SEL_MASK);
5009 temp |= TRANS_DP_PORT_SEL_NONE;
5010 I915_WRITE(reg, temp);
5012 /* disable DPLL_SEL */
5013 temp = I915_READ(PCH_DPLL_SEL);
5014 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5015 I915_WRITE(PCH_DPLL_SEL, temp);
5018 ironlake_fdi_pll_disable(intel_crtc);
5021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5022 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5025 static void haswell_crtc_disable(struct drm_crtc *crtc)
5027 struct drm_device *dev = crtc->dev;
5028 struct drm_i915_private *dev_priv = dev->dev_private;
5029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030 struct intel_encoder *encoder;
5031 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5033 if (intel_crtc->config->has_pch_encoder)
5034 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5037 for_each_encoder_on_crtc(dev, crtc, encoder) {
5038 intel_opregion_notify_encoder(encoder, false);
5039 encoder->disable(encoder);
5042 drm_crtc_vblank_off(crtc);
5043 assert_vblank_disabled(crtc);
5045 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5046 if (!intel_crtc->config->has_dsi_encoder)
5047 intel_disable_pipe(intel_crtc);
5049 if (intel_crtc->config->dp_encoder_is_mst)
5050 intel_ddi_set_vc_payload_alloc(crtc, false);
5052 if (!intel_crtc->config->has_dsi_encoder)
5053 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5055 if (INTEL_INFO(dev)->gen >= 9)
5056 skylake_scaler_disable(intel_crtc);
5058 ironlake_pfit_disable(intel_crtc, false);
5060 if (!intel_crtc->config->has_dsi_encoder)
5061 intel_ddi_disable_pipe_clock(intel_crtc);
5063 for_each_encoder_on_crtc(dev, crtc, encoder)
5064 if (encoder->post_disable)
5065 encoder->post_disable(encoder);
5067 if (intel_crtc->config->has_pch_encoder) {
5068 lpt_disable_pch_transcoder(dev_priv);
5069 lpt_disable_iclkip(dev_priv);
5070 intel_ddi_fdi_disable(crtc);
5072 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5077 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5079 struct drm_device *dev = crtc->base.dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_crtc_state *pipe_config = crtc->config;
5083 if (!pipe_config->gmch_pfit.control)
5087 * The panel fitter should only be adjusted whilst the pipe is disabled,
5088 * according to register description and PRM.
5090 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5091 assert_pipe_disabled(dev_priv, crtc->pipe);
5093 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5094 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5096 /* Border color in case we don't scale up to the full screen. Black by
5097 * default, change to something else for debugging. */
5098 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5101 static enum intel_display_power_domain port_to_power_domain(enum port port)
5105 return POWER_DOMAIN_PORT_DDI_A_LANES;
5107 return POWER_DOMAIN_PORT_DDI_B_LANES;
5109 return POWER_DOMAIN_PORT_DDI_C_LANES;
5111 return POWER_DOMAIN_PORT_DDI_D_LANES;
5113 return POWER_DOMAIN_PORT_DDI_E_LANES;
5116 return POWER_DOMAIN_PORT_OTHER;
5120 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5124 return POWER_DOMAIN_AUX_A;
5126 return POWER_DOMAIN_AUX_B;
5128 return POWER_DOMAIN_AUX_C;
5130 return POWER_DOMAIN_AUX_D;
5132 /* FIXME: Check VBT for actual wiring of PORT E */
5133 return POWER_DOMAIN_AUX_D;
5136 return POWER_DOMAIN_AUX_A;
5140 enum intel_display_power_domain
5141 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5143 struct drm_device *dev = intel_encoder->base.dev;
5144 struct intel_digital_port *intel_dig_port;
5146 switch (intel_encoder->type) {
5147 case INTEL_OUTPUT_UNKNOWN:
5148 /* Only DDI platforms should ever use this output type */
5149 WARN_ON_ONCE(!HAS_DDI(dev));
5150 case INTEL_OUTPUT_DISPLAYPORT:
5151 case INTEL_OUTPUT_HDMI:
5152 case INTEL_OUTPUT_EDP:
5153 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5154 return port_to_power_domain(intel_dig_port->port);
5155 case INTEL_OUTPUT_DP_MST:
5156 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5157 return port_to_power_domain(intel_dig_port->port);
5158 case INTEL_OUTPUT_ANALOG:
5159 return POWER_DOMAIN_PORT_CRT;
5160 case INTEL_OUTPUT_DSI:
5161 return POWER_DOMAIN_PORT_DSI;
5163 return POWER_DOMAIN_PORT_OTHER;
5167 enum intel_display_power_domain
5168 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5170 struct drm_device *dev = intel_encoder->base.dev;
5171 struct intel_digital_port *intel_dig_port;
5173 switch (intel_encoder->type) {
5174 case INTEL_OUTPUT_UNKNOWN:
5175 case INTEL_OUTPUT_HDMI:
5177 * Only DDI platforms should ever use these output types.
5178 * We can get here after the HDMI detect code has already set
5179 * the type of the shared encoder. Since we can't be sure
5180 * what's the status of the given connectors, play safe and
5181 * run the DP detection too.
5183 WARN_ON_ONCE(!HAS_DDI(dev));
5184 case INTEL_OUTPUT_DISPLAYPORT:
5185 case INTEL_OUTPUT_EDP:
5186 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5187 return port_to_aux_power_domain(intel_dig_port->port);
5188 case INTEL_OUTPUT_DP_MST:
5189 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5190 return port_to_aux_power_domain(intel_dig_port->port);
5192 MISSING_CASE(intel_encoder->type);
5193 return POWER_DOMAIN_AUX_A;
5197 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5198 struct intel_crtc_state *crtc_state)
5200 struct drm_device *dev = crtc->dev;
5201 struct drm_encoder *encoder;
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203 enum pipe pipe = intel_crtc->pipe;
5205 enum transcoder transcoder = crtc_state->cpu_transcoder;
5207 if (!crtc_state->base.active)
5210 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5211 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5212 if (crtc_state->pch_pfit.enabled ||
5213 crtc_state->pch_pfit.force_thru)
5214 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5216 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5217 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5219 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5222 if (crtc_state->shared_dpll)
5223 mask |= BIT(POWER_DOMAIN_PLLS);
5228 static unsigned long
5229 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5230 struct intel_crtc_state *crtc_state)
5232 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5234 enum intel_display_power_domain domain;
5235 unsigned long domains, new_domains, old_domains;
5237 old_domains = intel_crtc->enabled_power_domains;
5238 intel_crtc->enabled_power_domains = new_domains =
5239 get_crtc_power_domains(crtc, crtc_state);
5241 domains = new_domains & ~old_domains;
5243 for_each_power_domain(domain, domains)
5244 intel_display_power_get(dev_priv, domain);
5246 return old_domains & ~new_domains;
5249 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5250 unsigned long domains)
5252 enum intel_display_power_domain domain;
5254 for_each_power_domain(domain, domains)
5255 intel_display_power_put(dev_priv, domain);
5258 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5260 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5262 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5263 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5264 return max_cdclk_freq;
5265 else if (IS_CHERRYVIEW(dev_priv))
5266 return max_cdclk_freq*95/100;
5267 else if (INTEL_INFO(dev_priv)->gen < 4)
5268 return 2*max_cdclk_freq*90/100;
5270 return max_cdclk_freq*90/100;
5273 static void intel_update_max_cdclk(struct drm_device *dev)
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5277 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5278 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5280 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5281 dev_priv->max_cdclk_freq = 675000;
5282 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5283 dev_priv->max_cdclk_freq = 540000;
5284 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5285 dev_priv->max_cdclk_freq = 450000;
5287 dev_priv->max_cdclk_freq = 337500;
5288 } else if (IS_BROXTON(dev)) {
5289 dev_priv->max_cdclk_freq = 624000;
5290 } else if (IS_BROADWELL(dev)) {
5292 * FIXME with extra cooling we can allow
5293 * 540 MHz for ULX and 675 Mhz for ULT.
5294 * How can we know if extra cooling is
5295 * available? PCI ID, VTB, something else?
5297 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5298 dev_priv->max_cdclk_freq = 450000;
5299 else if (IS_BDW_ULX(dev))
5300 dev_priv->max_cdclk_freq = 450000;
5301 else if (IS_BDW_ULT(dev))
5302 dev_priv->max_cdclk_freq = 540000;
5304 dev_priv->max_cdclk_freq = 675000;
5305 } else if (IS_CHERRYVIEW(dev)) {
5306 dev_priv->max_cdclk_freq = 320000;
5307 } else if (IS_VALLEYVIEW(dev)) {
5308 dev_priv->max_cdclk_freq = 400000;
5310 /* otherwise assume cdclk is fixed */
5311 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5314 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5316 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5317 dev_priv->max_cdclk_freq);
5319 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5320 dev_priv->max_dotclk_freq);
5323 static void intel_update_cdclk(struct drm_device *dev)
5325 struct drm_i915_private *dev_priv = dev->dev_private;
5327 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5328 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5329 dev_priv->cdclk_freq);
5332 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5333 * Programmng [sic] note: bit[9:2] should be programmed to the number
5334 * of cdclk that generates 4MHz reference clock freq which is used to
5335 * generate GMBus clock. This will vary with the cdclk freq.
5337 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5338 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5340 if (dev_priv->max_cdclk_freq == 0)
5341 intel_update_max_cdclk(dev);
5344 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
5348 uint32_t current_freq;
5351 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5352 switch (frequency) {
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5355 ratio = BXT_DE_PLL_RATIO(60);
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5359 ratio = BXT_DE_PLL_RATIO(60);
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5363 ratio = BXT_DE_PLL_RATIO(60);
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5367 ratio = BXT_DE_PLL_RATIO(60);
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5371 ratio = BXT_DE_PLL_RATIO(65);
5375 * Bypass frequency with DE PLL disabled. Init ratio, divider
5376 * to suppress GCC warning.
5382 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5387 mutex_lock(&dev_priv->rps.hw_lock);
5388 /* Inform power controller of upcoming frequency change */
5389 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5391 mutex_unlock(&dev_priv->rps.hw_lock);
5394 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5399 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5400 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5401 current_freq = current_freq * 500 + 1000;
5404 * DE PLL has to be disabled when
5405 * - setting to 19.2MHz (bypass, PLL isn't used)
5406 * - before setting to 624MHz (PLL needs toggling)
5407 * - before setting to any frequency from 624MHz (PLL needs toggling)
5409 if (frequency == 19200 || frequency == 624000 ||
5410 current_freq == 624000) {
5411 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5413 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5415 DRM_ERROR("timout waiting for DE PLL unlock\n");
5418 if (frequency != 19200) {
5421 val = I915_READ(BXT_DE_PLL_CTL);
5422 val &= ~BXT_DE_PLL_RATIO_MASK;
5424 I915_WRITE(BXT_DE_PLL_CTL, val);
5426 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5428 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5429 DRM_ERROR("timeout waiting for DE PLL lock\n");
5431 val = I915_READ(CDCLK_CTL);
5432 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5435 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5438 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5439 if (frequency >= 500000)
5440 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5442 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5443 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5444 val |= (frequency - 1000) / 500;
5445 I915_WRITE(CDCLK_CTL, val);
5448 mutex_lock(&dev_priv->rps.hw_lock);
5449 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5450 DIV_ROUND_UP(frequency, 25000));
5451 mutex_unlock(&dev_priv->rps.hw_lock);
5454 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5459 intel_update_cdclk(dev_priv->dev);
5462 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5464 if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5467 /* TODO: Check for a valid CDCLK rate */
5469 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5470 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5475 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5476 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5484 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5486 return broxton_cdclk_is_enabled(dev_priv);
5489 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5491 /* check if cd clock is enabled */
5492 if (broxton_cdclk_is_enabled(dev_priv)) {
5493 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5497 DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5501 * - The initial CDCLK needs to be read from VBT.
5502 * Need to make this change after VBT has changes for BXT.
5503 * - check if setting the max (or any) cdclk freq is really necessary
5504 * here, it belongs to modeset time
5506 broxton_set_cdclk(dev_priv, 624000);
5508 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5509 POSTING_READ(DBUF_CTL);
5513 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5514 DRM_ERROR("DBuf power enable timeout!\n");
5517 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5519 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5520 POSTING_READ(DBUF_CTL);
5524 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5525 DRM_ERROR("DBuf power disable timeout!\n");
5527 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5528 broxton_set_cdclk(dev_priv, 19200);
5531 static const struct skl_cdclk_entry {
5534 } skl_cdclk_frequencies[] = {
5535 { .freq = 308570, .vco = 8640 },
5536 { .freq = 337500, .vco = 8100 },
5537 { .freq = 432000, .vco = 8640 },
5538 { .freq = 450000, .vco = 8100 },
5539 { .freq = 540000, .vco = 8100 },
5540 { .freq = 617140, .vco = 8640 },
5541 { .freq = 675000, .vco = 8100 },
5544 static unsigned int skl_cdclk_decimal(unsigned int freq)
5546 return (freq - 1000) / 500;
5549 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5553 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5554 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5556 if (e->freq == freq)
5564 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5566 unsigned int min_freq;
5569 /* select the minimum CDCLK before enabling DPLL 0 */
5570 val = I915_READ(CDCLK_CTL);
5571 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5572 val |= CDCLK_FREQ_337_308;
5574 if (required_vco == 8640)
5579 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5581 I915_WRITE(CDCLK_CTL, val);
5582 POSTING_READ(CDCLK_CTL);
5585 * We always enable DPLL0 with the lowest link rate possible, but still
5586 * taking into account the VCO required to operate the eDP panel at the
5587 * desired frequency. The usual DP link rates operate with a VCO of
5588 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5589 * The modeset code is responsible for the selection of the exact link
5590 * rate later on, with the constraint of choosing a frequency that
5591 * works with required_vco.
5593 val = I915_READ(DPLL_CTRL1);
5595 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5596 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5597 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5598 if (required_vco == 8640)
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5602 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5605 I915_WRITE(DPLL_CTRL1, val);
5606 POSTING_READ(DPLL_CTRL1);
5608 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5610 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5611 DRM_ERROR("DPLL0 not locked\n");
5614 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5619 /* inform PCU we want to change CDCLK */
5620 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5621 mutex_lock(&dev_priv->rps.hw_lock);
5622 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5623 mutex_unlock(&dev_priv->rps.hw_lock);
5625 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5628 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5632 for (i = 0; i < 15; i++) {
5633 if (skl_cdclk_pcu_ready(dev_priv))
5641 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5643 struct drm_device *dev = dev_priv->dev;
5644 u32 freq_select, pcu_ack;
5646 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5648 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5649 DRM_ERROR("failed to inform PCU about cdclk change\n");
5657 freq_select = CDCLK_FREQ_450_432;
5661 freq_select = CDCLK_FREQ_540;
5667 freq_select = CDCLK_FREQ_337_308;
5672 freq_select = CDCLK_FREQ_675_617;
5677 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5678 POSTING_READ(CDCLK_CTL);
5680 /* inform PCU of the change */
5681 mutex_lock(&dev_priv->rps.hw_lock);
5682 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5683 mutex_unlock(&dev_priv->rps.hw_lock);
5685 intel_update_cdclk(dev);
5688 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5690 /* disable DBUF power */
5691 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5692 POSTING_READ(DBUF_CTL);
5696 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5697 DRM_ERROR("DBuf power disable timeout\n");
5700 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5701 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5702 DRM_ERROR("Couldn't disable DPLL0\n");
5705 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5707 unsigned int required_vco;
5709 /* DPLL0 not enabled (happens on early BIOS versions) */
5710 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5712 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5713 skl_dpll0_enable(dev_priv, required_vco);
5716 /* set CDCLK to the frequency the BIOS chose */
5717 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5719 /* enable DBUF power */
5720 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5721 POSTING_READ(DBUF_CTL);
5725 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5726 DRM_ERROR("DBuf power enable timeout\n");
5729 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5731 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5732 uint32_t cdctl = I915_READ(CDCLK_CTL);
5733 int freq = dev_priv->skl_boot_cdclk;
5736 * check if the pre-os intialized the display
5737 * There is SWF18 scratchpad register defined which is set by the
5738 * pre-os which can be used by the OS drivers to check the status
5740 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5743 /* Is PLL enabled and locked ? */
5744 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5747 /* DPLL okay; verify the cdclock
5749 * Noticed in some instances that the freq selection is correct but
5750 * decimal part is programmed wrong from BIOS where pre-os does not
5751 * enable display. Verify the same as well.
5753 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5754 /* All well; nothing to sanitize */
5758 * As of now initialize with max cdclk till
5759 * we get dynamic cdclk support
5761 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5762 skl_init_cdclk(dev_priv);
5764 /* we did have to sanitize */
5768 /* Adjust CDclk dividers to allow high res or save power if possible */
5769 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5771 struct drm_i915_private *dev_priv = dev->dev_private;
5774 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5775 != dev_priv->cdclk_freq);
5777 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5779 else if (cdclk == 266667)
5784 mutex_lock(&dev_priv->rps.hw_lock);
5785 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5786 val &= ~DSPFREQGUAR_MASK;
5787 val |= (cmd << DSPFREQGUAR_SHIFT);
5788 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5789 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5790 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5792 DRM_ERROR("timed out waiting for CDclk change\n");
5794 mutex_unlock(&dev_priv->rps.hw_lock);
5796 mutex_lock(&dev_priv->sb_lock);
5798 if (cdclk == 400000) {
5801 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5803 /* adjust cdclk divider */
5804 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5805 val &= ~CCK_FREQUENCY_VALUES;
5807 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5809 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5810 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5812 DRM_ERROR("timed out waiting for CDclk change\n");
5815 /* adjust self-refresh exit latency value */
5816 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5820 * For high bandwidth configs, we set a higher latency in the bunit
5821 * so that the core display fetch happens in time to avoid underruns.
5823 if (cdclk == 400000)
5824 val |= 4500 / 250; /* 4.5 usec */
5826 val |= 3000 / 250; /* 3.0 usec */
5827 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5829 mutex_unlock(&dev_priv->sb_lock);
5831 intel_update_cdclk(dev);
5834 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5839 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5840 != dev_priv->cdclk_freq);
5849 MISSING_CASE(cdclk);
5854 * Specs are full of misinformation, but testing on actual
5855 * hardware has shown that we just need to write the desired
5856 * CCK divider into the Punit register.
5858 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5860 mutex_lock(&dev_priv->rps.hw_lock);
5861 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5862 val &= ~DSPFREQGUAR_MASK_CHV;
5863 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5864 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5865 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5866 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5868 DRM_ERROR("timed out waiting for CDclk change\n");
5870 mutex_unlock(&dev_priv->rps.hw_lock);
5872 intel_update_cdclk(dev);
5875 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5878 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5879 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5882 * Really only a few cases to deal with, as only 4 CDclks are supported:
5885 * 320/333MHz (depends on HPLL freq)
5887 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5888 * of the lower bin and adjust if needed.
5890 * We seem to get an unstable or solid color picture at 200MHz.
5891 * Not sure what's wrong. For now use 200MHz only when all pipes
5894 if (!IS_CHERRYVIEW(dev_priv) &&
5895 max_pixclk > freq_320*limit/100)
5897 else if (max_pixclk > 266667*limit/100)
5899 else if (max_pixclk > 0)
5905 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5910 * - remove the guardband, it's not needed on BXT
5911 * - set 19.2MHz bypass frequency if there are no active pipes
5913 if (max_pixclk > 576000*9/10)
5915 else if (max_pixclk > 384000*9/10)
5917 else if (max_pixclk > 288000*9/10)
5919 else if (max_pixclk > 144000*9/10)
5925 /* Compute the max pixel clock for new configuration. */
5926 static int intel_mode_max_pixclk(struct drm_device *dev,
5927 struct drm_atomic_state *state)
5929 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931 struct drm_crtc *crtc;
5932 struct drm_crtc_state *crtc_state;
5933 unsigned max_pixclk = 0, i;
5936 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5937 sizeof(intel_state->min_pixclk));
5939 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5942 if (crtc_state->enable)
5943 pixclk = crtc_state->adjusted_mode.crtc_clock;
5945 intel_state->min_pixclk[i] = pixclk;
5948 for_each_pipe(dev_priv, pipe)
5949 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5954 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5956 struct drm_device *dev = state->dev;
5957 struct drm_i915_private *dev_priv = dev->dev_private;
5958 int max_pixclk = intel_mode_max_pixclk(dev, state);
5959 struct intel_atomic_state *intel_state =
5960 to_intel_atomic_state(state);
5965 intel_state->cdclk = intel_state->dev_cdclk =
5966 valleyview_calc_cdclk(dev_priv, max_pixclk);
5968 if (!intel_state->active_crtcs)
5969 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5974 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5976 struct drm_device *dev = state->dev;
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978 int max_pixclk = intel_mode_max_pixclk(dev, state);
5979 struct intel_atomic_state *intel_state =
5980 to_intel_atomic_state(state);
5985 intel_state->cdclk = intel_state->dev_cdclk =
5986 broxton_calc_cdclk(dev_priv, max_pixclk);
5988 if (!intel_state->active_crtcs)
5989 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5994 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5996 unsigned int credits, default_credits;
5998 if (IS_CHERRYVIEW(dev_priv))
5999 default_credits = PFI_CREDIT(12);
6001 default_credits = PFI_CREDIT(8);
6003 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6004 /* CHV suggested value is 31 or 63 */
6005 if (IS_CHERRYVIEW(dev_priv))
6006 credits = PFI_CREDIT_63;
6008 credits = PFI_CREDIT(15);
6010 credits = default_credits;
6014 * WA - write default credits before re-programming
6015 * FIXME: should we also set the resend bit here?
6017 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6020 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6021 credits | PFI_CREDIT_RESEND);
6024 * FIXME is this guaranteed to clear
6025 * immediately or should we poll for it?
6027 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6030 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6032 struct drm_device *dev = old_state->dev;
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034 struct intel_atomic_state *old_intel_state =
6035 to_intel_atomic_state(old_state);
6036 unsigned req_cdclk = old_intel_state->dev_cdclk;
6039 * FIXME: We can end up here with all power domains off, yet
6040 * with a CDCLK frequency other than the minimum. To account
6041 * for this take the PIPE-A power domain, which covers the HW
6042 * blocks needed for the following programming. This can be
6043 * removed once it's guaranteed that we get here either with
6044 * the minimum CDCLK set, or the required power domains
6047 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6049 if (IS_CHERRYVIEW(dev))
6050 cherryview_set_cdclk(dev, req_cdclk);
6052 valleyview_set_cdclk(dev, req_cdclk);
6054 vlv_program_pfi_credits(dev_priv);
6056 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6059 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6061 struct drm_device *dev = crtc->dev;
6062 struct drm_i915_private *dev_priv = to_i915(dev);
6063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6064 struct intel_encoder *encoder;
6065 struct intel_crtc_state *pipe_config =
6066 to_intel_crtc_state(crtc->state);
6067 int pipe = intel_crtc->pipe;
6069 if (WARN_ON(intel_crtc->active))
6072 if (intel_crtc->config->has_dp_encoder)
6073 intel_dp_set_m_n(intel_crtc, M1_N1);
6075 intel_set_pipe_timings(intel_crtc);
6076 intel_set_pipe_src_size(intel_crtc);
6078 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6081 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6082 I915_WRITE(CHV_CANVAS(pipe), 0);
6085 i9xx_set_pipeconf(intel_crtc);
6087 intel_crtc->active = true;
6089 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6091 for_each_encoder_on_crtc(dev, crtc, encoder)
6092 if (encoder->pre_pll_enable)
6093 encoder->pre_pll_enable(encoder);
6095 if (IS_CHERRYVIEW(dev)) {
6096 chv_prepare_pll(intel_crtc, intel_crtc->config);
6097 chv_enable_pll(intel_crtc, intel_crtc->config);
6099 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6100 vlv_enable_pll(intel_crtc, intel_crtc->config);
6103 for_each_encoder_on_crtc(dev, crtc, encoder)
6104 if (encoder->pre_enable)
6105 encoder->pre_enable(encoder);
6107 i9xx_pfit_enable(intel_crtc);
6109 intel_color_load_luts(&pipe_config->base);
6111 intel_update_watermarks(crtc);
6112 intel_enable_pipe(intel_crtc);
6114 assert_vblank_disabled(crtc);
6115 drm_crtc_vblank_on(crtc);
6117 for_each_encoder_on_crtc(dev, crtc, encoder)
6118 encoder->enable(encoder);
6121 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6123 struct drm_device *dev = crtc->base.dev;
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6126 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6127 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6130 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6132 struct drm_device *dev = crtc->dev;
6133 struct drm_i915_private *dev_priv = to_i915(dev);
6134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135 struct intel_encoder *encoder;
6136 struct intel_crtc_state *pipe_config =
6137 to_intel_crtc_state(crtc->state);
6138 enum pipe pipe = intel_crtc->pipe;
6140 if (WARN_ON(intel_crtc->active))
6143 i9xx_set_pll_dividers(intel_crtc);
6145 if (intel_crtc->config->has_dp_encoder)
6146 intel_dp_set_m_n(intel_crtc, M1_N1);
6148 intel_set_pipe_timings(intel_crtc);
6149 intel_set_pipe_src_size(intel_crtc);
6151 i9xx_set_pipeconf(intel_crtc);
6153 intel_crtc->active = true;
6156 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6158 for_each_encoder_on_crtc(dev, crtc, encoder)
6159 if (encoder->pre_enable)
6160 encoder->pre_enable(encoder);
6162 i9xx_enable_pll(intel_crtc);
6164 i9xx_pfit_enable(intel_crtc);
6166 intel_color_load_luts(&pipe_config->base);
6168 intel_update_watermarks(crtc);
6169 intel_enable_pipe(intel_crtc);
6171 assert_vblank_disabled(crtc);
6172 drm_crtc_vblank_on(crtc);
6174 for_each_encoder_on_crtc(dev, crtc, encoder)
6175 encoder->enable(encoder);
6178 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6180 struct drm_device *dev = crtc->base.dev;
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6183 if (!crtc->config->gmch_pfit.control)
6186 assert_pipe_disabled(dev_priv, crtc->pipe);
6188 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6189 I915_READ(PFIT_CONTROL));
6190 I915_WRITE(PFIT_CONTROL, 0);
6193 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6195 struct drm_device *dev = crtc->dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6198 struct intel_encoder *encoder;
6199 int pipe = intel_crtc->pipe;
6202 * On gen2 planes are double buffered but the pipe isn't, so we must
6203 * wait for planes to fully turn off before disabling the pipe.
6206 intel_wait_for_vblank(dev, pipe);
6208 for_each_encoder_on_crtc(dev, crtc, encoder)
6209 encoder->disable(encoder);
6211 drm_crtc_vblank_off(crtc);
6212 assert_vblank_disabled(crtc);
6214 intel_disable_pipe(intel_crtc);
6216 i9xx_pfit_disable(intel_crtc);
6218 for_each_encoder_on_crtc(dev, crtc, encoder)
6219 if (encoder->post_disable)
6220 encoder->post_disable(encoder);
6222 if (!intel_crtc->config->has_dsi_encoder) {
6223 if (IS_CHERRYVIEW(dev))
6224 chv_disable_pll(dev_priv, pipe);
6225 else if (IS_VALLEYVIEW(dev))
6226 vlv_disable_pll(dev_priv, pipe);
6228 i9xx_disable_pll(intel_crtc);
6231 for_each_encoder_on_crtc(dev, crtc, encoder)
6232 if (encoder->post_pll_disable)
6233 encoder->post_pll_disable(encoder);
6236 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6239 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6241 struct intel_encoder *encoder;
6242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6243 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6244 enum intel_display_power_domain domain;
6245 unsigned long domains;
6247 if (!intel_crtc->active)
6250 if (to_intel_plane_state(crtc->primary->state)->visible) {
6251 WARN_ON(intel_crtc->unpin_work);
6253 intel_pre_disable_primary_noatomic(crtc);
6255 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6256 to_intel_plane_state(crtc->primary->state)->visible = false;
6259 dev_priv->display.crtc_disable(crtc);
6261 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6264 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6265 crtc->state->active = false;
6266 intel_crtc->active = false;
6267 crtc->enabled = false;
6268 crtc->state->connector_mask = 0;
6269 crtc->state->encoder_mask = 0;
6271 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6272 encoder->base.crtc = NULL;
6274 intel_fbc_disable(intel_crtc);
6275 intel_update_watermarks(crtc);
6276 intel_disable_shared_dpll(intel_crtc);
6278 domains = intel_crtc->enabled_power_domains;
6279 for_each_power_domain(domain, domains)
6280 intel_display_power_put(dev_priv, domain);
6281 intel_crtc->enabled_power_domains = 0;
6283 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6284 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6288 * turn all crtc's off, but do not adjust state
6289 * This has to be paired with a call to intel_modeset_setup_hw_state.
6291 int intel_display_suspend(struct drm_device *dev)
6293 struct drm_i915_private *dev_priv = to_i915(dev);
6294 struct drm_atomic_state *state;
6297 state = drm_atomic_helper_suspend(dev);
6298 ret = PTR_ERR_OR_ZERO(state);
6300 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6302 dev_priv->modeset_restore_state = state;
6306 void intel_encoder_destroy(struct drm_encoder *encoder)
6308 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6310 drm_encoder_cleanup(encoder);
6311 kfree(intel_encoder);
6314 /* Cross check the actual hw state with our own modeset state tracking (and it's
6315 * internal consistency). */
6316 static void intel_connector_verify_state(struct intel_connector *connector)
6318 struct drm_crtc *crtc = connector->base.state->crtc;
6320 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6321 connector->base.base.id,
6322 connector->base.name);
6324 if (connector->get_hw_state(connector)) {
6325 struct intel_encoder *encoder = connector->encoder;
6326 struct drm_connector_state *conn_state = connector->base.state;
6328 I915_STATE_WARN(!crtc,
6329 "connector enabled without attached crtc\n");
6334 I915_STATE_WARN(!crtc->state->active,
6335 "connector is active, but attached crtc isn't\n");
6337 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6340 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6341 "atomic encoder doesn't match attached encoder\n");
6343 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6344 "attached encoder crtc differs from connector crtc\n");
6346 I915_STATE_WARN(crtc && crtc->state->active,
6347 "attached crtc is active, but connector isn't\n");
6348 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6349 "best encoder set without crtc!\n");
6353 int intel_connector_init(struct intel_connector *connector)
6355 drm_atomic_helper_connector_reset(&connector->base);
6357 if (!connector->base.state)
6363 struct intel_connector *intel_connector_alloc(void)
6365 struct intel_connector *connector;
6367 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6371 if (intel_connector_init(connector) < 0) {
6379 /* Simple connector->get_hw_state implementation for encoders that support only
6380 * one connector and no cloning and hence the encoder state determines the state
6381 * of the connector. */
6382 bool intel_connector_get_hw_state(struct intel_connector *connector)
6385 struct intel_encoder *encoder = connector->encoder;
6387 return encoder->get_hw_state(encoder, &pipe);
6390 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6392 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6393 return crtc_state->fdi_lanes;
6398 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6399 struct intel_crtc_state *pipe_config)
6401 struct drm_atomic_state *state = pipe_config->base.state;
6402 struct intel_crtc *other_crtc;
6403 struct intel_crtc_state *other_crtc_state;
6405 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6406 pipe_name(pipe), pipe_config->fdi_lanes);
6407 if (pipe_config->fdi_lanes > 4) {
6408 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6409 pipe_name(pipe), pipe_config->fdi_lanes);
6413 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6414 if (pipe_config->fdi_lanes > 2) {
6415 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6416 pipe_config->fdi_lanes);
6423 if (INTEL_INFO(dev)->num_pipes == 2)
6426 /* Ivybridge 3 pipe is really complicated */
6431 if (pipe_config->fdi_lanes <= 2)
6434 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6436 intel_atomic_get_crtc_state(state, other_crtc);
6437 if (IS_ERR(other_crtc_state))
6438 return PTR_ERR(other_crtc_state);
6440 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6441 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6442 pipe_name(pipe), pipe_config->fdi_lanes);
6447 if (pipe_config->fdi_lanes > 2) {
6448 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6449 pipe_name(pipe), pipe_config->fdi_lanes);
6453 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6455 intel_atomic_get_crtc_state(state, other_crtc);
6456 if (IS_ERR(other_crtc_state))
6457 return PTR_ERR(other_crtc_state);
6459 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6460 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6470 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6471 struct intel_crtc_state *pipe_config)
6473 struct drm_device *dev = intel_crtc->base.dev;
6474 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6475 int lane, link_bw, fdi_dotclock, ret;
6476 bool needs_recompute = false;
6479 /* FDI is a binary signal running at ~2.7GHz, encoding
6480 * each output octet as 10 bits. The actual frequency
6481 * is stored as a divider into a 100MHz clock, and the
6482 * mode pixel clock is stored in units of 1KHz.
6483 * Hence the bw of each lane in terms of the mode signal
6486 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6488 fdi_dotclock = adjusted_mode->crtc_clock;
6490 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6491 pipe_config->pipe_bpp);
6493 pipe_config->fdi_lanes = lane;
6495 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6496 link_bw, &pipe_config->fdi_m_n);
6498 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6499 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6500 pipe_config->pipe_bpp -= 2*3;
6501 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6502 pipe_config->pipe_bpp);
6503 needs_recompute = true;
6504 pipe_config->bw_constrained = true;
6509 if (needs_recompute)
6515 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6516 struct intel_crtc_state *pipe_config)
6518 if (pipe_config->pipe_bpp > 24)
6521 /* HSW can handle pixel rate up to cdclk? */
6522 if (IS_HASWELL(dev_priv))
6526 * We compare against max which means we must take
6527 * the increased cdclk requirement into account when
6528 * calculating the new cdclk.
6530 * Should measure whether using a lower cdclk w/o IPS
6532 return ilk_pipe_pixel_rate(pipe_config) <=
6533 dev_priv->max_cdclk_freq * 95 / 100;
6536 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6537 struct intel_crtc_state *pipe_config)
6539 struct drm_device *dev = crtc->base.dev;
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6542 pipe_config->ips_enabled = i915.enable_ips &&
6543 hsw_crtc_supports_ips(crtc) &&
6544 pipe_config_supports_ips(dev_priv, pipe_config);
6547 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6549 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6551 /* GDG double wide on either pipe, otherwise pipe A only */
6552 return INTEL_INFO(dev_priv)->gen < 4 &&
6553 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6556 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6557 struct intel_crtc_state *pipe_config)
6559 struct drm_device *dev = crtc->base.dev;
6560 struct drm_i915_private *dev_priv = dev->dev_private;
6561 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6563 /* FIXME should check pixel clock limits on all platforms */
6564 if (INTEL_INFO(dev)->gen < 4) {
6565 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6568 * Enable double wide mode when the dot clock
6569 * is > 90% of the (display) core speed.
6571 if (intel_crtc_supports_double_wide(crtc) &&
6572 adjusted_mode->crtc_clock > clock_limit) {
6574 pipe_config->double_wide = true;
6577 if (adjusted_mode->crtc_clock > clock_limit) {
6578 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6579 adjusted_mode->crtc_clock, clock_limit,
6580 yesno(pipe_config->double_wide));
6586 * Pipe horizontal size must be even in:
6588 * - LVDS dual channel mode
6589 * - Double wide pipe
6591 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6592 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6593 pipe_config->pipe_src_w &= ~1;
6595 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6596 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6598 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6599 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6603 hsw_compute_ips_config(crtc, pipe_config);
6605 if (pipe_config->has_pch_encoder)
6606 return ironlake_fdi_compute_config(crtc, pipe_config);
6611 static int skylake_get_display_clock_speed(struct drm_device *dev)
6613 struct drm_i915_private *dev_priv = to_i915(dev);
6614 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6615 uint32_t cdctl = I915_READ(CDCLK_CTL);
6618 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6619 return 24000; /* 24MHz is the cd freq with NSSC ref */
6621 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6624 linkrate = (I915_READ(DPLL_CTRL1) &
6625 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6627 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6628 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6630 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6631 case CDCLK_FREQ_450_432:
6633 case CDCLK_FREQ_337_308:
6635 case CDCLK_FREQ_675_617:
6638 WARN(1, "Unknown cd freq selection\n");
6642 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6643 case CDCLK_FREQ_450_432:
6645 case CDCLK_FREQ_337_308:
6647 case CDCLK_FREQ_675_617:
6650 WARN(1, "Unknown cd freq selection\n");
6654 /* error case, do as if DPLL0 isn't enabled */
6658 static int broxton_get_display_clock_speed(struct drm_device *dev)
6660 struct drm_i915_private *dev_priv = to_i915(dev);
6661 uint32_t cdctl = I915_READ(CDCLK_CTL);
6662 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6663 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6666 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6669 cdclk = 19200 * pll_ratio / 2;
6671 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6672 case BXT_CDCLK_CD2X_DIV_SEL_1:
6673 return cdclk; /* 576MHz or 624MHz */
6674 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6675 return cdclk * 2 / 3; /* 384MHz */
6676 case BXT_CDCLK_CD2X_DIV_SEL_2:
6677 return cdclk / 2; /* 288MHz */
6678 case BXT_CDCLK_CD2X_DIV_SEL_4:
6679 return cdclk / 4; /* 144MHz */
6682 /* error case, do as if DE PLL isn't enabled */
6686 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6688 struct drm_i915_private *dev_priv = dev->dev_private;
6689 uint32_t lcpll = I915_READ(LCPLL_CTL);
6690 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6692 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6694 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6696 else if (freq == LCPLL_CLK_FREQ_450)
6698 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6700 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6706 static int haswell_get_display_clock_speed(struct drm_device *dev)
6708 struct drm_i915_private *dev_priv = dev->dev_private;
6709 uint32_t lcpll = I915_READ(LCPLL_CTL);
6710 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6712 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6714 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6716 else if (freq == LCPLL_CLK_FREQ_450)
6718 else if (IS_HSW_ULT(dev))
6724 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6726 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6727 CCK_DISPLAY_CLOCK_CONTROL);
6730 static int ilk_get_display_clock_speed(struct drm_device *dev)
6735 static int i945_get_display_clock_speed(struct drm_device *dev)
6740 static int i915_get_display_clock_speed(struct drm_device *dev)
6745 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6750 static int pnv_get_display_clock_speed(struct drm_device *dev)
6754 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6756 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6757 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6759 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6761 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6763 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6766 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6767 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6769 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6774 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6778 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6780 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6783 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6784 case GC_DISPLAY_CLOCK_333_MHZ:
6787 case GC_DISPLAY_CLOCK_190_200_MHZ:
6793 static int i865_get_display_clock_speed(struct drm_device *dev)
6798 static int i85x_get_display_clock_speed(struct drm_device *dev)
6803 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6804 * encoding is different :(
6805 * FIXME is this the right way to detect 852GM/852GMV?
6807 if (dev->pdev->revision == 0x1)
6810 pci_bus_read_config_word(dev->pdev->bus,
6811 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6813 /* Assume that the hardware is in the high speed state. This
6814 * should be the default.
6816 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6817 case GC_CLOCK_133_200:
6818 case GC_CLOCK_133_200_2:
6819 case GC_CLOCK_100_200:
6821 case GC_CLOCK_166_250:
6823 case GC_CLOCK_100_133:
6825 case GC_CLOCK_133_266:
6826 case GC_CLOCK_133_266_2:
6827 case GC_CLOCK_166_266:
6831 /* Shouldn't happen */
6835 static int i830_get_display_clock_speed(struct drm_device *dev)
6840 static unsigned int intel_hpll_vco(struct drm_device *dev)
6842 struct drm_i915_private *dev_priv = dev->dev_private;
6843 static const unsigned int blb_vco[8] = {
6850 static const unsigned int pnv_vco[8] = {
6857 static const unsigned int cl_vco[8] = {
6866 static const unsigned int elk_vco[8] = {
6872 static const unsigned int ctg_vco[8] = {
6880 const unsigned int *vco_table;
6884 /* FIXME other chipsets? */
6886 vco_table = ctg_vco;
6887 else if (IS_G4X(dev))
6888 vco_table = elk_vco;
6889 else if (IS_CRESTLINE(dev))
6891 else if (IS_PINEVIEW(dev))
6892 vco_table = pnv_vco;
6893 else if (IS_G33(dev))
6894 vco_table = blb_vco;
6898 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6900 vco = vco_table[tmp & 0x7];
6902 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6904 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6909 static int gm45_get_display_clock_speed(struct drm_device *dev)
6911 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6914 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6916 cdclk_sel = (tmp >> 12) & 0x1;
6922 return cdclk_sel ? 333333 : 222222;
6924 return cdclk_sel ? 320000 : 228571;
6926 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6931 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6933 static const uint8_t div_3200[] = { 16, 10, 8 };
6934 static const uint8_t div_4000[] = { 20, 12, 10 };
6935 static const uint8_t div_5333[] = { 24, 16, 14 };
6936 const uint8_t *div_table;
6937 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6940 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6942 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6944 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6949 div_table = div_3200;
6952 div_table = div_4000;
6955 div_table = div_5333;
6961 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6964 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6968 static int g33_get_display_clock_speed(struct drm_device *dev)
6970 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6971 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6972 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6973 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6974 const uint8_t *div_table;
6975 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6978 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6980 cdclk_sel = (tmp >> 4) & 0x7;
6982 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6987 div_table = div_3200;
6990 div_table = div_4000;
6993 div_table = div_4800;
6996 div_table = div_5333;
7002 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7005 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7010 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7012 while (*num > DATA_LINK_M_N_MASK ||
7013 *den > DATA_LINK_M_N_MASK) {
7019 static void compute_m_n(unsigned int m, unsigned int n,
7020 uint32_t *ret_m, uint32_t *ret_n)
7022 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7023 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7024 intel_reduce_m_n_ratio(ret_m, ret_n);
7028 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7029 int pixel_clock, int link_clock,
7030 struct intel_link_m_n *m_n)
7034 compute_m_n(bits_per_pixel * pixel_clock,
7035 link_clock * nlanes * 8,
7036 &m_n->gmch_m, &m_n->gmch_n);
7038 compute_m_n(pixel_clock, link_clock,
7039 &m_n->link_m, &m_n->link_n);
7042 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7044 if (i915.panel_use_ssc >= 0)
7045 return i915.panel_use_ssc != 0;
7046 return dev_priv->vbt.lvds_use_ssc
7047 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7050 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7052 return (1 << dpll->n) << 16 | dpll->m2;
7055 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7057 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7060 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7061 struct intel_crtc_state *crtc_state,
7062 intel_clock_t *reduced_clock)
7064 struct drm_device *dev = crtc->base.dev;
7067 if (IS_PINEVIEW(dev)) {
7068 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7070 fp2 = pnv_dpll_compute_fp(reduced_clock);
7072 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7074 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7077 crtc_state->dpll_hw_state.fp0 = fp;
7079 crtc->lowfreq_avail = false;
7080 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7082 crtc_state->dpll_hw_state.fp1 = fp2;
7083 crtc->lowfreq_avail = true;
7085 crtc_state->dpll_hw_state.fp1 = fp;
7089 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7095 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7096 * and set it to a reasonable value instead.
7098 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7099 reg_val &= 0xffffff00;
7100 reg_val |= 0x00000030;
7101 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7103 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7104 reg_val &= 0x8cffffff;
7105 reg_val = 0x8c000000;
7106 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7108 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7109 reg_val &= 0xffffff00;
7110 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7112 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7113 reg_val &= 0x00ffffff;
7114 reg_val |= 0xb0000000;
7115 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7118 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7119 struct intel_link_m_n *m_n)
7121 struct drm_device *dev = crtc->base.dev;
7122 struct drm_i915_private *dev_priv = dev->dev_private;
7123 int pipe = crtc->pipe;
7125 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7126 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7127 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7128 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7131 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7132 struct intel_link_m_n *m_n,
7133 struct intel_link_m_n *m2_n2)
7135 struct drm_device *dev = crtc->base.dev;
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7137 int pipe = crtc->pipe;
7138 enum transcoder transcoder = crtc->config->cpu_transcoder;
7140 if (INTEL_INFO(dev)->gen >= 5) {
7141 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7142 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7143 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7144 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7145 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7146 * for gen < 8) and if DRRS is supported (to make sure the
7147 * registers are not unnecessarily accessed).
7149 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7150 crtc->config->has_drrs) {
7151 I915_WRITE(PIPE_DATA_M2(transcoder),
7152 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7153 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7154 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7155 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7158 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7159 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7160 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7161 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7165 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7167 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7170 dp_m_n = &crtc->config->dp_m_n;
7171 dp_m2_n2 = &crtc->config->dp_m2_n2;
7172 } else if (m_n == M2_N2) {
7175 * M2_N2 registers are not supported. Hence m2_n2 divider value
7176 * needs to be programmed into M1_N1.
7178 dp_m_n = &crtc->config->dp_m2_n2;
7180 DRM_ERROR("Unsupported divider value\n");
7184 if (crtc->config->has_pch_encoder)
7185 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7187 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7190 static void vlv_compute_dpll(struct intel_crtc *crtc,
7191 struct intel_crtc_state *pipe_config)
7193 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7194 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7195 if (crtc->pipe != PIPE_A)
7196 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7198 /* DPLL not used with DSI, but still need the rest set up */
7199 if (!pipe_config->has_dsi_encoder)
7200 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7201 DPLL_EXT_BUFFER_ENABLE_VLV;
7203 pipe_config->dpll_hw_state.dpll_md =
7204 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7207 static void chv_compute_dpll(struct intel_crtc *crtc,
7208 struct intel_crtc_state *pipe_config)
7210 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7211 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7212 if (crtc->pipe != PIPE_A)
7213 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7215 /* DPLL not used with DSI, but still need the rest set up */
7216 if (!pipe_config->has_dsi_encoder)
7217 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7219 pipe_config->dpll_hw_state.dpll_md =
7220 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7223 static void vlv_prepare_pll(struct intel_crtc *crtc,
7224 const struct intel_crtc_state *pipe_config)
7226 struct drm_device *dev = crtc->base.dev;
7227 struct drm_i915_private *dev_priv = dev->dev_private;
7228 enum pipe pipe = crtc->pipe;
7230 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7231 u32 coreclk, reg_val;
7234 I915_WRITE(DPLL(pipe),
7235 pipe_config->dpll_hw_state.dpll &
7236 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7238 /* No need to actually set up the DPLL with DSI */
7239 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7242 mutex_lock(&dev_priv->sb_lock);
7244 bestn = pipe_config->dpll.n;
7245 bestm1 = pipe_config->dpll.m1;
7246 bestm2 = pipe_config->dpll.m2;
7247 bestp1 = pipe_config->dpll.p1;
7248 bestp2 = pipe_config->dpll.p2;
7250 /* See eDP HDMI DPIO driver vbios notes doc */
7252 /* PLL B needs special handling */
7254 vlv_pllb_recal_opamp(dev_priv, pipe);
7256 /* Set up Tx target for periodic Rcomp update */
7257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7259 /* Disable target IRef on PLL */
7260 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7261 reg_val &= 0x00ffffff;
7262 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7264 /* Disable fast lock */
7265 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7267 /* Set idtafcrecal before PLL is enabled */
7268 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7269 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7270 mdiv |= ((bestn << DPIO_N_SHIFT));
7271 mdiv |= (1 << DPIO_K_SHIFT);
7274 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7275 * but we don't support that).
7276 * Note: don't use the DAC post divider as it seems unstable.
7278 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7279 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7281 mdiv |= DPIO_ENABLE_CALIBRATION;
7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7284 /* Set HBR and RBR LPF coefficients */
7285 if (pipe_config->port_clock == 162000 ||
7286 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7287 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7288 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7294 if (pipe_config->has_dp_encoder) {
7295 /* Use SSC source */
7297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7302 } else { /* HDMI or VGA */
7303 /* Use bend source */
7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7312 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7313 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7314 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7315 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7316 coreclk |= 0x01000000;
7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7320 mutex_unlock(&dev_priv->sb_lock);
7323 static void chv_prepare_pll(struct intel_crtc *crtc,
7324 const struct intel_crtc_state *pipe_config)
7326 struct drm_device *dev = crtc->base.dev;
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328 enum pipe pipe = crtc->pipe;
7329 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7330 u32 loopfilter, tribuf_calcntr;
7331 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7335 /* Enable Refclk and SSC */
7336 I915_WRITE(DPLL(pipe),
7337 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7339 /* No need to actually set up the DPLL with DSI */
7340 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7343 bestn = pipe_config->dpll.n;
7344 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7345 bestm1 = pipe_config->dpll.m1;
7346 bestm2 = pipe_config->dpll.m2 >> 22;
7347 bestp1 = pipe_config->dpll.p1;
7348 bestp2 = pipe_config->dpll.p2;
7349 vco = pipe_config->dpll.vco;
7353 mutex_lock(&dev_priv->sb_lock);
7355 /* p1 and p2 divider */
7356 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7357 5 << DPIO_CHV_S1_DIV_SHIFT |
7358 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7359 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7360 1 << DPIO_CHV_K_DIV_SHIFT);
7362 /* Feedback post-divider - m2 */
7363 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7365 /* Feedback refclk divider - n and m1 */
7366 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7367 DPIO_CHV_M1_DIV_BY_2 |
7368 1 << DPIO_CHV_N_DIV_SHIFT);
7370 /* M2 fraction division */
7371 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7373 /* M2 fraction division enable */
7374 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7375 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7376 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7378 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7379 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7381 /* Program digital lock detect threshold */
7382 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7383 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7384 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7385 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7387 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7388 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7391 if (vco == 5400000) {
7392 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7393 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7394 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7395 tribuf_calcntr = 0x9;
7396 } else if (vco <= 6200000) {
7397 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7398 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7399 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7400 tribuf_calcntr = 0x9;
7401 } else if (vco <= 6480000) {
7402 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7403 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7404 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405 tribuf_calcntr = 0x8;
7407 /* Not supported. Apply the same limits as in the max case */
7408 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7409 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7410 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7413 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7415 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7416 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7417 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7418 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7421 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7422 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7425 mutex_unlock(&dev_priv->sb_lock);
7429 * vlv_force_pll_on - forcibly enable just the PLL
7430 * @dev_priv: i915 private structure
7431 * @pipe: pipe PLL to enable
7432 * @dpll: PLL configuration
7434 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7435 * in cases where we need the PLL enabled even when @pipe is not going to
7438 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7439 const struct dpll *dpll)
7441 struct intel_crtc *crtc =
7442 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7443 struct intel_crtc_state *pipe_config;
7445 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7449 pipe_config->base.crtc = &crtc->base;
7450 pipe_config->pixel_multiplier = 1;
7451 pipe_config->dpll = *dpll;
7453 if (IS_CHERRYVIEW(dev)) {
7454 chv_compute_dpll(crtc, pipe_config);
7455 chv_prepare_pll(crtc, pipe_config);
7456 chv_enable_pll(crtc, pipe_config);
7458 vlv_compute_dpll(crtc, pipe_config);
7459 vlv_prepare_pll(crtc, pipe_config);
7460 vlv_enable_pll(crtc, pipe_config);
7469 * vlv_force_pll_off - forcibly disable just the PLL
7470 * @dev_priv: i915 private structure
7471 * @pipe: pipe PLL to disable
7473 * Disable the PLL for @pipe. To be used in cases where we need
7474 * the PLL enabled even when @pipe is not going to be enabled.
7476 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7478 if (IS_CHERRYVIEW(dev))
7479 chv_disable_pll(to_i915(dev), pipe);
7481 vlv_disable_pll(to_i915(dev), pipe);
7484 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7485 struct intel_crtc_state *crtc_state,
7486 intel_clock_t *reduced_clock)
7488 struct drm_device *dev = crtc->base.dev;
7489 struct drm_i915_private *dev_priv = dev->dev_private;
7492 struct dpll *clock = &crtc_state->dpll;
7494 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7496 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7497 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7499 dpll = DPLL_VGA_MODE_DIS;
7501 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7502 dpll |= DPLLB_MODE_LVDS;
7504 dpll |= DPLLB_MODE_DAC_SERIAL;
7506 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7507 dpll |= (crtc_state->pixel_multiplier - 1)
7508 << SDVO_MULTIPLIER_SHIFT_HIRES;
7512 dpll |= DPLL_SDVO_HIGH_SPEED;
7514 if (crtc_state->has_dp_encoder)
7515 dpll |= DPLL_SDVO_HIGH_SPEED;
7517 /* compute bitmask from p1 value */
7518 if (IS_PINEVIEW(dev))
7519 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7521 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7522 if (IS_G4X(dev) && reduced_clock)
7523 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7525 switch (clock->p2) {
7527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7533 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7536 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7539 if (INTEL_INFO(dev)->gen >= 4)
7540 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7542 if (crtc_state->sdvo_tv_clock)
7543 dpll |= PLL_REF_INPUT_TVCLKINBC;
7544 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7545 intel_panel_use_ssc(dev_priv))
7546 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7548 dpll |= PLL_REF_INPUT_DREFCLK;
7550 dpll |= DPLL_VCO_ENABLE;
7551 crtc_state->dpll_hw_state.dpll = dpll;
7553 if (INTEL_INFO(dev)->gen >= 4) {
7554 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7555 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7556 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7560 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7561 struct intel_crtc_state *crtc_state,
7562 intel_clock_t *reduced_clock)
7564 struct drm_device *dev = crtc->base.dev;
7565 struct drm_i915_private *dev_priv = dev->dev_private;
7567 struct dpll *clock = &crtc_state->dpll;
7569 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7571 dpll = DPLL_VGA_MODE_DIS;
7573 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7574 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7577 dpll |= PLL_P1_DIVIDE_BY_TWO;
7579 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7581 dpll |= PLL_P2_DIVIDE_BY_4;
7584 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7585 dpll |= DPLL_DVO_2X_MODE;
7587 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7588 intel_panel_use_ssc(dev_priv))
7589 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7591 dpll |= PLL_REF_INPUT_DREFCLK;
7593 dpll |= DPLL_VCO_ENABLE;
7594 crtc_state->dpll_hw_state.dpll = dpll;
7597 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7599 struct drm_device *dev = intel_crtc->base.dev;
7600 struct drm_i915_private *dev_priv = dev->dev_private;
7601 enum pipe pipe = intel_crtc->pipe;
7602 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7603 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7604 uint32_t crtc_vtotal, crtc_vblank_end;
7607 /* We need to be careful not to changed the adjusted mode, for otherwise
7608 * the hw state checker will get angry at the mismatch. */
7609 crtc_vtotal = adjusted_mode->crtc_vtotal;
7610 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7612 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7613 /* the chip adds 2 halflines automatically */
7615 crtc_vblank_end -= 1;
7617 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7618 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7620 vsyncshift = adjusted_mode->crtc_hsync_start -
7621 adjusted_mode->crtc_htotal / 2;
7623 vsyncshift += adjusted_mode->crtc_htotal;
7626 if (INTEL_INFO(dev)->gen > 3)
7627 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7629 I915_WRITE(HTOTAL(cpu_transcoder),
7630 (adjusted_mode->crtc_hdisplay - 1) |
7631 ((adjusted_mode->crtc_htotal - 1) << 16));
7632 I915_WRITE(HBLANK(cpu_transcoder),
7633 (adjusted_mode->crtc_hblank_start - 1) |
7634 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7635 I915_WRITE(HSYNC(cpu_transcoder),
7636 (adjusted_mode->crtc_hsync_start - 1) |
7637 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7639 I915_WRITE(VTOTAL(cpu_transcoder),
7640 (adjusted_mode->crtc_vdisplay - 1) |
7641 ((crtc_vtotal - 1) << 16));
7642 I915_WRITE(VBLANK(cpu_transcoder),
7643 (adjusted_mode->crtc_vblank_start - 1) |
7644 ((crtc_vblank_end - 1) << 16));
7645 I915_WRITE(VSYNC(cpu_transcoder),
7646 (adjusted_mode->crtc_vsync_start - 1) |
7647 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7649 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7650 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7651 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7653 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7654 (pipe == PIPE_B || pipe == PIPE_C))
7655 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7659 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7661 struct drm_device *dev = intel_crtc->base.dev;
7662 struct drm_i915_private *dev_priv = dev->dev_private;
7663 enum pipe pipe = intel_crtc->pipe;
7665 /* pipesrc controls the size that is scaled from, which should
7666 * always be the user's requested size.
7668 I915_WRITE(PIPESRC(pipe),
7669 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7670 (intel_crtc->config->pipe_src_h - 1));
7673 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7674 struct intel_crtc_state *pipe_config)
7676 struct drm_device *dev = crtc->base.dev;
7677 struct drm_i915_private *dev_priv = dev->dev_private;
7678 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7681 tmp = I915_READ(HTOTAL(cpu_transcoder));
7682 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7684 tmp = I915_READ(HBLANK(cpu_transcoder));
7685 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7686 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7687 tmp = I915_READ(HSYNC(cpu_transcoder));
7688 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7689 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7691 tmp = I915_READ(VTOTAL(cpu_transcoder));
7692 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7693 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7694 tmp = I915_READ(VBLANK(cpu_transcoder));
7695 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7696 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7697 tmp = I915_READ(VSYNC(cpu_transcoder));
7698 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7699 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7701 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7702 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7703 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7704 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7708 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7709 struct intel_crtc_state *pipe_config)
7711 struct drm_device *dev = crtc->base.dev;
7712 struct drm_i915_private *dev_priv = dev->dev_private;
7715 tmp = I915_READ(PIPESRC(crtc->pipe));
7716 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7717 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7719 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7720 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7723 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7724 struct intel_crtc_state *pipe_config)
7726 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7727 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7728 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7729 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7731 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7732 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7733 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7734 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7736 mode->flags = pipe_config->base.adjusted_mode.flags;
7737 mode->type = DRM_MODE_TYPE_DRIVER;
7739 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7740 mode->flags |= pipe_config->base.adjusted_mode.flags;
7742 mode->hsync = drm_mode_hsync(mode);
7743 mode->vrefresh = drm_mode_vrefresh(mode);
7744 drm_mode_set_name(mode);
7747 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7749 struct drm_device *dev = intel_crtc->base.dev;
7750 struct drm_i915_private *dev_priv = dev->dev_private;
7755 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7756 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7757 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7759 if (intel_crtc->config->double_wide)
7760 pipeconf |= PIPECONF_DOUBLE_WIDE;
7762 /* only g4x and later have fancy bpc/dither controls */
7763 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7764 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7765 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7766 pipeconf |= PIPECONF_DITHER_EN |
7767 PIPECONF_DITHER_TYPE_SP;
7769 switch (intel_crtc->config->pipe_bpp) {
7771 pipeconf |= PIPECONF_6BPC;
7774 pipeconf |= PIPECONF_8BPC;
7777 pipeconf |= PIPECONF_10BPC;
7780 /* Case prevented by intel_choose_pipe_bpp_dither. */
7785 if (HAS_PIPE_CXSR(dev)) {
7786 if (intel_crtc->lowfreq_avail) {
7787 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7788 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7790 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7794 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7795 if (INTEL_INFO(dev)->gen < 4 ||
7796 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7797 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7799 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7801 pipeconf |= PIPECONF_PROGRESSIVE;
7803 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7804 intel_crtc->config->limited_color_range)
7805 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7807 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7808 POSTING_READ(PIPECONF(intel_crtc->pipe));
7811 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7812 struct intel_crtc_state *crtc_state)
7814 struct drm_device *dev = crtc->base.dev;
7815 struct drm_i915_private *dev_priv = dev->dev_private;
7816 const intel_limit_t *limit;
7819 memset(&crtc_state->dpll_hw_state, 0,
7820 sizeof(crtc_state->dpll_hw_state));
7822 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7823 if (intel_panel_use_ssc(dev_priv)) {
7824 refclk = dev_priv->vbt.lvds_ssc_freq;
7825 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7828 limit = &intel_limits_i8xx_lvds;
7829 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7830 limit = &intel_limits_i8xx_dvo;
7832 limit = &intel_limits_i8xx_dac;
7835 if (!crtc_state->clock_set &&
7836 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7837 refclk, NULL, &crtc_state->dpll)) {
7838 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7842 i8xx_compute_dpll(crtc, crtc_state, NULL);
7847 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7848 struct intel_crtc_state *crtc_state)
7850 struct drm_device *dev = crtc->base.dev;
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852 const intel_limit_t *limit;
7855 memset(&crtc_state->dpll_hw_state, 0,
7856 sizeof(crtc_state->dpll_hw_state));
7858 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7859 if (intel_panel_use_ssc(dev_priv)) {
7860 refclk = dev_priv->vbt.lvds_ssc_freq;
7861 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7864 if (intel_is_dual_link_lvds(dev))
7865 limit = &intel_limits_g4x_dual_channel_lvds;
7867 limit = &intel_limits_g4x_single_channel_lvds;
7868 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7869 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7870 limit = &intel_limits_g4x_hdmi;
7871 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7872 limit = &intel_limits_g4x_sdvo;
7874 /* The option is for other outputs */
7875 limit = &intel_limits_i9xx_sdvo;
7878 if (!crtc_state->clock_set &&
7879 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7880 refclk, NULL, &crtc_state->dpll)) {
7881 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7885 i9xx_compute_dpll(crtc, crtc_state, NULL);
7890 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7891 struct intel_crtc_state *crtc_state)
7893 struct drm_device *dev = crtc->base.dev;
7894 struct drm_i915_private *dev_priv = dev->dev_private;
7895 const intel_limit_t *limit;
7898 memset(&crtc_state->dpll_hw_state, 0,
7899 sizeof(crtc_state->dpll_hw_state));
7901 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7902 if (intel_panel_use_ssc(dev_priv)) {
7903 refclk = dev_priv->vbt.lvds_ssc_freq;
7904 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7907 limit = &intel_limits_pineview_lvds;
7909 limit = &intel_limits_pineview_sdvo;
7912 if (!crtc_state->clock_set &&
7913 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7914 refclk, NULL, &crtc_state->dpll)) {
7915 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7919 i9xx_compute_dpll(crtc, crtc_state, NULL);
7924 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7925 struct intel_crtc_state *crtc_state)
7927 struct drm_device *dev = crtc->base.dev;
7928 struct drm_i915_private *dev_priv = dev->dev_private;
7929 const intel_limit_t *limit;
7932 memset(&crtc_state->dpll_hw_state, 0,
7933 sizeof(crtc_state->dpll_hw_state));
7935 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7936 if (intel_panel_use_ssc(dev_priv)) {
7937 refclk = dev_priv->vbt.lvds_ssc_freq;
7938 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7941 limit = &intel_limits_i9xx_lvds;
7943 limit = &intel_limits_i9xx_sdvo;
7946 if (!crtc_state->clock_set &&
7947 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7948 refclk, NULL, &crtc_state->dpll)) {
7949 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7953 i9xx_compute_dpll(crtc, crtc_state, NULL);
7958 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7959 struct intel_crtc_state *crtc_state)
7961 int refclk = 100000;
7962 const intel_limit_t *limit = &intel_limits_chv;
7964 memset(&crtc_state->dpll_hw_state, 0,
7965 sizeof(crtc_state->dpll_hw_state));
7967 if (!crtc_state->clock_set &&
7968 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7969 refclk, NULL, &crtc_state->dpll)) {
7970 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7974 chv_compute_dpll(crtc, crtc_state);
7979 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7980 struct intel_crtc_state *crtc_state)
7982 int refclk = 100000;
7983 const intel_limit_t *limit = &intel_limits_vlv;
7985 memset(&crtc_state->dpll_hw_state, 0,
7986 sizeof(crtc_state->dpll_hw_state));
7988 if (!crtc_state->clock_set &&
7989 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7990 refclk, NULL, &crtc_state->dpll)) {
7991 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7995 vlv_compute_dpll(crtc, crtc_state);
8000 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8001 struct intel_crtc_state *pipe_config)
8003 struct drm_device *dev = crtc->base.dev;
8004 struct drm_i915_private *dev_priv = dev->dev_private;
8007 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8010 tmp = I915_READ(PFIT_CONTROL);
8011 if (!(tmp & PFIT_ENABLE))
8014 /* Check whether the pfit is attached to our pipe. */
8015 if (INTEL_INFO(dev)->gen < 4) {
8016 if (crtc->pipe != PIPE_B)
8019 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8023 pipe_config->gmch_pfit.control = tmp;
8024 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8027 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8028 struct intel_crtc_state *pipe_config)
8030 struct drm_device *dev = crtc->base.dev;
8031 struct drm_i915_private *dev_priv = dev->dev_private;
8032 int pipe = pipe_config->cpu_transcoder;
8033 intel_clock_t clock;
8035 int refclk = 100000;
8037 /* In case of DSI, DPLL will not be used */
8038 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8041 mutex_lock(&dev_priv->sb_lock);
8042 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8043 mutex_unlock(&dev_priv->sb_lock);
8045 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8046 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8047 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8048 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8049 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8051 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8055 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8056 struct intel_initial_plane_config *plane_config)
8058 struct drm_device *dev = crtc->base.dev;
8059 struct drm_i915_private *dev_priv = dev->dev_private;
8060 u32 val, base, offset;
8061 int pipe = crtc->pipe, plane = crtc->plane;
8062 int fourcc, pixel_format;
8063 unsigned int aligned_height;
8064 struct drm_framebuffer *fb;
8065 struct intel_framebuffer *intel_fb;
8067 val = I915_READ(DSPCNTR(plane));
8068 if (!(val & DISPLAY_PLANE_ENABLE))
8071 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8073 DRM_DEBUG_KMS("failed to alloc fb\n");
8077 fb = &intel_fb->base;
8079 if (INTEL_INFO(dev)->gen >= 4) {
8080 if (val & DISPPLANE_TILED) {
8081 plane_config->tiling = I915_TILING_X;
8082 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8086 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8087 fourcc = i9xx_format_to_fourcc(pixel_format);
8088 fb->pixel_format = fourcc;
8089 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8091 if (INTEL_INFO(dev)->gen >= 4) {
8092 if (plane_config->tiling)
8093 offset = I915_READ(DSPTILEOFF(plane));
8095 offset = I915_READ(DSPLINOFF(plane));
8096 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8098 base = I915_READ(DSPADDR(plane));
8100 plane_config->base = base;
8102 val = I915_READ(PIPESRC(pipe));
8103 fb->width = ((val >> 16) & 0xfff) + 1;
8104 fb->height = ((val >> 0) & 0xfff) + 1;
8106 val = I915_READ(DSPSTRIDE(pipe));
8107 fb->pitches[0] = val & 0xffffffc0;
8109 aligned_height = intel_fb_align_height(dev, fb->height,
8113 plane_config->size = fb->pitches[0] * aligned_height;
8115 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8116 pipe_name(pipe), plane, fb->width, fb->height,
8117 fb->bits_per_pixel, base, fb->pitches[0],
8118 plane_config->size);
8120 plane_config->fb = intel_fb;
8123 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8124 struct intel_crtc_state *pipe_config)
8126 struct drm_device *dev = crtc->base.dev;
8127 struct drm_i915_private *dev_priv = dev->dev_private;
8128 int pipe = pipe_config->cpu_transcoder;
8129 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8130 intel_clock_t clock;
8131 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8132 int refclk = 100000;
8134 /* In case of DSI, DPLL will not be used */
8135 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8138 mutex_lock(&dev_priv->sb_lock);
8139 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8140 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8141 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8142 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8143 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8144 mutex_unlock(&dev_priv->sb_lock);
8146 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8147 clock.m2 = (pll_dw0 & 0xff) << 22;
8148 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8149 clock.m2 |= pll_dw2 & 0x3fffff;
8150 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8151 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8152 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8154 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8157 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8158 struct intel_crtc_state *pipe_config)
8160 struct drm_device *dev = crtc->base.dev;
8161 struct drm_i915_private *dev_priv = dev->dev_private;
8162 enum intel_display_power_domain power_domain;
8166 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8167 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8170 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8171 pipe_config->shared_dpll = NULL;
8175 tmp = I915_READ(PIPECONF(crtc->pipe));
8176 if (!(tmp & PIPECONF_ENABLE))
8179 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8180 switch (tmp & PIPECONF_BPC_MASK) {
8182 pipe_config->pipe_bpp = 18;
8185 pipe_config->pipe_bpp = 24;
8187 case PIPECONF_10BPC:
8188 pipe_config->pipe_bpp = 30;
8195 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8196 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8197 pipe_config->limited_color_range = true;
8199 if (INTEL_INFO(dev)->gen < 4)
8200 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8202 intel_get_pipe_timings(crtc, pipe_config);
8203 intel_get_pipe_src_size(crtc, pipe_config);
8205 i9xx_get_pfit_config(crtc, pipe_config);
8207 if (INTEL_INFO(dev)->gen >= 4) {
8208 /* No way to read it out on pipes B and C */
8209 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8210 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8212 tmp = I915_READ(DPLL_MD(crtc->pipe));
8213 pipe_config->pixel_multiplier =
8214 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8215 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8216 pipe_config->dpll_hw_state.dpll_md = tmp;
8217 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8218 tmp = I915_READ(DPLL(crtc->pipe));
8219 pipe_config->pixel_multiplier =
8220 ((tmp & SDVO_MULTIPLIER_MASK)
8221 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8223 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8224 * port and will be fixed up in the encoder->get_config
8226 pipe_config->pixel_multiplier = 1;
8228 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8229 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8231 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8232 * on 830. Filter it out here so that we don't
8233 * report errors due to that.
8236 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8238 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8239 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8241 /* Mask out read-only status bits. */
8242 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8243 DPLL_PORTC_READY_MASK |
8244 DPLL_PORTB_READY_MASK);
8247 if (IS_CHERRYVIEW(dev))
8248 chv_crtc_clock_get(crtc, pipe_config);
8249 else if (IS_VALLEYVIEW(dev))
8250 vlv_crtc_clock_get(crtc, pipe_config);
8252 i9xx_crtc_clock_get(crtc, pipe_config);
8255 * Normally the dotclock is filled in by the encoder .get_config()
8256 * but in case the pipe is enabled w/o any ports we need a sane
8259 pipe_config->base.adjusted_mode.crtc_clock =
8260 pipe_config->port_clock / pipe_config->pixel_multiplier;
8265 intel_display_power_put(dev_priv, power_domain);
8270 static void ironlake_init_pch_refclk(struct drm_device *dev)
8272 struct drm_i915_private *dev_priv = dev->dev_private;
8273 struct intel_encoder *encoder;
8275 bool has_lvds = false;
8276 bool has_cpu_edp = false;
8277 bool has_panel = false;
8278 bool has_ck505 = false;
8279 bool can_ssc = false;
8281 /* We need to take the global config into account */
8282 for_each_intel_encoder(dev, encoder) {
8283 switch (encoder->type) {
8284 case INTEL_OUTPUT_LVDS:
8288 case INTEL_OUTPUT_EDP:
8290 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8298 if (HAS_PCH_IBX(dev)) {
8299 has_ck505 = dev_priv->vbt.display_clock_mode;
8300 can_ssc = has_ck505;
8306 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8307 has_panel, has_lvds, has_ck505);
8309 /* Ironlake: try to setup display ref clock before DPLL
8310 * enabling. This is only under driver's control after
8311 * PCH B stepping, previous chipset stepping should be
8312 * ignoring this setting.
8314 val = I915_READ(PCH_DREF_CONTROL);
8316 /* As we must carefully and slowly disable/enable each source in turn,
8317 * compute the final state we want first and check if we need to
8318 * make any changes at all.
8321 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8323 final |= DREF_NONSPREAD_CK505_ENABLE;
8325 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8327 final &= ~DREF_SSC_SOURCE_MASK;
8328 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8329 final &= ~DREF_SSC1_ENABLE;
8332 final |= DREF_SSC_SOURCE_ENABLE;
8334 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8335 final |= DREF_SSC1_ENABLE;
8338 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8339 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8341 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8343 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8345 final |= DREF_SSC_SOURCE_DISABLE;
8346 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8352 /* Always enable nonspread source */
8353 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8356 val |= DREF_NONSPREAD_CK505_ENABLE;
8358 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8361 val &= ~DREF_SSC_SOURCE_MASK;
8362 val |= DREF_SSC_SOURCE_ENABLE;
8364 /* SSC must be turned on before enabling the CPU output */
8365 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8366 DRM_DEBUG_KMS("Using SSC on panel\n");
8367 val |= DREF_SSC1_ENABLE;
8369 val &= ~DREF_SSC1_ENABLE;
8371 /* Get SSC going before enabling the outputs */
8372 I915_WRITE(PCH_DREF_CONTROL, val);
8373 POSTING_READ(PCH_DREF_CONTROL);
8376 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8378 /* Enable CPU source on CPU attached eDP */
8380 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8381 DRM_DEBUG_KMS("Using SSC on eDP\n");
8382 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8384 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8386 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8388 I915_WRITE(PCH_DREF_CONTROL, val);
8389 POSTING_READ(PCH_DREF_CONTROL);
8392 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8394 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8396 /* Turn off CPU output */
8397 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8399 I915_WRITE(PCH_DREF_CONTROL, val);
8400 POSTING_READ(PCH_DREF_CONTROL);
8403 /* Turn off the SSC source */
8404 val &= ~DREF_SSC_SOURCE_MASK;
8405 val |= DREF_SSC_SOURCE_DISABLE;
8408 val &= ~DREF_SSC1_ENABLE;
8410 I915_WRITE(PCH_DREF_CONTROL, val);
8411 POSTING_READ(PCH_DREF_CONTROL);
8415 BUG_ON(val != final);
8418 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8422 tmp = I915_READ(SOUTH_CHICKEN2);
8423 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8424 I915_WRITE(SOUTH_CHICKEN2, tmp);
8426 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8427 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8428 DRM_ERROR("FDI mPHY reset assert timeout\n");
8430 tmp = I915_READ(SOUTH_CHICKEN2);
8431 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8432 I915_WRITE(SOUTH_CHICKEN2, tmp);
8434 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8435 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8436 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8439 /* WaMPhyProgramming:hsw */
8440 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8444 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8445 tmp &= ~(0xFF << 24);
8446 tmp |= (0x12 << 24);
8447 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8449 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8451 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8453 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8455 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8457 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8458 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8459 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8461 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8462 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8463 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8465 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8468 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8470 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8473 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8475 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8478 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8480 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8483 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8485 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8486 tmp &= ~(0xFF << 16);
8487 tmp |= (0x1C << 16);
8488 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8490 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8491 tmp &= ~(0xFF << 16);
8492 tmp |= (0x1C << 16);
8493 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8495 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8497 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8499 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8501 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8503 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8504 tmp &= ~(0xF << 28);
8506 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8508 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8509 tmp &= ~(0xF << 28);
8511 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8514 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8515 * Programming" based on the parameters passed:
8516 * - Sequence to enable CLKOUT_DP
8517 * - Sequence to enable CLKOUT_DP without spread
8518 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8520 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8523 struct drm_i915_private *dev_priv = dev->dev_private;
8526 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8528 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8531 mutex_lock(&dev_priv->sb_lock);
8533 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8534 tmp &= ~SBI_SSCCTL_DISABLE;
8535 tmp |= SBI_SSCCTL_PATHALT;
8536 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8541 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8542 tmp &= ~SBI_SSCCTL_PATHALT;
8543 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8546 lpt_reset_fdi_mphy(dev_priv);
8547 lpt_program_fdi_mphy(dev_priv);
8551 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8552 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8553 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8554 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8556 mutex_unlock(&dev_priv->sb_lock);
8559 /* Sequence to disable CLKOUT_DP */
8560 static void lpt_disable_clkout_dp(struct drm_device *dev)
8562 struct drm_i915_private *dev_priv = dev->dev_private;
8565 mutex_lock(&dev_priv->sb_lock);
8567 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8568 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8569 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8570 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8572 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8573 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8574 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8575 tmp |= SBI_SSCCTL_PATHALT;
8576 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8579 tmp |= SBI_SSCCTL_DISABLE;
8580 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8583 mutex_unlock(&dev_priv->sb_lock);
8586 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8588 static const uint16_t sscdivintphase[] = {
8589 [BEND_IDX( 50)] = 0x3B23,
8590 [BEND_IDX( 45)] = 0x3B23,
8591 [BEND_IDX( 40)] = 0x3C23,
8592 [BEND_IDX( 35)] = 0x3C23,
8593 [BEND_IDX( 30)] = 0x3D23,
8594 [BEND_IDX( 25)] = 0x3D23,
8595 [BEND_IDX( 20)] = 0x3E23,
8596 [BEND_IDX( 15)] = 0x3E23,
8597 [BEND_IDX( 10)] = 0x3F23,
8598 [BEND_IDX( 5)] = 0x3F23,
8599 [BEND_IDX( 0)] = 0x0025,
8600 [BEND_IDX( -5)] = 0x0025,
8601 [BEND_IDX(-10)] = 0x0125,
8602 [BEND_IDX(-15)] = 0x0125,
8603 [BEND_IDX(-20)] = 0x0225,
8604 [BEND_IDX(-25)] = 0x0225,
8605 [BEND_IDX(-30)] = 0x0325,
8606 [BEND_IDX(-35)] = 0x0325,
8607 [BEND_IDX(-40)] = 0x0425,
8608 [BEND_IDX(-45)] = 0x0425,
8609 [BEND_IDX(-50)] = 0x0525,
8614 * steps -50 to 50 inclusive, in steps of 5
8615 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8616 * change in clock period = -(steps / 10) * 5.787 ps
8618 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8621 int idx = BEND_IDX(steps);
8623 if (WARN_ON(steps % 5 != 0))
8626 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8629 mutex_lock(&dev_priv->sb_lock);
8631 if (steps % 10 != 0)
8635 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8637 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8639 tmp |= sscdivintphase[idx];
8640 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8642 mutex_unlock(&dev_priv->sb_lock);
8647 static void lpt_init_pch_refclk(struct drm_device *dev)
8649 struct intel_encoder *encoder;
8650 bool has_vga = false;
8652 for_each_intel_encoder(dev, encoder) {
8653 switch (encoder->type) {
8654 case INTEL_OUTPUT_ANALOG:
8663 lpt_bend_clkout_dp(to_i915(dev), 0);
8664 lpt_enable_clkout_dp(dev, true, true);
8666 lpt_disable_clkout_dp(dev);
8671 * Initialize reference clocks when the driver loads
8673 void intel_init_pch_refclk(struct drm_device *dev)
8675 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8676 ironlake_init_pch_refclk(dev);
8677 else if (HAS_PCH_LPT(dev))
8678 lpt_init_pch_refclk(dev);
8681 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8683 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8685 int pipe = intel_crtc->pipe;
8690 switch (intel_crtc->config->pipe_bpp) {
8692 val |= PIPECONF_6BPC;
8695 val |= PIPECONF_8BPC;
8698 val |= PIPECONF_10BPC;
8701 val |= PIPECONF_12BPC;
8704 /* Case prevented by intel_choose_pipe_bpp_dither. */
8708 if (intel_crtc->config->dither)
8709 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8711 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8712 val |= PIPECONF_INTERLACED_ILK;
8714 val |= PIPECONF_PROGRESSIVE;
8716 if (intel_crtc->config->limited_color_range)
8717 val |= PIPECONF_COLOR_RANGE_SELECT;
8719 I915_WRITE(PIPECONF(pipe), val);
8720 POSTING_READ(PIPECONF(pipe));
8723 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8725 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8727 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8730 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8731 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8733 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8734 val |= PIPECONF_INTERLACED_ILK;
8736 val |= PIPECONF_PROGRESSIVE;
8738 I915_WRITE(PIPECONF(cpu_transcoder), val);
8739 POSTING_READ(PIPECONF(cpu_transcoder));
8742 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8744 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8747 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8750 switch (intel_crtc->config->pipe_bpp) {
8752 val |= PIPEMISC_DITHER_6_BPC;
8755 val |= PIPEMISC_DITHER_8_BPC;
8758 val |= PIPEMISC_DITHER_10_BPC;
8761 val |= PIPEMISC_DITHER_12_BPC;
8764 /* Case prevented by pipe_config_set_bpp. */
8768 if (intel_crtc->config->dither)
8769 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8771 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8775 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8778 * Account for spread spectrum to avoid
8779 * oversubscribing the link. Max center spread
8780 * is 2.5%; use 5% for safety's sake.
8782 u32 bps = target_clock * bpp * 21 / 20;
8783 return DIV_ROUND_UP(bps, link_bw * 8);
8786 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8788 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8791 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8792 struct intel_crtc_state *crtc_state,
8793 intel_clock_t *reduced_clock)
8795 struct drm_crtc *crtc = &intel_crtc->base;
8796 struct drm_device *dev = crtc->dev;
8797 struct drm_i915_private *dev_priv = dev->dev_private;
8798 struct drm_atomic_state *state = crtc_state->base.state;
8799 struct drm_connector *connector;
8800 struct drm_connector_state *connector_state;
8801 struct intel_encoder *encoder;
8804 bool is_lvds = false, is_sdvo = false;
8806 for_each_connector_in_state(state, connector, connector_state, i) {
8807 if (connector_state->crtc != crtc_state->base.crtc)
8810 encoder = to_intel_encoder(connector_state->best_encoder);
8812 switch (encoder->type) {
8813 case INTEL_OUTPUT_LVDS:
8816 case INTEL_OUTPUT_SDVO:
8817 case INTEL_OUTPUT_HDMI:
8825 /* Enable autotuning of the PLL clock (if permissible) */
8828 if ((intel_panel_use_ssc(dev_priv) &&
8829 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8830 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8832 } else if (crtc_state->sdvo_tv_clock)
8835 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8837 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8840 if (reduced_clock) {
8841 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8843 if (reduced_clock->m < factor * reduced_clock->n)
8852 dpll |= DPLLB_MODE_LVDS;
8854 dpll |= DPLLB_MODE_DAC_SERIAL;
8856 dpll |= (crtc_state->pixel_multiplier - 1)
8857 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8860 dpll |= DPLL_SDVO_HIGH_SPEED;
8861 if (crtc_state->has_dp_encoder)
8862 dpll |= DPLL_SDVO_HIGH_SPEED;
8864 /* compute bitmask from p1 value */
8865 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8867 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8869 switch (crtc_state->dpll.p2) {
8871 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8874 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8877 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8880 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8884 if (is_lvds && intel_panel_use_ssc(dev_priv))
8885 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8887 dpll |= PLL_REF_INPUT_DREFCLK;
8889 dpll |= DPLL_VCO_ENABLE;
8891 crtc_state->dpll_hw_state.dpll = dpll;
8892 crtc_state->dpll_hw_state.fp0 = fp;
8893 crtc_state->dpll_hw_state.fp1 = fp2;
8896 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8897 struct intel_crtc_state *crtc_state)
8899 struct drm_device *dev = crtc->base.dev;
8900 struct drm_i915_private *dev_priv = dev->dev_private;
8901 intel_clock_t reduced_clock;
8902 bool has_reduced_clock = false;
8903 struct intel_shared_dpll *pll;
8904 const intel_limit_t *limit;
8905 int refclk = 120000;
8907 memset(&crtc_state->dpll_hw_state, 0,
8908 sizeof(crtc_state->dpll_hw_state));
8910 crtc->lowfreq_avail = false;
8912 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8913 if (!crtc_state->has_pch_encoder)
8916 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8917 if (intel_panel_use_ssc(dev_priv)) {
8918 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8919 dev_priv->vbt.lvds_ssc_freq);
8920 refclk = dev_priv->vbt.lvds_ssc_freq;
8923 if (intel_is_dual_link_lvds(dev)) {
8924 if (refclk == 100000)
8925 limit = &intel_limits_ironlake_dual_lvds_100m;
8927 limit = &intel_limits_ironlake_dual_lvds;
8929 if (refclk == 100000)
8930 limit = &intel_limits_ironlake_single_lvds_100m;
8932 limit = &intel_limits_ironlake_single_lvds;
8935 limit = &intel_limits_ironlake_dac;
8938 if (!crtc_state->clock_set &&
8939 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8940 refclk, NULL, &crtc_state->dpll)) {
8941 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8945 ironlake_compute_dpll(crtc, crtc_state,
8946 has_reduced_clock ? &reduced_clock : NULL);
8948 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8950 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8951 pipe_name(crtc->pipe));
8955 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8957 crtc->lowfreq_avail = true;
8962 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8963 struct intel_link_m_n *m_n)
8965 struct drm_device *dev = crtc->base.dev;
8966 struct drm_i915_private *dev_priv = dev->dev_private;
8967 enum pipe pipe = crtc->pipe;
8969 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8970 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8971 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8973 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8974 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8975 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8978 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8979 enum transcoder transcoder,
8980 struct intel_link_m_n *m_n,
8981 struct intel_link_m_n *m2_n2)
8983 struct drm_device *dev = crtc->base.dev;
8984 struct drm_i915_private *dev_priv = dev->dev_private;
8985 enum pipe pipe = crtc->pipe;
8987 if (INTEL_INFO(dev)->gen >= 5) {
8988 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8989 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8990 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8992 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8993 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8994 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8995 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8996 * gen < 8) and if DRRS is supported (to make sure the
8997 * registers are not unnecessarily read).
8999 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9000 crtc->config->has_drrs) {
9001 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9002 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9003 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9005 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9006 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9007 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9010 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9011 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9012 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9014 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9015 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9016 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9020 void intel_dp_get_m_n(struct intel_crtc *crtc,
9021 struct intel_crtc_state *pipe_config)
9023 if (pipe_config->has_pch_encoder)
9024 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9026 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9027 &pipe_config->dp_m_n,
9028 &pipe_config->dp_m2_n2);
9031 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9032 struct intel_crtc_state *pipe_config)
9034 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9035 &pipe_config->fdi_m_n, NULL);
9038 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9039 struct intel_crtc_state *pipe_config)
9041 struct drm_device *dev = crtc->base.dev;
9042 struct drm_i915_private *dev_priv = dev->dev_private;
9043 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9044 uint32_t ps_ctrl = 0;
9048 /* find scaler attached to this pipe */
9049 for (i = 0; i < crtc->num_scalers; i++) {
9050 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9051 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9053 pipe_config->pch_pfit.enabled = true;
9054 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9055 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9060 scaler_state->scaler_id = id;
9062 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9064 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9069 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9070 struct intel_initial_plane_config *plane_config)
9072 struct drm_device *dev = crtc->base.dev;
9073 struct drm_i915_private *dev_priv = dev->dev_private;
9074 u32 val, base, offset, stride_mult, tiling;
9075 int pipe = crtc->pipe;
9076 int fourcc, pixel_format;
9077 unsigned int aligned_height;
9078 struct drm_framebuffer *fb;
9079 struct intel_framebuffer *intel_fb;
9081 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9083 DRM_DEBUG_KMS("failed to alloc fb\n");
9087 fb = &intel_fb->base;
9089 val = I915_READ(PLANE_CTL(pipe, 0));
9090 if (!(val & PLANE_CTL_ENABLE))
9093 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9094 fourcc = skl_format_to_fourcc(pixel_format,
9095 val & PLANE_CTL_ORDER_RGBX,
9096 val & PLANE_CTL_ALPHA_MASK);
9097 fb->pixel_format = fourcc;
9098 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9100 tiling = val & PLANE_CTL_TILED_MASK;
9102 case PLANE_CTL_TILED_LINEAR:
9103 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9105 case PLANE_CTL_TILED_X:
9106 plane_config->tiling = I915_TILING_X;
9107 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9109 case PLANE_CTL_TILED_Y:
9110 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9112 case PLANE_CTL_TILED_YF:
9113 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9116 MISSING_CASE(tiling);
9120 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9121 plane_config->base = base;
9123 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9125 val = I915_READ(PLANE_SIZE(pipe, 0));
9126 fb->height = ((val >> 16) & 0xfff) + 1;
9127 fb->width = ((val >> 0) & 0x1fff) + 1;
9129 val = I915_READ(PLANE_STRIDE(pipe, 0));
9130 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9132 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9134 aligned_height = intel_fb_align_height(dev, fb->height,
9138 plane_config->size = fb->pitches[0] * aligned_height;
9140 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9141 pipe_name(pipe), fb->width, fb->height,
9142 fb->bits_per_pixel, base, fb->pitches[0],
9143 plane_config->size);
9145 plane_config->fb = intel_fb;
9152 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9153 struct intel_crtc_state *pipe_config)
9155 struct drm_device *dev = crtc->base.dev;
9156 struct drm_i915_private *dev_priv = dev->dev_private;
9159 tmp = I915_READ(PF_CTL(crtc->pipe));
9161 if (tmp & PF_ENABLE) {
9162 pipe_config->pch_pfit.enabled = true;
9163 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9164 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9166 /* We currently do not free assignements of panel fitters on
9167 * ivb/hsw (since we don't use the higher upscaling modes which
9168 * differentiates them) so just WARN about this case for now. */
9170 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9171 PF_PIPE_SEL_IVB(crtc->pipe));
9177 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9178 struct intel_initial_plane_config *plane_config)
9180 struct drm_device *dev = crtc->base.dev;
9181 struct drm_i915_private *dev_priv = dev->dev_private;
9182 u32 val, base, offset;
9183 int pipe = crtc->pipe;
9184 int fourcc, pixel_format;
9185 unsigned int aligned_height;
9186 struct drm_framebuffer *fb;
9187 struct intel_framebuffer *intel_fb;
9189 val = I915_READ(DSPCNTR(pipe));
9190 if (!(val & DISPLAY_PLANE_ENABLE))
9193 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9195 DRM_DEBUG_KMS("failed to alloc fb\n");
9199 fb = &intel_fb->base;
9201 if (INTEL_INFO(dev)->gen >= 4) {
9202 if (val & DISPPLANE_TILED) {
9203 plane_config->tiling = I915_TILING_X;
9204 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9208 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9209 fourcc = i9xx_format_to_fourcc(pixel_format);
9210 fb->pixel_format = fourcc;
9211 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9213 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9214 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9215 offset = I915_READ(DSPOFFSET(pipe));
9217 if (plane_config->tiling)
9218 offset = I915_READ(DSPTILEOFF(pipe));
9220 offset = I915_READ(DSPLINOFF(pipe));
9222 plane_config->base = base;
9224 val = I915_READ(PIPESRC(pipe));
9225 fb->width = ((val >> 16) & 0xfff) + 1;
9226 fb->height = ((val >> 0) & 0xfff) + 1;
9228 val = I915_READ(DSPSTRIDE(pipe));
9229 fb->pitches[0] = val & 0xffffffc0;
9231 aligned_height = intel_fb_align_height(dev, fb->height,
9235 plane_config->size = fb->pitches[0] * aligned_height;
9237 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9238 pipe_name(pipe), fb->width, fb->height,
9239 fb->bits_per_pixel, base, fb->pitches[0],
9240 plane_config->size);
9242 plane_config->fb = intel_fb;
9245 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9246 struct intel_crtc_state *pipe_config)
9248 struct drm_device *dev = crtc->base.dev;
9249 struct drm_i915_private *dev_priv = dev->dev_private;
9250 enum intel_display_power_domain power_domain;
9254 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9255 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9258 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9259 pipe_config->shared_dpll = NULL;
9262 tmp = I915_READ(PIPECONF(crtc->pipe));
9263 if (!(tmp & PIPECONF_ENABLE))
9266 switch (tmp & PIPECONF_BPC_MASK) {
9268 pipe_config->pipe_bpp = 18;
9271 pipe_config->pipe_bpp = 24;
9273 case PIPECONF_10BPC:
9274 pipe_config->pipe_bpp = 30;
9276 case PIPECONF_12BPC:
9277 pipe_config->pipe_bpp = 36;
9283 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9284 pipe_config->limited_color_range = true;
9286 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9287 struct intel_shared_dpll *pll;
9288 enum intel_dpll_id pll_id;
9290 pipe_config->has_pch_encoder = true;
9292 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9293 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9294 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9296 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9298 if (HAS_PCH_IBX(dev_priv)) {
9299 pll_id = (enum intel_dpll_id) crtc->pipe;
9301 tmp = I915_READ(PCH_DPLL_SEL);
9302 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9303 pll_id = DPLL_ID_PCH_PLL_B;
9305 pll_id= DPLL_ID_PCH_PLL_A;
9308 pipe_config->shared_dpll =
9309 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9310 pll = pipe_config->shared_dpll;
9312 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9313 &pipe_config->dpll_hw_state));
9315 tmp = pipe_config->dpll_hw_state.dpll;
9316 pipe_config->pixel_multiplier =
9317 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9318 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9320 ironlake_pch_clock_get(crtc, pipe_config);
9322 pipe_config->pixel_multiplier = 1;
9325 intel_get_pipe_timings(crtc, pipe_config);
9326 intel_get_pipe_src_size(crtc, pipe_config);
9328 ironlake_get_pfit_config(crtc, pipe_config);
9333 intel_display_power_put(dev_priv, power_domain);
9338 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9340 struct drm_device *dev = dev_priv->dev;
9341 struct intel_crtc *crtc;
9343 for_each_intel_crtc(dev, crtc)
9344 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9345 pipe_name(crtc->pipe));
9347 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9348 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9349 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9350 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9351 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9352 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9353 "CPU PWM1 enabled\n");
9354 if (IS_HASWELL(dev))
9355 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9356 "CPU PWM2 enabled\n");
9357 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9358 "PCH PWM1 enabled\n");
9359 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9360 "Utility pin enabled\n");
9361 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9364 * In theory we can still leave IRQs enabled, as long as only the HPD
9365 * interrupts remain enabled. We used to check for that, but since it's
9366 * gen-specific and since we only disable LCPLL after we fully disable
9367 * the interrupts, the check below should be enough.
9369 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9372 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9374 struct drm_device *dev = dev_priv->dev;
9376 if (IS_HASWELL(dev))
9377 return I915_READ(D_COMP_HSW);
9379 return I915_READ(D_COMP_BDW);
9382 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9384 struct drm_device *dev = dev_priv->dev;
9386 if (IS_HASWELL(dev)) {
9387 mutex_lock(&dev_priv->rps.hw_lock);
9388 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9390 DRM_ERROR("Failed to write to D_COMP\n");
9391 mutex_unlock(&dev_priv->rps.hw_lock);
9393 I915_WRITE(D_COMP_BDW, val);
9394 POSTING_READ(D_COMP_BDW);
9399 * This function implements pieces of two sequences from BSpec:
9400 * - Sequence for display software to disable LCPLL
9401 * - Sequence for display software to allow package C8+
9402 * The steps implemented here are just the steps that actually touch the LCPLL
9403 * register. Callers should take care of disabling all the display engine
9404 * functions, doing the mode unset, fixing interrupts, etc.
9406 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9407 bool switch_to_fclk, bool allow_power_down)
9411 assert_can_disable_lcpll(dev_priv);
9413 val = I915_READ(LCPLL_CTL);
9415 if (switch_to_fclk) {
9416 val |= LCPLL_CD_SOURCE_FCLK;
9417 I915_WRITE(LCPLL_CTL, val);
9419 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9420 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9421 DRM_ERROR("Switching to FCLK failed\n");
9423 val = I915_READ(LCPLL_CTL);
9426 val |= LCPLL_PLL_DISABLE;
9427 I915_WRITE(LCPLL_CTL, val);
9428 POSTING_READ(LCPLL_CTL);
9430 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9431 DRM_ERROR("LCPLL still locked\n");
9433 val = hsw_read_dcomp(dev_priv);
9434 val |= D_COMP_COMP_DISABLE;
9435 hsw_write_dcomp(dev_priv, val);
9438 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9440 DRM_ERROR("D_COMP RCOMP still in progress\n");
9442 if (allow_power_down) {
9443 val = I915_READ(LCPLL_CTL);
9444 val |= LCPLL_POWER_DOWN_ALLOW;
9445 I915_WRITE(LCPLL_CTL, val);
9446 POSTING_READ(LCPLL_CTL);
9451 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9454 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9458 val = I915_READ(LCPLL_CTL);
9460 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9461 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9465 * Make sure we're not on PC8 state before disabling PC8, otherwise
9466 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9468 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9470 if (val & LCPLL_POWER_DOWN_ALLOW) {
9471 val &= ~LCPLL_POWER_DOWN_ALLOW;
9472 I915_WRITE(LCPLL_CTL, val);
9473 POSTING_READ(LCPLL_CTL);
9476 val = hsw_read_dcomp(dev_priv);
9477 val |= D_COMP_COMP_FORCE;
9478 val &= ~D_COMP_COMP_DISABLE;
9479 hsw_write_dcomp(dev_priv, val);
9481 val = I915_READ(LCPLL_CTL);
9482 val &= ~LCPLL_PLL_DISABLE;
9483 I915_WRITE(LCPLL_CTL, val);
9485 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9486 DRM_ERROR("LCPLL not locked yet\n");
9488 if (val & LCPLL_CD_SOURCE_FCLK) {
9489 val = I915_READ(LCPLL_CTL);
9490 val &= ~LCPLL_CD_SOURCE_FCLK;
9491 I915_WRITE(LCPLL_CTL, val);
9493 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9494 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9495 DRM_ERROR("Switching back to LCPLL failed\n");
9498 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9499 intel_update_cdclk(dev_priv->dev);
9503 * Package states C8 and deeper are really deep PC states that can only be
9504 * reached when all the devices on the system allow it, so even if the graphics
9505 * device allows PC8+, it doesn't mean the system will actually get to these
9506 * states. Our driver only allows PC8+ when going into runtime PM.
9508 * The requirements for PC8+ are that all the outputs are disabled, the power
9509 * well is disabled and most interrupts are disabled, and these are also
9510 * requirements for runtime PM. When these conditions are met, we manually do
9511 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9512 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9515 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9516 * the state of some registers, so when we come back from PC8+ we need to
9517 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9518 * need to take care of the registers kept by RC6. Notice that this happens even
9519 * if we don't put the device in PCI D3 state (which is what currently happens
9520 * because of the runtime PM support).
9522 * For more, read "Display Sequences for Package C8" on the hardware
9525 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9527 struct drm_device *dev = dev_priv->dev;
9530 DRM_DEBUG_KMS("Enabling package C8+\n");
9532 if (HAS_PCH_LPT_LP(dev)) {
9533 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9534 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9535 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9538 lpt_disable_clkout_dp(dev);
9539 hsw_disable_lcpll(dev_priv, true, true);
9542 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9544 struct drm_device *dev = dev_priv->dev;
9547 DRM_DEBUG_KMS("Disabling package C8+\n");
9549 hsw_restore_lcpll(dev_priv);
9550 lpt_init_pch_refclk(dev);
9552 if (HAS_PCH_LPT_LP(dev)) {
9553 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9554 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9555 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9559 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9561 struct drm_device *dev = old_state->dev;
9562 struct intel_atomic_state *old_intel_state =
9563 to_intel_atomic_state(old_state);
9564 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9566 broxton_set_cdclk(to_i915(dev), req_cdclk);
9569 /* compute the max rate for new configuration */
9570 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9572 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9573 struct drm_i915_private *dev_priv = state->dev->dev_private;
9574 struct drm_crtc *crtc;
9575 struct drm_crtc_state *cstate;
9576 struct intel_crtc_state *crtc_state;
9577 unsigned max_pixel_rate = 0, i;
9580 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9581 sizeof(intel_state->min_pixclk));
9583 for_each_crtc_in_state(state, crtc, cstate, i) {
9586 crtc_state = to_intel_crtc_state(cstate);
9587 if (!crtc_state->base.enable) {
9588 intel_state->min_pixclk[i] = 0;
9592 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9594 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9595 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9596 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9598 intel_state->min_pixclk[i] = pixel_rate;
9601 for_each_pipe(dev_priv, pipe)
9602 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9604 return max_pixel_rate;
9607 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9609 struct drm_i915_private *dev_priv = dev->dev_private;
9613 if (WARN((I915_READ(LCPLL_CTL) &
9614 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9615 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9616 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9617 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9618 "trying to change cdclk frequency with cdclk not enabled\n"))
9621 mutex_lock(&dev_priv->rps.hw_lock);
9622 ret = sandybridge_pcode_write(dev_priv,
9623 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9624 mutex_unlock(&dev_priv->rps.hw_lock);
9626 DRM_ERROR("failed to inform pcode about cdclk change\n");
9630 val = I915_READ(LCPLL_CTL);
9631 val |= LCPLL_CD_SOURCE_FCLK;
9632 I915_WRITE(LCPLL_CTL, val);
9634 if (wait_for_us(I915_READ(LCPLL_CTL) &
9635 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9636 DRM_ERROR("Switching to FCLK failed\n");
9638 val = I915_READ(LCPLL_CTL);
9639 val &= ~LCPLL_CLK_FREQ_MASK;
9643 val |= LCPLL_CLK_FREQ_450;
9647 val |= LCPLL_CLK_FREQ_54O_BDW;
9651 val |= LCPLL_CLK_FREQ_337_5_BDW;
9655 val |= LCPLL_CLK_FREQ_675_BDW;
9659 WARN(1, "invalid cdclk frequency\n");
9663 I915_WRITE(LCPLL_CTL, val);
9665 val = I915_READ(LCPLL_CTL);
9666 val &= ~LCPLL_CD_SOURCE_FCLK;
9667 I915_WRITE(LCPLL_CTL, val);
9669 if (wait_for_us((I915_READ(LCPLL_CTL) &
9670 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9671 DRM_ERROR("Switching back to LCPLL failed\n");
9673 mutex_lock(&dev_priv->rps.hw_lock);
9674 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9675 mutex_unlock(&dev_priv->rps.hw_lock);
9677 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9679 intel_update_cdclk(dev);
9681 WARN(cdclk != dev_priv->cdclk_freq,
9682 "cdclk requested %d kHz but got %d kHz\n",
9683 cdclk, dev_priv->cdclk_freq);
9686 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9688 struct drm_i915_private *dev_priv = to_i915(state->dev);
9689 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9690 int max_pixclk = ilk_max_pixel_rate(state);
9694 * FIXME should also account for plane ratio
9695 * once 64bpp pixel formats are supported.
9697 if (max_pixclk > 540000)
9699 else if (max_pixclk > 450000)
9701 else if (max_pixclk > 337500)
9706 if (cdclk > dev_priv->max_cdclk_freq) {
9707 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9708 cdclk, dev_priv->max_cdclk_freq);
9712 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9713 if (!intel_state->active_crtcs)
9714 intel_state->dev_cdclk = 337500;
9719 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9721 struct drm_device *dev = old_state->dev;
9722 struct intel_atomic_state *old_intel_state =
9723 to_intel_atomic_state(old_state);
9724 unsigned req_cdclk = old_intel_state->dev_cdclk;
9726 broadwell_set_cdclk(dev, req_cdclk);
9729 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9730 struct intel_crtc_state *crtc_state)
9732 struct intel_encoder *intel_encoder =
9733 intel_ddi_get_crtc_new_encoder(crtc_state);
9735 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9736 if (!intel_ddi_pll_select(crtc, crtc_state))
9740 crtc->lowfreq_avail = false;
9745 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9747 struct intel_crtc_state *pipe_config)
9749 enum intel_dpll_id id;
9753 pipe_config->ddi_pll_sel = SKL_DPLL0;
9754 id = DPLL_ID_SKL_DPLL0;
9757 pipe_config->ddi_pll_sel = SKL_DPLL1;
9758 id = DPLL_ID_SKL_DPLL1;
9761 pipe_config->ddi_pll_sel = SKL_DPLL2;
9762 id = DPLL_ID_SKL_DPLL2;
9765 DRM_ERROR("Incorrect port type\n");
9769 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9772 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9774 struct intel_crtc_state *pipe_config)
9776 enum intel_dpll_id id;
9779 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9780 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9782 switch (pipe_config->ddi_pll_sel) {
9784 id = DPLL_ID_SKL_DPLL0;
9787 id = DPLL_ID_SKL_DPLL1;
9790 id = DPLL_ID_SKL_DPLL2;
9793 id = DPLL_ID_SKL_DPLL3;
9796 MISSING_CASE(pipe_config->ddi_pll_sel);
9800 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9803 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9805 struct intel_crtc_state *pipe_config)
9807 enum intel_dpll_id id;
9809 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9811 switch (pipe_config->ddi_pll_sel) {
9812 case PORT_CLK_SEL_WRPLL1:
9813 id = DPLL_ID_WRPLL1;
9815 case PORT_CLK_SEL_WRPLL2:
9816 id = DPLL_ID_WRPLL2;
9818 case PORT_CLK_SEL_SPLL:
9821 case PORT_CLK_SEL_LCPLL_810:
9822 id = DPLL_ID_LCPLL_810;
9824 case PORT_CLK_SEL_LCPLL_1350:
9825 id = DPLL_ID_LCPLL_1350;
9827 case PORT_CLK_SEL_LCPLL_2700:
9828 id = DPLL_ID_LCPLL_2700;
9831 MISSING_CASE(pipe_config->ddi_pll_sel);
9833 case PORT_CLK_SEL_NONE:
9837 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9840 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9841 struct intel_crtc_state *pipe_config,
9842 unsigned long *power_domain_mask)
9844 struct drm_device *dev = crtc->base.dev;
9845 struct drm_i915_private *dev_priv = dev->dev_private;
9846 enum intel_display_power_domain power_domain;
9849 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9852 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9853 * consistency and less surprising code; it's in always on power).
9855 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9856 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9857 enum pipe trans_edp_pipe;
9858 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9860 WARN(1, "unknown pipe linked to edp transcoder\n");
9861 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9862 case TRANS_DDI_EDP_INPUT_A_ON:
9863 trans_edp_pipe = PIPE_A;
9865 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9866 trans_edp_pipe = PIPE_B;
9868 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9869 trans_edp_pipe = PIPE_C;
9873 if (trans_edp_pipe == crtc->pipe)
9874 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9877 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9878 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9880 *power_domain_mask |= BIT(power_domain);
9882 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9884 return tmp & PIPECONF_ENABLE;
9887 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9888 struct intel_crtc_state *pipe_config,
9889 unsigned long *power_domain_mask)
9891 struct drm_device *dev = crtc->base.dev;
9892 struct drm_i915_private *dev_priv = dev->dev_private;
9893 enum intel_display_power_domain power_domain;
9895 enum transcoder cpu_transcoder;
9898 pipe_config->has_dsi_encoder = false;
9900 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9902 cpu_transcoder = TRANSCODER_DSI_A;
9904 cpu_transcoder = TRANSCODER_DSI_C;
9906 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9907 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9909 *power_domain_mask |= BIT(power_domain);
9912 * The PLL needs to be enabled with a valid divider
9913 * configuration, otherwise accessing DSI registers will hang
9914 * the machine. See BSpec North Display Engine
9915 * registers/MIPI[BXT]. We can break out here early, since we
9916 * need the same DSI PLL to be enabled for both DSI ports.
9918 if (!intel_dsi_pll_is_enabled(dev_priv))
9921 /* XXX: this works for video mode only */
9922 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9923 if (!(tmp & DPI_ENABLE))
9926 tmp = I915_READ(MIPI_CTRL(port));
9927 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9930 pipe_config->cpu_transcoder = cpu_transcoder;
9931 pipe_config->has_dsi_encoder = true;
9935 return pipe_config->has_dsi_encoder;
9938 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9939 struct intel_crtc_state *pipe_config)
9941 struct drm_device *dev = crtc->base.dev;
9942 struct drm_i915_private *dev_priv = dev->dev_private;
9943 struct intel_shared_dpll *pll;
9947 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9949 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9951 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9952 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9953 else if (IS_BROXTON(dev))
9954 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9956 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9958 pll = pipe_config->shared_dpll;
9960 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9961 &pipe_config->dpll_hw_state));
9965 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9966 * DDI E. So just check whether this pipe is wired to DDI E and whether
9967 * the PCH transcoder is on.
9969 if (INTEL_INFO(dev)->gen < 9 &&
9970 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9971 pipe_config->has_pch_encoder = true;
9973 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9974 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9975 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9977 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9981 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9982 struct intel_crtc_state *pipe_config)
9984 struct drm_device *dev = crtc->base.dev;
9985 struct drm_i915_private *dev_priv = dev->dev_private;
9986 enum intel_display_power_domain power_domain;
9987 unsigned long power_domain_mask;
9990 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9991 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9993 power_domain_mask = BIT(power_domain);
9995 pipe_config->shared_dpll = NULL;
9997 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9999 if (IS_BROXTON(dev_priv)) {
10000 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10001 &power_domain_mask);
10002 WARN_ON(active && pipe_config->has_dsi_encoder);
10003 if (pipe_config->has_dsi_encoder)
10010 if (!pipe_config->has_dsi_encoder) {
10011 haswell_get_ddi_port_state(crtc, pipe_config);
10012 intel_get_pipe_timings(crtc, pipe_config);
10015 intel_get_pipe_src_size(crtc, pipe_config);
10017 pipe_config->gamma_mode =
10018 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10020 if (INTEL_INFO(dev)->gen >= 9) {
10021 skl_init_scalers(dev, crtc, pipe_config);
10024 if (INTEL_INFO(dev)->gen >= 9) {
10025 pipe_config->scaler_state.scaler_id = -1;
10026 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10029 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10030 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10031 power_domain_mask |= BIT(power_domain);
10032 if (INTEL_INFO(dev)->gen >= 9)
10033 skylake_get_pfit_config(crtc, pipe_config);
10035 ironlake_get_pfit_config(crtc, pipe_config);
10038 if (IS_HASWELL(dev))
10039 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10040 (I915_READ(IPS_CTL) & IPS_ENABLE);
10042 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10043 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10044 pipe_config->pixel_multiplier =
10045 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10047 pipe_config->pixel_multiplier = 1;
10051 for_each_power_domain(power_domain, power_domain_mask)
10052 intel_display_power_put(dev_priv, power_domain);
10057 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10058 const struct intel_plane_state *plane_state)
10060 struct drm_device *dev = crtc->dev;
10061 struct drm_i915_private *dev_priv = dev->dev_private;
10062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10063 uint32_t cntl = 0, size = 0;
10065 if (plane_state && plane_state->visible) {
10066 unsigned int width = plane_state->base.crtc_w;
10067 unsigned int height = plane_state->base.crtc_h;
10068 unsigned int stride = roundup_pow_of_two(width) * 4;
10072 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10083 cntl |= CURSOR_ENABLE |
10084 CURSOR_GAMMA_ENABLE |
10085 CURSOR_FORMAT_ARGB |
10086 CURSOR_STRIDE(stride);
10088 size = (height << 12) | width;
10091 if (intel_crtc->cursor_cntl != 0 &&
10092 (intel_crtc->cursor_base != base ||
10093 intel_crtc->cursor_size != size ||
10094 intel_crtc->cursor_cntl != cntl)) {
10095 /* On these chipsets we can only modify the base/size/stride
10096 * whilst the cursor is disabled.
10098 I915_WRITE(CURCNTR(PIPE_A), 0);
10099 POSTING_READ(CURCNTR(PIPE_A));
10100 intel_crtc->cursor_cntl = 0;
10103 if (intel_crtc->cursor_base != base) {
10104 I915_WRITE(CURBASE(PIPE_A), base);
10105 intel_crtc->cursor_base = base;
10108 if (intel_crtc->cursor_size != size) {
10109 I915_WRITE(CURSIZE, size);
10110 intel_crtc->cursor_size = size;
10113 if (intel_crtc->cursor_cntl != cntl) {
10114 I915_WRITE(CURCNTR(PIPE_A), cntl);
10115 POSTING_READ(CURCNTR(PIPE_A));
10116 intel_crtc->cursor_cntl = cntl;
10120 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10121 const struct intel_plane_state *plane_state)
10123 struct drm_device *dev = crtc->dev;
10124 struct drm_i915_private *dev_priv = dev->dev_private;
10125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10126 int pipe = intel_crtc->pipe;
10129 if (plane_state && plane_state->visible) {
10130 cntl = MCURSOR_GAMMA_ENABLE;
10131 switch (plane_state->base.crtc_w) {
10133 cntl |= CURSOR_MODE_64_ARGB_AX;
10136 cntl |= CURSOR_MODE_128_ARGB_AX;
10139 cntl |= CURSOR_MODE_256_ARGB_AX;
10142 MISSING_CASE(plane_state->base.crtc_w);
10145 cntl |= pipe << 28; /* Connect to correct pipe */
10148 cntl |= CURSOR_PIPE_CSC_ENABLE;
10150 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10151 cntl |= CURSOR_ROTATE_180;
10154 if (intel_crtc->cursor_cntl != cntl) {
10155 I915_WRITE(CURCNTR(pipe), cntl);
10156 POSTING_READ(CURCNTR(pipe));
10157 intel_crtc->cursor_cntl = cntl;
10160 /* and commit changes on next vblank */
10161 I915_WRITE(CURBASE(pipe), base);
10162 POSTING_READ(CURBASE(pipe));
10164 intel_crtc->cursor_base = base;
10167 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10168 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10169 const struct intel_plane_state *plane_state)
10171 struct drm_device *dev = crtc->dev;
10172 struct drm_i915_private *dev_priv = dev->dev_private;
10173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10174 int pipe = intel_crtc->pipe;
10175 u32 base = intel_crtc->cursor_addr;
10179 int x = plane_state->base.crtc_x;
10180 int y = plane_state->base.crtc_y;
10183 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10186 pos |= x << CURSOR_X_SHIFT;
10189 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10192 pos |= y << CURSOR_Y_SHIFT;
10194 /* ILK+ do this automagically */
10195 if (HAS_GMCH_DISPLAY(dev) &&
10196 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10197 base += (plane_state->base.crtc_h *
10198 plane_state->base.crtc_w - 1) * 4;
10202 I915_WRITE(CURPOS(pipe), pos);
10204 if (IS_845G(dev) || IS_I865G(dev))
10205 i845_update_cursor(crtc, base, plane_state);
10207 i9xx_update_cursor(crtc, base, plane_state);
10210 static bool cursor_size_ok(struct drm_device *dev,
10211 uint32_t width, uint32_t height)
10213 if (width == 0 || height == 0)
10217 * 845g/865g are special in that they are only limited by
10218 * the width of their cursors, the height is arbitrary up to
10219 * the precision of the register. Everything else requires
10220 * square cursors, limited to a few power-of-two sizes.
10222 if (IS_845G(dev) || IS_I865G(dev)) {
10223 if ((width & 63) != 0)
10226 if (width > (IS_845G(dev) ? 64 : 512))
10232 switch (width | height) {
10247 /* VESA 640x480x72Hz mode to set on the pipe */
10248 static struct drm_display_mode load_detect_mode = {
10249 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10250 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10253 struct drm_framebuffer *
10254 __intel_framebuffer_create(struct drm_device *dev,
10255 struct drm_mode_fb_cmd2 *mode_cmd,
10256 struct drm_i915_gem_object *obj)
10258 struct intel_framebuffer *intel_fb;
10261 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10263 return ERR_PTR(-ENOMEM);
10265 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10269 return &intel_fb->base;
10273 return ERR_PTR(ret);
10276 static struct drm_framebuffer *
10277 intel_framebuffer_create(struct drm_device *dev,
10278 struct drm_mode_fb_cmd2 *mode_cmd,
10279 struct drm_i915_gem_object *obj)
10281 struct drm_framebuffer *fb;
10284 ret = i915_mutex_lock_interruptible(dev);
10286 return ERR_PTR(ret);
10287 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10288 mutex_unlock(&dev->struct_mutex);
10294 intel_framebuffer_pitch_for_width(int width, int bpp)
10296 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10297 return ALIGN(pitch, 64);
10301 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10303 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10304 return PAGE_ALIGN(pitch * mode->vdisplay);
10307 static struct drm_framebuffer *
10308 intel_framebuffer_create_for_mode(struct drm_device *dev,
10309 struct drm_display_mode *mode,
10310 int depth, int bpp)
10312 struct drm_framebuffer *fb;
10313 struct drm_i915_gem_object *obj;
10314 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10316 obj = i915_gem_object_create(dev,
10317 intel_framebuffer_size_for_mode(mode, bpp));
10319 return ERR_CAST(obj);
10321 mode_cmd.width = mode->hdisplay;
10322 mode_cmd.height = mode->vdisplay;
10323 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10325 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10327 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10329 drm_gem_object_unreference_unlocked(&obj->base);
10334 static struct drm_framebuffer *
10335 mode_fits_in_fbdev(struct drm_device *dev,
10336 struct drm_display_mode *mode)
10338 #ifdef CONFIG_DRM_FBDEV_EMULATION
10339 struct drm_i915_private *dev_priv = dev->dev_private;
10340 struct drm_i915_gem_object *obj;
10341 struct drm_framebuffer *fb;
10343 if (!dev_priv->fbdev)
10346 if (!dev_priv->fbdev->fb)
10349 obj = dev_priv->fbdev->fb->obj;
10352 fb = &dev_priv->fbdev->fb->base;
10353 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10354 fb->bits_per_pixel))
10357 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10360 drm_framebuffer_reference(fb);
10367 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10368 struct drm_crtc *crtc,
10369 struct drm_display_mode *mode,
10370 struct drm_framebuffer *fb,
10373 struct drm_plane_state *plane_state;
10374 int hdisplay, vdisplay;
10377 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10378 if (IS_ERR(plane_state))
10379 return PTR_ERR(plane_state);
10382 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10384 hdisplay = vdisplay = 0;
10386 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10389 drm_atomic_set_fb_for_plane(plane_state, fb);
10390 plane_state->crtc_x = 0;
10391 plane_state->crtc_y = 0;
10392 plane_state->crtc_w = hdisplay;
10393 plane_state->crtc_h = vdisplay;
10394 plane_state->src_x = x << 16;
10395 plane_state->src_y = y << 16;
10396 plane_state->src_w = hdisplay << 16;
10397 plane_state->src_h = vdisplay << 16;
10402 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10403 struct drm_display_mode *mode,
10404 struct intel_load_detect_pipe *old,
10405 struct drm_modeset_acquire_ctx *ctx)
10407 struct intel_crtc *intel_crtc;
10408 struct intel_encoder *intel_encoder =
10409 intel_attached_encoder(connector);
10410 struct drm_crtc *possible_crtc;
10411 struct drm_encoder *encoder = &intel_encoder->base;
10412 struct drm_crtc *crtc = NULL;
10413 struct drm_device *dev = encoder->dev;
10414 struct drm_framebuffer *fb;
10415 struct drm_mode_config *config = &dev->mode_config;
10416 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10417 struct drm_connector_state *connector_state;
10418 struct intel_crtc_state *crtc_state;
10421 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10422 connector->base.id, connector->name,
10423 encoder->base.id, encoder->name);
10425 old->restore_state = NULL;
10428 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10433 * Algorithm gets a little messy:
10435 * - if the connector already has an assigned crtc, use it (but make
10436 * sure it's on first)
10438 * - try to find the first unused crtc that can drive this connector,
10439 * and use that if we find one
10442 /* See if we already have a CRTC for this connector */
10443 if (connector->state->crtc) {
10444 crtc = connector->state->crtc;
10446 ret = drm_modeset_lock(&crtc->mutex, ctx);
10450 /* Make sure the crtc and connector are running */
10454 /* Find an unused one (if possible) */
10455 for_each_crtc(dev, possible_crtc) {
10457 if (!(encoder->possible_crtcs & (1 << i)))
10460 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10464 if (possible_crtc->state->enable) {
10465 drm_modeset_unlock(&possible_crtc->mutex);
10469 crtc = possible_crtc;
10474 * If we didn't find an unused CRTC, don't use any.
10477 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10482 intel_crtc = to_intel_crtc(crtc);
10484 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10488 state = drm_atomic_state_alloc(dev);
10489 restore_state = drm_atomic_state_alloc(dev);
10490 if (!state || !restore_state) {
10495 state->acquire_ctx = ctx;
10496 restore_state->acquire_ctx = ctx;
10498 connector_state = drm_atomic_get_connector_state(state, connector);
10499 if (IS_ERR(connector_state)) {
10500 ret = PTR_ERR(connector_state);
10504 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10508 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10509 if (IS_ERR(crtc_state)) {
10510 ret = PTR_ERR(crtc_state);
10514 crtc_state->base.active = crtc_state->base.enable = true;
10517 mode = &load_detect_mode;
10519 /* We need a framebuffer large enough to accommodate all accesses
10520 * that the plane may generate whilst we perform load detection.
10521 * We can not rely on the fbcon either being present (we get called
10522 * during its initialisation to detect all boot displays, or it may
10523 * not even exist) or that it is large enough to satisfy the
10526 fb = mode_fits_in_fbdev(dev, mode);
10528 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10529 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10531 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10533 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10537 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10541 drm_framebuffer_unreference(fb);
10543 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10547 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10549 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10551 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10553 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10557 ret = drm_atomic_commit(state);
10559 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10563 old->restore_state = restore_state;
10565 /* let the connector get through one full cycle before testing */
10566 intel_wait_for_vblank(dev, intel_crtc->pipe);
10570 drm_atomic_state_free(state);
10571 drm_atomic_state_free(restore_state);
10572 restore_state = state = NULL;
10574 if (ret == -EDEADLK) {
10575 drm_modeset_backoff(ctx);
10582 void intel_release_load_detect_pipe(struct drm_connector *connector,
10583 struct intel_load_detect_pipe *old,
10584 struct drm_modeset_acquire_ctx *ctx)
10586 struct intel_encoder *intel_encoder =
10587 intel_attached_encoder(connector);
10588 struct drm_encoder *encoder = &intel_encoder->base;
10589 struct drm_atomic_state *state = old->restore_state;
10592 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10593 connector->base.id, connector->name,
10594 encoder->base.id, encoder->name);
10599 ret = drm_atomic_commit(state);
10601 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10602 drm_atomic_state_free(state);
10606 static int i9xx_pll_refclk(struct drm_device *dev,
10607 const struct intel_crtc_state *pipe_config)
10609 struct drm_i915_private *dev_priv = dev->dev_private;
10610 u32 dpll = pipe_config->dpll_hw_state.dpll;
10612 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10613 return dev_priv->vbt.lvds_ssc_freq;
10614 else if (HAS_PCH_SPLIT(dev))
10616 else if (!IS_GEN2(dev))
10622 /* Returns the clock of the currently programmed mode of the given pipe. */
10623 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10624 struct intel_crtc_state *pipe_config)
10626 struct drm_device *dev = crtc->base.dev;
10627 struct drm_i915_private *dev_priv = dev->dev_private;
10628 int pipe = pipe_config->cpu_transcoder;
10629 u32 dpll = pipe_config->dpll_hw_state.dpll;
10631 intel_clock_t clock;
10633 int refclk = i9xx_pll_refclk(dev, pipe_config);
10635 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10636 fp = pipe_config->dpll_hw_state.fp0;
10638 fp = pipe_config->dpll_hw_state.fp1;
10640 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10641 if (IS_PINEVIEW(dev)) {
10642 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10643 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10645 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10646 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10649 if (!IS_GEN2(dev)) {
10650 if (IS_PINEVIEW(dev))
10651 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10652 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10654 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10655 DPLL_FPA01_P1_POST_DIV_SHIFT);
10657 switch (dpll & DPLL_MODE_MASK) {
10658 case DPLLB_MODE_DAC_SERIAL:
10659 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10662 case DPLLB_MODE_LVDS:
10663 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10667 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10668 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10672 if (IS_PINEVIEW(dev))
10673 port_clock = pnv_calc_dpll_params(refclk, &clock);
10675 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10677 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10678 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10681 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10682 DPLL_FPA01_P1_POST_DIV_SHIFT);
10684 if (lvds & LVDS_CLKB_POWER_UP)
10689 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10692 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10693 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10695 if (dpll & PLL_P2_DIVIDE_BY_4)
10701 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10705 * This value includes pixel_multiplier. We will use
10706 * port_clock to compute adjusted_mode.crtc_clock in the
10707 * encoder's get_config() function.
10709 pipe_config->port_clock = port_clock;
10712 int intel_dotclock_calculate(int link_freq,
10713 const struct intel_link_m_n *m_n)
10716 * The calculation for the data clock is:
10717 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10718 * But we want to avoid losing precison if possible, so:
10719 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10721 * and the link clock is simpler:
10722 * link_clock = (m * link_clock) / n
10728 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10731 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10732 struct intel_crtc_state *pipe_config)
10734 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10736 /* read out port_clock from the DPLL */
10737 i9xx_crtc_clock_get(crtc, pipe_config);
10740 * In case there is an active pipe without active ports,
10741 * we may need some idea for the dotclock anyway.
10742 * Calculate one based on the FDI configuration.
10744 pipe_config->base.adjusted_mode.crtc_clock =
10745 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10746 &pipe_config->fdi_m_n);
10749 /** Returns the currently programmed mode of the given pipe. */
10750 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10751 struct drm_crtc *crtc)
10753 struct drm_i915_private *dev_priv = dev->dev_private;
10754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10755 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10756 struct drm_display_mode *mode;
10757 struct intel_crtc_state *pipe_config;
10758 int htot = I915_READ(HTOTAL(cpu_transcoder));
10759 int hsync = I915_READ(HSYNC(cpu_transcoder));
10760 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10761 int vsync = I915_READ(VSYNC(cpu_transcoder));
10762 enum pipe pipe = intel_crtc->pipe;
10764 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10768 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10769 if (!pipe_config) {
10775 * Construct a pipe_config sufficient for getting the clock info
10776 * back out of crtc_clock_get.
10778 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10779 * to use a real value here instead.
10781 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10782 pipe_config->pixel_multiplier = 1;
10783 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10784 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10785 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10786 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10788 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10789 mode->hdisplay = (htot & 0xffff) + 1;
10790 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10791 mode->hsync_start = (hsync & 0xffff) + 1;
10792 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10793 mode->vdisplay = (vtot & 0xffff) + 1;
10794 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10795 mode->vsync_start = (vsync & 0xffff) + 1;
10796 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10798 drm_mode_set_name(mode);
10800 kfree(pipe_config);
10805 void intel_mark_busy(struct drm_i915_private *dev_priv)
10807 if (dev_priv->mm.busy)
10810 intel_runtime_pm_get(dev_priv);
10811 i915_update_gfx_val(dev_priv);
10812 if (INTEL_GEN(dev_priv) >= 6)
10813 gen6_rps_busy(dev_priv);
10814 dev_priv->mm.busy = true;
10817 void intel_mark_idle(struct drm_i915_private *dev_priv)
10819 if (!dev_priv->mm.busy)
10822 dev_priv->mm.busy = false;
10824 if (INTEL_GEN(dev_priv) >= 6)
10825 gen6_rps_idle(dev_priv);
10827 intel_runtime_pm_put(dev_priv);
10830 static void intel_crtc_destroy(struct drm_crtc *crtc)
10832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10833 struct drm_device *dev = crtc->dev;
10834 struct intel_unpin_work *work;
10836 spin_lock_irq(&dev->event_lock);
10837 work = intel_crtc->unpin_work;
10838 intel_crtc->unpin_work = NULL;
10839 spin_unlock_irq(&dev->event_lock);
10842 cancel_work_sync(&work->work);
10846 drm_crtc_cleanup(crtc);
10851 static void intel_unpin_work_fn(struct work_struct *__work)
10853 struct intel_unpin_work *work =
10854 container_of(__work, struct intel_unpin_work, work);
10855 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10856 struct drm_device *dev = crtc->base.dev;
10857 struct drm_plane *primary = crtc->base.primary;
10859 mutex_lock(&dev->struct_mutex);
10860 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10861 drm_gem_object_unreference(&work->pending_flip_obj->base);
10863 if (work->flip_queued_req)
10864 i915_gem_request_assign(&work->flip_queued_req, NULL);
10865 mutex_unlock(&dev->struct_mutex);
10867 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10868 intel_fbc_post_update(crtc);
10869 drm_framebuffer_unreference(work->old_fb);
10871 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10872 atomic_dec(&crtc->unpin_work_count);
10877 static void do_intel_finish_page_flip(struct drm_device *dev,
10878 struct drm_crtc *crtc)
10880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10881 struct intel_unpin_work *work;
10882 unsigned long flags;
10884 /* Ignore early vblank irqs */
10885 if (intel_crtc == NULL)
10889 * This is called both by irq handlers and the reset code (to complete
10890 * lost pageflips) so needs the full irqsave spinlocks.
10892 spin_lock_irqsave(&dev->event_lock, flags);
10893 work = intel_crtc->unpin_work;
10895 /* Ensure we don't miss a work->pending update ... */
10898 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10899 spin_unlock_irqrestore(&dev->event_lock, flags);
10903 page_flip_completed(intel_crtc);
10905 spin_unlock_irqrestore(&dev->event_lock, flags);
10908 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10910 struct drm_i915_private *dev_priv = dev->dev_private;
10911 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10913 do_intel_finish_page_flip(dev, crtc);
10916 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10918 struct drm_i915_private *dev_priv = dev->dev_private;
10919 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10921 do_intel_finish_page_flip(dev, crtc);
10924 /* Is 'a' after or equal to 'b'? */
10925 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10927 return !((a - b) & 0x80000000);
10930 static bool page_flip_finished(struct intel_crtc *crtc)
10932 struct drm_device *dev = crtc->base.dev;
10933 struct drm_i915_private *dev_priv = dev->dev_private;
10934 unsigned reset_counter;
10936 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10937 if (crtc->reset_counter != reset_counter)
10941 * The relevant registers doen't exist on pre-ctg.
10942 * As the flip done interrupt doesn't trigger for mmio
10943 * flips on gmch platforms, a flip count check isn't
10944 * really needed there. But since ctg has the registers,
10945 * include it in the check anyway.
10947 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10951 * BDW signals flip done immediately if the plane
10952 * is disabled, even if the plane enable is already
10953 * armed to occur at the next vblank :(
10957 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10958 * used the same base address. In that case the mmio flip might
10959 * have completed, but the CS hasn't even executed the flip yet.
10961 * A flip count check isn't enough as the CS might have updated
10962 * the base address just after start of vblank, but before we
10963 * managed to process the interrupt. This means we'd complete the
10964 * CS flip too soon.
10966 * Combining both checks should get us a good enough result. It may
10967 * still happen that the CS flip has been executed, but has not
10968 * yet actually completed. But in case the base address is the same
10969 * anyway, we don't really care.
10971 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10972 crtc->unpin_work->gtt_offset &&
10973 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10974 crtc->unpin_work->flip_count);
10977 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10979 struct drm_i915_private *dev_priv = dev->dev_private;
10980 struct intel_crtc *intel_crtc =
10981 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10982 unsigned long flags;
10986 * This is called both by irq handlers and the reset code (to complete
10987 * lost pageflips) so needs the full irqsave spinlocks.
10989 * NB: An MMIO update of the plane base pointer will also
10990 * generate a page-flip completion irq, i.e. every modeset
10991 * is also accompanied by a spurious intel_prepare_page_flip().
10993 spin_lock_irqsave(&dev->event_lock, flags);
10994 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10995 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10996 spin_unlock_irqrestore(&dev->event_lock, flags);
10999 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11001 /* Ensure that the work item is consistent when activating it ... */
11003 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11004 /* and that it is marked active as soon as the irq could fire. */
11008 static int intel_gen2_queue_flip(struct drm_device *dev,
11009 struct drm_crtc *crtc,
11010 struct drm_framebuffer *fb,
11011 struct drm_i915_gem_object *obj,
11012 struct drm_i915_gem_request *req,
11015 struct intel_engine_cs *engine = req->engine;
11016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11020 ret = intel_ring_begin(req, 6);
11024 /* Can't queue multiple flips, so wait for the previous
11025 * one to finish before executing the next.
11027 if (intel_crtc->plane)
11028 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11030 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11031 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11032 intel_ring_emit(engine, MI_NOOP);
11033 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11034 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11035 intel_ring_emit(engine, fb->pitches[0]);
11036 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11037 intel_ring_emit(engine, 0); /* aux display base address, unused */
11039 intel_mark_page_flip_active(intel_crtc->unpin_work);
11043 static int intel_gen3_queue_flip(struct drm_device *dev,
11044 struct drm_crtc *crtc,
11045 struct drm_framebuffer *fb,
11046 struct drm_i915_gem_object *obj,
11047 struct drm_i915_gem_request *req,
11050 struct intel_engine_cs *engine = req->engine;
11051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11055 ret = intel_ring_begin(req, 6);
11059 if (intel_crtc->plane)
11060 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11062 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11063 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11064 intel_ring_emit(engine, MI_NOOP);
11065 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11066 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11067 intel_ring_emit(engine, fb->pitches[0]);
11068 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11069 intel_ring_emit(engine, MI_NOOP);
11071 intel_mark_page_flip_active(intel_crtc->unpin_work);
11075 static int intel_gen4_queue_flip(struct drm_device *dev,
11076 struct drm_crtc *crtc,
11077 struct drm_framebuffer *fb,
11078 struct drm_i915_gem_object *obj,
11079 struct drm_i915_gem_request *req,
11082 struct intel_engine_cs *engine = req->engine;
11083 struct drm_i915_private *dev_priv = dev->dev_private;
11084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11085 uint32_t pf, pipesrc;
11088 ret = intel_ring_begin(req, 4);
11092 /* i965+ uses the linear or tiled offsets from the
11093 * Display Registers (which do not change across a page-flip)
11094 * so we need only reprogram the base address.
11096 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11097 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11098 intel_ring_emit(engine, fb->pitches[0]);
11099 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11102 /* XXX Enabling the panel-fitter across page-flip is so far
11103 * untested on non-native modes, so ignore it for now.
11104 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11107 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11108 intel_ring_emit(engine, pf | pipesrc);
11110 intel_mark_page_flip_active(intel_crtc->unpin_work);
11114 static int intel_gen6_queue_flip(struct drm_device *dev,
11115 struct drm_crtc *crtc,
11116 struct drm_framebuffer *fb,
11117 struct drm_i915_gem_object *obj,
11118 struct drm_i915_gem_request *req,
11121 struct intel_engine_cs *engine = req->engine;
11122 struct drm_i915_private *dev_priv = dev->dev_private;
11123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11124 uint32_t pf, pipesrc;
11127 ret = intel_ring_begin(req, 4);
11131 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11132 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11133 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11134 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11136 /* Contrary to the suggestions in the documentation,
11137 * "Enable Panel Fitter" does not seem to be required when page
11138 * flipping with a non-native mode, and worse causes a normal
11140 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11143 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11144 intel_ring_emit(engine, pf | pipesrc);
11146 intel_mark_page_flip_active(intel_crtc->unpin_work);
11150 static int intel_gen7_queue_flip(struct drm_device *dev,
11151 struct drm_crtc *crtc,
11152 struct drm_framebuffer *fb,
11153 struct drm_i915_gem_object *obj,
11154 struct drm_i915_gem_request *req,
11157 struct intel_engine_cs *engine = req->engine;
11158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11159 uint32_t plane_bit = 0;
11162 switch (intel_crtc->plane) {
11164 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11167 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11173 WARN_ONCE(1, "unknown plane in flip command\n");
11178 if (engine->id == RCS) {
11181 * On Gen 8, SRM is now taking an extra dword to accommodate
11182 * 48bits addresses, and we need a NOOP for the batch size to
11190 * BSpec MI_DISPLAY_FLIP for IVB:
11191 * "The full packet must be contained within the same cache line."
11193 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11194 * cacheline, if we ever start emitting more commands before
11195 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11196 * then do the cacheline alignment, and finally emit the
11199 ret = intel_ring_cacheline_align(req);
11203 ret = intel_ring_begin(req, len);
11207 /* Unmask the flip-done completion message. Note that the bspec says that
11208 * we should do this for both the BCS and RCS, and that we must not unmask
11209 * more than one flip event at any time (or ensure that one flip message
11210 * can be sent by waiting for flip-done prior to queueing new flips).
11211 * Experimentation says that BCS works despite DERRMR masking all
11212 * flip-done completion events and that unmasking all planes at once
11213 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11214 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11216 if (engine->id == RCS) {
11217 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11218 intel_ring_emit_reg(engine, DERRMR);
11219 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11220 DERRMR_PIPEB_PRI_FLIP_DONE |
11221 DERRMR_PIPEC_PRI_FLIP_DONE));
11223 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11224 MI_SRM_LRM_GLOBAL_GTT);
11226 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11227 MI_SRM_LRM_GLOBAL_GTT);
11228 intel_ring_emit_reg(engine, DERRMR);
11229 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11230 if (IS_GEN8(dev)) {
11231 intel_ring_emit(engine, 0);
11232 intel_ring_emit(engine, MI_NOOP);
11236 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11237 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11238 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11239 intel_ring_emit(engine, (MI_NOOP));
11241 intel_mark_page_flip_active(intel_crtc->unpin_work);
11245 static bool use_mmio_flip(struct intel_engine_cs *engine,
11246 struct drm_i915_gem_object *obj)
11249 * This is not being used for older platforms, because
11250 * non-availability of flip done interrupt forces us to use
11251 * CS flips. Older platforms derive flip done using some clever
11252 * tricks involving the flip_pending status bits and vblank irqs.
11253 * So using MMIO flips there would disrupt this mechanism.
11256 if (engine == NULL)
11259 if (INTEL_INFO(engine->dev)->gen < 5)
11262 if (i915.use_mmio_flip < 0)
11264 else if (i915.use_mmio_flip > 0)
11266 else if (i915.enable_execlists)
11268 else if (obj->base.dma_buf &&
11269 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11273 return engine != i915_gem_request_get_engine(obj->last_write_req);
11276 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11277 unsigned int rotation,
11278 struct intel_unpin_work *work)
11280 struct drm_device *dev = intel_crtc->base.dev;
11281 struct drm_i915_private *dev_priv = dev->dev_private;
11282 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11283 const enum pipe pipe = intel_crtc->pipe;
11284 u32 ctl, stride, tile_height;
11286 ctl = I915_READ(PLANE_CTL(pipe, 0));
11287 ctl &= ~PLANE_CTL_TILED_MASK;
11288 switch (fb->modifier[0]) {
11289 case DRM_FORMAT_MOD_NONE:
11291 case I915_FORMAT_MOD_X_TILED:
11292 ctl |= PLANE_CTL_TILED_X;
11294 case I915_FORMAT_MOD_Y_TILED:
11295 ctl |= PLANE_CTL_TILED_Y;
11297 case I915_FORMAT_MOD_Yf_TILED:
11298 ctl |= PLANE_CTL_TILED_YF;
11301 MISSING_CASE(fb->modifier[0]);
11305 * The stride is either expressed as a multiple of 64 bytes chunks for
11306 * linear buffers or in number of tiles for tiled buffers.
11308 if (intel_rotation_90_or_270(rotation)) {
11309 /* stride = Surface height in tiles */
11310 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11311 stride = DIV_ROUND_UP(fb->height, tile_height);
11313 stride = fb->pitches[0] /
11314 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11319 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11320 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11322 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11323 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11325 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11326 POSTING_READ(PLANE_SURF(pipe, 0));
11329 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11330 struct intel_unpin_work *work)
11332 struct drm_device *dev = intel_crtc->base.dev;
11333 struct drm_i915_private *dev_priv = dev->dev_private;
11334 struct intel_framebuffer *intel_fb =
11335 to_intel_framebuffer(intel_crtc->base.primary->fb);
11336 struct drm_i915_gem_object *obj = intel_fb->obj;
11337 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11340 dspcntr = I915_READ(reg);
11342 if (obj->tiling_mode != I915_TILING_NONE)
11343 dspcntr |= DISPPLANE_TILED;
11345 dspcntr &= ~DISPPLANE_TILED;
11347 I915_WRITE(reg, dspcntr);
11349 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11350 POSTING_READ(DSPSURF(intel_crtc->plane));
11354 * XXX: This is the temporary way to update the plane registers until we get
11355 * around to using the usual plane update functions for MMIO flips
11357 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11359 struct intel_crtc *crtc = mmio_flip->crtc;
11360 struct intel_unpin_work *work;
11362 spin_lock_irq(&crtc->base.dev->event_lock);
11363 work = crtc->unpin_work;
11364 spin_unlock_irq(&crtc->base.dev->event_lock);
11368 intel_mark_page_flip_active(work);
11370 intel_pipe_update_start(crtc);
11372 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11373 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11375 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11376 ilk_do_mmio_flip(crtc, work);
11378 intel_pipe_update_end(crtc);
11381 static void intel_mmio_flip_work_func(struct work_struct *work)
11383 struct intel_mmio_flip *mmio_flip =
11384 container_of(work, struct intel_mmio_flip, work);
11385 struct intel_framebuffer *intel_fb =
11386 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11387 struct drm_i915_gem_object *obj = intel_fb->obj;
11389 if (mmio_flip->req) {
11390 WARN_ON(__i915_wait_request(mmio_flip->req,
11392 &mmio_flip->i915->rps.mmioflips));
11393 i915_gem_request_unreference(mmio_flip->req);
11396 /* For framebuffer backed by dmabuf, wait for fence */
11397 if (obj->base.dma_buf)
11398 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11400 MAX_SCHEDULE_TIMEOUT) < 0);
11402 intel_do_mmio_flip(mmio_flip);
11406 static int intel_queue_mmio_flip(struct drm_device *dev,
11407 struct drm_crtc *crtc,
11408 struct drm_i915_gem_object *obj)
11410 struct intel_mmio_flip *mmio_flip;
11412 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11413 if (mmio_flip == NULL)
11416 mmio_flip->i915 = to_i915(dev);
11417 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11418 mmio_flip->crtc = to_intel_crtc(crtc);
11419 mmio_flip->rotation = crtc->primary->state->rotation;
11421 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11422 schedule_work(&mmio_flip->work);
11427 static int intel_default_queue_flip(struct drm_device *dev,
11428 struct drm_crtc *crtc,
11429 struct drm_framebuffer *fb,
11430 struct drm_i915_gem_object *obj,
11431 struct drm_i915_gem_request *req,
11437 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11438 struct drm_crtc *crtc)
11440 struct drm_i915_private *dev_priv = dev->dev_private;
11441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11442 struct intel_unpin_work *work = intel_crtc->unpin_work;
11445 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11448 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11451 if (!work->enable_stall_check)
11454 if (work->flip_ready_vblank == 0) {
11455 if (work->flip_queued_req &&
11456 !i915_gem_request_completed(work->flip_queued_req, true))
11459 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11462 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11465 /* Potential stall - if we see that the flip has happened,
11466 * assume a missed interrupt. */
11467 if (INTEL_INFO(dev)->gen >= 4)
11468 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11470 addr = I915_READ(DSPADDR(intel_crtc->plane));
11472 /* There is a potential issue here with a false positive after a flip
11473 * to the same address. We could address this by checking for a
11474 * non-incrementing frame counter.
11476 return addr == work->gtt_offset;
11479 void intel_check_page_flip(struct drm_device *dev, int pipe)
11481 struct drm_i915_private *dev_priv = dev->dev_private;
11482 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11484 struct intel_unpin_work *work;
11486 WARN_ON(!in_interrupt());
11491 spin_lock(&dev->event_lock);
11492 work = intel_crtc->unpin_work;
11493 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11494 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11495 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11496 page_flip_completed(intel_crtc);
11499 if (work != NULL &&
11500 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11501 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11502 spin_unlock(&dev->event_lock);
11505 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11506 struct drm_framebuffer *fb,
11507 struct drm_pending_vblank_event *event,
11508 uint32_t page_flip_flags)
11510 struct drm_device *dev = crtc->dev;
11511 struct drm_i915_private *dev_priv = dev->dev_private;
11512 struct drm_framebuffer *old_fb = crtc->primary->fb;
11513 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11515 struct drm_plane *primary = crtc->primary;
11516 enum pipe pipe = intel_crtc->pipe;
11517 struct intel_unpin_work *work;
11518 struct intel_engine_cs *engine;
11520 struct drm_i915_gem_request *request = NULL;
11524 * drm_mode_page_flip_ioctl() should already catch this, but double
11525 * check to be safe. In the future we may enable pageflipping from
11526 * a disabled primary plane.
11528 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11531 /* Can't change pixel format via MI display flips. */
11532 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11536 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11537 * Note that pitch changes could also affect these register.
11539 if (INTEL_INFO(dev)->gen > 3 &&
11540 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11541 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11544 if (i915_terminally_wedged(&dev_priv->gpu_error))
11547 work = kzalloc(sizeof(*work), GFP_KERNEL);
11551 work->event = event;
11553 work->old_fb = old_fb;
11554 INIT_WORK(&work->work, intel_unpin_work_fn);
11556 ret = drm_crtc_vblank_get(crtc);
11560 /* We borrow the event spin lock for protecting unpin_work */
11561 spin_lock_irq(&dev->event_lock);
11562 if (intel_crtc->unpin_work) {
11563 /* Before declaring the flip queue wedged, check if
11564 * the hardware completed the operation behind our backs.
11566 if (__intel_pageflip_stall_check(dev, crtc)) {
11567 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11568 page_flip_completed(intel_crtc);
11570 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11571 spin_unlock_irq(&dev->event_lock);
11573 drm_crtc_vblank_put(crtc);
11578 intel_crtc->unpin_work = work;
11579 spin_unlock_irq(&dev->event_lock);
11581 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11582 flush_workqueue(dev_priv->wq);
11584 /* Reference the objects for the scheduled work. */
11585 drm_framebuffer_reference(work->old_fb);
11586 drm_gem_object_reference(&obj->base);
11588 crtc->primary->fb = fb;
11589 update_state_fb(crtc->primary);
11590 intel_fbc_pre_update(intel_crtc);
11592 work->pending_flip_obj = obj;
11594 ret = i915_mutex_lock_interruptible(dev);
11598 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11599 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11604 atomic_inc(&intel_crtc->unpin_work_count);
11606 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11607 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11609 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11610 engine = &dev_priv->engine[BCS];
11611 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11612 /* vlv: DISPLAY_FLIP fails to change tiling */
11614 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11615 engine = &dev_priv->engine[BCS];
11616 } else if (INTEL_INFO(dev)->gen >= 7) {
11617 engine = i915_gem_request_get_engine(obj->last_write_req);
11618 if (engine == NULL || engine->id != RCS)
11619 engine = &dev_priv->engine[BCS];
11621 engine = &dev_priv->engine[RCS];
11624 mmio_flip = use_mmio_flip(engine, obj);
11626 /* When using CS flips, we want to emit semaphores between rings.
11627 * However, when using mmio flips we will create a task to do the
11628 * synchronisation, so all we want here is to pin the framebuffer
11629 * into the display plane and skip any waits.
11632 ret = i915_gem_object_sync(obj, engine, &request);
11634 goto cleanup_pending;
11637 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11639 goto cleanup_pending;
11641 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11643 work->gtt_offset += intel_crtc->dspaddr_offset;
11646 ret = intel_queue_mmio_flip(dev, crtc, obj);
11648 goto cleanup_unpin;
11650 i915_gem_request_assign(&work->flip_queued_req,
11651 obj->last_write_req);
11654 request = i915_gem_request_alloc(engine, NULL);
11655 if (IS_ERR(request)) {
11656 ret = PTR_ERR(request);
11657 goto cleanup_unpin;
11661 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11664 goto cleanup_unpin;
11666 i915_gem_request_assign(&work->flip_queued_req, request);
11670 i915_add_request_no_flush(request);
11672 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11673 work->enable_stall_check = true;
11675 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11676 to_intel_plane(primary)->frontbuffer_bit);
11677 mutex_unlock(&dev->struct_mutex);
11679 intel_frontbuffer_flip_prepare(dev,
11680 to_intel_plane(primary)->frontbuffer_bit);
11682 trace_i915_flip_request(intel_crtc->plane, obj);
11687 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11689 if (!IS_ERR_OR_NULL(request))
11690 i915_add_request_no_flush(request);
11691 atomic_dec(&intel_crtc->unpin_work_count);
11692 mutex_unlock(&dev->struct_mutex);
11694 crtc->primary->fb = old_fb;
11695 update_state_fb(crtc->primary);
11697 drm_gem_object_unreference_unlocked(&obj->base);
11698 drm_framebuffer_unreference(work->old_fb);
11700 spin_lock_irq(&dev->event_lock);
11701 intel_crtc->unpin_work = NULL;
11702 spin_unlock_irq(&dev->event_lock);
11704 drm_crtc_vblank_put(crtc);
11709 struct drm_atomic_state *state;
11710 struct drm_plane_state *plane_state;
11713 state = drm_atomic_state_alloc(dev);
11716 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11719 plane_state = drm_atomic_get_plane_state(state, primary);
11720 ret = PTR_ERR_OR_ZERO(plane_state);
11722 drm_atomic_set_fb_for_plane(plane_state, fb);
11724 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11726 ret = drm_atomic_commit(state);
11729 if (ret == -EDEADLK) {
11730 drm_modeset_backoff(state->acquire_ctx);
11731 drm_atomic_state_clear(state);
11736 drm_atomic_state_free(state);
11738 if (ret == 0 && event) {
11739 spin_lock_irq(&dev->event_lock);
11740 drm_crtc_send_vblank_event(crtc, event);
11741 spin_unlock_irq(&dev->event_lock);
11749 * intel_wm_need_update - Check whether watermarks need updating
11750 * @plane: drm plane
11751 * @state: new plane state
11753 * Check current plane state versus the new one to determine whether
11754 * watermarks need to be recalculated.
11756 * Returns true or false.
11758 static bool intel_wm_need_update(struct drm_plane *plane,
11759 struct drm_plane_state *state)
11761 struct intel_plane_state *new = to_intel_plane_state(state);
11762 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11764 /* Update watermarks on tiling or size changes. */
11765 if (new->visible != cur->visible)
11768 if (!cur->base.fb || !new->base.fb)
11771 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11772 cur->base.rotation != new->base.rotation ||
11773 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11774 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11775 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11776 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11782 static bool needs_scaling(struct intel_plane_state *state)
11784 int src_w = drm_rect_width(&state->src) >> 16;
11785 int src_h = drm_rect_height(&state->src) >> 16;
11786 int dst_w = drm_rect_width(&state->dst);
11787 int dst_h = drm_rect_height(&state->dst);
11789 return (src_w != dst_w || src_h != dst_h);
11792 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11793 struct drm_plane_state *plane_state)
11795 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11796 struct drm_crtc *crtc = crtc_state->crtc;
11797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11798 struct drm_plane *plane = plane_state->plane;
11799 struct drm_device *dev = crtc->dev;
11800 struct drm_i915_private *dev_priv = to_i915(dev);
11801 struct intel_plane_state *old_plane_state =
11802 to_intel_plane_state(plane->state);
11803 int idx = intel_crtc->base.base.id, ret;
11804 bool mode_changed = needs_modeset(crtc_state);
11805 bool was_crtc_enabled = crtc->state->active;
11806 bool is_crtc_enabled = crtc_state->active;
11807 bool turn_off, turn_on, visible, was_visible;
11808 struct drm_framebuffer *fb = plane_state->fb;
11810 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11811 plane->type != DRM_PLANE_TYPE_CURSOR) {
11812 ret = skl_update_scaler_plane(
11813 to_intel_crtc_state(crtc_state),
11814 to_intel_plane_state(plane_state));
11819 was_visible = old_plane_state->visible;
11820 visible = to_intel_plane_state(plane_state)->visible;
11822 if (!was_crtc_enabled && WARN_ON(was_visible))
11823 was_visible = false;
11826 * Visibility is calculated as if the crtc was on, but
11827 * after scaler setup everything depends on it being off
11828 * when the crtc isn't active.
11830 if (!is_crtc_enabled)
11831 to_intel_plane_state(plane_state)->visible = visible = false;
11833 if (!was_visible && !visible)
11836 if (fb != old_plane_state->base.fb)
11837 pipe_config->fb_changed = true;
11839 turn_off = was_visible && (!visible || mode_changed);
11840 turn_on = visible && (!was_visible || mode_changed);
11842 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11843 plane->base.id, fb ? fb->base.id : -1);
11845 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11846 plane->base.id, was_visible, visible,
11847 turn_off, turn_on, mode_changed);
11850 pipe_config->update_wm_pre = true;
11852 /* must disable cxsr around plane enable/disable */
11853 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11854 pipe_config->disable_cxsr = true;
11855 } else if (turn_off) {
11856 pipe_config->update_wm_post = true;
11858 /* must disable cxsr around plane enable/disable */
11859 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11860 pipe_config->disable_cxsr = true;
11861 } else if (intel_wm_need_update(plane, plane_state)) {
11862 /* FIXME bollocks */
11863 pipe_config->update_wm_pre = true;
11864 pipe_config->update_wm_post = true;
11867 /* Pre-gen9 platforms need two-step watermark updates */
11868 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11869 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11870 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11872 if (visible || was_visible)
11873 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11876 * WaCxSRDisabledForSpriteScaling:ivb
11878 * cstate->update_wm was already set above, so this flag will
11879 * take effect when we commit and program watermarks.
11881 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11882 needs_scaling(to_intel_plane_state(plane_state)) &&
11883 !needs_scaling(old_plane_state))
11884 pipe_config->disable_lp_wm = true;
11889 static bool encoders_cloneable(const struct intel_encoder *a,
11890 const struct intel_encoder *b)
11892 /* masks could be asymmetric, so check both ways */
11893 return a == b || (a->cloneable & (1 << b->type) &&
11894 b->cloneable & (1 << a->type));
11897 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11898 struct intel_crtc *crtc,
11899 struct intel_encoder *encoder)
11901 struct intel_encoder *source_encoder;
11902 struct drm_connector *connector;
11903 struct drm_connector_state *connector_state;
11906 for_each_connector_in_state(state, connector, connector_state, i) {
11907 if (connector_state->crtc != &crtc->base)
11911 to_intel_encoder(connector_state->best_encoder);
11912 if (!encoders_cloneable(encoder, source_encoder))
11919 static bool check_encoder_cloning(struct drm_atomic_state *state,
11920 struct intel_crtc *crtc)
11922 struct intel_encoder *encoder;
11923 struct drm_connector *connector;
11924 struct drm_connector_state *connector_state;
11927 for_each_connector_in_state(state, connector, connector_state, i) {
11928 if (connector_state->crtc != &crtc->base)
11931 encoder = to_intel_encoder(connector_state->best_encoder);
11932 if (!check_single_encoder_cloning(state, crtc, encoder))
11939 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11940 struct drm_crtc_state *crtc_state)
11942 struct drm_device *dev = crtc->dev;
11943 struct drm_i915_private *dev_priv = dev->dev_private;
11944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11945 struct intel_crtc_state *pipe_config =
11946 to_intel_crtc_state(crtc_state);
11947 struct drm_atomic_state *state = crtc_state->state;
11949 bool mode_changed = needs_modeset(crtc_state);
11951 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11952 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11956 if (mode_changed && !crtc_state->active)
11957 pipe_config->update_wm_post = true;
11959 if (mode_changed && crtc_state->enable &&
11960 dev_priv->display.crtc_compute_clock &&
11961 !WARN_ON(pipe_config->shared_dpll)) {
11962 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11968 if (crtc_state->color_mgmt_changed) {
11969 ret = intel_color_check(crtc, crtc_state);
11975 if (dev_priv->display.compute_pipe_wm) {
11976 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11978 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11983 if (dev_priv->display.compute_intermediate_wm &&
11984 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11985 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11989 * Calculate 'intermediate' watermarks that satisfy both the
11990 * old state and the new state. We can program these
11993 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11997 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12002 if (INTEL_INFO(dev)->gen >= 9) {
12004 ret = skl_update_scaler_crtc(pipe_config);
12007 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12014 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12015 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12016 .atomic_begin = intel_begin_crtc_commit,
12017 .atomic_flush = intel_finish_crtc_commit,
12018 .atomic_check = intel_crtc_atomic_check,
12021 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12023 struct intel_connector *connector;
12025 for_each_intel_connector(dev, connector) {
12026 if (connector->base.encoder) {
12027 connector->base.state->best_encoder =
12028 connector->base.encoder;
12029 connector->base.state->crtc =
12030 connector->base.encoder->crtc;
12032 connector->base.state->best_encoder = NULL;
12033 connector->base.state->crtc = NULL;
12039 connected_sink_compute_bpp(struct intel_connector *connector,
12040 struct intel_crtc_state *pipe_config)
12042 int bpp = pipe_config->pipe_bpp;
12044 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12045 connector->base.base.id,
12046 connector->base.name);
12048 /* Don't use an invalid EDID bpc value */
12049 if (connector->base.display_info.bpc &&
12050 connector->base.display_info.bpc * 3 < bpp) {
12051 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12052 bpp, connector->base.display_info.bpc*3);
12053 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12056 /* Clamp bpp to default limit on screens without EDID 1.4 */
12057 if (connector->base.display_info.bpc == 0) {
12058 int type = connector->base.connector_type;
12059 int clamp_bpp = 24;
12061 /* Fall back to 18 bpp when DP sink capability is unknown. */
12062 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12063 type == DRM_MODE_CONNECTOR_eDP)
12066 if (bpp > clamp_bpp) {
12067 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12069 pipe_config->pipe_bpp = clamp_bpp;
12075 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12076 struct intel_crtc_state *pipe_config)
12078 struct drm_device *dev = crtc->base.dev;
12079 struct drm_atomic_state *state;
12080 struct drm_connector *connector;
12081 struct drm_connector_state *connector_state;
12084 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12086 else if (INTEL_INFO(dev)->gen >= 5)
12092 pipe_config->pipe_bpp = bpp;
12094 state = pipe_config->base.state;
12096 /* Clamp display bpp to EDID value */
12097 for_each_connector_in_state(state, connector, connector_state, i) {
12098 if (connector_state->crtc != &crtc->base)
12101 connected_sink_compute_bpp(to_intel_connector(connector),
12108 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12110 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12111 "type: 0x%x flags: 0x%x\n",
12113 mode->crtc_hdisplay, mode->crtc_hsync_start,
12114 mode->crtc_hsync_end, mode->crtc_htotal,
12115 mode->crtc_vdisplay, mode->crtc_vsync_start,
12116 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12119 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12120 struct intel_crtc_state *pipe_config,
12121 const char *context)
12123 struct drm_device *dev = crtc->base.dev;
12124 struct drm_plane *plane;
12125 struct intel_plane *intel_plane;
12126 struct intel_plane_state *state;
12127 struct drm_framebuffer *fb;
12129 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12130 context, pipe_config, pipe_name(crtc->pipe));
12132 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12133 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12134 pipe_config->pipe_bpp, pipe_config->dither);
12135 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12136 pipe_config->has_pch_encoder,
12137 pipe_config->fdi_lanes,
12138 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12139 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12140 pipe_config->fdi_m_n.tu);
12141 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12142 pipe_config->has_dp_encoder,
12143 pipe_config->lane_count,
12144 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12145 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12146 pipe_config->dp_m_n.tu);
12148 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12149 pipe_config->has_dp_encoder,
12150 pipe_config->lane_count,
12151 pipe_config->dp_m2_n2.gmch_m,
12152 pipe_config->dp_m2_n2.gmch_n,
12153 pipe_config->dp_m2_n2.link_m,
12154 pipe_config->dp_m2_n2.link_n,
12155 pipe_config->dp_m2_n2.tu);
12157 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12158 pipe_config->has_audio,
12159 pipe_config->has_infoframe);
12161 DRM_DEBUG_KMS("requested mode:\n");
12162 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12163 DRM_DEBUG_KMS("adjusted mode:\n");
12164 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12165 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12166 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12167 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12168 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12169 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12171 pipe_config->scaler_state.scaler_users,
12172 pipe_config->scaler_state.scaler_id);
12173 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12174 pipe_config->gmch_pfit.control,
12175 pipe_config->gmch_pfit.pgm_ratios,
12176 pipe_config->gmch_pfit.lvds_border_bits);
12177 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12178 pipe_config->pch_pfit.pos,
12179 pipe_config->pch_pfit.size,
12180 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12181 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12182 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12184 if (IS_BROXTON(dev)) {
12185 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12186 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12187 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12188 pipe_config->ddi_pll_sel,
12189 pipe_config->dpll_hw_state.ebb0,
12190 pipe_config->dpll_hw_state.ebb4,
12191 pipe_config->dpll_hw_state.pll0,
12192 pipe_config->dpll_hw_state.pll1,
12193 pipe_config->dpll_hw_state.pll2,
12194 pipe_config->dpll_hw_state.pll3,
12195 pipe_config->dpll_hw_state.pll6,
12196 pipe_config->dpll_hw_state.pll8,
12197 pipe_config->dpll_hw_state.pll9,
12198 pipe_config->dpll_hw_state.pll10,
12199 pipe_config->dpll_hw_state.pcsdw12);
12200 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12201 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12202 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12203 pipe_config->ddi_pll_sel,
12204 pipe_config->dpll_hw_state.ctrl1,
12205 pipe_config->dpll_hw_state.cfgcr1,
12206 pipe_config->dpll_hw_state.cfgcr2);
12207 } else if (HAS_DDI(dev)) {
12208 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12209 pipe_config->ddi_pll_sel,
12210 pipe_config->dpll_hw_state.wrpll,
12211 pipe_config->dpll_hw_state.spll);
12213 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12214 "fp0: 0x%x, fp1: 0x%x\n",
12215 pipe_config->dpll_hw_state.dpll,
12216 pipe_config->dpll_hw_state.dpll_md,
12217 pipe_config->dpll_hw_state.fp0,
12218 pipe_config->dpll_hw_state.fp1);
12221 DRM_DEBUG_KMS("planes on this crtc\n");
12222 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12223 intel_plane = to_intel_plane(plane);
12224 if (intel_plane->pipe != crtc->pipe)
12227 state = to_intel_plane_state(plane->state);
12228 fb = state->base.fb;
12230 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12231 "disabled, scaler_id = %d\n",
12232 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12233 plane->base.id, intel_plane->pipe,
12234 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12235 drm_plane_index(plane), state->scaler_id);
12239 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12240 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12241 plane->base.id, intel_plane->pipe,
12242 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12243 drm_plane_index(plane));
12244 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12245 fb->base.id, fb->width, fb->height, fb->pixel_format);
12246 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12248 state->src.x1 >> 16, state->src.y1 >> 16,
12249 drm_rect_width(&state->src) >> 16,
12250 drm_rect_height(&state->src) >> 16,
12251 state->dst.x1, state->dst.y1,
12252 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12256 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12258 struct drm_device *dev = state->dev;
12259 struct drm_connector *connector;
12260 unsigned int used_ports = 0;
12263 * Walk the connector list instead of the encoder
12264 * list to detect the problem on ddi platforms
12265 * where there's just one encoder per digital port.
12267 drm_for_each_connector(connector, dev) {
12268 struct drm_connector_state *connector_state;
12269 struct intel_encoder *encoder;
12271 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12272 if (!connector_state)
12273 connector_state = connector->state;
12275 if (!connector_state->best_encoder)
12278 encoder = to_intel_encoder(connector_state->best_encoder);
12280 WARN_ON(!connector_state->crtc);
12282 switch (encoder->type) {
12283 unsigned int port_mask;
12284 case INTEL_OUTPUT_UNKNOWN:
12285 if (WARN_ON(!HAS_DDI(dev)))
12287 case INTEL_OUTPUT_DISPLAYPORT:
12288 case INTEL_OUTPUT_HDMI:
12289 case INTEL_OUTPUT_EDP:
12290 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12292 /* the same port mustn't appear more than once */
12293 if (used_ports & port_mask)
12296 used_ports |= port_mask;
12306 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12308 struct drm_crtc_state tmp_state;
12309 struct intel_crtc_scaler_state scaler_state;
12310 struct intel_dpll_hw_state dpll_hw_state;
12311 struct intel_shared_dpll *shared_dpll;
12312 uint32_t ddi_pll_sel;
12315 /* FIXME: before the switch to atomic started, a new pipe_config was
12316 * kzalloc'd. Code that depends on any field being zero should be
12317 * fixed, so that the crtc_state can be safely duplicated. For now,
12318 * only fields that are know to not cause problems are preserved. */
12320 tmp_state = crtc_state->base;
12321 scaler_state = crtc_state->scaler_state;
12322 shared_dpll = crtc_state->shared_dpll;
12323 dpll_hw_state = crtc_state->dpll_hw_state;
12324 ddi_pll_sel = crtc_state->ddi_pll_sel;
12325 force_thru = crtc_state->pch_pfit.force_thru;
12327 memset(crtc_state, 0, sizeof *crtc_state);
12329 crtc_state->base = tmp_state;
12330 crtc_state->scaler_state = scaler_state;
12331 crtc_state->shared_dpll = shared_dpll;
12332 crtc_state->dpll_hw_state = dpll_hw_state;
12333 crtc_state->ddi_pll_sel = ddi_pll_sel;
12334 crtc_state->pch_pfit.force_thru = force_thru;
12338 intel_modeset_pipe_config(struct drm_crtc *crtc,
12339 struct intel_crtc_state *pipe_config)
12341 struct drm_atomic_state *state = pipe_config->base.state;
12342 struct intel_encoder *encoder;
12343 struct drm_connector *connector;
12344 struct drm_connector_state *connector_state;
12345 int base_bpp, ret = -EINVAL;
12349 clear_intel_crtc_state(pipe_config);
12351 pipe_config->cpu_transcoder =
12352 (enum transcoder) to_intel_crtc(crtc)->pipe;
12355 * Sanitize sync polarity flags based on requested ones. If neither
12356 * positive or negative polarity is requested, treat this as meaning
12357 * negative polarity.
12359 if (!(pipe_config->base.adjusted_mode.flags &
12360 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12361 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12363 if (!(pipe_config->base.adjusted_mode.flags &
12364 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12365 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12367 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12373 * Determine the real pipe dimensions. Note that stereo modes can
12374 * increase the actual pipe size due to the frame doubling and
12375 * insertion of additional space for blanks between the frame. This
12376 * is stored in the crtc timings. We use the requested mode to do this
12377 * computation to clearly distinguish it from the adjusted mode, which
12378 * can be changed by the connectors in the below retry loop.
12380 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12381 &pipe_config->pipe_src_w,
12382 &pipe_config->pipe_src_h);
12385 /* Ensure the port clock defaults are reset when retrying. */
12386 pipe_config->port_clock = 0;
12387 pipe_config->pixel_multiplier = 1;
12389 /* Fill in default crtc timings, allow encoders to overwrite them. */
12390 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12391 CRTC_STEREO_DOUBLE);
12393 /* Pass our mode to the connectors and the CRTC to give them a chance to
12394 * adjust it according to limitations or connector properties, and also
12395 * a chance to reject the mode entirely.
12397 for_each_connector_in_state(state, connector, connector_state, i) {
12398 if (connector_state->crtc != crtc)
12401 encoder = to_intel_encoder(connector_state->best_encoder);
12403 if (!(encoder->compute_config(encoder, pipe_config))) {
12404 DRM_DEBUG_KMS("Encoder config failure\n");
12409 /* Set default port clock if not overwritten by the encoder. Needs to be
12410 * done afterwards in case the encoder adjusts the mode. */
12411 if (!pipe_config->port_clock)
12412 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12413 * pipe_config->pixel_multiplier;
12415 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12417 DRM_DEBUG_KMS("CRTC fixup failed\n");
12421 if (ret == RETRY) {
12422 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12427 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12429 goto encoder_retry;
12432 /* Dithering seems to not pass-through bits correctly when it should, so
12433 * only enable it on 6bpc panels. */
12434 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12435 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12436 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12443 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12445 struct drm_crtc *crtc;
12446 struct drm_crtc_state *crtc_state;
12449 /* Double check state. */
12450 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12451 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12453 /* Update hwmode for vblank functions */
12454 if (crtc->state->active)
12455 crtc->hwmode = crtc->state->adjusted_mode;
12457 crtc->hwmode.crtc_clock = 0;
12460 * Update legacy state to satisfy fbc code. This can
12461 * be removed when fbc uses the atomic state.
12463 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12464 struct drm_plane_state *plane_state = crtc->primary->state;
12466 crtc->primary->fb = plane_state->fb;
12467 crtc->x = plane_state->src_x >> 16;
12468 crtc->y = plane_state->src_y >> 16;
12473 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12477 if (clock1 == clock2)
12480 if (!clock1 || !clock2)
12483 diff = abs(clock1 - clock2);
12485 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12491 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12492 list_for_each_entry((intel_crtc), \
12493 &(dev)->mode_config.crtc_list, \
12495 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12498 intel_compare_m_n(unsigned int m, unsigned int n,
12499 unsigned int m2, unsigned int n2,
12502 if (m == m2 && n == n2)
12505 if (exact || !m || !n || !m2 || !n2)
12508 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12515 } else if (n < n2) {
12525 return intel_fuzzy_clock_check(m, m2);
12529 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12530 struct intel_link_m_n *m2_n2,
12533 if (m_n->tu == m2_n2->tu &&
12534 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12535 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12536 intel_compare_m_n(m_n->link_m, m_n->link_n,
12537 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12548 intel_pipe_config_compare(struct drm_device *dev,
12549 struct intel_crtc_state *current_config,
12550 struct intel_crtc_state *pipe_config,
12555 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12558 DRM_ERROR(fmt, ##__VA_ARGS__); \
12560 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12563 #define PIPE_CONF_CHECK_X(name) \
12564 if (current_config->name != pipe_config->name) { \
12565 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12566 "(expected 0x%08x, found 0x%08x)\n", \
12567 current_config->name, \
12568 pipe_config->name); \
12572 #define PIPE_CONF_CHECK_I(name) \
12573 if (current_config->name != pipe_config->name) { \
12574 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12575 "(expected %i, found %i)\n", \
12576 current_config->name, \
12577 pipe_config->name); \
12581 #define PIPE_CONF_CHECK_P(name) \
12582 if (current_config->name != pipe_config->name) { \
12583 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12584 "(expected %p, found %p)\n", \
12585 current_config->name, \
12586 pipe_config->name); \
12590 #define PIPE_CONF_CHECK_M_N(name) \
12591 if (!intel_compare_link_m_n(¤t_config->name, \
12592 &pipe_config->name,\
12594 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12595 "(expected tu %i gmch %i/%i link %i/%i, " \
12596 "found tu %i, gmch %i/%i link %i/%i)\n", \
12597 current_config->name.tu, \
12598 current_config->name.gmch_m, \
12599 current_config->name.gmch_n, \
12600 current_config->name.link_m, \
12601 current_config->name.link_n, \
12602 pipe_config->name.tu, \
12603 pipe_config->name.gmch_m, \
12604 pipe_config->name.gmch_n, \
12605 pipe_config->name.link_m, \
12606 pipe_config->name.link_n); \
12610 /* This is required for BDW+ where there is only one set of registers for
12611 * switching between high and low RR.
12612 * This macro can be used whenever a comparison has to be made between one
12613 * hw state and multiple sw state variables.
12615 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12616 if (!intel_compare_link_m_n(¤t_config->name, \
12617 &pipe_config->name, adjust) && \
12618 !intel_compare_link_m_n(¤t_config->alt_name, \
12619 &pipe_config->name, adjust)) { \
12620 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12621 "(expected tu %i gmch %i/%i link %i/%i, " \
12622 "or tu %i gmch %i/%i link %i/%i, " \
12623 "found tu %i, gmch %i/%i link %i/%i)\n", \
12624 current_config->name.tu, \
12625 current_config->name.gmch_m, \
12626 current_config->name.gmch_n, \
12627 current_config->name.link_m, \
12628 current_config->name.link_n, \
12629 current_config->alt_name.tu, \
12630 current_config->alt_name.gmch_m, \
12631 current_config->alt_name.gmch_n, \
12632 current_config->alt_name.link_m, \
12633 current_config->alt_name.link_n, \
12634 pipe_config->name.tu, \
12635 pipe_config->name.gmch_m, \
12636 pipe_config->name.gmch_n, \
12637 pipe_config->name.link_m, \
12638 pipe_config->name.link_n); \
12642 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12643 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12644 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12645 "(expected %i, found %i)\n", \
12646 current_config->name & (mask), \
12647 pipe_config->name & (mask)); \
12651 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12652 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12653 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12654 "(expected %i, found %i)\n", \
12655 current_config->name, \
12656 pipe_config->name); \
12660 #define PIPE_CONF_QUIRK(quirk) \
12661 ((current_config->quirks | pipe_config->quirks) & (quirk))
12663 PIPE_CONF_CHECK_I(cpu_transcoder);
12665 PIPE_CONF_CHECK_I(has_pch_encoder);
12666 PIPE_CONF_CHECK_I(fdi_lanes);
12667 PIPE_CONF_CHECK_M_N(fdi_m_n);
12669 PIPE_CONF_CHECK_I(has_dp_encoder);
12670 PIPE_CONF_CHECK_I(lane_count);
12672 if (INTEL_INFO(dev)->gen < 8) {
12673 PIPE_CONF_CHECK_M_N(dp_m_n);
12675 if (current_config->has_drrs)
12676 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12678 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12680 PIPE_CONF_CHECK_I(has_dsi_encoder);
12682 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12683 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12684 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12685 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12686 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12687 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12690 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12691 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12694 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12696 PIPE_CONF_CHECK_I(pixel_multiplier);
12697 PIPE_CONF_CHECK_I(has_hdmi_sink);
12698 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12699 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12700 PIPE_CONF_CHECK_I(limited_color_range);
12701 PIPE_CONF_CHECK_I(has_infoframe);
12703 PIPE_CONF_CHECK_I(has_audio);
12705 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12706 DRM_MODE_FLAG_INTERLACE);
12708 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12709 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12710 DRM_MODE_FLAG_PHSYNC);
12711 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12712 DRM_MODE_FLAG_NHSYNC);
12713 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12714 DRM_MODE_FLAG_PVSYNC);
12715 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12716 DRM_MODE_FLAG_NVSYNC);
12719 PIPE_CONF_CHECK_X(gmch_pfit.control);
12720 /* pfit ratios are autocomputed by the hw on gen4+ */
12721 if (INTEL_INFO(dev)->gen < 4)
12722 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12723 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12726 PIPE_CONF_CHECK_I(pipe_src_w);
12727 PIPE_CONF_CHECK_I(pipe_src_h);
12729 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12730 if (current_config->pch_pfit.enabled) {
12731 PIPE_CONF_CHECK_X(pch_pfit.pos);
12732 PIPE_CONF_CHECK_X(pch_pfit.size);
12735 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12738 /* BDW+ don't expose a synchronous way to read the state */
12739 if (IS_HASWELL(dev))
12740 PIPE_CONF_CHECK_I(ips_enabled);
12742 PIPE_CONF_CHECK_I(double_wide);
12744 PIPE_CONF_CHECK_X(ddi_pll_sel);
12746 PIPE_CONF_CHECK_P(shared_dpll);
12747 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12748 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12749 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12750 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12751 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12752 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12753 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12754 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12755 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12757 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12758 PIPE_CONF_CHECK_X(dsi_pll.div);
12760 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12761 PIPE_CONF_CHECK_I(pipe_bpp);
12763 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12764 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12766 #undef PIPE_CONF_CHECK_X
12767 #undef PIPE_CONF_CHECK_I
12768 #undef PIPE_CONF_CHECK_P
12769 #undef PIPE_CONF_CHECK_FLAGS
12770 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12771 #undef PIPE_CONF_QUIRK
12772 #undef INTEL_ERR_OR_DBG_KMS
12777 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12778 const struct intel_crtc_state *pipe_config)
12780 if (pipe_config->has_pch_encoder) {
12781 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12782 &pipe_config->fdi_m_n);
12783 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12786 * FDI already provided one idea for the dotclock.
12787 * Yell if the encoder disagrees.
12789 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12790 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12791 fdi_dotclock, dotclock);
12795 static void verify_wm_state(struct drm_crtc *crtc,
12796 struct drm_crtc_state *new_state)
12798 struct drm_device *dev = crtc->dev;
12799 struct drm_i915_private *dev_priv = dev->dev_private;
12800 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12801 struct skl_ddb_entry *hw_entry, *sw_entry;
12802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12803 const enum pipe pipe = intel_crtc->pipe;
12806 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12809 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12810 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12813 for_each_plane(dev_priv, pipe, plane) {
12814 hw_entry = &hw_ddb.plane[pipe][plane];
12815 sw_entry = &sw_ddb->plane[pipe][plane];
12817 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12820 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12821 "(expected (%u,%u), found (%u,%u))\n",
12822 pipe_name(pipe), plane + 1,
12823 sw_entry->start, sw_entry->end,
12824 hw_entry->start, hw_entry->end);
12828 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12829 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12831 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12832 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12833 "(expected (%u,%u), found (%u,%u))\n",
12835 sw_entry->start, sw_entry->end,
12836 hw_entry->start, hw_entry->end);
12841 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12843 struct drm_connector *connector;
12845 drm_for_each_connector(connector, dev) {
12846 struct drm_encoder *encoder = connector->encoder;
12847 struct drm_connector_state *state = connector->state;
12849 if (state->crtc != crtc)
12852 intel_connector_verify_state(to_intel_connector(connector));
12854 I915_STATE_WARN(state->best_encoder != encoder,
12855 "connector's atomic encoder doesn't match legacy encoder\n");
12860 verify_encoder_state(struct drm_device *dev)
12862 struct intel_encoder *encoder;
12863 struct intel_connector *connector;
12865 for_each_intel_encoder(dev, encoder) {
12866 bool enabled = false;
12869 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12870 encoder->base.base.id,
12871 encoder->base.name);
12873 for_each_intel_connector(dev, connector) {
12874 if (connector->base.state->best_encoder != &encoder->base)
12878 I915_STATE_WARN(connector->base.state->crtc !=
12879 encoder->base.crtc,
12880 "connector's crtc doesn't match encoder crtc\n");
12883 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12884 "encoder's enabled state mismatch "
12885 "(expected %i, found %i)\n",
12886 !!encoder->base.crtc, enabled);
12888 if (!encoder->base.crtc) {
12891 active = encoder->get_hw_state(encoder, &pipe);
12892 I915_STATE_WARN(active,
12893 "encoder detached but still enabled on pipe %c.\n",
12900 verify_crtc_state(struct drm_crtc *crtc,
12901 struct drm_crtc_state *old_crtc_state,
12902 struct drm_crtc_state *new_crtc_state)
12904 struct drm_device *dev = crtc->dev;
12905 struct drm_i915_private *dev_priv = dev->dev_private;
12906 struct intel_encoder *encoder;
12907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12908 struct intel_crtc_state *pipe_config, *sw_config;
12909 struct drm_atomic_state *old_state;
12912 old_state = old_crtc_state->state;
12913 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12914 pipe_config = to_intel_crtc_state(old_crtc_state);
12915 memset(pipe_config, 0, sizeof(*pipe_config));
12916 pipe_config->base.crtc = crtc;
12917 pipe_config->base.state = old_state;
12919 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12921 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12923 /* hw state is inconsistent with the pipe quirk */
12924 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12925 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12926 active = new_crtc_state->active;
12928 I915_STATE_WARN(new_crtc_state->active != active,
12929 "crtc active state doesn't match with hw state "
12930 "(expected %i, found %i)\n", new_crtc_state->active, active);
12932 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12933 "transitional active state does not match atomic hw state "
12934 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12936 for_each_encoder_on_crtc(dev, crtc, encoder) {
12939 active = encoder->get_hw_state(encoder, &pipe);
12940 I915_STATE_WARN(active != new_crtc_state->active,
12941 "[ENCODER:%i] active %i with crtc active %i\n",
12942 encoder->base.base.id, active, new_crtc_state->active);
12944 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12945 "Encoder connected to wrong pipe %c\n",
12949 encoder->get_config(encoder, pipe_config);
12952 if (!new_crtc_state->active)
12955 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12957 sw_config = to_intel_crtc_state(crtc->state);
12958 if (!intel_pipe_config_compare(dev, sw_config,
12959 pipe_config, false)) {
12960 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12961 intel_dump_pipe_config(intel_crtc, pipe_config,
12963 intel_dump_pipe_config(intel_crtc, sw_config,
12969 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12970 struct intel_shared_dpll *pll,
12971 struct drm_crtc *crtc,
12972 struct drm_crtc_state *new_state)
12974 struct intel_dpll_hw_state dpll_hw_state;
12975 unsigned crtc_mask;
12978 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12980 DRM_DEBUG_KMS("%s\n", pll->name);
12982 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12984 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12985 I915_STATE_WARN(!pll->on && pll->active_mask,
12986 "pll in active use but not on in sw tracking\n");
12987 I915_STATE_WARN(pll->on && !pll->active_mask,
12988 "pll is on but not used by any active crtc\n");
12989 I915_STATE_WARN(pll->on != active,
12990 "pll on state mismatch (expected %i, found %i)\n",
12995 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12996 "more active pll users than references: %x vs %x\n",
12997 pll->active_mask, pll->config.crtc_mask);
13002 crtc_mask = 1 << drm_crtc_index(crtc);
13004 if (new_state->active)
13005 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13006 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13007 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13009 I915_STATE_WARN(pll->active_mask & crtc_mask,
13010 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13011 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13013 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13014 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13015 crtc_mask, pll->config.crtc_mask);
13017 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13019 sizeof(dpll_hw_state)),
13020 "pll hw state mismatch\n");
13024 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13025 struct drm_crtc_state *old_crtc_state,
13026 struct drm_crtc_state *new_crtc_state)
13028 struct drm_i915_private *dev_priv = dev->dev_private;
13029 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13030 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13032 if (new_state->shared_dpll)
13033 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13035 if (old_state->shared_dpll &&
13036 old_state->shared_dpll != new_state->shared_dpll) {
13037 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13038 struct intel_shared_dpll *pll = old_state->shared_dpll;
13040 I915_STATE_WARN(pll->active_mask & crtc_mask,
13041 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13042 pipe_name(drm_crtc_index(crtc)));
13043 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13044 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13045 pipe_name(drm_crtc_index(crtc)));
13050 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13051 struct drm_crtc_state *old_state,
13052 struct drm_crtc_state *new_state)
13054 if (!needs_modeset(new_state) &&
13055 !to_intel_crtc_state(new_state)->update_pipe)
13058 verify_wm_state(crtc, new_state);
13059 verify_connector_state(crtc->dev, crtc);
13060 verify_crtc_state(crtc, old_state, new_state);
13061 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13065 verify_disabled_dpll_state(struct drm_device *dev)
13067 struct drm_i915_private *dev_priv = dev->dev_private;
13070 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13071 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13075 intel_modeset_verify_disabled(struct drm_device *dev)
13077 verify_encoder_state(dev);
13078 verify_connector_state(dev, NULL);
13079 verify_disabled_dpll_state(dev);
13082 static void update_scanline_offset(struct intel_crtc *crtc)
13084 struct drm_device *dev = crtc->base.dev;
13087 * The scanline counter increments at the leading edge of hsync.
13089 * On most platforms it starts counting from vtotal-1 on the
13090 * first active line. That means the scanline counter value is
13091 * always one less than what we would expect. Ie. just after
13092 * start of vblank, which also occurs at start of hsync (on the
13093 * last active line), the scanline counter will read vblank_start-1.
13095 * On gen2 the scanline counter starts counting from 1 instead
13096 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13097 * to keep the value positive), instead of adding one.
13099 * On HSW+ the behaviour of the scanline counter depends on the output
13100 * type. For DP ports it behaves like most other platforms, but on HDMI
13101 * there's an extra 1 line difference. So we need to add two instead of
13102 * one to the value.
13104 if (IS_GEN2(dev)) {
13105 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13108 vtotal = adjusted_mode->crtc_vtotal;
13109 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13112 crtc->scanline_offset = vtotal - 1;
13113 } else if (HAS_DDI(dev) &&
13114 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13115 crtc->scanline_offset = 2;
13117 crtc->scanline_offset = 1;
13120 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13122 struct drm_device *dev = state->dev;
13123 struct drm_i915_private *dev_priv = to_i915(dev);
13124 struct intel_shared_dpll_config *shared_dpll = NULL;
13125 struct drm_crtc *crtc;
13126 struct drm_crtc_state *crtc_state;
13129 if (!dev_priv->display.crtc_compute_clock)
13132 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13134 struct intel_shared_dpll *old_dpll =
13135 to_intel_crtc_state(crtc->state)->shared_dpll;
13137 if (!needs_modeset(crtc_state))
13140 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13146 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13148 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13153 * This implements the workaround described in the "notes" section of the mode
13154 * set sequence documentation. When going from no pipes or single pipe to
13155 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13156 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13158 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13160 struct drm_crtc_state *crtc_state;
13161 struct intel_crtc *intel_crtc;
13162 struct drm_crtc *crtc;
13163 struct intel_crtc_state *first_crtc_state = NULL;
13164 struct intel_crtc_state *other_crtc_state = NULL;
13165 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13168 /* look at all crtc's that are going to be enabled in during modeset */
13169 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13170 intel_crtc = to_intel_crtc(crtc);
13172 if (!crtc_state->active || !needs_modeset(crtc_state))
13175 if (first_crtc_state) {
13176 other_crtc_state = to_intel_crtc_state(crtc_state);
13179 first_crtc_state = to_intel_crtc_state(crtc_state);
13180 first_pipe = intel_crtc->pipe;
13184 /* No workaround needed? */
13185 if (!first_crtc_state)
13188 /* w/a possibly needed, check how many crtc's are already enabled. */
13189 for_each_intel_crtc(state->dev, intel_crtc) {
13190 struct intel_crtc_state *pipe_config;
13192 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13193 if (IS_ERR(pipe_config))
13194 return PTR_ERR(pipe_config);
13196 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13198 if (!pipe_config->base.active ||
13199 needs_modeset(&pipe_config->base))
13202 /* 2 or more enabled crtcs means no need for w/a */
13203 if (enabled_pipe != INVALID_PIPE)
13206 enabled_pipe = intel_crtc->pipe;
13209 if (enabled_pipe != INVALID_PIPE)
13210 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13211 else if (other_crtc_state)
13212 other_crtc_state->hsw_workaround_pipe = first_pipe;
13217 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13219 struct drm_crtc *crtc;
13220 struct drm_crtc_state *crtc_state;
13223 /* add all active pipes to the state */
13224 for_each_crtc(state->dev, crtc) {
13225 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13226 if (IS_ERR(crtc_state))
13227 return PTR_ERR(crtc_state);
13229 if (!crtc_state->active || needs_modeset(crtc_state))
13232 crtc_state->mode_changed = true;
13234 ret = drm_atomic_add_affected_connectors(state, crtc);
13238 ret = drm_atomic_add_affected_planes(state, crtc);
13246 static int intel_modeset_checks(struct drm_atomic_state *state)
13248 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13249 struct drm_i915_private *dev_priv = state->dev->dev_private;
13250 struct drm_crtc *crtc;
13251 struct drm_crtc_state *crtc_state;
13254 if (!check_digital_port_conflicts(state)) {
13255 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13259 intel_state->modeset = true;
13260 intel_state->active_crtcs = dev_priv->active_crtcs;
13262 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13263 if (crtc_state->active)
13264 intel_state->active_crtcs |= 1 << i;
13266 intel_state->active_crtcs &= ~(1 << i);
13270 * See if the config requires any additional preparation, e.g.
13271 * to adjust global state with pipes off. We need to do this
13272 * here so we can get the modeset_pipe updated config for the new
13273 * mode set on this crtc. For other crtcs we need to use the
13274 * adjusted_mode bits in the crtc directly.
13276 if (dev_priv->display.modeset_calc_cdclk) {
13277 ret = dev_priv->display.modeset_calc_cdclk(state);
13279 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13280 ret = intel_modeset_all_pipes(state);
13285 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13286 intel_state->cdclk, intel_state->dev_cdclk);
13288 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13290 intel_modeset_clear_plls(state);
13292 if (IS_HASWELL(dev_priv))
13293 return haswell_mode_set_planes_workaround(state);
13299 * Handle calculation of various watermark data at the end of the atomic check
13300 * phase. The code here should be run after the per-crtc and per-plane 'check'
13301 * handlers to ensure that all derived state has been updated.
13303 static void calc_watermark_data(struct drm_atomic_state *state)
13305 struct drm_device *dev = state->dev;
13306 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13307 struct drm_crtc *crtc;
13308 struct drm_crtc_state *cstate;
13309 struct drm_plane *plane;
13310 struct drm_plane_state *pstate;
13313 * Calculate watermark configuration details now that derived
13314 * plane/crtc state is all properly updated.
13316 drm_for_each_crtc(crtc, dev) {
13317 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13320 if (cstate->active)
13321 intel_state->wm_config.num_pipes_active++;
13323 drm_for_each_legacy_plane(plane, dev) {
13324 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13327 if (!to_intel_plane_state(pstate)->visible)
13330 intel_state->wm_config.sprites_enabled = true;
13331 if (pstate->crtc_w != pstate->src_w >> 16 ||
13332 pstate->crtc_h != pstate->src_h >> 16)
13333 intel_state->wm_config.sprites_scaled = true;
13338 * intel_atomic_check - validate state object
13340 * @state: state to validate
13342 static int intel_atomic_check(struct drm_device *dev,
13343 struct drm_atomic_state *state)
13345 struct drm_i915_private *dev_priv = to_i915(dev);
13346 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13347 struct drm_crtc *crtc;
13348 struct drm_crtc_state *crtc_state;
13350 bool any_ms = false;
13352 ret = drm_atomic_helper_check_modeset(dev, state);
13356 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13357 struct intel_crtc_state *pipe_config =
13358 to_intel_crtc_state(crtc_state);
13360 /* Catch I915_MODE_FLAG_INHERITED */
13361 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13362 crtc_state->mode_changed = true;
13364 if (!crtc_state->enable) {
13365 if (needs_modeset(crtc_state))
13370 if (!needs_modeset(crtc_state))
13373 /* FIXME: For only active_changed we shouldn't need to do any
13374 * state recomputation at all. */
13376 ret = drm_atomic_add_affected_connectors(state, crtc);
13380 ret = intel_modeset_pipe_config(crtc, pipe_config);
13384 if (i915.fastboot &&
13385 intel_pipe_config_compare(dev,
13386 to_intel_crtc_state(crtc->state),
13387 pipe_config, true)) {
13388 crtc_state->mode_changed = false;
13389 to_intel_crtc_state(crtc_state)->update_pipe = true;
13392 if (needs_modeset(crtc_state)) {
13395 ret = drm_atomic_add_affected_planes(state, crtc);
13400 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13401 needs_modeset(crtc_state) ?
13402 "[modeset]" : "[fastset]");
13406 ret = intel_modeset_checks(state);
13411 intel_state->cdclk = dev_priv->cdclk_freq;
13413 ret = drm_atomic_helper_check_planes(dev, state);
13417 intel_fbc_choose_crtc(dev_priv, state);
13418 calc_watermark_data(state);
13423 static int intel_atomic_prepare_commit(struct drm_device *dev,
13424 struct drm_atomic_state *state,
13427 struct drm_i915_private *dev_priv = dev->dev_private;
13428 struct drm_plane_state *plane_state;
13429 struct drm_crtc_state *crtc_state;
13430 struct drm_plane *plane;
13431 struct drm_crtc *crtc;
13435 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13439 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13440 if (state->legacy_cursor_update)
13443 ret = intel_crtc_wait_for_pending_flips(crtc);
13447 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13448 flush_workqueue(dev_priv->wq);
13451 ret = mutex_lock_interruptible(&dev->struct_mutex);
13455 ret = drm_atomic_helper_prepare_planes(dev, state);
13456 mutex_unlock(&dev->struct_mutex);
13458 if (!ret && !async) {
13459 for_each_plane_in_state(state, plane, plane_state, i) {
13460 struct intel_plane_state *intel_plane_state =
13461 to_intel_plane_state(plane_state);
13463 if (!intel_plane_state->wait_req)
13466 ret = __i915_wait_request(intel_plane_state->wait_req,
13469 /* Any hang should be swallowed by the wait */
13470 WARN_ON(ret == -EIO);
13471 mutex_lock(&dev->struct_mutex);
13472 drm_atomic_helper_cleanup_planes(dev, state);
13473 mutex_unlock(&dev->struct_mutex);
13482 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13483 struct drm_i915_private *dev_priv,
13484 unsigned crtc_mask)
13486 unsigned last_vblank_count[I915_MAX_PIPES];
13493 for_each_pipe(dev_priv, pipe) {
13494 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13496 if (!((1 << pipe) & crtc_mask))
13499 ret = drm_crtc_vblank_get(crtc);
13500 if (WARN_ON(ret != 0)) {
13501 crtc_mask &= ~(1 << pipe);
13505 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13508 for_each_pipe(dev_priv, pipe) {
13509 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13512 if (!((1 << pipe) & crtc_mask))
13515 lret = wait_event_timeout(dev->vblank[pipe].queue,
13516 last_vblank_count[pipe] !=
13517 drm_crtc_vblank_count(crtc),
13518 msecs_to_jiffies(50));
13520 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13522 drm_crtc_vblank_put(crtc);
13526 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13528 /* fb updated, need to unpin old fb */
13529 if (crtc_state->fb_changed)
13532 /* wm changes, need vblank before final wm's */
13533 if (crtc_state->update_wm_post)
13537 * cxsr is re-enabled after vblank.
13538 * This is already handled by crtc_state->update_wm_post,
13539 * but added for clarity.
13541 if (crtc_state->disable_cxsr)
13548 * intel_atomic_commit - commit validated state object
13550 * @state: the top-level driver state object
13551 * @async: asynchronous commit
13553 * This function commits a top-level state object that has been validated
13554 * with drm_atomic_helper_check().
13556 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13557 * we can only handle plane-related operations and do not yet support
13558 * asynchronous commit.
13561 * Zero for success or -errno.
13563 static int intel_atomic_commit(struct drm_device *dev,
13564 struct drm_atomic_state *state,
13567 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13568 struct drm_i915_private *dev_priv = dev->dev_private;
13569 struct drm_crtc_state *old_crtc_state;
13570 struct drm_crtc *crtc;
13571 struct intel_crtc_state *intel_cstate;
13573 bool hw_check = intel_state->modeset;
13574 unsigned long put_domains[I915_MAX_PIPES] = {};
13575 unsigned crtc_vblank_mask = 0;
13577 ret = intel_atomic_prepare_commit(dev, state, async);
13579 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13583 drm_atomic_helper_swap_state(dev, state);
13584 dev_priv->wm.config = intel_state->wm_config;
13585 intel_shared_dpll_commit(state);
13587 if (intel_state->modeset) {
13588 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13589 sizeof(intel_state->min_pixclk));
13590 dev_priv->active_crtcs = intel_state->active_crtcs;
13591 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13593 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13596 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13599 if (needs_modeset(crtc->state) ||
13600 to_intel_crtc_state(crtc->state)->update_pipe) {
13603 put_domains[to_intel_crtc(crtc)->pipe] =
13604 modeset_get_crtc_power_domains(crtc,
13605 to_intel_crtc_state(crtc->state));
13608 if (!needs_modeset(crtc->state))
13611 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13613 if (old_crtc_state->active) {
13614 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13615 dev_priv->display.crtc_disable(crtc);
13616 intel_crtc->active = false;
13617 intel_fbc_disable(intel_crtc);
13618 intel_disable_shared_dpll(intel_crtc);
13621 * Underruns don't always raise
13622 * interrupts, so check manually.
13624 intel_check_cpu_fifo_underruns(dev_priv);
13625 intel_check_pch_fifo_underruns(dev_priv);
13627 if (!crtc->state->active)
13628 intel_update_watermarks(crtc);
13632 /* Only after disabling all output pipelines that will be changed can we
13633 * update the the output configuration. */
13634 intel_modeset_update_crtc_state(state);
13636 if (intel_state->modeset) {
13637 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13639 if (dev_priv->display.modeset_commit_cdclk &&
13640 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13641 dev_priv->display.modeset_commit_cdclk(state);
13643 intel_modeset_verify_disabled(dev);
13646 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13647 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13649 bool modeset = needs_modeset(crtc->state);
13650 struct intel_crtc_state *pipe_config =
13651 to_intel_crtc_state(crtc->state);
13652 bool update_pipe = !modeset && pipe_config->update_pipe;
13654 if (modeset && crtc->state->active) {
13655 update_scanline_offset(to_intel_crtc(crtc));
13656 dev_priv->display.crtc_enable(crtc);
13660 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13662 if (crtc->state->active &&
13663 drm_atomic_get_existing_plane_state(state, crtc->primary))
13664 intel_fbc_enable(intel_crtc);
13666 if (crtc->state->active &&
13667 (crtc->state->planes_changed || update_pipe))
13668 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13670 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13671 crtc_vblank_mask |= 1 << i;
13674 /* FIXME: add subpixel order */
13676 if (!state->legacy_cursor_update)
13677 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13680 * Now that the vblank has passed, we can go ahead and program the
13681 * optimal watermarks on platforms that need two-step watermark
13684 * TODO: Move this (and other cleanup) to an async worker eventually.
13686 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13687 intel_cstate = to_intel_crtc_state(crtc->state);
13689 if (dev_priv->display.optimize_watermarks)
13690 dev_priv->display.optimize_watermarks(intel_cstate);
13693 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13694 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13696 if (put_domains[i])
13697 modeset_put_power_domains(dev_priv, put_domains[i]);
13699 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13702 if (intel_state->modeset)
13703 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13705 mutex_lock(&dev->struct_mutex);
13706 drm_atomic_helper_cleanup_planes(dev, state);
13707 mutex_unlock(&dev->struct_mutex);
13709 drm_atomic_state_free(state);
13711 /* As one of the primary mmio accessors, KMS has a high likelihood
13712 * of triggering bugs in unclaimed access. After we finish
13713 * modesetting, see if an error has been flagged, and if so
13714 * enable debugging for the next modeset - and hope we catch
13717 * XXX note that we assume display power is on at this point.
13718 * This might hold true now but we need to add pm helper to check
13719 * unclaimed only when the hardware is on, as atomic commits
13720 * can happen also when the device is completely off.
13722 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13727 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13729 struct drm_device *dev = crtc->dev;
13730 struct drm_atomic_state *state;
13731 struct drm_crtc_state *crtc_state;
13734 state = drm_atomic_state_alloc(dev);
13736 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13741 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13744 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13745 ret = PTR_ERR_OR_ZERO(crtc_state);
13747 if (!crtc_state->active)
13750 crtc_state->mode_changed = true;
13751 ret = drm_atomic_commit(state);
13754 if (ret == -EDEADLK) {
13755 drm_atomic_state_clear(state);
13756 drm_modeset_backoff(state->acquire_ctx);
13762 drm_atomic_state_free(state);
13765 #undef for_each_intel_crtc_masked
13767 static const struct drm_crtc_funcs intel_crtc_funcs = {
13768 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13769 .set_config = drm_atomic_helper_set_config,
13770 .set_property = drm_atomic_helper_crtc_set_property,
13771 .destroy = intel_crtc_destroy,
13772 .page_flip = intel_crtc_page_flip,
13773 .atomic_duplicate_state = intel_crtc_duplicate_state,
13774 .atomic_destroy_state = intel_crtc_destroy_state,
13778 * intel_prepare_plane_fb - Prepare fb for usage on plane
13779 * @plane: drm plane to prepare for
13780 * @fb: framebuffer to prepare for presentation
13782 * Prepares a framebuffer for usage on a display plane. Generally this
13783 * involves pinning the underlying object and updating the frontbuffer tracking
13784 * bits. Some older platforms need special physical address handling for
13787 * Must be called with struct_mutex held.
13789 * Returns 0 on success, negative error code on failure.
13792 intel_prepare_plane_fb(struct drm_plane *plane,
13793 const struct drm_plane_state *new_state)
13795 struct drm_device *dev = plane->dev;
13796 struct drm_framebuffer *fb = new_state->fb;
13797 struct intel_plane *intel_plane = to_intel_plane(plane);
13798 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13799 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13802 if (!obj && !old_obj)
13806 struct drm_crtc_state *crtc_state =
13807 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13809 /* Big Hammer, we also need to ensure that any pending
13810 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13811 * current scanout is retired before unpinning the old
13812 * framebuffer. Note that we rely on userspace rendering
13813 * into the buffer attached to the pipe they are waiting
13814 * on. If not, userspace generates a GPU hang with IPEHR
13815 * point to the MI_WAIT_FOR_EVENT.
13817 * This should only fail upon a hung GPU, in which case we
13818 * can safely continue.
13820 if (needs_modeset(crtc_state))
13821 ret = i915_gem_object_wait_rendering(old_obj, true);
13823 /* GPU hangs should have been swallowed by the wait */
13824 WARN_ON(ret == -EIO);
13829 /* For framebuffer backed by dmabuf, wait for fence */
13830 if (obj && obj->base.dma_buf) {
13833 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13835 MAX_SCHEDULE_TIMEOUT);
13836 if (lret == -ERESTARTSYS)
13839 WARN(lret < 0, "waiting returns %li\n", lret);
13844 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13845 INTEL_INFO(dev)->cursor_needs_physical) {
13846 int align = IS_I830(dev) ? 16 * 1024 : 256;
13847 ret = i915_gem_object_attach_phys(obj, align);
13849 DRM_DEBUG_KMS("failed to attach phys object\n");
13851 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13856 struct intel_plane_state *plane_state =
13857 to_intel_plane_state(new_state);
13859 i915_gem_request_assign(&plane_state->wait_req,
13860 obj->last_write_req);
13863 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13870 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13871 * @plane: drm plane to clean up for
13872 * @fb: old framebuffer that was on plane
13874 * Cleans up a framebuffer that has just been removed from a plane.
13876 * Must be called with struct_mutex held.
13879 intel_cleanup_plane_fb(struct drm_plane *plane,
13880 const struct drm_plane_state *old_state)
13882 struct drm_device *dev = plane->dev;
13883 struct intel_plane *intel_plane = to_intel_plane(plane);
13884 struct intel_plane_state *old_intel_state;
13885 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13886 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13888 old_intel_state = to_intel_plane_state(old_state);
13890 if (!obj && !old_obj)
13893 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13894 !INTEL_INFO(dev)->cursor_needs_physical))
13895 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13897 /* prepare_fb aborted? */
13898 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13899 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13900 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13902 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13906 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13909 struct drm_device *dev;
13910 struct drm_i915_private *dev_priv;
13911 int crtc_clock, cdclk;
13913 if (!intel_crtc || !crtc_state->base.enable)
13914 return DRM_PLANE_HELPER_NO_SCALING;
13916 dev = intel_crtc->base.dev;
13917 dev_priv = dev->dev_private;
13918 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13919 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13921 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13922 return DRM_PLANE_HELPER_NO_SCALING;
13925 * skl max scale is lower of:
13926 * close to 3 but not 3, -1 is for that purpose
13930 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13936 intel_check_primary_plane(struct drm_plane *plane,
13937 struct intel_crtc_state *crtc_state,
13938 struct intel_plane_state *state)
13940 struct drm_crtc *crtc = state->base.crtc;
13941 struct drm_framebuffer *fb = state->base.fb;
13942 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13943 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13944 bool can_position = false;
13946 if (INTEL_INFO(plane->dev)->gen >= 9) {
13947 /* use scaler when colorkey is not required */
13948 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13950 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13952 can_position = true;
13955 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13956 &state->dst, &state->clip,
13957 min_scale, max_scale,
13958 can_position, true,
13962 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13963 struct drm_crtc_state *old_crtc_state)
13965 struct drm_device *dev = crtc->dev;
13966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13967 struct intel_crtc_state *old_intel_state =
13968 to_intel_crtc_state(old_crtc_state);
13969 bool modeset = needs_modeset(crtc->state);
13971 /* Perform vblank evasion around commit operation */
13972 intel_pipe_update_start(intel_crtc);
13977 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13978 intel_color_set_csc(crtc->state);
13979 intel_color_load_luts(crtc->state);
13982 if (to_intel_crtc_state(crtc->state)->update_pipe)
13983 intel_update_pipe_config(intel_crtc, old_intel_state);
13984 else if (INTEL_INFO(dev)->gen >= 9)
13985 skl_detach_scalers(intel_crtc);
13988 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13989 struct drm_crtc_state *old_crtc_state)
13991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13993 intel_pipe_update_end(intel_crtc);
13997 * intel_plane_destroy - destroy a plane
13998 * @plane: plane to destroy
14000 * Common destruction function for all types of planes (primary, cursor,
14003 void intel_plane_destroy(struct drm_plane *plane)
14005 struct intel_plane *intel_plane = to_intel_plane(plane);
14006 drm_plane_cleanup(plane);
14007 kfree(intel_plane);
14010 const struct drm_plane_funcs intel_plane_funcs = {
14011 .update_plane = drm_atomic_helper_update_plane,
14012 .disable_plane = drm_atomic_helper_disable_plane,
14013 .destroy = intel_plane_destroy,
14014 .set_property = drm_atomic_helper_plane_set_property,
14015 .atomic_get_property = intel_plane_atomic_get_property,
14016 .atomic_set_property = intel_plane_atomic_set_property,
14017 .atomic_duplicate_state = intel_plane_duplicate_state,
14018 .atomic_destroy_state = intel_plane_destroy_state,
14022 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14025 struct intel_plane *primary = NULL;
14026 struct intel_plane_state *state = NULL;
14027 const uint32_t *intel_primary_formats;
14028 unsigned int num_formats;
14031 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14035 state = intel_create_plane_state(&primary->base);
14038 primary->base.state = &state->base;
14040 primary->can_scale = false;
14041 primary->max_downscale = 1;
14042 if (INTEL_INFO(dev)->gen >= 9) {
14043 primary->can_scale = true;
14044 state->scaler_id = -1;
14046 primary->pipe = pipe;
14047 primary->plane = pipe;
14048 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14049 primary->check_plane = intel_check_primary_plane;
14050 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14051 primary->plane = !pipe;
14053 if (INTEL_INFO(dev)->gen >= 9) {
14054 intel_primary_formats = skl_primary_formats;
14055 num_formats = ARRAY_SIZE(skl_primary_formats);
14057 primary->update_plane = skylake_update_primary_plane;
14058 primary->disable_plane = skylake_disable_primary_plane;
14059 } else if (HAS_PCH_SPLIT(dev)) {
14060 intel_primary_formats = i965_primary_formats;
14061 num_formats = ARRAY_SIZE(i965_primary_formats);
14063 primary->update_plane = ironlake_update_primary_plane;
14064 primary->disable_plane = i9xx_disable_primary_plane;
14065 } else if (INTEL_INFO(dev)->gen >= 4) {
14066 intel_primary_formats = i965_primary_formats;
14067 num_formats = ARRAY_SIZE(i965_primary_formats);
14069 primary->update_plane = i9xx_update_primary_plane;
14070 primary->disable_plane = i9xx_disable_primary_plane;
14072 intel_primary_formats = i8xx_primary_formats;
14073 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14075 primary->update_plane = i9xx_update_primary_plane;
14076 primary->disable_plane = i9xx_disable_primary_plane;
14079 ret = drm_universal_plane_init(dev, &primary->base, 0,
14080 &intel_plane_funcs,
14081 intel_primary_formats, num_formats,
14082 DRM_PLANE_TYPE_PRIMARY, NULL);
14086 if (INTEL_INFO(dev)->gen >= 4)
14087 intel_create_rotation_property(dev, primary);
14089 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14091 return &primary->base;
14100 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14102 if (!dev->mode_config.rotation_property) {
14103 unsigned long flags = BIT(DRM_ROTATE_0) |
14104 BIT(DRM_ROTATE_180);
14106 if (INTEL_INFO(dev)->gen >= 9)
14107 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14109 dev->mode_config.rotation_property =
14110 drm_mode_create_rotation_property(dev, flags);
14112 if (dev->mode_config.rotation_property)
14113 drm_object_attach_property(&plane->base.base,
14114 dev->mode_config.rotation_property,
14115 plane->base.state->rotation);
14119 intel_check_cursor_plane(struct drm_plane *plane,
14120 struct intel_crtc_state *crtc_state,
14121 struct intel_plane_state *state)
14123 struct drm_crtc *crtc = crtc_state->base.crtc;
14124 struct drm_framebuffer *fb = state->base.fb;
14125 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14126 enum pipe pipe = to_intel_plane(plane)->pipe;
14130 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14131 &state->dst, &state->clip,
14132 DRM_PLANE_HELPER_NO_SCALING,
14133 DRM_PLANE_HELPER_NO_SCALING,
14134 true, true, &state->visible);
14138 /* if we want to turn off the cursor ignore width and height */
14142 /* Check for which cursor types we support */
14143 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14144 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14145 state->base.crtc_w, state->base.crtc_h);
14149 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14150 if (obj->base.size < stride * state->base.crtc_h) {
14151 DRM_DEBUG_KMS("buffer is too small\n");
14155 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14156 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14161 * There's something wrong with the cursor on CHV pipe C.
14162 * If it straddles the left edge of the screen then
14163 * moving it away from the edge or disabling it often
14164 * results in a pipe underrun, and often that can lead to
14165 * dead pipe (constant underrun reported, and it scans
14166 * out just a solid color). To recover from that, the
14167 * display power well must be turned off and on again.
14168 * Refuse the put the cursor into that compromised position.
14170 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14171 state->visible && state->base.crtc_x < 0) {
14172 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14180 intel_disable_cursor_plane(struct drm_plane *plane,
14181 struct drm_crtc *crtc)
14183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14185 intel_crtc->cursor_addr = 0;
14186 intel_crtc_update_cursor(crtc, NULL);
14190 intel_update_cursor_plane(struct drm_plane *plane,
14191 const struct intel_crtc_state *crtc_state,
14192 const struct intel_plane_state *state)
14194 struct drm_crtc *crtc = crtc_state->base.crtc;
14195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14196 struct drm_device *dev = plane->dev;
14197 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14202 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14203 addr = i915_gem_obj_ggtt_offset(obj);
14205 addr = obj->phys_handle->busaddr;
14207 intel_crtc->cursor_addr = addr;
14208 intel_crtc_update_cursor(crtc, state);
14211 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14214 struct intel_plane *cursor = NULL;
14215 struct intel_plane_state *state = NULL;
14218 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14222 state = intel_create_plane_state(&cursor->base);
14225 cursor->base.state = &state->base;
14227 cursor->can_scale = false;
14228 cursor->max_downscale = 1;
14229 cursor->pipe = pipe;
14230 cursor->plane = pipe;
14231 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14232 cursor->check_plane = intel_check_cursor_plane;
14233 cursor->update_plane = intel_update_cursor_plane;
14234 cursor->disable_plane = intel_disable_cursor_plane;
14236 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14237 &intel_plane_funcs,
14238 intel_cursor_formats,
14239 ARRAY_SIZE(intel_cursor_formats),
14240 DRM_PLANE_TYPE_CURSOR, NULL);
14244 if (INTEL_INFO(dev)->gen >= 4) {
14245 if (!dev->mode_config.rotation_property)
14246 dev->mode_config.rotation_property =
14247 drm_mode_create_rotation_property(dev,
14248 BIT(DRM_ROTATE_0) |
14249 BIT(DRM_ROTATE_180));
14250 if (dev->mode_config.rotation_property)
14251 drm_object_attach_property(&cursor->base.base,
14252 dev->mode_config.rotation_property,
14253 state->base.rotation);
14256 if (INTEL_INFO(dev)->gen >=9)
14257 state->scaler_id = -1;
14259 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14261 return &cursor->base;
14270 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14271 struct intel_crtc_state *crtc_state)
14274 struct intel_scaler *intel_scaler;
14275 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14277 for (i = 0; i < intel_crtc->num_scalers; i++) {
14278 intel_scaler = &scaler_state->scalers[i];
14279 intel_scaler->in_use = 0;
14280 intel_scaler->mode = PS_SCALER_MODE_DYN;
14283 scaler_state->scaler_id = -1;
14286 static void intel_crtc_init(struct drm_device *dev, int pipe)
14288 struct drm_i915_private *dev_priv = dev->dev_private;
14289 struct intel_crtc *intel_crtc;
14290 struct intel_crtc_state *crtc_state = NULL;
14291 struct drm_plane *primary = NULL;
14292 struct drm_plane *cursor = NULL;
14295 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14296 if (intel_crtc == NULL)
14299 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14302 intel_crtc->config = crtc_state;
14303 intel_crtc->base.state = &crtc_state->base;
14304 crtc_state->base.crtc = &intel_crtc->base;
14306 /* initialize shared scalers */
14307 if (INTEL_INFO(dev)->gen >= 9) {
14308 if (pipe == PIPE_C)
14309 intel_crtc->num_scalers = 1;
14311 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14313 skl_init_scalers(dev, intel_crtc, crtc_state);
14316 primary = intel_primary_plane_create(dev, pipe);
14320 cursor = intel_cursor_plane_create(dev, pipe);
14324 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14325 cursor, &intel_crtc_funcs, NULL);
14330 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14331 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14333 intel_crtc->pipe = pipe;
14334 intel_crtc->plane = pipe;
14335 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14336 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14337 intel_crtc->plane = !pipe;
14340 intel_crtc->cursor_base = ~0;
14341 intel_crtc->cursor_cntl = ~0;
14342 intel_crtc->cursor_size = ~0;
14344 intel_crtc->wm.cxsr_allowed = true;
14346 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14347 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14348 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14349 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14351 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14353 intel_color_init(&intel_crtc->base);
14355 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14360 drm_plane_cleanup(primary);
14362 drm_plane_cleanup(cursor);
14367 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14369 struct drm_encoder *encoder = connector->base.encoder;
14370 struct drm_device *dev = connector->base.dev;
14372 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14374 if (!encoder || WARN_ON(!encoder->crtc))
14375 return INVALID_PIPE;
14377 return to_intel_crtc(encoder->crtc)->pipe;
14380 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14381 struct drm_file *file)
14383 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14384 struct drm_crtc *drmmode_crtc;
14385 struct intel_crtc *crtc;
14387 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14389 if (!drmmode_crtc) {
14390 DRM_ERROR("no such CRTC id\n");
14394 crtc = to_intel_crtc(drmmode_crtc);
14395 pipe_from_crtc_id->pipe = crtc->pipe;
14400 static int intel_encoder_clones(struct intel_encoder *encoder)
14402 struct drm_device *dev = encoder->base.dev;
14403 struct intel_encoder *source_encoder;
14404 int index_mask = 0;
14407 for_each_intel_encoder(dev, source_encoder) {
14408 if (encoders_cloneable(encoder, source_encoder))
14409 index_mask |= (1 << entry);
14417 static bool has_edp_a(struct drm_device *dev)
14419 struct drm_i915_private *dev_priv = dev->dev_private;
14421 if (!IS_MOBILE(dev))
14424 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14427 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14433 static bool intel_crt_present(struct drm_device *dev)
14435 struct drm_i915_private *dev_priv = dev->dev_private;
14437 if (INTEL_INFO(dev)->gen >= 9)
14440 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14443 if (IS_CHERRYVIEW(dev))
14446 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14449 /* DDI E can't be used if DDI A requires 4 lanes */
14450 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14453 if (!dev_priv->vbt.int_crt_support)
14459 static void intel_setup_outputs(struct drm_device *dev)
14461 struct drm_i915_private *dev_priv = dev->dev_private;
14462 struct intel_encoder *encoder;
14463 bool dpd_is_edp = false;
14465 intel_lvds_init(dev);
14467 if (intel_crt_present(dev))
14468 intel_crt_init(dev);
14470 if (IS_BROXTON(dev)) {
14472 * FIXME: Broxton doesn't support port detection via the
14473 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14474 * detect the ports.
14476 intel_ddi_init(dev, PORT_A);
14477 intel_ddi_init(dev, PORT_B);
14478 intel_ddi_init(dev, PORT_C);
14480 intel_dsi_init(dev);
14481 } else if (HAS_DDI(dev)) {
14485 * Haswell uses DDI functions to detect digital outputs.
14486 * On SKL pre-D0 the strap isn't connected, so we assume
14489 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14490 /* WaIgnoreDDIAStrap: skl */
14491 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14492 intel_ddi_init(dev, PORT_A);
14494 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14496 found = I915_READ(SFUSE_STRAP);
14498 if (found & SFUSE_STRAP_DDIB_DETECTED)
14499 intel_ddi_init(dev, PORT_B);
14500 if (found & SFUSE_STRAP_DDIC_DETECTED)
14501 intel_ddi_init(dev, PORT_C);
14502 if (found & SFUSE_STRAP_DDID_DETECTED)
14503 intel_ddi_init(dev, PORT_D);
14505 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14507 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14508 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14509 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14510 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14511 intel_ddi_init(dev, PORT_E);
14513 } else if (HAS_PCH_SPLIT(dev)) {
14515 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14517 if (has_edp_a(dev))
14518 intel_dp_init(dev, DP_A, PORT_A);
14520 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14521 /* PCH SDVOB multiplex with HDMIB */
14522 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14524 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14525 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14526 intel_dp_init(dev, PCH_DP_B, PORT_B);
14529 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14530 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14532 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14533 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14535 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14536 intel_dp_init(dev, PCH_DP_C, PORT_C);
14538 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14539 intel_dp_init(dev, PCH_DP_D, PORT_D);
14540 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14542 * The DP_DETECTED bit is the latched state of the DDC
14543 * SDA pin at boot. However since eDP doesn't require DDC
14544 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14545 * eDP ports may have been muxed to an alternate function.
14546 * Thus we can't rely on the DP_DETECTED bit alone to detect
14547 * eDP ports. Consult the VBT as well as DP_DETECTED to
14548 * detect eDP ports.
14550 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14551 !intel_dp_is_edp(dev, PORT_B))
14552 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14553 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14554 intel_dp_is_edp(dev, PORT_B))
14555 intel_dp_init(dev, VLV_DP_B, PORT_B);
14557 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14558 !intel_dp_is_edp(dev, PORT_C))
14559 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14560 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14561 intel_dp_is_edp(dev, PORT_C))
14562 intel_dp_init(dev, VLV_DP_C, PORT_C);
14564 if (IS_CHERRYVIEW(dev)) {
14565 /* eDP not supported on port D, so don't check VBT */
14566 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14567 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14568 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14569 intel_dp_init(dev, CHV_DP_D, PORT_D);
14572 intel_dsi_init(dev);
14573 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14574 bool found = false;
14576 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14577 DRM_DEBUG_KMS("probing SDVOB\n");
14578 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14579 if (!found && IS_G4X(dev)) {
14580 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14581 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14584 if (!found && IS_G4X(dev))
14585 intel_dp_init(dev, DP_B, PORT_B);
14588 /* Before G4X SDVOC doesn't have its own detect register */
14590 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14591 DRM_DEBUG_KMS("probing SDVOC\n");
14592 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14595 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14598 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14599 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14602 intel_dp_init(dev, DP_C, PORT_C);
14606 (I915_READ(DP_D) & DP_DETECTED))
14607 intel_dp_init(dev, DP_D, PORT_D);
14608 } else if (IS_GEN2(dev))
14609 intel_dvo_init(dev);
14611 if (SUPPORTS_TV(dev))
14612 intel_tv_init(dev);
14614 intel_psr_init(dev);
14616 for_each_intel_encoder(dev, encoder) {
14617 encoder->base.possible_crtcs = encoder->crtc_mask;
14618 encoder->base.possible_clones =
14619 intel_encoder_clones(encoder);
14622 intel_init_pch_refclk(dev);
14624 drm_helper_move_panel_connectors_to_head(dev);
14627 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14629 struct drm_device *dev = fb->dev;
14630 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14632 drm_framebuffer_cleanup(fb);
14633 mutex_lock(&dev->struct_mutex);
14634 WARN_ON(!intel_fb->obj->framebuffer_references--);
14635 drm_gem_object_unreference(&intel_fb->obj->base);
14636 mutex_unlock(&dev->struct_mutex);
14640 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14641 struct drm_file *file,
14642 unsigned int *handle)
14644 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14645 struct drm_i915_gem_object *obj = intel_fb->obj;
14647 if (obj->userptr.mm) {
14648 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14652 return drm_gem_handle_create(file, &obj->base, handle);
14655 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14656 struct drm_file *file,
14657 unsigned flags, unsigned color,
14658 struct drm_clip_rect *clips,
14659 unsigned num_clips)
14661 struct drm_device *dev = fb->dev;
14662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14663 struct drm_i915_gem_object *obj = intel_fb->obj;
14665 mutex_lock(&dev->struct_mutex);
14666 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14667 mutex_unlock(&dev->struct_mutex);
14672 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14673 .destroy = intel_user_framebuffer_destroy,
14674 .create_handle = intel_user_framebuffer_create_handle,
14675 .dirty = intel_user_framebuffer_dirty,
14679 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14680 uint32_t pixel_format)
14682 u32 gen = INTEL_INFO(dev)->gen;
14685 int cpp = drm_format_plane_cpp(pixel_format, 0);
14687 /* "The stride in bytes must not exceed the of the size of 8K
14688 * pixels and 32K bytes."
14690 return min(8192 * cpp, 32768);
14691 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14693 } else if (gen >= 4) {
14694 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14698 } else if (gen >= 3) {
14699 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14704 /* XXX DSPC is limited to 4k tiled */
14709 static int intel_framebuffer_init(struct drm_device *dev,
14710 struct intel_framebuffer *intel_fb,
14711 struct drm_mode_fb_cmd2 *mode_cmd,
14712 struct drm_i915_gem_object *obj)
14714 struct drm_i915_private *dev_priv = to_i915(dev);
14715 unsigned int aligned_height;
14717 u32 pitch_limit, stride_alignment;
14719 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14721 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14722 /* Enforce that fb modifier and tiling mode match, but only for
14723 * X-tiled. This is needed for FBC. */
14724 if (!!(obj->tiling_mode == I915_TILING_X) !=
14725 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14726 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14730 if (obj->tiling_mode == I915_TILING_X)
14731 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14732 else if (obj->tiling_mode == I915_TILING_Y) {
14733 DRM_DEBUG("No Y tiling for legacy addfb\n");
14738 /* Passed in modifier sanity checking. */
14739 switch (mode_cmd->modifier[0]) {
14740 case I915_FORMAT_MOD_Y_TILED:
14741 case I915_FORMAT_MOD_Yf_TILED:
14742 if (INTEL_INFO(dev)->gen < 9) {
14743 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14744 mode_cmd->modifier[0]);
14747 case DRM_FORMAT_MOD_NONE:
14748 case I915_FORMAT_MOD_X_TILED:
14751 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14752 mode_cmd->modifier[0]);
14756 stride_alignment = intel_fb_stride_alignment(dev_priv,
14757 mode_cmd->modifier[0],
14758 mode_cmd->pixel_format);
14759 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14760 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14761 mode_cmd->pitches[0], stride_alignment);
14765 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14766 mode_cmd->pixel_format);
14767 if (mode_cmd->pitches[0] > pitch_limit) {
14768 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14769 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14770 "tiled" : "linear",
14771 mode_cmd->pitches[0], pitch_limit);
14775 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14776 mode_cmd->pitches[0] != obj->stride) {
14777 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14778 mode_cmd->pitches[0], obj->stride);
14782 /* Reject formats not supported by any plane early. */
14783 switch (mode_cmd->pixel_format) {
14784 case DRM_FORMAT_C8:
14785 case DRM_FORMAT_RGB565:
14786 case DRM_FORMAT_XRGB8888:
14787 case DRM_FORMAT_ARGB8888:
14789 case DRM_FORMAT_XRGB1555:
14790 if (INTEL_INFO(dev)->gen > 3) {
14791 DRM_DEBUG("unsupported pixel format: %s\n",
14792 drm_get_format_name(mode_cmd->pixel_format));
14796 case DRM_FORMAT_ABGR8888:
14797 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14798 INTEL_INFO(dev)->gen < 9) {
14799 DRM_DEBUG("unsupported pixel format: %s\n",
14800 drm_get_format_name(mode_cmd->pixel_format));
14804 case DRM_FORMAT_XBGR8888:
14805 case DRM_FORMAT_XRGB2101010:
14806 case DRM_FORMAT_XBGR2101010:
14807 if (INTEL_INFO(dev)->gen < 4) {
14808 DRM_DEBUG("unsupported pixel format: %s\n",
14809 drm_get_format_name(mode_cmd->pixel_format));
14813 case DRM_FORMAT_ABGR2101010:
14814 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14815 DRM_DEBUG("unsupported pixel format: %s\n",
14816 drm_get_format_name(mode_cmd->pixel_format));
14820 case DRM_FORMAT_YUYV:
14821 case DRM_FORMAT_UYVY:
14822 case DRM_FORMAT_YVYU:
14823 case DRM_FORMAT_VYUY:
14824 if (INTEL_INFO(dev)->gen < 5) {
14825 DRM_DEBUG("unsupported pixel format: %s\n",
14826 drm_get_format_name(mode_cmd->pixel_format));
14831 DRM_DEBUG("unsupported pixel format: %s\n",
14832 drm_get_format_name(mode_cmd->pixel_format));
14836 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14837 if (mode_cmd->offsets[0] != 0)
14840 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14841 mode_cmd->pixel_format,
14842 mode_cmd->modifier[0]);
14843 /* FIXME drm helper for size checks (especially planar formats)? */
14844 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14847 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14848 intel_fb->obj = obj;
14850 intel_fill_fb_info(dev_priv, &intel_fb->base);
14852 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14854 DRM_ERROR("framebuffer init failed %d\n", ret);
14858 intel_fb->obj->framebuffer_references++;
14863 static struct drm_framebuffer *
14864 intel_user_framebuffer_create(struct drm_device *dev,
14865 struct drm_file *filp,
14866 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14868 struct drm_framebuffer *fb;
14869 struct drm_i915_gem_object *obj;
14870 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14872 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14873 mode_cmd.handles[0]));
14874 if (&obj->base == NULL)
14875 return ERR_PTR(-ENOENT);
14877 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14879 drm_gem_object_unreference_unlocked(&obj->base);
14884 #ifndef CONFIG_DRM_FBDEV_EMULATION
14885 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14890 static const struct drm_mode_config_funcs intel_mode_funcs = {
14891 .fb_create = intel_user_framebuffer_create,
14892 .output_poll_changed = intel_fbdev_output_poll_changed,
14893 .atomic_check = intel_atomic_check,
14894 .atomic_commit = intel_atomic_commit,
14895 .atomic_state_alloc = intel_atomic_state_alloc,
14896 .atomic_state_clear = intel_atomic_state_clear,
14900 * intel_init_display_hooks - initialize the display modesetting hooks
14901 * @dev_priv: device private
14903 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14905 if (INTEL_INFO(dev_priv)->gen >= 9) {
14906 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14907 dev_priv->display.get_initial_plane_config =
14908 skylake_get_initial_plane_config;
14909 dev_priv->display.crtc_compute_clock =
14910 haswell_crtc_compute_clock;
14911 dev_priv->display.crtc_enable = haswell_crtc_enable;
14912 dev_priv->display.crtc_disable = haswell_crtc_disable;
14913 } else if (HAS_DDI(dev_priv)) {
14914 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14915 dev_priv->display.get_initial_plane_config =
14916 ironlake_get_initial_plane_config;
14917 dev_priv->display.crtc_compute_clock =
14918 haswell_crtc_compute_clock;
14919 dev_priv->display.crtc_enable = haswell_crtc_enable;
14920 dev_priv->display.crtc_disable = haswell_crtc_disable;
14921 } else if (HAS_PCH_SPLIT(dev_priv)) {
14922 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14923 dev_priv->display.get_initial_plane_config =
14924 ironlake_get_initial_plane_config;
14925 dev_priv->display.crtc_compute_clock =
14926 ironlake_crtc_compute_clock;
14927 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14928 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14929 } else if (IS_CHERRYVIEW(dev_priv)) {
14930 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14931 dev_priv->display.get_initial_plane_config =
14932 i9xx_get_initial_plane_config;
14933 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14934 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14935 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14936 } else if (IS_VALLEYVIEW(dev_priv)) {
14937 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14938 dev_priv->display.get_initial_plane_config =
14939 i9xx_get_initial_plane_config;
14940 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14941 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14942 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14943 } else if (IS_G4X(dev_priv)) {
14944 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14945 dev_priv->display.get_initial_plane_config =
14946 i9xx_get_initial_plane_config;
14947 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14948 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14949 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14950 } else if (IS_PINEVIEW(dev_priv)) {
14951 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14952 dev_priv->display.get_initial_plane_config =
14953 i9xx_get_initial_plane_config;
14954 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14955 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14956 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14957 } else if (!IS_GEN2(dev_priv)) {
14958 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14959 dev_priv->display.get_initial_plane_config =
14960 i9xx_get_initial_plane_config;
14961 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14962 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14963 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14965 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14966 dev_priv->display.get_initial_plane_config =
14967 i9xx_get_initial_plane_config;
14968 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14969 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14970 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14973 /* Returns the core display clock speed */
14974 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14975 dev_priv->display.get_display_clock_speed =
14976 skylake_get_display_clock_speed;
14977 else if (IS_BROXTON(dev_priv))
14978 dev_priv->display.get_display_clock_speed =
14979 broxton_get_display_clock_speed;
14980 else if (IS_BROADWELL(dev_priv))
14981 dev_priv->display.get_display_clock_speed =
14982 broadwell_get_display_clock_speed;
14983 else if (IS_HASWELL(dev_priv))
14984 dev_priv->display.get_display_clock_speed =
14985 haswell_get_display_clock_speed;
14986 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14987 dev_priv->display.get_display_clock_speed =
14988 valleyview_get_display_clock_speed;
14989 else if (IS_GEN5(dev_priv))
14990 dev_priv->display.get_display_clock_speed =
14991 ilk_get_display_clock_speed;
14992 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14993 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14994 dev_priv->display.get_display_clock_speed =
14995 i945_get_display_clock_speed;
14996 else if (IS_GM45(dev_priv))
14997 dev_priv->display.get_display_clock_speed =
14998 gm45_get_display_clock_speed;
14999 else if (IS_CRESTLINE(dev_priv))
15000 dev_priv->display.get_display_clock_speed =
15001 i965gm_get_display_clock_speed;
15002 else if (IS_PINEVIEW(dev_priv))
15003 dev_priv->display.get_display_clock_speed =
15004 pnv_get_display_clock_speed;
15005 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15006 dev_priv->display.get_display_clock_speed =
15007 g33_get_display_clock_speed;
15008 else if (IS_I915G(dev_priv))
15009 dev_priv->display.get_display_clock_speed =
15010 i915_get_display_clock_speed;
15011 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15012 dev_priv->display.get_display_clock_speed =
15013 i9xx_misc_get_display_clock_speed;
15014 else if (IS_I915GM(dev_priv))
15015 dev_priv->display.get_display_clock_speed =
15016 i915gm_get_display_clock_speed;
15017 else if (IS_I865G(dev_priv))
15018 dev_priv->display.get_display_clock_speed =
15019 i865_get_display_clock_speed;
15020 else if (IS_I85X(dev_priv))
15021 dev_priv->display.get_display_clock_speed =
15022 i85x_get_display_clock_speed;
15024 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15025 dev_priv->display.get_display_clock_speed =
15026 i830_get_display_clock_speed;
15029 if (IS_GEN5(dev_priv)) {
15030 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15031 } else if (IS_GEN6(dev_priv)) {
15032 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15033 } else if (IS_IVYBRIDGE(dev_priv)) {
15034 /* FIXME: detect B0+ stepping and use auto training */
15035 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15036 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15037 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15038 if (IS_BROADWELL(dev_priv)) {
15039 dev_priv->display.modeset_commit_cdclk =
15040 broadwell_modeset_commit_cdclk;
15041 dev_priv->display.modeset_calc_cdclk =
15042 broadwell_modeset_calc_cdclk;
15044 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15045 dev_priv->display.modeset_commit_cdclk =
15046 valleyview_modeset_commit_cdclk;
15047 dev_priv->display.modeset_calc_cdclk =
15048 valleyview_modeset_calc_cdclk;
15049 } else if (IS_BROXTON(dev_priv)) {
15050 dev_priv->display.modeset_commit_cdclk =
15051 broxton_modeset_commit_cdclk;
15052 dev_priv->display.modeset_calc_cdclk =
15053 broxton_modeset_calc_cdclk;
15056 switch (INTEL_INFO(dev_priv)->gen) {
15058 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15062 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15067 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15071 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15074 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15075 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15078 /* Drop through - unsupported since execlist only. */
15080 /* Default just returns -ENODEV to indicate unsupported */
15081 dev_priv->display.queue_flip = intel_default_queue_flip;
15086 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15087 * resume, or other times. This quirk makes sure that's the case for
15088 * affected systems.
15090 static void quirk_pipea_force(struct drm_device *dev)
15092 struct drm_i915_private *dev_priv = dev->dev_private;
15094 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15095 DRM_INFO("applying pipe a force quirk\n");
15098 static void quirk_pipeb_force(struct drm_device *dev)
15100 struct drm_i915_private *dev_priv = dev->dev_private;
15102 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15103 DRM_INFO("applying pipe b force quirk\n");
15107 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15109 static void quirk_ssc_force_disable(struct drm_device *dev)
15111 struct drm_i915_private *dev_priv = dev->dev_private;
15112 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15113 DRM_INFO("applying lvds SSC disable quirk\n");
15117 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15120 static void quirk_invert_brightness(struct drm_device *dev)
15122 struct drm_i915_private *dev_priv = dev->dev_private;
15123 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15124 DRM_INFO("applying inverted panel brightness quirk\n");
15127 /* Some VBT's incorrectly indicate no backlight is present */
15128 static void quirk_backlight_present(struct drm_device *dev)
15130 struct drm_i915_private *dev_priv = dev->dev_private;
15131 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15132 DRM_INFO("applying backlight present quirk\n");
15135 struct intel_quirk {
15137 int subsystem_vendor;
15138 int subsystem_device;
15139 void (*hook)(struct drm_device *dev);
15142 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15143 struct intel_dmi_quirk {
15144 void (*hook)(struct drm_device *dev);
15145 const struct dmi_system_id (*dmi_id_list)[];
15148 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15150 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15154 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15156 .dmi_id_list = &(const struct dmi_system_id[]) {
15158 .callback = intel_dmi_reverse_brightness,
15159 .ident = "NCR Corporation",
15160 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15161 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15164 { } /* terminating entry */
15166 .hook = quirk_invert_brightness,
15170 static struct intel_quirk intel_quirks[] = {
15171 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15172 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15174 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15175 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15177 /* 830 needs to leave pipe A & dpll A up */
15178 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15180 /* 830 needs to leave pipe B & dpll B up */
15181 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15183 /* Lenovo U160 cannot use SSC on LVDS */
15184 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15186 /* Sony Vaio Y cannot use SSC on LVDS */
15187 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15189 /* Acer Aspire 5734Z must invert backlight brightness */
15190 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15192 /* Acer/eMachines G725 */
15193 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15195 /* Acer/eMachines e725 */
15196 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15198 /* Acer/Packard Bell NCL20 */
15199 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15201 /* Acer Aspire 4736Z */
15202 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15204 /* Acer Aspire 5336 */
15205 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15207 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15208 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15210 /* Acer C720 Chromebook (Core i3 4005U) */
15211 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15213 /* Apple Macbook 2,1 (Core 2 T7400) */
15214 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15216 /* Apple Macbook 4,1 */
15217 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15219 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15220 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15222 /* HP Chromebook 14 (Celeron 2955U) */
15223 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15225 /* Dell Chromebook 11 */
15226 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15228 /* Dell Chromebook 11 (2015 version) */
15229 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15232 static void intel_init_quirks(struct drm_device *dev)
15234 struct pci_dev *d = dev->pdev;
15237 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15238 struct intel_quirk *q = &intel_quirks[i];
15240 if (d->device == q->device &&
15241 (d->subsystem_vendor == q->subsystem_vendor ||
15242 q->subsystem_vendor == PCI_ANY_ID) &&
15243 (d->subsystem_device == q->subsystem_device ||
15244 q->subsystem_device == PCI_ANY_ID))
15247 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15248 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15249 intel_dmi_quirks[i].hook(dev);
15253 /* Disable the VGA plane that we never use */
15254 static void i915_disable_vga(struct drm_device *dev)
15256 struct drm_i915_private *dev_priv = dev->dev_private;
15258 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15260 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15261 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15262 outb(SR01, VGA_SR_INDEX);
15263 sr1 = inb(VGA_SR_DATA);
15264 outb(sr1 | 1<<5, VGA_SR_DATA);
15265 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15268 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15269 POSTING_READ(vga_reg);
15272 void intel_modeset_init_hw(struct drm_device *dev)
15274 struct drm_i915_private *dev_priv = dev->dev_private;
15276 intel_update_cdclk(dev);
15278 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15280 intel_init_clock_gating(dev);
15281 intel_enable_gt_powersave(dev);
15285 * Calculate what we think the watermarks should be for the state we've read
15286 * out of the hardware and then immediately program those watermarks so that
15287 * we ensure the hardware settings match our internal state.
15289 * We can calculate what we think WM's should be by creating a duplicate of the
15290 * current state (which was constructed during hardware readout) and running it
15291 * through the atomic check code to calculate new watermark values in the
15294 static void sanitize_watermarks(struct drm_device *dev)
15296 struct drm_i915_private *dev_priv = to_i915(dev);
15297 struct drm_atomic_state *state;
15298 struct drm_crtc *crtc;
15299 struct drm_crtc_state *cstate;
15300 struct drm_modeset_acquire_ctx ctx;
15304 /* Only supported on platforms that use atomic watermark design */
15305 if (!dev_priv->display.optimize_watermarks)
15309 * We need to hold connection_mutex before calling duplicate_state so
15310 * that the connector loop is protected.
15312 drm_modeset_acquire_init(&ctx, 0);
15314 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15315 if (ret == -EDEADLK) {
15316 drm_modeset_backoff(&ctx);
15318 } else if (WARN_ON(ret)) {
15322 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15323 if (WARN_ON(IS_ERR(state)))
15327 * Hardware readout is the only time we don't want to calculate
15328 * intermediate watermarks (since we don't trust the current
15331 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15333 ret = intel_atomic_check(dev, state);
15336 * If we fail here, it means that the hardware appears to be
15337 * programmed in a way that shouldn't be possible, given our
15338 * understanding of watermark requirements. This might mean a
15339 * mistake in the hardware readout code or a mistake in the
15340 * watermark calculations for a given platform. Raise a WARN
15341 * so that this is noticeable.
15343 * If this actually happens, we'll have to just leave the
15344 * BIOS-programmed watermarks untouched and hope for the best.
15346 WARN(true, "Could not determine valid watermarks for inherited state\n");
15350 /* Write calculated watermark values back */
15351 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15352 for_each_crtc_in_state(state, crtc, cstate, i) {
15353 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15355 cs->wm.need_postvbl_update = true;
15356 dev_priv->display.optimize_watermarks(cs);
15359 drm_atomic_state_free(state);
15361 drm_modeset_drop_locks(&ctx);
15362 drm_modeset_acquire_fini(&ctx);
15365 void intel_modeset_init(struct drm_device *dev)
15367 struct drm_i915_private *dev_priv = to_i915(dev);
15368 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15371 struct intel_crtc *crtc;
15373 drm_mode_config_init(dev);
15375 dev->mode_config.min_width = 0;
15376 dev->mode_config.min_height = 0;
15378 dev->mode_config.preferred_depth = 24;
15379 dev->mode_config.prefer_shadow = 1;
15381 dev->mode_config.allow_fb_modifiers = true;
15383 dev->mode_config.funcs = &intel_mode_funcs;
15385 intel_init_quirks(dev);
15387 intel_init_pm(dev);
15389 if (INTEL_INFO(dev)->num_pipes == 0)
15393 * There may be no VBT; and if the BIOS enabled SSC we can
15394 * just keep using it to avoid unnecessary flicker. Whereas if the
15395 * BIOS isn't using it, don't assume it will work even if the VBT
15396 * indicates as much.
15398 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15399 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15402 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15403 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15404 bios_lvds_use_ssc ? "en" : "dis",
15405 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15406 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15410 if (IS_GEN2(dev)) {
15411 dev->mode_config.max_width = 2048;
15412 dev->mode_config.max_height = 2048;
15413 } else if (IS_GEN3(dev)) {
15414 dev->mode_config.max_width = 4096;
15415 dev->mode_config.max_height = 4096;
15417 dev->mode_config.max_width = 8192;
15418 dev->mode_config.max_height = 8192;
15421 if (IS_845G(dev) || IS_I865G(dev)) {
15422 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15423 dev->mode_config.cursor_height = 1023;
15424 } else if (IS_GEN2(dev)) {
15425 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15426 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15428 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15429 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15432 dev->mode_config.fb_base = ggtt->mappable_base;
15434 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15435 INTEL_INFO(dev)->num_pipes,
15436 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15438 for_each_pipe(dev_priv, pipe) {
15439 intel_crtc_init(dev, pipe);
15440 for_each_sprite(dev_priv, pipe, sprite) {
15441 ret = intel_plane_init(dev, pipe, sprite);
15443 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15444 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15448 intel_update_czclk(dev_priv);
15449 intel_update_cdclk(dev);
15451 intel_shared_dpll_init(dev);
15453 /* Just disable it once at startup */
15454 i915_disable_vga(dev);
15455 intel_setup_outputs(dev);
15457 drm_modeset_lock_all(dev);
15458 intel_modeset_setup_hw_state(dev);
15459 drm_modeset_unlock_all(dev);
15461 for_each_intel_crtc(dev, crtc) {
15462 struct intel_initial_plane_config plane_config = {};
15468 * Note that reserving the BIOS fb up front prevents us
15469 * from stuffing other stolen allocations like the ring
15470 * on top. This prevents some ugliness at boot time, and
15471 * can even allow for smooth boot transitions if the BIOS
15472 * fb is large enough for the active pipe configuration.
15474 dev_priv->display.get_initial_plane_config(crtc,
15478 * If the fb is shared between multiple heads, we'll
15479 * just get the first one.
15481 intel_find_initial_plane_obj(crtc, &plane_config);
15485 * Make sure hardware watermarks really match the state we read out.
15486 * Note that we need to do this after reconstructing the BIOS fb's
15487 * since the watermark calculation done here will use pstate->fb.
15489 sanitize_watermarks(dev);
15492 static void intel_enable_pipe_a(struct drm_device *dev)
15494 struct intel_connector *connector;
15495 struct drm_connector *crt = NULL;
15496 struct intel_load_detect_pipe load_detect_temp;
15497 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15499 /* We can't just switch on the pipe A, we need to set things up with a
15500 * proper mode and output configuration. As a gross hack, enable pipe A
15501 * by enabling the load detect pipe once. */
15502 for_each_intel_connector(dev, connector) {
15503 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15504 crt = &connector->base;
15512 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15513 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15517 intel_check_plane_mapping(struct intel_crtc *crtc)
15519 struct drm_device *dev = crtc->base.dev;
15520 struct drm_i915_private *dev_priv = dev->dev_private;
15523 if (INTEL_INFO(dev)->num_pipes == 1)
15526 val = I915_READ(DSPCNTR(!crtc->plane));
15528 if ((val & DISPLAY_PLANE_ENABLE) &&
15529 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15535 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15537 struct drm_device *dev = crtc->base.dev;
15538 struct intel_encoder *encoder;
15540 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15546 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15548 struct drm_device *dev = encoder->base.dev;
15549 struct intel_connector *connector;
15551 for_each_connector_on_encoder(dev, &encoder->base, connector)
15557 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15559 struct drm_device *dev = crtc->base.dev;
15560 struct drm_i915_private *dev_priv = dev->dev_private;
15561 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15563 /* Clear any frame start delays used for debugging left by the BIOS */
15564 if (!transcoder_is_dsi(cpu_transcoder)) {
15565 i915_reg_t reg = PIPECONF(cpu_transcoder);
15568 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15571 /* restore vblank interrupts to correct state */
15572 drm_crtc_vblank_reset(&crtc->base);
15573 if (crtc->active) {
15574 struct intel_plane *plane;
15576 drm_crtc_vblank_on(&crtc->base);
15578 /* Disable everything but the primary plane */
15579 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15580 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15583 plane->disable_plane(&plane->base, &crtc->base);
15587 /* We need to sanitize the plane -> pipe mapping first because this will
15588 * disable the crtc (and hence change the state) if it is wrong. Note
15589 * that gen4+ has a fixed plane -> pipe mapping. */
15590 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15593 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15594 crtc->base.base.id);
15596 /* Pipe has the wrong plane attached and the plane is active.
15597 * Temporarily change the plane mapping and disable everything
15599 plane = crtc->plane;
15600 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15601 crtc->plane = !plane;
15602 intel_crtc_disable_noatomic(&crtc->base);
15603 crtc->plane = plane;
15606 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15607 crtc->pipe == PIPE_A && !crtc->active) {
15608 /* BIOS forgot to enable pipe A, this mostly happens after
15609 * resume. Force-enable the pipe to fix this, the update_dpms
15610 * call below we restore the pipe to the right state, but leave
15611 * the required bits on. */
15612 intel_enable_pipe_a(dev);
15615 /* Adjust the state of the output pipe according to whether we
15616 * have active connectors/encoders. */
15617 if (crtc->active && !intel_crtc_has_encoders(crtc))
15618 intel_crtc_disable_noatomic(&crtc->base);
15620 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15622 * We start out with underrun reporting disabled to avoid races.
15623 * For correct bookkeeping mark this on active crtcs.
15625 * Also on gmch platforms we dont have any hardware bits to
15626 * disable the underrun reporting. Which means we need to start
15627 * out with underrun reporting disabled also on inactive pipes,
15628 * since otherwise we'll complain about the garbage we read when
15629 * e.g. coming up after runtime pm.
15631 * No protection against concurrent access is required - at
15632 * worst a fifo underrun happens which also sets this to false.
15634 crtc->cpu_fifo_underrun_disabled = true;
15635 crtc->pch_fifo_underrun_disabled = true;
15639 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15641 struct intel_connector *connector;
15642 struct drm_device *dev = encoder->base.dev;
15644 /* We need to check both for a crtc link (meaning that the
15645 * encoder is active and trying to read from a pipe) and the
15646 * pipe itself being active. */
15647 bool has_active_crtc = encoder->base.crtc &&
15648 to_intel_crtc(encoder->base.crtc)->active;
15650 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15651 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15652 encoder->base.base.id,
15653 encoder->base.name);
15655 /* Connector is active, but has no active pipe. This is
15656 * fallout from our resume register restoring. Disable
15657 * the encoder manually again. */
15658 if (encoder->base.crtc) {
15659 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15660 encoder->base.base.id,
15661 encoder->base.name);
15662 encoder->disable(encoder);
15663 if (encoder->post_disable)
15664 encoder->post_disable(encoder);
15666 encoder->base.crtc = NULL;
15668 /* Inconsistent output/port/pipe state happens presumably due to
15669 * a bug in one of the get_hw_state functions. Or someplace else
15670 * in our code, like the register restore mess on resume. Clamp
15671 * things to off as a safer default. */
15672 for_each_intel_connector(dev, connector) {
15673 if (connector->encoder != encoder)
15675 connector->base.dpms = DRM_MODE_DPMS_OFF;
15676 connector->base.encoder = NULL;
15679 /* Enabled encoders without active connectors will be fixed in
15680 * the crtc fixup. */
15683 void i915_redisable_vga_power_on(struct drm_device *dev)
15685 struct drm_i915_private *dev_priv = dev->dev_private;
15686 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15688 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15689 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15690 i915_disable_vga(dev);
15694 void i915_redisable_vga(struct drm_device *dev)
15696 struct drm_i915_private *dev_priv = dev->dev_private;
15698 /* This function can be called both from intel_modeset_setup_hw_state or
15699 * at a very early point in our resume sequence, where the power well
15700 * structures are not yet restored. Since this function is at a very
15701 * paranoid "someone might have enabled VGA while we were not looking"
15702 * level, just check if the power well is enabled instead of trying to
15703 * follow the "don't touch the power well if we don't need it" policy
15704 * the rest of the driver uses. */
15705 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15708 i915_redisable_vga_power_on(dev);
15710 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15713 static bool primary_get_hw_state(struct intel_plane *plane)
15715 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15717 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15720 /* FIXME read out full plane state for all planes */
15721 static void readout_plane_state(struct intel_crtc *crtc)
15723 struct drm_plane *primary = crtc->base.primary;
15724 struct intel_plane_state *plane_state =
15725 to_intel_plane_state(primary->state);
15727 plane_state->visible = crtc->active &&
15728 primary_get_hw_state(to_intel_plane(primary));
15730 if (plane_state->visible)
15731 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15734 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15736 struct drm_i915_private *dev_priv = dev->dev_private;
15738 struct intel_crtc *crtc;
15739 struct intel_encoder *encoder;
15740 struct intel_connector *connector;
15743 dev_priv->active_crtcs = 0;
15745 for_each_intel_crtc(dev, crtc) {
15746 struct intel_crtc_state *crtc_state = crtc->config;
15749 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15750 memset(crtc_state, 0, sizeof(*crtc_state));
15751 crtc_state->base.crtc = &crtc->base;
15753 crtc_state->base.active = crtc_state->base.enable =
15754 dev_priv->display.get_pipe_config(crtc, crtc_state);
15756 crtc->base.enabled = crtc_state->base.enable;
15757 crtc->active = crtc_state->base.active;
15759 if (crtc_state->base.active) {
15760 dev_priv->active_crtcs |= 1 << crtc->pipe;
15762 if (IS_BROADWELL(dev_priv)) {
15763 pixclk = ilk_pipe_pixel_rate(crtc_state);
15765 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15766 if (crtc_state->ips_enabled)
15767 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15768 } else if (IS_VALLEYVIEW(dev_priv) ||
15769 IS_CHERRYVIEW(dev_priv) ||
15770 IS_BROXTON(dev_priv))
15771 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15773 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15776 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15778 readout_plane_state(crtc);
15780 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15781 crtc->base.base.id,
15782 crtc->active ? "enabled" : "disabled");
15785 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15786 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15788 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15789 &pll->config.hw_state);
15790 pll->config.crtc_mask = 0;
15791 for_each_intel_crtc(dev, crtc) {
15792 if (crtc->active && crtc->config->shared_dpll == pll)
15793 pll->config.crtc_mask |= 1 << crtc->pipe;
15795 pll->active_mask = pll->config.crtc_mask;
15797 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15798 pll->name, pll->config.crtc_mask, pll->on);
15801 for_each_intel_encoder(dev, encoder) {
15804 if (encoder->get_hw_state(encoder, &pipe)) {
15805 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15806 encoder->base.crtc = &crtc->base;
15807 encoder->get_config(encoder, crtc->config);
15809 encoder->base.crtc = NULL;
15812 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15813 encoder->base.base.id,
15814 encoder->base.name,
15815 encoder->base.crtc ? "enabled" : "disabled",
15819 for_each_intel_connector(dev, connector) {
15820 if (connector->get_hw_state(connector)) {
15821 connector->base.dpms = DRM_MODE_DPMS_ON;
15823 encoder = connector->encoder;
15824 connector->base.encoder = &encoder->base;
15826 if (encoder->base.crtc &&
15827 encoder->base.crtc->state->active) {
15829 * This has to be done during hardware readout
15830 * because anything calling .crtc_disable may
15831 * rely on the connector_mask being accurate.
15833 encoder->base.crtc->state->connector_mask |=
15834 1 << drm_connector_index(&connector->base);
15835 encoder->base.crtc->state->encoder_mask |=
15836 1 << drm_encoder_index(&encoder->base);
15840 connector->base.dpms = DRM_MODE_DPMS_OFF;
15841 connector->base.encoder = NULL;
15843 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15844 connector->base.base.id,
15845 connector->base.name,
15846 connector->base.encoder ? "enabled" : "disabled");
15849 for_each_intel_crtc(dev, crtc) {
15850 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15852 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15853 if (crtc->base.state->active) {
15854 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15855 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15856 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15859 * The initial mode needs to be set in order to keep
15860 * the atomic core happy. It wants a valid mode if the
15861 * crtc's enabled, so we do the above call.
15863 * At this point some state updated by the connectors
15864 * in their ->detect() callback has not run yet, so
15865 * no recalculation can be done yet.
15867 * Even if we could do a recalculation and modeset
15868 * right now it would cause a double modeset if
15869 * fbdev or userspace chooses a different initial mode.
15871 * If that happens, someone indicated they wanted a
15872 * mode change, which means it's safe to do a full
15875 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15877 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15878 update_scanline_offset(crtc);
15881 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15885 /* Scan out the current hw modeset state,
15886 * and sanitizes it to the current state
15889 intel_modeset_setup_hw_state(struct drm_device *dev)
15891 struct drm_i915_private *dev_priv = dev->dev_private;
15893 struct intel_crtc *crtc;
15894 struct intel_encoder *encoder;
15897 intel_modeset_readout_hw_state(dev);
15899 /* HW state is read out, now we need to sanitize this mess. */
15900 for_each_intel_encoder(dev, encoder) {
15901 intel_sanitize_encoder(encoder);
15904 for_each_pipe(dev_priv, pipe) {
15905 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15906 intel_sanitize_crtc(crtc);
15907 intel_dump_pipe_config(crtc, crtc->config,
15908 "[setup_hw_state]");
15911 intel_modeset_update_connector_atomic_state(dev);
15913 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15914 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15916 if (!pll->on || pll->active_mask)
15919 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15921 pll->funcs.disable(dev_priv, pll);
15925 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15926 vlv_wm_get_hw_state(dev);
15927 else if (IS_GEN9(dev))
15928 skl_wm_get_hw_state(dev);
15929 else if (HAS_PCH_SPLIT(dev))
15930 ilk_wm_get_hw_state(dev);
15932 for_each_intel_crtc(dev, crtc) {
15933 unsigned long put_domains;
15935 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15936 if (WARN_ON(put_domains))
15937 modeset_put_power_domains(dev_priv, put_domains);
15939 intel_display_set_init_power(dev_priv, false);
15941 intel_fbc_init_pipe_state(dev_priv);
15944 void intel_display_resume(struct drm_device *dev)
15946 struct drm_i915_private *dev_priv = to_i915(dev);
15947 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15948 struct drm_modeset_acquire_ctx ctx;
15950 bool setup = false;
15952 dev_priv->modeset_restore_state = NULL;
15955 * This is a cludge because with real atomic modeset mode_config.mutex
15956 * won't be taken. Unfortunately some probed state like
15957 * audio_codec_enable is still protected by mode_config.mutex, so lock
15960 mutex_lock(&dev->mode_config.mutex);
15961 drm_modeset_acquire_init(&ctx, 0);
15964 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15966 if (ret == 0 && !setup) {
15969 intel_modeset_setup_hw_state(dev);
15970 i915_redisable_vga(dev);
15973 if (ret == 0 && state) {
15974 struct drm_crtc_state *crtc_state;
15975 struct drm_crtc *crtc;
15978 state->acquire_ctx = &ctx;
15980 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15982 * Force recalculation even if we restore
15983 * current state. With fast modeset this may not result
15984 * in a modeset when the state is compatible.
15986 crtc_state->mode_changed = true;
15989 ret = drm_atomic_commit(state);
15992 if (ret == -EDEADLK) {
15993 drm_modeset_backoff(&ctx);
15997 drm_modeset_drop_locks(&ctx);
15998 drm_modeset_acquire_fini(&ctx);
15999 mutex_unlock(&dev->mode_config.mutex);
16002 DRM_ERROR("Restoring old state failed with %i\n", ret);
16003 drm_atomic_state_free(state);
16007 void intel_modeset_gem_init(struct drm_device *dev)
16009 struct drm_crtc *c;
16010 struct drm_i915_gem_object *obj;
16013 intel_init_gt_powersave(dev);
16015 intel_modeset_init_hw(dev);
16017 intel_setup_overlay(dev);
16020 * Make sure any fbs we allocated at startup are properly
16021 * pinned & fenced. When we do the allocation it's too early
16024 for_each_crtc(dev, c) {
16025 obj = intel_fb_obj(c->primary->fb);
16029 mutex_lock(&dev->struct_mutex);
16030 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16031 c->primary->state->rotation);
16032 mutex_unlock(&dev->struct_mutex);
16034 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16035 to_intel_crtc(c)->pipe);
16036 drm_framebuffer_unreference(c->primary->fb);
16037 c->primary->fb = NULL;
16038 c->primary->crtc = c->primary->state->crtc = NULL;
16039 update_state_fb(c->primary);
16040 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16044 intel_backlight_register(dev);
16047 void intel_connector_unregister(struct intel_connector *intel_connector)
16049 struct drm_connector *connector = &intel_connector->base;
16051 intel_panel_destroy_backlight(connector);
16052 drm_connector_unregister(connector);
16055 void intel_modeset_cleanup(struct drm_device *dev)
16057 struct drm_i915_private *dev_priv = dev->dev_private;
16058 struct intel_connector *connector;
16060 intel_disable_gt_powersave(dev);
16062 intel_backlight_unregister(dev);
16065 * Interrupts and polling as the first thing to avoid creating havoc.
16066 * Too much stuff here (turning of connectors, ...) would
16067 * experience fancy races otherwise.
16069 intel_irq_uninstall(dev_priv);
16072 * Due to the hpd irq storm handling the hotplug work can re-arm the
16073 * poll handlers. Hence disable polling after hpd handling is shut down.
16075 drm_kms_helper_poll_fini(dev);
16077 intel_unregister_dsm_handler();
16079 intel_fbc_global_disable(dev_priv);
16081 /* flush any delayed tasks or pending work */
16082 flush_scheduled_work();
16084 /* destroy the backlight and sysfs files before encoders/connectors */
16085 for_each_intel_connector(dev, connector)
16086 connector->unregister(connector);
16088 drm_mode_config_cleanup(dev);
16090 intel_cleanup_overlay(dev);
16092 intel_cleanup_gt_powersave(dev);
16094 intel_teardown_gmbus(dev);
16098 * Return which encoder is currently attached for connector.
16100 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16102 return &intel_attached_encoder(connector)->base;
16105 void intel_connector_attach_encoder(struct intel_connector *connector,
16106 struct intel_encoder *encoder)
16108 connector->encoder = encoder;
16109 drm_mode_connector_attach_encoder(&connector->base,
16114 * set vga decode state - true == enable VGA decode
16116 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16118 struct drm_i915_private *dev_priv = dev->dev_private;
16119 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16122 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16123 DRM_ERROR("failed to read control word\n");
16127 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16131 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16133 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16135 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16136 DRM_ERROR("failed to write control word\n");
16143 struct intel_display_error_state {
16145 u32 power_well_driver;
16147 int num_transcoders;
16149 struct intel_cursor_error_state {
16154 } cursor[I915_MAX_PIPES];
16156 struct intel_pipe_error_state {
16157 bool power_domain_on;
16160 } pipe[I915_MAX_PIPES];
16162 struct intel_plane_error_state {
16170 } plane[I915_MAX_PIPES];
16172 struct intel_transcoder_error_state {
16173 bool power_domain_on;
16174 enum transcoder cpu_transcoder;
16187 struct intel_display_error_state *
16188 intel_display_capture_error_state(struct drm_device *dev)
16190 struct drm_i915_private *dev_priv = dev->dev_private;
16191 struct intel_display_error_state *error;
16192 int transcoders[] = {
16200 if (INTEL_INFO(dev)->num_pipes == 0)
16203 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16208 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16210 for_each_pipe(dev_priv, i) {
16211 error->pipe[i].power_domain_on =
16212 __intel_display_power_is_enabled(dev_priv,
16213 POWER_DOMAIN_PIPE(i));
16214 if (!error->pipe[i].power_domain_on)
16217 error->cursor[i].control = I915_READ(CURCNTR(i));
16218 error->cursor[i].position = I915_READ(CURPOS(i));
16219 error->cursor[i].base = I915_READ(CURBASE(i));
16221 error->plane[i].control = I915_READ(DSPCNTR(i));
16222 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16223 if (INTEL_INFO(dev)->gen <= 3) {
16224 error->plane[i].size = I915_READ(DSPSIZE(i));
16225 error->plane[i].pos = I915_READ(DSPPOS(i));
16227 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16228 error->plane[i].addr = I915_READ(DSPADDR(i));
16229 if (INTEL_INFO(dev)->gen >= 4) {
16230 error->plane[i].surface = I915_READ(DSPSURF(i));
16231 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16234 error->pipe[i].source = I915_READ(PIPESRC(i));
16236 if (HAS_GMCH_DISPLAY(dev))
16237 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16240 /* Note: this does not include DSI transcoders. */
16241 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16242 if (HAS_DDI(dev_priv))
16243 error->num_transcoders++; /* Account for eDP. */
16245 for (i = 0; i < error->num_transcoders; i++) {
16246 enum transcoder cpu_transcoder = transcoders[i];
16248 error->transcoder[i].power_domain_on =
16249 __intel_display_power_is_enabled(dev_priv,
16250 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16251 if (!error->transcoder[i].power_domain_on)
16254 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16256 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16257 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16258 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16259 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16260 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16261 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16262 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16268 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16271 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16272 struct drm_device *dev,
16273 struct intel_display_error_state *error)
16275 struct drm_i915_private *dev_priv = dev->dev_private;
16281 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16282 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16283 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16284 error->power_well_driver);
16285 for_each_pipe(dev_priv, i) {
16286 err_printf(m, "Pipe [%d]:\n", i);
16287 err_printf(m, " Power: %s\n",
16288 onoff(error->pipe[i].power_domain_on));
16289 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16290 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16292 err_printf(m, "Plane [%d]:\n", i);
16293 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16294 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16295 if (INTEL_INFO(dev)->gen <= 3) {
16296 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16297 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16299 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16300 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16301 if (INTEL_INFO(dev)->gen >= 4) {
16302 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16303 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16306 err_printf(m, "Cursor [%d]:\n", i);
16307 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16308 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16309 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16312 for (i = 0; i < error->num_transcoders; i++) {
16313 err_printf(m, "CPU transcoder: %s\n",
16314 transcoder_name(error->transcoder[i].cpu_transcoder));
16315 err_printf(m, " Power: %s\n",
16316 onoff(error->transcoder[i].power_domain_on));
16317 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16318 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16319 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16320 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16321 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16322 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16323 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);