drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 646                                                 int refclk)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         const intel_limit_t *limit;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100000)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100000)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc, refclk);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_device *dev,
 774                                const intel_limit_t *limit,
 775                                const intel_clock_t *clock)
 776 {
 777         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 778                 INTELPllInvalid ("p1 out of range\n");
 779         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 780                 INTELPllInvalid ("p out of range\n");
 781         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 782                 INTELPllInvalid ("m2 out of range\n");
 783         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 784                 INTELPllInvalid ("m1 out of range\n");
 785         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 786                 INTELPllInvalid ("m1 <= m2\n");
 787         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 788                 INTELPllInvalid ("m out of range\n");
 789         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 790                 INTELPllInvalid ("n out of range\n");
 791         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 792                 INTELPllInvalid ("vco out of range\n");
 793         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 794          * connector, etc., rather than just a single range.
 795          */
 796         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 797                 INTELPllInvalid ("dot out of range\n");
 798
 799         return true;
 800 }
 801
 802 static bool
 803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 804                     int target, int refclk, intel_clock_t *best_clock)
 805
 806 {
 807         struct drm_device *dev = crtc->dev;
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         intel_clock_t clock;
 810         int err = target;
 811
 812         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 813             (I915_READ(LVDS)) != 0) {
 814                 /*
 815                  * For LVDS, if the panel is on, just rely on its current
 816                  * settings for dual-channel.  We haven't figured out how to
 817                  * reliably set up different single/dual channel state, if we
 818                  * even can.
 819                  */
 820                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 821                     LVDS_CLKB_POWER_UP)
 822                         clock.p2 = limit->p2.p2_fast;
 823                 else
 824                         clock.p2 = limit->p2.p2_slow;
 825         } else {
 826                 if (target < limit->p2.dot_limit)
 827                         clock.p2 = limit->p2.p2_slow;
 828                 else
 829                         clock.p2 = limit->p2.p2_fast;
 830         }
 831
 832         memset (best_clock, 0, sizeof (*best_clock));
 833
 834         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 835              clock.m1++) {
 836                 for (clock.m2 = limit->m2.min;
 837                      clock.m2 <= limit->m2.max; clock.m2++) {
 838                         /* m1 is always 0 in Pineview */
 839                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 840                                 break;
 841                         for (clock.n = limit->n.min;
 842                              clock.n <= limit->n.max; clock.n++) {
 843                                 for (clock.p1 = limit->p1.min;
 844                                         clock.p1 <= limit->p1.max; clock.p1++) {
 845                                         int this_err;
 846
 847                                         intel_clock(dev, refclk, &clock);
 848                                         if (!intel_PLL_is_valid(dev, limit,
 849                                                                 &clock))
 850                                                 continue;
 851
 852                                         this_err = abs(clock.dot - target);
 853                                         if (this_err < err) {
 854                                                 *best_clock = clock;
 855                                                 err = this_err;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861
 862         return (err != target);
 863 }
 864
 865 static bool
 866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 867                         int target, int refclk, intel_clock_t *best_clock)
 868 {
 869         struct drm_device *dev = crtc->dev;
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         intel_clock_t clock;
 872         int max_n;
 873         bool found;
 874         /* approximately equals target * 0.00585 */
 875         int err_most = (target >> 8) + (target >> 9);
 876         found = false;
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 int lvds_reg;
 880
 881                 if (HAS_PCH_SPLIT(dev))
 882                         lvds_reg = PCH_LVDS;
 883                 else
 884                         lvds_reg = LVDS;
 885                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 886                     LVDS_CLKB_POWER_UP)
 887                         clock.p2 = limit->p2.p2_fast;
 888                 else
 889                         clock.p2 = limit->p2.p2_slow;
 890         } else {
 891                 if (target < limit->p2.dot_limit)
 892                         clock.p2 = limit->p2.p2_slow;
 893                 else
 894                         clock.p2 = limit->p2.p2_fast;
 895         }
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         max_n = limit->n.max;
 899         /* based on hardware requirement, prefer smaller n to precision */
 900         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 901                 /* based on hardware requirement, prefere larger m1,m2 */
 902                 for (clock.m1 = limit->m1.max;
 903                      clock.m1 >= limit->m1.min; clock.m1--) {
 904                         for (clock.m2 = limit->m2.max;
 905                              clock.m2 >= limit->m2.min; clock.m2--) {
 906                                 for (clock.p1 = limit->p1.max;
 907                                      clock.p1 >= limit->p1.min; clock.p1--) {
 908                                         int this_err;
 909
 910                                         intel_clock(dev, refclk, &clock);
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         this_err = abs(clock.dot - target);
 916                                         if (this_err < err_most) {
 917                                                 *best_clock = clock;
 918                                                 err_most = this_err;
 919                                                 max_n = clock.n;
 920                                                 found = true;
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926         return found;
 927 }
 928
 929 static bool
 930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 931                            int target, int refclk, intel_clock_t *best_clock)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         intel_clock_t clock;
 935
 936         if (target < 200000) {
 937                 clock.n = 1;
 938                 clock.p1 = 2;
 939                 clock.p2 = 10;
 940                 clock.m1 = 12;
 941                 clock.m2 = 9;
 942         } else {
 943                 clock.n = 2;
 944                 clock.p1 = 1;
 945                 clock.p2 = 10;
 946                 clock.m1 = 14;
 947                 clock.m2 = 8;
 948         }
 949         intel_clock(dev, refclk, &clock);
 950         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 951         return true;
 952 }
 953
 954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 955 static bool
 956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 957                       int target, int refclk, intel_clock_t *best_clock)
 958 {
 959         intel_clock_t clock;
 960         if (target < 200000) {
 961                 clock.p1 = 2;
 962                 clock.p2 = 10;
 963                 clock.n = 2;
 964                 clock.m1 = 23;
 965                 clock.m2 = 8;
 966         } else {
 967                 clock.p1 = 1;
 968                 clock.p2 = 10;
 969                 clock.n = 1;
 970                 clock.m1 = 14;
 971                 clock.m2 = 2;
 972         }
 973         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 974         clock.p = (clock.p1 * clock.p2);
 975         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 976         clock.vco = 0;
 977         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 978         return true;
 979 }
 980
 981 /**
 982  * intel_wait_for_vblank - wait for vblank on a given pipe
 983  * @dev: drm device
 984  * @pipe: pipe to wait for
 985  *
 986  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 987  * mode setting code.
 988  */
 989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 993
 994         /* Clear existing vblank status. Note this will clear any other
 995          * sticky status fields as well.
 996          *
 997          * This races with i915_driver_irq_handler() with the result
 998          * that either function could miss a vblank event.  Here it is not
 999          * fatal, as we will either wait upon the next vblank interrupt or
1000          * timeout.  Generally speaking intel_wait_for_vblank() is only
1001          * called during modeset at which time the GPU should be idle and
1002          * should *not* be performing page flips and thus not waiting on
1003          * vblanks...
1004          * Currently, the result of us stealing a vblank from the irq
1005          * handler is that a single frame will be skipped during swapbuffers.
1006          */
1007         I915_WRITE(pipestat_reg,
1008                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010         /* Wait for vblank interrupt bit to set */
1011         if (wait_for(I915_READ(pipestat_reg) &
1012                      PIPE_VBLANK_INTERRUPT_STATUS,
1013                      50))
1014                 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018  * intel_wait_for_pipe_off - wait for pipe to turn off
1019  * @dev: drm device
1020  * @pipe: pipe to wait for
1021  *
1022  * After disabling a pipe, we can't wait for vblank in the usual way,
1023  * spinning on the vblank interrupt status bit, since we won't actually
1024  * see an interrupt when the pipe is disabled.
1025  *
1026  * On Gen4 and above:
1027  *   wait for the pipe register state bit to turn off
1028  *
1029  * Otherwise:
1030  *   wait for the display line value to settle (it usually
1031  *   ends up stopping at the start of the next frame).
1032  *
1033  */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         if (INTEL_INFO(dev)->gen >= 4) {
1039                 int reg = PIPECONF(pipe);
1040
1041                 /* Wait for the Pipe State to go off */
1042                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043                              100))
1044                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045         } else {
1046                 u32 last_line;
1047                 int reg = PIPEDSL(pipe);
1048                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050                 /* Wait for the display line to settle */
1051                 do {
1052                         last_line = I915_READ(reg) & DSL_LINEMASK;
1053                         mdelay(5);
1054                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055                          time_after(timeout, jiffies));
1056                 if (time_after(jiffies, timeout))
1057                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058         }
1059 }
1060
1061 static const char *state_string(bool enabled)
1062 {
1063         return enabled ? "on" : "off";
1064 }
1065
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private *dev_priv,
1068                        enum pipe pipe, bool state)
1069 {
1070         int reg;
1071         u32 val;
1072         bool cur_state;
1073
1074         reg = DPLL(pipe);
1075         val = I915_READ(reg);
1076         cur_state = !!(val & DPLL_VCO_ENABLE);
1077         WARN(cur_state != state,
1078              "PLL state assertion failure (expected %s, current %s)\n",
1079              state_string(state), state_string(cur_state));
1080 }
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
1084 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1085                                   enum pipe pipe)
1086 {
1087         int pp_reg, lvds_reg;
1088         u32 val;
1089         enum pipe panel_pipe = PIPE_A;
1090         bool locked = locked;
1091
1092         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1093                 pp_reg = PCH_PP_CONTROL;
1094                 lvds_reg = PCH_LVDS;
1095         } else {
1096                 pp_reg = PP_CONTROL;
1097                 lvds_reg = LVDS;
1098         }
1099
1100         val = I915_READ(pp_reg);
1101         if (!(val & PANEL_POWER_ON) ||
1102             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1103                 locked = false;
1104
1105         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1106                 panel_pipe = PIPE_B;
1107
1108         WARN(panel_pipe == pipe && locked,
1109              "panel assertion failure, pipe %c regs locked\n",
1110              pipe ? 'B' : 'A');
1111 }
1112
1113 static void assert_pipe(struct drm_i915_private *dev_priv,
1114                         enum pipe pipe, bool state)
1115 {
1116         int reg;
1117         u32 val;
1118         bool cur_state;
1119
1120         reg = PIPECONF(pipe);
1121         val = I915_READ(reg);
1122         cur_state = !!(val & PIPECONF_ENABLE);
1123         WARN(cur_state != state,
1124              "pipe %c assertion failure (expected %s, current %s)\n",
1125              pipe ? 'B' : 'A', state_string(state), state_string(cur_state));
1126 }
1127 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1128 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1129
1130 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1131                                  enum plane plane)
1132 {
1133         int reg;
1134         u32 val;
1135
1136         reg = DSPCNTR(plane);
1137         val = I915_READ(reg);
1138         WARN(!(val & DISPLAY_PLANE_ENABLE),
1139              "plane %c assertion failure, should be active but is disabled\n",
1140              plane ? 'B' : 'A');
1141 }
1142
1143 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1144                                    enum pipe pipe)
1145 {
1146         int reg, i;
1147         u32 val;
1148         int cur_pipe;
1149
1150         /* Need to check both planes against the pipe */
1151         for (i = 0; i < 2; i++) {
1152                 reg = DSPCNTR(i);
1153                 val = I915_READ(reg);
1154                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1155                         DISPPLANE_SEL_PIPE_SHIFT;
1156                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1157                      "plane %d assertion failure, should be off on pipe %c but is still active\n",
1158                      i, pipe ? 'B' : 'A');
1159         }
1160 }
1161
1162 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1163 {
1164         u32 val;
1165         bool enabled;
1166
1167         val = I915_READ(PCH_DREF_CONTROL);
1168         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1169                             DREF_SUPERSPREAD_SOURCE_MASK));
1170         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1171 }
1172
1173 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1174                                        enum pipe pipe)
1175 {
1176         int reg;
1177         u32 val;
1178         bool enabled;
1179
1180         reg = TRANSCONF(pipe);
1181         val = I915_READ(reg);
1182         enabled = !!(val & TRANS_ENABLE);
1183         WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", pipe ? 'B' :'A');
1184 }
1185
1186 /**
1187  * intel_enable_pll - enable a PLL
1188  * @dev_priv: i915 private structure
1189  * @pipe: pipe PLL to enable
1190  *
1191  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1192  * make sure the PLL reg is writable first though, since the panel write
1193  * protect mechanism may be enabled.
1194  *
1195  * Note!  This is for pre-ILK only.
1196  */
1197 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1198 {
1199         int reg;
1200         u32 val;
1201
1202         /* No really, not for ILK+ */
1203         BUG_ON(dev_priv->info->gen >= 5);
1204
1205         /* PLL is protected by panel, make sure we can write it */
1206         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1207                 assert_panel_unlocked(dev_priv, pipe);
1208
1209         reg = DPLL(pipe);
1210         val = I915_READ(reg);
1211         val |= DPLL_VCO_ENABLE;
1212
1213         /* We do this three times for luck */
1214         I915_WRITE(reg, val);
1215         POSTING_READ(reg);
1216         udelay(150); /* wait for warmup */
1217         I915_WRITE(reg, val);
1218         POSTING_READ(reg);
1219         udelay(150); /* wait for warmup */
1220         I915_WRITE(reg, val);
1221         POSTING_READ(reg);
1222         udelay(150); /* wait for warmup */
1223 }
1224
1225 /**
1226  * intel_disable_pll - disable a PLL
1227  * @dev_priv: i915 private structure
1228  * @pipe: pipe PLL to disable
1229  *
1230  * Disable the PLL for @pipe, making sure the pipe is off first.
1231  *
1232  * Note!  This is for pre-ILK only.
1233  */
1234 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1235 {
1236         int reg;
1237         u32 val;
1238
1239         /* Don't disable pipe A or pipe A PLLs if needed */
1240         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1241                 return;
1242
1243         /* Make sure the pipe isn't still relying on us */
1244         assert_pipe_disabled(dev_priv, pipe);
1245
1246         reg = DPLL(pipe);
1247         val = I915_READ(reg);
1248         val &= ~DPLL_VCO_ENABLE;
1249         I915_WRITE(reg, val);
1250         POSTING_READ(reg);
1251 }
1252
1253 /**
1254  * intel_enable_pch_pll - enable PCH PLL
1255  * @dev_priv: i915 private structure
1256  * @pipe: pipe PLL to enable
1257  *
1258  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1259  * drives the transcoder clock.
1260  */
1261 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1262                                  enum pipe pipe)
1263 {
1264         int reg;
1265         u32 val;
1266
1267         /* PCH only available on ILK+ */
1268         BUG_ON(dev_priv->info->gen < 5);
1269
1270         /* PCH refclock must be enabled first */
1271         assert_pch_refclk_enabled(dev_priv);
1272
1273         reg = PCH_DPLL(pipe);
1274         val = I915_READ(reg);
1275         val |= DPLL_VCO_ENABLE;
1276         I915_WRITE(reg, val);
1277         POSTING_READ(reg);
1278         udelay(200);
1279 }
1280
1281 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1282                                   enum pipe pipe)
1283 {
1284         int reg;
1285         u32 val;
1286
1287         /* PCH only available on ILK+ */
1288         BUG_ON(dev_priv->info->gen < 5);
1289
1290         /* Make sure transcoder isn't still depending on us */
1291         assert_transcoder_disabled(dev_priv, pipe);
1292
1293         reg = PCH_DPLL(pipe);
1294         val = I915_READ(reg);
1295         val &= ~DPLL_VCO_ENABLE;
1296         I915_WRITE(reg, val);
1297         POSTING_READ(reg);
1298         udelay(200);
1299 }
1300
1301 /**
1302  * intel_enable_pipe - enable a pipe, assertiing requirements
1303  * @dev_priv: i915 private structure
1304  * @pipe: pipe to enable
1305  *
1306  * Enable @pipe, making sure that various hardware specific requirements
1307  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1308  *
1309  * @pipe should be %PIPE_A or %PIPE_B.
1310  *
1311  * Will wait until the pipe is actually running (i.e. first vblank) before
1312  * returning.
1313  */
1314 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1315 {
1316         int reg;
1317         u32 val;
1318
1319         /*
1320          * A pipe without a PLL won't actually be able to drive bits from
1321          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1322          * need the check.
1323          */
1324         if (!HAS_PCH_SPLIT(dev_priv->dev))
1325                 assert_pll_enabled(dev_priv, pipe);
1326
1327         reg = PIPECONF(pipe);
1328         val = I915_READ(reg);
1329         val |= PIPECONF_ENABLE;
1330         I915_WRITE(reg, val);
1331         POSTING_READ(reg);
1332         intel_wait_for_vblank(dev_priv->dev, pipe);
1333 }
1334
1335 /**
1336  * intel_disable_pipe - disable a pipe, assertiing requirements
1337  * @dev_priv: i915 private structure
1338  * @pipe: pipe to disable
1339  *
1340  * Disable @pipe, making sure that various hardware specific requirements
1341  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1342  *
1343  * @pipe should be %PIPE_A or %PIPE_B.
1344  *
1345  * Will wait until the pipe has shut down before returning.
1346  */
1347 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1348                                enum pipe pipe)
1349 {
1350         int reg;
1351         u32 val;
1352
1353         /*
1354          * Make sure planes won't keep trying to pump pixels to us,
1355          * or we might hang the display.
1356          */
1357         assert_planes_disabled(dev_priv, pipe);
1358
1359         /* Don't disable pipe A or pipe A PLLs if needed */
1360         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361                 return;
1362
1363         reg = PIPECONF(pipe);
1364         val = I915_READ(reg);
1365         val &= ~PIPECONF_ENABLE;
1366         I915_WRITE(reg, val);
1367         POSTING_READ(reg);
1368         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1369 }
1370
1371 /**
1372  * intel_enable_plane - enable a display plane on a given pipe
1373  * @dev_priv: i915 private structure
1374  * @plane: plane to enable
1375  * @pipe: pipe being fed
1376  *
1377  * Enable @plane on @pipe, making sure that @pipe is running first.
1378  */
1379 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1380                                enum plane plane, enum pipe pipe)
1381 {
1382         int reg;
1383         u32 val;
1384
1385         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1386         assert_pipe_enabled(dev_priv, pipe);
1387
1388         reg = DSPCNTR(plane);
1389         val = I915_READ(reg);
1390         val |= DISPLAY_PLANE_ENABLE;
1391         I915_WRITE(reg, val);
1392         POSTING_READ(reg);
1393         intel_wait_for_vblank(dev_priv->dev, pipe);
1394 }
1395
1396 /*
1397  * Plane regs are double buffered, going from enabled->disabled needs a
1398  * trigger in order to latch.  The display address reg provides this.
1399  */
1400 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1401                                       enum plane plane)
1402 {
1403         u32 reg = DSPADDR(plane);
1404         I915_WRITE(reg, I915_READ(reg));
1405 }
1406
1407 /**
1408  * intel_disable_plane - disable a display plane
1409  * @dev_priv: i915 private structure
1410  * @plane: plane to disable
1411  * @pipe: pipe consuming the data
1412  *
1413  * Disable @plane; should be an independent operation.
1414  */
1415 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1416                                 enum plane plane, enum pipe pipe)
1417 {
1418         int reg;
1419         u32 val;
1420
1421         reg = DSPCNTR(plane);
1422         val = I915_READ(reg);
1423         val &= ~DISPLAY_PLANE_ENABLE;
1424         I915_WRITE(reg, val);
1425         POSTING_READ(reg);
1426         intel_flush_display_plane(dev_priv, plane);
1427         intel_wait_for_vblank(dev_priv->dev, pipe);
1428 }
1429
1430 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1431 {
1432         struct drm_device *dev = crtc->dev;
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         struct drm_framebuffer *fb = crtc->fb;
1435         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1436         struct drm_i915_gem_object *obj = intel_fb->obj;
1437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1438         int plane, i;
1439         u32 fbc_ctl, fbc_ctl2;
1440
1441         if (fb->pitch == dev_priv->cfb_pitch &&
1442             obj->fence_reg == dev_priv->cfb_fence &&
1443             intel_crtc->plane == dev_priv->cfb_plane &&
1444             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1445                 return;
1446
1447         i8xx_disable_fbc(dev);
1448
1449         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1450
1451         if (fb->pitch < dev_priv->cfb_pitch)
1452                 dev_priv->cfb_pitch = fb->pitch;
1453
1454         /* FBC_CTL wants 64B units */
1455         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1456         dev_priv->cfb_fence = obj->fence_reg;
1457         dev_priv->cfb_plane = intel_crtc->plane;
1458         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1459
1460         /* Clear old tags */
1461         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1462                 I915_WRITE(FBC_TAG + (i * 4), 0);
1463
1464         /* Set it up... */
1465         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1466         if (obj->tiling_mode != I915_TILING_NONE)
1467                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1468         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1469         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1470
1471         /* enable it... */
1472         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1473         if (IS_I945GM(dev))
1474                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1475         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1476         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1477         if (obj->tiling_mode != I915_TILING_NONE)
1478                 fbc_ctl |= dev_priv->cfb_fence;
1479         I915_WRITE(FBC_CONTROL, fbc_ctl);
1480
1481         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1482                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1483 }
1484
1485 void i8xx_disable_fbc(struct drm_device *dev)
1486 {
1487         struct drm_i915_private *dev_priv = dev->dev_private;
1488         u32 fbc_ctl;
1489
1490         /* Disable compression */
1491         fbc_ctl = I915_READ(FBC_CONTROL);
1492         if ((fbc_ctl & FBC_CTL_EN) == 0)
1493                 return;
1494
1495         fbc_ctl &= ~FBC_CTL_EN;
1496         I915_WRITE(FBC_CONTROL, fbc_ctl);
1497
1498         /* Wait for compressing bit to clear */
1499         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1500                 DRM_DEBUG_KMS("FBC idle timed out\n");
1501                 return;
1502         }
1503
1504         DRM_DEBUG_KMS("disabled FBC\n");
1505 }
1506
1507 static bool i8xx_fbc_enabled(struct drm_device *dev)
1508 {
1509         struct drm_i915_private *dev_priv = dev->dev_private;
1510
1511         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1512 }
1513
1514 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1515 {
1516         struct drm_device *dev = crtc->dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         struct drm_framebuffer *fb = crtc->fb;
1519         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1520         struct drm_i915_gem_object *obj = intel_fb->obj;
1521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1522         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1523         unsigned long stall_watermark = 200;
1524         u32 dpfc_ctl;
1525
1526         dpfc_ctl = I915_READ(DPFC_CONTROL);
1527         if (dpfc_ctl & DPFC_CTL_EN) {
1528                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1529                     dev_priv->cfb_fence == obj->fence_reg &&
1530                     dev_priv->cfb_plane == intel_crtc->plane &&
1531                     dev_priv->cfb_y == crtc->y)
1532                         return;
1533
1534                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1535                 POSTING_READ(DPFC_CONTROL);
1536                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1537         }
1538
1539         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1540         dev_priv->cfb_fence = obj->fence_reg;
1541         dev_priv->cfb_plane = intel_crtc->plane;
1542         dev_priv->cfb_y = crtc->y;
1543
1544         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1545         if (obj->tiling_mode != I915_TILING_NONE) {
1546                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1547                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1548         } else {
1549                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1550         }
1551
1552         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1553                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1554                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1555         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1556
1557         /* enable it... */
1558         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1559
1560         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1561 }
1562
1563 void g4x_disable_fbc(struct drm_device *dev)
1564 {
1565         struct drm_i915_private *dev_priv = dev->dev_private;
1566         u32 dpfc_ctl;
1567
1568         /* Disable compression */
1569         dpfc_ctl = I915_READ(DPFC_CONTROL);
1570         if (dpfc_ctl & DPFC_CTL_EN) {
1571                 dpfc_ctl &= ~DPFC_CTL_EN;
1572                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1573
1574                 DRM_DEBUG_KMS("disabled FBC\n");
1575         }
1576 }
1577
1578 static bool g4x_fbc_enabled(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1583 }
1584
1585 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1586 {
1587         struct drm_device *dev = crtc->dev;
1588         struct drm_i915_private *dev_priv = dev->dev_private;
1589         struct drm_framebuffer *fb = crtc->fb;
1590         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1591         struct drm_i915_gem_object *obj = intel_fb->obj;
1592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1593         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1594         unsigned long stall_watermark = 200;
1595         u32 dpfc_ctl;
1596
1597         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1598         if (dpfc_ctl & DPFC_CTL_EN) {
1599                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1600                     dev_priv->cfb_fence == obj->fence_reg &&
1601                     dev_priv->cfb_plane == intel_crtc->plane &&
1602                     dev_priv->cfb_offset == obj->gtt_offset &&
1603                     dev_priv->cfb_y == crtc->y)
1604                         return;
1605
1606                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1607                 POSTING_READ(ILK_DPFC_CONTROL);
1608                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1609         }
1610
1611         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1612         dev_priv->cfb_fence = obj->fence_reg;
1613         dev_priv->cfb_plane = intel_crtc->plane;
1614         dev_priv->cfb_offset = obj->gtt_offset;
1615         dev_priv->cfb_y = crtc->y;
1616
1617         dpfc_ctl &= DPFC_RESERVED;
1618         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1619         if (obj->tiling_mode != I915_TILING_NONE) {
1620                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1621                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1622         } else {
1623                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1624         }
1625
1626         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1627                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1628                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1629         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1630         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1631         /* enable it... */
1632         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1633
1634         if (IS_GEN6(dev)) {
1635                 I915_WRITE(SNB_DPFC_CTL_SA,
1636                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1637                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1638         }
1639
1640         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1641 }
1642
1643 void ironlake_disable_fbc(struct drm_device *dev)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646         u32 dpfc_ctl;
1647
1648         /* Disable compression */
1649         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1650         if (dpfc_ctl & DPFC_CTL_EN) {
1651                 dpfc_ctl &= ~DPFC_CTL_EN;
1652                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1653
1654                 DRM_DEBUG_KMS("disabled FBC\n");
1655         }
1656 }
1657
1658 static bool ironlake_fbc_enabled(struct drm_device *dev)
1659 {
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661
1662         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1663 }
1664
1665 bool intel_fbc_enabled(struct drm_device *dev)
1666 {
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668
1669         if (!dev_priv->display.fbc_enabled)
1670                 return false;
1671
1672         return dev_priv->display.fbc_enabled(dev);
1673 }
1674
1675 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1676 {
1677         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1678
1679         if (!dev_priv->display.enable_fbc)
1680                 return;
1681
1682         dev_priv->display.enable_fbc(crtc, interval);
1683 }
1684
1685 void intel_disable_fbc(struct drm_device *dev)
1686 {
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688
1689         if (!dev_priv->display.disable_fbc)
1690                 return;
1691
1692         dev_priv->display.disable_fbc(dev);
1693 }
1694
1695 /**
1696  * intel_update_fbc - enable/disable FBC as needed
1697  * @dev: the drm_device
1698  *
1699  * Set up the framebuffer compression hardware at mode set time.  We
1700  * enable it if possible:
1701  *   - plane A only (on pre-965)
1702  *   - no pixel mulitply/line duplication
1703  *   - no alpha buffer discard
1704  *   - no dual wide
1705  *   - framebuffer <= 2048 in width, 1536 in height
1706  *
1707  * We can't assume that any compression will take place (worst case),
1708  * so the compressed buffer has to be the same size as the uncompressed
1709  * one.  It also must reside (along with the line length buffer) in
1710  * stolen memory.
1711  *
1712  * We need to enable/disable FBC on a global basis.
1713  */
1714 static void intel_update_fbc(struct drm_device *dev)
1715 {
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         struct drm_crtc *crtc = NULL, *tmp_crtc;
1718         struct intel_crtc *intel_crtc;
1719         struct drm_framebuffer *fb;
1720         struct intel_framebuffer *intel_fb;
1721         struct drm_i915_gem_object *obj;
1722
1723         DRM_DEBUG_KMS("\n");
1724
1725         if (!i915_powersave)
1726                 return;
1727
1728         if (!I915_HAS_FBC(dev))
1729                 return;
1730
1731         /*
1732          * If FBC is already on, we just have to verify that we can
1733          * keep it that way...
1734          * Need to disable if:
1735          *   - more than one pipe is active
1736          *   - changing FBC params (stride, fence, mode)
1737          *   - new fb is too large to fit in compressed buffer
1738          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1739          */
1740         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1741                 if (tmp_crtc->enabled) {
1742                         if (crtc) {
1743                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1744                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1745                                 goto out_disable;
1746                         }
1747                         crtc = tmp_crtc;
1748                 }
1749         }
1750
1751         if (!crtc || crtc->fb == NULL) {
1752                 DRM_DEBUG_KMS("no output, disabling\n");
1753                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1754                 goto out_disable;
1755         }
1756
1757         intel_crtc = to_intel_crtc(crtc);
1758         fb = crtc->fb;
1759         intel_fb = to_intel_framebuffer(fb);
1760         obj = intel_fb->obj;
1761
1762         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1763                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1764                               "compression\n");
1765                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1766                 goto out_disable;
1767         }
1768         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1769             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1770                 DRM_DEBUG_KMS("mode incompatible with compression, "
1771                               "disabling\n");
1772                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1773                 goto out_disable;
1774         }
1775         if ((crtc->mode.hdisplay > 2048) ||
1776             (crtc->mode.vdisplay > 1536)) {
1777                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1778                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1779                 goto out_disable;
1780         }
1781         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1782                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1783                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1784                 goto out_disable;
1785         }
1786         if (obj->tiling_mode != I915_TILING_X) {
1787                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1788                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1789                 goto out_disable;
1790         }
1791
1792         /* If the kernel debugger is active, always disable compression */
1793         if (in_dbg_master())
1794                 goto out_disable;
1795
1796         intel_enable_fbc(crtc, 500);
1797         return;
1798
1799 out_disable:
1800         /* Multiple disables should be harmless */
1801         if (intel_fbc_enabled(dev)) {
1802                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1803                 intel_disable_fbc(dev);
1804         }
1805 }
1806
1807 int
1808 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1809                            struct drm_i915_gem_object *obj,
1810                            struct intel_ring_buffer *pipelined)
1811 {
1812         u32 alignment;
1813         int ret;
1814
1815         switch (obj->tiling_mode) {
1816         case I915_TILING_NONE:
1817                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1818                         alignment = 128 * 1024;
1819                 else if (INTEL_INFO(dev)->gen >= 4)
1820                         alignment = 4 * 1024;
1821                 else
1822                         alignment = 64 * 1024;
1823                 break;
1824         case I915_TILING_X:
1825                 /* pin() will align the object as required by fence */
1826                 alignment = 0;
1827                 break;
1828         case I915_TILING_Y:
1829                 /* FIXME: Is this true? */
1830                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1831                 return -EINVAL;
1832         default:
1833                 BUG();
1834         }
1835
1836         ret = i915_gem_object_pin(obj, alignment, true);
1837         if (ret)
1838                 return ret;
1839
1840         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1841         if (ret)
1842                 goto err_unpin;
1843
1844         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1845          * fence, whereas 965+ only requires a fence if using
1846          * framebuffer compression.  For simplicity, we always install
1847          * a fence as the cost is not that onerous.
1848          */
1849         if (obj->tiling_mode != I915_TILING_NONE) {
1850                 ret = i915_gem_object_get_fence(obj, pipelined, false);
1851                 if (ret)
1852                         goto err_unpin;
1853         }
1854
1855         return 0;
1856
1857 err_unpin:
1858         i915_gem_object_unpin(obj);
1859         return ret;
1860 }
1861
1862 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1863 static int
1864 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1865                            int x, int y, enum mode_set_atomic state)
1866 {
1867         struct drm_device *dev = crtc->dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1870         struct intel_framebuffer *intel_fb;
1871         struct drm_i915_gem_object *obj;
1872         int plane = intel_crtc->plane;
1873         unsigned long Start, Offset;
1874         u32 dspcntr;
1875         u32 reg;
1876
1877         switch (plane) {
1878         case 0:
1879         case 1:
1880                 break;
1881         default:
1882                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1883                 return -EINVAL;
1884         }
1885
1886         intel_fb = to_intel_framebuffer(fb);
1887         obj = intel_fb->obj;
1888
1889         reg = DSPCNTR(plane);
1890         dspcntr = I915_READ(reg);
1891         /* Mask out pixel format bits in case we change it */
1892         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1893         switch (fb->bits_per_pixel) {
1894         case 8:
1895                 dspcntr |= DISPPLANE_8BPP;
1896                 break;
1897         case 16:
1898                 if (fb->depth == 15)
1899                         dspcntr |= DISPPLANE_15_16BPP;
1900                 else
1901                         dspcntr |= DISPPLANE_16BPP;
1902                 break;
1903         case 24:
1904         case 32:
1905                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1906                 break;
1907         default:
1908                 DRM_ERROR("Unknown color depth\n");
1909                 return -EINVAL;
1910         }
1911         if (INTEL_INFO(dev)->gen >= 4) {
1912                 if (obj->tiling_mode != I915_TILING_NONE)
1913                         dspcntr |= DISPPLANE_TILED;
1914                 else
1915                         dspcntr &= ~DISPPLANE_TILED;
1916         }
1917
1918         if (HAS_PCH_SPLIT(dev))
1919                 /* must disable */
1920                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1921
1922         I915_WRITE(reg, dspcntr);
1923
1924         Start = obj->gtt_offset;
1925         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1926
1927         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1928                       Start, Offset, x, y, fb->pitch);
1929         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1930         if (INTEL_INFO(dev)->gen >= 4) {
1931                 I915_WRITE(DSPSURF(plane), Start);
1932                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1933                 I915_WRITE(DSPADDR(plane), Offset);
1934         } else
1935                 I915_WRITE(DSPADDR(plane), Start + Offset);
1936         POSTING_READ(reg);
1937
1938         intel_update_fbc(dev);
1939         intel_increase_pllclock(crtc);
1940
1941         return 0;
1942 }
1943
1944 static int
1945 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1946                     struct drm_framebuffer *old_fb)
1947 {
1948         struct drm_device *dev = crtc->dev;
1949         struct drm_i915_master_private *master_priv;
1950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1951         int ret;
1952
1953         /* no fb bound */
1954         if (!crtc->fb) {
1955                 DRM_DEBUG_KMS("No FB bound\n");
1956                 return 0;
1957         }
1958
1959         switch (intel_crtc->plane) {
1960         case 0:
1961         case 1:
1962                 break;
1963         default:
1964                 return -EINVAL;
1965         }
1966
1967         mutex_lock(&dev->struct_mutex);
1968         ret = intel_pin_and_fence_fb_obj(dev,
1969                                          to_intel_framebuffer(crtc->fb)->obj,
1970                                          NULL);
1971         if (ret != 0) {
1972                 mutex_unlock(&dev->struct_mutex);
1973                 return ret;
1974         }
1975
1976         if (old_fb) {
1977                 struct drm_i915_private *dev_priv = dev->dev_private;
1978                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1979
1980                 wait_event(dev_priv->pending_flip_queue,
1981                            atomic_read(&obj->pending_flip) == 0);
1982
1983                 /* Big Hammer, we also need to ensure that any pending
1984                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1985                  * current scanout is retired before unpinning the old
1986                  * framebuffer.
1987                  */
1988                 ret = i915_gem_object_flush_gpu(obj, false);
1989                 if (ret) {
1990                         i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1991                         mutex_unlock(&dev->struct_mutex);
1992                         return ret;
1993                 }
1994         }
1995
1996         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1997                                          LEAVE_ATOMIC_MODE_SET);
1998         if (ret) {
1999                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2000                 mutex_unlock(&dev->struct_mutex);
2001                 return ret;
2002         }
2003
2004         if (old_fb) {
2005                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2006                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2007         }
2008
2009         mutex_unlock(&dev->struct_mutex);
2010
2011         if (!dev->primary->master)
2012                 return 0;
2013
2014         master_priv = dev->primary->master->driver_priv;
2015         if (!master_priv->sarea_priv)
2016                 return 0;
2017
2018         if (intel_crtc->pipe) {
2019                 master_priv->sarea_priv->pipeB_x = x;
2020                 master_priv->sarea_priv->pipeB_y = y;
2021         } else {
2022                 master_priv->sarea_priv->pipeA_x = x;
2023                 master_priv->sarea_priv->pipeA_y = y;
2024         }
2025
2026         return 0;
2027 }
2028
2029 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2030 {
2031         struct drm_device *dev = crtc->dev;
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033         u32 dpa_ctl;
2034
2035         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2036         dpa_ctl = I915_READ(DP_A);
2037         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2038
2039         if (clock < 200000) {
2040                 u32 temp;
2041                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2042                 /* workaround for 160Mhz:
2043                    1) program 0x4600c bits 15:0 = 0x8124
2044                    2) program 0x46010 bit 0 = 1
2045                    3) program 0x46034 bit 24 = 1
2046                    4) program 0x64000 bit 14 = 1
2047                    */
2048                 temp = I915_READ(0x4600c);
2049                 temp &= 0xffff0000;
2050                 I915_WRITE(0x4600c, temp | 0x8124);
2051
2052                 temp = I915_READ(0x46010);
2053                 I915_WRITE(0x46010, temp | 1);
2054
2055                 temp = I915_READ(0x46034);
2056                 I915_WRITE(0x46034, temp | (1 << 24));
2057         } else {
2058                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2059         }
2060         I915_WRITE(DP_A, dpa_ctl);
2061
2062         POSTING_READ(DP_A);
2063         udelay(500);
2064 }
2065
2066 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2067 {
2068         struct drm_device *dev = crtc->dev;
2069         struct drm_i915_private *dev_priv = dev->dev_private;
2070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2071         int pipe = intel_crtc->pipe;
2072         u32 reg, temp;
2073
2074         /* enable normal train */
2075         reg = FDI_TX_CTL(pipe);
2076         temp = I915_READ(reg);
2077         temp &= ~FDI_LINK_TRAIN_NONE;
2078         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2079         I915_WRITE(reg, temp);
2080
2081         reg = FDI_RX_CTL(pipe);
2082         temp = I915_READ(reg);
2083         if (HAS_PCH_CPT(dev)) {
2084                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2085                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2086         } else {
2087                 temp &= ~FDI_LINK_TRAIN_NONE;
2088                 temp |= FDI_LINK_TRAIN_NONE;
2089         }
2090         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2091
2092         /* wait one idle pattern time */
2093         POSTING_READ(reg);
2094         udelay(1000);
2095 }
2096
2097 /* The FDI link training functions for ILK/Ibexpeak. */
2098 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2099 {
2100         struct drm_device *dev = crtc->dev;
2101         struct drm_i915_private *dev_priv = dev->dev_private;
2102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103         int pipe = intel_crtc->pipe;
2104         u32 reg, temp, tries;
2105
2106         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2107            for train result */
2108         reg = FDI_RX_IMR(pipe);
2109         temp = I915_READ(reg);
2110         temp &= ~FDI_RX_SYMBOL_LOCK;
2111         temp &= ~FDI_RX_BIT_LOCK;
2112         I915_WRITE(reg, temp);
2113         I915_READ(reg);
2114         udelay(150);
2115
2116         /* enable CPU FDI TX and PCH FDI RX */
2117         reg = FDI_TX_CTL(pipe);
2118         temp = I915_READ(reg);
2119         temp &= ~(7 << 19);
2120         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2121         temp &= ~FDI_LINK_TRAIN_NONE;
2122         temp |= FDI_LINK_TRAIN_PATTERN_1;
2123         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2124
2125         reg = FDI_RX_CTL(pipe);
2126         temp = I915_READ(reg);
2127         temp &= ~FDI_LINK_TRAIN_NONE;
2128         temp |= FDI_LINK_TRAIN_PATTERN_1;
2129         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2130
2131         POSTING_READ(reg);
2132         udelay(150);
2133
2134         /* Ironlake workaround, enable clock pointer after FDI enable*/
2135         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
2136
2137         reg = FDI_RX_IIR(pipe);
2138         for (tries = 0; tries < 5; tries++) {
2139                 temp = I915_READ(reg);
2140                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2141
2142                 if ((temp & FDI_RX_BIT_LOCK)) {
2143                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2144                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2145                         break;
2146                 }
2147         }
2148         if (tries == 5)
2149                 DRM_ERROR("FDI train 1 fail!\n");
2150
2151         /* Train 2 */
2152         reg = FDI_TX_CTL(pipe);
2153         temp = I915_READ(reg);
2154         temp &= ~FDI_LINK_TRAIN_NONE;
2155         temp |= FDI_LINK_TRAIN_PATTERN_2;
2156         I915_WRITE(reg, temp);
2157
2158         reg = FDI_RX_CTL(pipe);
2159         temp = I915_READ(reg);
2160         temp &= ~FDI_LINK_TRAIN_NONE;
2161         temp |= FDI_LINK_TRAIN_PATTERN_2;
2162         I915_WRITE(reg, temp);
2163
2164         POSTING_READ(reg);
2165         udelay(150);
2166
2167         reg = FDI_RX_IIR(pipe);
2168         for (tries = 0; tries < 5; tries++) {
2169                 temp = I915_READ(reg);
2170                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2171
2172                 if (temp & FDI_RX_SYMBOL_LOCK) {
2173                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2174                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2175                         break;
2176                 }
2177         }
2178         if (tries == 5)
2179                 DRM_ERROR("FDI train 2 fail!\n");
2180
2181         DRM_DEBUG_KMS("FDI train done\n");
2182
2183 }
2184
2185 static const int const snb_b_fdi_train_param [] = {
2186         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2187         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2188         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2189         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2190 };
2191
2192 /* The FDI link training functions for SNB/Cougarpoint. */
2193 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2194 {
2195         struct drm_device *dev = crtc->dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2198         int pipe = intel_crtc->pipe;
2199         u32 reg, temp, i;
2200
2201         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2202            for train result */
2203         reg = FDI_RX_IMR(pipe);
2204         temp = I915_READ(reg);
2205         temp &= ~FDI_RX_SYMBOL_LOCK;
2206         temp &= ~FDI_RX_BIT_LOCK;
2207         I915_WRITE(reg, temp);
2208
2209         POSTING_READ(reg);
2210         udelay(150);
2211
2212         /* enable CPU FDI TX and PCH FDI RX */
2213         reg = FDI_TX_CTL(pipe);
2214         temp = I915_READ(reg);
2215         temp &= ~(7 << 19);
2216         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2217         temp &= ~FDI_LINK_TRAIN_NONE;
2218         temp |= FDI_LINK_TRAIN_PATTERN_1;
2219         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2220         /* SNB-B */
2221         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2222         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2223
2224         reg = FDI_RX_CTL(pipe);
2225         temp = I915_READ(reg);
2226         if (HAS_PCH_CPT(dev)) {
2227                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2228                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2229         } else {
2230                 temp &= ~FDI_LINK_TRAIN_NONE;
2231                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2232         }
2233         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2234
2235         POSTING_READ(reg);
2236         udelay(150);
2237
2238         for (i = 0; i < 4; i++ ) {
2239                 reg = FDI_TX_CTL(pipe);
2240                 temp = I915_READ(reg);
2241                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2242                 temp |= snb_b_fdi_train_param[i];
2243                 I915_WRITE(reg, temp);
2244
2245                 POSTING_READ(reg);
2246                 udelay(500);
2247
2248                 reg = FDI_RX_IIR(pipe);
2249                 temp = I915_READ(reg);
2250                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2251
2252                 if (temp & FDI_RX_BIT_LOCK) {
2253                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2254                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2255                         break;
2256                 }
2257         }
2258         if (i == 4)
2259                 DRM_ERROR("FDI train 1 fail!\n");
2260
2261         /* Train 2 */
2262         reg = FDI_TX_CTL(pipe);
2263         temp = I915_READ(reg);
2264         temp &= ~FDI_LINK_TRAIN_NONE;
2265         temp |= FDI_LINK_TRAIN_PATTERN_2;
2266         if (IS_GEN6(dev)) {
2267                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2268                 /* SNB-B */
2269                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2270         }
2271         I915_WRITE(reg, temp);
2272
2273         reg = FDI_RX_CTL(pipe);
2274         temp = I915_READ(reg);
2275         if (HAS_PCH_CPT(dev)) {
2276                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2277                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2278         } else {
2279                 temp &= ~FDI_LINK_TRAIN_NONE;
2280                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2281         }
2282         I915_WRITE(reg, temp);
2283
2284         POSTING_READ(reg);
2285         udelay(150);
2286
2287         for (i = 0; i < 4; i++ ) {
2288                 reg = FDI_TX_CTL(pipe);
2289                 temp = I915_READ(reg);
2290                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2291                 temp |= snb_b_fdi_train_param[i];
2292                 I915_WRITE(reg, temp);
2293
2294                 POSTING_READ(reg);
2295                 udelay(500);
2296
2297                 reg = FDI_RX_IIR(pipe);
2298                 temp = I915_READ(reg);
2299                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2300
2301                 if (temp & FDI_RX_SYMBOL_LOCK) {
2302                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2303                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2304                         break;
2305                 }
2306         }
2307         if (i == 4)
2308                 DRM_ERROR("FDI train 2 fail!\n");
2309
2310         DRM_DEBUG_KMS("FDI train done.\n");
2311 }
2312
2313 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2314 {
2315         struct drm_device *dev = crtc->dev;
2316         struct drm_i915_private *dev_priv = dev->dev_private;
2317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318         int pipe = intel_crtc->pipe;
2319         u32 reg, temp;
2320
2321         /* Write the TU size bits so error detection works */
2322         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2323                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2324
2325         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2326         reg = FDI_RX_CTL(pipe);
2327         temp = I915_READ(reg);
2328         temp &= ~((0x7 << 19) | (0x7 << 16));
2329         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2330         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2331         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2332
2333         POSTING_READ(reg);
2334         udelay(200);
2335
2336         /* Switch from Rawclk to PCDclk */
2337         temp = I915_READ(reg);
2338         I915_WRITE(reg, temp | FDI_PCDCLK);
2339
2340         POSTING_READ(reg);
2341         udelay(200);
2342
2343         /* Enable CPU FDI TX PLL, always on for Ironlake */
2344         reg = FDI_TX_CTL(pipe);
2345         temp = I915_READ(reg);
2346         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2347                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2348
2349                 POSTING_READ(reg);
2350                 udelay(100);
2351         }
2352 }
2353
2354 /*
2355  * When we disable a pipe, we need to clear any pending scanline wait events
2356  * to avoid hanging the ring, which we assume we are waiting on.
2357  */
2358 static void intel_clear_scanline_wait(struct drm_device *dev)
2359 {
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct intel_ring_buffer *ring;
2362         u32 tmp;
2363
2364         if (IS_GEN2(dev))
2365                 /* Can't break the hang on i8xx */
2366                 return;
2367
2368         ring = LP_RING(dev_priv);
2369         tmp = I915_READ_CTL(ring);
2370         if (tmp & RING_WAIT)
2371                 I915_WRITE_CTL(ring, tmp);
2372 }
2373
2374 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2375 {
2376         struct drm_i915_gem_object *obj;
2377         struct drm_i915_private *dev_priv;
2378
2379         if (crtc->fb == NULL)
2380                 return;
2381
2382         obj = to_intel_framebuffer(crtc->fb)->obj;
2383         dev_priv = crtc->dev->dev_private;
2384         wait_event(dev_priv->pending_flip_queue,
2385                    atomic_read(&obj->pending_flip) == 0);
2386 }
2387
2388 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2389 {
2390         struct drm_device *dev = crtc->dev;
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393         int pipe = intel_crtc->pipe;
2394         int plane = intel_crtc->plane;
2395         u32 reg, temp;
2396
2397         if (intel_crtc->active)
2398                 return;
2399
2400         intel_crtc->active = true;
2401         intel_update_watermarks(dev);
2402
2403         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2404                 temp = I915_READ(PCH_LVDS);
2405                 if ((temp & LVDS_PORT_EN) == 0)
2406                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2407         }
2408
2409         ironlake_fdi_enable(crtc);
2410
2411         /* Enable panel fitting for LVDS */
2412         if (dev_priv->pch_pf_size &&
2413             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2414                 /* Force use of hard-coded filter coefficients
2415                  * as some pre-programmed values are broken,
2416                  * e.g. x201.
2417                  */
2418                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2419                            PF_ENABLE | PF_FILTER_MED_3x3);
2420                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2421                            dev_priv->pch_pf_pos);
2422                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2423                            dev_priv->pch_pf_size);
2424         }
2425
2426         intel_enable_pipe(dev_priv, pipe);
2427         intel_enable_plane(dev_priv, plane, pipe);
2428
2429         /* For PCH output, training FDI link */
2430         if (IS_GEN6(dev))
2431                 gen6_fdi_link_train(crtc);
2432         else
2433                 ironlake_fdi_link_train(crtc);
2434
2435         intel_enable_pch_pll(dev_priv, pipe);
2436
2437         if (HAS_PCH_CPT(dev)) {
2438                 /* Be sure PCH DPLL SEL is set */
2439                 temp = I915_READ(PCH_DPLL_SEL);
2440                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2441                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2442                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2443                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2444                 I915_WRITE(PCH_DPLL_SEL, temp);
2445         }
2446
2447         /* set transcoder timing */
2448         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2449         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2450         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2451
2452         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2453         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2454         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2455
2456         intel_fdi_normal_train(crtc);
2457
2458         /* For PCH DP, enable TRANS_DP_CTL */
2459         if (HAS_PCH_CPT(dev) &&
2460             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2461                 reg = TRANS_DP_CTL(pipe);
2462                 temp = I915_READ(reg);
2463                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2464                           TRANS_DP_SYNC_MASK |
2465                           TRANS_DP_BPC_MASK);
2466                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2467                          TRANS_DP_ENH_FRAMING);
2468                 temp |= TRANS_DP_8BPC;
2469
2470                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2471                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2472                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2473                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2474
2475                 switch (intel_trans_dp_port_sel(crtc)) {
2476                 case PCH_DP_B:
2477                         temp |= TRANS_DP_PORT_SEL_B;
2478                         break;
2479                 case PCH_DP_C:
2480                         temp |= TRANS_DP_PORT_SEL_C;
2481                         break;
2482                 case PCH_DP_D:
2483                         temp |= TRANS_DP_PORT_SEL_D;
2484                         break;
2485                 default:
2486                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2487                         temp |= TRANS_DP_PORT_SEL_B;
2488                         break;
2489                 }
2490
2491                 I915_WRITE(reg, temp);
2492         }
2493
2494         /* enable PCH transcoder */
2495         reg = TRANSCONF(pipe);
2496         temp = I915_READ(reg);
2497         /*
2498          * make the BPC in transcoder be consistent with
2499          * that in pipeconf reg.
2500          */
2501         temp &= ~PIPE_BPC_MASK;
2502         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2503         I915_WRITE(reg, temp | TRANS_ENABLE);
2504         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2505                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2506
2507         intel_crtc_load_lut(crtc);
2508         intel_update_fbc(dev);
2509         intel_crtc_update_cursor(crtc, true);
2510 }
2511
2512 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517         int pipe = intel_crtc->pipe;
2518         int plane = intel_crtc->plane;
2519         u32 reg, temp;
2520
2521         if (!intel_crtc->active)
2522                 return;
2523
2524         intel_crtc_wait_for_pending_flips(crtc);
2525         drm_vblank_off(dev, pipe);
2526         intel_crtc_update_cursor(crtc, false);
2527
2528         intel_disable_plane(dev_priv, plane, pipe);
2529
2530         if (dev_priv->cfb_plane == plane &&
2531             dev_priv->display.disable_fbc)
2532                 dev_priv->display.disable_fbc(dev);
2533
2534         intel_disable_pipe(dev_priv, pipe);
2535
2536         /* Disable PF */
2537         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2538         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2539
2540         /* disable CPU FDI tx and PCH FDI rx */
2541         reg = FDI_TX_CTL(pipe);
2542         temp = I915_READ(reg);
2543         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2544         POSTING_READ(reg);
2545
2546         reg = FDI_RX_CTL(pipe);
2547         temp = I915_READ(reg);
2548         temp &= ~(0x7 << 16);
2549         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2550         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2551
2552         POSTING_READ(reg);
2553         udelay(100);
2554
2555         /* Ironlake workaround, disable clock pointer after downing FDI */
2556         if (HAS_PCH_IBX(dev))
2557                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2558                            I915_READ(FDI_RX_CHICKEN(pipe) &
2559                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2560
2561         /* still set train pattern 1 */
2562         reg = FDI_TX_CTL(pipe);
2563         temp = I915_READ(reg);
2564         temp &= ~FDI_LINK_TRAIN_NONE;
2565         temp |= FDI_LINK_TRAIN_PATTERN_1;
2566         I915_WRITE(reg, temp);
2567
2568         reg = FDI_RX_CTL(pipe);
2569         temp = I915_READ(reg);
2570         if (HAS_PCH_CPT(dev)) {
2571                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2572                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2573         } else {
2574                 temp &= ~FDI_LINK_TRAIN_NONE;
2575                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2576         }
2577         /* BPC in FDI rx is consistent with that in PIPECONF */
2578         temp &= ~(0x07 << 16);
2579         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2580         I915_WRITE(reg, temp);
2581
2582         POSTING_READ(reg);
2583         udelay(100);
2584
2585         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2586                 temp = I915_READ(PCH_LVDS);
2587                 if (temp & LVDS_PORT_EN) {
2588                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2589                         POSTING_READ(PCH_LVDS);
2590                         udelay(100);
2591                 }
2592         }
2593
2594         /* disable PCH transcoder */
2595         reg = TRANSCONF(plane);
2596         temp = I915_READ(reg);
2597         if (temp & TRANS_ENABLE) {
2598                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2599                 /* wait for PCH transcoder off, transcoder state */
2600                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2601                         DRM_ERROR("failed to disable transcoder\n");
2602         }
2603
2604         if (HAS_PCH_CPT(dev)) {
2605                 /* disable TRANS_DP_CTL */
2606                 reg = TRANS_DP_CTL(pipe);
2607                 temp = I915_READ(reg);
2608                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2609                 I915_WRITE(reg, temp);
2610
2611                 /* disable DPLL_SEL */
2612                 temp = I915_READ(PCH_DPLL_SEL);
2613                 if (pipe == 0)
2614                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2615                 else
2616                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2617                 I915_WRITE(PCH_DPLL_SEL, temp);
2618         }
2619
2620         /* disable PCH DPLL */
2621         intel_disable_pch_pll(dev_priv, pipe);
2622
2623         /* Switch from PCDclk to Rawclk */
2624         reg = FDI_RX_CTL(pipe);
2625         temp = I915_READ(reg);
2626         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2627
2628         /* Disable CPU FDI TX PLL */
2629         reg = FDI_TX_CTL(pipe);
2630         temp = I915_READ(reg);
2631         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2632
2633         POSTING_READ(reg);
2634         udelay(100);
2635
2636         reg = FDI_RX_CTL(pipe);
2637         temp = I915_READ(reg);
2638         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2639
2640         /* Wait for the clocks to turn off. */
2641         POSTING_READ(reg);
2642         udelay(100);
2643
2644         intel_crtc->active = false;
2645         intel_update_watermarks(dev);
2646         intel_update_fbc(dev);
2647         intel_clear_scanline_wait(dev);
2648 }
2649
2650 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2651 {
2652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653         int pipe = intel_crtc->pipe;
2654         int plane = intel_crtc->plane;
2655
2656         /* XXX: When our outputs are all unaware of DPMS modes other than off
2657          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2658          */
2659         switch (mode) {
2660         case DRM_MODE_DPMS_ON:
2661         case DRM_MODE_DPMS_STANDBY:
2662         case DRM_MODE_DPMS_SUSPEND:
2663                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2664                 ironlake_crtc_enable(crtc);
2665                 break;
2666
2667         case DRM_MODE_DPMS_OFF:
2668                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2669                 ironlake_crtc_disable(crtc);
2670                 break;
2671         }
2672 }
2673
2674 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2675 {
2676         if (!enable && intel_crtc->overlay) {
2677                 struct drm_device *dev = intel_crtc->base.dev;
2678
2679                 mutex_lock(&dev->struct_mutex);
2680                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2681                 mutex_unlock(&dev->struct_mutex);
2682         }
2683
2684         /* Let userspace switch the overlay on again. In most cases userspace
2685          * has to recompute where to put it anyway.
2686          */
2687 }
2688
2689 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2690 {
2691         struct drm_device *dev = crtc->dev;
2692         struct drm_i915_private *dev_priv = dev->dev_private;
2693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694         int pipe = intel_crtc->pipe;
2695         int plane = intel_crtc->plane;
2696
2697         if (intel_crtc->active)
2698                 return;
2699
2700         intel_crtc->active = true;
2701         intel_update_watermarks(dev);
2702
2703         intel_enable_pll(dev_priv, pipe);
2704         intel_enable_pipe(dev_priv, pipe);
2705         intel_enable_plane(dev_priv, plane, pipe);
2706
2707         intel_crtc_load_lut(crtc);
2708         intel_update_fbc(dev);
2709
2710         /* Give the overlay scaler a chance to enable if it's on this pipe */
2711         intel_crtc_dpms_overlay(intel_crtc, true);
2712         intel_crtc_update_cursor(crtc, true);
2713 }
2714
2715 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2716 {
2717         struct drm_device *dev = crtc->dev;
2718         struct drm_i915_private *dev_priv = dev->dev_private;
2719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2720         int pipe = intel_crtc->pipe;
2721         int plane = intel_crtc->plane;
2722
2723         if (!intel_crtc->active)
2724                 return;
2725
2726         /* Give the overlay scaler a chance to disable if it's on this pipe */
2727         intel_crtc_wait_for_pending_flips(crtc);
2728         drm_vblank_off(dev, pipe);
2729         intel_crtc_dpms_overlay(intel_crtc, false);
2730         intel_crtc_update_cursor(crtc, false);
2731
2732         if (dev_priv->cfb_plane == plane &&
2733             dev_priv->display.disable_fbc)
2734                 dev_priv->display.disable_fbc(dev);
2735
2736         intel_disable_plane(dev_priv, plane, pipe);
2737         intel_disable_pipe(dev_priv, pipe);
2738         intel_disable_pll(dev_priv, pipe);
2739
2740         intel_crtc->active = false;
2741         intel_update_fbc(dev);
2742         intel_update_watermarks(dev);
2743         intel_clear_scanline_wait(dev);
2744 }
2745
2746 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2747 {
2748         /* XXX: When our outputs are all unaware of DPMS modes other than off
2749          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2750          */
2751         switch (mode) {
2752         case DRM_MODE_DPMS_ON:
2753         case DRM_MODE_DPMS_STANDBY:
2754         case DRM_MODE_DPMS_SUSPEND:
2755                 i9xx_crtc_enable(crtc);
2756                 break;
2757         case DRM_MODE_DPMS_OFF:
2758                 i9xx_crtc_disable(crtc);
2759                 break;
2760         }
2761 }
2762
2763 /**
2764  * Sets the power management mode of the pipe and plane.
2765  */
2766 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2767 {
2768         struct drm_device *dev = crtc->dev;
2769         struct drm_i915_private *dev_priv = dev->dev_private;
2770         struct drm_i915_master_private *master_priv;
2771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2772         int pipe = intel_crtc->pipe;
2773         bool enabled;
2774
2775         if (intel_crtc->dpms_mode == mode)
2776                 return;
2777
2778         intel_crtc->dpms_mode = mode;
2779
2780         dev_priv->display.dpms(crtc, mode);
2781
2782         if (!dev->primary->master)
2783                 return;
2784
2785         master_priv = dev->primary->master->driver_priv;
2786         if (!master_priv->sarea_priv)
2787                 return;
2788
2789         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2790
2791         switch (pipe) {
2792         case 0:
2793                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2794                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2795                 break;
2796         case 1:
2797                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2798                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2799                 break;
2800         default:
2801                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2802                 break;
2803         }
2804 }
2805
2806 static void intel_crtc_disable(struct drm_crtc *crtc)
2807 {
2808         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2809         struct drm_device *dev = crtc->dev;
2810
2811         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2812
2813         if (crtc->fb) {
2814                 mutex_lock(&dev->struct_mutex);
2815                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2816                 mutex_unlock(&dev->struct_mutex);
2817         }
2818 }
2819
2820 /* Prepare for a mode set.
2821  *
2822  * Note we could be a lot smarter here.  We need to figure out which outputs
2823  * will be enabled, which disabled (in short, how the config will changes)
2824  * and perform the minimum necessary steps to accomplish that, e.g. updating
2825  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2826  * panel fitting is in the proper state, etc.
2827  */
2828 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2829 {
2830         i9xx_crtc_disable(crtc);
2831 }
2832
2833 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2834 {
2835         i9xx_crtc_enable(crtc);
2836 }
2837
2838 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2839 {
2840         ironlake_crtc_disable(crtc);
2841 }
2842
2843 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2844 {
2845         ironlake_crtc_enable(crtc);
2846 }
2847
2848 void intel_encoder_prepare (struct drm_encoder *encoder)
2849 {
2850         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2851         /* lvds has its own version of prepare see intel_lvds_prepare */
2852         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2853 }
2854
2855 void intel_encoder_commit (struct drm_encoder *encoder)
2856 {
2857         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2858         /* lvds has its own version of commit see intel_lvds_commit */
2859         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2860 }
2861
2862 void intel_encoder_destroy(struct drm_encoder *encoder)
2863 {
2864         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2865
2866         drm_encoder_cleanup(encoder);
2867         kfree(intel_encoder);
2868 }
2869
2870 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2871                                   struct drm_display_mode *mode,
2872                                   struct drm_display_mode *adjusted_mode)
2873 {
2874         struct drm_device *dev = crtc->dev;
2875
2876         if (HAS_PCH_SPLIT(dev)) {
2877                 /* FDI link clock is fixed at 2.7G */
2878                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2879                         return false;
2880         }
2881
2882         /* XXX some encoders set the crtcinfo, others don't.
2883          * Obviously we need some form of conflict resolution here...
2884          */
2885         if (adjusted_mode->crtc_htotal == 0)
2886                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2887
2888         return true;
2889 }
2890
2891 static int i945_get_display_clock_speed(struct drm_device *dev)
2892 {
2893         return 400000;
2894 }
2895
2896 static int i915_get_display_clock_speed(struct drm_device *dev)
2897 {
2898         return 333000;
2899 }
2900
2901 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2902 {
2903         return 200000;
2904 }
2905
2906 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2907 {
2908         u16 gcfgc = 0;
2909
2910         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2911
2912         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2913                 return 133000;
2914         else {
2915                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2916                 case GC_DISPLAY_CLOCK_333_MHZ:
2917                         return 333000;
2918                 default:
2919                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2920                         return 190000;
2921                 }
2922         }
2923 }
2924
2925 static int i865_get_display_clock_speed(struct drm_device *dev)
2926 {
2927         return 266000;
2928 }
2929
2930 static int i855_get_display_clock_speed(struct drm_device *dev)
2931 {
2932         u16 hpllcc = 0;
2933         /* Assume that the hardware is in the high speed state.  This
2934          * should be the default.
2935          */
2936         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2937         case GC_CLOCK_133_200:
2938         case GC_CLOCK_100_200:
2939                 return 200000;
2940         case GC_CLOCK_166_250:
2941                 return 250000;
2942         case GC_CLOCK_100_133:
2943                 return 133000;
2944         }
2945
2946         /* Shouldn't happen */
2947         return 0;
2948 }
2949
2950 static int i830_get_display_clock_speed(struct drm_device *dev)
2951 {
2952         return 133000;
2953 }
2954
2955 struct fdi_m_n {
2956         u32        tu;
2957         u32        gmch_m;
2958         u32        gmch_n;
2959         u32        link_m;
2960         u32        link_n;
2961 };
2962
2963 static void
2964 fdi_reduce_ratio(u32 *num, u32 *den)
2965 {
2966         while (*num > 0xffffff || *den > 0xffffff) {
2967                 *num >>= 1;
2968                 *den >>= 1;
2969         }
2970 }
2971
2972 static void
2973 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2974                      int link_clock, struct fdi_m_n *m_n)
2975 {
2976         m_n->tu = 64; /* default size */
2977
2978         /* BUG_ON(pixel_clock > INT_MAX / 36); */
2979         m_n->gmch_m = bits_per_pixel * pixel_clock;
2980         m_n->gmch_n = link_clock * nlanes * 8;
2981         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2982
2983         m_n->link_m = pixel_clock;
2984         m_n->link_n = link_clock;
2985         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2986 }
2987
2988
2989 struct intel_watermark_params {
2990         unsigned long fifo_size;
2991         unsigned long max_wm;
2992         unsigned long default_wm;
2993         unsigned long guard_size;
2994         unsigned long cacheline_size;
2995 };
2996
2997 /* Pineview has different values for various configs */
2998 static struct intel_watermark_params pineview_display_wm = {
2999         PINEVIEW_DISPLAY_FIFO,
3000         PINEVIEW_MAX_WM,
3001         PINEVIEW_DFT_WM,
3002         PINEVIEW_GUARD_WM,
3003         PINEVIEW_FIFO_LINE_SIZE
3004 };
3005 static struct intel_watermark_params pineview_display_hplloff_wm = {
3006         PINEVIEW_DISPLAY_FIFO,
3007         PINEVIEW_MAX_WM,
3008         PINEVIEW_DFT_HPLLOFF_WM,
3009         PINEVIEW_GUARD_WM,
3010         PINEVIEW_FIFO_LINE_SIZE
3011 };
3012 static struct intel_watermark_params pineview_cursor_wm = {
3013         PINEVIEW_CURSOR_FIFO,
3014         PINEVIEW_CURSOR_MAX_WM,
3015         PINEVIEW_CURSOR_DFT_WM,
3016         PINEVIEW_CURSOR_GUARD_WM,
3017         PINEVIEW_FIFO_LINE_SIZE,
3018 };
3019 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
3020         PINEVIEW_CURSOR_FIFO,
3021         PINEVIEW_CURSOR_MAX_WM,
3022         PINEVIEW_CURSOR_DFT_WM,
3023         PINEVIEW_CURSOR_GUARD_WM,
3024         PINEVIEW_FIFO_LINE_SIZE
3025 };
3026 static struct intel_watermark_params g4x_wm_info = {
3027         G4X_FIFO_SIZE,
3028         G4X_MAX_WM,
3029         G4X_MAX_WM,
3030         2,
3031         G4X_FIFO_LINE_SIZE,
3032 };
3033 static struct intel_watermark_params g4x_cursor_wm_info = {
3034         I965_CURSOR_FIFO,
3035         I965_CURSOR_MAX_WM,
3036         I965_CURSOR_DFT_WM,
3037         2,
3038         G4X_FIFO_LINE_SIZE,
3039 };
3040 static struct intel_watermark_params i965_cursor_wm_info = {
3041         I965_CURSOR_FIFO,
3042         I965_CURSOR_MAX_WM,
3043         I965_CURSOR_DFT_WM,
3044         2,
3045         I915_FIFO_LINE_SIZE,
3046 };
3047 static struct intel_watermark_params i945_wm_info = {
3048         I945_FIFO_SIZE,
3049         I915_MAX_WM,
3050         1,
3051         2,
3052         I915_FIFO_LINE_SIZE
3053 };
3054 static struct intel_watermark_params i915_wm_info = {
3055         I915_FIFO_SIZE,
3056         I915_MAX_WM,
3057         1,
3058         2,
3059         I915_FIFO_LINE_SIZE
3060 };
3061 static struct intel_watermark_params i855_wm_info = {
3062         I855GM_FIFO_SIZE,
3063         I915_MAX_WM,
3064         1,
3065         2,
3066         I830_FIFO_LINE_SIZE
3067 };
3068 static struct intel_watermark_params i830_wm_info = {
3069         I830_FIFO_SIZE,
3070         I915_MAX_WM,
3071         1,
3072         2,
3073         I830_FIFO_LINE_SIZE
3074 };
3075
3076 static struct intel_watermark_params ironlake_display_wm_info = {
3077         ILK_DISPLAY_FIFO,
3078         ILK_DISPLAY_MAXWM,
3079         ILK_DISPLAY_DFTWM,
3080         2,
3081         ILK_FIFO_LINE_SIZE
3082 };
3083
3084 static struct intel_watermark_params ironlake_cursor_wm_info = {
3085         ILK_CURSOR_FIFO,
3086         ILK_CURSOR_MAXWM,
3087         ILK_CURSOR_DFTWM,
3088         2,
3089         ILK_FIFO_LINE_SIZE
3090 };
3091
3092 static struct intel_watermark_params ironlake_display_srwm_info = {
3093         ILK_DISPLAY_SR_FIFO,
3094         ILK_DISPLAY_MAX_SRWM,
3095         ILK_DISPLAY_DFT_SRWM,
3096         2,
3097         ILK_FIFO_LINE_SIZE
3098 };
3099
3100 static struct intel_watermark_params ironlake_cursor_srwm_info = {
3101         ILK_CURSOR_SR_FIFO,
3102         ILK_CURSOR_MAX_SRWM,
3103         ILK_CURSOR_DFT_SRWM,
3104         2,
3105         ILK_FIFO_LINE_SIZE
3106 };
3107
3108 static struct intel_watermark_params sandybridge_display_wm_info = {
3109         SNB_DISPLAY_FIFO,
3110         SNB_DISPLAY_MAXWM,
3111         SNB_DISPLAY_DFTWM,
3112         2,
3113         SNB_FIFO_LINE_SIZE
3114 };
3115
3116 static struct intel_watermark_params sandybridge_cursor_wm_info = {
3117         SNB_CURSOR_FIFO,
3118         SNB_CURSOR_MAXWM,
3119         SNB_CURSOR_DFTWM,
3120         2,
3121         SNB_FIFO_LINE_SIZE
3122 };
3123
3124 static struct intel_watermark_params sandybridge_display_srwm_info = {
3125         SNB_DISPLAY_SR_FIFO,
3126         SNB_DISPLAY_MAX_SRWM,
3127         SNB_DISPLAY_DFT_SRWM,
3128         2,
3129         SNB_FIFO_LINE_SIZE
3130 };
3131
3132 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
3133         SNB_CURSOR_SR_FIFO,
3134         SNB_CURSOR_MAX_SRWM,
3135         SNB_CURSOR_DFT_SRWM,
3136         2,
3137         SNB_FIFO_LINE_SIZE
3138 };
3139
3140
3141 /**
3142  * intel_calculate_wm - calculate watermark level
3143  * @clock_in_khz: pixel clock
3144  * @wm: chip FIFO params
3145  * @pixel_size: display pixel size
3146  * @latency_ns: memory latency for the platform
3147  *
3148  * Calculate the watermark level (the level at which the display plane will
3149  * start fetching from memory again).  Each chip has a different display
3150  * FIFO size and allocation, so the caller needs to figure that out and pass
3151  * in the correct intel_watermark_params structure.
3152  *
3153  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3154  * on the pixel size.  When it reaches the watermark level, it'll start
3155  * fetching FIFO line sized based chunks from memory until the FIFO fills
3156  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3157  * will occur, and a display engine hang could result.
3158  */
3159 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3160                                         struct intel_watermark_params *wm,
3161                                         int pixel_size,
3162                                         unsigned long latency_ns)
3163 {
3164         long entries_required, wm_size;
3165
3166         /*
3167          * Note: we need to make sure we don't overflow for various clock &
3168          * latency values.
3169          * clocks go from a few thousand to several hundred thousand.
3170          * latency is usually a few thousand
3171          */
3172         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3173                 1000;
3174         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3175
3176         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3177
3178         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
3179
3180         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3181
3182         /* Don't promote wm_size to unsigned... */
3183         if (wm_size > (long)wm->max_wm)
3184                 wm_size = wm->max_wm;
3185         if (wm_size <= 0)
3186                 wm_size = wm->default_wm;
3187         return wm_size;
3188 }
3189
3190 struct cxsr_latency {
3191         int is_desktop;
3192         int is_ddr3;
3193         unsigned long fsb_freq;
3194         unsigned long mem_freq;
3195         unsigned long display_sr;
3196         unsigned long display_hpll_disable;
3197         unsigned long cursor_sr;
3198         unsigned long cursor_hpll_disable;
3199 };
3200
3201 static const struct cxsr_latency cxsr_latency_table[] = {
3202         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3203         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3204         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3205         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3206         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3207
3208         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3209         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3210         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3211         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3212         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3213
3214         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3215         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3216         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3217         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3218         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3219
3220         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3221         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3222         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3223         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3224         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3225
3226         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3227         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3228         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3229         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3230         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3231
3232         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3233         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3234         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3235         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3236         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3237 };
3238
3239 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3240                                                          int is_ddr3,
3241                                                          int fsb,
3242                                                          int mem)
3243 {
3244         const struct cxsr_latency *latency;
3245         int i;
3246
3247         if (fsb == 0 || mem == 0)
3248                 return NULL;
3249
3250         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3251                 latency = &cxsr_latency_table[i];
3252                 if (is_desktop == latency->is_desktop &&
3253                     is_ddr3 == latency->is_ddr3 &&
3254                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3255                         return latency;
3256         }
3257
3258         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3259
3260         return NULL;
3261 }
3262
3263 static void pineview_disable_cxsr(struct drm_device *dev)
3264 {
3265         struct drm_i915_private *dev_priv = dev->dev_private;
3266
3267         /* deactivate cxsr */
3268         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3269 }
3270
3271 /*
3272  * Latency for FIFO fetches is dependent on several factors:
3273  *   - memory configuration (speed, channels)
3274  *   - chipset
3275  *   - current MCH state
3276  * It can be fairly high in some situations, so here we assume a fairly
3277  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3278  * set this value too high, the FIFO will fetch frequently to stay full)
3279  * and power consumption (set it too low to save power and we might see
3280  * FIFO underruns and display "flicker").
3281  *
3282  * A value of 5us seems to be a good balance; safe for very low end
3283  * platforms but not overly aggressive on lower latency configs.
3284  */
3285 static const int latency_ns = 5000;
3286
3287 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3288 {
3289         struct drm_i915_private *dev_priv = dev->dev_private;
3290         uint32_t dsparb = I915_READ(DSPARB);
3291         int size;
3292
3293         size = dsparb & 0x7f;
3294         if (plane)
3295                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3296
3297         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3298                       plane ? "B" : "A", size);
3299
3300         return size;
3301 }
3302
3303 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3304 {
3305         struct drm_i915_private *dev_priv = dev->dev_private;
3306         uint32_t dsparb = I915_READ(DSPARB);
3307         int size;
3308
3309         size = dsparb & 0x1ff;
3310         if (plane)
3311                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3312         size >>= 1; /* Convert to cachelines */
3313
3314         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3315                       plane ? "B" : "A", size);
3316
3317         return size;
3318 }
3319
3320 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3321 {
3322         struct drm_i915_private *dev_priv = dev->dev_private;
3323         uint32_t dsparb = I915_READ(DSPARB);
3324         int size;
3325
3326         size = dsparb & 0x7f;
3327         size >>= 2; /* Convert to cachelines */
3328
3329         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3330                       plane ? "B" : "A",
3331                       size);
3332
3333         return size;
3334 }
3335
3336 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3337 {
3338         struct drm_i915_private *dev_priv = dev->dev_private;
3339         uint32_t dsparb = I915_READ(DSPARB);
3340         int size;
3341
3342         size = dsparb & 0x7f;
3343         size >>= 1; /* Convert to cachelines */
3344
3345         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3346                       plane ? "B" : "A", size);
3347
3348         return size;
3349 }
3350
3351 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3352                                int planeb_clock, int sr_hdisplay, int unused,
3353                                int pixel_size)
3354 {
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         const struct cxsr_latency *latency;
3357         u32 reg;
3358         unsigned long wm;
3359         int sr_clock;
3360
3361         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3362                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3363         if (!latency) {
3364                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3365                 pineview_disable_cxsr(dev);
3366                 return;
3367         }
3368
3369         if (!planea_clock || !planeb_clock) {
3370                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3371
3372                 /* Display SR */
3373                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3374                                         pixel_size, latency->display_sr);
3375                 reg = I915_READ(DSPFW1);
3376                 reg &= ~DSPFW_SR_MASK;
3377                 reg |= wm << DSPFW_SR_SHIFT;
3378                 I915_WRITE(DSPFW1, reg);
3379                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3380
3381                 /* cursor SR */
3382                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3383                                         pixel_size, latency->cursor_sr);
3384                 reg = I915_READ(DSPFW3);
3385                 reg &= ~DSPFW_CURSOR_SR_MASK;
3386                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3387                 I915_WRITE(DSPFW3, reg);
3388
3389                 /* Display HPLL off SR */
3390                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3391                                         pixel_size, latency->display_hpll_disable);
3392                 reg = I915_READ(DSPFW3);
3393                 reg &= ~DSPFW_HPLL_SR_MASK;
3394                 reg |= wm & DSPFW_HPLL_SR_MASK;
3395                 I915_WRITE(DSPFW3, reg);
3396
3397                 /* cursor HPLL off SR */
3398                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3399                                         pixel_size, latency->cursor_hpll_disable);
3400                 reg = I915_READ(DSPFW3);
3401                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3402                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3403                 I915_WRITE(DSPFW3, reg);
3404                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3405
3406                 /* activate cxsr */
3407                 I915_WRITE(DSPFW3,
3408                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3409                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3410         } else {
3411                 pineview_disable_cxsr(dev);
3412                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3413         }
3414 }
3415
3416 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3417                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3418                           int pixel_size)
3419 {
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         int total_size, cacheline_size;
3422         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3423         struct intel_watermark_params planea_params, planeb_params;
3424         unsigned long line_time_us;
3425         int sr_clock, sr_entries = 0, entries_required;
3426
3427         /* Create copies of the base settings for each pipe */
3428         planea_params = planeb_params = g4x_wm_info;
3429
3430         /* Grab a couple of global values before we overwrite them */
3431         total_size = planea_params.fifo_size;
3432         cacheline_size = planea_params.cacheline_size;
3433
3434         /*
3435          * Note: we need to make sure we don't overflow for various clock &
3436          * latency values.
3437          * clocks go from a few thousand to several hundred thousand.
3438          * latency is usually a few thousand
3439          */
3440         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3441                 1000;
3442         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3443         planea_wm = entries_required + planea_params.guard_size;
3444
3445         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3446                 1000;
3447         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3448         planeb_wm = entries_required + planeb_params.guard_size;
3449
3450         cursora_wm = cursorb_wm = 16;
3451         cursor_sr = 32;
3452
3453         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3454
3455         /* Calc sr entries for one plane configs */
3456         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3457                 /* self-refresh has much higher latency */
3458                 static const int sr_latency_ns = 12000;
3459
3460                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3461                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3462
3463                 /* Use ns/us then divide to preserve precision */
3464                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3465                         pixel_size * sr_hdisplay;
3466                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3467
3468                 entries_required = (((sr_latency_ns / line_time_us) +
3469                                      1000) / 1000) * pixel_size * 64;
3470                 entries_required = DIV_ROUND_UP(entries_required,
3471                                                 g4x_cursor_wm_info.cacheline_size);
3472                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3473
3474                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3475                         cursor_sr = g4x_cursor_wm_info.max_wm;
3476                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3477                               "cursor %d\n", sr_entries, cursor_sr);
3478
3479                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3480         } else {
3481                 /* Turn off self refresh if both pipes are enabled */
3482                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3483                            & ~FW_BLC_SELF_EN);
3484         }
3485
3486         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3487                   planea_wm, planeb_wm, sr_entries);
3488
3489         planea_wm &= 0x3f;
3490         planeb_wm &= 0x3f;
3491
3492         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3493                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3494                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3495         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3496                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3497         /* HPLL off in SR has some issues on G4x... disable it */
3498         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3499                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3500 }
3501
3502 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3503                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3504                            int pixel_size)
3505 {
3506         struct drm_i915_private *dev_priv = dev->dev_private;
3507         unsigned long line_time_us;
3508         int sr_clock, sr_entries, srwm = 1;
3509         int cursor_sr = 16;
3510
3511         /* Calc sr entries for one plane configs */
3512         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3513                 /* self-refresh has much higher latency */
3514                 static const int sr_latency_ns = 12000;
3515
3516                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3517                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3518
3519                 /* Use ns/us then divide to preserve precision */
3520                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3521                         pixel_size * sr_hdisplay;
3522                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3523                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3524                 srwm = I965_FIFO_SIZE - sr_entries;
3525                 if (srwm < 0)
3526                         srwm = 1;
3527                 srwm &= 0x1ff;
3528
3529                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3530                         pixel_size * 64;
3531                 sr_entries = DIV_ROUND_UP(sr_entries,
3532                                           i965_cursor_wm_info.cacheline_size);
3533                 cursor_sr = i965_cursor_wm_info.fifo_size -
3534                         (sr_entries + i965_cursor_wm_info.guard_size);
3535
3536                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3537                         cursor_sr = i965_cursor_wm_info.max_wm;
3538
3539                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3540                               "cursor %d\n", srwm, cursor_sr);
3541
3542                 if (IS_CRESTLINE(dev))
3543                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3544         } else {
3545                 /* Turn off self refresh if both pipes are enabled */
3546                 if (IS_CRESTLINE(dev))
3547                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3548                                    & ~FW_BLC_SELF_EN);
3549         }
3550
3551         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3552                       srwm);
3553
3554         /* 965 has limitations... */
3555         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3556                    (8 << 0));
3557         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3558         /* update cursor SR watermark */
3559         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3560 }
3561
3562 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3563                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3564                            int pixel_size)
3565 {
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567         uint32_t fwater_lo;
3568         uint32_t fwater_hi;
3569         int total_size, cacheline_size, cwm, srwm = 1;
3570         int planea_wm, planeb_wm;
3571         struct intel_watermark_params planea_params, planeb_params;
3572         unsigned long line_time_us;
3573         int sr_clock, sr_entries = 0;
3574
3575         /* Create copies of the base settings for each pipe */
3576         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3577                 planea_params = planeb_params = i945_wm_info;
3578         else if (!IS_GEN2(dev))
3579                 planea_params = planeb_params = i915_wm_info;
3580         else
3581                 planea_params = planeb_params = i855_wm_info;
3582
3583         /* Grab a couple of global values before we overwrite them */
3584         total_size = planea_params.fifo_size;
3585         cacheline_size = planea_params.cacheline_size;
3586
3587         /* Update per-plane FIFO sizes */
3588         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3589         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3590
3591         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3592                                        pixel_size, latency_ns);
3593         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3594                                        pixel_size, latency_ns);
3595         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3596
3597         /*
3598          * Overlay gets an aggressive default since video jitter is bad.
3599          */
3600         cwm = 2;
3601
3602         /* Calc sr entries for one plane configs */
3603         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3604             (!planea_clock || !planeb_clock)) {
3605                 /* self-refresh has much higher latency */
3606                 static const int sr_latency_ns = 6000;
3607
3608                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3609                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3610
3611                 /* Use ns/us then divide to preserve precision */
3612                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3613                         pixel_size * sr_hdisplay;
3614                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3615                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3616                 srwm = total_size - sr_entries;
3617                 if (srwm < 0)
3618                         srwm = 1;
3619
3620                 if (IS_I945G(dev) || IS_I945GM(dev))
3621                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3622                 else if (IS_I915GM(dev)) {
3623                         /* 915M has a smaller SRWM field */
3624                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3625                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3626                 }
3627         } else {
3628                 /* Turn off self refresh if both pipes are enabled */
3629                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3630                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3631                                    & ~FW_BLC_SELF_EN);
3632                 } else if (IS_I915GM(dev)) {
3633                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3634                 }
3635         }
3636
3637         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3638                       planea_wm, planeb_wm, cwm, srwm);
3639
3640         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3641         fwater_hi = (cwm & 0x1f);
3642
3643         /* Set request length to 8 cachelines per fetch */
3644         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3645         fwater_hi = fwater_hi | (1 << 8);
3646
3647         I915_WRITE(FW_BLC, fwater_lo);
3648         I915_WRITE(FW_BLC2, fwater_hi);
3649 }
3650
3651 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3652                            int unused2, int unused3, int pixel_size)
3653 {
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3656         int planea_wm;
3657
3658         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3659
3660         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3661                                        pixel_size, latency_ns);
3662         fwater_lo |= (3<<8) | planea_wm;
3663
3664         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3665
3666         I915_WRITE(FW_BLC, fwater_lo);
3667 }
3668
3669 #define ILK_LP0_PLANE_LATENCY           700
3670 #define ILK_LP0_CURSOR_LATENCY          1300
3671
3672 static bool ironlake_compute_wm0(struct drm_device *dev,
3673                                  int pipe,
3674                                  const struct intel_watermark_params *display,
3675                                  int display_latency_ns,
3676                                  const struct intel_watermark_params *cursor,
3677                                  int cursor_latency_ns,
3678                                  int *plane_wm,
3679                                  int *cursor_wm)
3680 {
3681         struct drm_crtc *crtc;
3682         int htotal, hdisplay, clock, pixel_size;
3683         int line_time_us, line_count;
3684         int entries, tlb_miss;
3685
3686         crtc = intel_get_crtc_for_pipe(dev, pipe);
3687         if (crtc->fb == NULL || !crtc->enabled)
3688                 return false;
3689
3690         htotal = crtc->mode.htotal;
3691         hdisplay = crtc->mode.hdisplay;
3692         clock = crtc->mode.clock;
3693         pixel_size = crtc->fb->bits_per_pixel / 8;
3694
3695         /* Use the small buffer method to calculate plane watermark */
3696         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3697         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3698         if (tlb_miss > 0)
3699                 entries += tlb_miss;
3700         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3701         *plane_wm = entries + display->guard_size;
3702         if (*plane_wm > (int)display->max_wm)
3703                 *plane_wm = display->max_wm;
3704
3705         /* Use the large buffer method to calculate cursor watermark */
3706         line_time_us = ((htotal * 1000) / clock);
3707         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3708         entries = line_count * 64 * pixel_size;
3709         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3710         if (tlb_miss > 0)
3711                 entries += tlb_miss;
3712         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3713         *cursor_wm = entries + cursor->guard_size;
3714         if (*cursor_wm > (int)cursor->max_wm)
3715                 *cursor_wm = (int)cursor->max_wm;
3716
3717         return true;
3718 }
3719
3720 /*
3721  * Check the wm result.
3722  *
3723  * If any calculated watermark values is larger than the maximum value that
3724  * can be programmed into the associated watermark register, that watermark
3725  * must be disabled.
3726  */
3727 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3728                                 int fbc_wm, int display_wm, int cursor_wm,
3729                                 const struct intel_watermark_params *display,
3730                                 const struct intel_watermark_params *cursor)
3731 {
3732         struct drm_i915_private *dev_priv = dev->dev_private;
3733
3734         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3735                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3736
3737         if (fbc_wm > SNB_FBC_MAX_SRWM) {
3738                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3739                               fbc_wm, SNB_FBC_MAX_SRWM, level);
3740
3741                 /* fbc has it's own way to disable FBC WM */
3742                 I915_WRITE(DISP_ARB_CTL,
3743                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3744                 return false;
3745         }
3746
3747         if (display_wm > display->max_wm) {
3748                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3749                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
3750                 return false;
3751         }
3752
3753         if (cursor_wm > cursor->max_wm) {
3754                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3755                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3756                 return false;
3757         }
3758
3759         if (!(fbc_wm || display_wm || cursor_wm)) {
3760                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3761                 return false;
3762         }
3763
3764         return true;
3765 }
3766
3767 /*
3768  * Compute watermark values of WM[1-3],
3769  */
3770 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3771                                   int hdisplay, int htotal,
3772                                   int pixel_size, int clock, int latency_ns,
3773                                   const struct intel_watermark_params *display,
3774                                   const struct intel_watermark_params *cursor,
3775                                   int *fbc_wm, int *display_wm, int *cursor_wm)
3776 {
3777
3778         unsigned long line_time_us;
3779         int line_count, line_size;
3780         int small, large;
3781         int entries;
3782
3783         if (!latency_ns) {
3784                 *fbc_wm = *display_wm = *cursor_wm = 0;
3785                 return false;
3786         }
3787
3788         line_time_us = (htotal * 1000) / clock;
3789         line_count = (latency_ns / line_time_us + 1000) / 1000;
3790         line_size = hdisplay * pixel_size;
3791
3792         /* Use the minimum of the small and large buffer method for primary */
3793         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3794         large = line_count * line_size;
3795
3796         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3797         *display_wm = entries + display->guard_size;
3798
3799         /*
3800          * Spec says:
3801          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3802          */
3803         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3804
3805         /* calculate the self-refresh watermark for display cursor */
3806         entries = line_count * pixel_size * 64;
3807         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3808         *cursor_wm = entries + cursor->guard_size;
3809
3810         return ironlake_check_srwm(dev, level,
3811                                    *fbc_wm, *display_wm, *cursor_wm,
3812                                    display, cursor);
3813 }
3814
3815 static void ironlake_update_wm(struct drm_device *dev,
3816                                int planea_clock, int planeb_clock,
3817                                int hdisplay, int htotal,
3818                                int pixel_size)
3819 {
3820         struct drm_i915_private *dev_priv = dev->dev_private;
3821         int fbc_wm, plane_wm, cursor_wm, enabled;
3822         int clock;
3823
3824         enabled = 0;
3825         if (ironlake_compute_wm0(dev, 0,
3826                                  &ironlake_display_wm_info,
3827                                  ILK_LP0_PLANE_LATENCY,
3828                                  &ironlake_cursor_wm_info,
3829                                  ILK_LP0_CURSOR_LATENCY,
3830                                  &plane_wm, &cursor_wm)) {
3831                 I915_WRITE(WM0_PIPEA_ILK,
3832                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3833                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3834                               " plane %d, " "cursor: %d\n",
3835                               plane_wm, cursor_wm);
3836                 enabled++;
3837         }
3838
3839         if (ironlake_compute_wm0(dev, 1,
3840                                  &ironlake_display_wm_info,
3841                                  ILK_LP0_PLANE_LATENCY,
3842                                  &ironlake_cursor_wm_info,
3843                                  ILK_LP0_CURSOR_LATENCY,
3844                                  &plane_wm, &cursor_wm)) {
3845                 I915_WRITE(WM0_PIPEB_ILK,
3846                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3847                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3848                               " plane %d, cursor: %d\n",
3849                               plane_wm, cursor_wm);
3850                 enabled++;
3851         }
3852
3853         /*
3854          * Calculate and update the self-refresh watermark only when one
3855          * display plane is used.
3856          */
3857         I915_WRITE(WM3_LP_ILK, 0);
3858         I915_WRITE(WM2_LP_ILK, 0);
3859         I915_WRITE(WM1_LP_ILK, 0);
3860
3861         if (enabled != 1)
3862                 return;
3863
3864         clock = planea_clock ? planea_clock : planeb_clock;
3865
3866         /* WM1 */
3867         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3868                                    clock, ILK_READ_WM1_LATENCY() * 500,
3869                                    &ironlake_display_srwm_info,
3870                                    &ironlake_cursor_srwm_info,
3871                                    &fbc_wm, &plane_wm, &cursor_wm))
3872                 return;
3873
3874         I915_WRITE(WM1_LP_ILK,
3875                    WM1_LP_SR_EN |
3876                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3877                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3878                    (plane_wm << WM1_LP_SR_SHIFT) |
3879                    cursor_wm);
3880
3881         /* WM2 */
3882         if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
3883                                    clock, ILK_READ_WM2_LATENCY() * 500,
3884                                    &ironlake_display_srwm_info,
3885                                    &ironlake_cursor_srwm_info,
3886                                    &fbc_wm, &plane_wm, &cursor_wm))
3887                 return;
3888
3889         I915_WRITE(WM2_LP_ILK,
3890                    WM2_LP_EN |
3891                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3892                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3893                    (plane_wm << WM1_LP_SR_SHIFT) |
3894                    cursor_wm);
3895
3896         /*
3897          * WM3 is unsupported on ILK, probably because we don't have latency
3898          * data for that power state
3899          */
3900 }
3901
3902 static void sandybridge_update_wm(struct drm_device *dev,
3903                                int planea_clock, int planeb_clock,
3904                                int hdisplay, int htotal,
3905                                int pixel_size)
3906 {
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
3909         int fbc_wm, plane_wm, cursor_wm, enabled;
3910         int clock;
3911
3912         enabled = 0;
3913         if (ironlake_compute_wm0(dev, 0,
3914                                  &sandybridge_display_wm_info, latency,
3915                                  &sandybridge_cursor_wm_info, latency,
3916                                  &plane_wm, &cursor_wm)) {
3917                 I915_WRITE(WM0_PIPEA_ILK,
3918                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3919                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3920                               " plane %d, " "cursor: %d\n",
3921                               plane_wm, cursor_wm);
3922                 enabled++;
3923         }
3924
3925         if (ironlake_compute_wm0(dev, 1,
3926                                  &sandybridge_display_wm_info, latency,
3927                                  &sandybridge_cursor_wm_info, latency,
3928                                  &plane_wm, &cursor_wm)) {
3929                 I915_WRITE(WM0_PIPEB_ILK,
3930                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3931                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3932                               " plane %d, cursor: %d\n",
3933                               plane_wm, cursor_wm);
3934                 enabled++;
3935         }
3936
3937         /*
3938          * Calculate and update the self-refresh watermark only when one
3939          * display plane is used.
3940          *
3941          * SNB support 3 levels of watermark.
3942          *
3943          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
3944          * and disabled in the descending order
3945          *
3946          */
3947         I915_WRITE(WM3_LP_ILK, 0);
3948         I915_WRITE(WM2_LP_ILK, 0);
3949         I915_WRITE(WM1_LP_ILK, 0);
3950
3951         if (enabled != 1)
3952                 return;
3953
3954         clock = planea_clock ? planea_clock : planeb_clock;
3955
3956         /* WM1 */
3957         if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3958                                    clock, SNB_READ_WM1_LATENCY() * 500,
3959                                    &sandybridge_display_srwm_info,
3960                                    &sandybridge_cursor_srwm_info,
3961                                    &fbc_wm, &plane_wm, &cursor_wm))
3962                 return;
3963
3964         I915_WRITE(WM1_LP_ILK,
3965                    WM1_LP_SR_EN |
3966                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3967                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3968                    (plane_wm << WM1_LP_SR_SHIFT) |
3969                    cursor_wm);
3970
3971         /* WM2 */
3972         if (!ironlake_compute_srwm(dev, 2,
3973                                    hdisplay, htotal, pixel_size,
3974                                    clock, SNB_READ_WM2_LATENCY() * 500,
3975                                    &sandybridge_display_srwm_info,
3976                                    &sandybridge_cursor_srwm_info,
3977                                    &fbc_wm, &plane_wm, &cursor_wm))
3978                 return;
3979
3980         I915_WRITE(WM2_LP_ILK,
3981                    WM2_LP_EN |
3982                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3983                    (fbc_wm << WM1_LP_FBC_SHIFT) |
3984                    (plane_wm << WM1_LP_SR_SHIFT) |
3985                    cursor_wm);
3986
3987         /* WM3 */
3988         if (!ironlake_compute_srwm(dev, 3,
3989                                    hdisplay, htotal, pixel_size,
3990                                    clock, SNB_READ_WM3_LATENCY() * 500,
3991                                    &sandybridge_display_srwm_info,
3992                                    &sandybridge_cursor_srwm_info,
3993                                    &fbc_wm, &plane_wm, &cursor_wm))
3994                 return;
3995
3996         I915_WRITE(WM3_LP_ILK,
3997                    WM3_LP_EN |
3998                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3999                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4000                    (plane_wm << WM1_LP_SR_SHIFT) |
4001                    cursor_wm);
4002 }
4003
4004 /**
4005  * intel_update_watermarks - update FIFO watermark values based on current modes
4006  *
4007  * Calculate watermark values for the various WM regs based on current mode
4008  * and plane configuration.
4009  *
4010  * There are several cases to deal with here:
4011  *   - normal (i.e. non-self-refresh)
4012  *   - self-refresh (SR) mode
4013  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4014  *   - lines are small relative to FIFO size (buffer can hold more than 2
4015  *     lines), so need to account for TLB latency
4016  *
4017  *   The normal calculation is:
4018  *     watermark = dotclock * bytes per pixel * latency
4019  *   where latency is platform & configuration dependent (we assume pessimal
4020  *   values here).
4021  *
4022  *   The SR calculation is:
4023  *     watermark = (trunc(latency/line time)+1) * surface width *
4024  *       bytes per pixel
4025  *   where
4026  *     line time = htotal / dotclock
4027  *     surface width = hdisplay for normal plane and 64 for cursor
4028  *   and latency is assumed to be high, as above.
4029  *
4030  * The final value programmed to the register should always be rounded up,
4031  * and include an extra 2 entries to account for clock crossings.
4032  *
4033  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4034  * to set the non-SR watermarks to 8.
4035  */
4036 static void intel_update_watermarks(struct drm_device *dev)
4037 {
4038         struct drm_i915_private *dev_priv = dev->dev_private;
4039         struct drm_crtc *crtc;
4040         int sr_hdisplay = 0;
4041         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
4042         int enabled = 0, pixel_size = 0;
4043         int sr_htotal = 0;
4044
4045         if (!dev_priv->display.update_wm)
4046                 return;
4047
4048         /* Get the clock config from both planes */
4049         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4050                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4051                 if (intel_crtc->active) {
4052                         enabled++;
4053                         if (intel_crtc->plane == 0) {
4054                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
4055                                               intel_crtc->pipe, crtc->mode.clock);
4056                                 planea_clock = crtc->mode.clock;
4057                         } else {
4058                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
4059                                               intel_crtc->pipe, crtc->mode.clock);
4060                                 planeb_clock = crtc->mode.clock;
4061                         }
4062                         sr_hdisplay = crtc->mode.hdisplay;
4063                         sr_clock = crtc->mode.clock;
4064                         sr_htotal = crtc->mode.htotal;
4065                         if (crtc->fb)
4066                                 pixel_size = crtc->fb->bits_per_pixel / 8;
4067                         else
4068                                 pixel_size = 4; /* by default */
4069                 }
4070         }
4071
4072         if (enabled <= 0)
4073                 return;
4074
4075         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
4076                                     sr_hdisplay, sr_htotal, pixel_size);
4077 }
4078
4079 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4080 {
4081         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4082 }
4083
4084 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4085                                struct drm_display_mode *mode,
4086                                struct drm_display_mode *adjusted_mode,
4087                                int x, int y,
4088                                struct drm_framebuffer *old_fb)
4089 {
4090         struct drm_device *dev = crtc->dev;
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093         int pipe = intel_crtc->pipe;
4094         int plane = intel_crtc->plane;
4095         u32 fp_reg, dpll_reg;
4096         int refclk, num_connectors = 0;
4097         intel_clock_t clock, reduced_clock;
4098         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4099         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4100         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4101         struct intel_encoder *has_edp_encoder = NULL;
4102         struct drm_mode_config *mode_config = &dev->mode_config;
4103         struct intel_encoder *encoder;
4104         const intel_limit_t *limit;
4105         int ret;
4106         struct fdi_m_n m_n = {0};
4107         u32 reg, temp;
4108         int target_clock;
4109
4110         drm_vblank_pre_modeset(dev, pipe);
4111
4112         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4113                 if (encoder->base.crtc != crtc)
4114                         continue;
4115
4116                 switch (encoder->type) {
4117                 case INTEL_OUTPUT_LVDS:
4118                         is_lvds = true;
4119                         break;
4120                 case INTEL_OUTPUT_SDVO:
4121                 case INTEL_OUTPUT_HDMI:
4122                         is_sdvo = true;
4123                         if (encoder->needs_tv_clock)
4124                                 is_tv = true;
4125                         break;
4126                 case INTEL_OUTPUT_DVO:
4127                         is_dvo = true;
4128                         break;
4129                 case INTEL_OUTPUT_TVOUT:
4130                         is_tv = true;
4131                         break;
4132                 case INTEL_OUTPUT_ANALOG:
4133                         is_crt = true;
4134                         break;
4135                 case INTEL_OUTPUT_DISPLAYPORT:
4136                         is_dp = true;
4137                         break;
4138                 case INTEL_OUTPUT_EDP:
4139                         has_edp_encoder = encoder;
4140                         break;
4141                 }
4142
4143                 num_connectors++;
4144         }
4145
4146         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4147                 refclk = dev_priv->lvds_ssc_freq * 1000;
4148                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4149                               refclk / 1000);
4150         } else if (!IS_GEN2(dev)) {
4151                 refclk = 96000;
4152                 if (HAS_PCH_SPLIT(dev) &&
4153                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4154                         refclk = 120000; /* 120Mhz refclk */
4155         } else {
4156                 refclk = 48000;
4157         }
4158
4159         /*
4160          * Returns a set of divisors for the desired target clock with the given
4161          * refclk, or FALSE.  The returned values represent the clock equation:
4162          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4163          */
4164         limit = intel_limit(crtc, refclk);
4165         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4166         if (!ok) {
4167                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4168                 drm_vblank_post_modeset(dev, pipe);
4169                 return -EINVAL;
4170         }
4171
4172         /* Ensure that the cursor is valid for the new mode before changing... */
4173         intel_crtc_update_cursor(crtc, true);
4174
4175         if (is_lvds && dev_priv->lvds_downclock_avail) {
4176                 has_reduced_clock = limit->find_pll(limit, crtc,
4177                                                     dev_priv->lvds_downclock,
4178                                                     refclk,
4179                                                     &reduced_clock);
4180                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4181                         /*
4182                          * If the different P is found, it means that we can't
4183                          * switch the display clock by using the FP0/FP1.
4184                          * In such case we will disable the LVDS downclock
4185                          * feature.
4186                          */
4187                         DRM_DEBUG_KMS("Different P is found for "
4188                                       "LVDS clock/downclock\n");
4189                         has_reduced_clock = 0;
4190                 }
4191         }
4192         /* SDVO TV has fixed PLL values depend on its clock range,
4193            this mirrors vbios setting. */
4194         if (is_sdvo && is_tv) {
4195                 if (adjusted_mode->clock >= 100000
4196                     && adjusted_mode->clock < 140500) {
4197                         clock.p1 = 2;
4198                         clock.p2 = 10;
4199                         clock.n = 3;
4200                         clock.m1 = 16;
4201                         clock.m2 = 8;
4202                 } else if (adjusted_mode->clock >= 140500
4203                            && adjusted_mode->clock <= 200000) {
4204                         clock.p1 = 1;
4205                         clock.p2 = 10;
4206                         clock.n = 6;
4207                         clock.m1 = 12;
4208                         clock.m2 = 8;
4209                 }
4210         }
4211
4212         /* FDI link */
4213         if (HAS_PCH_SPLIT(dev)) {
4214                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4215                 int lane = 0, link_bw, bpp;
4216                 /* CPU eDP doesn't require FDI link, so just set DP M/N
4217                    according to current link config */
4218                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4219                         target_clock = mode->clock;
4220                         intel_edp_link_config(has_edp_encoder,
4221                                               &lane, &link_bw);
4222                 } else {
4223                         /* [e]DP over FDI requires target mode clock
4224                            instead of link clock */
4225                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4226                                 target_clock = mode->clock;
4227                         else
4228                                 target_clock = adjusted_mode->clock;
4229
4230                         /* FDI is a binary signal running at ~2.7GHz, encoding
4231                          * each output octet as 10 bits. The actual frequency
4232                          * is stored as a divider into a 100MHz clock, and the
4233                          * mode pixel clock is stored in units of 1KHz.
4234                          * Hence the bw of each lane in terms of the mode signal
4235                          * is:
4236                          */
4237                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4238                 }
4239
4240                 /* determine panel color depth */
4241                 temp = I915_READ(PIPECONF(pipe));
4242                 temp &= ~PIPE_BPC_MASK;
4243                 if (is_lvds) {
4244                         /* the BPC will be 6 if it is 18-bit LVDS panel */
4245                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4246                                 temp |= PIPE_8BPC;
4247                         else
4248                                 temp |= PIPE_6BPC;
4249                 } else if (has_edp_encoder) {
4250                         switch (dev_priv->edp.bpp/3) {
4251                         case 8:
4252                                 temp |= PIPE_8BPC;
4253                                 break;
4254                         case 10:
4255                                 temp |= PIPE_10BPC;
4256                                 break;
4257                         case 6:
4258                                 temp |= PIPE_6BPC;
4259                                 break;
4260                         case 12:
4261                                 temp |= PIPE_12BPC;
4262                                 break;
4263                         }
4264                 } else
4265                         temp |= PIPE_8BPC;
4266                 I915_WRITE(PIPECONF(pipe), temp);
4267
4268                 switch (temp & PIPE_BPC_MASK) {
4269                 case PIPE_8BPC:
4270                         bpp = 24;
4271                         break;
4272                 case PIPE_10BPC:
4273                         bpp = 30;
4274                         break;
4275                 case PIPE_6BPC:
4276                         bpp = 18;
4277                         break;
4278                 case PIPE_12BPC:
4279                         bpp = 36;
4280                         break;
4281                 default:
4282                         DRM_ERROR("unknown pipe bpc value\n");
4283                         bpp = 24;
4284                 }
4285
4286                 if (!lane) {
4287                         /*
4288                          * Account for spread spectrum to avoid
4289                          * oversubscribing the link. Max center spread
4290                          * is 2.5%; use 5% for safety's sake.
4291                          */
4292                         u32 bps = target_clock * bpp * 21 / 20;
4293                         lane = bps / (link_bw * 8) + 1;
4294                 }
4295
4296                 intel_crtc->fdi_lanes = lane;
4297
4298                 if (pixel_multiplier > 1)
4299                         link_bw *= pixel_multiplier;
4300                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4301         }
4302
4303         /* Ironlake: try to setup display ref clock before DPLL
4304          * enabling. This is only under driver's control after
4305          * PCH B stepping, previous chipset stepping should be
4306          * ignoring this setting.
4307          */
4308         if (HAS_PCH_SPLIT(dev)) {
4309                 temp = I915_READ(PCH_DREF_CONTROL);
4310                 /* Always enable nonspread source */
4311                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4312                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4313                 temp &= ~DREF_SSC_SOURCE_MASK;
4314                 temp |= DREF_SSC_SOURCE_ENABLE;
4315                 I915_WRITE(PCH_DREF_CONTROL, temp);
4316
4317                 POSTING_READ(PCH_DREF_CONTROL);
4318                 udelay(200);
4319
4320                 if (has_edp_encoder) {
4321                         if (intel_panel_use_ssc(dev_priv)) {
4322                                 temp |= DREF_SSC1_ENABLE;
4323                                 I915_WRITE(PCH_DREF_CONTROL, temp);
4324
4325                                 POSTING_READ(PCH_DREF_CONTROL);
4326                                 udelay(200);
4327                         }
4328                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4329
4330                         /* Enable CPU source on CPU attached eDP */
4331                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4332                                 if (intel_panel_use_ssc(dev_priv))
4333                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4334                                 else
4335                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4336                         } else {
4337                                 /* Enable SSC on PCH eDP if needed */
4338                                 if (intel_panel_use_ssc(dev_priv)) {
4339                                         DRM_ERROR("enabling SSC on PCH\n");
4340                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4341                                 }
4342                         }
4343                         I915_WRITE(PCH_DREF_CONTROL, temp);
4344                         POSTING_READ(PCH_DREF_CONTROL);
4345                         udelay(200);
4346                 }
4347         }
4348
4349         if (IS_PINEVIEW(dev)) {
4350                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4351                 if (has_reduced_clock)
4352                         fp2 = (1 << reduced_clock.n) << 16 |
4353                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4354         } else {
4355                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4356                 if (has_reduced_clock)
4357                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4358                                 reduced_clock.m2;
4359         }
4360
4361         /* Enable autotuning of the PLL clock (if permissible) */
4362         if (HAS_PCH_SPLIT(dev)) {
4363                 int factor = 21;
4364
4365                 if (is_lvds) {
4366                         if ((intel_panel_use_ssc(dev_priv) &&
4367                              dev_priv->lvds_ssc_freq == 100) ||
4368                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4369                                 factor = 25;
4370                 } else if (is_sdvo && is_tv)
4371                         factor = 20;
4372
4373                 if (clock.m1 < factor * clock.n)
4374                         fp |= FP_CB_TUNE;
4375         }
4376
4377         dpll = 0;
4378         if (!HAS_PCH_SPLIT(dev))
4379                 dpll = DPLL_VGA_MODE_DIS;
4380
4381         if (!IS_GEN2(dev)) {
4382                 if (is_lvds)
4383                         dpll |= DPLLB_MODE_LVDS;
4384                 else
4385                         dpll |= DPLLB_MODE_DAC_SERIAL;
4386                 if (is_sdvo) {
4387                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4388                         if (pixel_multiplier > 1) {
4389                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4390                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4391                                 else if (HAS_PCH_SPLIT(dev))
4392                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4393                         }
4394                         dpll |= DPLL_DVO_HIGH_SPEED;
4395                 }
4396                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4397                         dpll |= DPLL_DVO_HIGH_SPEED;
4398
4399                 /* compute bitmask from p1 value */
4400                 if (IS_PINEVIEW(dev))
4401                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4402                 else {
4403                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4404                         /* also FPA1 */
4405                         if (HAS_PCH_SPLIT(dev))
4406                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4407                         if (IS_G4X(dev) && has_reduced_clock)
4408                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4409                 }
4410                 switch (clock.p2) {
4411                 case 5:
4412                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4413                         break;
4414                 case 7:
4415                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4416                         break;
4417                 case 10:
4418                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4419                         break;
4420                 case 14:
4421                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4422                         break;
4423                 }
4424                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4425                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4426         } else {
4427                 if (is_lvds) {
4428                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4429                 } else {
4430                         if (clock.p1 == 2)
4431                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4432                         else
4433                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4434                         if (clock.p2 == 4)
4435                                 dpll |= PLL_P2_DIVIDE_BY_4;
4436                 }
4437         }
4438
4439         if (is_sdvo && is_tv)
4440                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4441         else if (is_tv)
4442                 /* XXX: just matching BIOS for now */
4443                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4444                 dpll |= 3;
4445         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4446                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4447         else
4448                 dpll |= PLL_REF_INPUT_DREFCLK;
4449
4450         /* setup pipeconf */
4451         pipeconf = I915_READ(PIPECONF(pipe));
4452
4453         /* Set up the display plane register */
4454         dspcntr = DISPPLANE_GAMMA_ENABLE;
4455
4456         /* Ironlake's plane is forced to pipe, bit 24 is to
4457            enable color space conversion */
4458         if (!HAS_PCH_SPLIT(dev)) {
4459                 if (pipe == 0)
4460                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4461                 else
4462                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4463         }
4464
4465         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4466                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4467                  * core speed.
4468                  *
4469                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4470                  * pipe == 0 check?
4471                  */
4472                 if (mode->clock >
4473                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4474                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4475                 else
4476                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4477         }
4478
4479         if (!HAS_PCH_SPLIT(dev))
4480                 dpll |= DPLL_VCO_ENABLE;
4481
4482         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4483         drm_mode_debug_printmodeline(mode);
4484
4485         /* assign to Ironlake registers */
4486         if (HAS_PCH_SPLIT(dev)) {
4487                 fp_reg = PCH_FP0(pipe);
4488                 dpll_reg = PCH_DPLL(pipe);
4489         } else {
4490                 fp_reg = FP0(pipe);
4491                 dpll_reg = DPLL(pipe);
4492         }
4493
4494         /* PCH eDP needs FDI, but CPU eDP does not */
4495         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4496                 I915_WRITE(fp_reg, fp);
4497                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4498
4499                 POSTING_READ(dpll_reg);
4500                 udelay(150);
4501         }
4502
4503         /* enable transcoder DPLL */
4504         if (HAS_PCH_CPT(dev)) {
4505                 temp = I915_READ(PCH_DPLL_SEL);
4506                 if (pipe == 0)
4507                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4508                 else
4509                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4510                 I915_WRITE(PCH_DPLL_SEL, temp);
4511
4512                 POSTING_READ(PCH_DPLL_SEL);
4513                 udelay(150);
4514         }
4515
4516         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4517          * This is an exception to the general rule that mode_set doesn't turn
4518          * things on.
4519          */
4520         if (is_lvds) {
4521                 reg = LVDS;
4522                 if (HAS_PCH_SPLIT(dev))
4523                         reg = PCH_LVDS;
4524
4525                 temp = I915_READ(reg);
4526                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4527                 if (pipe == 1) {
4528                         if (HAS_PCH_CPT(dev))
4529                                 temp |= PORT_TRANS_B_SEL_CPT;
4530                         else
4531                                 temp |= LVDS_PIPEB_SELECT;
4532                 } else {
4533                         if (HAS_PCH_CPT(dev))
4534                                 temp &= ~PORT_TRANS_SEL_MASK;
4535                         else
4536                                 temp &= ~LVDS_PIPEB_SELECT;
4537                 }
4538                 /* set the corresponsding LVDS_BORDER bit */
4539                 temp |= dev_priv->lvds_border_bits;
4540                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4541                  * set the DPLLs for dual-channel mode or not.
4542                  */
4543                 if (clock.p2 == 7)
4544                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4545                 else
4546                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4547
4548                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4549                  * appropriately here, but we need to look more thoroughly into how
4550                  * panels behave in the two modes.
4551                  */
4552                 /* set the dithering flag on non-PCH LVDS as needed */
4553                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4554                         if (dev_priv->lvds_dither)
4555                                 temp |= LVDS_ENABLE_DITHER;
4556                         else
4557                                 temp &= ~LVDS_ENABLE_DITHER;
4558                 }
4559                 I915_WRITE(reg, temp);
4560         }
4561
4562         /* set the dithering flag and clear for anything other than a panel. */
4563         if (HAS_PCH_SPLIT(dev)) {
4564                 pipeconf &= ~PIPECONF_DITHER_EN;
4565                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4566                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4567                         pipeconf |= PIPECONF_DITHER_EN;
4568                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4569                 }
4570         }
4571
4572         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4573                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4574         } else if (HAS_PCH_SPLIT(dev)) {
4575                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4576                 if (pipe == 0) {
4577                         I915_WRITE(TRANSA_DATA_M1, 0);
4578                         I915_WRITE(TRANSA_DATA_N1, 0);
4579                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4580                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4581                 } else {
4582                         I915_WRITE(TRANSB_DATA_M1, 0);
4583                         I915_WRITE(TRANSB_DATA_N1, 0);
4584                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4585                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4586                 }
4587         }
4588
4589         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4590                 I915_WRITE(dpll_reg, dpll);
4591
4592                 /* Wait for the clocks to stabilize. */
4593                 POSTING_READ(dpll_reg);
4594                 udelay(150);
4595
4596                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4597                         temp = 0;
4598                         if (is_sdvo) {
4599                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4600                                 if (temp > 1)
4601                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4602                                 else
4603                                         temp = 0;
4604                         }
4605                         I915_WRITE(DPLL_MD(pipe), temp);
4606                 } else {
4607                         /* The pixel multiplier can only be updated once the
4608                          * DPLL is enabled and the clocks are stable.
4609                          *
4610                          * So write it again.
4611                          */
4612                         I915_WRITE(dpll_reg, dpll);
4613                 }
4614         }
4615
4616         intel_crtc->lowfreq_avail = false;
4617         if (is_lvds && has_reduced_clock && i915_powersave) {
4618                 I915_WRITE(fp_reg + 4, fp2);
4619                 intel_crtc->lowfreq_avail = true;
4620                 if (HAS_PIPE_CXSR(dev)) {
4621                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4622                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4623                 }
4624         } else {
4625                 I915_WRITE(fp_reg + 4, fp);
4626                 if (HAS_PIPE_CXSR(dev)) {
4627                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4628                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4629                 }
4630         }
4631
4632         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4633                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4634                 /* the chip adds 2 halflines automatically */
4635                 adjusted_mode->crtc_vdisplay -= 1;
4636                 adjusted_mode->crtc_vtotal -= 1;
4637                 adjusted_mode->crtc_vblank_start -= 1;
4638                 adjusted_mode->crtc_vblank_end -= 1;
4639                 adjusted_mode->crtc_vsync_end -= 1;
4640                 adjusted_mode->crtc_vsync_start -= 1;
4641         } else
4642                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4643
4644         I915_WRITE(HTOTAL(pipe),
4645                    (adjusted_mode->crtc_hdisplay - 1) |
4646                    ((adjusted_mode->crtc_htotal - 1) << 16));
4647         I915_WRITE(HBLANK(pipe),
4648                    (adjusted_mode->crtc_hblank_start - 1) |
4649                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4650         I915_WRITE(HSYNC(pipe),
4651                    (adjusted_mode->crtc_hsync_start - 1) |
4652                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4653
4654         I915_WRITE(VTOTAL(pipe),
4655                    (adjusted_mode->crtc_vdisplay - 1) |
4656                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4657         I915_WRITE(VBLANK(pipe),
4658                    (adjusted_mode->crtc_vblank_start - 1) |
4659                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4660         I915_WRITE(VSYNC(pipe),
4661                    (adjusted_mode->crtc_vsync_start - 1) |
4662                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4663
4664         /* pipesrc and dspsize control the size that is scaled from,
4665          * which should always be the user's requested size.
4666          */
4667         if (!HAS_PCH_SPLIT(dev)) {
4668                 I915_WRITE(DSPSIZE(plane),
4669                            ((mode->vdisplay - 1) << 16) |
4670                            (mode->hdisplay - 1));
4671                 I915_WRITE(DSPPOS(plane), 0);
4672         }
4673         I915_WRITE(PIPESRC(pipe),
4674                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4675
4676         if (HAS_PCH_SPLIT(dev)) {
4677                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4678                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4679                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4680                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4681
4682                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4683                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4684                 }
4685         }
4686
4687         I915_WRITE(PIPECONF(pipe), pipeconf);
4688         POSTING_READ(PIPECONF(pipe));
4689         if (!HAS_PCH_SPLIT(dev))
4690                 intel_enable_pipe(dev_priv, pipe);
4691
4692         intel_wait_for_vblank(dev, pipe);
4693
4694         if (IS_GEN5(dev)) {
4695                 /* enable address swizzle for tiling buffer */
4696                 temp = I915_READ(DISP_ARB_CTL);
4697                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4698         }
4699
4700         I915_WRITE(DSPCNTR(plane), dspcntr);
4701         POSTING_READ(DSPCNTR(plane));
4702         if (!HAS_PCH_SPLIT(dev))
4703                 intel_enable_plane(dev_priv, plane, pipe);
4704
4705         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4706
4707         intel_update_watermarks(dev);
4708
4709         drm_vblank_post_modeset(dev, pipe);
4710
4711         return ret;
4712 }
4713
4714 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4715 void intel_crtc_load_lut(struct drm_crtc *crtc)
4716 {
4717         struct drm_device *dev = crtc->dev;
4718         struct drm_i915_private *dev_priv = dev->dev_private;
4719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4721         int i;
4722
4723         /* The clocks have to be on to load the palette. */
4724         if (!crtc->enabled)
4725                 return;
4726
4727         /* use legacy palette for Ironlake */
4728         if (HAS_PCH_SPLIT(dev))
4729                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4730                                                    LGC_PALETTE_B;
4731
4732         for (i = 0; i < 256; i++) {
4733                 I915_WRITE(palreg + 4 * i,
4734                            (intel_crtc->lut_r[i] << 16) |
4735                            (intel_crtc->lut_g[i] << 8) |
4736                            intel_crtc->lut_b[i]);
4737         }
4738 }
4739
4740 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4741 {
4742         struct drm_device *dev = crtc->dev;
4743         struct drm_i915_private *dev_priv = dev->dev_private;
4744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4745         bool visible = base != 0;
4746         u32 cntl;
4747
4748         if (intel_crtc->cursor_visible == visible)
4749                 return;
4750
4751         cntl = I915_READ(CURACNTR);
4752         if (visible) {
4753                 /* On these chipsets we can only modify the base whilst
4754                  * the cursor is disabled.
4755                  */
4756                 I915_WRITE(CURABASE, base);
4757
4758                 cntl &= ~(CURSOR_FORMAT_MASK);
4759                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4760                 cntl |= CURSOR_ENABLE |
4761                         CURSOR_GAMMA_ENABLE |
4762                         CURSOR_FORMAT_ARGB;
4763         } else
4764                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4765         I915_WRITE(CURACNTR, cntl);
4766
4767         intel_crtc->cursor_visible = visible;
4768 }
4769
4770 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4771 {
4772         struct drm_device *dev = crtc->dev;
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4775         int pipe = intel_crtc->pipe;
4776         bool visible = base != 0;
4777
4778         if (intel_crtc->cursor_visible != visible) {
4779                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4780                 if (base) {
4781                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4782                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4783                         cntl |= pipe << 28; /* Connect to correct pipe */
4784                 } else {
4785                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4786                         cntl |= CURSOR_MODE_DISABLE;
4787                 }
4788                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4789
4790                 intel_crtc->cursor_visible = visible;
4791         }
4792         /* and commit changes on next vblank */
4793         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4794 }
4795
4796 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4797 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4798                                      bool on)
4799 {
4800         struct drm_device *dev = crtc->dev;
4801         struct drm_i915_private *dev_priv = dev->dev_private;
4802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4803         int pipe = intel_crtc->pipe;
4804         int x = intel_crtc->cursor_x;
4805         int y = intel_crtc->cursor_y;
4806         u32 base, pos;
4807         bool visible;
4808
4809         pos = 0;
4810
4811         if (on && crtc->enabled && crtc->fb) {
4812                 base = intel_crtc->cursor_addr;
4813                 if (x > (int) crtc->fb->width)
4814                         base = 0;
4815
4816                 if (y > (int) crtc->fb->height)
4817                         base = 0;
4818         } else
4819                 base = 0;
4820
4821         if (x < 0) {
4822                 if (x + intel_crtc->cursor_width < 0)
4823                         base = 0;
4824
4825                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4826                 x = -x;
4827         }
4828         pos |= x << CURSOR_X_SHIFT;
4829
4830         if (y < 0) {
4831                 if (y + intel_crtc->cursor_height < 0)
4832                         base = 0;
4833
4834                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4835                 y = -y;
4836         }
4837         pos |= y << CURSOR_Y_SHIFT;
4838
4839         visible = base != 0;
4840         if (!visible && !intel_crtc->cursor_visible)
4841                 return;
4842
4843         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4844         if (IS_845G(dev) || IS_I865G(dev))
4845                 i845_update_cursor(crtc, base);
4846         else
4847                 i9xx_update_cursor(crtc, base);
4848
4849         if (visible)
4850                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4851 }
4852
4853 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4854                                  struct drm_file *file,
4855                                  uint32_t handle,
4856                                  uint32_t width, uint32_t height)
4857 {
4858         struct drm_device *dev = crtc->dev;
4859         struct drm_i915_private *dev_priv = dev->dev_private;
4860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4861         struct drm_i915_gem_object *obj;
4862         uint32_t addr;
4863         int ret;
4864
4865         DRM_DEBUG_KMS("\n");
4866
4867         /* if we want to turn off the cursor ignore width and height */
4868         if (!handle) {
4869                 DRM_DEBUG_KMS("cursor off\n");
4870                 addr = 0;
4871                 obj = NULL;
4872                 mutex_lock(&dev->struct_mutex);
4873                 goto finish;
4874         }
4875
4876         /* Currently we only support 64x64 cursors */
4877         if (width != 64 || height != 64) {
4878                 DRM_ERROR("we currently only support 64x64 cursors\n");
4879                 return -EINVAL;
4880         }
4881
4882         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4883         if (!obj)
4884                 return -ENOENT;
4885
4886         if (obj->base.size < width * height * 4) {
4887                 DRM_ERROR("buffer is to small\n");
4888                 ret = -ENOMEM;
4889                 goto fail;
4890         }
4891
4892         /* we only need to pin inside GTT if cursor is non-phy */
4893         mutex_lock(&dev->struct_mutex);
4894         if (!dev_priv->info->cursor_needs_physical) {
4895                 if (obj->tiling_mode) {
4896                         DRM_ERROR("cursor cannot be tiled\n");
4897                         ret = -EINVAL;
4898                         goto fail_locked;
4899                 }
4900
4901                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4902                 if (ret) {
4903                         DRM_ERROR("failed to pin cursor bo\n");
4904                         goto fail_locked;
4905                 }
4906
4907                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4908                 if (ret) {
4909                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4910                         goto fail_unpin;
4911                 }
4912
4913                 ret = i915_gem_object_put_fence(obj);
4914                 if (ret) {
4915                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4916                         goto fail_unpin;
4917                 }
4918
4919                 addr = obj->gtt_offset;
4920         } else {
4921                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4922                 ret = i915_gem_attach_phys_object(dev, obj,
4923                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4924                                                   align);
4925                 if (ret) {
4926                         DRM_ERROR("failed to attach phys object\n");
4927                         goto fail_locked;
4928                 }
4929                 addr = obj->phys_obj->handle->busaddr;
4930         }
4931
4932         if (IS_GEN2(dev))
4933                 I915_WRITE(CURSIZE, (height << 12) | width);
4934
4935  finish:
4936         if (intel_crtc->cursor_bo) {
4937                 if (dev_priv->info->cursor_needs_physical) {
4938                         if (intel_crtc->cursor_bo != obj)
4939                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4940                 } else
4941                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4942                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4943         }
4944
4945         mutex_unlock(&dev->struct_mutex);
4946
4947         intel_crtc->cursor_addr = addr;
4948         intel_crtc->cursor_bo = obj;
4949         intel_crtc->cursor_width = width;
4950         intel_crtc->cursor_height = height;
4951
4952         intel_crtc_update_cursor(crtc, true);
4953
4954         return 0;
4955 fail_unpin:
4956         i915_gem_object_unpin(obj);
4957 fail_locked:
4958         mutex_unlock(&dev->struct_mutex);
4959 fail:
4960         drm_gem_object_unreference_unlocked(&obj->base);
4961         return ret;
4962 }
4963
4964 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4965 {
4966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967
4968         intel_crtc->cursor_x = x;
4969         intel_crtc->cursor_y = y;
4970
4971         intel_crtc_update_cursor(crtc, true);
4972
4973         return 0;
4974 }
4975
4976 /** Sets the color ramps on behalf of RandR */
4977 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4978                                  u16 blue, int regno)
4979 {
4980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4981
4982         intel_crtc->lut_r[regno] = red >> 8;
4983         intel_crtc->lut_g[regno] = green >> 8;
4984         intel_crtc->lut_b[regno] = blue >> 8;
4985 }
4986
4987 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4988                              u16 *blue, int regno)
4989 {
4990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4991
4992         *red = intel_crtc->lut_r[regno] << 8;
4993         *green = intel_crtc->lut_g[regno] << 8;
4994         *blue = intel_crtc->lut_b[regno] << 8;
4995 }
4996
4997 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4998                                  u16 *blue, uint32_t start, uint32_t size)
4999 {
5000         int end = (start + size > 256) ? 256 : start + size, i;
5001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5002
5003         for (i = start; i < end; i++) {
5004                 intel_crtc->lut_r[i] = red[i] >> 8;
5005                 intel_crtc->lut_g[i] = green[i] >> 8;
5006                 intel_crtc->lut_b[i] = blue[i] >> 8;
5007         }
5008
5009         intel_crtc_load_lut(crtc);
5010 }
5011
5012 /**
5013  * Get a pipe with a simple mode set on it for doing load-based monitor
5014  * detection.
5015  *
5016  * It will be up to the load-detect code to adjust the pipe as appropriate for
5017  * its requirements.  The pipe will be connected to no other encoders.
5018  *
5019  * Currently this code will only succeed if there is a pipe with no encoders
5020  * configured for it.  In the future, it could choose to temporarily disable
5021  * some outputs to free up a pipe for its use.
5022  *
5023  * \return crtc, or NULL if no pipes are available.
5024  */
5025
5026 /* VESA 640x480x72Hz mode to set on the pipe */
5027 static struct drm_display_mode load_detect_mode = {
5028         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5029                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5030 };
5031
5032 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5033                                             struct drm_connector *connector,
5034                                             struct drm_display_mode *mode,
5035                                             int *dpms_mode)
5036 {
5037         struct intel_crtc *intel_crtc;
5038         struct drm_crtc *possible_crtc;
5039         struct drm_crtc *supported_crtc =NULL;
5040         struct drm_encoder *encoder = &intel_encoder->base;
5041         struct drm_crtc *crtc = NULL;
5042         struct drm_device *dev = encoder->dev;
5043         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5044         struct drm_crtc_helper_funcs *crtc_funcs;
5045         int i = -1;
5046
5047         /*
5048          * Algorithm gets a little messy:
5049          *   - if the connector already has an assigned crtc, use it (but make
5050          *     sure it's on first)
5051          *   - try to find the first unused crtc that can drive this connector,
5052          *     and use that if we find one
5053          *   - if there are no unused crtcs available, try to use the first
5054          *     one we found that supports the connector
5055          */
5056
5057         /* See if we already have a CRTC for this connector */
5058         if (encoder->crtc) {
5059                 crtc = encoder->crtc;
5060                 /* Make sure the crtc and connector are running */
5061                 intel_crtc = to_intel_crtc(crtc);
5062                 *dpms_mode = intel_crtc->dpms_mode;
5063                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5064                         crtc_funcs = crtc->helper_private;
5065                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5066                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5067                 }
5068                 return crtc;
5069         }
5070
5071         /* Find an unused one (if possible) */
5072         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5073                 i++;
5074                 if (!(encoder->possible_crtcs & (1 << i)))
5075                         continue;
5076                 if (!possible_crtc->enabled) {
5077                         crtc = possible_crtc;
5078                         break;
5079                 }
5080                 if (!supported_crtc)
5081                         supported_crtc = possible_crtc;
5082         }
5083
5084         /*
5085          * If we didn't find an unused CRTC, don't use any.
5086          */
5087         if (!crtc) {
5088                 return NULL;
5089         }
5090
5091         encoder->crtc = crtc;
5092         connector->encoder = encoder;
5093         intel_encoder->load_detect_temp = true;
5094
5095         intel_crtc = to_intel_crtc(crtc);
5096         *dpms_mode = intel_crtc->dpms_mode;
5097
5098         if (!crtc->enabled) {
5099                 if (!mode)
5100                         mode = &load_detect_mode;
5101                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5102         } else {
5103                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5104                         crtc_funcs = crtc->helper_private;
5105                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5106                 }
5107
5108                 /* Add this connector to the crtc */
5109                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5110                 encoder_funcs->commit(encoder);
5111         }
5112         /* let the connector get through one full cycle before testing */
5113         intel_wait_for_vblank(dev, intel_crtc->pipe);
5114
5115         return crtc;
5116 }
5117
5118 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5119                                     struct drm_connector *connector, int dpms_mode)
5120 {
5121         struct drm_encoder *encoder = &intel_encoder->base;
5122         struct drm_device *dev = encoder->dev;
5123         struct drm_crtc *crtc = encoder->crtc;
5124         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5125         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5126
5127         if (intel_encoder->load_detect_temp) {
5128                 encoder->crtc = NULL;
5129                 connector->encoder = NULL;
5130                 intel_encoder->load_detect_temp = false;
5131                 crtc->enabled = drm_helper_crtc_in_use(crtc);
5132                 drm_helper_disable_unused_functions(dev);
5133         }
5134
5135         /* Switch crtc and encoder back off if necessary */
5136         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5137                 if (encoder->crtc == crtc)
5138                         encoder_funcs->dpms(encoder, dpms_mode);
5139                 crtc_funcs->dpms(crtc, dpms_mode);
5140         }
5141 }
5142
5143 /* Returns the clock of the currently programmed mode of the given pipe. */
5144 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5145 {
5146         struct drm_i915_private *dev_priv = dev->dev_private;
5147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5148         int pipe = intel_crtc->pipe;
5149         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
5150         u32 fp;
5151         intel_clock_t clock;
5152
5153         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5154                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
5155         else
5156                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
5157
5158         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5159         if (IS_PINEVIEW(dev)) {
5160                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5161                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5162         } else {
5163                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5164                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5165         }
5166
5167         if (!IS_GEN2(dev)) {
5168                 if (IS_PINEVIEW(dev))
5169                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5170                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5171                 else
5172                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5173                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5174
5175                 switch (dpll & DPLL_MODE_MASK) {
5176                 case DPLLB_MODE_DAC_SERIAL:
5177                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5178                                 5 : 10;
5179                         break;
5180                 case DPLLB_MODE_LVDS:
5181                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5182                                 7 : 14;
5183                         break;
5184                 default:
5185                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5186                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5187                         return 0;
5188                 }
5189
5190                 /* XXX: Handle the 100Mhz refclk */
5191                 intel_clock(dev, 96000, &clock);
5192         } else {
5193                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5194
5195                 if (is_lvds) {
5196                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5197                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5198                         clock.p2 = 14;
5199
5200                         if ((dpll & PLL_REF_INPUT_MASK) ==
5201                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5202                                 /* XXX: might not be 66MHz */
5203                                 intel_clock(dev, 66000, &clock);
5204                         } else
5205                                 intel_clock(dev, 48000, &clock);
5206                 } else {
5207                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5208                                 clock.p1 = 2;
5209                         else {
5210                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5211                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5212                         }
5213                         if (dpll & PLL_P2_DIVIDE_BY_4)
5214                                 clock.p2 = 4;
5215                         else
5216                                 clock.p2 = 2;
5217
5218                         intel_clock(dev, 48000, &clock);
5219                 }
5220         }
5221
5222         /* XXX: It would be nice to validate the clocks, but we can't reuse
5223          * i830PllIsValid() because it relies on the xf86_config connector
5224          * configuration being accurate, which it isn't necessarily.
5225          */
5226
5227         return clock.dot;
5228 }
5229
5230 /** Returns the currently programmed mode of the given pipe. */
5231 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5232                                              struct drm_crtc *crtc)
5233 {
5234         struct drm_i915_private *dev_priv = dev->dev_private;
5235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236         int pipe = intel_crtc->pipe;
5237         struct drm_display_mode *mode;
5238         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
5239         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
5240         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
5241         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
5242
5243         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5244         if (!mode)
5245                 return NULL;
5246
5247         mode->clock = intel_crtc_clock_get(dev, crtc);
5248         mode->hdisplay = (htot & 0xffff) + 1;
5249         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5250         mode->hsync_start = (hsync & 0xffff) + 1;
5251         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5252         mode->vdisplay = (vtot & 0xffff) + 1;
5253         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5254         mode->vsync_start = (vsync & 0xffff) + 1;
5255         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5256
5257         drm_mode_set_name(mode);
5258         drm_mode_set_crtcinfo(mode, 0);
5259
5260         return mode;
5261 }
5262
5263 #define GPU_IDLE_TIMEOUT 500 /* ms */
5264
5265 /* When this timer fires, we've been idle for awhile */
5266 static void intel_gpu_idle_timer(unsigned long arg)
5267 {
5268         struct drm_device *dev = (struct drm_device *)arg;
5269         drm_i915_private_t *dev_priv = dev->dev_private;
5270
5271         if (!list_empty(&dev_priv->mm.active_list)) {
5272                 /* Still processing requests, so just re-arm the timer. */
5273                 mod_timer(&dev_priv->idle_timer, jiffies +
5274                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5275                 return;
5276         }
5277
5278         dev_priv->busy = false;
5279         queue_work(dev_priv->wq, &dev_priv->idle_work);
5280 }
5281
5282 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5283
5284 static void intel_crtc_idle_timer(unsigned long arg)
5285 {
5286         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5287         struct drm_crtc *crtc = &intel_crtc->base;
5288         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5289         struct intel_framebuffer *intel_fb;
5290
5291         intel_fb = to_intel_framebuffer(crtc->fb);
5292         if (intel_fb && intel_fb->obj->active) {
5293                 /* The framebuffer is still being accessed by the GPU. */
5294                 mod_timer(&intel_crtc->idle_timer, jiffies +
5295                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5296                 return;
5297         }
5298
5299         intel_crtc->busy = false;
5300         queue_work(dev_priv->wq, &dev_priv->idle_work);
5301 }
5302
5303 static void intel_increase_pllclock(struct drm_crtc *crtc)
5304 {
5305         struct drm_device *dev = crtc->dev;
5306         drm_i915_private_t *dev_priv = dev->dev_private;
5307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5308         int pipe = intel_crtc->pipe;
5309         int dpll_reg = DPLL(pipe);
5310         int dpll;
5311
5312         if (HAS_PCH_SPLIT(dev))
5313                 return;
5314
5315         if (!dev_priv->lvds_downclock_avail)
5316                 return;
5317
5318         dpll = I915_READ(dpll_reg);
5319         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5320                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5321
5322                 /* Unlock panel regs */
5323                 I915_WRITE(PP_CONTROL,
5324                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5325
5326                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5327                 I915_WRITE(dpll_reg, dpll);
5328                 POSTING_READ(dpll_reg);
5329                 intel_wait_for_vblank(dev, pipe);
5330
5331                 dpll = I915_READ(dpll_reg);
5332                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5333                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5334
5335                 /* ...and lock them again */
5336                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5337         }
5338
5339         /* Schedule downclock */
5340         mod_timer(&intel_crtc->idle_timer, jiffies +
5341                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5342 }
5343
5344 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5345 {
5346         struct drm_device *dev = crtc->dev;
5347         drm_i915_private_t *dev_priv = dev->dev_private;
5348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5349         int pipe = intel_crtc->pipe;
5350         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5351         int dpll = I915_READ(dpll_reg);
5352
5353         if (HAS_PCH_SPLIT(dev))
5354                 return;
5355
5356         if (!dev_priv->lvds_downclock_avail)
5357                 return;
5358
5359         /*
5360          * Since this is called by a timer, we should never get here in
5361          * the manual case.
5362          */
5363         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5364                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5365
5366                 /* Unlock panel regs */
5367                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5368                            PANEL_UNLOCK_REGS);
5369
5370                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5371                 I915_WRITE(dpll_reg, dpll);
5372                 dpll = I915_READ(dpll_reg);
5373                 intel_wait_for_vblank(dev, pipe);
5374                 dpll = I915_READ(dpll_reg);
5375                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5376                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5377
5378                 /* ...and lock them again */
5379                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5380         }
5381
5382 }
5383
5384 /**
5385  * intel_idle_update - adjust clocks for idleness
5386  * @work: work struct
5387  *
5388  * Either the GPU or display (or both) went idle.  Check the busy status
5389  * here and adjust the CRTC and GPU clocks as necessary.
5390  */
5391 static void intel_idle_update(struct work_struct *work)
5392 {
5393         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5394                                                     idle_work);
5395         struct drm_device *dev = dev_priv->dev;
5396         struct drm_crtc *crtc;
5397         struct intel_crtc *intel_crtc;
5398         int enabled = 0;
5399
5400         if (!i915_powersave)
5401                 return;
5402
5403         mutex_lock(&dev->struct_mutex);
5404
5405         i915_update_gfx_val(dev_priv);
5406
5407         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5408                 /* Skip inactive CRTCs */
5409                 if (!crtc->fb)
5410                         continue;
5411
5412                 enabled++;
5413                 intel_crtc = to_intel_crtc(crtc);
5414                 if (!intel_crtc->busy)
5415                         intel_decrease_pllclock(crtc);
5416         }
5417
5418         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5419                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5420                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5421         }
5422
5423         mutex_unlock(&dev->struct_mutex);
5424 }
5425
5426 /**
5427  * intel_mark_busy - mark the GPU and possibly the display busy
5428  * @dev: drm device
5429  * @obj: object we're operating on
5430  *
5431  * Callers can use this function to indicate that the GPU is busy processing
5432  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5433  * buffer), we'll also mark the display as busy, so we know to increase its
5434  * clock frequency.
5435  */
5436 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5437 {
5438         drm_i915_private_t *dev_priv = dev->dev_private;
5439         struct drm_crtc *crtc = NULL;
5440         struct intel_framebuffer *intel_fb;
5441         struct intel_crtc *intel_crtc;
5442
5443         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5444                 return;
5445
5446         if (!dev_priv->busy) {
5447                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5448                         u32 fw_blc_self;
5449
5450                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5451                         fw_blc_self = I915_READ(FW_BLC_SELF);
5452                         fw_blc_self &= ~FW_BLC_SELF_EN;
5453                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5454                 }
5455                 dev_priv->busy = true;
5456         } else
5457                 mod_timer(&dev_priv->idle_timer, jiffies +
5458                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5459
5460         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5461                 if (!crtc->fb)
5462                         continue;
5463
5464                 intel_crtc = to_intel_crtc(crtc);
5465                 intel_fb = to_intel_framebuffer(crtc->fb);
5466                 if (intel_fb->obj == obj) {
5467                         if (!intel_crtc->busy) {
5468                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
5469                                         u32 fw_blc_self;
5470
5471                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5472                                         fw_blc_self = I915_READ(FW_BLC_SELF);
5473                                         fw_blc_self &= ~FW_BLC_SELF_EN;
5474                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5475                                 }
5476                                 /* Non-busy -> busy, upclock */
5477                                 intel_increase_pllclock(crtc);
5478                                 intel_crtc->busy = true;
5479                         } else {
5480                                 /* Busy -> busy, put off timer */
5481                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5482                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5483                         }
5484                 }
5485         }
5486 }
5487
5488 static void intel_crtc_destroy(struct drm_crtc *crtc)
5489 {
5490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5491         struct drm_device *dev = crtc->dev;
5492         struct intel_unpin_work *work;
5493         unsigned long flags;
5494
5495         spin_lock_irqsave(&dev->event_lock, flags);
5496         work = intel_crtc->unpin_work;
5497         intel_crtc->unpin_work = NULL;
5498         spin_unlock_irqrestore(&dev->event_lock, flags);
5499
5500         if (work) {
5501                 cancel_work_sync(&work->work);
5502                 kfree(work);
5503         }
5504
5505         drm_crtc_cleanup(crtc);
5506
5507         kfree(intel_crtc);
5508 }
5509
5510 static void intel_unpin_work_fn(struct work_struct *__work)
5511 {
5512         struct intel_unpin_work *work =
5513                 container_of(__work, struct intel_unpin_work, work);
5514
5515         mutex_lock(&work->dev->struct_mutex);
5516         i915_gem_object_unpin(work->old_fb_obj);
5517         drm_gem_object_unreference(&work->pending_flip_obj->base);
5518         drm_gem_object_unreference(&work->old_fb_obj->base);
5519
5520         mutex_unlock(&work->dev->struct_mutex);
5521         kfree(work);
5522 }
5523
5524 static void do_intel_finish_page_flip(struct drm_device *dev,
5525                                       struct drm_crtc *crtc)
5526 {
5527         drm_i915_private_t *dev_priv = dev->dev_private;
5528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5529         struct intel_unpin_work *work;
5530         struct drm_i915_gem_object *obj;
5531         struct drm_pending_vblank_event *e;
5532         struct timeval tnow, tvbl;
5533         unsigned long flags;
5534
5535         /* Ignore early vblank irqs */
5536         if (intel_crtc == NULL)
5537                 return;
5538
5539         do_gettimeofday(&tnow);
5540
5541         spin_lock_irqsave(&dev->event_lock, flags);
5542         work = intel_crtc->unpin_work;
5543         if (work == NULL || !work->pending) {
5544                 spin_unlock_irqrestore(&dev->event_lock, flags);
5545                 return;
5546         }
5547
5548         intel_crtc->unpin_work = NULL;
5549
5550         if (work->event) {
5551                 e = work->event;
5552                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5553
5554                 /* Called before vblank count and timestamps have
5555                  * been updated for the vblank interval of flip
5556                  * completion? Need to increment vblank count and
5557                  * add one videorefresh duration to returned timestamp
5558                  * to account for this. We assume this happened if we
5559                  * get called over 0.9 frame durations after the last
5560                  * timestamped vblank.
5561                  *
5562                  * This calculation can not be used with vrefresh rates
5563                  * below 5Hz (10Hz to be on the safe side) without
5564                  * promoting to 64 integers.
5565                  */
5566                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5567                     9 * crtc->framedur_ns) {
5568                         e->event.sequence++;
5569                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5570                                              crtc->framedur_ns);
5571                 }
5572
5573                 e->event.tv_sec = tvbl.tv_sec;
5574                 e->event.tv_usec = tvbl.tv_usec;
5575
5576                 list_add_tail(&e->base.link,
5577                               &e->base.file_priv->event_list);
5578                 wake_up_interruptible(&e->base.file_priv->event_wait);
5579         }
5580
5581         drm_vblank_put(dev, intel_crtc->pipe);
5582
5583         spin_unlock_irqrestore(&dev->event_lock, flags);
5584
5585         obj = work->old_fb_obj;
5586
5587         atomic_clear_mask(1 << intel_crtc->plane,
5588                           &obj->pending_flip.counter);
5589         if (atomic_read(&obj->pending_flip) == 0)
5590                 wake_up(&dev_priv->pending_flip_queue);
5591
5592         schedule_work(&work->work);
5593
5594         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5595 }
5596
5597 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5598 {
5599         drm_i915_private_t *dev_priv = dev->dev_private;
5600         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5601
5602         do_intel_finish_page_flip(dev, crtc);
5603 }
5604
5605 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5606 {
5607         drm_i915_private_t *dev_priv = dev->dev_private;
5608         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5609
5610         do_intel_finish_page_flip(dev, crtc);
5611 }
5612
5613 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5614 {
5615         drm_i915_private_t *dev_priv = dev->dev_private;
5616         struct intel_crtc *intel_crtc =
5617                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5618         unsigned long flags;
5619
5620         spin_lock_irqsave(&dev->event_lock, flags);
5621         if (intel_crtc->unpin_work) {
5622                 if ((++intel_crtc->unpin_work->pending) > 1)
5623                         DRM_ERROR("Prepared flip multiple times\n");
5624         } else {
5625                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5626         }
5627         spin_unlock_irqrestore(&dev->event_lock, flags);
5628 }
5629
5630 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5631                                 struct drm_framebuffer *fb,
5632                                 struct drm_pending_vblank_event *event)
5633 {
5634         struct drm_device *dev = crtc->dev;
5635         struct drm_i915_private *dev_priv = dev->dev_private;
5636         struct intel_framebuffer *intel_fb;
5637         struct drm_i915_gem_object *obj;
5638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5639         struct intel_unpin_work *work;
5640         unsigned long flags, offset;
5641         int pipe = intel_crtc->pipe;
5642         u32 pf, pipesrc;
5643         int ret;
5644
5645         work = kzalloc(sizeof *work, GFP_KERNEL);
5646         if (work == NULL)
5647                 return -ENOMEM;
5648
5649         work->event = event;
5650         work->dev = crtc->dev;
5651         intel_fb = to_intel_framebuffer(crtc->fb);
5652         work->old_fb_obj = intel_fb->obj;
5653         INIT_WORK(&work->work, intel_unpin_work_fn);
5654
5655         /* We borrow the event spin lock for protecting unpin_work */
5656         spin_lock_irqsave(&dev->event_lock, flags);
5657         if (intel_crtc->unpin_work) {
5658                 spin_unlock_irqrestore(&dev->event_lock, flags);
5659                 kfree(work);
5660
5661                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5662                 return -EBUSY;
5663         }
5664         intel_crtc->unpin_work = work;
5665         spin_unlock_irqrestore(&dev->event_lock, flags);
5666
5667         intel_fb = to_intel_framebuffer(fb);
5668         obj = intel_fb->obj;
5669
5670         mutex_lock(&dev->struct_mutex);
5671         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5672         if (ret)
5673                 goto cleanup_work;
5674
5675         /* Reference the objects for the scheduled work. */
5676         drm_gem_object_reference(&work->old_fb_obj->base);
5677         drm_gem_object_reference(&obj->base);
5678
5679         crtc->fb = fb;
5680
5681         ret = drm_vblank_get(dev, intel_crtc->pipe);
5682         if (ret)
5683                 goto cleanup_objs;
5684
5685         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5686                 u32 flip_mask;
5687
5688                 /* Can't queue multiple flips, so wait for the previous
5689                  * one to finish before executing the next.
5690                  */
5691                 ret = BEGIN_LP_RING(2);
5692                 if (ret)
5693                         goto cleanup_objs;
5694
5695                 if (intel_crtc->plane)
5696                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5697                 else
5698                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5699                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5700                 OUT_RING(MI_NOOP);
5701                 ADVANCE_LP_RING();
5702         }
5703
5704         work->pending_flip_obj = obj;
5705
5706         work->enable_stall_check = true;
5707
5708         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5709         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5710
5711         ret = BEGIN_LP_RING(4);
5712         if (ret)
5713                 goto cleanup_objs;
5714
5715         /* Block clients from rendering to the new back buffer until
5716          * the flip occurs and the object is no longer visible.
5717          */
5718         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5719
5720         switch (INTEL_INFO(dev)->gen) {
5721         case 2:
5722                 OUT_RING(MI_DISPLAY_FLIP |
5723                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5724                 OUT_RING(fb->pitch);
5725                 OUT_RING(obj->gtt_offset + offset);
5726                 OUT_RING(MI_NOOP);
5727                 break;
5728
5729         case 3:
5730                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5731                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5732                 OUT_RING(fb->pitch);
5733                 OUT_RING(obj->gtt_offset + offset);
5734                 OUT_RING(MI_NOOP);
5735                 break;
5736
5737         case 4:
5738         case 5:
5739                 /* i965+ uses the linear or tiled offsets from the
5740                  * Display Registers (which do not change across a page-flip)
5741                  * so we need only reprogram the base address.
5742                  */
5743                 OUT_RING(MI_DISPLAY_FLIP |
5744                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5745                 OUT_RING(fb->pitch);
5746                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5747
5748                 /* XXX Enabling the panel-fitter across page-flip is so far
5749                  * untested on non-native modes, so ignore it for now.
5750                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5751                  */
5752                 pf = 0;
5753                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5754                 OUT_RING(pf | pipesrc);
5755                 break;
5756
5757         case 6:
5758                 OUT_RING(MI_DISPLAY_FLIP |
5759                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5760                 OUT_RING(fb->pitch | obj->tiling_mode);
5761                 OUT_RING(obj->gtt_offset);
5762
5763                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5764                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5765                 OUT_RING(pf | pipesrc);
5766                 break;
5767         }
5768         ADVANCE_LP_RING();
5769
5770         mutex_unlock(&dev->struct_mutex);
5771
5772         trace_i915_flip_request(intel_crtc->plane, obj);
5773
5774         return 0;
5775
5776 cleanup_objs:
5777         drm_gem_object_unreference(&work->old_fb_obj->base);
5778         drm_gem_object_unreference(&obj->base);
5779 cleanup_work:
5780         mutex_unlock(&dev->struct_mutex);
5781
5782         spin_lock_irqsave(&dev->event_lock, flags);
5783         intel_crtc->unpin_work = NULL;
5784         spin_unlock_irqrestore(&dev->event_lock, flags);
5785
5786         kfree(work);
5787
5788         return ret;
5789 }
5790
5791 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5792         .dpms = intel_crtc_dpms,
5793         .mode_fixup = intel_crtc_mode_fixup,
5794         .mode_set = intel_crtc_mode_set,
5795         .mode_set_base = intel_pipe_set_base,
5796         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5797         .load_lut = intel_crtc_load_lut,
5798         .disable = intel_crtc_disable,
5799 };
5800
5801 static const struct drm_crtc_funcs intel_crtc_funcs = {
5802         .cursor_set = intel_crtc_cursor_set,
5803         .cursor_move = intel_crtc_cursor_move,
5804         .gamma_set = intel_crtc_gamma_set,
5805         .set_config = drm_crtc_helper_set_config,
5806         .destroy = intel_crtc_destroy,
5807         .page_flip = intel_crtc_page_flip,
5808 };
5809
5810 static void intel_sanitize_modesetting(struct drm_device *dev,
5811                                        int pipe, int plane)
5812 {
5813         struct drm_i915_private *dev_priv = dev->dev_private;
5814         u32 reg, val;
5815
5816         if (HAS_PCH_SPLIT(dev))
5817                 return;
5818
5819         /* Who knows what state these registers were left in by the BIOS or
5820          * grub?
5821          *
5822          * If we leave the registers in a conflicting state (e.g. with the
5823          * display plane reading from the other pipe than the one we intend
5824          * to use) then when we attempt to teardown the active mode, we will
5825          * not disable the pipes and planes in the correct order -- leaving
5826          * a plane reading from a disabled pipe and possibly leading to
5827          * undefined behaviour.
5828          */
5829
5830         reg = DSPCNTR(plane);
5831         val = I915_READ(reg);
5832
5833         if ((val & DISPLAY_PLANE_ENABLE) == 0)
5834                 return;
5835         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5836                 return;
5837
5838         /* This display plane is active and attached to the other CPU pipe. */
5839         pipe = !pipe;
5840
5841         /* Disable the plane and wait for it to stop reading from the pipe. */
5842         intel_disable_plane(dev_priv, plane, pipe);
5843         intel_disable_pipe(dev_priv, pipe);
5844 }
5845
5846 static void intel_crtc_init(struct drm_device *dev, int pipe)
5847 {
5848         drm_i915_private_t *dev_priv = dev->dev_private;
5849         struct intel_crtc *intel_crtc;
5850         int i;
5851
5852         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5853         if (intel_crtc == NULL)
5854                 return;
5855
5856         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5857
5858         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5859         for (i = 0; i < 256; i++) {
5860                 intel_crtc->lut_r[i] = i;
5861                 intel_crtc->lut_g[i] = i;
5862                 intel_crtc->lut_b[i] = i;
5863         }
5864
5865         /* Swap pipes & planes for FBC on pre-965 */
5866         intel_crtc->pipe = pipe;
5867         intel_crtc->plane = pipe;
5868         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5869                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5870                 intel_crtc->plane = !pipe;
5871         }
5872
5873         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5874                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5875         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5876         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5877
5878         intel_crtc->cursor_addr = 0;
5879         intel_crtc->dpms_mode = -1;
5880         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5881
5882         if (HAS_PCH_SPLIT(dev)) {
5883                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5884                 intel_helper_funcs.commit = ironlake_crtc_commit;
5885         } else {
5886                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5887                 intel_helper_funcs.commit = i9xx_crtc_commit;
5888         }
5889
5890         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5891
5892         intel_crtc->busy = false;
5893
5894         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5895                     (unsigned long)intel_crtc);
5896
5897         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5898 }
5899
5900 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5901                                 struct drm_file *file)
5902 {
5903         drm_i915_private_t *dev_priv = dev->dev_private;
5904         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5905         struct drm_mode_object *drmmode_obj;
5906         struct intel_crtc *crtc;
5907
5908         if (!dev_priv) {
5909                 DRM_ERROR("called with no initialization\n");
5910                 return -EINVAL;
5911         }
5912
5913         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5914                         DRM_MODE_OBJECT_CRTC);
5915
5916         if (!drmmode_obj) {
5917                 DRM_ERROR("no such CRTC id\n");
5918                 return -EINVAL;
5919         }
5920
5921         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5922         pipe_from_crtc_id->pipe = crtc->pipe;
5923
5924         return 0;
5925 }
5926
5927 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5928 {
5929         struct intel_encoder *encoder;
5930         int index_mask = 0;
5931         int entry = 0;
5932
5933         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5934                 if (type_mask & encoder->clone_mask)
5935                         index_mask |= (1 << entry);
5936                 entry++;
5937         }
5938
5939         return index_mask;
5940 }
5941
5942 static bool has_edp_a(struct drm_device *dev)
5943 {
5944         struct drm_i915_private *dev_priv = dev->dev_private;
5945
5946         if (!IS_MOBILE(dev))
5947                 return false;
5948
5949         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5950                 return false;
5951
5952         if (IS_GEN5(dev) &&
5953             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5954                 return false;
5955
5956         return true;
5957 }
5958
5959 static void intel_setup_outputs(struct drm_device *dev)
5960 {
5961         struct drm_i915_private *dev_priv = dev->dev_private;
5962         struct intel_encoder *encoder;
5963         bool dpd_is_edp = false;
5964         bool has_lvds = false;
5965
5966         if (IS_MOBILE(dev) && !IS_I830(dev))
5967                 has_lvds = intel_lvds_init(dev);
5968         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5969                 /* disable the panel fitter on everything but LVDS */
5970                 I915_WRITE(PFIT_CONTROL, 0);
5971         }
5972
5973         if (HAS_PCH_SPLIT(dev)) {
5974                 dpd_is_edp = intel_dpd_is_edp(dev);
5975
5976                 if (has_edp_a(dev))
5977                         intel_dp_init(dev, DP_A);
5978
5979                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5980                         intel_dp_init(dev, PCH_DP_D);
5981         }
5982
5983         intel_crt_init(dev);
5984
5985         if (HAS_PCH_SPLIT(dev)) {
5986                 int found;
5987
5988                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5989                         /* PCH SDVOB multiplex with HDMIB */
5990                         found = intel_sdvo_init(dev, PCH_SDVOB);
5991                         if (!found)
5992                                 intel_hdmi_init(dev, HDMIB);
5993                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5994                                 intel_dp_init(dev, PCH_DP_B);
5995                 }
5996
5997                 if (I915_READ(HDMIC) & PORT_DETECTED)
5998                         intel_hdmi_init(dev, HDMIC);
5999
6000                 if (I915_READ(HDMID) & PORT_DETECTED)
6001                         intel_hdmi_init(dev, HDMID);
6002
6003                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6004                         intel_dp_init(dev, PCH_DP_C);
6005
6006                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6007                         intel_dp_init(dev, PCH_DP_D);
6008
6009         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6010                 bool found = false;
6011
6012                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6013                         DRM_DEBUG_KMS("probing SDVOB\n");
6014                         found = intel_sdvo_init(dev, SDVOB);
6015                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6016                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6017                                 intel_hdmi_init(dev, SDVOB);
6018                         }
6019
6020                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6021                                 DRM_DEBUG_KMS("probing DP_B\n");
6022                                 intel_dp_init(dev, DP_B);
6023                         }
6024                 }
6025
6026                 /* Before G4X SDVOC doesn't have its own detect register */
6027
6028                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6029                         DRM_DEBUG_KMS("probing SDVOC\n");
6030                         found = intel_sdvo_init(dev, SDVOC);
6031                 }
6032
6033                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6034
6035                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6036                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6037                                 intel_hdmi_init(dev, SDVOC);
6038                         }
6039                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6040                                 DRM_DEBUG_KMS("probing DP_C\n");
6041                                 intel_dp_init(dev, DP_C);
6042                         }
6043                 }
6044
6045                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6046                     (I915_READ(DP_D) & DP_DETECTED)) {
6047                         DRM_DEBUG_KMS("probing DP_D\n");
6048                         intel_dp_init(dev, DP_D);
6049                 }
6050         } else if (IS_GEN2(dev))
6051                 intel_dvo_init(dev);
6052
6053         if (SUPPORTS_TV(dev))
6054                 intel_tv_init(dev);
6055
6056         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6057                 encoder->base.possible_crtcs = encoder->crtc_mask;
6058                 encoder->base.possible_clones =
6059                         intel_encoder_clones(dev, encoder->clone_mask);
6060         }
6061
6062         intel_panel_setup_backlight(dev);
6063 }
6064
6065 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6066 {
6067         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6068
6069         drm_framebuffer_cleanup(fb);
6070         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6071
6072         kfree(intel_fb);
6073 }
6074
6075 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6076                                                 struct drm_file *file,
6077                                                 unsigned int *handle)
6078 {
6079         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6080         struct drm_i915_gem_object *obj = intel_fb->obj;
6081
6082         return drm_gem_handle_create(file, &obj->base, handle);
6083 }
6084
6085 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6086         .destroy = intel_user_framebuffer_destroy,
6087         .create_handle = intel_user_framebuffer_create_handle,
6088 };
6089
6090 int intel_framebuffer_init(struct drm_device *dev,
6091                            struct intel_framebuffer *intel_fb,
6092                            struct drm_mode_fb_cmd *mode_cmd,
6093                            struct drm_i915_gem_object *obj)
6094 {
6095         int ret;
6096
6097         if (obj->tiling_mode == I915_TILING_Y)
6098                 return -EINVAL;
6099
6100         if (mode_cmd->pitch & 63)
6101                 return -EINVAL;
6102
6103         switch (mode_cmd->bpp) {
6104         case 8:
6105         case 16:
6106         case 24:
6107         case 32:
6108                 break;
6109         default:
6110                 return -EINVAL;
6111         }
6112
6113         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6114         if (ret) {
6115                 DRM_ERROR("framebuffer init failed %d\n", ret);
6116                 return ret;
6117         }
6118
6119         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6120         intel_fb->obj = obj;
6121         return 0;
6122 }
6123
6124 static struct drm_framebuffer *
6125 intel_user_framebuffer_create(struct drm_device *dev,
6126                               struct drm_file *filp,
6127                               struct drm_mode_fb_cmd *mode_cmd)
6128 {
6129         struct drm_i915_gem_object *obj;
6130         struct intel_framebuffer *intel_fb;
6131         int ret;
6132
6133         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6134         if (!obj)
6135                 return ERR_PTR(-ENOENT);
6136
6137         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6138         if (!intel_fb)
6139                 return ERR_PTR(-ENOMEM);
6140
6141         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6142         if (ret) {
6143                 drm_gem_object_unreference_unlocked(&obj->base);
6144                 kfree(intel_fb);
6145                 return ERR_PTR(ret);
6146         }
6147
6148         return &intel_fb->base;
6149 }
6150
6151 static const struct drm_mode_config_funcs intel_mode_funcs = {
6152         .fb_create = intel_user_framebuffer_create,
6153         .output_poll_changed = intel_fb_output_poll_changed,
6154 };
6155
6156 static struct drm_i915_gem_object *
6157 intel_alloc_context_page(struct drm_device *dev)
6158 {
6159         struct drm_i915_gem_object *ctx;
6160         int ret;
6161
6162         ctx = i915_gem_alloc_object(dev, 4096);
6163         if (!ctx) {
6164                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6165                 return NULL;
6166         }
6167
6168         mutex_lock(&dev->struct_mutex);
6169         ret = i915_gem_object_pin(ctx, 4096, true);
6170         if (ret) {
6171                 DRM_ERROR("failed to pin power context: %d\n", ret);
6172                 goto err_unref;
6173         }
6174
6175         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6176         if (ret) {
6177                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6178                 goto err_unpin;
6179         }
6180         mutex_unlock(&dev->struct_mutex);
6181
6182         return ctx;
6183
6184 err_unpin:
6185         i915_gem_object_unpin(ctx);
6186 err_unref:
6187         drm_gem_object_unreference(&ctx->base);
6188         mutex_unlock(&dev->struct_mutex);
6189         return NULL;
6190 }
6191
6192 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6193 {
6194         struct drm_i915_private *dev_priv = dev->dev_private;
6195         u16 rgvswctl;
6196
6197         rgvswctl = I915_READ16(MEMSWCTL);
6198         if (rgvswctl & MEMCTL_CMD_STS) {
6199                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6200                 return false; /* still busy with another command */
6201         }
6202
6203         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6204                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6205         I915_WRITE16(MEMSWCTL, rgvswctl);
6206         POSTING_READ16(MEMSWCTL);
6207
6208         rgvswctl |= MEMCTL_CMD_STS;
6209         I915_WRITE16(MEMSWCTL, rgvswctl);
6210
6211         return true;
6212 }
6213
6214 void ironlake_enable_drps(struct drm_device *dev)
6215 {
6216         struct drm_i915_private *dev_priv = dev->dev_private;
6217         u32 rgvmodectl = I915_READ(MEMMODECTL);
6218         u8 fmax, fmin, fstart, vstart;
6219
6220         /* Enable temp reporting */
6221         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6222         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6223
6224         /* 100ms RC evaluation intervals */
6225         I915_WRITE(RCUPEI, 100000);
6226         I915_WRITE(RCDNEI, 100000);
6227
6228         /* Set max/min thresholds to 90ms and 80ms respectively */
6229         I915_WRITE(RCBMAXAVG, 90000);
6230         I915_WRITE(RCBMINAVG, 80000);
6231
6232         I915_WRITE(MEMIHYST, 1);
6233
6234         /* Set up min, max, and cur for interrupt handling */
6235         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6236         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6237         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6238                 MEMMODE_FSTART_SHIFT;
6239
6240         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6241                 PXVFREQ_PX_SHIFT;
6242
6243         dev_priv->fmax = fmax; /* IPS callback will increase this */
6244         dev_priv->fstart = fstart;
6245
6246         dev_priv->max_delay = fstart;
6247         dev_priv->min_delay = fmin;
6248         dev_priv->cur_delay = fstart;
6249
6250         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6251                          fmax, fmin, fstart);
6252
6253         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6254
6255         /*
6256          * Interrupts will be enabled in ironlake_irq_postinstall
6257          */
6258
6259         I915_WRITE(VIDSTART, vstart);
6260         POSTING_READ(VIDSTART);
6261
6262         rgvmodectl |= MEMMODE_SWMODE_EN;
6263         I915_WRITE(MEMMODECTL, rgvmodectl);
6264
6265         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6266                 DRM_ERROR("stuck trying to change perf mode\n");
6267         msleep(1);
6268
6269         ironlake_set_drps(dev, fstart);
6270
6271         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6272                 I915_READ(0x112e0);
6273         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6274         dev_priv->last_count2 = I915_READ(0x112f4);
6275         getrawmonotonic(&dev_priv->last_time2);
6276 }
6277
6278 void ironlake_disable_drps(struct drm_device *dev)
6279 {
6280         struct drm_i915_private *dev_priv = dev->dev_private;
6281         u16 rgvswctl = I915_READ16(MEMSWCTL);
6282
6283         /* Ack interrupts, disable EFC interrupt */
6284         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6285         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6286         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6287         I915_WRITE(DEIIR, DE_PCU_EVENT);
6288         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6289
6290         /* Go back to the starting frequency */
6291         ironlake_set_drps(dev, dev_priv->fstart);
6292         msleep(1);
6293         rgvswctl |= MEMCTL_CMD_STS;
6294         I915_WRITE(MEMSWCTL, rgvswctl);
6295         msleep(1);
6296
6297 }
6298
6299 void gen6_set_rps(struct drm_device *dev, u8 val)
6300 {
6301         struct drm_i915_private *dev_priv = dev->dev_private;
6302         u32 swreq;
6303
6304         swreq = (val & 0x3ff) << 25;
6305         I915_WRITE(GEN6_RPNSWREQ, swreq);
6306 }
6307
6308 void gen6_disable_rps(struct drm_device *dev)
6309 {
6310         struct drm_i915_private *dev_priv = dev->dev_private;
6311
6312         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6313         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6314         I915_WRITE(GEN6_PMIER, 0);
6315         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6316 }
6317
6318 static unsigned long intel_pxfreq(u32 vidfreq)
6319 {
6320         unsigned long freq;
6321         int div = (vidfreq & 0x3f0000) >> 16;
6322         int post = (vidfreq & 0x3000) >> 12;
6323         int pre = (vidfreq & 0x7);
6324
6325         if (!pre)
6326                 return 0;
6327
6328         freq = ((div * 133333) / ((1<<post) * pre));
6329
6330         return freq;
6331 }
6332
6333 void intel_init_emon(struct drm_device *dev)
6334 {
6335         struct drm_i915_private *dev_priv = dev->dev_private;
6336         u32 lcfuse;
6337         u8 pxw[16];
6338         int i;
6339
6340         /* Disable to program */
6341         I915_WRITE(ECR, 0);
6342         POSTING_READ(ECR);
6343
6344         /* Program energy weights for various events */
6345         I915_WRITE(SDEW, 0x15040d00);
6346         I915_WRITE(CSIEW0, 0x007f0000);
6347         I915_WRITE(CSIEW1, 0x1e220004);
6348         I915_WRITE(CSIEW2, 0x04000004);
6349
6350         for (i = 0; i < 5; i++)
6351                 I915_WRITE(PEW + (i * 4), 0);
6352         for (i = 0; i < 3; i++)
6353                 I915_WRITE(DEW + (i * 4), 0);
6354
6355         /* Program P-state weights to account for frequency power adjustment */
6356         for (i = 0; i < 16; i++) {
6357                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6358                 unsigned long freq = intel_pxfreq(pxvidfreq);
6359                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6360                         PXVFREQ_PX_SHIFT;
6361                 unsigned long val;
6362
6363                 val = vid * vid;
6364                 val *= (freq / 1000);
6365                 val *= 255;
6366                 val /= (127*127*900);
6367                 if (val > 0xff)
6368                         DRM_ERROR("bad pxval: %ld\n", val);
6369                 pxw[i] = val;
6370         }
6371         /* Render standby states get 0 weight */
6372         pxw[14] = 0;
6373         pxw[15] = 0;
6374
6375         for (i = 0; i < 4; i++) {
6376                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6377                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6378                 I915_WRITE(PXW + (i * 4), val);
6379         }
6380
6381         /* Adjust magic regs to magic values (more experimental results) */
6382         I915_WRITE(OGW0, 0);
6383         I915_WRITE(OGW1, 0);
6384         I915_WRITE(EG0, 0x00007f00);
6385         I915_WRITE(EG1, 0x0000000e);
6386         I915_WRITE(EG2, 0x000e0000);
6387         I915_WRITE(EG3, 0x68000300);
6388         I915_WRITE(EG4, 0x42000000);
6389         I915_WRITE(EG5, 0x00140031);
6390         I915_WRITE(EG6, 0);
6391         I915_WRITE(EG7, 0);
6392
6393         for (i = 0; i < 8; i++)
6394                 I915_WRITE(PXWL + (i * 4), 0);
6395
6396         /* Enable PMON + select events */
6397         I915_WRITE(ECR, 0x80000019);
6398
6399         lcfuse = I915_READ(LCFUSE02);
6400
6401         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6402 }
6403
6404 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6405 {
6406         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6407         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6408         u32 pcu_mbox;
6409         int cur_freq, min_freq, max_freq;
6410         int i;
6411
6412         /* Here begins a magic sequence of register writes to enable
6413          * auto-downclocking.
6414          *
6415          * Perhaps there might be some value in exposing these to
6416          * userspace...
6417          */
6418         I915_WRITE(GEN6_RC_STATE, 0);
6419         __gen6_force_wake_get(dev_priv);
6420
6421         /* disable the counters and set deterministic thresholds */
6422         I915_WRITE(GEN6_RC_CONTROL, 0);
6423
6424         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6425         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6426         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6427         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6428         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6429
6430         for (i = 0; i < I915_NUM_RINGS; i++)
6431                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6432
6433         I915_WRITE(GEN6_RC_SLEEP, 0);
6434         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6435         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6436         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6437         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6438
6439         I915_WRITE(GEN6_RC_CONTROL,
6440                    GEN6_RC_CTL_RC6p_ENABLE |
6441                    GEN6_RC_CTL_RC6_ENABLE |
6442                    GEN6_RC_CTL_EI_MODE(1) |
6443                    GEN6_RC_CTL_HW_ENABLE);
6444
6445         I915_WRITE(GEN6_RPNSWREQ,
6446                    GEN6_FREQUENCY(10) |
6447                    GEN6_OFFSET(0) |
6448                    GEN6_AGGRESSIVE_TURBO);
6449         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6450                    GEN6_FREQUENCY(12));
6451
6452         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6453         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6454                    18 << 24 |
6455                    6 << 16);
6456         I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6457         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6458         I915_WRITE(GEN6_RP_UP_EI, 100000);
6459         I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6460         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6461         I915_WRITE(GEN6_RP_CONTROL,
6462                    GEN6_RP_MEDIA_TURBO |
6463                    GEN6_RP_USE_NORMAL_FREQ |
6464                    GEN6_RP_MEDIA_IS_GFX |
6465                    GEN6_RP_ENABLE |
6466                    GEN6_RP_UP_BUSY_MAX |
6467                    GEN6_RP_DOWN_BUSY_MIN);
6468
6469         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6470                      500))
6471                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6472
6473         I915_WRITE(GEN6_PCODE_DATA, 0);
6474         I915_WRITE(GEN6_PCODE_MAILBOX,
6475                    GEN6_PCODE_READY |
6476                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6477         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6478                      500))
6479                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6480
6481         min_freq = (rp_state_cap & 0xff0000) >> 16;
6482         max_freq = rp_state_cap & 0xff;
6483         cur_freq = (gt_perf_status & 0xff00) >> 8;
6484
6485         /* Check for overclock support */
6486         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6487                      500))
6488                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6489         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6490         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6491         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6492                      500))
6493                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6494         if (pcu_mbox & (1<<31)) { /* OC supported */
6495                 max_freq = pcu_mbox & 0xff;
6496                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6497         }
6498
6499         /* In units of 100MHz */
6500         dev_priv->max_delay = max_freq;
6501         dev_priv->min_delay = min_freq;
6502         dev_priv->cur_delay = cur_freq;
6503
6504         /* requires MSI enabled */
6505         I915_WRITE(GEN6_PMIER,
6506                    GEN6_PM_MBOX_EVENT |
6507                    GEN6_PM_THERMAL_EVENT |
6508                    GEN6_PM_RP_DOWN_TIMEOUT |
6509                    GEN6_PM_RP_UP_THRESHOLD |
6510                    GEN6_PM_RP_DOWN_THRESHOLD |
6511                    GEN6_PM_RP_UP_EI_EXPIRED |
6512                    GEN6_PM_RP_DOWN_EI_EXPIRED);
6513         I915_WRITE(GEN6_PMIMR, 0);
6514         /* enable all PM interrupts */
6515         I915_WRITE(GEN6_PMINTRMSK, 0);
6516
6517         __gen6_force_wake_put(dev_priv);
6518 }
6519
6520 void intel_enable_clock_gating(struct drm_device *dev)
6521 {
6522         struct drm_i915_private *dev_priv = dev->dev_private;
6523
6524         /*
6525          * Disable clock gating reported to work incorrectly according to the
6526          * specs, but enable as much else as we can.
6527          */
6528         if (HAS_PCH_SPLIT(dev)) {
6529                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6530
6531                 if (IS_GEN5(dev)) {
6532                         /* Required for FBC */
6533                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
6534                         /* Required for CxSR */
6535                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6536
6537                         I915_WRITE(PCH_3DCGDIS0,
6538                                    MARIUNIT_CLOCK_GATE_DISABLE |
6539                                    SVSMUNIT_CLOCK_GATE_DISABLE);
6540                         I915_WRITE(PCH_3DCGDIS1,
6541                                    VFMUNIT_CLOCK_GATE_DISABLE);
6542                 }
6543
6544                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6545
6546                 /*
6547                  * On Ibex Peak and Cougar Point, we need to disable clock
6548                  * gating for the panel power sequencer or it will fail to
6549                  * start up when no ports are active.
6550                  */
6551                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6552
6553                 /*
6554                  * According to the spec the following bits should be set in
6555                  * order to enable memory self-refresh
6556                  * The bit 22/21 of 0x42004
6557                  * The bit 5 of 0x42020
6558                  * The bit 15 of 0x45000
6559                  */
6560                 if (IS_GEN5(dev)) {
6561                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6562                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
6563                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6564                         I915_WRITE(ILK_DSPCLK_GATE,
6565                                         (I915_READ(ILK_DSPCLK_GATE) |
6566                                                 ILK_DPARB_CLK_GATE));
6567                         I915_WRITE(DISP_ARB_CTL,
6568                                         (I915_READ(DISP_ARB_CTL) |
6569                                                 DISP_FBC_WM_DIS));
6570                         I915_WRITE(WM3_LP_ILK, 0);
6571                         I915_WRITE(WM2_LP_ILK, 0);
6572                         I915_WRITE(WM1_LP_ILK, 0);
6573                 }
6574                 /*
6575                  * Based on the document from hardware guys the following bits
6576                  * should be set unconditionally in order to enable FBC.
6577                  * The bit 22 of 0x42000
6578                  * The bit 22 of 0x42004
6579                  * The bit 7,8,9 of 0x42020.
6580                  */
6581                 if (IS_IRONLAKE_M(dev)) {
6582                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6583                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6584                                    ILK_FBCQ_DIS);
6585                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6586                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6587                                    ILK_DPARB_GATE);
6588                         I915_WRITE(ILK_DSPCLK_GATE,
6589                                    I915_READ(ILK_DSPCLK_GATE) |
6590                                    ILK_DPFC_DIS1 |
6591                                    ILK_DPFC_DIS2 |
6592                                    ILK_CLK_FBC);
6593                 }
6594
6595                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6596                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6597                            ILK_ELPIN_409_SELECT);
6598
6599                 if (IS_GEN5(dev)) {
6600                         I915_WRITE(_3D_CHICKEN2,
6601                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6602                                    _3D_CHICKEN2_WM_READ_PIPELINED);
6603                 }
6604
6605                 if (IS_GEN6(dev)) {
6606                         I915_WRITE(WM3_LP_ILK, 0);
6607                         I915_WRITE(WM2_LP_ILK, 0);
6608                         I915_WRITE(WM1_LP_ILK, 0);
6609
6610                         /*
6611                          * According to the spec the following bits should be
6612                          * set in order to enable memory self-refresh and fbc:
6613                          * The bit21 and bit22 of 0x42000
6614                          * The bit21 and bit22 of 0x42004
6615                          * The bit5 and bit7 of 0x42020
6616                          * The bit14 of 0x70180
6617                          * The bit14 of 0x71180
6618                          */
6619                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6620                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6621                                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6622                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6623                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6624                                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6625                         I915_WRITE(ILK_DSPCLK_GATE,
6626                                    I915_READ(ILK_DSPCLK_GATE) |
6627                                    ILK_DPARB_CLK_GATE  |
6628                                    ILK_DPFD_CLK_GATE);
6629
6630                         I915_WRITE(DSPACNTR,
6631                                    I915_READ(DSPACNTR) |
6632                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6633                         I915_WRITE(DSPBCNTR,
6634                                    I915_READ(DSPBCNTR) |
6635                                    DISPPLANE_TRICKLE_FEED_DISABLE);
6636                 }
6637         } else if (IS_G4X(dev)) {
6638                 uint32_t dspclk_gate;
6639                 I915_WRITE(RENCLK_GATE_D1, 0);
6640                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6641                        GS_UNIT_CLOCK_GATE_DISABLE |
6642                        CL_UNIT_CLOCK_GATE_DISABLE);
6643                 I915_WRITE(RAMCLK_GATE_D, 0);
6644                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6645                         OVRUNIT_CLOCK_GATE_DISABLE |
6646                         OVCUNIT_CLOCK_GATE_DISABLE;
6647                 if (IS_GM45(dev))
6648                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6649                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6650         } else if (IS_CRESTLINE(dev)) {
6651                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6652                 I915_WRITE(RENCLK_GATE_D2, 0);
6653                 I915_WRITE(DSPCLK_GATE_D, 0);
6654                 I915_WRITE(RAMCLK_GATE_D, 0);
6655                 I915_WRITE16(DEUC, 0);
6656         } else if (IS_BROADWATER(dev)) {
6657                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6658                        I965_RCC_CLOCK_GATE_DISABLE |
6659                        I965_RCPB_CLOCK_GATE_DISABLE |
6660                        I965_ISC_CLOCK_GATE_DISABLE |
6661                        I965_FBC_CLOCK_GATE_DISABLE);
6662                 I915_WRITE(RENCLK_GATE_D2, 0);
6663         } else if (IS_GEN3(dev)) {
6664                 u32 dstate = I915_READ(D_STATE);
6665
6666                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6667                         DSTATE_DOT_CLOCK_GATING;
6668                 I915_WRITE(D_STATE, dstate);
6669         } else if (IS_I85X(dev) || IS_I865G(dev)) {
6670                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6671         } else if (IS_I830(dev)) {
6672                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6673         }
6674 }
6675
6676 void intel_disable_clock_gating(struct drm_device *dev)
6677 {
6678         struct drm_i915_private *dev_priv = dev->dev_private;
6679
6680         if (dev_priv->renderctx) {
6681                 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6682
6683                 I915_WRITE(CCID, 0);
6684                 POSTING_READ(CCID);
6685
6686                 i915_gem_object_unpin(obj);
6687                 drm_gem_object_unreference(&obj->base);
6688                 dev_priv->renderctx = NULL;
6689         }
6690
6691         if (dev_priv->pwrctx) {
6692                 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6693
6694                 I915_WRITE(PWRCTXA, 0);
6695                 POSTING_READ(PWRCTXA);
6696
6697                 i915_gem_object_unpin(obj);
6698                 drm_gem_object_unreference(&obj->base);
6699                 dev_priv->pwrctx = NULL;
6700         }
6701 }
6702
6703 static void ironlake_disable_rc6(struct drm_device *dev)
6704 {
6705         struct drm_i915_private *dev_priv = dev->dev_private;
6706
6707         /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6708         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6709         wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6710                  10);
6711         POSTING_READ(CCID);
6712         I915_WRITE(PWRCTXA, 0);
6713         POSTING_READ(PWRCTXA);
6714         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6715         POSTING_READ(RSTDBYCTL);
6716         i915_gem_object_unpin(dev_priv->renderctx);
6717         drm_gem_object_unreference(&dev_priv->renderctx->base);
6718         dev_priv->renderctx = NULL;
6719         i915_gem_object_unpin(dev_priv->pwrctx);
6720         drm_gem_object_unreference(&dev_priv->pwrctx->base);
6721         dev_priv->pwrctx = NULL;
6722 }
6723
6724 void ironlake_enable_rc6(struct drm_device *dev)
6725 {
6726         struct drm_i915_private *dev_priv = dev->dev_private;
6727         int ret;
6728
6729         /*
6730          * GPU can automatically power down the render unit if given a page
6731          * to save state.
6732          */
6733         ret = BEGIN_LP_RING(6);
6734         if (ret) {
6735                 ironlake_disable_rc6(dev);
6736                 return;
6737         }
6738         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6739         OUT_RING(MI_SET_CONTEXT);
6740         OUT_RING(dev_priv->renderctx->gtt_offset |
6741                  MI_MM_SPACE_GTT |
6742                  MI_SAVE_EXT_STATE_EN |
6743                  MI_RESTORE_EXT_STATE_EN |
6744                  MI_RESTORE_INHIBIT);
6745         OUT_RING(MI_SUSPEND_FLUSH);
6746         OUT_RING(MI_NOOP);
6747         OUT_RING(MI_FLUSH);
6748         ADVANCE_LP_RING();
6749
6750         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6751         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6752 }
6753
6754 /* Set up chip specific display functions */
6755 static void intel_init_display(struct drm_device *dev)
6756 {
6757         struct drm_i915_private *dev_priv = dev->dev_private;
6758
6759         /* We always want a DPMS function */
6760         if (HAS_PCH_SPLIT(dev))
6761                 dev_priv->display.dpms = ironlake_crtc_dpms;
6762         else
6763                 dev_priv->display.dpms = i9xx_crtc_dpms;
6764
6765         if (I915_HAS_FBC(dev)) {
6766                 if (HAS_PCH_SPLIT(dev)) {
6767                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6768                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6769                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6770                 } else if (IS_GM45(dev)) {
6771                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6772                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6773                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6774                 } else if (IS_CRESTLINE(dev)) {
6775                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6776                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6777                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6778                 }
6779                 /* 855GM needs testing */
6780         }
6781
6782         /* Returns the core display clock speed */
6783         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6784                 dev_priv->display.get_display_clock_speed =
6785                         i945_get_display_clock_speed;
6786         else if (IS_I915G(dev))
6787                 dev_priv->display.get_display_clock_speed =
6788                         i915_get_display_clock_speed;
6789         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6790                 dev_priv->display.get_display_clock_speed =
6791                         i9xx_misc_get_display_clock_speed;
6792         else if (IS_I915GM(dev))
6793                 dev_priv->display.get_display_clock_speed =
6794                         i915gm_get_display_clock_speed;
6795         else if (IS_I865G(dev))
6796                 dev_priv->display.get_display_clock_speed =
6797                         i865_get_display_clock_speed;
6798         else if (IS_I85X(dev))
6799                 dev_priv->display.get_display_clock_speed =
6800                         i855_get_display_clock_speed;
6801         else /* 852, 830 */
6802                 dev_priv->display.get_display_clock_speed =
6803                         i830_get_display_clock_speed;
6804
6805         /* For FIFO watermark updates */
6806         if (HAS_PCH_SPLIT(dev)) {
6807                 if (IS_GEN5(dev)) {
6808                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6809                                 dev_priv->display.update_wm = ironlake_update_wm;
6810                         else {
6811                                 DRM_DEBUG_KMS("Failed to get proper latency. "
6812                                               "Disable CxSR\n");
6813                                 dev_priv->display.update_wm = NULL;
6814                         }
6815                 } else if (IS_GEN6(dev)) {
6816                         if (SNB_READ_WM0_LATENCY()) {
6817                                 dev_priv->display.update_wm = sandybridge_update_wm;
6818                         } else {
6819                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6820                                               "Disable CxSR\n");
6821                                 dev_priv->display.update_wm = NULL;
6822                         }
6823                 } else
6824                         dev_priv->display.update_wm = NULL;
6825         } else if (IS_PINEVIEW(dev)) {
6826                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6827                                             dev_priv->is_ddr3,
6828                                             dev_priv->fsb_freq,
6829                                             dev_priv->mem_freq)) {
6830                         DRM_INFO("failed to find known CxSR latency "
6831                                  "(found ddr%s fsb freq %d, mem freq %d), "
6832                                  "disabling CxSR\n",
6833                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
6834                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6835                         /* Disable CxSR and never update its watermark again */
6836                         pineview_disable_cxsr(dev);
6837                         dev_priv->display.update_wm = NULL;
6838                 } else
6839                         dev_priv->display.update_wm = pineview_update_wm;
6840         } else if (IS_G4X(dev))
6841                 dev_priv->display.update_wm = g4x_update_wm;
6842         else if (IS_GEN4(dev))
6843                 dev_priv->display.update_wm = i965_update_wm;
6844         else if (IS_GEN3(dev)) {
6845                 dev_priv->display.update_wm = i9xx_update_wm;
6846                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6847         } else if (IS_I85X(dev)) {
6848                 dev_priv->display.update_wm = i9xx_update_wm;
6849                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6850         } else {
6851                 dev_priv->display.update_wm = i830_update_wm;
6852                 if (IS_845G(dev))
6853                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6854                 else
6855                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6856         }
6857 }
6858
6859 /*
6860  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6861  * resume, or other times.  This quirk makes sure that's the case for
6862  * affected systems.
6863  */
6864 static void quirk_pipea_force (struct drm_device *dev)
6865 {
6866         struct drm_i915_private *dev_priv = dev->dev_private;
6867
6868         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6869         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6870 }
6871
6872 struct intel_quirk {
6873         int device;
6874         int subsystem_vendor;
6875         int subsystem_device;
6876         void (*hook)(struct drm_device *dev);
6877 };
6878
6879 struct intel_quirk intel_quirks[] = {
6880         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6881         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6882         /* HP Mini needs pipe A force quirk (LP: #322104) */
6883         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6884
6885         /* Thinkpad R31 needs pipe A force quirk */
6886         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6887         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6888         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6889
6890         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6891         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6892         /* ThinkPad X40 needs pipe A force quirk */
6893
6894         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6895         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6896
6897         /* 855 & before need to leave pipe A & dpll A up */
6898         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6899         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6900 };
6901
6902 static void intel_init_quirks(struct drm_device *dev)
6903 {
6904         struct pci_dev *d = dev->pdev;
6905         int i;
6906
6907         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6908                 struct intel_quirk *q = &intel_quirks[i];
6909
6910                 if (d->device == q->device &&
6911                     (d->subsystem_vendor == q->subsystem_vendor ||
6912                      q->subsystem_vendor == PCI_ANY_ID) &&
6913                     (d->subsystem_device == q->subsystem_device ||
6914                      q->subsystem_device == PCI_ANY_ID))
6915                         q->hook(dev);
6916         }
6917 }
6918
6919 /* Disable the VGA plane that we never use */
6920 static void i915_disable_vga(struct drm_device *dev)
6921 {
6922         struct drm_i915_private *dev_priv = dev->dev_private;
6923         u8 sr1;
6924         u32 vga_reg;
6925
6926         if (HAS_PCH_SPLIT(dev))
6927                 vga_reg = CPU_VGACNTRL;
6928         else
6929                 vga_reg = VGACNTRL;
6930
6931         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6932         outb(1, VGA_SR_INDEX);
6933         sr1 = inb(VGA_SR_DATA);
6934         outb(sr1 | 1<<5, VGA_SR_DATA);
6935         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6936         udelay(300);
6937
6938         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6939         POSTING_READ(vga_reg);
6940 }
6941
6942 void intel_modeset_init(struct drm_device *dev)
6943 {
6944         struct drm_i915_private *dev_priv = dev->dev_private;
6945         int i;
6946
6947         drm_mode_config_init(dev);
6948
6949         dev->mode_config.min_width = 0;
6950         dev->mode_config.min_height = 0;
6951
6952         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6953
6954         intel_init_quirks(dev);
6955
6956         intel_init_display(dev);
6957
6958         if (IS_GEN2(dev)) {
6959                 dev->mode_config.max_width = 2048;
6960                 dev->mode_config.max_height = 2048;
6961         } else if (IS_GEN3(dev)) {
6962                 dev->mode_config.max_width = 4096;
6963                 dev->mode_config.max_height = 4096;
6964         } else {
6965                 dev->mode_config.max_width = 8192;
6966                 dev->mode_config.max_height = 8192;
6967         }
6968         dev->mode_config.fb_base = dev->agp->base;
6969
6970         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6971                 dev_priv->num_pipe = 2;
6972         else
6973                 dev_priv->num_pipe = 1;
6974         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6975                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6976
6977         for (i = 0; i < dev_priv->num_pipe; i++) {
6978                 intel_crtc_init(dev, i);
6979         }
6980
6981         intel_setup_outputs(dev);
6982
6983         intel_enable_clock_gating(dev);
6984
6985         /* Just disable it once at startup */
6986         i915_disable_vga(dev);
6987
6988         if (IS_IRONLAKE_M(dev)) {
6989                 ironlake_enable_drps(dev);
6990                 intel_init_emon(dev);
6991         }
6992
6993         if (IS_GEN6(dev))
6994                 gen6_enable_rps(dev_priv);
6995
6996         if (IS_IRONLAKE_M(dev)) {
6997                 dev_priv->renderctx = intel_alloc_context_page(dev);
6998                 if (!dev_priv->renderctx)
6999                         goto skip_rc6;
7000                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7001                 if (!dev_priv->pwrctx) {
7002                         i915_gem_object_unpin(dev_priv->renderctx);
7003                         drm_gem_object_unreference(&dev_priv->renderctx->base);
7004                         dev_priv->renderctx = NULL;
7005                         goto skip_rc6;
7006                 }
7007                 ironlake_enable_rc6(dev);
7008         }
7009
7010 skip_rc6:
7011         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7012         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7013                     (unsigned long)dev);
7014
7015         intel_setup_overlay(dev);
7016 }
7017
7018 void intel_modeset_cleanup(struct drm_device *dev)
7019 {
7020         struct drm_i915_private *dev_priv = dev->dev_private;
7021         struct drm_crtc *crtc;
7022         struct intel_crtc *intel_crtc;
7023
7024         drm_kms_helper_poll_fini(dev);
7025         mutex_lock(&dev->struct_mutex);
7026
7027         intel_unregister_dsm_handler();
7028
7029
7030         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7031                 /* Skip inactive CRTCs */
7032                 if (!crtc->fb)
7033                         continue;
7034
7035                 intel_crtc = to_intel_crtc(crtc);
7036                 intel_increase_pllclock(crtc);
7037         }
7038
7039         if (dev_priv->display.disable_fbc)
7040                 dev_priv->display.disable_fbc(dev);
7041
7042         if (IS_IRONLAKE_M(dev))
7043                 ironlake_disable_drps(dev);
7044         if (IS_GEN6(dev))
7045                 gen6_disable_rps(dev);
7046
7047         if (IS_IRONLAKE_M(dev))
7048                 ironlake_disable_rc6(dev);
7049
7050         mutex_unlock(&dev->struct_mutex);
7051
7052         /* Disable the irq before mode object teardown, for the irq might
7053          * enqueue unpin/hotplug work. */
7054         drm_irq_uninstall(dev);
7055         cancel_work_sync(&dev_priv->hotplug_work);
7056
7057         /* Shut off idle work before the crtcs get freed. */
7058         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7059                 intel_crtc = to_intel_crtc(crtc);
7060                 del_timer_sync(&intel_crtc->idle_timer);
7061         }
7062         del_timer_sync(&dev_priv->idle_timer);
7063         cancel_work_sync(&dev_priv->idle_work);
7064
7065         drm_mode_config_cleanup(dev);
7066 }
7067
7068 /*
7069  * Return which encoder is currently attached for connector.
7070  */
7071 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7072 {
7073         return &intel_attached_encoder(connector)->base;
7074 }
7075
7076 void intel_connector_attach_encoder(struct intel_connector *connector,
7077                                     struct intel_encoder *encoder)
7078 {
7079         connector->encoder = encoder;
7080         drm_mode_connector_attach_encoder(&connector->base,
7081                                           &encoder->base);
7082 }
7083
7084 /*
7085  * set vga decode state - true == enable VGA decode
7086  */
7087 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7088 {
7089         struct drm_i915_private *dev_priv = dev->dev_private;
7090         u16 gmch_ctrl;
7091
7092         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7093         if (state)
7094                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7095         else
7096                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7097         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7098         return 0;
7099 }
7100
7101 #ifdef CONFIG_DEBUG_FS
7102 #include <linux/seq_file.h>
7103
7104 struct intel_display_error_state {
7105         struct intel_cursor_error_state {
7106                 u32 control;
7107                 u32 position;
7108                 u32 base;
7109                 u32 size;
7110         } cursor[2];
7111
7112         struct intel_pipe_error_state {
7113                 u32 conf;
7114                 u32 source;
7115
7116                 u32 htotal;
7117                 u32 hblank;
7118                 u32 hsync;
7119                 u32 vtotal;
7120                 u32 vblank;
7121                 u32 vsync;
7122         } pipe[2];
7123
7124         struct intel_plane_error_state {
7125                 u32 control;
7126                 u32 stride;
7127                 u32 size;
7128                 u32 pos;
7129                 u32 addr;
7130                 u32 surface;
7131                 u32 tile_offset;
7132         } plane[2];
7133 };
7134
7135 struct intel_display_error_state *
7136 intel_display_capture_error_state(struct drm_device *dev)
7137 {
7138         drm_i915_private_t *dev_priv = dev->dev_private;
7139         struct intel_display_error_state *error;
7140         int i;
7141
7142         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7143         if (error == NULL)
7144                 return NULL;
7145
7146         for (i = 0; i < 2; i++) {
7147                 error->cursor[i].control = I915_READ(CURCNTR(i));
7148                 error->cursor[i].position = I915_READ(CURPOS(i));
7149                 error->cursor[i].base = I915_READ(CURBASE(i));
7150
7151                 error->plane[i].control = I915_READ(DSPCNTR(i));
7152                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7153                 error->plane[i].size = I915_READ(DSPSIZE(i));
7154                 error->plane[i].pos= I915_READ(DSPPOS(i));
7155                 error->plane[i].addr = I915_READ(DSPADDR(i));
7156                 if (INTEL_INFO(dev)->gen >= 4) {
7157                         error->plane[i].surface = I915_READ(DSPSURF(i));
7158                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7159                 }
7160
7161                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7162                 error->pipe[i].source = I915_READ(PIPESRC(i));
7163                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7164                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7165                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7166                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7167                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7168                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7169         }
7170
7171         return error;
7172 }
7173
7174 void
7175 intel_display_print_error_state(struct seq_file *m,
7176                                 struct drm_device *dev,
7177                                 struct intel_display_error_state *error)
7178 {
7179         int i;
7180
7181         for (i = 0; i < 2; i++) {
7182                 seq_printf(m, "Pipe [%d]:\n", i);
7183                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7184                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7185                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7186                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7187                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7188                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7189                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7190                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7191
7192                 seq_printf(m, "Plane [%d]:\n", i);
7193                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7194                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7195                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7196                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7197                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7198                 if (INTEL_INFO(dev)->gen >= 4) {
7199                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7200                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7201                 }
7202
7203                 seq_printf(m, "Cursor [%d]:\n", i);
7204                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7205                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7206                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7207         }
7208 }
7209 #endif