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1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54         return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59         DRM_FORMAT_C8,
60         DRM_FORMAT_RGB565,
61         DRM_FORMAT_XRGB1555,
62         DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67         DRM_FORMAT_C8,
68         DRM_FORMAT_RGB565,
69         DRM_FORMAT_XRGB8888,
70         DRM_FORMAT_XBGR8888,
71         DRM_FORMAT_XRGB2101010,
72         DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76         DRM_FORMAT_C8,
77         DRM_FORMAT_RGB565,
78         DRM_FORMAT_XRGB8888,
79         DRM_FORMAT_XBGR8888,
80         DRM_FORMAT_ARGB8888,
81         DRM_FORMAT_ABGR8888,
82         DRM_FORMAT_XRGB2101010,
83         DRM_FORMAT_XBGR2101010,
84         DRM_FORMAT_YUYV,
85         DRM_FORMAT_YVYU,
86         DRM_FORMAT_UYVY,
87         DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92         DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96                                 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98                                    struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101                                   struct drm_i915_gem_object *obj,
102                                   struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107                                          struct intel_link_m_n *m_n,
108                                          struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113                             const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115                             const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119                                     struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125
126 struct intel_limit {
127         struct {
128                 int min, max;
129         } dot, vco, n, m, m1, m2, p, p1;
130
131         struct {
132                 int dot_limit;
133                 int p2_slow, p2_fast;
134         } p2;
135 };
136
137 /* returns HPLL frequency in kHz */
138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
139 {
140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142         /* Obtain SKU information */
143         mutex_lock(&dev_priv->sb_lock);
144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145                 CCK_FUSE_HPLL_FREQ_MASK;
146         mutex_unlock(&dev_priv->sb_lock);
147
148         return vco_freq[hpll_freq] * 1000;
149 }
150
151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152                       const char *name, u32 reg, int ref_freq)
153 {
154         u32 val;
155         int divider;
156
157         mutex_lock(&dev_priv->sb_lock);
158         val = vlv_cck_read(dev_priv, reg);
159         mutex_unlock(&dev_priv->sb_lock);
160
161         divider = val & CCK_FREQUENCY_VALUES;
162
163         WARN((val & CCK_FREQUENCY_STATUS) !=
164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
165              "%s change in progress\n", name);
166
167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
168 }
169
170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171                            const char *name, u32 reg)
172 {
173         if (dev_priv->hpll_freq == 0)
174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
175
176         return vlv_get_cck_clock(dev_priv, name, reg,
177                                  dev_priv->hpll_freq);
178 }
179
180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
181 {
182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
183                 return;
184
185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186                                                       CCK_CZ_CLOCK_CONTROL);
187
188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
189 }
190
191 static inline u32 /* units of 100MHz */
192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193                     const struct intel_crtc_state *pipe_config)
194 {
195         if (HAS_DDI(dev_priv))
196                 return pipe_config->port_clock; /* SPLL */
197         else if (IS_GEN5(dev_priv))
198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
199         else
200                 return 270000;
201 }
202
203 static const struct intel_limit intel_limits_i8xx_dac = {
204         .dot = { .min = 25000, .max = 350000 },
205         .vco = { .min = 908000, .max = 1512000 },
206         .n = { .min = 2, .max = 16 },
207         .m = { .min = 96, .max = 140 },
208         .m1 = { .min = 18, .max = 26 },
209         .m2 = { .min = 6, .max = 16 },
210         .p = { .min = 4, .max = 128 },
211         .p1 = { .min = 2, .max = 33 },
212         .p2 = { .dot_limit = 165000,
213                 .p2_slow = 4, .p2_fast = 2 },
214 };
215
216 static const struct intel_limit intel_limits_i8xx_dvo = {
217         .dot = { .min = 25000, .max = 350000 },
218         .vco = { .min = 908000, .max = 1512000 },
219         .n = { .min = 2, .max = 16 },
220         .m = { .min = 96, .max = 140 },
221         .m1 = { .min = 18, .max = 26 },
222         .m2 = { .min = 6, .max = 16 },
223         .p = { .min = 4, .max = 128 },
224         .p1 = { .min = 2, .max = 33 },
225         .p2 = { .dot_limit = 165000,
226                 .p2_slow = 4, .p2_fast = 4 },
227 };
228
229 static const struct intel_limit intel_limits_i8xx_lvds = {
230         .dot = { .min = 25000, .max = 350000 },
231         .vco = { .min = 908000, .max = 1512000 },
232         .n = { .min = 2, .max = 16 },
233         .m = { .min = 96, .max = 140 },
234         .m1 = { .min = 18, .max = 26 },
235         .m2 = { .min = 6, .max = 16 },
236         .p = { .min = 4, .max = 128 },
237         .p1 = { .min = 1, .max = 6 },
238         .p2 = { .dot_limit = 165000,
239                 .p2_slow = 14, .p2_fast = 7 },
240 };
241
242 static const struct intel_limit intel_limits_i9xx_sdvo = {
243         .dot = { .min = 20000, .max = 400000 },
244         .vco = { .min = 1400000, .max = 2800000 },
245         .n = { .min = 1, .max = 6 },
246         .m = { .min = 70, .max = 120 },
247         .m1 = { .min = 8, .max = 18 },
248         .m2 = { .min = 3, .max = 7 },
249         .p = { .min = 5, .max = 80 },
250         .p1 = { .min = 1, .max = 8 },
251         .p2 = { .dot_limit = 200000,
252                 .p2_slow = 10, .p2_fast = 5 },
253 };
254
255 static const struct intel_limit intel_limits_i9xx_lvds = {
256         .dot = { .min = 20000, .max = 400000 },
257         .vco = { .min = 1400000, .max = 2800000 },
258         .n = { .min = 1, .max = 6 },
259         .m = { .min = 70, .max = 120 },
260         .m1 = { .min = 8, .max = 18 },
261         .m2 = { .min = 3, .max = 7 },
262         .p = { .min = 7, .max = 98 },
263         .p1 = { .min = 1, .max = 8 },
264         .p2 = { .dot_limit = 112000,
265                 .p2_slow = 14, .p2_fast = 7 },
266 };
267
268
269 static const struct intel_limit intel_limits_g4x_sdvo = {
270         .dot = { .min = 25000, .max = 270000 },
271         .vco = { .min = 1750000, .max = 3500000},
272         .n = { .min = 1, .max = 4 },
273         .m = { .min = 104, .max = 138 },
274         .m1 = { .min = 17, .max = 23 },
275         .m2 = { .min = 5, .max = 11 },
276         .p = { .min = 10, .max = 30 },
277         .p1 = { .min = 1, .max = 3},
278         .p2 = { .dot_limit = 270000,
279                 .p2_slow = 10,
280                 .p2_fast = 10
281         },
282 };
283
284 static const struct intel_limit intel_limits_g4x_hdmi = {
285         .dot = { .min = 22000, .max = 400000 },
286         .vco = { .min = 1750000, .max = 3500000},
287         .n = { .min = 1, .max = 4 },
288         .m = { .min = 104, .max = 138 },
289         .m1 = { .min = 16, .max = 23 },
290         .m2 = { .min = 5, .max = 11 },
291         .p = { .min = 5, .max = 80 },
292         .p1 = { .min = 1, .max = 8},
293         .p2 = { .dot_limit = 165000,
294                 .p2_slow = 10, .p2_fast = 5 },
295 };
296
297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
298         .dot = { .min = 20000, .max = 115000 },
299         .vco = { .min = 1750000, .max = 3500000 },
300         .n = { .min = 1, .max = 3 },
301         .m = { .min = 104, .max = 138 },
302         .m1 = { .min = 17, .max = 23 },
303         .m2 = { .min = 5, .max = 11 },
304         .p = { .min = 28, .max = 112 },
305         .p1 = { .min = 2, .max = 8 },
306         .p2 = { .dot_limit = 0,
307                 .p2_slow = 14, .p2_fast = 14
308         },
309 };
310
311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
312         .dot = { .min = 80000, .max = 224000 },
313         .vco = { .min = 1750000, .max = 3500000 },
314         .n = { .min = 1, .max = 3 },
315         .m = { .min = 104, .max = 138 },
316         .m1 = { .min = 17, .max = 23 },
317         .m2 = { .min = 5, .max = 11 },
318         .p = { .min = 14, .max = 42 },
319         .p1 = { .min = 2, .max = 6 },
320         .p2 = { .dot_limit = 0,
321                 .p2_slow = 7, .p2_fast = 7
322         },
323 };
324
325 static const struct intel_limit intel_limits_pineview_sdvo = {
326         .dot = { .min = 20000, .max = 400000},
327         .vco = { .min = 1700000, .max = 3500000 },
328         /* Pineview's Ncounter is a ring counter */
329         .n = { .min = 3, .max = 6 },
330         .m = { .min = 2, .max = 256 },
331         /* Pineview only has one combined m divider, which we treat as m2. */
332         .m1 = { .min = 0, .max = 0 },
333         .m2 = { .min = 0, .max = 254 },
334         .p = { .min = 5, .max = 80 },
335         .p1 = { .min = 1, .max = 8 },
336         .p2 = { .dot_limit = 200000,
337                 .p2_slow = 10, .p2_fast = 5 },
338 };
339
340 static const struct intel_limit intel_limits_pineview_lvds = {
341         .dot = { .min = 20000, .max = 400000 },
342         .vco = { .min = 1700000, .max = 3500000 },
343         .n = { .min = 3, .max = 6 },
344         .m = { .min = 2, .max = 256 },
345         .m1 = { .min = 0, .max = 0 },
346         .m2 = { .min = 0, .max = 254 },
347         .p = { .min = 7, .max = 112 },
348         .p1 = { .min = 1, .max = 8 },
349         .p2 = { .dot_limit = 112000,
350                 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 /* Ironlake / Sandybridge
354  *
355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
356  * the range value for them is (actual_value - 2).
357  */
358 static const struct intel_limit intel_limits_ironlake_dac = {
359         .dot = { .min = 25000, .max = 350000 },
360         .vco = { .min = 1760000, .max = 3510000 },
361         .n = { .min = 1, .max = 5 },
362         .m = { .min = 79, .max = 127 },
363         .m1 = { .min = 12, .max = 22 },
364         .m2 = { .min = 5, .max = 9 },
365         .p = { .min = 5, .max = 80 },
366         .p1 = { .min = 1, .max = 8 },
367         .p2 = { .dot_limit = 225000,
368                 .p2_slow = 10, .p2_fast = 5 },
369 };
370
371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
372         .dot = { .min = 25000, .max = 350000 },
373         .vco = { .min = 1760000, .max = 3510000 },
374         .n = { .min = 1, .max = 3 },
375         .m = { .min = 79, .max = 118 },
376         .m1 = { .min = 12, .max = 22 },
377         .m2 = { .min = 5, .max = 9 },
378         .p = { .min = 28, .max = 112 },
379         .p1 = { .min = 2, .max = 8 },
380         .p2 = { .dot_limit = 225000,
381                 .p2_slow = 14, .p2_fast = 14 },
382 };
383
384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
385         .dot = { .min = 25000, .max = 350000 },
386         .vco = { .min = 1760000, .max = 3510000 },
387         .n = { .min = 1, .max = 3 },
388         .m = { .min = 79, .max = 127 },
389         .m1 = { .min = 12, .max = 22 },
390         .m2 = { .min = 5, .max = 9 },
391         .p = { .min = 14, .max = 56 },
392         .p1 = { .min = 2, .max = 8 },
393         .p2 = { .dot_limit = 225000,
394                 .p2_slow = 7, .p2_fast = 7 },
395 };
396
397 /* LVDS 100mhz refclk limits. */
398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
399         .dot = { .min = 25000, .max = 350000 },
400         .vco = { .min = 1760000, .max = 3510000 },
401         .n = { .min = 1, .max = 2 },
402         .m = { .min = 79, .max = 126 },
403         .m1 = { .min = 12, .max = 22 },
404         .m2 = { .min = 5, .max = 9 },
405         .p = { .min = 28, .max = 112 },
406         .p1 = { .min = 2, .max = 8 },
407         .p2 = { .dot_limit = 225000,
408                 .p2_slow = 14, .p2_fast = 14 },
409 };
410
411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
412         .dot = { .min = 25000, .max = 350000 },
413         .vco = { .min = 1760000, .max = 3510000 },
414         .n = { .min = 1, .max = 3 },
415         .m = { .min = 79, .max = 126 },
416         .m1 = { .min = 12, .max = 22 },
417         .m2 = { .min = 5, .max = 9 },
418         .p = { .min = 14, .max = 42 },
419         .p1 = { .min = 2, .max = 6 },
420         .p2 = { .dot_limit = 225000,
421                 .p2_slow = 7, .p2_fast = 7 },
422 };
423
424 static const struct intel_limit intel_limits_vlv = {
425          /*
426           * These are the data rate limits (measured in fast clocks)
427           * since those are the strictest limits we have. The fast
428           * clock and actual rate limits are more relaxed, so checking
429           * them would make no difference.
430           */
431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
432         .vco = { .min = 4000000, .max = 6000000 },
433         .n = { .min = 1, .max = 7 },
434         .m1 = { .min = 2, .max = 3 },
435         .m2 = { .min = 11, .max = 156 },
436         .p1 = { .min = 2, .max = 3 },
437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
438 };
439
440 static const struct intel_limit intel_limits_chv = {
441         /*
442          * These are the data rate limits (measured in fast clocks)
443          * since those are the strictest limits we have.  The fast
444          * clock and actual rate limits are more relaxed, so checking
445          * them would make no difference.
446          */
447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
448         .vco = { .min = 4800000, .max = 6480000 },
449         .n = { .min = 1, .max = 1 },
450         .m1 = { .min = 2, .max = 2 },
451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
452         .p1 = { .min = 2, .max = 4 },
453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
454 };
455
456 static const struct intel_limit intel_limits_bxt = {
457         /* FIXME: find real dot limits */
458         .dot = { .min = 0, .max = INT_MAX },
459         .vco = { .min = 4800000, .max = 6700000 },
460         .n = { .min = 1, .max = 1 },
461         .m1 = { .min = 2, .max = 2 },
462         /* FIXME: find real m2 limits */
463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
464         .p1 = { .min = 2, .max = 4 },
465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
466 };
467
468 static bool
469 needs_modeset(struct drm_crtc_state *state)
470 {
471         return drm_atomic_crtc_needs_modeset(state);
472 }
473
474 /*
475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
478  * The helpers' return value is the rate of the clock that is fed to the
479  * display engine's pipe which can be the above fast dot clock rate or a
480  * divided-down version of it.
481  */
482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
484 {
485         clock->m = clock->m2 + 2;
486         clock->p = clock->p1 * clock->p2;
487         if (WARN_ON(clock->n == 0 || clock->p == 0))
488                 return 0;
489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
491
492         return clock->dot;
493 }
494
495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
496 {
497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
498 }
499
500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
501 {
502         clock->m = i9xx_dpll_compute_m(clock);
503         clock->p = clock->p1 * clock->p2;
504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
505                 return 0;
506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
508
509         return clock->dot;
510 }
511
512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
513 {
514         clock->m = clock->m1 * clock->m2;
515         clock->p = clock->p1 * clock->p2;
516         if (WARN_ON(clock->n == 0 || clock->p == 0))
517                 return 0;
518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520
521         return clock->dot / 5;
522 }
523
524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
525 {
526         clock->m = clock->m1 * clock->m2;
527         clock->p = clock->p1 * clock->p2;
528         if (WARN_ON(clock->n == 0 || clock->p == 0))
529                 return 0;
530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
531                         clock->n << 22);
532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534         return clock->dot / 5;
535 }
536
537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
538 /**
539  * Returns whether the given set of divisors are valid for a given refclk with
540  * the given connectors.
541  */
542
543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
544                                const struct intel_limit *limit,
545                                const struct dpll *clock)
546 {
547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
548                 INTELPllInvalid("n out of range\n");
549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
550                 INTELPllInvalid("p1 out of range\n");
551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
552                 INTELPllInvalid("m2 out of range\n");
553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
554                 INTELPllInvalid("m1 out of range\n");
555
556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
558                 if (clock->m1 <= clock->m2)
559                         INTELPllInvalid("m1 <= m2\n");
560
561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
562             !IS_GEN9_LP(dev_priv)) {
563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
564                         INTELPllInvalid("p out of range\n");
565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
566                         INTELPllInvalid("m out of range\n");
567         }
568
569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570                 INTELPllInvalid("vco out of range\n");
571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572          * connector, etc., rather than just a single range.
573          */
574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575                 INTELPllInvalid("dot out of range\n");
576
577         return true;
578 }
579
580 static int
581 i9xx_select_p2_div(const struct intel_limit *limit,
582                    const struct intel_crtc_state *crtc_state,
583                    int target)
584 {
585         struct drm_device *dev = crtc_state->base.crtc->dev;
586
587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
588                 /*
589                  * For LVDS just rely on its current settings for dual-channel.
590                  * We haven't figured out how to reliably set up different
591                  * single/dual channel state, if we even can.
592                  */
593                 if (intel_is_dual_link_lvds(dev))
594                         return limit->p2.p2_fast;
595                 else
596                         return limit->p2.p2_slow;
597         } else {
598                 if (target < limit->p2.dot_limit)
599                         return limit->p2.p2_slow;
600                 else
601                         return limit->p2.p2_fast;
602         }
603 }
604
605 /*
606  * Returns a set of divisors for the desired target clock with the given
607  * refclk, or FALSE.  The returned values represent the clock equation:
608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
609  *
610  * Target and reference clocks are specified in kHz.
611  *
612  * If match_clock is provided, then best_clock P divider must match the P
613  * divider from @match_clock used for LVDS downclocking.
614  */
615 static bool
616 i9xx_find_best_dpll(const struct intel_limit *limit,
617                     struct intel_crtc_state *crtc_state,
618                     int target, int refclk, struct dpll *match_clock,
619                     struct dpll *best_clock)
620 {
621         struct drm_device *dev = crtc_state->base.crtc->dev;
622         struct dpll clock;
623         int err = target;
624
625         memset(best_clock, 0, sizeof(*best_clock));
626
627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
628
629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630              clock.m1++) {
631                 for (clock.m2 = limit->m2.min;
632                      clock.m2 <= limit->m2.max; clock.m2++) {
633                         if (clock.m2 >= clock.m1)
634                                 break;
635                         for (clock.n = limit->n.min;
636                              clock.n <= limit->n.max; clock.n++) {
637                                 for (clock.p1 = limit->p1.min;
638                                         clock.p1 <= limit->p1.max; clock.p1++) {
639                                         int this_err;
640
641                                         i9xx_calc_dpll_params(refclk, &clock);
642                                         if (!intel_PLL_is_valid(to_i915(dev),
643                                                                 limit,
644                                                                 &clock))
645                                                 continue;
646                                         if (match_clock &&
647                                             clock.p != match_clock->p)
648                                                 continue;
649
650                                         this_err = abs(clock.dot - target);
651                                         if (this_err < err) {
652                                                 *best_clock = clock;
653                                                 err = this_err;
654                                         }
655                                 }
656                         }
657                 }
658         }
659
660         return (err != target);
661 }
662
663 /*
664  * Returns a set of divisors for the desired target clock with the given
665  * refclk, or FALSE.  The returned values represent the clock equation:
666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667  *
668  * Target and reference clocks are specified in kHz.
669  *
670  * If match_clock is provided, then best_clock P divider must match the P
671  * divider from @match_clock used for LVDS downclocking.
672  */
673 static bool
674 pnv_find_best_dpll(const struct intel_limit *limit,
675                    struct intel_crtc_state *crtc_state,
676                    int target, int refclk, struct dpll *match_clock,
677                    struct dpll *best_clock)
678 {
679         struct drm_device *dev = crtc_state->base.crtc->dev;
680         struct dpll clock;
681         int err = target;
682
683         memset(best_clock, 0, sizeof(*best_clock));
684
685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688              clock.m1++) {
689                 for (clock.m2 = limit->m2.min;
690                      clock.m2 <= limit->m2.max; clock.m2++) {
691                         for (clock.n = limit->n.min;
692                              clock.n <= limit->n.max; clock.n++) {
693                                 for (clock.p1 = limit->p1.min;
694                                         clock.p1 <= limit->p1.max; clock.p1++) {
695                                         int this_err;
696
697                                         pnv_calc_dpll_params(refclk, &clock);
698                                         if (!intel_PLL_is_valid(to_i915(dev),
699                                                                 limit,
700                                                                 &clock))
701                                                 continue;
702                                         if (match_clock &&
703                                             clock.p != match_clock->p)
704                                                 continue;
705
706                                         this_err = abs(clock.dot - target);
707                                         if (this_err < err) {
708                                                 *best_clock = clock;
709                                                 err = this_err;
710                                         }
711                                 }
712                         }
713                 }
714         }
715
716         return (err != target);
717 }
718
719 /*
720  * Returns a set of divisors for the desired target clock with the given
721  * refclk, or FALSE.  The returned values represent the clock equation:
722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
723  *
724  * Target and reference clocks are specified in kHz.
725  *
726  * If match_clock is provided, then best_clock P divider must match the P
727  * divider from @match_clock used for LVDS downclocking.
728  */
729 static bool
730 g4x_find_best_dpll(const struct intel_limit *limit,
731                    struct intel_crtc_state *crtc_state,
732                    int target, int refclk, struct dpll *match_clock,
733                    struct dpll *best_clock)
734 {
735         struct drm_device *dev = crtc_state->base.crtc->dev;
736         struct dpll clock;
737         int max_n;
738         bool found = false;
739         /* approximately equals target * 0.00585 */
740         int err_most = (target >> 8) + (target >> 9);
741
742         memset(best_clock, 0, sizeof(*best_clock));
743
744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
746         max_n = limit->n.max;
747         /* based on hardware requirement, prefer smaller n to precision */
748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749                 /* based on hardware requirement, prefere larger m1,m2 */
750                 for (clock.m1 = limit->m1.max;
751                      clock.m1 >= limit->m1.min; clock.m1--) {
752                         for (clock.m2 = limit->m2.max;
753                              clock.m2 >= limit->m2.min; clock.m2--) {
754                                 for (clock.p1 = limit->p1.max;
755                                      clock.p1 >= limit->p1.min; clock.p1--) {
756                                         int this_err;
757
758                                         i9xx_calc_dpll_params(refclk, &clock);
759                                         if (!intel_PLL_is_valid(to_i915(dev),
760                                                                 limit,
761                                                                 &clock))
762                                                 continue;
763
764                                         this_err = abs(clock.dot - target);
765                                         if (this_err < err_most) {
766                                                 *best_clock = clock;
767                                                 err_most = this_err;
768                                                 max_n = clock.n;
769                                                 found = true;
770                                         }
771                                 }
772                         }
773                 }
774         }
775         return found;
776 }
777
778 /*
779  * Check if the calculated PLL configuration is more optimal compared to the
780  * best configuration and error found so far. Return the calculated error.
781  */
782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
783                                const struct dpll *calculated_clock,
784                                const struct dpll *best_clock,
785                                unsigned int best_error_ppm,
786                                unsigned int *error_ppm)
787 {
788         /*
789          * For CHV ignore the error and consider only the P value.
790          * Prefer a bigger P value based on HW requirements.
791          */
792         if (IS_CHERRYVIEW(to_i915(dev))) {
793                 *error_ppm = 0;
794
795                 return calculated_clock->p > best_clock->p;
796         }
797
798         if (WARN_ON_ONCE(!target_freq))
799                 return false;
800
801         *error_ppm = div_u64(1000000ULL *
802                                 abs(target_freq - calculated_clock->dot),
803                              target_freq);
804         /*
805          * Prefer a better P value over a better (smaller) error if the error
806          * is small. Ensure this preference for future configurations too by
807          * setting the error to 0.
808          */
809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
810                 *error_ppm = 0;
811
812                 return true;
813         }
814
815         return *error_ppm + 10 < best_error_ppm;
816 }
817
818 /*
819  * Returns a set of divisors for the desired target clock with the given
820  * refclk, or FALSE.  The returned values represent the clock equation:
821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822  */
823 static bool
824 vlv_find_best_dpll(const struct intel_limit *limit,
825                    struct intel_crtc_state *crtc_state,
826                    int target, int refclk, struct dpll *match_clock,
827                    struct dpll *best_clock)
828 {
829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
830         struct drm_device *dev = crtc->base.dev;
831         struct dpll clock;
832         unsigned int bestppm = 1000000;
833         /* min update 19.2 MHz */
834         int max_n = min(limit->n.max, refclk / 19200);
835         bool found = false;
836
837         target *= 5; /* fast clock */
838
839         memset(best_clock, 0, sizeof(*best_clock));
840
841         /* based on hardware requirement, prefer smaller n to precision */
842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
846                                 clock.p = clock.p1 * clock.p2;
847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
849                                         unsigned int ppm;
850
851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
852                                                                      refclk * clock.m1);
853
854                                         vlv_calc_dpll_params(refclk, &clock);
855
856                                         if (!intel_PLL_is_valid(to_i915(dev),
857                                                                 limit,
858                                                                 &clock))
859                                                 continue;
860
861                                         if (!vlv_PLL_is_optimal(dev, target,
862                                                                 &clock,
863                                                                 best_clock,
864                                                                 bestppm, &ppm))
865                                                 continue;
866
867                                         *best_clock = clock;
868                                         bestppm = ppm;
869                                         found = true;
870                                 }
871                         }
872                 }
873         }
874
875         return found;
876 }
877
878 /*
879  * Returns a set of divisors for the desired target clock with the given
880  * refclk, or FALSE.  The returned values represent the clock equation:
881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882  */
883 static bool
884 chv_find_best_dpll(const struct intel_limit *limit,
885                    struct intel_crtc_state *crtc_state,
886                    int target, int refclk, struct dpll *match_clock,
887                    struct dpll *best_clock)
888 {
889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890         struct drm_device *dev = crtc->base.dev;
891         unsigned int best_error_ppm;
892         struct dpll clock;
893         uint64_t m2;
894         int found = false;
895
896         memset(best_clock, 0, sizeof(*best_clock));
897         best_error_ppm = 1000000;
898
899         /*
900          * Based on hardware doc, the n always set to 1, and m1 always
901          * set to 2.  If requires to support 200Mhz refclk, we need to
902          * revisit this because n may not 1 anymore.
903          */
904         clock.n = 1, clock.m1 = 2;
905         target *= 5;    /* fast clock */
906
907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
908                 for (clock.p2 = limit->p2.p2_fast;
909                                 clock.p2 >= limit->p2.p2_slow;
910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
911                         unsigned int error_ppm;
912
913                         clock.p = clock.p1 * clock.p2;
914
915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
916                                         clock.n) << 22, refclk * clock.m1);
917
918                         if (m2 > INT_MAX/clock.m1)
919                                 continue;
920
921                         clock.m2 = m2;
922
923                         chv_calc_dpll_params(refclk, &clock);
924
925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
926                                 continue;
927
928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
929                                                 best_error_ppm, &error_ppm))
930                                 continue;
931
932                         *best_clock = clock;
933                         best_error_ppm = error_ppm;
934                         found = true;
935                 }
936         }
937
938         return found;
939 }
940
941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
942                         struct dpll *best_clock)
943 {
944         int refclk = 100000;
945         const struct intel_limit *limit = &intel_limits_bxt;
946
947         return chv_find_best_dpll(limit, crtc_state,
948                                   target_clock, refclk, NULL, best_clock);
949 }
950
951 bool intel_crtc_active(struct intel_crtc *crtc)
952 {
953         /* Be paranoid as we can arrive here with only partial
954          * state retrieved from the hardware during setup.
955          *
956          * We can ditch the adjusted_mode.crtc_clock check as soon
957          * as Haswell has gained clock readout/fastboot support.
958          *
959          * We can ditch the crtc->primary->fb check as soon as we can
960          * properly reconstruct framebuffers.
961          *
962          * FIXME: The intel_crtc->active here should be switched to
963          * crtc->state->active once we have proper CRTC states wired up
964          * for atomic.
965          */
966         return crtc->active && crtc->base.primary->state->fb &&
967                 crtc->config->base.adjusted_mode.crtc_clock;
968 }
969
970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
971                                              enum pipe pipe)
972 {
973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
974
975         return crtc->config->cpu_transcoder;
976 }
977
978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
979 {
980         i915_reg_t reg = PIPEDSL(pipe);
981         u32 line1, line2;
982         u32 line_mask;
983
984         if (IS_GEN2(dev_priv))
985                 line_mask = DSL_LINEMASK_GEN2;
986         else
987                 line_mask = DSL_LINEMASK_GEN3;
988
989         line1 = I915_READ(reg) & line_mask;
990         msleep(5);
991         line2 = I915_READ(reg) & line_mask;
992
993         return line1 == line2;
994 }
995
996 /*
997  * intel_wait_for_pipe_off - wait for pipe to turn off
998  * @crtc: crtc whose pipe to wait for
999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997         unsigned int cpp = fb->format->cpp[plane];
1998
1999         switch (fb->modifier) {
2000         case DRM_FORMAT_MOD_LINEAR:
2001                 return cpp;
2002         case I915_FORMAT_MOD_X_TILED:
2003                 if (IS_GEN2(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Y_TILED:
2008                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009                         return 128;
2010                 else
2011                         return 512;
2012         case I915_FORMAT_MOD_Yf_TILED:
2013                 switch (cpp) {
2014                 case 1:
2015                         return 64;
2016                 case 2:
2017                 case 4:
2018                         return 128;
2019                 case 8:
2020                 case 16:
2021                         return 256;
2022                 default:
2023                         MISSING_CASE(cpp);
2024                         return cpp;
2025                 }
2026                 break;
2027         default:
2028                 MISSING_CASE(fb->modifier);
2029                 return cpp;
2030         }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2037                 return 1;
2038         else
2039                 return intel_tile_size(to_i915(fb->dev)) /
2040                         intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045                             unsigned int *tile_width,
2046                             unsigned int *tile_height)
2047 {
2048         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049         unsigned int cpp = fb->format->cpp[plane];
2050
2051         *tile_width = tile_width_bytes / cpp;
2052         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057                       int plane, unsigned int height)
2058 {
2059         unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061         return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066         unsigned int size = 0;
2067         int i;
2068
2069         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072         return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077                         const struct drm_framebuffer *fb,
2078                         unsigned int rotation)
2079 {
2080         view->type = I915_GGTT_VIEW_NORMAL;
2081         if (drm_rotation_90_or_270(rotation)) {
2082                 view->type = I915_GGTT_VIEW_ROTATED;
2083                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084         }
2085 }
2086
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089         if (INTEL_INFO(dev_priv)->gen >= 9)
2090                 return 256 * 1024;
2091         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2093                 return 128 * 1024;
2094         else if (INTEL_INFO(dev_priv)->gen >= 4)
2095                 return 4 * 1024;
2096         else
2097                 return 0;
2098 }
2099
2100 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2101                                          int plane)
2102 {
2103         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2104
2105         /* AUX_DIST needs only 4K alignment */
2106         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2107                 return 4096;
2108
2109         switch (fb->modifier) {
2110         case DRM_FORMAT_MOD_LINEAR:
2111                 return intel_linear_alignment(dev_priv);
2112         case I915_FORMAT_MOD_X_TILED:
2113                 if (INTEL_GEN(dev_priv) >= 9)
2114                         return 256 * 1024;
2115                 return 0;
2116         case I915_FORMAT_MOD_Y_TILED:
2117         case I915_FORMAT_MOD_Yf_TILED:
2118                 return 1 * 1024 * 1024;
2119         default:
2120                 MISSING_CASE(fb->modifier);
2121                 return 0;
2122         }
2123 }
2124
2125 struct i915_vma *
2126 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2127 {
2128         struct drm_device *dev = fb->dev;
2129         struct drm_i915_private *dev_priv = to_i915(dev);
2130         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2131         struct i915_ggtt_view view;
2132         struct i915_vma *vma;
2133         u32 alignment;
2134
2135         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137         alignment = intel_surf_alignment(fb, 0);
2138
2139         intel_fill_fb_ggtt_view(&view, fb, rotation);
2140
2141         /* Note that the w/a also requires 64 PTE of padding following the
2142          * bo. We currently fill all unused PTE with the shadow page and so
2143          * we should always have valid PTE following the scanout preventing
2144          * the VT-d warning.
2145          */
2146         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147                 alignment = 256 * 1024;
2148
2149         /*
2150          * Global gtt pte registers are special registers which actually forward
2151          * writes to a chunk of system memory. Which means that there is no risk
2152          * that the register values disappear as soon as we call
2153          * intel_runtime_pm_put(), so it is correct to wrap only the
2154          * pin/unpin/fence and not more.
2155          */
2156         intel_runtime_pm_get(dev_priv);
2157
2158         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2159         if (IS_ERR(vma))
2160                 goto err;
2161
2162         if (i915_vma_is_map_and_fenceable(vma)) {
2163                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164                  * fence, whereas 965+ only requires a fence if using
2165                  * framebuffer compression.  For simplicity, we always, when
2166                  * possible, install a fence as the cost is not that onerous.
2167                  *
2168                  * If we fail to fence the tiled scanout, then either the
2169                  * modeset will reject the change (which is highly unlikely as
2170                  * the affected systems, all but one, do not have unmappable
2171                  * space) or we will not be able to enable full powersaving
2172                  * techniques (also likely not to apply due to various limits
2173                  * FBC and the like impose on the size of the buffer, which
2174                  * presumably we violated anyway with this unmappable buffer).
2175                  * Anyway, it is presumably better to stumble onwards with
2176                  * something and try to run the system in a "less than optimal"
2177                  * mode that matches the user configuration.
2178                  */
2179                 if (i915_vma_get_fence(vma) == 0)
2180                         i915_vma_pin_fence(vma);
2181         }
2182
2183         i915_vma_get(vma);
2184 err:
2185         intel_runtime_pm_put(dev_priv);
2186         return vma;
2187 }
2188
2189 void intel_unpin_fb_vma(struct i915_vma *vma)
2190 {
2191         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2192
2193         i915_vma_unpin_fence(vma);
2194         i915_gem_object_unpin_from_display_plane(vma);
2195         i915_vma_put(vma);
2196 }
2197
2198 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199                           unsigned int rotation)
2200 {
2201         if (drm_rotation_90_or_270(rotation))
2202                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2203         else
2204                 return fb->pitches[plane];
2205 }
2206
2207 /*
2208  * Convert the x/y offsets into a linear offset.
2209  * Only valid with 0/180 degree rotation, which is fine since linear
2210  * offset is only used with linear buffers on pre-hsw and tiled buffers
2211  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2212  */
2213 u32 intel_fb_xy_to_linear(int x, int y,
2214                           const struct intel_plane_state *state,
2215                           int plane)
2216 {
2217         const struct drm_framebuffer *fb = state->base.fb;
2218         unsigned int cpp = fb->format->cpp[plane];
2219         unsigned int pitch = fb->pitches[plane];
2220
2221         return y * pitch + x * cpp;
2222 }
2223
2224 /*
2225  * Add the x/y offsets derived from fb->offsets[] to the user
2226  * specified plane src x/y offsets. The resulting x/y offsets
2227  * specify the start of scanout from the beginning of the gtt mapping.
2228  */
2229 void intel_add_fb_offsets(int *x, int *y,
2230                           const struct intel_plane_state *state,
2231                           int plane)
2232
2233 {
2234         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235         unsigned int rotation = state->base.rotation;
2236
2237         if (drm_rotation_90_or_270(rotation)) {
2238                 *x += intel_fb->rotated[plane].x;
2239                 *y += intel_fb->rotated[plane].y;
2240         } else {
2241                 *x += intel_fb->normal[plane].x;
2242                 *y += intel_fb->normal[plane].y;
2243         }
2244 }
2245
2246 /*
2247  * Input tile dimensions and pitch must already be
2248  * rotated to match x and y, and in pixel units.
2249  */
2250 static u32 _intel_adjust_tile_offset(int *x, int *y,
2251                                      unsigned int tile_width,
2252                                      unsigned int tile_height,
2253                                      unsigned int tile_size,
2254                                      unsigned int pitch_tiles,
2255                                      u32 old_offset,
2256                                      u32 new_offset)
2257 {
2258         unsigned int pitch_pixels = pitch_tiles * tile_width;
2259         unsigned int tiles;
2260
2261         WARN_ON(old_offset & (tile_size - 1));
2262         WARN_ON(new_offset & (tile_size - 1));
2263         WARN_ON(new_offset > old_offset);
2264
2265         tiles = (old_offset - new_offset) / tile_size;
2266
2267         *y += tiles / pitch_tiles * tile_height;
2268         *x += tiles % pitch_tiles * tile_width;
2269
2270         /* minimize x in case it got needlessly big */
2271         *y += *x / pitch_pixels * tile_height;
2272         *x %= pitch_pixels;
2273
2274         return new_offset;
2275 }
2276
2277 /*
2278  * Adjust the tile offset by moving the difference into
2279  * the x/y offsets.
2280  */
2281 static u32 intel_adjust_tile_offset(int *x, int *y,
2282                                     const struct intel_plane_state *state, int plane,
2283                                     u32 old_offset, u32 new_offset)
2284 {
2285         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286         const struct drm_framebuffer *fb = state->base.fb;
2287         unsigned int cpp = fb->format->cpp[plane];
2288         unsigned int rotation = state->base.rotation;
2289         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2290
2291         WARN_ON(new_offset > old_offset);
2292
2293         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2294                 unsigned int tile_size, tile_width, tile_height;
2295                 unsigned int pitch_tiles;
2296
2297                 tile_size = intel_tile_size(dev_priv);
2298                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2299
2300                 if (drm_rotation_90_or_270(rotation)) {
2301                         pitch_tiles = pitch / tile_height;
2302                         swap(tile_width, tile_height);
2303                 } else {
2304                         pitch_tiles = pitch / (tile_width * cpp);
2305                 }
2306
2307                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308                                           tile_size, pitch_tiles,
2309                                           old_offset, new_offset);
2310         } else {
2311                 old_offset += *y * pitch + *x * cpp;
2312
2313                 *y = (old_offset - new_offset) / pitch;
2314                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2315         }
2316
2317         return new_offset;
2318 }
2319
2320 /*
2321  * Computes the linear offset to the base tile and adjusts
2322  * x, y. bytes per pixel is assumed to be a power-of-two.
2323  *
2324  * In the 90/270 rotated case, x and y are assumed
2325  * to be already rotated to match the rotated GTT view, and
2326  * pitch is the tile_height aligned framebuffer height.
2327  *
2328  * This function is used when computing the derived information
2329  * under intel_framebuffer, so using any of that information
2330  * here is not allowed. Anything under drm_framebuffer can be
2331  * used. This is why the user has to pass in the pitch since it
2332  * is specified in the rotated orientation.
2333  */
2334 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2335                                       int *x, int *y,
2336                                       const struct drm_framebuffer *fb, int plane,
2337                                       unsigned int pitch,
2338                                       unsigned int rotation,
2339                                       u32 alignment)
2340 {
2341         uint64_t fb_modifier = fb->modifier;
2342         unsigned int cpp = fb->format->cpp[plane];
2343         u32 offset, offset_aligned;
2344
2345         if (alignment)
2346                 alignment--;
2347
2348         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2349                 unsigned int tile_size, tile_width, tile_height;
2350                 unsigned int tile_rows, tiles, pitch_tiles;
2351
2352                 tile_size = intel_tile_size(dev_priv);
2353                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2354
2355                 if (drm_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                           tile_size, pitch_tiles,
2373                                           offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386                               const struct intel_plane_state *state,
2387                               int plane)
2388 {
2389         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390         const struct drm_framebuffer *fb = state->base.fb;
2391         unsigned int rotation = state->base.rotation;
2392         int pitch = intel_fb_pitch(fb, plane, rotation);
2393         u32 alignment = intel_surf_alignment(fb, plane);
2394
2395         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396                                           rotation, alignment);
2397 }
2398
2399 /* Convert the fb->offset[] linear offset into x/y offsets */
2400 static void intel_fb_offset_to_xy(int *x, int *y,
2401                                   const struct drm_framebuffer *fb, int plane)
2402 {
2403         unsigned int cpp = fb->format->cpp[plane];
2404         unsigned int pitch = fb->pitches[plane];
2405         u32 linear_offset = fb->offsets[plane];
2406
2407         *y = linear_offset / pitch;
2408         *x = linear_offset % pitch / cpp;
2409 }
2410
2411 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2412 {
2413         switch (fb_modifier) {
2414         case I915_FORMAT_MOD_X_TILED:
2415                 return I915_TILING_X;
2416         case I915_FORMAT_MOD_Y_TILED:
2417                 return I915_TILING_Y;
2418         default:
2419                 return I915_TILING_NONE;
2420         }
2421 }
2422
2423 static int
2424 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425                    struct drm_framebuffer *fb)
2426 {
2427         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429         u32 gtt_offset_rotated = 0;
2430         unsigned int max_size = 0;
2431         int i, num_planes = fb->format->num_planes;
2432         unsigned int tile_size = intel_tile_size(dev_priv);
2433
2434         for (i = 0; i < num_planes; i++) {
2435                 unsigned int width, height;
2436                 unsigned int cpp, size;
2437                 u32 offset;
2438                 int x, y;
2439
2440                 cpp = fb->format->cpp[i];
2441                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2443
2444                 intel_fb_offset_to_xy(&x, &y, fb, i);
2445
2446                 /*
2447                  * The fence (if used) is aligned to the start of the object
2448                  * so having the framebuffer wrap around across the edge of the
2449                  * fenced region doesn't really work. We have no API to configure
2450                  * the fence start offset within the object (nor could we probably
2451                  * on gen2/3). So it's just easier if we just require that the
2452                  * fb layout agrees with the fence layout. We already check that the
2453                  * fb stride matches the fence stride elsewhere.
2454                  */
2455                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456                     (x + width) * cpp > fb->pitches[i]) {
2457                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2458                                       i, fb->offsets[i]);
2459                         return -EINVAL;
2460                 }
2461
2462                 /*
2463                  * First pixel of the framebuffer from
2464                  * the start of the normal gtt mapping.
2465                  */
2466                 intel_fb->normal[i].x = x;
2467                 intel_fb->normal[i].y = y;
2468
2469                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2470                                                     fb, i, fb->pitches[i],
2471                                                     DRM_ROTATE_0, tile_size);
2472                 offset /= tile_size;
2473
2474                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2475                         unsigned int tile_width, tile_height;
2476                         unsigned int pitch_tiles;
2477                         struct drm_rect r;
2478
2479                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2480
2481                         rot_info->plane[i].offset = offset;
2482                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2485
2486                         intel_fb->rotated[i].pitch =
2487                                 rot_info->plane[i].height * tile_height;
2488
2489                         /* how many tiles does this plane need */
2490                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2491                         /*
2492                          * If the plane isn't horizontally tile aligned,
2493                          * we need one more tile.
2494                          */
2495                         if (x != 0)
2496                                 size++;
2497
2498                         /* rotate the x/y offsets to match the GTT view */
2499                         r.x1 = x;
2500                         r.y1 = y;
2501                         r.x2 = x + width;
2502                         r.y2 = y + height;
2503                         drm_rect_rotate(&r,
2504                                         rot_info->plane[i].width * tile_width,
2505                                         rot_info->plane[i].height * tile_height,
2506                                         DRM_ROTATE_270);
2507                         x = r.x1;
2508                         y = r.y1;
2509
2510                         /* rotate the tile dimensions to match the GTT view */
2511                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512                         swap(tile_width, tile_height);
2513
2514                         /*
2515                          * We only keep the x/y offsets, so push all of the
2516                          * gtt offset into the x/y offsets.
2517                          */
2518                         _intel_adjust_tile_offset(&x, &y,
2519                                                   tile_width, tile_height,
2520                                                   tile_size, pitch_tiles,
2521                                                   gtt_offset_rotated * tile_size, 0);
2522
2523                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2524
2525                         /*
2526                          * First pixel of the framebuffer from
2527                          * the start of the rotated gtt mapping.
2528                          */
2529                         intel_fb->rotated[i].x = x;
2530                         intel_fb->rotated[i].y = y;
2531                 } else {
2532                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533                                             x * cpp, tile_size);
2534                 }
2535
2536                 /* how many tiles in total needed in the bo */
2537                 max_size = max(max_size, offset + size);
2538         }
2539
2540         if (max_size * tile_size > intel_fb->obj->base.size) {
2541                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542                               max_size * tile_size, intel_fb->obj->base.size);
2543                 return -EINVAL;
2544         }
2545
2546         return 0;
2547 }
2548
2549 static int i9xx_format_to_fourcc(int format)
2550 {
2551         switch (format) {
2552         case DISPPLANE_8BPP:
2553                 return DRM_FORMAT_C8;
2554         case DISPPLANE_BGRX555:
2555                 return DRM_FORMAT_XRGB1555;
2556         case DISPPLANE_BGRX565:
2557                 return DRM_FORMAT_RGB565;
2558         default:
2559         case DISPPLANE_BGRX888:
2560                 return DRM_FORMAT_XRGB8888;
2561         case DISPPLANE_RGBX888:
2562                 return DRM_FORMAT_XBGR8888;
2563         case DISPPLANE_BGRX101010:
2564                 return DRM_FORMAT_XRGB2101010;
2565         case DISPPLANE_RGBX101010:
2566                 return DRM_FORMAT_XBGR2101010;
2567         }
2568 }
2569
2570 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2571 {
2572         switch (format) {
2573         case PLANE_CTL_FORMAT_RGB_565:
2574                 return DRM_FORMAT_RGB565;
2575         default:
2576         case PLANE_CTL_FORMAT_XRGB_8888:
2577                 if (rgb_order) {
2578                         if (alpha)
2579                                 return DRM_FORMAT_ABGR8888;
2580                         else
2581                                 return DRM_FORMAT_XBGR8888;
2582                 } else {
2583                         if (alpha)
2584                                 return DRM_FORMAT_ARGB8888;
2585                         else
2586                                 return DRM_FORMAT_XRGB8888;
2587                 }
2588         case PLANE_CTL_FORMAT_XRGB_2101010:
2589                 if (rgb_order)
2590                         return DRM_FORMAT_XBGR2101010;
2591                 else
2592                         return DRM_FORMAT_XRGB2101010;
2593         }
2594 }
2595
2596 static bool
2597 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598                               struct intel_initial_plane_config *plane_config)
2599 {
2600         struct drm_device *dev = crtc->base.dev;
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2603         struct drm_i915_gem_object *obj = NULL;
2604         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605         struct drm_framebuffer *fb = &plane_config->fb->base;
2606         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608                                     PAGE_SIZE);
2609
2610         size_aligned -= base_aligned;
2611
2612         if (plane_config->size == 0)
2613                 return false;
2614
2615         /* If the FB is too big, just don't use it since fbdev is not very
2616          * important and we should probably use that space with FBC or other
2617          * features. */
2618         if (size_aligned * 2 > ggtt->stolen_usable_size)
2619                 return false;
2620
2621         mutex_lock(&dev->struct_mutex);
2622         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2623                                                              base_aligned,
2624                                                              base_aligned,
2625                                                              size_aligned);
2626         mutex_unlock(&dev->struct_mutex);
2627         if (!obj)
2628                 return false;
2629
2630         if (plane_config->tiling == I915_TILING_X)
2631                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2632
2633         mode_cmd.pixel_format = fb->format->format;
2634         mode_cmd.width = fb->width;
2635         mode_cmd.height = fb->height;
2636         mode_cmd.pitches[0] = fb->pitches[0];
2637         mode_cmd.modifier[0] = fb->modifier;
2638         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2639
2640         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2641                 DRM_DEBUG_KMS("intel fb init failed\n");
2642                 goto out_unref_obj;
2643         }
2644
2645
2646         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2647         return true;
2648
2649 out_unref_obj:
2650         i915_gem_object_put(obj);
2651         return false;
2652 }
2653
2654 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2655 static void
2656 update_state_fb(struct drm_plane *plane)
2657 {
2658         if (plane->fb == plane->state->fb)
2659                 return;
2660
2661         if (plane->state->fb)
2662                 drm_framebuffer_unreference(plane->state->fb);
2663         plane->state->fb = plane->fb;
2664         if (plane->state->fb)
2665                 drm_framebuffer_reference(plane->state->fb);
2666 }
2667
2668 static void
2669 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670                         struct intel_plane_state *plane_state,
2671                         bool visible)
2672 {
2673         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2674
2675         plane_state->base.visible = visible;
2676
2677         /* FIXME pre-g4x don't work like this */
2678         if (visible) {
2679                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680                 crtc_state->active_planes |= BIT(plane->id);
2681         } else {
2682                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683                 crtc_state->active_planes &= ~BIT(plane->id);
2684         }
2685
2686         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687                       crtc_state->base.crtc->name,
2688                       crtc_state->active_planes);
2689 }
2690
2691 static void
2692 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693                              struct intel_initial_plane_config *plane_config)
2694 {
2695         struct drm_device *dev = intel_crtc->base.dev;
2696         struct drm_i915_private *dev_priv = to_i915(dev);
2697         struct drm_crtc *c;
2698         struct drm_i915_gem_object *obj;
2699         struct drm_plane *primary = intel_crtc->base.primary;
2700         struct drm_plane_state *plane_state = primary->state;
2701         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702         struct intel_plane *intel_plane = to_intel_plane(primary);
2703         struct intel_plane_state *intel_state =
2704                 to_intel_plane_state(plane_state);
2705         struct drm_framebuffer *fb;
2706
2707         if (!plane_config->fb)
2708                 return;
2709
2710         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2711                 fb = &plane_config->fb->base;
2712                 goto valid_fb;
2713         }
2714
2715         kfree(plane_config->fb);
2716
2717         /*
2718          * Failed to alloc the obj, check to see if we should share
2719          * an fb with another CRTC instead
2720          */
2721         for_each_crtc(dev, c) {
2722                 struct intel_plane_state *state;
2723
2724                 if (c == &intel_crtc->base)
2725                         continue;
2726
2727                 if (!to_intel_crtc(c)->active)
2728                         continue;
2729
2730                 state = to_intel_plane_state(c->primary->state);
2731                 if (!state->vma)
2732                         continue;
2733
2734                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735                         fb = c->primary->fb;
2736                         drm_framebuffer_reference(fb);
2737                         goto valid_fb;
2738                 }
2739         }
2740
2741         /*
2742          * We've failed to reconstruct the BIOS FB.  Current display state
2743          * indicates that the primary plane is visible, but has a NULL FB,
2744          * which will lead to problems later if we don't fix it up.  The
2745          * simplest solution is to just disable the primary plane now and
2746          * pretend the BIOS never had it enabled.
2747          */
2748         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749                                 to_intel_plane_state(plane_state),
2750                                 false);
2751         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2752         trace_intel_disable_plane(primary, intel_crtc);
2753         intel_plane->disable_plane(primary, &intel_crtc->base);
2754
2755         return;
2756
2757 valid_fb:
2758         mutex_lock(&dev->struct_mutex);
2759         intel_state->vma =
2760                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761         mutex_unlock(&dev->struct_mutex);
2762         if (IS_ERR(intel_state->vma)) {
2763                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2765
2766                 intel_state->vma = NULL;
2767                 drm_framebuffer_unreference(fb);
2768                 return;
2769         }
2770
2771         plane_state->src_x = 0;
2772         plane_state->src_y = 0;
2773         plane_state->src_w = fb->width << 16;
2774         plane_state->src_h = fb->height << 16;
2775
2776         plane_state->crtc_x = 0;
2777         plane_state->crtc_y = 0;
2778         plane_state->crtc_w = fb->width;
2779         plane_state->crtc_h = fb->height;
2780
2781         intel_state->base.src = drm_plane_state_src(plane_state);
2782         intel_state->base.dst = drm_plane_state_dest(plane_state);
2783
2784         obj = intel_fb_obj(fb);
2785         if (i915_gem_object_is_tiled(obj))
2786                 dev_priv->preserve_bios_swizzle = true;
2787
2788         drm_framebuffer_reference(fb);
2789         primary->fb = primary->state->fb = fb;
2790         primary->crtc = primary->state->crtc = &intel_crtc->base;
2791
2792         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793                                 to_intel_plane_state(plane_state),
2794                                 true);
2795
2796         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797                   &obj->frontbuffer_bits);
2798 }
2799
2800 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801                                unsigned int rotation)
2802 {
2803         int cpp = fb->format->cpp[plane];
2804
2805         switch (fb->modifier) {
2806         case DRM_FORMAT_MOD_LINEAR:
2807         case I915_FORMAT_MOD_X_TILED:
2808                 switch (cpp) {
2809                 case 8:
2810                         return 4096;
2811                 case 4:
2812                 case 2:
2813                 case 1:
2814                         return 8192;
2815                 default:
2816                         MISSING_CASE(cpp);
2817                         break;
2818                 }
2819                 break;
2820         case I915_FORMAT_MOD_Y_TILED:
2821         case I915_FORMAT_MOD_Yf_TILED:
2822                 switch (cpp) {
2823                 case 8:
2824                         return 2048;
2825                 case 4:
2826                         return 4096;
2827                 case 2:
2828                 case 1:
2829                         return 8192;
2830                 default:
2831                         MISSING_CASE(cpp);
2832                         break;
2833                 }
2834                 break;
2835         default:
2836                 MISSING_CASE(fb->modifier);
2837         }
2838
2839         return 2048;
2840 }
2841
2842 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2843 {
2844         const struct drm_framebuffer *fb = plane_state->base.fb;
2845         unsigned int rotation = plane_state->base.rotation;
2846         int x = plane_state->base.src.x1 >> 16;
2847         int y = plane_state->base.src.y1 >> 16;
2848         int w = drm_rect_width(&plane_state->base.src) >> 16;
2849         int h = drm_rect_height(&plane_state->base.src) >> 16;
2850         int max_width = skl_max_plane_width(fb, 0, rotation);
2851         int max_height = 4096;
2852         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2853
2854         if (w > max_width || h > max_height) {
2855                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856                               w, h, max_width, max_height);
2857                 return -EINVAL;
2858         }
2859
2860         intel_add_fb_offsets(&x, &y, plane_state, 0);
2861         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2862         alignment = intel_surf_alignment(fb, 0);
2863
2864         /*
2865          * AUX surface offset is specified as the distance from the
2866          * main surface offset, and it must be non-negative. Make
2867          * sure that is what we will get.
2868          */
2869         if (offset > aux_offset)
2870                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871                                                   offset, aux_offset & ~(alignment - 1));
2872
2873         /*
2874          * When using an X-tiled surface, the plane blows up
2875          * if the x offset + width exceed the stride.
2876          *
2877          * TODO: linear and Y-tiled seem fine, Yf untested,
2878          */
2879         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2880                 int cpp = fb->format->cpp[0];
2881
2882                 while ((x + w) * cpp > fb->pitches[0]) {
2883                         if (offset == 0) {
2884                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2885                                 return -EINVAL;
2886                         }
2887
2888                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889                                                           offset, offset - alignment);
2890                 }
2891         }
2892
2893         plane_state->main.offset = offset;
2894         plane_state->main.x = x;
2895         plane_state->main.y = y;
2896
2897         return 0;
2898 }
2899
2900 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2901 {
2902         const struct drm_framebuffer *fb = plane_state->base.fb;
2903         unsigned int rotation = plane_state->base.rotation;
2904         int max_width = skl_max_plane_width(fb, 1, rotation);
2905         int max_height = 4096;
2906         int x = plane_state->base.src.x1 >> 17;
2907         int y = plane_state->base.src.y1 >> 17;
2908         int w = drm_rect_width(&plane_state->base.src) >> 17;
2909         int h = drm_rect_height(&plane_state->base.src) >> 17;
2910         u32 offset;
2911
2912         intel_add_fb_offsets(&x, &y, plane_state, 1);
2913         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2914
2915         /* FIXME not quite sure how/if these apply to the chroma plane */
2916         if (w > max_width || h > max_height) {
2917                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918                               w, h, max_width, max_height);
2919                 return -EINVAL;
2920         }
2921
2922         plane_state->aux.offset = offset;
2923         plane_state->aux.x = x;
2924         plane_state->aux.y = y;
2925
2926         return 0;
2927 }
2928
2929 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2930 {
2931         const struct drm_framebuffer *fb = plane_state->base.fb;
2932         unsigned int rotation = plane_state->base.rotation;
2933         int ret;
2934
2935         if (!plane_state->base.visible)
2936                 return 0;
2937
2938         /* Rotate src coordinates to match rotated GTT view */
2939         if (drm_rotation_90_or_270(rotation))
2940                 drm_rect_rotate(&plane_state->base.src,
2941                                 fb->width << 16, fb->height << 16,
2942                                 DRM_ROTATE_270);
2943
2944         /*
2945          * Handle the AUX surface first since
2946          * the main surface setup depends on it.
2947          */
2948         if (fb->format->format == DRM_FORMAT_NV12) {
2949                 ret = skl_check_nv12_aux_surface(plane_state);
2950                 if (ret)
2951                         return ret;
2952         } else {
2953                 plane_state->aux.offset = ~0xfff;
2954                 plane_state->aux.x = 0;
2955                 plane_state->aux.y = 0;
2956         }
2957
2958         ret = skl_check_main_surface(plane_state);
2959         if (ret)
2960                 return ret;
2961
2962         return 0;
2963 }
2964
2965 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2966                           const struct intel_plane_state *plane_state)
2967 {
2968         struct drm_i915_private *dev_priv =
2969                 to_i915(plane_state->base.plane->dev);
2970         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2971         const struct drm_framebuffer *fb = plane_state->base.fb;
2972         unsigned int rotation = plane_state->base.rotation;
2973         u32 dspcntr;
2974
2975         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2976
2977         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2978             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2979                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2980
2981         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2982                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2983
2984         if (INTEL_GEN(dev_priv) < 4) {
2985                 if (crtc->pipe == PIPE_B)
2986                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2987         }
2988
2989         switch (fb->format->format) {
2990         case DRM_FORMAT_C8:
2991                 dspcntr |= DISPPLANE_8BPP;
2992                 break;
2993         case DRM_FORMAT_XRGB1555:
2994                 dspcntr |= DISPPLANE_BGRX555;
2995                 break;
2996         case DRM_FORMAT_RGB565:
2997                 dspcntr |= DISPPLANE_BGRX565;
2998                 break;
2999         case DRM_FORMAT_XRGB8888:
3000                 dspcntr |= DISPPLANE_BGRX888;
3001                 break;
3002         case DRM_FORMAT_XBGR8888:
3003                 dspcntr |= DISPPLANE_RGBX888;
3004                 break;
3005         case DRM_FORMAT_XRGB2101010:
3006                 dspcntr |= DISPPLANE_BGRX101010;
3007                 break;
3008         case DRM_FORMAT_XBGR2101010:
3009                 dspcntr |= DISPPLANE_RGBX101010;
3010                 break;
3011         default:
3012                 MISSING_CASE(fb->format->format);
3013                 return 0;
3014         }
3015
3016         if (INTEL_GEN(dev_priv) >= 4 &&
3017             fb->modifier == I915_FORMAT_MOD_X_TILED)
3018                 dspcntr |= DISPPLANE_TILED;
3019
3020         if (rotation & DRM_ROTATE_180)
3021                 dspcntr |= DISPPLANE_ROTATE_180;
3022
3023         if (rotation & DRM_REFLECT_X)
3024                 dspcntr |= DISPPLANE_MIRROR;
3025
3026         return dspcntr;
3027 }
3028
3029 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3030 {
3031         struct drm_i915_private *dev_priv =
3032                 to_i915(plane_state->base.plane->dev);
3033         int src_x = plane_state->base.src.x1 >> 16;
3034         int src_y = plane_state->base.src.y1 >> 16;
3035         u32 offset;
3036
3037         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3038
3039         if (INTEL_GEN(dev_priv) >= 4)
3040                 offset = intel_compute_tile_offset(&src_x, &src_y,
3041                                                    plane_state, 0);
3042         else
3043                 offset = 0;
3044
3045         /* HSW/BDW do this automagically in hardware */
3046         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3047                 unsigned int rotation = plane_state->base.rotation;
3048                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3049                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3050
3051                 if (rotation & DRM_ROTATE_180) {
3052                         src_x += src_w - 1;
3053                         src_y += src_h - 1;
3054                 } else if (rotation & DRM_REFLECT_X) {
3055                         src_x += src_w - 1;
3056                 }
3057         }
3058
3059         plane_state->main.offset = offset;
3060         plane_state->main.x = src_x;
3061         plane_state->main.y = src_y;
3062
3063         return 0;
3064 }
3065
3066 static void i9xx_update_primary_plane(struct drm_plane *primary,
3067                                       const struct intel_crtc_state *crtc_state,
3068                                       const struct intel_plane_state *plane_state)
3069 {
3070         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3072         struct drm_framebuffer *fb = plane_state->base.fb;
3073         int plane = intel_crtc->plane;
3074         u32 linear_offset;
3075         u32 dspcntr = plane_state->ctl;
3076         i915_reg_t reg = DSPCNTR(plane);
3077         int x = plane_state->main.x;
3078         int y = plane_state->main.y;
3079         unsigned long irqflags;
3080
3081         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3082
3083         if (INTEL_GEN(dev_priv) >= 4)
3084                 intel_crtc->dspaddr_offset = plane_state->main.offset;
3085         else
3086                 intel_crtc->dspaddr_offset = linear_offset;
3087
3088         intel_crtc->adjusted_x = x;
3089         intel_crtc->adjusted_y = y;
3090
3091         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3092
3093         if (INTEL_GEN(dev_priv) < 4) {
3094                 /* pipesrc and dspsize control the size that is scaled from,
3095                  * which should always be the user's requested size.
3096                  */
3097                 I915_WRITE_FW(DSPSIZE(plane),
3098                               ((crtc_state->pipe_src_h - 1) << 16) |
3099                               (crtc_state->pipe_src_w - 1));
3100                 I915_WRITE_FW(DSPPOS(plane), 0);
3101         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3102                 I915_WRITE_FW(PRIMSIZE(plane),
3103                               ((crtc_state->pipe_src_h - 1) << 16) |
3104                               (crtc_state->pipe_src_w - 1));
3105                 I915_WRITE_FW(PRIMPOS(plane), 0);
3106                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3107         }
3108
3109         I915_WRITE_FW(reg, dspcntr);
3110
3111         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3112         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3113                 I915_WRITE_FW(DSPSURF(plane),
3114                               intel_plane_ggtt_offset(plane_state) +
3115                               intel_crtc->dspaddr_offset);
3116                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3117         } else if (INTEL_GEN(dev_priv) >= 4) {
3118                 I915_WRITE_FW(DSPSURF(plane),
3119                               intel_plane_ggtt_offset(plane_state) +
3120                               intel_crtc->dspaddr_offset);
3121                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3122                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3123         } else {
3124                 I915_WRITE_FW(DSPADDR(plane),
3125                               intel_plane_ggtt_offset(plane_state) +
3126                               intel_crtc->dspaddr_offset);
3127         }
3128         POSTING_READ_FW(reg);
3129
3130         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3131 }
3132
3133 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3134                                        struct drm_crtc *crtc)
3135 {
3136         struct drm_device *dev = crtc->dev;
3137         struct drm_i915_private *dev_priv = to_i915(dev);
3138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139         int plane = intel_crtc->plane;
3140         unsigned long irqflags;
3141
3142         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3143
3144         I915_WRITE_FW(DSPCNTR(plane), 0);
3145         if (INTEL_INFO(dev_priv)->gen >= 4)
3146                 I915_WRITE_FW(DSPSURF(plane), 0);
3147         else
3148                 I915_WRITE_FW(DSPADDR(plane), 0);
3149         POSTING_READ_FW(DSPCNTR(plane));
3150
3151         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3152 }
3153
3154 static u32
3155 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3156 {
3157         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3158                 return 64;
3159         else
3160                 return intel_tile_width_bytes(fb, plane);
3161 }
3162
3163 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3164 {
3165         struct drm_device *dev = intel_crtc->base.dev;
3166         struct drm_i915_private *dev_priv = to_i915(dev);
3167
3168         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3169         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3170         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3171 }
3172
3173 /*
3174  * This function detaches (aka. unbinds) unused scalers in hardware
3175  */
3176 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3177 {
3178         struct intel_crtc_scaler_state *scaler_state;
3179         int i;
3180
3181         scaler_state = &intel_crtc->config->scaler_state;
3182
3183         /* loop through and disable scalers that aren't in use */
3184         for (i = 0; i < intel_crtc->num_scalers; i++) {
3185                 if (!scaler_state->scalers[i].in_use)
3186                         skl_detach_scaler(intel_crtc, i);
3187         }
3188 }
3189
3190 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3191                      unsigned int rotation)
3192 {
3193         u32 stride;
3194
3195         if (plane >= fb->format->num_planes)
3196                 return 0;
3197
3198         stride = intel_fb_pitch(fb, plane, rotation);
3199
3200         /*
3201          * The stride is either expressed as a multiple of 64 bytes chunks for
3202          * linear buffers or in number of tiles for tiled buffers.
3203          */
3204         if (drm_rotation_90_or_270(rotation))
3205                 stride /= intel_tile_height(fb, plane);
3206         else
3207                 stride /= intel_fb_stride_alignment(fb, plane);
3208
3209         return stride;
3210 }
3211
3212 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3213 {
3214         switch (pixel_format) {
3215         case DRM_FORMAT_C8:
3216                 return PLANE_CTL_FORMAT_INDEXED;
3217         case DRM_FORMAT_RGB565:
3218                 return PLANE_CTL_FORMAT_RGB_565;
3219         case DRM_FORMAT_XBGR8888:
3220                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3221         case DRM_FORMAT_XRGB8888:
3222                 return PLANE_CTL_FORMAT_XRGB_8888;
3223         /*
3224          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3225          * to be already pre-multiplied. We need to add a knob (or a different
3226          * DRM_FORMAT) for user-space to configure that.
3227          */
3228         case DRM_FORMAT_ABGR8888:
3229                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3230                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3231         case DRM_FORMAT_ARGB8888:
3232                 return PLANE_CTL_FORMAT_XRGB_8888 |
3233                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3234         case DRM_FORMAT_XRGB2101010:
3235                 return PLANE_CTL_FORMAT_XRGB_2101010;
3236         case DRM_FORMAT_XBGR2101010:
3237                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3238         case DRM_FORMAT_YUYV:
3239                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3240         case DRM_FORMAT_YVYU:
3241                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3242         case DRM_FORMAT_UYVY:
3243                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3244         case DRM_FORMAT_VYUY:
3245                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3246         default:
3247                 MISSING_CASE(pixel_format);
3248         }
3249
3250         return 0;
3251 }
3252
3253 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3254 {
3255         switch (fb_modifier) {
3256         case DRM_FORMAT_MOD_LINEAR:
3257                 break;
3258         case I915_FORMAT_MOD_X_TILED:
3259                 return PLANE_CTL_TILED_X;
3260         case I915_FORMAT_MOD_Y_TILED:
3261                 return PLANE_CTL_TILED_Y;
3262         case I915_FORMAT_MOD_Yf_TILED:
3263                 return PLANE_CTL_TILED_YF;
3264         default:
3265                 MISSING_CASE(fb_modifier);
3266         }
3267
3268         return 0;
3269 }
3270
3271 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3272 {
3273         switch (rotation) {
3274         case DRM_ROTATE_0:
3275                 break;
3276         /*
3277          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3278          * while i915 HW rotation is clockwise, thats why this swapping.
3279          */
3280         case DRM_ROTATE_90:
3281                 return PLANE_CTL_ROTATE_270;
3282         case DRM_ROTATE_180:
3283                 return PLANE_CTL_ROTATE_180;
3284         case DRM_ROTATE_270:
3285                 return PLANE_CTL_ROTATE_90;
3286         default:
3287                 MISSING_CASE(rotation);
3288         }
3289
3290         return 0;
3291 }
3292
3293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3294                   const struct intel_plane_state *plane_state)
3295 {
3296         struct drm_i915_private *dev_priv =
3297                 to_i915(plane_state->base.plane->dev);
3298         const struct drm_framebuffer *fb = plane_state->base.fb;
3299         unsigned int rotation = plane_state->base.rotation;
3300         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3301         u32 plane_ctl;
3302
3303         plane_ctl = PLANE_CTL_ENABLE;
3304
3305         if (!IS_GEMINILAKE(dev_priv)) {
3306                 plane_ctl |=
3307                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3308                         PLANE_CTL_PIPE_CSC_ENABLE |
3309                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3310         }
3311
3312         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3313         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3314         plane_ctl |= skl_plane_ctl_rotation(rotation);
3315
3316         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3317                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3318         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3319                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3320
3321         return plane_ctl;
3322 }
3323
3324 static void skylake_update_primary_plane(struct drm_plane *plane,
3325                                          const struct intel_crtc_state *crtc_state,
3326                                          const struct intel_plane_state *plane_state)
3327 {
3328         struct drm_device *dev = plane->dev;
3329         struct drm_i915_private *dev_priv = to_i915(dev);
3330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3331         struct drm_framebuffer *fb = plane_state->base.fb;
3332         enum plane_id plane_id = to_intel_plane(plane)->id;
3333         enum pipe pipe = to_intel_plane(plane)->pipe;
3334         u32 plane_ctl = plane_state->ctl;
3335         unsigned int rotation = plane_state->base.rotation;
3336         u32 stride = skl_plane_stride(fb, 0, rotation);
3337         u32 surf_addr = plane_state->main.offset;
3338         int scaler_id = plane_state->scaler_id;
3339         int src_x = plane_state->main.x;
3340         int src_y = plane_state->main.y;
3341         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3342         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3343         int dst_x = plane_state->base.dst.x1;
3344         int dst_y = plane_state->base.dst.y1;
3345         int dst_w = drm_rect_width(&plane_state->base.dst);
3346         int dst_h = drm_rect_height(&plane_state->base.dst);
3347         unsigned long irqflags;
3348
3349         /* Sizes are 0 based */
3350         src_w--;
3351         src_h--;
3352         dst_w--;
3353         dst_h--;
3354
3355         intel_crtc->dspaddr_offset = surf_addr;
3356
3357         intel_crtc->adjusted_x = src_x;
3358         intel_crtc->adjusted_y = src_y;
3359
3360         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3361
3362         if (IS_GEMINILAKE(dev_priv)) {
3363                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3364                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3365                               PLANE_COLOR_PIPE_CSC_ENABLE |
3366                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3367         }
3368
3369         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3370         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3371         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3372         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3373
3374         if (scaler_id >= 0) {
3375                 uint32_t ps_ctrl = 0;
3376
3377                 WARN_ON(!dst_w || !dst_h);
3378                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3379                         crtc_state->scaler_state.scalers[scaler_id].mode;
3380                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3381                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3382                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3383                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3384                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3385         } else {
3386                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3387         }
3388
3389         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3390                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3391
3392         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3393
3394         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3395 }
3396
3397 static void skylake_disable_primary_plane(struct drm_plane *primary,
3398                                           struct drm_crtc *crtc)
3399 {
3400         struct drm_device *dev = crtc->dev;
3401         struct drm_i915_private *dev_priv = to_i915(dev);
3402         enum plane_id plane_id = to_intel_plane(primary)->id;
3403         enum pipe pipe = to_intel_plane(primary)->pipe;
3404         unsigned long irqflags;
3405
3406         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3407
3408         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3409         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3410         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3411
3412         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3413 }
3414
3415 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3416 {
3417         struct intel_crtc *crtc;
3418
3419         for_each_intel_crtc(&dev_priv->drm, crtc)
3420                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3421 }
3422
3423 static void intel_update_primary_planes(struct drm_device *dev)
3424 {
3425         struct drm_crtc *crtc;
3426
3427         for_each_crtc(dev, crtc) {
3428                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3429                 struct intel_plane_state *plane_state =
3430                         to_intel_plane_state(plane->base.state);
3431
3432                 if (plane_state->base.visible) {
3433                         trace_intel_update_plane(&plane->base,
3434                                                  to_intel_crtc(crtc));
3435
3436                         plane->update_plane(&plane->base,
3437                                             to_intel_crtc_state(crtc->state),
3438                                             plane_state);
3439                 }
3440         }
3441 }
3442
3443 static int
3444 __intel_display_resume(struct drm_device *dev,
3445                        struct drm_atomic_state *state,
3446                        struct drm_modeset_acquire_ctx *ctx)
3447 {
3448         struct drm_crtc_state *crtc_state;
3449         struct drm_crtc *crtc;
3450         int i, ret;
3451
3452         intel_modeset_setup_hw_state(dev);
3453         i915_redisable_vga(to_i915(dev));
3454
3455         if (!state)
3456                 return 0;
3457
3458         /*
3459          * We've duplicated the state, pointers to the old state are invalid.
3460          *
3461          * Don't attempt to use the old state until we commit the duplicated state.
3462          */
3463         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3464                 /*
3465                  * Force recalculation even if we restore
3466                  * current state. With fast modeset this may not result
3467                  * in a modeset when the state is compatible.
3468                  */
3469                 crtc_state->mode_changed = true;
3470         }
3471
3472         /* ignore any reset values/BIOS leftovers in the WM registers */
3473         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3474                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3475
3476         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3477
3478         WARN_ON(ret == -EDEADLK);
3479         return ret;
3480 }
3481
3482 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3483 {
3484         return intel_has_gpu_reset(dev_priv) &&
3485                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3486 }
3487
3488 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3489 {
3490         struct drm_device *dev = &dev_priv->drm;
3491         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3492         struct drm_atomic_state *state;
3493         int ret;
3494
3495         /*
3496          * Need mode_config.mutex so that we don't
3497          * trample ongoing ->detect() and whatnot.
3498          */
3499         mutex_lock(&dev->mode_config.mutex);
3500         drm_modeset_acquire_init(ctx, 0);
3501         while (1) {
3502                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3503                 if (ret != -EDEADLK)
3504                         break;
3505
3506                 drm_modeset_backoff(ctx);
3507         }
3508
3509         /* reset doesn't touch the display, but flips might get nuked anyway, */
3510         if (!i915.force_reset_modeset_test &&
3511             !gpu_reset_clobbers_display(dev_priv))
3512                 return;
3513
3514         /*
3515          * Disabling the crtcs gracefully seems nicer. Also the
3516          * g33 docs say we should at least disable all the planes.
3517          */
3518         state = drm_atomic_helper_duplicate_state(dev, ctx);
3519         if (IS_ERR(state)) {
3520                 ret = PTR_ERR(state);
3521                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3522                 return;
3523         }
3524
3525         ret = drm_atomic_helper_disable_all(dev, ctx);
3526         if (ret) {
3527                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3528                 drm_atomic_state_put(state);
3529                 return;
3530         }
3531
3532         dev_priv->modeset_restore_state = state;
3533         state->acquire_ctx = ctx;
3534 }
3535
3536 void intel_finish_reset(struct drm_i915_private *dev_priv)
3537 {
3538         struct drm_device *dev = &dev_priv->drm;
3539         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3541         int ret;
3542
3543         /*
3544          * Flips in the rings will be nuked by the reset,
3545          * so complete all pending flips so that user space
3546          * will get its events and not get stuck.
3547          */
3548         intel_complete_page_flips(dev_priv);
3549
3550         dev_priv->modeset_restore_state = NULL;
3551
3552         /* reset doesn't touch the display */
3553         if (!gpu_reset_clobbers_display(dev_priv)) {
3554                 if (!state) {
3555                         /*
3556                          * Flips in the rings have been nuked by the reset,
3557                          * so update the base address of all primary
3558                          * planes to the the last fb to make sure we're
3559                          * showing the correct fb after a reset.
3560                          *
3561                          * FIXME: Atomic will make this obsolete since we won't schedule
3562                          * CS-based flips (which might get lost in gpu resets) any more.
3563                          */
3564                         intel_update_primary_planes(dev);
3565                 } else {
3566                         ret = __intel_display_resume(dev, state, ctx);
3567                         if (ret)
3568                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3569                 }
3570         } else {
3571                 /*
3572                  * The display has been reset as well,
3573                  * so need a full re-initialization.
3574                  */
3575                 intel_runtime_pm_disable_interrupts(dev_priv);
3576                 intel_runtime_pm_enable_interrupts(dev_priv);
3577
3578                 intel_pps_unlock_regs_wa(dev_priv);
3579                 intel_modeset_init_hw(dev);
3580
3581                 spin_lock_irq(&dev_priv->irq_lock);
3582                 if (dev_priv->display.hpd_irq_setup)
3583                         dev_priv->display.hpd_irq_setup(dev_priv);
3584                 spin_unlock_irq(&dev_priv->irq_lock);
3585
3586                 ret = __intel_display_resume(dev, state, ctx);
3587                 if (ret)
3588                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3589
3590                 intel_hpd_init(dev_priv);
3591         }
3592
3593         if (state)
3594                 drm_atomic_state_put(state);
3595         drm_modeset_drop_locks(ctx);
3596         drm_modeset_acquire_fini(ctx);
3597         mutex_unlock(&dev->mode_config.mutex);
3598 }
3599
3600 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3601 {
3602         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3603
3604         if (i915_reset_backoff(error))
3605                 return true;
3606
3607         if (crtc->reset_count != i915_reset_count(error))
3608                 return true;
3609
3610         return false;
3611 }
3612
3613 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3614 {
3615         struct drm_device *dev = crtc->dev;
3616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617         bool pending;
3618
3619         if (abort_flip_on_reset(intel_crtc))
3620                 return false;
3621
3622         spin_lock_irq(&dev->event_lock);
3623         pending = to_intel_crtc(crtc)->flip_work != NULL;
3624         spin_unlock_irq(&dev->event_lock);
3625
3626         return pending;
3627 }
3628
3629 static void intel_update_pipe_config(struct intel_crtc *crtc,
3630                                      struct intel_crtc_state *old_crtc_state)
3631 {
3632         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3633         struct intel_crtc_state *pipe_config =
3634                 to_intel_crtc_state(crtc->base.state);
3635
3636         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3637         crtc->base.mode = crtc->base.state->mode;
3638
3639         /*
3640          * Update pipe size and adjust fitter if needed: the reason for this is
3641          * that in compute_mode_changes we check the native mode (not the pfit
3642          * mode) to see if we can flip rather than do a full mode set. In the
3643          * fastboot case, we'll flip, but if we don't update the pipesrc and
3644          * pfit state, we'll end up with a big fb scanned out into the wrong
3645          * sized surface.
3646          */
3647
3648         I915_WRITE(PIPESRC(crtc->pipe),
3649                    ((pipe_config->pipe_src_w - 1) << 16) |
3650                    (pipe_config->pipe_src_h - 1));
3651
3652         /* on skylake this is done by detaching scalers */
3653         if (INTEL_GEN(dev_priv) >= 9) {
3654                 skl_detach_scalers(crtc);
3655
3656                 if (pipe_config->pch_pfit.enabled)
3657                         skylake_pfit_enable(crtc);
3658         } else if (HAS_PCH_SPLIT(dev_priv)) {
3659                 if (pipe_config->pch_pfit.enabled)
3660                         ironlake_pfit_enable(crtc);
3661                 else if (old_crtc_state->pch_pfit.enabled)
3662                         ironlake_pfit_disable(crtc, true);
3663         }
3664 }
3665
3666 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3667 {
3668         struct drm_device *dev = crtc->base.dev;
3669         struct drm_i915_private *dev_priv = to_i915(dev);
3670         int pipe = crtc->pipe;
3671         i915_reg_t reg;
3672         u32 temp;
3673
3674         /* enable normal train */
3675         reg = FDI_TX_CTL(pipe);
3676         temp = I915_READ(reg);
3677         if (IS_IVYBRIDGE(dev_priv)) {
3678                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3679                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3680         } else {
3681                 temp &= ~FDI_LINK_TRAIN_NONE;
3682                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3683         }
3684         I915_WRITE(reg, temp);
3685
3686         reg = FDI_RX_CTL(pipe);
3687         temp = I915_READ(reg);
3688         if (HAS_PCH_CPT(dev_priv)) {
3689                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3691         } else {
3692                 temp &= ~FDI_LINK_TRAIN_NONE;
3693                 temp |= FDI_LINK_TRAIN_NONE;
3694         }
3695         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3696
3697         /* wait one idle pattern time */
3698         POSTING_READ(reg);
3699         udelay(1000);
3700
3701         /* IVB wants error correction enabled */
3702         if (IS_IVYBRIDGE(dev_priv))
3703                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3704                            FDI_FE_ERRC_ENABLE);
3705 }
3706
3707 /* The FDI link training functions for ILK/Ibexpeak. */
3708 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3709                                     const struct intel_crtc_state *crtc_state)
3710 {
3711         struct drm_device *dev = crtc->base.dev;
3712         struct drm_i915_private *dev_priv = to_i915(dev);
3713         int pipe = crtc->pipe;
3714         i915_reg_t reg;
3715         u32 temp, tries;
3716
3717         /* FDI needs bits from pipe first */
3718         assert_pipe_enabled(dev_priv, pipe);
3719
3720         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3721            for train result */
3722         reg = FDI_RX_IMR(pipe);
3723         temp = I915_READ(reg);
3724         temp &= ~FDI_RX_SYMBOL_LOCK;
3725         temp &= ~FDI_RX_BIT_LOCK;
3726         I915_WRITE(reg, temp);
3727         I915_READ(reg);
3728         udelay(150);
3729
3730         /* enable CPU FDI TX and PCH FDI RX */
3731         reg = FDI_TX_CTL(pipe);
3732         temp = I915_READ(reg);
3733         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3734         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3735         temp &= ~FDI_LINK_TRAIN_NONE;
3736         temp |= FDI_LINK_TRAIN_PATTERN_1;
3737         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3738
3739         reg = FDI_RX_CTL(pipe);
3740         temp = I915_READ(reg);
3741         temp &= ~FDI_LINK_TRAIN_NONE;
3742         temp |= FDI_LINK_TRAIN_PATTERN_1;
3743         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3744
3745         POSTING_READ(reg);
3746         udelay(150);
3747
3748         /* Ironlake workaround, enable clock pointer after FDI enable*/
3749         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3750         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3751                    FDI_RX_PHASE_SYNC_POINTER_EN);
3752
3753         reg = FDI_RX_IIR(pipe);
3754         for (tries = 0; tries < 5; tries++) {
3755                 temp = I915_READ(reg);
3756                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3757
3758                 if ((temp & FDI_RX_BIT_LOCK)) {
3759                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3760                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3761                         break;
3762                 }
3763         }
3764         if (tries == 5)
3765                 DRM_ERROR("FDI train 1 fail!\n");
3766
3767         /* Train 2 */
3768         reg = FDI_TX_CTL(pipe);
3769         temp = I915_READ(reg);
3770         temp &= ~FDI_LINK_TRAIN_NONE;
3771         temp |= FDI_LINK_TRAIN_PATTERN_2;
3772         I915_WRITE(reg, temp);
3773
3774         reg = FDI_RX_CTL(pipe);
3775         temp = I915_READ(reg);
3776         temp &= ~FDI_LINK_TRAIN_NONE;
3777         temp |= FDI_LINK_TRAIN_PATTERN_2;
3778         I915_WRITE(reg, temp);
3779
3780         POSTING_READ(reg);
3781         udelay(150);
3782
3783         reg = FDI_RX_IIR(pipe);
3784         for (tries = 0; tries < 5; tries++) {
3785                 temp = I915_READ(reg);
3786                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3787
3788                 if (temp & FDI_RX_SYMBOL_LOCK) {
3789                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3790                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3791                         break;
3792                 }
3793         }
3794         if (tries == 5)
3795                 DRM_ERROR("FDI train 2 fail!\n");
3796
3797         DRM_DEBUG_KMS("FDI train done\n");
3798
3799 }
3800
3801 static const int snb_b_fdi_train_param[] = {
3802         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3803         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3804         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3805         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3806 };
3807
3808 /* The FDI link training functions for SNB/Cougarpoint. */
3809 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3810                                 const struct intel_crtc_state *crtc_state)
3811 {
3812         struct drm_device *dev = crtc->base.dev;
3813         struct drm_i915_private *dev_priv = to_i915(dev);
3814         int pipe = crtc->pipe;
3815         i915_reg_t reg;
3816         u32 temp, i, retry;
3817
3818         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3819            for train result */
3820         reg = FDI_RX_IMR(pipe);
3821         temp = I915_READ(reg);
3822         temp &= ~FDI_RX_SYMBOL_LOCK;
3823         temp &= ~FDI_RX_BIT_LOCK;
3824         I915_WRITE(reg, temp);
3825
3826         POSTING_READ(reg);
3827         udelay(150);
3828
3829         /* enable CPU FDI TX and PCH FDI RX */
3830         reg = FDI_TX_CTL(pipe);
3831         temp = I915_READ(reg);
3832         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3833         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3834         temp &= ~FDI_LINK_TRAIN_NONE;
3835         temp |= FDI_LINK_TRAIN_PATTERN_1;
3836         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3837         /* SNB-B */
3838         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3839         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3840
3841         I915_WRITE(FDI_RX_MISC(pipe),
3842                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3843
3844         reg = FDI_RX_CTL(pipe);
3845         temp = I915_READ(reg);
3846         if (HAS_PCH_CPT(dev_priv)) {
3847                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849         } else {
3850                 temp &= ~FDI_LINK_TRAIN_NONE;
3851                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852         }
3853         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3854
3855         POSTING_READ(reg);
3856         udelay(150);
3857
3858         for (i = 0; i < 4; i++) {
3859                 reg = FDI_TX_CTL(pipe);
3860                 temp = I915_READ(reg);
3861                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3862                 temp |= snb_b_fdi_train_param[i];
3863                 I915_WRITE(reg, temp);
3864
3865                 POSTING_READ(reg);
3866                 udelay(500);
3867
3868                 for (retry = 0; retry < 5; retry++) {
3869                         reg = FDI_RX_IIR(pipe);
3870                         temp = I915_READ(reg);
3871                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3872                         if (temp & FDI_RX_BIT_LOCK) {
3873                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3874                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3875                                 break;
3876                         }
3877                         udelay(50);
3878                 }
3879                 if (retry < 5)
3880                         break;
3881         }
3882         if (i == 4)
3883                 DRM_ERROR("FDI train 1 fail!\n");
3884
3885         /* Train 2 */
3886         reg = FDI_TX_CTL(pipe);
3887         temp = I915_READ(reg);
3888         temp &= ~FDI_LINK_TRAIN_NONE;
3889         temp |= FDI_LINK_TRAIN_PATTERN_2;
3890         if (IS_GEN6(dev_priv)) {
3891                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3892                 /* SNB-B */
3893                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3894         }
3895         I915_WRITE(reg, temp);
3896
3897         reg = FDI_RX_CTL(pipe);
3898         temp = I915_READ(reg);
3899         if (HAS_PCH_CPT(dev_priv)) {
3900                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3901                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3902         } else {
3903                 temp &= ~FDI_LINK_TRAIN_NONE;
3904                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3905         }
3906         I915_WRITE(reg, temp);
3907
3908         POSTING_READ(reg);
3909         udelay(150);
3910
3911         for (i = 0; i < 4; i++) {
3912                 reg = FDI_TX_CTL(pipe);
3913                 temp = I915_READ(reg);
3914                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3915                 temp |= snb_b_fdi_train_param[i];
3916                 I915_WRITE(reg, temp);
3917
3918                 POSTING_READ(reg);
3919                 udelay(500);
3920
3921                 for (retry = 0; retry < 5; retry++) {
3922                         reg = FDI_RX_IIR(pipe);
3923                         temp = I915_READ(reg);
3924                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3925                         if (temp & FDI_RX_SYMBOL_LOCK) {
3926                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3927                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3928                                 break;
3929                         }
3930                         udelay(50);
3931                 }
3932                 if (retry < 5)
3933                         break;
3934         }
3935         if (i == 4)
3936                 DRM_ERROR("FDI train 2 fail!\n");
3937
3938         DRM_DEBUG_KMS("FDI train done.\n");
3939 }
3940
3941 /* Manual link training for Ivy Bridge A0 parts */
3942 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3943                                       const struct intel_crtc_state *crtc_state)
3944 {
3945         struct drm_device *dev = crtc->base.dev;
3946         struct drm_i915_private *dev_priv = to_i915(dev);
3947         int pipe = crtc->pipe;
3948         i915_reg_t reg;
3949         u32 temp, i, j;
3950
3951         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3952            for train result */
3953         reg = FDI_RX_IMR(pipe);
3954         temp = I915_READ(reg);
3955         temp &= ~FDI_RX_SYMBOL_LOCK;
3956         temp &= ~FDI_RX_BIT_LOCK;
3957         I915_WRITE(reg, temp);
3958
3959         POSTING_READ(reg);
3960         udelay(150);
3961
3962         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3963                       I915_READ(FDI_RX_IIR(pipe)));
3964
3965         /* Try each vswing and preemphasis setting twice before moving on */
3966         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3967                 /* disable first in case we need to retry */
3968                 reg = FDI_TX_CTL(pipe);
3969                 temp = I915_READ(reg);
3970                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3971                 temp &= ~FDI_TX_ENABLE;
3972                 I915_WRITE(reg, temp);
3973
3974                 reg = FDI_RX_CTL(pipe);
3975                 temp = I915_READ(reg);
3976                 temp &= ~FDI_LINK_TRAIN_AUTO;
3977                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3978                 temp &= ~FDI_RX_ENABLE;
3979                 I915_WRITE(reg, temp);
3980
3981                 /* enable CPU FDI TX and PCH FDI RX */
3982                 reg = FDI_TX_CTL(pipe);
3983                 temp = I915_READ(reg);
3984                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3985                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3986                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3987                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3988                 temp |= snb_b_fdi_train_param[j/2];
3989                 temp |= FDI_COMPOSITE_SYNC;
3990                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3991
3992                 I915_WRITE(FDI_RX_MISC(pipe),
3993                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3994
3995                 reg = FDI_RX_CTL(pipe);
3996                 temp = I915_READ(reg);
3997                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3998                 temp |= FDI_COMPOSITE_SYNC;
3999                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4000
4001                 POSTING_READ(reg);
4002                 udelay(1); /* should be 0.5us */
4003
4004                 for (i = 0; i < 4; i++) {
4005                         reg = FDI_RX_IIR(pipe);
4006                         temp = I915_READ(reg);
4007                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4008
4009                         if (temp & FDI_RX_BIT_LOCK ||
4010                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4011                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4012                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4013                                               i);
4014                                 break;
4015                         }
4016                         udelay(1); /* should be 0.5us */
4017                 }
4018                 if (i == 4) {
4019                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4020                         continue;
4021                 }
4022
4023                 /* Train 2 */
4024                 reg = FDI_TX_CTL(pipe);
4025                 temp = I915_READ(reg);
4026                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4027                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4028                 I915_WRITE(reg, temp);
4029
4030                 reg = FDI_RX_CTL(pipe);
4031                 temp = I915_READ(reg);
4032                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4033                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4034                 I915_WRITE(reg, temp);
4035
4036                 POSTING_READ(reg);
4037                 udelay(2); /* should be 1.5us */
4038
4039                 for (i = 0; i < 4; i++) {
4040                         reg = FDI_RX_IIR(pipe);
4041                         temp = I915_READ(reg);
4042                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4043
4044                         if (temp & FDI_RX_SYMBOL_LOCK ||
4045                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4046                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4047                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4048                                               i);
4049                                 goto train_done;
4050                         }
4051                         udelay(2); /* should be 1.5us */
4052                 }
4053                 if (i == 4)
4054                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4055         }
4056
4057 train_done:
4058         DRM_DEBUG_KMS("FDI train done.\n");
4059 }
4060
4061 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4062 {
4063         struct drm_device *dev = intel_crtc->base.dev;
4064         struct drm_i915_private *dev_priv = to_i915(dev);
4065         int pipe = intel_crtc->pipe;
4066         i915_reg_t reg;
4067         u32 temp;
4068
4069         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4070         reg = FDI_RX_CTL(pipe);
4071         temp = I915_READ(reg);
4072         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4073         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4074         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4075         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4076
4077         POSTING_READ(reg);
4078         udelay(200);
4079
4080         /* Switch from Rawclk to PCDclk */
4081         temp = I915_READ(reg);
4082         I915_WRITE(reg, temp | FDI_PCDCLK);
4083
4084         POSTING_READ(reg);
4085         udelay(200);
4086
4087         /* Enable CPU FDI TX PLL, always on for Ironlake */
4088         reg = FDI_TX_CTL(pipe);
4089         temp = I915_READ(reg);
4090         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4091                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4092
4093                 POSTING_READ(reg);
4094                 udelay(100);
4095         }
4096 }
4097
4098 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4099 {
4100         struct drm_device *dev = intel_crtc->base.dev;
4101         struct drm_i915_private *dev_priv = to_i915(dev);
4102         int pipe = intel_crtc->pipe;
4103         i915_reg_t reg;
4104         u32 temp;
4105
4106         /* Switch from PCDclk to Rawclk */
4107         reg = FDI_RX_CTL(pipe);
4108         temp = I915_READ(reg);
4109         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4110
4111         /* Disable CPU FDI TX PLL */
4112         reg = FDI_TX_CTL(pipe);
4113         temp = I915_READ(reg);
4114         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4115
4116         POSTING_READ(reg);
4117         udelay(100);
4118
4119         reg = FDI_RX_CTL(pipe);
4120         temp = I915_READ(reg);
4121         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4122
4123         /* Wait for the clocks to turn off. */
4124         POSTING_READ(reg);
4125         udelay(100);
4126 }
4127
4128 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4129 {
4130         struct drm_device *dev = crtc->dev;
4131         struct drm_i915_private *dev_priv = to_i915(dev);
4132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133         int pipe = intel_crtc->pipe;
4134         i915_reg_t reg;
4135         u32 temp;
4136
4137         /* disable CPU FDI tx and PCH FDI rx */
4138         reg = FDI_TX_CTL(pipe);
4139         temp = I915_READ(reg);
4140         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4141         POSTING_READ(reg);
4142
4143         reg = FDI_RX_CTL(pipe);
4144         temp = I915_READ(reg);
4145         temp &= ~(0x7 << 16);
4146         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4147         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4148
4149         POSTING_READ(reg);
4150         udelay(100);
4151
4152         /* Ironlake workaround, disable clock pointer after downing FDI */
4153         if (HAS_PCH_IBX(dev_priv))
4154                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4155
4156         /* still set train pattern 1 */
4157         reg = FDI_TX_CTL(pipe);
4158         temp = I915_READ(reg);
4159         temp &= ~FDI_LINK_TRAIN_NONE;
4160         temp |= FDI_LINK_TRAIN_PATTERN_1;
4161         I915_WRITE(reg, temp);
4162
4163         reg = FDI_RX_CTL(pipe);
4164         temp = I915_READ(reg);
4165         if (HAS_PCH_CPT(dev_priv)) {
4166                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4167                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4168         } else {
4169                 temp &= ~FDI_LINK_TRAIN_NONE;
4170                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4171         }
4172         /* BPC in FDI rx is consistent with that in PIPECONF */
4173         temp &= ~(0x07 << 16);
4174         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4175         I915_WRITE(reg, temp);
4176
4177         POSTING_READ(reg);
4178         udelay(100);
4179 }
4180
4181 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4182 {
4183         struct intel_crtc *crtc;
4184
4185         /* Note that we don't need to be called with mode_config.lock here
4186          * as our list of CRTC objects is static for the lifetime of the
4187          * device and so cannot disappear as we iterate. Similarly, we can
4188          * happily treat the predicates as racy, atomic checks as userspace
4189          * cannot claim and pin a new fb without at least acquring the
4190          * struct_mutex and so serialising with us.
4191          */
4192         for_each_intel_crtc(&dev_priv->drm, crtc) {
4193                 if (atomic_read(&crtc->unpin_work_count) == 0)
4194                         continue;
4195
4196                 if (crtc->flip_work)
4197                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4198
4199                 return true;
4200         }
4201
4202         return false;
4203 }
4204
4205 static void page_flip_completed(struct intel_crtc *intel_crtc)
4206 {
4207         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4208         struct intel_flip_work *work = intel_crtc->flip_work;
4209
4210         intel_crtc->flip_work = NULL;
4211
4212         if (work->event)
4213                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4214
4215         drm_crtc_vblank_put(&intel_crtc->base);
4216
4217         wake_up_all(&dev_priv->pending_flip_queue);
4218         trace_i915_flip_complete(intel_crtc->plane,
4219                                  work->pending_flip_obj);
4220
4221         queue_work(dev_priv->wq, &work->unpin_work);
4222 }
4223
4224 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4225 {
4226         struct drm_device *dev = crtc->dev;
4227         struct drm_i915_private *dev_priv = to_i915(dev);
4228         long ret;
4229
4230         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4231
4232         ret = wait_event_interruptible_timeout(
4233                                         dev_priv->pending_flip_queue,
4234                                         !intel_crtc_has_pending_flip(crtc),
4235                                         60*HZ);
4236
4237         if (ret < 0)
4238                 return ret;
4239
4240         if (ret == 0) {
4241                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242                 struct intel_flip_work *work;
4243
4244                 spin_lock_irq(&dev->event_lock);
4245                 work = intel_crtc->flip_work;
4246                 if (work && !is_mmio_work(work)) {
4247                         WARN_ONCE(1, "Removing stuck page flip\n");
4248                         page_flip_completed(intel_crtc);
4249                 }
4250                 spin_unlock_irq(&dev->event_lock);
4251         }
4252
4253         return 0;
4254 }
4255
4256 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4257 {
4258         u32 temp;
4259
4260         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4261
4262         mutex_lock(&dev_priv->sb_lock);
4263
4264         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4265         temp |= SBI_SSCCTL_DISABLE;
4266         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4267
4268         mutex_unlock(&dev_priv->sb_lock);
4269 }
4270
4271 /* Program iCLKIP clock to the desired frequency */
4272 static void lpt_program_iclkip(struct intel_crtc *crtc)
4273 {
4274         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4275         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4276         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4277         u32 temp;
4278
4279         lpt_disable_iclkip(dev_priv);
4280
4281         /* The iCLK virtual clock root frequency is in MHz,
4282          * but the adjusted_mode->crtc_clock in in KHz. To get the
4283          * divisors, it is necessary to divide one by another, so we
4284          * convert the virtual clock precision to KHz here for higher
4285          * precision.
4286          */
4287         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4288                 u32 iclk_virtual_root_freq = 172800 * 1000;
4289                 u32 iclk_pi_range = 64;
4290                 u32 desired_divisor;
4291
4292                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4293                                                     clock << auxdiv);
4294                 divsel = (desired_divisor / iclk_pi_range) - 2;
4295                 phaseinc = desired_divisor % iclk_pi_range;
4296
4297                 /*
4298                  * Near 20MHz is a corner case which is
4299                  * out of range for the 7-bit divisor
4300                  */
4301                 if (divsel <= 0x7f)
4302                         break;
4303         }
4304
4305         /* This should not happen with any sane values */
4306         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4307                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4308         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4309                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4310
4311         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4312                         clock,
4313                         auxdiv,
4314                         divsel,
4315                         phasedir,
4316                         phaseinc);
4317
4318         mutex_lock(&dev_priv->sb_lock);
4319
4320         /* Program SSCDIVINTPHASE6 */
4321         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4322         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4323         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4324         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4325         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4326         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4327         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4328         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4329
4330         /* Program SSCAUXDIV */
4331         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4332         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4333         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4334         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4335
4336         /* Enable modulator and associated divider */
4337         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4338         temp &= ~SBI_SSCCTL_DISABLE;
4339         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4340
4341         mutex_unlock(&dev_priv->sb_lock);
4342
4343         /* Wait for initialization time */
4344         udelay(24);
4345
4346         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4347 }
4348
4349 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4350 {
4351         u32 divsel, phaseinc, auxdiv;
4352         u32 iclk_virtual_root_freq = 172800 * 1000;
4353         u32 iclk_pi_range = 64;
4354         u32 desired_divisor;
4355         u32 temp;
4356
4357         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4358                 return 0;
4359
4360         mutex_lock(&dev_priv->sb_lock);
4361
4362         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4363         if (temp & SBI_SSCCTL_DISABLE) {
4364                 mutex_unlock(&dev_priv->sb_lock);
4365                 return 0;
4366         }
4367
4368         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4369         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4370                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4371         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4372                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4373
4374         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4375         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4376                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4377
4378         mutex_unlock(&dev_priv->sb_lock);
4379
4380         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4381
4382         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4383                                  desired_divisor << auxdiv);
4384 }
4385
4386 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4387                                                 enum pipe pch_transcoder)
4388 {
4389         struct drm_device *dev = crtc->base.dev;
4390         struct drm_i915_private *dev_priv = to_i915(dev);
4391         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4392
4393         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4394                    I915_READ(HTOTAL(cpu_transcoder)));
4395         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4396                    I915_READ(HBLANK(cpu_transcoder)));
4397         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4398                    I915_READ(HSYNC(cpu_transcoder)));
4399
4400         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4401                    I915_READ(VTOTAL(cpu_transcoder)));
4402         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4403                    I915_READ(VBLANK(cpu_transcoder)));
4404         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4405                    I915_READ(VSYNC(cpu_transcoder)));
4406         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4407                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4408 }
4409
4410 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4411 {
4412         struct drm_i915_private *dev_priv = to_i915(dev);
4413         uint32_t temp;
4414
4415         temp = I915_READ(SOUTH_CHICKEN1);
4416         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4417                 return;
4418
4419         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4420         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4421
4422         temp &= ~FDI_BC_BIFURCATION_SELECT;
4423         if (enable)
4424                 temp |= FDI_BC_BIFURCATION_SELECT;
4425
4426         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4427         I915_WRITE(SOUTH_CHICKEN1, temp);
4428         POSTING_READ(SOUTH_CHICKEN1);
4429 }
4430
4431 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4432 {
4433         struct drm_device *dev = intel_crtc->base.dev;
4434
4435         switch (intel_crtc->pipe) {
4436         case PIPE_A:
4437                 break;
4438         case PIPE_B:
4439                 if (intel_crtc->config->fdi_lanes > 2)
4440                         cpt_set_fdi_bc_bifurcation(dev, false);
4441                 else
4442                         cpt_set_fdi_bc_bifurcation(dev, true);
4443
4444                 break;
4445         case PIPE_C:
4446                 cpt_set_fdi_bc_bifurcation(dev, true);
4447
4448                 break;
4449         default:
4450                 BUG();
4451         }
4452 }
4453
4454 /* Return which DP Port should be selected for Transcoder DP control */
4455 static enum port
4456 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4457 {
4458         struct drm_device *dev = crtc->base.dev;
4459         struct intel_encoder *encoder;
4460
4461         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4462                 if (encoder->type == INTEL_OUTPUT_DP ||
4463                     encoder->type == INTEL_OUTPUT_EDP)
4464                         return enc_to_dig_port(&encoder->base)->port;
4465         }
4466
4467         return -1;
4468 }
4469
4470 /*
4471  * Enable PCH resources required for PCH ports:
4472  *   - PCH PLLs
4473  *   - FDI training & RX/TX
4474  *   - update transcoder timings
4475  *   - DP transcoding bits
4476  *   - transcoder
4477  */
4478 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4479 {
4480         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4481         struct drm_device *dev = crtc->base.dev;
4482         struct drm_i915_private *dev_priv = to_i915(dev);
4483         int pipe = crtc->pipe;
4484         u32 temp;
4485
4486         assert_pch_transcoder_disabled(dev_priv, pipe);
4487
4488         if (IS_IVYBRIDGE(dev_priv))
4489                 ivybridge_update_fdi_bc_bifurcation(crtc);
4490
4491         /* Write the TU size bits before fdi link training, so that error
4492          * detection works. */
4493         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4494                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4495
4496         /* For PCH output, training FDI link */
4497         dev_priv->display.fdi_link_train(crtc, crtc_state);
4498
4499         /* We need to program the right clock selection before writing the pixel
4500          * mutliplier into the DPLL. */
4501         if (HAS_PCH_CPT(dev_priv)) {
4502                 u32 sel;
4503
4504                 temp = I915_READ(PCH_DPLL_SEL);
4505                 temp |= TRANS_DPLL_ENABLE(pipe);
4506                 sel = TRANS_DPLLB_SEL(pipe);
4507                 if (crtc_state->shared_dpll ==
4508                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4509                         temp |= sel;
4510                 else
4511                         temp &= ~sel;
4512                 I915_WRITE(PCH_DPLL_SEL, temp);
4513         }
4514
4515         /* XXX: pch pll's can be enabled any time before we enable the PCH
4516          * transcoder, and we actually should do this to not upset any PCH
4517          * transcoder that already use the clock when we share it.
4518          *
4519          * Note that enable_shared_dpll tries to do the right thing, but
4520          * get_shared_dpll unconditionally resets the pll - we need that to have
4521          * the right LVDS enable sequence. */
4522         intel_enable_shared_dpll(crtc);
4523
4524         /* set transcoder timing, panel must allow it */
4525         assert_panel_unlocked(dev_priv, pipe);
4526         ironlake_pch_transcoder_set_timings(crtc, pipe);
4527
4528         intel_fdi_normal_train(crtc);
4529
4530         /* For PCH DP, enable TRANS_DP_CTL */
4531         if (HAS_PCH_CPT(dev_priv) &&
4532             intel_crtc_has_dp_encoder(crtc_state)) {
4533                 const struct drm_display_mode *adjusted_mode =
4534                         &crtc_state->base.adjusted_mode;
4535                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4536                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4537                 temp = I915_READ(reg);
4538                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4539                           TRANS_DP_SYNC_MASK |
4540                           TRANS_DP_BPC_MASK);
4541                 temp |= TRANS_DP_OUTPUT_ENABLE;
4542                 temp |= bpc << 9; /* same format but at 11:9 */
4543
4544                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4545                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4546                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4547                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4548
4549                 switch (intel_trans_dp_port_sel(crtc)) {
4550                 case PORT_B:
4551                         temp |= TRANS_DP_PORT_SEL_B;
4552                         break;
4553                 case PORT_C:
4554                         temp |= TRANS_DP_PORT_SEL_C;
4555                         break;
4556                 case PORT_D:
4557                         temp |= TRANS_DP_PORT_SEL_D;
4558                         break;
4559                 default:
4560                         BUG();
4561                 }
4562
4563                 I915_WRITE(reg, temp);
4564         }
4565
4566         ironlake_enable_pch_transcoder(dev_priv, pipe);
4567 }
4568
4569 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4570 {
4571         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4572         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4573         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4574
4575         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4576
4577         lpt_program_iclkip(crtc);
4578
4579         /* Set transcoder timing. */
4580         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4581
4582         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4583 }
4584
4585 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4586 {
4587         struct drm_i915_private *dev_priv = to_i915(dev);
4588         i915_reg_t dslreg = PIPEDSL(pipe);
4589         u32 temp;
4590
4591         temp = I915_READ(dslreg);
4592         udelay(500);
4593         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4594                 if (wait_for(I915_READ(dslreg) != temp, 5))
4595                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4596         }
4597 }
4598
4599 static int
4600 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4601                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4602                   int src_w, int src_h, int dst_w, int dst_h)
4603 {
4604         struct intel_crtc_scaler_state *scaler_state =
4605                 &crtc_state->scaler_state;
4606         struct intel_crtc *intel_crtc =
4607                 to_intel_crtc(crtc_state->base.crtc);
4608         int need_scaling;
4609
4610         need_scaling = drm_rotation_90_or_270(rotation) ?
4611                 (src_h != dst_w || src_w != dst_h):
4612                 (src_w != dst_w || src_h != dst_h);
4613
4614         /*
4615          * if plane is being disabled or scaler is no more required or force detach
4616          *  - free scaler binded to this plane/crtc
4617          *  - in order to do this, update crtc->scaler_usage
4618          *
4619          * Here scaler state in crtc_state is set free so that
4620          * scaler can be assigned to other user. Actual register
4621          * update to free the scaler is done in plane/panel-fit programming.
4622          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4623          */
4624         if (force_detach || !need_scaling) {
4625                 if (*scaler_id >= 0) {
4626                         scaler_state->scaler_users &= ~(1 << scaler_user);
4627                         scaler_state->scalers[*scaler_id].in_use = 0;
4628
4629                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4630                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4631                                 intel_crtc->pipe, scaler_user, *scaler_id,
4632                                 scaler_state->scaler_users);
4633                         *scaler_id = -1;
4634                 }
4635                 return 0;
4636         }
4637
4638         /* range checks */
4639         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4640                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4641
4642                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4643                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4644                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4645                         "size is out of scaler range\n",
4646                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4647                 return -EINVAL;
4648         }
4649
4650         /* mark this plane as a scaler user in crtc_state */
4651         scaler_state->scaler_users |= (1 << scaler_user);
4652         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4653                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4654                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4655                 scaler_state->scaler_users);
4656
4657         return 0;
4658 }
4659
4660 /**
4661  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4662  *
4663  * @state: crtc's scaler state
4664  *
4665  * Return
4666  *     0 - scaler_usage updated successfully
4667  *    error - requested scaling cannot be supported or other error condition
4668  */
4669 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4670 {
4671         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4672
4673         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4674                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4675                 state->pipe_src_w, state->pipe_src_h,
4676                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4677 }
4678
4679 /**
4680  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4681  *
4682  * @state: crtc's scaler state
4683  * @plane_state: atomic plane state to update
4684  *
4685  * Return
4686  *     0 - scaler_usage updated successfully
4687  *    error - requested scaling cannot be supported or other error condition
4688  */
4689 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4690                                    struct intel_plane_state *plane_state)
4691 {
4692
4693         struct intel_plane *intel_plane =
4694                 to_intel_plane(plane_state->base.plane);
4695         struct drm_framebuffer *fb = plane_state->base.fb;
4696         int ret;
4697
4698         bool force_detach = !fb || !plane_state->base.visible;
4699
4700         ret = skl_update_scaler(crtc_state, force_detach,
4701                                 drm_plane_index(&intel_plane->base),
4702                                 &plane_state->scaler_id,
4703                                 plane_state->base.rotation,
4704                                 drm_rect_width(&plane_state->base.src) >> 16,
4705                                 drm_rect_height(&plane_state->base.src) >> 16,
4706                                 drm_rect_width(&plane_state->base.dst),
4707                                 drm_rect_height(&plane_state->base.dst));
4708
4709         if (ret || plane_state->scaler_id < 0)
4710                 return ret;
4711
4712         /* check colorkey */
4713         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4714                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4715                               intel_plane->base.base.id,
4716                               intel_plane->base.name);
4717                 return -EINVAL;
4718         }
4719
4720         /* Check src format */
4721         switch (fb->format->format) {
4722         case DRM_FORMAT_RGB565:
4723         case DRM_FORMAT_XBGR8888:
4724         case DRM_FORMAT_XRGB8888:
4725         case DRM_FORMAT_ABGR8888:
4726         case DRM_FORMAT_ARGB8888:
4727         case DRM_FORMAT_XRGB2101010:
4728         case DRM_FORMAT_XBGR2101010:
4729         case DRM_FORMAT_YUYV:
4730         case DRM_FORMAT_YVYU:
4731         case DRM_FORMAT_UYVY:
4732         case DRM_FORMAT_VYUY:
4733                 break;
4734         default:
4735                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4736                               intel_plane->base.base.id, intel_plane->base.name,
4737                               fb->base.id, fb->format->format);
4738                 return -EINVAL;
4739         }
4740
4741         return 0;
4742 }
4743
4744 static void skylake_scaler_disable(struct intel_crtc *crtc)
4745 {
4746         int i;
4747
4748         for (i = 0; i < crtc->num_scalers; i++)
4749                 skl_detach_scaler(crtc, i);
4750 }
4751
4752 static void skylake_pfit_enable(struct intel_crtc *crtc)
4753 {
4754         struct drm_device *dev = crtc->base.dev;
4755         struct drm_i915_private *dev_priv = to_i915(dev);
4756         int pipe = crtc->pipe;
4757         struct intel_crtc_scaler_state *scaler_state =
4758                 &crtc->config->scaler_state;
4759
4760         if (crtc->config->pch_pfit.enabled) {
4761                 int id;
4762
4763                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4764                         return;
4765
4766                 id = scaler_state->scaler_id;
4767                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4768                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4769                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4770                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4771         }
4772 }
4773
4774 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4775 {
4776         struct drm_device *dev = crtc->base.dev;
4777         struct drm_i915_private *dev_priv = to_i915(dev);
4778         int pipe = crtc->pipe;
4779
4780         if (crtc->config->pch_pfit.enabled) {
4781                 /* Force use of hard-coded filter coefficients
4782                  * as some pre-programmed values are broken,
4783                  * e.g. x201.
4784                  */
4785                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4786                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4787                                                  PF_PIPE_SEL_IVB(pipe));
4788                 else
4789                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4790                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4791                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4792         }
4793 }
4794
4795 void hsw_enable_ips(struct intel_crtc *crtc)
4796 {
4797         struct drm_device *dev = crtc->base.dev;
4798         struct drm_i915_private *dev_priv = to_i915(dev);
4799
4800         if (!crtc->config->ips_enabled)
4801                 return;
4802
4803         /*
4804          * We can only enable IPS after we enable a plane and wait for a vblank
4805          * This function is called from post_plane_update, which is run after
4806          * a vblank wait.
4807          */
4808
4809         assert_plane_enabled(dev_priv, crtc->plane);
4810         if (IS_BROADWELL(dev_priv)) {
4811                 mutex_lock(&dev_priv->rps.hw_lock);
4812                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4813                 mutex_unlock(&dev_priv->rps.hw_lock);
4814                 /* Quoting Art Runyan: "its not safe to expect any particular
4815                  * value in IPS_CTL bit 31 after enabling IPS through the
4816                  * mailbox." Moreover, the mailbox may return a bogus state,
4817                  * so we need to just enable it and continue on.
4818                  */
4819         } else {
4820                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4821                 /* The bit only becomes 1 in the next vblank, so this wait here
4822                  * is essentially intel_wait_for_vblank. If we don't have this
4823                  * and don't wait for vblanks until the end of crtc_enable, then
4824                  * the HW state readout code will complain that the expected
4825                  * IPS_CTL value is not the one we read. */
4826                 if (intel_wait_for_register(dev_priv,
4827                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4828                                             50))
4829                         DRM_ERROR("Timed out waiting for IPS enable\n");
4830         }
4831 }
4832
4833 void hsw_disable_ips(struct intel_crtc *crtc)
4834 {
4835         struct drm_device *dev = crtc->base.dev;
4836         struct drm_i915_private *dev_priv = to_i915(dev);
4837
4838         if (!crtc->config->ips_enabled)
4839                 return;
4840
4841         assert_plane_enabled(dev_priv, crtc->plane);
4842         if (IS_BROADWELL(dev_priv)) {
4843                 mutex_lock(&dev_priv->rps.hw_lock);
4844                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4845                 mutex_unlock(&dev_priv->rps.hw_lock);
4846                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4847                 if (intel_wait_for_register(dev_priv,
4848                                             IPS_CTL, IPS_ENABLE, 0,
4849                                             42))
4850                         DRM_ERROR("Timed out waiting for IPS disable\n");
4851         } else {
4852                 I915_WRITE(IPS_CTL, 0);
4853                 POSTING_READ(IPS_CTL);
4854         }
4855
4856         /* We need to wait for a vblank before we can disable the plane. */
4857         intel_wait_for_vblank(dev_priv, crtc->pipe);
4858 }
4859
4860 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4861 {
4862         if (intel_crtc->overlay) {
4863                 struct drm_device *dev = intel_crtc->base.dev;
4864                 struct drm_i915_private *dev_priv = to_i915(dev);
4865
4866                 mutex_lock(&dev->struct_mutex);
4867                 dev_priv->mm.interruptible = false;
4868                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4869                 dev_priv->mm.interruptible = true;
4870                 mutex_unlock(&dev->struct_mutex);
4871         }
4872
4873         /* Let userspace switch the overlay on again. In most cases userspace
4874          * has to recompute where to put it anyway.
4875          */
4876 }
4877
4878 /**
4879  * intel_post_enable_primary - Perform operations after enabling primary plane
4880  * @crtc: the CRTC whose primary plane was just enabled
4881  *
4882  * Performs potentially sleeping operations that must be done after the primary
4883  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4884  * called due to an explicit primary plane update, or due to an implicit
4885  * re-enable that is caused when a sprite plane is updated to no longer
4886  * completely hide the primary plane.
4887  */
4888 static void
4889 intel_post_enable_primary(struct drm_crtc *crtc)
4890 {
4891         struct drm_device *dev = crtc->dev;
4892         struct drm_i915_private *dev_priv = to_i915(dev);
4893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894         int pipe = intel_crtc->pipe;
4895
4896         /*
4897          * FIXME IPS should be fine as long as one plane is
4898          * enabled, but in practice it seems to have problems
4899          * when going from primary only to sprite only and vice
4900          * versa.
4901          */
4902         hsw_enable_ips(intel_crtc);
4903
4904         /*
4905          * Gen2 reports pipe underruns whenever all planes are disabled.
4906          * So don't enable underrun reporting before at least some planes
4907          * are enabled.
4908          * FIXME: Need to fix the logic to work when we turn off all planes
4909          * but leave the pipe running.
4910          */
4911         if (IS_GEN2(dev_priv))
4912                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4913
4914         /* Underruns don't always raise interrupts, so check manually. */
4915         intel_check_cpu_fifo_underruns(dev_priv);
4916         intel_check_pch_fifo_underruns(dev_priv);
4917 }
4918
4919 /* FIXME move all this to pre_plane_update() with proper state tracking */
4920 static void
4921 intel_pre_disable_primary(struct drm_crtc *crtc)
4922 {
4923         struct drm_device *dev = crtc->dev;
4924         struct drm_i915_private *dev_priv = to_i915(dev);
4925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4926         int pipe = intel_crtc->pipe;
4927
4928         /*
4929          * Gen2 reports pipe underruns whenever all planes are disabled.
4930          * So diasble underrun reporting before all the planes get disabled.
4931          * FIXME: Need to fix the logic to work when we turn off all planes
4932          * but leave the pipe running.
4933          */
4934         if (IS_GEN2(dev_priv))
4935                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4936
4937         /*
4938          * FIXME IPS should be fine as long as one plane is
4939          * enabled, but in practice it seems to have problems
4940          * when going from primary only to sprite only and vice
4941          * versa.
4942          */
4943         hsw_disable_ips(intel_crtc);
4944 }
4945
4946 /* FIXME get rid of this and use pre_plane_update */
4947 static void
4948 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4949 {
4950         struct drm_device *dev = crtc->dev;
4951         struct drm_i915_private *dev_priv = to_i915(dev);
4952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4953         int pipe = intel_crtc->pipe;
4954
4955         intel_pre_disable_primary(crtc);
4956
4957         /*
4958          * Vblank time updates from the shadow to live plane control register
4959          * are blocked if the memory self-refresh mode is active at that
4960          * moment. So to make sure the plane gets truly disabled, disable
4961          * first the self-refresh mode. The self-refresh enable bit in turn
4962          * will be checked/applied by the HW only at the next frame start
4963          * event which is after the vblank start event, so we need to have a
4964          * wait-for-vblank between disabling the plane and the pipe.
4965          */
4966         if (HAS_GMCH_DISPLAY(dev_priv) &&
4967             intel_set_memory_cxsr(dev_priv, false))
4968                 intel_wait_for_vblank(dev_priv, pipe);
4969 }
4970
4971 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4972 {
4973         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4974         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4975         struct intel_crtc_state *pipe_config =
4976                 to_intel_crtc_state(crtc->base.state);
4977         struct drm_plane *primary = crtc->base.primary;
4978         struct drm_plane_state *old_pri_state =
4979                 drm_atomic_get_existing_plane_state(old_state, primary);
4980
4981         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4982
4983         if (pipe_config->update_wm_post && pipe_config->base.active)
4984                 intel_update_watermarks(crtc);
4985
4986         if (old_pri_state) {
4987                 struct intel_plane_state *primary_state =
4988                         to_intel_plane_state(primary->state);
4989                 struct intel_plane_state *old_primary_state =
4990                         to_intel_plane_state(old_pri_state);
4991
4992                 intel_fbc_post_update(crtc);
4993
4994                 if (primary_state->base.visible &&
4995                     (needs_modeset(&pipe_config->base) ||
4996                      !old_primary_state->base.visible))
4997                         intel_post_enable_primary(&crtc->base);
4998         }
4999 }
5000
5001 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5002                                    struct intel_crtc_state *pipe_config)
5003 {
5004         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5005         struct drm_device *dev = crtc->base.dev;
5006         struct drm_i915_private *dev_priv = to_i915(dev);
5007         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5008         struct drm_plane *primary = crtc->base.primary;
5009         struct drm_plane_state *old_pri_state =
5010                 drm_atomic_get_existing_plane_state(old_state, primary);
5011         bool modeset = needs_modeset(&pipe_config->base);
5012         struct intel_atomic_state *old_intel_state =
5013                 to_intel_atomic_state(old_state);
5014
5015         if (old_pri_state) {
5016                 struct intel_plane_state *primary_state =
5017                         to_intel_plane_state(primary->state);
5018                 struct intel_plane_state *old_primary_state =
5019                         to_intel_plane_state(old_pri_state);
5020
5021                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5022
5023                 if (old_primary_state->base.visible &&
5024                     (modeset || !primary_state->base.visible))
5025                         intel_pre_disable_primary(&crtc->base);
5026         }
5027
5028         /*
5029          * Vblank time updates from the shadow to live plane control register
5030          * are blocked if the memory self-refresh mode is active at that
5031          * moment. So to make sure the plane gets truly disabled, disable
5032          * first the self-refresh mode. The self-refresh enable bit in turn
5033          * will be checked/applied by the HW only at the next frame start
5034          * event which is after the vblank start event, so we need to have a
5035          * wait-for-vblank between disabling the plane and the pipe.
5036          */
5037         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5038             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5039                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5040
5041         /*
5042          * IVB workaround: must disable low power watermarks for at least
5043          * one frame before enabling scaling.  LP watermarks can be re-enabled
5044          * when scaling is disabled.
5045          *
5046          * WaCxSRDisabledForSpriteScaling:ivb
5047          */
5048         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5049                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5050
5051         /*
5052          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5053          * watermark programming here.
5054          */
5055         if (needs_modeset(&pipe_config->base))
5056                 return;
5057
5058         /*
5059          * For platforms that support atomic watermarks, program the
5060          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5061          * will be the intermediate values that are safe for both pre- and
5062          * post- vblank; when vblank happens, the 'active' values will be set
5063          * to the final 'target' values and we'll do this again to get the
5064          * optimal watermarks.  For gen9+ platforms, the values we program here
5065          * will be the final target values which will get automatically latched
5066          * at vblank time; no further programming will be necessary.
5067          *
5068          * If a platform hasn't been transitioned to atomic watermarks yet,
5069          * we'll continue to update watermarks the old way, if flags tell
5070          * us to.
5071          */
5072         if (dev_priv->display.initial_watermarks != NULL)
5073                 dev_priv->display.initial_watermarks(old_intel_state,
5074                                                      pipe_config);
5075         else if (pipe_config->update_wm_pre)
5076                 intel_update_watermarks(crtc);
5077 }
5078
5079 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5080 {
5081         struct drm_device *dev = crtc->dev;
5082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083         struct drm_plane *p;
5084         int pipe = intel_crtc->pipe;
5085
5086         intel_crtc_dpms_overlay_disable(intel_crtc);
5087
5088         drm_for_each_plane_mask(p, dev, plane_mask)
5089                 to_intel_plane(p)->disable_plane(p, crtc);
5090
5091         /*
5092          * FIXME: Once we grow proper nuclear flip support out of this we need
5093          * to compute the mask of flip planes precisely. For the time being
5094          * consider this a flip to a NULL plane.
5095          */
5096         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5097 }
5098
5099 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5100                                           struct intel_crtc_state *crtc_state,
5101                                           struct drm_atomic_state *old_state)
5102 {
5103         struct drm_connector_state *conn_state;
5104         struct drm_connector *conn;
5105         int i;
5106
5107         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5108                 struct intel_encoder *encoder =
5109                         to_intel_encoder(conn_state->best_encoder);
5110
5111                 if (conn_state->crtc != crtc)
5112                         continue;
5113
5114                 if (encoder->pre_pll_enable)
5115                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5116         }
5117 }
5118
5119 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5120                                       struct intel_crtc_state *crtc_state,
5121                                       struct drm_atomic_state *old_state)
5122 {
5123         struct drm_connector_state *conn_state;
5124         struct drm_connector *conn;
5125         int i;
5126
5127         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5128                 struct intel_encoder *encoder =
5129                         to_intel_encoder(conn_state->best_encoder);
5130
5131                 if (conn_state->crtc != crtc)
5132                         continue;
5133
5134                 if (encoder->pre_enable)
5135                         encoder->pre_enable(encoder, crtc_state, conn_state);
5136         }
5137 }
5138
5139 static void intel_encoders_enable(struct drm_crtc *crtc,
5140                                   struct intel_crtc_state *crtc_state,
5141                                   struct drm_atomic_state *old_state)
5142 {
5143         struct drm_connector_state *conn_state;
5144         struct drm_connector *conn;
5145         int i;
5146
5147         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5148                 struct intel_encoder *encoder =
5149                         to_intel_encoder(conn_state->best_encoder);
5150
5151                 if (conn_state->crtc != crtc)
5152                         continue;
5153
5154                 encoder->enable(encoder, crtc_state, conn_state);
5155                 intel_opregion_notify_encoder(encoder, true);
5156         }
5157 }
5158
5159 static void intel_encoders_disable(struct drm_crtc *crtc,
5160                                    struct intel_crtc_state *old_crtc_state,
5161                                    struct drm_atomic_state *old_state)
5162 {
5163         struct drm_connector_state *old_conn_state;
5164         struct drm_connector *conn;
5165         int i;
5166
5167         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5168                 struct intel_encoder *encoder =
5169                         to_intel_encoder(old_conn_state->best_encoder);
5170
5171                 if (old_conn_state->crtc != crtc)
5172                         continue;
5173
5174                 intel_opregion_notify_encoder(encoder, false);
5175                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5176         }
5177 }
5178
5179 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5180                                         struct intel_crtc_state *old_crtc_state,
5181                                         struct drm_atomic_state *old_state)
5182 {
5183         struct drm_connector_state *old_conn_state;
5184         struct drm_connector *conn;
5185         int i;
5186
5187         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5188                 struct intel_encoder *encoder =
5189                         to_intel_encoder(old_conn_state->best_encoder);
5190
5191                 if (old_conn_state->crtc != crtc)
5192                         continue;
5193
5194                 if (encoder->post_disable)
5195                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5196         }
5197 }
5198
5199 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5200                                             struct intel_crtc_state *old_crtc_state,
5201                                             struct drm_atomic_state *old_state)
5202 {
5203         struct drm_connector_state *old_conn_state;
5204         struct drm_connector *conn;
5205         int i;
5206
5207         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5208                 struct intel_encoder *encoder =
5209                         to_intel_encoder(old_conn_state->best_encoder);
5210
5211                 if (old_conn_state->crtc != crtc)
5212                         continue;
5213
5214                 if (encoder->post_pll_disable)
5215                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5216         }
5217 }
5218
5219 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5220                                  struct drm_atomic_state *old_state)
5221 {
5222         struct drm_crtc *crtc = pipe_config->base.crtc;
5223         struct drm_device *dev = crtc->dev;
5224         struct drm_i915_private *dev_priv = to_i915(dev);
5225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226         int pipe = intel_crtc->pipe;
5227         struct intel_atomic_state *old_intel_state =
5228                 to_intel_atomic_state(old_state);
5229
5230         if (WARN_ON(intel_crtc->active))
5231                 return;
5232
5233         /*
5234          * Sometimes spurious CPU pipe underruns happen during FDI
5235          * training, at least with VGA+HDMI cloning. Suppress them.
5236          *
5237          * On ILK we get an occasional spurious CPU pipe underruns
5238          * between eDP port A enable and vdd enable. Also PCH port
5239          * enable seems to result in the occasional CPU pipe underrun.
5240          *
5241          * Spurious PCH underruns also occur during PCH enabling.
5242          */
5243         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5244                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5245         if (intel_crtc->config->has_pch_encoder)
5246                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5247
5248         if (intel_crtc->config->has_pch_encoder)
5249                 intel_prepare_shared_dpll(intel_crtc);
5250
5251         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5252                 intel_dp_set_m_n(intel_crtc, M1_N1);
5253
5254         intel_set_pipe_timings(intel_crtc);
5255         intel_set_pipe_src_size(intel_crtc);
5256
5257         if (intel_crtc->config->has_pch_encoder) {
5258                 intel_cpu_transcoder_set_m_n(intel_crtc,
5259                                      &intel_crtc->config->fdi_m_n, NULL);
5260         }
5261
5262         ironlake_set_pipeconf(crtc);
5263
5264         intel_crtc->active = true;
5265
5266         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5267
5268         if (intel_crtc->config->has_pch_encoder) {
5269                 /* Note: FDI PLL enabling _must_ be done before we enable the
5270                  * cpu pipes, hence this is separate from all the other fdi/pch
5271                  * enabling. */
5272                 ironlake_fdi_pll_enable(intel_crtc);
5273         } else {
5274                 assert_fdi_tx_disabled(dev_priv, pipe);
5275                 assert_fdi_rx_disabled(dev_priv, pipe);
5276         }
5277
5278         ironlake_pfit_enable(intel_crtc);
5279
5280         /*
5281          * On ILK+ LUT must be loaded before the pipe is running but with
5282          * clocks enabled
5283          */
5284         intel_color_load_luts(&pipe_config->base);
5285
5286         if (dev_priv->display.initial_watermarks != NULL)
5287                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5288         intel_enable_pipe(intel_crtc);
5289
5290         if (intel_crtc->config->has_pch_encoder)
5291                 ironlake_pch_enable(pipe_config);
5292
5293         assert_vblank_disabled(crtc);
5294         drm_crtc_vblank_on(crtc);
5295
5296         intel_encoders_enable(crtc, pipe_config, old_state);
5297
5298         if (HAS_PCH_CPT(dev_priv))
5299                 cpt_verify_modeset(dev, intel_crtc->pipe);
5300
5301         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5302         if (intel_crtc->config->has_pch_encoder)
5303                 intel_wait_for_vblank(dev_priv, pipe);
5304         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5305         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5306 }
5307
5308 /* IPS only exists on ULT machines and is tied to pipe A. */
5309 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5310 {
5311         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5312 }
5313
5314 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5315                                 struct drm_atomic_state *old_state)
5316 {
5317         struct drm_crtc *crtc = pipe_config->base.crtc;
5318         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5320         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5321         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5322         struct intel_atomic_state *old_intel_state =
5323                 to_intel_atomic_state(old_state);
5324
5325         if (WARN_ON(intel_crtc->active))
5326                 return;
5327
5328         if (intel_crtc->config->has_pch_encoder)
5329                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5330                                                       false);
5331
5332         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5333
5334         if (intel_crtc->config->shared_dpll)
5335                 intel_enable_shared_dpll(intel_crtc);
5336
5337         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5338                 intel_dp_set_m_n(intel_crtc, M1_N1);
5339
5340         if (!transcoder_is_dsi(cpu_transcoder))
5341                 intel_set_pipe_timings(intel_crtc);
5342
5343         intel_set_pipe_src_size(intel_crtc);
5344
5345         if (cpu_transcoder != TRANSCODER_EDP &&
5346             !transcoder_is_dsi(cpu_transcoder)) {
5347                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5348                            intel_crtc->config->pixel_multiplier - 1);
5349         }
5350
5351         if (intel_crtc->config->has_pch_encoder) {
5352                 intel_cpu_transcoder_set_m_n(intel_crtc,
5353                                      &intel_crtc->config->fdi_m_n, NULL);
5354         }
5355
5356         if (!transcoder_is_dsi(cpu_transcoder))
5357                 haswell_set_pipeconf(crtc);
5358
5359         haswell_set_pipemisc(crtc);
5360
5361         intel_color_set_csc(&pipe_config->base);
5362
5363         intel_crtc->active = true;
5364
5365         if (intel_crtc->config->has_pch_encoder)
5366                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5367         else
5368                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5369
5370         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5371
5372         if (intel_crtc->config->has_pch_encoder)
5373                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5374
5375         if (!transcoder_is_dsi(cpu_transcoder))
5376                 intel_ddi_enable_pipe_clock(pipe_config);
5377
5378         if (INTEL_GEN(dev_priv) >= 9)
5379                 skylake_pfit_enable(intel_crtc);
5380         else
5381                 ironlake_pfit_enable(intel_crtc);
5382
5383         /*
5384          * On ILK+ LUT must be loaded before the pipe is running but with
5385          * clocks enabled
5386          */
5387         intel_color_load_luts(&pipe_config->base);
5388
5389         intel_ddi_set_pipe_settings(pipe_config);
5390         if (!transcoder_is_dsi(cpu_transcoder))
5391                 intel_ddi_enable_transcoder_func(pipe_config);
5392
5393         if (dev_priv->display.initial_watermarks != NULL)
5394                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5395
5396         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5397         if (!transcoder_is_dsi(cpu_transcoder))
5398                 intel_enable_pipe(intel_crtc);
5399
5400         if (intel_crtc->config->has_pch_encoder)
5401                 lpt_pch_enable(pipe_config);
5402
5403         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5404                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5405
5406         assert_vblank_disabled(crtc);
5407         drm_crtc_vblank_on(crtc);
5408
5409         intel_encoders_enable(crtc, pipe_config, old_state);
5410
5411         if (intel_crtc->config->has_pch_encoder) {
5412                 intel_wait_for_vblank(dev_priv, pipe);
5413                 intel_wait_for_vblank(dev_priv, pipe);
5414                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5415                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5416                                                       true);
5417         }
5418
5419         /* If we change the relative order between pipe/planes enabling, we need
5420          * to change the workaround. */
5421         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5422         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5423                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5424                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5425         }
5426 }
5427
5428 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5429 {
5430         struct drm_device *dev = crtc->base.dev;
5431         struct drm_i915_private *dev_priv = to_i915(dev);
5432         int pipe = crtc->pipe;
5433
5434         /* To avoid upsetting the power well on haswell only disable the pfit if
5435          * it's in use. The hw state code will make sure we get this right. */
5436         if (force || crtc->config->pch_pfit.enabled) {
5437                 I915_WRITE(PF_CTL(pipe), 0);
5438                 I915_WRITE(PF_WIN_POS(pipe), 0);
5439                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5440         }
5441 }
5442
5443 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5444                                   struct drm_atomic_state *old_state)
5445 {
5446         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5447         struct drm_device *dev = crtc->dev;
5448         struct drm_i915_private *dev_priv = to_i915(dev);
5449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5450         int pipe = intel_crtc->pipe;
5451
5452         /*
5453          * Sometimes spurious CPU pipe underruns happen when the
5454          * pipe is already disabled, but FDI RX/TX is still enabled.
5455          * Happens at least with VGA+HDMI cloning. Suppress them.
5456          */
5457         if (intel_crtc->config->has_pch_encoder) {
5458                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5459                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5460         }
5461
5462         intel_encoders_disable(crtc, old_crtc_state, old_state);
5463
5464         drm_crtc_vblank_off(crtc);
5465         assert_vblank_disabled(crtc);
5466
5467         intel_disable_pipe(intel_crtc);
5468
5469         ironlake_pfit_disable(intel_crtc, false);
5470
5471         if (intel_crtc->config->has_pch_encoder)
5472                 ironlake_fdi_disable(crtc);
5473
5474         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5475
5476         if (intel_crtc->config->has_pch_encoder) {
5477                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5478
5479                 if (HAS_PCH_CPT(dev_priv)) {
5480                         i915_reg_t reg;
5481                         u32 temp;
5482
5483                         /* disable TRANS_DP_CTL */
5484                         reg = TRANS_DP_CTL(pipe);
5485                         temp = I915_READ(reg);
5486                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5487                                   TRANS_DP_PORT_SEL_MASK);
5488                         temp |= TRANS_DP_PORT_SEL_NONE;
5489                         I915_WRITE(reg, temp);
5490
5491                         /* disable DPLL_SEL */
5492                         temp = I915_READ(PCH_DPLL_SEL);
5493                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5494                         I915_WRITE(PCH_DPLL_SEL, temp);
5495                 }
5496
5497                 ironlake_fdi_pll_disable(intel_crtc);
5498         }
5499
5500         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5501         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5502 }
5503
5504 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5505                                  struct drm_atomic_state *old_state)
5506 {
5507         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5508         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5510         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5511
5512         if (intel_crtc->config->has_pch_encoder)
5513                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5514                                                       false);
5515
5516         intel_encoders_disable(crtc, old_crtc_state, old_state);
5517
5518         drm_crtc_vblank_off(crtc);
5519         assert_vblank_disabled(crtc);
5520
5521         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5522         if (!transcoder_is_dsi(cpu_transcoder))
5523                 intel_disable_pipe(intel_crtc);
5524
5525         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5526                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5527
5528         if (!transcoder_is_dsi(cpu_transcoder))
5529                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5530
5531         if (INTEL_GEN(dev_priv) >= 9)
5532                 skylake_scaler_disable(intel_crtc);
5533         else
5534                 ironlake_pfit_disable(intel_crtc, false);
5535
5536         if (!transcoder_is_dsi(cpu_transcoder))
5537                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5538
5539         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5540
5541         if (old_crtc_state->has_pch_encoder)
5542                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5543                                                       true);
5544 }
5545
5546 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5547 {
5548         struct drm_device *dev = crtc->base.dev;
5549         struct drm_i915_private *dev_priv = to_i915(dev);
5550         struct intel_crtc_state *pipe_config = crtc->config;
5551
5552         if (!pipe_config->gmch_pfit.control)
5553                 return;
5554
5555         /*
5556          * The panel fitter should only be adjusted whilst the pipe is disabled,
5557          * according to register description and PRM.
5558          */
5559         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5560         assert_pipe_disabled(dev_priv, crtc->pipe);
5561
5562         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5563         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5564
5565         /* Border color in case we don't scale up to the full screen. Black by
5566          * default, change to something else for debugging. */
5567         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5568 }
5569
5570 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5571 {
5572         switch (port) {
5573         case PORT_A:
5574                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5575         case PORT_B:
5576                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5577         case PORT_C:
5578                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5579         case PORT_D:
5580                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5581         case PORT_E:
5582                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5583         default:
5584                 MISSING_CASE(port);
5585                 return POWER_DOMAIN_PORT_OTHER;
5586         }
5587 }
5588
5589 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5590                                   struct intel_crtc_state *crtc_state)
5591 {
5592         struct drm_device *dev = crtc->dev;
5593         struct drm_i915_private *dev_priv = to_i915(dev);
5594         struct drm_encoder *encoder;
5595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596         enum pipe pipe = intel_crtc->pipe;
5597         u64 mask;
5598         enum transcoder transcoder = crtc_state->cpu_transcoder;
5599
5600         if (!crtc_state->base.active)
5601                 return 0;
5602
5603         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5604         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5605         if (crtc_state->pch_pfit.enabled ||
5606             crtc_state->pch_pfit.force_thru)
5607                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5608
5609         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5610                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5611
5612                 mask |= BIT_ULL(intel_encoder->power_domain);
5613         }
5614
5615         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5616                 mask |= BIT(POWER_DOMAIN_AUDIO);
5617
5618         if (crtc_state->shared_dpll)
5619                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5620
5621         return mask;
5622 }
5623
5624 static u64
5625 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5626                                struct intel_crtc_state *crtc_state)
5627 {
5628         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5630         enum intel_display_power_domain domain;
5631         u64 domains, new_domains, old_domains;
5632
5633         old_domains = intel_crtc->enabled_power_domains;
5634         intel_crtc->enabled_power_domains = new_domains =
5635                 get_crtc_power_domains(crtc, crtc_state);
5636
5637         domains = new_domains & ~old_domains;
5638
5639         for_each_power_domain(domain, domains)
5640                 intel_display_power_get(dev_priv, domain);
5641
5642         return old_domains & ~new_domains;
5643 }
5644
5645 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5646                                       u64 domains)
5647 {
5648         enum intel_display_power_domain domain;
5649
5650         for_each_power_domain(domain, domains)
5651                 intel_display_power_put(dev_priv, domain);
5652 }
5653
5654 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5655                                    struct drm_atomic_state *old_state)
5656 {
5657         struct intel_atomic_state *old_intel_state =
5658                 to_intel_atomic_state(old_state);
5659         struct drm_crtc *crtc = pipe_config->base.crtc;
5660         struct drm_device *dev = crtc->dev;
5661         struct drm_i915_private *dev_priv = to_i915(dev);
5662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5663         int pipe = intel_crtc->pipe;
5664
5665         if (WARN_ON(intel_crtc->active))
5666                 return;
5667
5668         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5669                 intel_dp_set_m_n(intel_crtc, M1_N1);
5670
5671         intel_set_pipe_timings(intel_crtc);
5672         intel_set_pipe_src_size(intel_crtc);
5673
5674         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5675                 struct drm_i915_private *dev_priv = to_i915(dev);
5676
5677                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5678                 I915_WRITE(CHV_CANVAS(pipe), 0);
5679         }
5680
5681         i9xx_set_pipeconf(intel_crtc);
5682
5683         intel_crtc->active = true;
5684
5685         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5686
5687         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5688
5689         if (IS_CHERRYVIEW(dev_priv)) {
5690                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5691                 chv_enable_pll(intel_crtc, intel_crtc->config);
5692         } else {
5693                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5694                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5695         }
5696
5697         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5698
5699         i9xx_pfit_enable(intel_crtc);
5700
5701         intel_color_load_luts(&pipe_config->base);
5702
5703         dev_priv->display.initial_watermarks(old_intel_state,
5704                                              pipe_config);
5705         intel_enable_pipe(intel_crtc);
5706
5707         assert_vblank_disabled(crtc);
5708         drm_crtc_vblank_on(crtc);
5709
5710         intel_encoders_enable(crtc, pipe_config, old_state);
5711 }
5712
5713 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5714 {
5715         struct drm_device *dev = crtc->base.dev;
5716         struct drm_i915_private *dev_priv = to_i915(dev);
5717
5718         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5719         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5720 }
5721
5722 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5723                              struct drm_atomic_state *old_state)
5724 {
5725         struct drm_crtc *crtc = pipe_config->base.crtc;
5726         struct drm_device *dev = crtc->dev;
5727         struct drm_i915_private *dev_priv = to_i915(dev);
5728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729         enum pipe pipe = intel_crtc->pipe;
5730
5731         if (WARN_ON(intel_crtc->active))
5732                 return;
5733
5734         i9xx_set_pll_dividers(intel_crtc);
5735
5736         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5737                 intel_dp_set_m_n(intel_crtc, M1_N1);
5738
5739         intel_set_pipe_timings(intel_crtc);
5740         intel_set_pipe_src_size(intel_crtc);
5741
5742         i9xx_set_pipeconf(intel_crtc);
5743
5744         intel_crtc->active = true;
5745
5746         if (!IS_GEN2(dev_priv))
5747                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5748
5749         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5750
5751         i9xx_enable_pll(intel_crtc);
5752
5753         i9xx_pfit_enable(intel_crtc);
5754
5755         intel_color_load_luts(&pipe_config->base);
5756
5757         intel_update_watermarks(intel_crtc);
5758         intel_enable_pipe(intel_crtc);
5759
5760         assert_vblank_disabled(crtc);
5761         drm_crtc_vblank_on(crtc);
5762
5763         intel_encoders_enable(crtc, pipe_config, old_state);
5764 }
5765
5766 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5767 {
5768         struct drm_device *dev = crtc->base.dev;
5769         struct drm_i915_private *dev_priv = to_i915(dev);
5770
5771         if (!crtc->config->gmch_pfit.control)
5772                 return;
5773
5774         assert_pipe_disabled(dev_priv, crtc->pipe);
5775
5776         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5777                          I915_READ(PFIT_CONTROL));
5778         I915_WRITE(PFIT_CONTROL, 0);
5779 }
5780
5781 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5782                               struct drm_atomic_state *old_state)
5783 {
5784         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5785         struct drm_device *dev = crtc->dev;
5786         struct drm_i915_private *dev_priv = to_i915(dev);
5787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5788         int pipe = intel_crtc->pipe;
5789
5790         /*
5791          * On gen2 planes are double buffered but the pipe isn't, so we must
5792          * wait for planes to fully turn off before disabling the pipe.
5793          */
5794         if (IS_GEN2(dev_priv))
5795                 intel_wait_for_vblank(dev_priv, pipe);
5796
5797         intel_encoders_disable(crtc, old_crtc_state, old_state);
5798
5799         drm_crtc_vblank_off(crtc);
5800         assert_vblank_disabled(crtc);
5801
5802         intel_disable_pipe(intel_crtc);
5803
5804         i9xx_pfit_disable(intel_crtc);
5805
5806         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5807
5808         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5809                 if (IS_CHERRYVIEW(dev_priv))
5810                         chv_disable_pll(dev_priv, pipe);
5811                 else if (IS_VALLEYVIEW(dev_priv))
5812                         vlv_disable_pll(dev_priv, pipe);
5813                 else
5814                         i9xx_disable_pll(intel_crtc);
5815         }
5816
5817         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5818
5819         if (!IS_GEN2(dev_priv))
5820                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5821
5822         if (!dev_priv->display.initial_watermarks)
5823                 intel_update_watermarks(intel_crtc);
5824 }
5825
5826 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5827 {
5828         struct intel_encoder *encoder;
5829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5830         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5831         enum intel_display_power_domain domain;
5832         u64 domains;
5833         struct drm_atomic_state *state;
5834         struct intel_crtc_state *crtc_state;
5835         int ret;
5836
5837         if (!intel_crtc->active)
5838                 return;
5839
5840         if (crtc->primary->state->visible) {
5841                 WARN_ON(intel_crtc->flip_work);
5842
5843                 intel_pre_disable_primary_noatomic(crtc);
5844
5845                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5846                 crtc->primary->state->visible = false;
5847         }
5848
5849         state = drm_atomic_state_alloc(crtc->dev);
5850         if (!state) {
5851                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5852                               crtc->base.id, crtc->name);
5853                 return;
5854         }
5855
5856         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5857
5858         /* Everything's already locked, -EDEADLK can't happen. */
5859         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5860         ret = drm_atomic_add_affected_connectors(state, crtc);
5861
5862         WARN_ON(IS_ERR(crtc_state) || ret);
5863
5864         dev_priv->display.crtc_disable(crtc_state, state);
5865
5866         drm_atomic_state_put(state);
5867
5868         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5869                       crtc->base.id, crtc->name);
5870
5871         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5872         crtc->state->active = false;
5873         intel_crtc->active = false;
5874         crtc->enabled = false;
5875         crtc->state->connector_mask = 0;
5876         crtc->state->encoder_mask = 0;
5877
5878         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5879                 encoder->base.crtc = NULL;
5880
5881         intel_fbc_disable(intel_crtc);
5882         intel_update_watermarks(intel_crtc);
5883         intel_disable_shared_dpll(intel_crtc);
5884
5885         domains = intel_crtc->enabled_power_domains;
5886         for_each_power_domain(domain, domains)
5887                 intel_display_power_put(dev_priv, domain);
5888         intel_crtc->enabled_power_domains = 0;
5889
5890         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5891         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5892 }
5893
5894 /*
5895  * turn all crtc's off, but do not adjust state
5896  * This has to be paired with a call to intel_modeset_setup_hw_state.
5897  */
5898 int intel_display_suspend(struct drm_device *dev)
5899 {
5900         struct drm_i915_private *dev_priv = to_i915(dev);
5901         struct drm_atomic_state *state;
5902         int ret;
5903
5904         state = drm_atomic_helper_suspend(dev);
5905         ret = PTR_ERR_OR_ZERO(state);
5906         if (ret)
5907                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5908         else
5909                 dev_priv->modeset_restore_state = state;
5910         return ret;
5911 }
5912
5913 void intel_encoder_destroy(struct drm_encoder *encoder)
5914 {
5915         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5916
5917         drm_encoder_cleanup(encoder);
5918         kfree(intel_encoder);
5919 }
5920
5921 /* Cross check the actual hw state with our own modeset state tracking (and it's
5922  * internal consistency). */
5923 static void intel_connector_verify_state(struct intel_connector *connector)
5924 {
5925         struct drm_crtc *crtc = connector->base.state->crtc;
5926
5927         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5928                       connector->base.base.id,
5929                       connector->base.name);
5930
5931         if (connector->get_hw_state(connector)) {
5932                 struct intel_encoder *encoder = connector->encoder;
5933                 struct drm_connector_state *conn_state = connector->base.state;
5934
5935                 I915_STATE_WARN(!crtc,
5936                          "connector enabled without attached crtc\n");
5937
5938                 if (!crtc)
5939                         return;
5940
5941                 I915_STATE_WARN(!crtc->state->active,
5942                       "connector is active, but attached crtc isn't\n");
5943
5944                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5945                         return;
5946
5947                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5948                         "atomic encoder doesn't match attached encoder\n");
5949
5950                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5951                         "attached encoder crtc differs from connector crtc\n");
5952         } else {
5953                 I915_STATE_WARN(crtc && crtc->state->active,
5954                         "attached crtc is active, but connector isn't\n");
5955                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5956                         "best encoder set without crtc!\n");
5957         }
5958 }
5959
5960 int intel_connector_init(struct intel_connector *connector)
5961 {
5962         drm_atomic_helper_connector_reset(&connector->base);
5963
5964         if (!connector->base.state)
5965                 return -ENOMEM;
5966
5967         return 0;
5968 }
5969
5970 struct intel_connector *intel_connector_alloc(void)
5971 {
5972         struct intel_connector *connector;
5973
5974         connector = kzalloc(sizeof *connector, GFP_KERNEL);
5975         if (!connector)
5976                 return NULL;
5977
5978         if (intel_connector_init(connector) < 0) {
5979                 kfree(connector);
5980                 return NULL;
5981         }
5982
5983         return connector;
5984 }
5985
5986 /* Simple connector->get_hw_state implementation for encoders that support only
5987  * one connector and no cloning and hence the encoder state determines the state
5988  * of the connector. */
5989 bool intel_connector_get_hw_state(struct intel_connector *connector)
5990 {
5991         enum pipe pipe = 0;
5992         struct intel_encoder *encoder = connector->encoder;
5993
5994         return encoder->get_hw_state(encoder, &pipe);
5995 }
5996
5997 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
5998 {
5999         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6000                 return crtc_state->fdi_lanes;
6001
6002         return 0;
6003 }
6004
6005 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6006                                      struct intel_crtc_state *pipe_config)
6007 {
6008         struct drm_i915_private *dev_priv = to_i915(dev);
6009         struct drm_atomic_state *state = pipe_config->base.state;
6010         struct intel_crtc *other_crtc;
6011         struct intel_crtc_state *other_crtc_state;
6012
6013         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6014                       pipe_name(pipe), pipe_config->fdi_lanes);
6015         if (pipe_config->fdi_lanes > 4) {
6016                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6017                               pipe_name(pipe), pipe_config->fdi_lanes);
6018                 return -EINVAL;
6019         }
6020
6021         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6022                 if (pipe_config->fdi_lanes > 2) {
6023                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6024                                       pipe_config->fdi_lanes);
6025                         return -EINVAL;
6026                 } else {
6027                         return 0;
6028                 }
6029         }
6030
6031         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6032                 return 0;
6033
6034         /* Ivybridge 3 pipe is really complicated */
6035         switch (pipe) {
6036         case PIPE_A:
6037                 return 0;
6038         case PIPE_B:
6039                 if (pipe_config->fdi_lanes <= 2)
6040                         return 0;
6041
6042                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6043                 other_crtc_state =
6044                         intel_atomic_get_crtc_state(state, other_crtc);
6045                 if (IS_ERR(other_crtc_state))
6046                         return PTR_ERR(other_crtc_state);
6047
6048                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6049                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6050                                       pipe_name(pipe), pipe_config->fdi_lanes);
6051                         return -EINVAL;
6052                 }
6053                 return 0;
6054         case PIPE_C:
6055                 if (pipe_config->fdi_lanes > 2) {
6056                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6057                                       pipe_name(pipe), pipe_config->fdi_lanes);
6058                         return -EINVAL;
6059                 }
6060
6061                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6062                 other_crtc_state =
6063                         intel_atomic_get_crtc_state(state, other_crtc);
6064                 if (IS_ERR(other_crtc_state))
6065                         return PTR_ERR(other_crtc_state);
6066
6067                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6068                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6069                         return -EINVAL;
6070                 }
6071                 return 0;
6072         default:
6073                 BUG();
6074         }
6075 }
6076
6077 #define RETRY 1
6078 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6079                                        struct intel_crtc_state *pipe_config)
6080 {
6081         struct drm_device *dev = intel_crtc->base.dev;
6082         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6083         int lane, link_bw, fdi_dotclock, ret;
6084         bool needs_recompute = false;
6085
6086 retry:
6087         /* FDI is a binary signal running at ~2.7GHz, encoding
6088          * each output octet as 10 bits. The actual frequency
6089          * is stored as a divider into a 100MHz clock, and the
6090          * mode pixel clock is stored in units of 1KHz.
6091          * Hence the bw of each lane in terms of the mode signal
6092          * is:
6093          */
6094         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6095
6096         fdi_dotclock = adjusted_mode->crtc_clock;
6097
6098         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6099                                            pipe_config->pipe_bpp);
6100
6101         pipe_config->fdi_lanes = lane;
6102
6103         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6104                                link_bw, &pipe_config->fdi_m_n, false);
6105
6106         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6107         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6108                 pipe_config->pipe_bpp -= 2*3;
6109                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6110                               pipe_config->pipe_bpp);
6111                 needs_recompute = true;
6112                 pipe_config->bw_constrained = true;
6113
6114                 goto retry;
6115         }
6116
6117         if (needs_recompute)
6118                 return RETRY;
6119
6120         return ret;
6121 }
6122
6123 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6124                                      struct intel_crtc_state *pipe_config)
6125 {
6126         if (pipe_config->pipe_bpp > 24)
6127                 return false;
6128
6129         /* HSW can handle pixel rate up to cdclk? */
6130         if (IS_HASWELL(dev_priv))
6131                 return true;
6132
6133         /*
6134          * We compare against max which means we must take
6135          * the increased cdclk requirement into account when
6136          * calculating the new cdclk.
6137          *
6138          * Should measure whether using a lower cdclk w/o IPS
6139          */
6140         return pipe_config->pixel_rate <=
6141                 dev_priv->max_cdclk_freq * 95 / 100;
6142 }
6143
6144 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6145                                    struct intel_crtc_state *pipe_config)
6146 {
6147         struct drm_device *dev = crtc->base.dev;
6148         struct drm_i915_private *dev_priv = to_i915(dev);
6149
6150         pipe_config->ips_enabled = i915.enable_ips &&
6151                 hsw_crtc_supports_ips(crtc) &&
6152                 pipe_config_supports_ips(dev_priv, pipe_config);
6153 }
6154
6155 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6156 {
6157         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6158
6159         /* GDG double wide on either pipe, otherwise pipe A only */
6160         return INTEL_INFO(dev_priv)->gen < 4 &&
6161                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6162 }
6163
6164 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6165 {
6166         uint32_t pixel_rate;
6167
6168         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6169
6170         /*
6171          * We only use IF-ID interlacing. If we ever use
6172          * PF-ID we'll need to adjust the pixel_rate here.
6173          */
6174
6175         if (pipe_config->pch_pfit.enabled) {
6176                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6177                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6178
6179                 pipe_w = pipe_config->pipe_src_w;
6180                 pipe_h = pipe_config->pipe_src_h;
6181
6182                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6183                 pfit_h = pfit_size & 0xFFFF;
6184                 if (pipe_w < pfit_w)
6185                         pipe_w = pfit_w;
6186                 if (pipe_h < pfit_h)
6187                         pipe_h = pfit_h;
6188
6189                 if (WARN_ON(!pfit_w || !pfit_h))
6190                         return pixel_rate;
6191
6192                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6193                                      pfit_w * pfit_h);
6194         }
6195
6196         return pixel_rate;
6197 }
6198
6199 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6200 {
6201         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6202
6203         if (HAS_GMCH_DISPLAY(dev_priv))
6204                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6205                 crtc_state->pixel_rate =
6206                         crtc_state->base.adjusted_mode.crtc_clock;
6207         else
6208                 crtc_state->pixel_rate =
6209                         ilk_pipe_pixel_rate(crtc_state);
6210 }
6211
6212 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6213                                      struct intel_crtc_state *pipe_config)
6214 {
6215         struct drm_device *dev = crtc->base.dev;
6216         struct drm_i915_private *dev_priv = to_i915(dev);
6217         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6218         int clock_limit = dev_priv->max_dotclk_freq;
6219
6220         if (INTEL_GEN(dev_priv) < 4) {
6221                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6222
6223                 /*
6224                  * Enable double wide mode when the dot clock
6225                  * is > 90% of the (display) core speed.
6226                  */
6227                 if (intel_crtc_supports_double_wide(crtc) &&
6228                     adjusted_mode->crtc_clock > clock_limit) {
6229                         clock_limit = dev_priv->max_dotclk_freq;
6230                         pipe_config->double_wide = true;
6231                 }
6232         }
6233
6234         if (adjusted_mode->crtc_clock > clock_limit) {
6235                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6236                               adjusted_mode->crtc_clock, clock_limit,
6237                               yesno(pipe_config->double_wide));
6238                 return -EINVAL;
6239         }
6240
6241         /*
6242          * Pipe horizontal size must be even in:
6243          * - DVO ganged mode
6244          * - LVDS dual channel mode
6245          * - Double wide pipe
6246          */
6247         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6248              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6249                 pipe_config->pipe_src_w &= ~1;
6250
6251         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6252          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6253          */
6254         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6255                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6256                 return -EINVAL;
6257
6258         intel_crtc_compute_pixel_rate(pipe_config);
6259
6260         if (HAS_IPS(dev_priv))
6261                 hsw_compute_ips_config(crtc, pipe_config);
6262
6263         if (pipe_config->has_pch_encoder)
6264                 return ironlake_fdi_compute_config(crtc, pipe_config);
6265
6266         return 0;
6267 }
6268
6269 static void
6270 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6271 {
6272         while (*num > DATA_LINK_M_N_MASK ||
6273                *den > DATA_LINK_M_N_MASK) {
6274                 *num >>= 1;
6275                 *den >>= 1;
6276         }
6277 }
6278
6279 static void compute_m_n(unsigned int m, unsigned int n,
6280                         uint32_t *ret_m, uint32_t *ret_n,
6281                         bool reduce_m_n)
6282 {
6283         /*
6284          * Reduce M/N as much as possible without loss in precision. Several DP
6285          * dongles in particular seem to be fussy about too large *link* M/N
6286          * values. The passed in values are more likely to have the least
6287          * significant bits zero than M after rounding below, so do this first.
6288          */
6289         if (reduce_m_n) {
6290                 while ((m & 1) == 0 && (n & 1) == 0) {
6291                         m >>= 1;
6292                         n >>= 1;
6293                 }
6294         }
6295
6296         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6297         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6298         intel_reduce_m_n_ratio(ret_m, ret_n);
6299 }
6300
6301 void
6302 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6303                        int pixel_clock, int link_clock,
6304                        struct intel_link_m_n *m_n,
6305                        bool reduce_m_n)
6306 {
6307         m_n->tu = 64;
6308
6309         compute_m_n(bits_per_pixel * pixel_clock,
6310                     link_clock * nlanes * 8,
6311                     &m_n->gmch_m, &m_n->gmch_n,
6312                     reduce_m_n);
6313
6314         compute_m_n(pixel_clock, link_clock,
6315                     &m_n->link_m, &m_n->link_n,
6316                     reduce_m_n);
6317 }
6318
6319 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6320 {
6321         if (i915.panel_use_ssc >= 0)
6322                 return i915.panel_use_ssc != 0;
6323         return dev_priv->vbt.lvds_use_ssc
6324                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6325 }
6326
6327 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6328 {
6329         return (1 << dpll->n) << 16 | dpll->m2;
6330 }
6331
6332 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6333 {
6334         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6335 }
6336
6337 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6338                                      struct intel_crtc_state *crtc_state,
6339                                      struct dpll *reduced_clock)
6340 {
6341         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6342         u32 fp, fp2 = 0;
6343
6344         if (IS_PINEVIEW(dev_priv)) {
6345                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6346                 if (reduced_clock)
6347                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6348         } else {
6349                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6350                 if (reduced_clock)
6351                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6352         }
6353
6354         crtc_state->dpll_hw_state.fp0 = fp;
6355
6356         crtc->lowfreq_avail = false;
6357         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6358             reduced_clock) {
6359                 crtc_state->dpll_hw_state.fp1 = fp2;
6360                 crtc->lowfreq_avail = true;
6361         } else {
6362                 crtc_state->dpll_hw_state.fp1 = fp;
6363         }
6364 }
6365
6366 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6367                 pipe)
6368 {
6369         u32 reg_val;
6370
6371         /*
6372          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6373          * and set it to a reasonable value instead.
6374          */
6375         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6376         reg_val &= 0xffffff00;
6377         reg_val |= 0x00000030;
6378         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6379
6380         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6381         reg_val &= 0x8cffffff;
6382         reg_val = 0x8c000000;
6383         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6384
6385         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6386         reg_val &= 0xffffff00;
6387         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6388
6389         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6390         reg_val &= 0x00ffffff;
6391         reg_val |= 0xb0000000;
6392         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6393 }
6394
6395 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6396                                          struct intel_link_m_n *m_n)
6397 {
6398         struct drm_device *dev = crtc->base.dev;
6399         struct drm_i915_private *dev_priv = to_i915(dev);
6400         int pipe = crtc->pipe;
6401
6402         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6403         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6404         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6405         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6406 }
6407
6408 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6409                                          struct intel_link_m_n *m_n,
6410                                          struct intel_link_m_n *m2_n2)
6411 {
6412         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6413         int pipe = crtc->pipe;
6414         enum transcoder transcoder = crtc->config->cpu_transcoder;
6415
6416         if (INTEL_GEN(dev_priv) >= 5) {
6417                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6418                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6419                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6420                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6421                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6422                  * for gen < 8) and if DRRS is supported (to make sure the
6423                  * registers are not unnecessarily accessed).
6424                  */
6425                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6426                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6427                         I915_WRITE(PIPE_DATA_M2(transcoder),
6428                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6429                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6430                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6431                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6432                 }
6433         } else {
6434                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6435                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6436                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6437                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6438         }
6439 }
6440
6441 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6442 {
6443         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6444
6445         if (m_n == M1_N1) {
6446                 dp_m_n = &crtc->config->dp_m_n;
6447                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6448         } else if (m_n == M2_N2) {
6449
6450                 /*
6451                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6452                  * needs to be programmed into M1_N1.
6453                  */
6454                 dp_m_n = &crtc->config->dp_m2_n2;
6455         } else {
6456                 DRM_ERROR("Unsupported divider value\n");
6457                 return;
6458         }
6459
6460         if (crtc->config->has_pch_encoder)
6461                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6462         else
6463                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6464 }
6465
6466 static void vlv_compute_dpll(struct intel_crtc *crtc,
6467                              struct intel_crtc_state *pipe_config)
6468 {
6469         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6470                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6471         if (crtc->pipe != PIPE_A)
6472                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6473
6474         /* DPLL not used with DSI, but still need the rest set up */
6475         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6476                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6477                         DPLL_EXT_BUFFER_ENABLE_VLV;
6478
6479         pipe_config->dpll_hw_state.dpll_md =
6480                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6481 }
6482
6483 static void chv_compute_dpll(struct intel_crtc *crtc,
6484                              struct intel_crtc_state *pipe_config)
6485 {
6486         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6487                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6488         if (crtc->pipe != PIPE_A)
6489                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6490
6491         /* DPLL not used with DSI, but still need the rest set up */
6492         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6493                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6494
6495         pipe_config->dpll_hw_state.dpll_md =
6496                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6497 }
6498
6499 static void vlv_prepare_pll(struct intel_crtc *crtc,
6500                             const struct intel_crtc_state *pipe_config)
6501 {
6502         struct drm_device *dev = crtc->base.dev;
6503         struct drm_i915_private *dev_priv = to_i915(dev);
6504         enum pipe pipe = crtc->pipe;
6505         u32 mdiv;
6506         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6507         u32 coreclk, reg_val;
6508
6509         /* Enable Refclk */
6510         I915_WRITE(DPLL(pipe),
6511                    pipe_config->dpll_hw_state.dpll &
6512                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6513
6514         /* No need to actually set up the DPLL with DSI */
6515         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6516                 return;
6517
6518         mutex_lock(&dev_priv->sb_lock);
6519
6520         bestn = pipe_config->dpll.n;
6521         bestm1 = pipe_config->dpll.m1;
6522         bestm2 = pipe_config->dpll.m2;
6523         bestp1 = pipe_config->dpll.p1;
6524         bestp2 = pipe_config->dpll.p2;
6525
6526         /* See eDP HDMI DPIO driver vbios notes doc */
6527
6528         /* PLL B needs special handling */
6529         if (pipe == PIPE_B)
6530                 vlv_pllb_recal_opamp(dev_priv, pipe);
6531
6532         /* Set up Tx target for periodic Rcomp update */
6533         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6534
6535         /* Disable target IRef on PLL */
6536         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6537         reg_val &= 0x00ffffff;
6538         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6539
6540         /* Disable fast lock */
6541         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6542
6543         /* Set idtafcrecal before PLL is enabled */
6544         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6545         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6546         mdiv |= ((bestn << DPIO_N_SHIFT));
6547         mdiv |= (1 << DPIO_K_SHIFT);
6548
6549         /*
6550          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6551          * but we don't support that).
6552          * Note: don't use the DAC post divider as it seems unstable.
6553          */
6554         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6555         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6556
6557         mdiv |= DPIO_ENABLE_CALIBRATION;
6558         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6559
6560         /* Set HBR and RBR LPF coefficients */
6561         if (pipe_config->port_clock == 162000 ||
6562             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6563             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6564                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6565                                  0x009f0003);
6566         else
6567                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6568                                  0x00d0000f);
6569
6570         if (intel_crtc_has_dp_encoder(pipe_config)) {
6571                 /* Use SSC source */
6572                 if (pipe == PIPE_A)
6573                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6574                                          0x0df40000);
6575                 else
6576                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6577                                          0x0df70000);
6578         } else { /* HDMI or VGA */
6579                 /* Use bend source */
6580                 if (pipe == PIPE_A)
6581                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6582                                          0x0df70000);
6583                 else
6584                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6585                                          0x0df40000);
6586         }
6587
6588         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6589         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6590         if (intel_crtc_has_dp_encoder(crtc->config))
6591                 coreclk |= 0x01000000;
6592         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6593
6594         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6595         mutex_unlock(&dev_priv->sb_lock);
6596 }
6597
6598 static void chv_prepare_pll(struct intel_crtc *crtc,
6599                             const struct intel_crtc_state *pipe_config)
6600 {
6601         struct drm_device *dev = crtc->base.dev;
6602         struct drm_i915_private *dev_priv = to_i915(dev);
6603         enum pipe pipe = crtc->pipe;
6604         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6605         u32 loopfilter, tribuf_calcntr;
6606         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6607         u32 dpio_val;
6608         int vco;
6609
6610         /* Enable Refclk and SSC */
6611         I915_WRITE(DPLL(pipe),
6612                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6613
6614         /* No need to actually set up the DPLL with DSI */
6615         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6616                 return;
6617
6618         bestn = pipe_config->dpll.n;
6619         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6620         bestm1 = pipe_config->dpll.m1;
6621         bestm2 = pipe_config->dpll.m2 >> 22;
6622         bestp1 = pipe_config->dpll.p1;
6623         bestp2 = pipe_config->dpll.p2;
6624         vco = pipe_config->dpll.vco;
6625         dpio_val = 0;
6626         loopfilter = 0;
6627
6628         mutex_lock(&dev_priv->sb_lock);
6629
6630         /* p1 and p2 divider */
6631         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6632                         5 << DPIO_CHV_S1_DIV_SHIFT |
6633                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6634                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6635                         1 << DPIO_CHV_K_DIV_SHIFT);
6636
6637         /* Feedback post-divider - m2 */
6638         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6639
6640         /* Feedback refclk divider - n and m1 */
6641         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6642                         DPIO_CHV_M1_DIV_BY_2 |
6643                         1 << DPIO_CHV_N_DIV_SHIFT);
6644
6645         /* M2 fraction division */
6646         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6647
6648         /* M2 fraction division enable */
6649         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6650         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6651         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6652         if (bestm2_frac)
6653                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6654         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6655
6656         /* Program digital lock detect threshold */
6657         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6658         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6659                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6660         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6661         if (!bestm2_frac)
6662                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6663         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6664
6665         /* Loop filter */
6666         if (vco == 5400000) {
6667                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6668                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6669                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6670                 tribuf_calcntr = 0x9;
6671         } else if (vco <= 6200000) {
6672                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6673                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6674                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6675                 tribuf_calcntr = 0x9;
6676         } else if (vco <= 6480000) {
6677                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6678                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6679                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6680                 tribuf_calcntr = 0x8;
6681         } else {
6682                 /* Not supported. Apply the same limits as in the max case */
6683                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6684                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6685                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6686                 tribuf_calcntr = 0;
6687         }
6688         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6689
6690         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6691         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6692         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6693         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6694
6695         /* AFC Recal */
6696         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6697                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6698                         DPIO_AFC_RECAL);
6699
6700         mutex_unlock(&dev_priv->sb_lock);
6701 }
6702
6703 /**
6704  * vlv_force_pll_on - forcibly enable just the PLL
6705  * @dev_priv: i915 private structure
6706  * @pipe: pipe PLL to enable
6707  * @dpll: PLL configuration
6708  *
6709  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6710  * in cases where we need the PLL enabled even when @pipe is not going to
6711  * be enabled.
6712  */
6713 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6714                      const struct dpll *dpll)
6715 {
6716         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6717         struct intel_crtc_state *pipe_config;
6718
6719         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6720         if (!pipe_config)
6721                 return -ENOMEM;
6722
6723         pipe_config->base.crtc = &crtc->base;
6724         pipe_config->pixel_multiplier = 1;
6725         pipe_config->dpll = *dpll;
6726
6727         if (IS_CHERRYVIEW(dev_priv)) {
6728                 chv_compute_dpll(crtc, pipe_config);
6729                 chv_prepare_pll(crtc, pipe_config);
6730                 chv_enable_pll(crtc, pipe_config);
6731         } else {
6732                 vlv_compute_dpll(crtc, pipe_config);
6733                 vlv_prepare_pll(crtc, pipe_config);
6734                 vlv_enable_pll(crtc, pipe_config);
6735         }
6736
6737         kfree(pipe_config);
6738
6739         return 0;
6740 }
6741
6742 /**
6743  * vlv_force_pll_off - forcibly disable just the PLL
6744  * @dev_priv: i915 private structure
6745  * @pipe: pipe PLL to disable
6746  *
6747  * Disable the PLL for @pipe. To be used in cases where we need
6748  * the PLL enabled even when @pipe is not going to be enabled.
6749  */
6750 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6751 {
6752         if (IS_CHERRYVIEW(dev_priv))
6753                 chv_disable_pll(dev_priv, pipe);
6754         else
6755                 vlv_disable_pll(dev_priv, pipe);
6756 }
6757
6758 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6759                               struct intel_crtc_state *crtc_state,
6760                               struct dpll *reduced_clock)
6761 {
6762         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6763         u32 dpll;
6764         struct dpll *clock = &crtc_state->dpll;
6765
6766         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6767
6768         dpll = DPLL_VGA_MODE_DIS;
6769
6770         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6771                 dpll |= DPLLB_MODE_LVDS;
6772         else
6773                 dpll |= DPLLB_MODE_DAC_SERIAL;
6774
6775         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6776             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6777                 dpll |= (crtc_state->pixel_multiplier - 1)
6778                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6779         }
6780
6781         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6782             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6783                 dpll |= DPLL_SDVO_HIGH_SPEED;
6784
6785         if (intel_crtc_has_dp_encoder(crtc_state))
6786                 dpll |= DPLL_SDVO_HIGH_SPEED;
6787
6788         /* compute bitmask from p1 value */
6789         if (IS_PINEVIEW(dev_priv))
6790                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6791         else {
6792                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6793                 if (IS_G4X(dev_priv) && reduced_clock)
6794                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6795         }
6796         switch (clock->p2) {
6797         case 5:
6798                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6799                 break;
6800         case 7:
6801                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6802                 break;
6803         case 10:
6804                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6805                 break;
6806         case 14:
6807                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6808                 break;
6809         }
6810         if (INTEL_GEN(dev_priv) >= 4)
6811                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6812
6813         if (crtc_state->sdvo_tv_clock)
6814                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6815         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6816                  intel_panel_use_ssc(dev_priv))
6817                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6818         else
6819                 dpll |= PLL_REF_INPUT_DREFCLK;
6820
6821         dpll |= DPLL_VCO_ENABLE;
6822         crtc_state->dpll_hw_state.dpll = dpll;
6823
6824         if (INTEL_GEN(dev_priv) >= 4) {
6825                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6826                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6827                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6828         }
6829 }
6830
6831 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6832                               struct intel_crtc_state *crtc_state,
6833                               struct dpll *reduced_clock)
6834 {
6835         struct drm_device *dev = crtc->base.dev;
6836         struct drm_i915_private *dev_priv = to_i915(dev);
6837         u32 dpll;
6838         struct dpll *clock = &crtc_state->dpll;
6839
6840         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6841
6842         dpll = DPLL_VGA_MODE_DIS;
6843
6844         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6845                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6846         } else {
6847                 if (clock->p1 == 2)
6848                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6849                 else
6850                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6851                 if (clock->p2 == 4)
6852                         dpll |= PLL_P2_DIVIDE_BY_4;
6853         }
6854
6855         if (!IS_I830(dev_priv) &&
6856             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6857                 dpll |= DPLL_DVO_2X_MODE;
6858
6859         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6860             intel_panel_use_ssc(dev_priv))
6861                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6862         else
6863                 dpll |= PLL_REF_INPUT_DREFCLK;
6864
6865         dpll |= DPLL_VCO_ENABLE;
6866         crtc_state->dpll_hw_state.dpll = dpll;
6867 }
6868
6869 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6870 {
6871         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6872         enum pipe pipe = intel_crtc->pipe;
6873         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6874         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6875         uint32_t crtc_vtotal, crtc_vblank_end;
6876         int vsyncshift = 0;
6877
6878         /* We need to be careful not to changed the adjusted mode, for otherwise
6879          * the hw state checker will get angry at the mismatch. */
6880         crtc_vtotal = adjusted_mode->crtc_vtotal;
6881         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6882
6883         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6884                 /* the chip adds 2 halflines automatically */
6885                 crtc_vtotal -= 1;
6886                 crtc_vblank_end -= 1;
6887
6888                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6889                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6890                 else
6891                         vsyncshift = adjusted_mode->crtc_hsync_start -
6892                                 adjusted_mode->crtc_htotal / 2;
6893                 if (vsyncshift < 0)
6894                         vsyncshift += adjusted_mode->crtc_htotal;
6895         }
6896
6897         if (INTEL_GEN(dev_priv) > 3)
6898                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6899
6900         I915_WRITE(HTOTAL(cpu_transcoder),
6901                    (adjusted_mode->crtc_hdisplay - 1) |
6902                    ((adjusted_mode->crtc_htotal - 1) << 16));
6903         I915_WRITE(HBLANK(cpu_transcoder),
6904                    (adjusted_mode->crtc_hblank_start - 1) |
6905                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6906         I915_WRITE(HSYNC(cpu_transcoder),
6907                    (adjusted_mode->crtc_hsync_start - 1) |
6908                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6909
6910         I915_WRITE(VTOTAL(cpu_transcoder),
6911                    (adjusted_mode->crtc_vdisplay - 1) |
6912                    ((crtc_vtotal - 1) << 16));
6913         I915_WRITE(VBLANK(cpu_transcoder),
6914                    (adjusted_mode->crtc_vblank_start - 1) |
6915                    ((crtc_vblank_end - 1) << 16));
6916         I915_WRITE(VSYNC(cpu_transcoder),
6917                    (adjusted_mode->crtc_vsync_start - 1) |
6918                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6919
6920         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6921          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6922          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6923          * bits. */
6924         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6925             (pipe == PIPE_B || pipe == PIPE_C))
6926                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6927
6928 }
6929
6930 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6931 {
6932         struct drm_device *dev = intel_crtc->base.dev;
6933         struct drm_i915_private *dev_priv = to_i915(dev);
6934         enum pipe pipe = intel_crtc->pipe;
6935
6936         /* pipesrc controls the size that is scaled from, which should
6937          * always be the user's requested size.
6938          */
6939         I915_WRITE(PIPESRC(pipe),
6940                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6941                    (intel_crtc->config->pipe_src_h - 1));
6942 }
6943
6944 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6945                                    struct intel_crtc_state *pipe_config)
6946 {
6947         struct drm_device *dev = crtc->base.dev;
6948         struct drm_i915_private *dev_priv = to_i915(dev);
6949         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6950         uint32_t tmp;
6951
6952         tmp = I915_READ(HTOTAL(cpu_transcoder));
6953         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6954         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6955         tmp = I915_READ(HBLANK(cpu_transcoder));
6956         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6957         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6958         tmp = I915_READ(HSYNC(cpu_transcoder));
6959         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6960         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6961
6962         tmp = I915_READ(VTOTAL(cpu_transcoder));
6963         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6964         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6965         tmp = I915_READ(VBLANK(cpu_transcoder));
6966         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6967         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6968         tmp = I915_READ(VSYNC(cpu_transcoder));
6969         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6970         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6971
6972         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6973                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6974                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6975                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6976         }
6977 }
6978
6979 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6980                                     struct intel_crtc_state *pipe_config)
6981 {
6982         struct drm_device *dev = crtc->base.dev;
6983         struct drm_i915_private *dev_priv = to_i915(dev);
6984         u32 tmp;
6985
6986         tmp = I915_READ(PIPESRC(crtc->pipe));
6987         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6988         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6989
6990         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6991         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6992 }
6993
6994 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6995                                  struct intel_crtc_state *pipe_config)
6996 {
6997         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6998         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6999         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7000         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7001
7002         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7003         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7004         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7005         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7006
7007         mode->flags = pipe_config->base.adjusted_mode.flags;
7008         mode->type = DRM_MODE_TYPE_DRIVER;
7009
7010         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7011
7012         mode->hsync = drm_mode_hsync(mode);
7013         mode->vrefresh = drm_mode_vrefresh(mode);
7014         drm_mode_set_name(mode);
7015 }
7016
7017 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7018 {
7019         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7020         uint32_t pipeconf;
7021
7022         pipeconf = 0;
7023
7024         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7025             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7026                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7027
7028         if (intel_crtc->config->double_wide)
7029                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7030
7031         /* only g4x and later have fancy bpc/dither controls */
7032         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7033             IS_CHERRYVIEW(dev_priv)) {
7034                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7035                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7036                         pipeconf |= PIPECONF_DITHER_EN |
7037                                     PIPECONF_DITHER_TYPE_SP;
7038
7039                 switch (intel_crtc->config->pipe_bpp) {
7040                 case 18:
7041                         pipeconf |= PIPECONF_6BPC;
7042                         break;
7043                 case 24:
7044                         pipeconf |= PIPECONF_8BPC;
7045                         break;
7046                 case 30:
7047                         pipeconf |= PIPECONF_10BPC;
7048                         break;
7049                 default:
7050                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7051                         BUG();
7052                 }
7053         }
7054
7055         if (HAS_PIPE_CXSR(dev_priv)) {
7056                 if (intel_crtc->lowfreq_avail) {
7057                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7058                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7059                 } else {
7060                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7061                 }
7062         }
7063
7064         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7065                 if (INTEL_GEN(dev_priv) < 4 ||
7066                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7067                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7068                 else
7069                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7070         } else
7071                 pipeconf |= PIPECONF_PROGRESSIVE;
7072
7073         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7074              intel_crtc->config->limited_color_range)
7075                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7076
7077         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7078         POSTING_READ(PIPECONF(intel_crtc->pipe));
7079 }
7080
7081 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7082                                    struct intel_crtc_state *crtc_state)
7083 {
7084         struct drm_device *dev = crtc->base.dev;
7085         struct drm_i915_private *dev_priv = to_i915(dev);
7086         const struct intel_limit *limit;
7087         int refclk = 48000;
7088
7089         memset(&crtc_state->dpll_hw_state, 0,
7090                sizeof(crtc_state->dpll_hw_state));
7091
7092         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7093                 if (intel_panel_use_ssc(dev_priv)) {
7094                         refclk = dev_priv->vbt.lvds_ssc_freq;
7095                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7096                 }
7097
7098                 limit = &intel_limits_i8xx_lvds;
7099         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7100                 limit = &intel_limits_i8xx_dvo;
7101         } else {
7102                 limit = &intel_limits_i8xx_dac;
7103         }
7104
7105         if (!crtc_state->clock_set &&
7106             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7107                                  refclk, NULL, &crtc_state->dpll)) {
7108                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7109                 return -EINVAL;
7110         }
7111
7112         i8xx_compute_dpll(crtc, crtc_state, NULL);
7113
7114         return 0;
7115 }
7116
7117 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7118                                   struct intel_crtc_state *crtc_state)
7119 {
7120         struct drm_device *dev = crtc->base.dev;
7121         struct drm_i915_private *dev_priv = to_i915(dev);
7122         const struct intel_limit *limit;
7123         int refclk = 96000;
7124
7125         memset(&crtc_state->dpll_hw_state, 0,
7126                sizeof(crtc_state->dpll_hw_state));
7127
7128         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7129                 if (intel_panel_use_ssc(dev_priv)) {
7130                         refclk = dev_priv->vbt.lvds_ssc_freq;
7131                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7132                 }
7133
7134                 if (intel_is_dual_link_lvds(dev))
7135                         limit = &intel_limits_g4x_dual_channel_lvds;
7136                 else
7137                         limit = &intel_limits_g4x_single_channel_lvds;
7138         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7139                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7140                 limit = &intel_limits_g4x_hdmi;
7141         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7142                 limit = &intel_limits_g4x_sdvo;
7143         } else {
7144                 /* The option is for other outputs */
7145                 limit = &intel_limits_i9xx_sdvo;
7146         }
7147
7148         if (!crtc_state->clock_set &&
7149             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7150                                 refclk, NULL, &crtc_state->dpll)) {
7151                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7152                 return -EINVAL;
7153         }
7154
7155         i9xx_compute_dpll(crtc, crtc_state, NULL);
7156
7157         return 0;
7158 }
7159
7160 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7161                                   struct intel_crtc_state *crtc_state)
7162 {
7163         struct drm_device *dev = crtc->base.dev;
7164         struct drm_i915_private *dev_priv = to_i915(dev);
7165         const struct intel_limit *limit;
7166         int refclk = 96000;
7167
7168         memset(&crtc_state->dpll_hw_state, 0,
7169                sizeof(crtc_state->dpll_hw_state));
7170
7171         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7172                 if (intel_panel_use_ssc(dev_priv)) {
7173                         refclk = dev_priv->vbt.lvds_ssc_freq;
7174                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7175                 }
7176
7177                 limit = &intel_limits_pineview_lvds;
7178         } else {
7179                 limit = &intel_limits_pineview_sdvo;
7180         }
7181
7182         if (!crtc_state->clock_set &&
7183             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7184                                 refclk, NULL, &crtc_state->dpll)) {
7185                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7186                 return -EINVAL;
7187         }
7188
7189         i9xx_compute_dpll(crtc, crtc_state, NULL);
7190
7191         return 0;
7192 }
7193
7194 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7195                                    struct intel_crtc_state *crtc_state)
7196 {
7197         struct drm_device *dev = crtc->base.dev;
7198         struct drm_i915_private *dev_priv = to_i915(dev);
7199         const struct intel_limit *limit;
7200         int refclk = 96000;
7201
7202         memset(&crtc_state->dpll_hw_state, 0,
7203                sizeof(crtc_state->dpll_hw_state));
7204
7205         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7206                 if (intel_panel_use_ssc(dev_priv)) {
7207                         refclk = dev_priv->vbt.lvds_ssc_freq;
7208                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7209                 }
7210
7211                 limit = &intel_limits_i9xx_lvds;
7212         } else {
7213                 limit = &intel_limits_i9xx_sdvo;
7214         }
7215
7216         if (!crtc_state->clock_set &&
7217             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7218                                  refclk, NULL, &crtc_state->dpll)) {
7219                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7220                 return -EINVAL;
7221         }
7222
7223         i9xx_compute_dpll(crtc, crtc_state, NULL);
7224
7225         return 0;
7226 }
7227
7228 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7229                                   struct intel_crtc_state *crtc_state)
7230 {
7231         int refclk = 100000;
7232         const struct intel_limit *limit = &intel_limits_chv;
7233
7234         memset(&crtc_state->dpll_hw_state, 0,
7235                sizeof(crtc_state->dpll_hw_state));
7236
7237         if (!crtc_state->clock_set &&
7238             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7239                                 refclk, NULL, &crtc_state->dpll)) {
7240                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7241                 return -EINVAL;
7242         }
7243
7244         chv_compute_dpll(crtc, crtc_state);
7245
7246         return 0;
7247 }
7248
7249 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7250                                   struct intel_crtc_state *crtc_state)
7251 {
7252         int refclk = 100000;
7253         const struct intel_limit *limit = &intel_limits_vlv;
7254
7255         memset(&crtc_state->dpll_hw_state, 0,
7256                sizeof(crtc_state->dpll_hw_state));
7257
7258         if (!crtc_state->clock_set &&
7259             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7260                                 refclk, NULL, &crtc_state->dpll)) {
7261                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7262                 return -EINVAL;
7263         }
7264
7265         vlv_compute_dpll(crtc, crtc_state);
7266
7267         return 0;
7268 }
7269
7270 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7271                                  struct intel_crtc_state *pipe_config)
7272 {
7273         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7274         uint32_t tmp;
7275
7276         if (INTEL_GEN(dev_priv) <= 3 &&
7277             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7278                 return;
7279
7280         tmp = I915_READ(PFIT_CONTROL);
7281         if (!(tmp & PFIT_ENABLE))
7282                 return;
7283
7284         /* Check whether the pfit is attached to our pipe. */
7285         if (INTEL_GEN(dev_priv) < 4) {
7286                 if (crtc->pipe != PIPE_B)
7287                         return;
7288         } else {
7289                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7290                         return;
7291         }
7292
7293         pipe_config->gmch_pfit.control = tmp;
7294         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7295 }
7296
7297 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7298                                struct intel_crtc_state *pipe_config)
7299 {
7300         struct drm_device *dev = crtc->base.dev;
7301         struct drm_i915_private *dev_priv = to_i915(dev);
7302         int pipe = pipe_config->cpu_transcoder;
7303         struct dpll clock;
7304         u32 mdiv;
7305         int refclk = 100000;
7306
7307         /* In case of DSI, DPLL will not be used */
7308         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7309                 return;
7310
7311         mutex_lock(&dev_priv->sb_lock);
7312         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7313         mutex_unlock(&dev_priv->sb_lock);
7314
7315         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7316         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7317         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7318         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7319         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7320
7321         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7322 }
7323
7324 static void
7325 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7326                               struct intel_initial_plane_config *plane_config)
7327 {
7328         struct drm_device *dev = crtc->base.dev;
7329         struct drm_i915_private *dev_priv = to_i915(dev);
7330         u32 val, base, offset;
7331         int pipe = crtc->pipe, plane = crtc->plane;
7332         int fourcc, pixel_format;
7333         unsigned int aligned_height;
7334         struct drm_framebuffer *fb;
7335         struct intel_framebuffer *intel_fb;
7336
7337         val = I915_READ(DSPCNTR(plane));
7338         if (!(val & DISPLAY_PLANE_ENABLE))
7339                 return;
7340
7341         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7342         if (!intel_fb) {
7343                 DRM_DEBUG_KMS("failed to alloc fb\n");
7344                 return;
7345         }
7346
7347         fb = &intel_fb->base;
7348
7349         fb->dev = dev;
7350
7351         if (INTEL_GEN(dev_priv) >= 4) {
7352                 if (val & DISPPLANE_TILED) {
7353                         plane_config->tiling = I915_TILING_X;
7354                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7355                 }
7356         }
7357
7358         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7359         fourcc = i9xx_format_to_fourcc(pixel_format);
7360         fb->format = drm_format_info(fourcc);
7361
7362         if (INTEL_GEN(dev_priv) >= 4) {
7363                 if (plane_config->tiling)
7364                         offset = I915_READ(DSPTILEOFF(plane));
7365                 else
7366                         offset = I915_READ(DSPLINOFF(plane));
7367                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7368         } else {
7369                 base = I915_READ(DSPADDR(plane));
7370         }
7371         plane_config->base = base;
7372
7373         val = I915_READ(PIPESRC(pipe));
7374         fb->width = ((val >> 16) & 0xfff) + 1;
7375         fb->height = ((val >> 0) & 0xfff) + 1;
7376
7377         val = I915_READ(DSPSTRIDE(pipe));
7378         fb->pitches[0] = val & 0xffffffc0;
7379
7380         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7381
7382         plane_config->size = fb->pitches[0] * aligned_height;
7383
7384         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7385                       pipe_name(pipe), plane, fb->width, fb->height,
7386                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7387                       plane_config->size);
7388
7389         plane_config->fb = intel_fb;
7390 }
7391
7392 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7393                                struct intel_crtc_state *pipe_config)
7394 {
7395         struct drm_device *dev = crtc->base.dev;
7396         struct drm_i915_private *dev_priv = to_i915(dev);
7397         int pipe = pipe_config->cpu_transcoder;
7398         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7399         struct dpll clock;
7400         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7401         int refclk = 100000;
7402
7403         /* In case of DSI, DPLL will not be used */
7404         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7405                 return;
7406
7407         mutex_lock(&dev_priv->sb_lock);
7408         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7409         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7410         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7411         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7412         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7413         mutex_unlock(&dev_priv->sb_lock);
7414
7415         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7416         clock.m2 = (pll_dw0 & 0xff) << 22;
7417         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7418                 clock.m2 |= pll_dw2 & 0x3fffff;
7419         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7420         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7421         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7422
7423         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7424 }
7425
7426 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7427                                  struct intel_crtc_state *pipe_config)
7428 {
7429         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7430         enum intel_display_power_domain power_domain;
7431         uint32_t tmp;
7432         bool ret;
7433
7434         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7435         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7436                 return false;
7437
7438         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7439         pipe_config->shared_dpll = NULL;
7440
7441         ret = false;
7442
7443         tmp = I915_READ(PIPECONF(crtc->pipe));
7444         if (!(tmp & PIPECONF_ENABLE))
7445                 goto out;
7446
7447         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7448             IS_CHERRYVIEW(dev_priv)) {
7449                 switch (tmp & PIPECONF_BPC_MASK) {
7450                 case PIPECONF_6BPC:
7451                         pipe_config->pipe_bpp = 18;
7452                         break;
7453                 case PIPECONF_8BPC:
7454                         pipe_config->pipe_bpp = 24;
7455                         break;
7456                 case PIPECONF_10BPC:
7457                         pipe_config->pipe_bpp = 30;
7458                         break;
7459                 default:
7460                         break;
7461                 }
7462         }
7463
7464         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7465             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7466                 pipe_config->limited_color_range = true;
7467
7468         if (INTEL_GEN(dev_priv) < 4)
7469                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7470
7471         intel_get_pipe_timings(crtc, pipe_config);
7472         intel_get_pipe_src_size(crtc, pipe_config);
7473
7474         i9xx_get_pfit_config(crtc, pipe_config);
7475
7476         if (INTEL_GEN(dev_priv) >= 4) {
7477                 /* No way to read it out on pipes B and C */
7478                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7479                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7480                 else
7481                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7482                 pipe_config->pixel_multiplier =
7483                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7484                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7485                 pipe_config->dpll_hw_state.dpll_md = tmp;
7486         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7487                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7488                 tmp = I915_READ(DPLL(crtc->pipe));
7489                 pipe_config->pixel_multiplier =
7490                         ((tmp & SDVO_MULTIPLIER_MASK)
7491                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7492         } else {
7493                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7494                  * port and will be fixed up in the encoder->get_config
7495                  * function. */
7496                 pipe_config->pixel_multiplier = 1;
7497         }
7498         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7499         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7500                 /*
7501                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7502                  * on 830. Filter it out here so that we don't
7503                  * report errors due to that.
7504                  */
7505                 if (IS_I830(dev_priv))
7506                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7507
7508                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7509                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7510         } else {
7511                 /* Mask out read-only status bits. */
7512                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7513                                                      DPLL_PORTC_READY_MASK |
7514                                                      DPLL_PORTB_READY_MASK);
7515         }
7516
7517         if (IS_CHERRYVIEW(dev_priv))
7518                 chv_crtc_clock_get(crtc, pipe_config);
7519         else if (IS_VALLEYVIEW(dev_priv))
7520                 vlv_crtc_clock_get(crtc, pipe_config);
7521         else
7522                 i9xx_crtc_clock_get(crtc, pipe_config);
7523
7524         /*
7525          * Normally the dotclock is filled in by the encoder .get_config()
7526          * but in case the pipe is enabled w/o any ports we need a sane
7527          * default.
7528          */
7529         pipe_config->base.adjusted_mode.crtc_clock =
7530                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7531
7532         ret = true;
7533
7534 out:
7535         intel_display_power_put(dev_priv, power_domain);
7536
7537         return ret;
7538 }
7539
7540 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7541 {
7542         struct intel_encoder *encoder;
7543         int i;
7544         u32 val, final;
7545         bool has_lvds = false;
7546         bool has_cpu_edp = false;
7547         bool has_panel = false;
7548         bool has_ck505 = false;
7549         bool can_ssc = false;
7550         bool using_ssc_source = false;
7551
7552         /* We need to take the global config into account */
7553         for_each_intel_encoder(&dev_priv->drm, encoder) {
7554                 switch (encoder->type) {
7555                 case INTEL_OUTPUT_LVDS:
7556                         has_panel = true;
7557                         has_lvds = true;
7558                         break;
7559                 case INTEL_OUTPUT_EDP:
7560                         has_panel = true;
7561                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7562                                 has_cpu_edp = true;
7563                         break;
7564                 default:
7565                         break;
7566                 }
7567         }
7568
7569         if (HAS_PCH_IBX(dev_priv)) {
7570                 has_ck505 = dev_priv->vbt.display_clock_mode;
7571                 can_ssc = has_ck505;
7572         } else {
7573                 has_ck505 = false;
7574                 can_ssc = true;
7575         }
7576
7577         /* Check if any DPLLs are using the SSC source */
7578         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7579                 u32 temp = I915_READ(PCH_DPLL(i));
7580
7581                 if (!(temp & DPLL_VCO_ENABLE))
7582                         continue;
7583
7584                 if ((temp & PLL_REF_INPUT_MASK) ==
7585                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7586                         using_ssc_source = true;
7587                         break;
7588                 }
7589         }
7590
7591         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7592                       has_panel, has_lvds, has_ck505, using_ssc_source);
7593
7594         /* Ironlake: try to setup display ref clock before DPLL
7595          * enabling. This is only under driver's control after
7596          * PCH B stepping, previous chipset stepping should be
7597          * ignoring this setting.
7598          */
7599         val = I915_READ(PCH_DREF_CONTROL);
7600
7601         /* As we must carefully and slowly disable/enable each source in turn,
7602          * compute the final state we want first and check if we need to
7603          * make any changes at all.
7604          */
7605         final = val;
7606         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7607         if (has_ck505)
7608                 final |= DREF_NONSPREAD_CK505_ENABLE;
7609         else
7610                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7611
7612         final &= ~DREF_SSC_SOURCE_MASK;
7613         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7614         final &= ~DREF_SSC1_ENABLE;
7615
7616         if (has_panel) {
7617                 final |= DREF_SSC_SOURCE_ENABLE;
7618
7619                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7620                         final |= DREF_SSC1_ENABLE;
7621
7622                 if (has_cpu_edp) {
7623                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7624                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7625                         else
7626                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7627                 } else
7628                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7629         } else if (using_ssc_source) {
7630                 final |= DREF_SSC_SOURCE_ENABLE;
7631                 final |= DREF_SSC1_ENABLE;
7632         }
7633
7634         if (final == val)
7635                 return;
7636
7637         /* Always enable nonspread source */
7638         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7639
7640         if (has_ck505)
7641                 val |= DREF_NONSPREAD_CK505_ENABLE;
7642         else
7643                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7644
7645         if (has_panel) {
7646                 val &= ~DREF_SSC_SOURCE_MASK;
7647                 val |= DREF_SSC_SOURCE_ENABLE;
7648
7649                 /* SSC must be turned on before enabling the CPU output  */
7650                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7651                         DRM_DEBUG_KMS("Using SSC on panel\n");
7652                         val |= DREF_SSC1_ENABLE;
7653                 } else
7654                         val &= ~DREF_SSC1_ENABLE;
7655
7656                 /* Get SSC going before enabling the outputs */
7657                 I915_WRITE(PCH_DREF_CONTROL, val);
7658                 POSTING_READ(PCH_DREF_CONTROL);
7659                 udelay(200);
7660
7661                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7662
7663                 /* Enable CPU source on CPU attached eDP */
7664                 if (has_cpu_edp) {
7665                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7666                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7667                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7668                         } else
7669                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7670                 } else
7671                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7672
7673                 I915_WRITE(PCH_DREF_CONTROL, val);
7674                 POSTING_READ(PCH_DREF_CONTROL);
7675                 udelay(200);
7676         } else {
7677                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7678
7679                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7680
7681                 /* Turn off CPU output */
7682                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7683
7684                 I915_WRITE(PCH_DREF_CONTROL, val);
7685                 POSTING_READ(PCH_DREF_CONTROL);
7686                 udelay(200);
7687
7688                 if (!using_ssc_source) {
7689                         DRM_DEBUG_KMS("Disabling SSC source\n");
7690
7691                         /* Turn off the SSC source */
7692                         val &= ~DREF_SSC_SOURCE_MASK;
7693                         val |= DREF_SSC_SOURCE_DISABLE;
7694
7695                         /* Turn off SSC1 */
7696                         val &= ~DREF_SSC1_ENABLE;
7697
7698                         I915_WRITE(PCH_DREF_CONTROL, val);
7699                         POSTING_READ(PCH_DREF_CONTROL);
7700                         udelay(200);
7701                 }
7702         }
7703
7704         BUG_ON(val != final);
7705 }
7706
7707 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7708 {
7709         uint32_t tmp;
7710
7711         tmp = I915_READ(SOUTH_CHICKEN2);
7712         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7713         I915_WRITE(SOUTH_CHICKEN2, tmp);
7714
7715         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7716                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7717                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7718
7719         tmp = I915_READ(SOUTH_CHICKEN2);
7720         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7721         I915_WRITE(SOUTH_CHICKEN2, tmp);
7722
7723         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7724                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7725                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7726 }
7727
7728 /* WaMPhyProgramming:hsw */
7729 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7730 {
7731         uint32_t tmp;
7732
7733         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7734         tmp &= ~(0xFF << 24);
7735         tmp |= (0x12 << 24);
7736         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7737
7738         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7739         tmp |= (1 << 11);
7740         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7741
7742         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7743         tmp |= (1 << 11);
7744         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7745
7746         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7747         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7748         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7749
7750         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7751         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7752         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7753
7754         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7755         tmp &= ~(7 << 13);
7756         tmp |= (5 << 13);
7757         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7758
7759         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7760         tmp &= ~(7 << 13);
7761         tmp |= (5 << 13);
7762         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7763
7764         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7765         tmp &= ~0xFF;
7766         tmp |= 0x1C;
7767         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7768
7769         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7770         tmp &= ~0xFF;
7771         tmp |= 0x1C;
7772         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7773
7774         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7775         tmp &= ~(0xFF << 16);
7776         tmp |= (0x1C << 16);
7777         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7778
7779         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7780         tmp &= ~(0xFF << 16);
7781         tmp |= (0x1C << 16);
7782         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7783
7784         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7785         tmp |= (1 << 27);
7786         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7787
7788         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7789         tmp |= (1 << 27);
7790         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7791
7792         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7793         tmp &= ~(0xF << 28);
7794         tmp |= (4 << 28);
7795         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7796
7797         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7798         tmp &= ~(0xF << 28);
7799         tmp |= (4 << 28);
7800         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7801 }
7802
7803 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7804  * Programming" based on the parameters passed:
7805  * - Sequence to enable CLKOUT_DP
7806  * - Sequence to enable CLKOUT_DP without spread
7807  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7808  */
7809 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7810                                  bool with_spread, bool with_fdi)
7811 {
7812         uint32_t reg, tmp;
7813
7814         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7815                 with_spread = true;
7816         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7817             with_fdi, "LP PCH doesn't have FDI\n"))
7818                 with_fdi = false;
7819
7820         mutex_lock(&dev_priv->sb_lock);
7821
7822         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7823         tmp &= ~SBI_SSCCTL_DISABLE;
7824         tmp |= SBI_SSCCTL_PATHALT;
7825         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7826
7827         udelay(24);
7828
7829         if (with_spread) {
7830                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7831                 tmp &= ~SBI_SSCCTL_PATHALT;
7832                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7833
7834                 if (with_fdi) {
7835                         lpt_reset_fdi_mphy(dev_priv);
7836                         lpt_program_fdi_mphy(dev_priv);
7837                 }
7838         }
7839
7840         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7841         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7842         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7843         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7844
7845         mutex_unlock(&dev_priv->sb_lock);
7846 }
7847
7848 /* Sequence to disable CLKOUT_DP */
7849 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7850 {
7851         uint32_t reg, tmp;
7852
7853         mutex_lock(&dev_priv->sb_lock);
7854
7855         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7856         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7857         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7858         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7859
7860         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7861         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7862                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7863                         tmp |= SBI_SSCCTL_PATHALT;
7864                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7865                         udelay(32);
7866                 }
7867                 tmp |= SBI_SSCCTL_DISABLE;
7868                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7869         }
7870
7871         mutex_unlock(&dev_priv->sb_lock);
7872 }
7873
7874 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7875
7876 static const uint16_t sscdivintphase[] = {
7877         [BEND_IDX( 50)] = 0x3B23,
7878         [BEND_IDX( 45)] = 0x3B23,
7879         [BEND_IDX( 40)] = 0x3C23,
7880         [BEND_IDX( 35)] = 0x3C23,
7881         [BEND_IDX( 30)] = 0x3D23,
7882         [BEND_IDX( 25)] = 0x3D23,
7883         [BEND_IDX( 20)] = 0x3E23,
7884         [BEND_IDX( 15)] = 0x3E23,
7885         [BEND_IDX( 10)] = 0x3F23,
7886         [BEND_IDX(  5)] = 0x3F23,
7887         [BEND_IDX(  0)] = 0x0025,
7888         [BEND_IDX( -5)] = 0x0025,
7889         [BEND_IDX(-10)] = 0x0125,
7890         [BEND_IDX(-15)] = 0x0125,
7891         [BEND_IDX(-20)] = 0x0225,
7892         [BEND_IDX(-25)] = 0x0225,
7893         [BEND_IDX(-30)] = 0x0325,
7894         [BEND_IDX(-35)] = 0x0325,
7895         [BEND_IDX(-40)] = 0x0425,
7896         [BEND_IDX(-45)] = 0x0425,
7897         [BEND_IDX(-50)] = 0x0525,
7898 };
7899
7900 /*
7901  * Bend CLKOUT_DP
7902  * steps -50 to 50 inclusive, in steps of 5
7903  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7904  * change in clock period = -(steps / 10) * 5.787 ps
7905  */
7906 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7907 {
7908         uint32_t tmp;
7909         int idx = BEND_IDX(steps);
7910
7911         if (WARN_ON(steps % 5 != 0))
7912                 return;
7913
7914         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7915                 return;
7916
7917         mutex_lock(&dev_priv->sb_lock);
7918
7919         if (steps % 10 != 0)
7920                 tmp = 0xAAAAAAAB;
7921         else
7922                 tmp = 0x00000000;
7923         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7924
7925         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7926         tmp &= 0xffff0000;
7927         tmp |= sscdivintphase[idx];
7928         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7929
7930         mutex_unlock(&dev_priv->sb_lock);
7931 }
7932
7933 #undef BEND_IDX
7934
7935 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7936 {
7937         struct intel_encoder *encoder;
7938         bool has_vga = false;
7939
7940         for_each_intel_encoder(&dev_priv->drm, encoder) {
7941                 switch (encoder->type) {
7942                 case INTEL_OUTPUT_ANALOG:
7943                         has_vga = true;
7944                         break;
7945                 default:
7946                         break;
7947                 }
7948         }
7949
7950         if (has_vga) {
7951                 lpt_bend_clkout_dp(dev_priv, 0);
7952                 lpt_enable_clkout_dp(dev_priv, true, true);
7953         } else {
7954                 lpt_disable_clkout_dp(dev_priv);
7955         }
7956 }
7957
7958 /*
7959  * Initialize reference clocks when the driver loads
7960  */
7961 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7962 {
7963         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7964                 ironlake_init_pch_refclk(dev_priv);
7965         else if (HAS_PCH_LPT(dev_priv))
7966                 lpt_init_pch_refclk(dev_priv);
7967 }
7968
7969 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7970 {
7971         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7973         int pipe = intel_crtc->pipe;
7974         uint32_t val;
7975
7976         val = 0;
7977
7978         switch (intel_crtc->config->pipe_bpp) {
7979         case 18:
7980                 val |= PIPECONF_6BPC;
7981                 break;
7982         case 24:
7983                 val |= PIPECONF_8BPC;
7984                 break;
7985         case 30:
7986                 val |= PIPECONF_10BPC;
7987                 break;
7988         case 36:
7989                 val |= PIPECONF_12BPC;
7990                 break;
7991         default:
7992                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7993                 BUG();
7994         }
7995
7996         if (intel_crtc->config->dither)
7997                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7998
7999         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8000                 val |= PIPECONF_INTERLACED_ILK;
8001         else
8002                 val |= PIPECONF_PROGRESSIVE;
8003
8004         if (intel_crtc->config->limited_color_range)
8005                 val |= PIPECONF_COLOR_RANGE_SELECT;
8006
8007         I915_WRITE(PIPECONF(pipe), val);
8008         POSTING_READ(PIPECONF(pipe));
8009 }
8010
8011 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8012 {
8013         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8016         u32 val = 0;
8017
8018         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8019                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8020
8021         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8022                 val |= PIPECONF_INTERLACED_ILK;
8023         else
8024                 val |= PIPECONF_PROGRESSIVE;
8025
8026         I915_WRITE(PIPECONF(cpu_transcoder), val);
8027         POSTING_READ(PIPECONF(cpu_transcoder));
8028 }
8029
8030 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8031 {
8032         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8034
8035         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8036                 u32 val = 0;
8037
8038                 switch (intel_crtc->config->pipe_bpp) {
8039                 case 18:
8040                         val |= PIPEMISC_DITHER_6_BPC;
8041                         break;
8042                 case 24:
8043                         val |= PIPEMISC_DITHER_8_BPC;
8044                         break;
8045                 case 30:
8046                         val |= PIPEMISC_DITHER_10_BPC;
8047                         break;
8048                 case 36:
8049                         val |= PIPEMISC_DITHER_12_BPC;
8050                         break;
8051                 default:
8052                         /* Case prevented by pipe_config_set_bpp. */
8053                         BUG();
8054                 }
8055
8056                 if (intel_crtc->config->dither)
8057                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8058
8059                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8060         }
8061 }
8062
8063 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8064 {
8065         /*
8066          * Account for spread spectrum to avoid
8067          * oversubscribing the link. Max center spread
8068          * is 2.5%; use 5% for safety's sake.
8069          */
8070         u32 bps = target_clock * bpp * 21 / 20;
8071         return DIV_ROUND_UP(bps, link_bw * 8);
8072 }
8073
8074 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8075 {
8076         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8077 }
8078
8079 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8080                                   struct intel_crtc_state *crtc_state,
8081                                   struct dpll *reduced_clock)
8082 {
8083         struct drm_crtc *crtc = &intel_crtc->base;
8084         struct drm_device *dev = crtc->dev;
8085         struct drm_i915_private *dev_priv = to_i915(dev);
8086         u32 dpll, fp, fp2;
8087         int factor;
8088
8089         /* Enable autotuning of the PLL clock (if permissible) */
8090         factor = 21;
8091         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8092                 if ((intel_panel_use_ssc(dev_priv) &&
8093                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8094                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8095                         factor = 25;
8096         } else if (crtc_state->sdvo_tv_clock)
8097                 factor = 20;
8098
8099         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8100
8101         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8102                 fp |= FP_CB_TUNE;
8103
8104         if (reduced_clock) {
8105                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8106
8107                 if (reduced_clock->m < factor * reduced_clock->n)
8108                         fp2 |= FP_CB_TUNE;
8109         } else {
8110                 fp2 = fp;
8111         }
8112
8113         dpll = 0;
8114
8115         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8116                 dpll |= DPLLB_MODE_LVDS;
8117         else
8118                 dpll |= DPLLB_MODE_DAC_SERIAL;
8119
8120         dpll |= (crtc_state->pixel_multiplier - 1)
8121                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8122
8123         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8124             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8125                 dpll |= DPLL_SDVO_HIGH_SPEED;
8126
8127         if (intel_crtc_has_dp_encoder(crtc_state))
8128                 dpll |= DPLL_SDVO_HIGH_SPEED;
8129
8130         /*
8131          * The high speed IO clock is only really required for
8132          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8133          * possible to share the DPLL between CRT and HDMI. Enabling
8134          * the clock needlessly does no real harm, except use up a
8135          * bit of power potentially.
8136          *
8137          * We'll limit this to IVB with 3 pipes, since it has only two
8138          * DPLLs and so DPLL sharing is the only way to get three pipes
8139          * driving PCH ports at the same time. On SNB we could do this,
8140          * and potentially avoid enabling the second DPLL, but it's not
8141          * clear if it''s a win or loss power wise. No point in doing
8142          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8143          */
8144         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8145             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8146                 dpll |= DPLL_SDVO_HIGH_SPEED;
8147
8148         /* compute bitmask from p1 value */
8149         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8150         /* also FPA1 */
8151         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8152
8153         switch (crtc_state->dpll.p2) {
8154         case 5:
8155                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8156                 break;
8157         case 7:
8158                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8159                 break;
8160         case 10:
8161                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8162                 break;
8163         case 14:
8164                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8165                 break;
8166         }
8167
8168         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8169             intel_panel_use_ssc(dev_priv))
8170                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8171         else
8172                 dpll |= PLL_REF_INPUT_DREFCLK;
8173
8174         dpll |= DPLL_VCO_ENABLE;
8175
8176         crtc_state->dpll_hw_state.dpll = dpll;
8177         crtc_state->dpll_hw_state.fp0 = fp;
8178         crtc_state->dpll_hw_state.fp1 = fp2;
8179 }
8180
8181 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8182                                        struct intel_crtc_state *crtc_state)
8183 {
8184         struct drm_device *dev = crtc->base.dev;
8185         struct drm_i915_private *dev_priv = to_i915(dev);
8186         struct dpll reduced_clock;
8187         bool has_reduced_clock = false;
8188         struct intel_shared_dpll *pll;
8189         const struct intel_limit *limit;
8190         int refclk = 120000;
8191
8192         memset(&crtc_state->dpll_hw_state, 0,
8193                sizeof(crtc_state->dpll_hw_state));
8194
8195         crtc->lowfreq_avail = false;
8196
8197         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8198         if (!crtc_state->has_pch_encoder)
8199                 return 0;
8200
8201         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8202                 if (intel_panel_use_ssc(dev_priv)) {
8203                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8204                                       dev_priv->vbt.lvds_ssc_freq);
8205                         refclk = dev_priv->vbt.lvds_ssc_freq;
8206                 }
8207
8208                 if (intel_is_dual_link_lvds(dev)) {
8209                         if (refclk == 100000)
8210                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8211                         else
8212                                 limit = &intel_limits_ironlake_dual_lvds;
8213                 } else {
8214                         if (refclk == 100000)
8215                                 limit = &intel_limits_ironlake_single_lvds_100m;
8216                         else
8217                                 limit = &intel_limits_ironlake_single_lvds;
8218                 }
8219         } else {
8220                 limit = &intel_limits_ironlake_dac;
8221         }
8222
8223         if (!crtc_state->clock_set &&
8224             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8225                                 refclk, NULL, &crtc_state->dpll)) {
8226                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8227                 return -EINVAL;
8228         }
8229
8230         ironlake_compute_dpll(crtc, crtc_state,
8231                               has_reduced_clock ? &reduced_clock : NULL);
8232
8233         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8234         if (pll == NULL) {
8235                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8236                                  pipe_name(crtc->pipe));
8237                 return -EINVAL;
8238         }
8239
8240         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8241             has_reduced_clock)
8242                 crtc->lowfreq_avail = true;
8243
8244         return 0;
8245 }
8246
8247 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8248                                          struct intel_link_m_n *m_n)
8249 {
8250         struct drm_device *dev = crtc->base.dev;
8251         struct drm_i915_private *dev_priv = to_i915(dev);
8252         enum pipe pipe = crtc->pipe;
8253
8254         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8255         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8256         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8257                 & ~TU_SIZE_MASK;
8258         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8259         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8260                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8261 }
8262
8263 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8264                                          enum transcoder transcoder,
8265                                          struct intel_link_m_n *m_n,
8266                                          struct intel_link_m_n *m2_n2)
8267 {
8268         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8269         enum pipe pipe = crtc->pipe;
8270
8271         if (INTEL_GEN(dev_priv) >= 5) {
8272                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8273                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8274                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8275                         & ~TU_SIZE_MASK;
8276                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8277                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8278                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8279                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8280                  * gen < 8) and if DRRS is supported (to make sure the
8281                  * registers are not unnecessarily read).
8282                  */
8283                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8284                         crtc->config->has_drrs) {
8285                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8286                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8287                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8288                                         & ~TU_SIZE_MASK;
8289                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8290                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8291                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8292                 }
8293         } else {
8294                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8295                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8296                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8297                         & ~TU_SIZE_MASK;
8298                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8299                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8300                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8301         }
8302 }
8303
8304 void intel_dp_get_m_n(struct intel_crtc *crtc,
8305                       struct intel_crtc_state *pipe_config)
8306 {
8307         if (pipe_config->has_pch_encoder)
8308                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8309         else
8310                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8311                                              &pipe_config->dp_m_n,
8312                                              &pipe_config->dp_m2_n2);
8313 }
8314
8315 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8316                                         struct intel_crtc_state *pipe_config)
8317 {
8318         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8319                                      &pipe_config->fdi_m_n, NULL);
8320 }
8321
8322 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8323                                     struct intel_crtc_state *pipe_config)
8324 {
8325         struct drm_device *dev = crtc->base.dev;
8326         struct drm_i915_private *dev_priv = to_i915(dev);
8327         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8328         uint32_t ps_ctrl = 0;
8329         int id = -1;
8330         int i;
8331
8332         /* find scaler attached to this pipe */
8333         for (i = 0; i < crtc->num_scalers; i++) {
8334                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8335                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8336                         id = i;
8337                         pipe_config->pch_pfit.enabled = true;
8338                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8339                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8340                         break;
8341                 }
8342         }
8343
8344         scaler_state->scaler_id = id;
8345         if (id >= 0) {
8346                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8347         } else {
8348                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8349         }
8350 }
8351
8352 static void
8353 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8354                                  struct intel_initial_plane_config *plane_config)
8355 {
8356         struct drm_device *dev = crtc->base.dev;
8357         struct drm_i915_private *dev_priv = to_i915(dev);
8358         u32 val, base, offset, stride_mult, tiling;
8359         int pipe = crtc->pipe;
8360         int fourcc, pixel_format;
8361         unsigned int aligned_height;
8362         struct drm_framebuffer *fb;
8363         struct intel_framebuffer *intel_fb;
8364
8365         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8366         if (!intel_fb) {
8367                 DRM_DEBUG_KMS("failed to alloc fb\n");
8368                 return;
8369         }
8370
8371         fb = &intel_fb->base;
8372
8373         fb->dev = dev;
8374
8375         val = I915_READ(PLANE_CTL(pipe, 0));
8376         if (!(val & PLANE_CTL_ENABLE))
8377                 goto error;
8378
8379         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8380         fourcc = skl_format_to_fourcc(pixel_format,
8381                                       val & PLANE_CTL_ORDER_RGBX,
8382                                       val & PLANE_CTL_ALPHA_MASK);
8383         fb->format = drm_format_info(fourcc);
8384
8385         tiling = val & PLANE_CTL_TILED_MASK;
8386         switch (tiling) {
8387         case PLANE_CTL_TILED_LINEAR:
8388                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8389                 break;
8390         case PLANE_CTL_TILED_X:
8391                 plane_config->tiling = I915_TILING_X;
8392                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8393                 break;
8394         case PLANE_CTL_TILED_Y:
8395                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8396                 break;
8397         case PLANE_CTL_TILED_YF:
8398                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8399                 break;
8400         default:
8401                 MISSING_CASE(tiling);
8402                 goto error;
8403         }
8404
8405         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8406         plane_config->base = base;
8407
8408         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8409
8410         val = I915_READ(PLANE_SIZE(pipe, 0));
8411         fb->height = ((val >> 16) & 0xfff) + 1;
8412         fb->width = ((val >> 0) & 0x1fff) + 1;
8413
8414         val = I915_READ(PLANE_STRIDE(pipe, 0));
8415         stride_mult = intel_fb_stride_alignment(fb, 0);
8416         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8417
8418         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8419
8420         plane_config->size = fb->pitches[0] * aligned_height;
8421
8422         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8423                       pipe_name(pipe), fb->width, fb->height,
8424                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8425                       plane_config->size);
8426
8427         plane_config->fb = intel_fb;
8428         return;
8429
8430 error:
8431         kfree(intel_fb);
8432 }
8433
8434 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8435                                      struct intel_crtc_state *pipe_config)
8436 {
8437         struct drm_device *dev = crtc->base.dev;
8438         struct drm_i915_private *dev_priv = to_i915(dev);
8439         uint32_t tmp;
8440
8441         tmp = I915_READ(PF_CTL(crtc->pipe));
8442
8443         if (tmp & PF_ENABLE) {
8444                 pipe_config->pch_pfit.enabled = true;
8445                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8446                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8447
8448                 /* We currently do not free assignements of panel fitters on
8449                  * ivb/hsw (since we don't use the higher upscaling modes which
8450                  * differentiates them) so just WARN about this case for now. */
8451                 if (IS_GEN7(dev_priv)) {
8452                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8453                                 PF_PIPE_SEL_IVB(crtc->pipe));
8454                 }
8455         }
8456 }
8457
8458 static void
8459 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8460                                   struct intel_initial_plane_config *plane_config)
8461 {
8462         struct drm_device *dev = crtc->base.dev;
8463         struct drm_i915_private *dev_priv = to_i915(dev);
8464         u32 val, base, offset;
8465         int pipe = crtc->pipe;
8466         int fourcc, pixel_format;
8467         unsigned int aligned_height;
8468         struct drm_framebuffer *fb;
8469         struct intel_framebuffer *intel_fb;
8470
8471         val = I915_READ(DSPCNTR(pipe));
8472         if (!(val & DISPLAY_PLANE_ENABLE))
8473                 return;
8474
8475         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8476         if (!intel_fb) {
8477                 DRM_DEBUG_KMS("failed to alloc fb\n");
8478                 return;
8479         }
8480
8481         fb = &intel_fb->base;
8482
8483         fb->dev = dev;
8484
8485         if (INTEL_GEN(dev_priv) >= 4) {
8486                 if (val & DISPPLANE_TILED) {
8487                         plane_config->tiling = I915_TILING_X;
8488                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8489                 }
8490         }
8491
8492         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8493         fourcc = i9xx_format_to_fourcc(pixel_format);
8494         fb->format = drm_format_info(fourcc);
8495
8496         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8497         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8498                 offset = I915_READ(DSPOFFSET(pipe));
8499         } else {
8500                 if (plane_config->tiling)
8501                         offset = I915_READ(DSPTILEOFF(pipe));
8502                 else
8503                         offset = I915_READ(DSPLINOFF(pipe));
8504         }
8505         plane_config->base = base;
8506
8507         val = I915_READ(PIPESRC(pipe));
8508         fb->width = ((val >> 16) & 0xfff) + 1;
8509         fb->height = ((val >> 0) & 0xfff) + 1;
8510
8511         val = I915_READ(DSPSTRIDE(pipe));
8512         fb->pitches[0] = val & 0xffffffc0;
8513
8514         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8515
8516         plane_config->size = fb->pitches[0] * aligned_height;
8517
8518         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8519                       pipe_name(pipe), fb->width, fb->height,
8520                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8521                       plane_config->size);
8522
8523         plane_config->fb = intel_fb;
8524 }
8525
8526 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8527                                      struct intel_crtc_state *pipe_config)
8528 {
8529         struct drm_device *dev = crtc->base.dev;
8530         struct drm_i915_private *dev_priv = to_i915(dev);
8531         enum intel_display_power_domain power_domain;
8532         uint32_t tmp;
8533         bool ret;
8534
8535         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8536         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8537                 return false;
8538
8539         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8540         pipe_config->shared_dpll = NULL;
8541
8542         ret = false;
8543         tmp = I915_READ(PIPECONF(crtc->pipe));
8544         if (!(tmp & PIPECONF_ENABLE))
8545                 goto out;
8546
8547         switch (tmp & PIPECONF_BPC_MASK) {
8548         case PIPECONF_6BPC:
8549                 pipe_config->pipe_bpp = 18;
8550                 break;
8551         case PIPECONF_8BPC:
8552                 pipe_config->pipe_bpp = 24;
8553                 break;
8554         case PIPECONF_10BPC:
8555                 pipe_config->pipe_bpp = 30;
8556                 break;
8557         case PIPECONF_12BPC:
8558                 pipe_config->pipe_bpp = 36;
8559                 break;
8560         default:
8561                 break;
8562         }
8563
8564         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8565                 pipe_config->limited_color_range = true;
8566
8567         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8568                 struct intel_shared_dpll *pll;
8569                 enum intel_dpll_id pll_id;
8570
8571                 pipe_config->has_pch_encoder = true;
8572
8573                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8574                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8575                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8576
8577                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8578
8579                 if (HAS_PCH_IBX(dev_priv)) {
8580                         /*
8581                          * The pipe->pch transcoder and pch transcoder->pll
8582                          * mapping is fixed.
8583                          */
8584                         pll_id = (enum intel_dpll_id) crtc->pipe;
8585                 } else {
8586                         tmp = I915_READ(PCH_DPLL_SEL);
8587                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8588                                 pll_id = DPLL_ID_PCH_PLL_B;
8589                         else
8590                                 pll_id= DPLL_ID_PCH_PLL_A;
8591                 }
8592
8593                 pipe_config->shared_dpll =
8594                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8595                 pll = pipe_config->shared_dpll;
8596
8597                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8598                                                  &pipe_config->dpll_hw_state));
8599
8600                 tmp = pipe_config->dpll_hw_state.dpll;
8601                 pipe_config->pixel_multiplier =
8602                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8603                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8604
8605                 ironlake_pch_clock_get(crtc, pipe_config);
8606         } else {
8607                 pipe_config->pixel_multiplier = 1;
8608         }
8609
8610         intel_get_pipe_timings(crtc, pipe_config);
8611         intel_get_pipe_src_size(crtc, pipe_config);
8612
8613         ironlake_get_pfit_config(crtc, pipe_config);
8614
8615         ret = true;
8616
8617 out:
8618         intel_display_power_put(dev_priv, power_domain);
8619
8620         return ret;
8621 }
8622
8623 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8624 {
8625         struct drm_device *dev = &dev_priv->drm;
8626         struct intel_crtc *crtc;
8627
8628         for_each_intel_crtc(dev, crtc)
8629                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8630                      pipe_name(crtc->pipe));
8631
8632         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8633         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8634         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8635         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8636         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8637         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8638              "CPU PWM1 enabled\n");
8639         if (IS_HASWELL(dev_priv))
8640                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8641                      "CPU PWM2 enabled\n");
8642         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8643              "PCH PWM1 enabled\n");
8644         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8645              "Utility pin enabled\n");
8646         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8647
8648         /*
8649          * In theory we can still leave IRQs enabled, as long as only the HPD
8650          * interrupts remain enabled. We used to check for that, but since it's
8651          * gen-specific and since we only disable LCPLL after we fully disable
8652          * the interrupts, the check below should be enough.
8653          */
8654         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8655 }
8656
8657 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8658 {
8659         if (IS_HASWELL(dev_priv))
8660                 return I915_READ(D_COMP_HSW);
8661         else
8662                 return I915_READ(D_COMP_BDW);
8663 }
8664
8665 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8666 {
8667         if (IS_HASWELL(dev_priv)) {
8668                 mutex_lock(&dev_priv->rps.hw_lock);
8669                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8670                                             val))
8671                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8672                 mutex_unlock(&dev_priv->rps.hw_lock);
8673         } else {
8674                 I915_WRITE(D_COMP_BDW, val);
8675                 POSTING_READ(D_COMP_BDW);
8676         }
8677 }
8678
8679 /*
8680  * This function implements pieces of two sequences from BSpec:
8681  * - Sequence for display software to disable LCPLL
8682  * - Sequence for display software to allow package C8+
8683  * The steps implemented here are just the steps that actually touch the LCPLL
8684  * register. Callers should take care of disabling all the display engine
8685  * functions, doing the mode unset, fixing interrupts, etc.
8686  */
8687 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8688                               bool switch_to_fclk, bool allow_power_down)
8689 {
8690         uint32_t val;
8691
8692         assert_can_disable_lcpll(dev_priv);
8693
8694         val = I915_READ(LCPLL_CTL);
8695
8696         if (switch_to_fclk) {
8697                 val |= LCPLL_CD_SOURCE_FCLK;
8698                 I915_WRITE(LCPLL_CTL, val);
8699
8700                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8701                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8702                         DRM_ERROR("Switching to FCLK failed\n");
8703
8704                 val = I915_READ(LCPLL_CTL);
8705         }
8706
8707         val |= LCPLL_PLL_DISABLE;
8708         I915_WRITE(LCPLL_CTL, val);
8709         POSTING_READ(LCPLL_CTL);
8710
8711         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8712                 DRM_ERROR("LCPLL still locked\n");
8713
8714         val = hsw_read_dcomp(dev_priv);
8715         val |= D_COMP_COMP_DISABLE;
8716         hsw_write_dcomp(dev_priv, val);
8717         ndelay(100);
8718
8719         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8720                      1))
8721                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8722
8723         if (allow_power_down) {
8724                 val = I915_READ(LCPLL_CTL);
8725                 val |= LCPLL_POWER_DOWN_ALLOW;
8726                 I915_WRITE(LCPLL_CTL, val);
8727                 POSTING_READ(LCPLL_CTL);
8728         }
8729 }
8730
8731 /*
8732  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8733  * source.
8734  */
8735 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8736 {
8737         uint32_t val;
8738
8739         val = I915_READ(LCPLL_CTL);
8740
8741         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8742                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8743                 return;
8744
8745         /*
8746          * Make sure we're not on PC8 state before disabling PC8, otherwise
8747          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8748          */
8749         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8750
8751         if (val & LCPLL_POWER_DOWN_ALLOW) {
8752                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8753                 I915_WRITE(LCPLL_CTL, val);
8754                 POSTING_READ(LCPLL_CTL);
8755         }
8756
8757         val = hsw_read_dcomp(dev_priv);
8758         val |= D_COMP_COMP_FORCE;
8759         val &= ~D_COMP_COMP_DISABLE;
8760         hsw_write_dcomp(dev_priv, val);
8761
8762         val = I915_READ(LCPLL_CTL);
8763         val &= ~LCPLL_PLL_DISABLE;
8764         I915_WRITE(LCPLL_CTL, val);
8765
8766         if (intel_wait_for_register(dev_priv,
8767                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8768                                     5))
8769                 DRM_ERROR("LCPLL not locked yet\n");
8770
8771         if (val & LCPLL_CD_SOURCE_FCLK) {
8772                 val = I915_READ(LCPLL_CTL);
8773                 val &= ~LCPLL_CD_SOURCE_FCLK;
8774                 I915_WRITE(LCPLL_CTL, val);
8775
8776                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8777                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8778                         DRM_ERROR("Switching back to LCPLL failed\n");
8779         }
8780
8781         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8782         intel_update_cdclk(dev_priv);
8783 }
8784
8785 /*
8786  * Package states C8 and deeper are really deep PC states that can only be
8787  * reached when all the devices on the system allow it, so even if the graphics
8788  * device allows PC8+, it doesn't mean the system will actually get to these
8789  * states. Our driver only allows PC8+ when going into runtime PM.
8790  *
8791  * The requirements for PC8+ are that all the outputs are disabled, the power
8792  * well is disabled and most interrupts are disabled, and these are also
8793  * requirements for runtime PM. When these conditions are met, we manually do
8794  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8795  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8796  * hang the machine.
8797  *
8798  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8799  * the state of some registers, so when we come back from PC8+ we need to
8800  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8801  * need to take care of the registers kept by RC6. Notice that this happens even
8802  * if we don't put the device in PCI D3 state (which is what currently happens
8803  * because of the runtime PM support).
8804  *
8805  * For more, read "Display Sequences for Package C8" on the hardware
8806  * documentation.
8807  */
8808 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8809 {
8810         uint32_t val;
8811
8812         DRM_DEBUG_KMS("Enabling package C8+\n");
8813
8814         if (HAS_PCH_LPT_LP(dev_priv)) {
8815                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8816                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8817                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8818         }
8819
8820         lpt_disable_clkout_dp(dev_priv);
8821         hsw_disable_lcpll(dev_priv, true, true);
8822 }
8823
8824 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8825 {
8826         uint32_t val;
8827
8828         DRM_DEBUG_KMS("Disabling package C8+\n");
8829
8830         hsw_restore_lcpll(dev_priv);
8831         lpt_init_pch_refclk(dev_priv);
8832
8833         if (HAS_PCH_LPT_LP(dev_priv)) {
8834                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8835                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8836                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8837         }
8838 }
8839
8840 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8841                                       struct intel_crtc_state *crtc_state)
8842 {
8843         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8844                 struct intel_encoder *encoder =
8845                         intel_ddi_get_crtc_new_encoder(crtc_state);
8846
8847                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8848                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8849                                          pipe_name(crtc->pipe));
8850                         return -EINVAL;
8851                 }
8852         }
8853
8854         crtc->lowfreq_avail = false;
8855
8856         return 0;
8857 }
8858
8859 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8860                                 enum port port,
8861                                 struct intel_crtc_state *pipe_config)
8862 {
8863         enum intel_dpll_id id;
8864
8865         switch (port) {
8866         case PORT_A:
8867                 id = DPLL_ID_SKL_DPLL0;
8868                 break;
8869         case PORT_B:
8870                 id = DPLL_ID_SKL_DPLL1;
8871                 break;
8872         case PORT_C:
8873                 id = DPLL_ID_SKL_DPLL2;
8874                 break;
8875         default:
8876                 DRM_ERROR("Incorrect port type\n");
8877                 return;
8878         }
8879
8880         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8881 }
8882
8883 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8884                                 enum port port,
8885                                 struct intel_crtc_state *pipe_config)
8886 {
8887         enum intel_dpll_id id;
8888         u32 temp;
8889
8890         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8891         id = temp >> (port * 3 + 1);
8892
8893         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8894                 return;
8895
8896         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8897 }
8898
8899 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8900                                 enum port port,
8901                                 struct intel_crtc_state *pipe_config)
8902 {
8903         enum intel_dpll_id id;
8904         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8905
8906         switch (ddi_pll_sel) {
8907         case PORT_CLK_SEL_WRPLL1:
8908                 id = DPLL_ID_WRPLL1;
8909                 break;
8910         case PORT_CLK_SEL_WRPLL2:
8911                 id = DPLL_ID_WRPLL2;
8912                 break;
8913         case PORT_CLK_SEL_SPLL:
8914                 id = DPLL_ID_SPLL;
8915                 break;
8916         case PORT_CLK_SEL_LCPLL_810:
8917                 id = DPLL_ID_LCPLL_810;
8918                 break;
8919         case PORT_CLK_SEL_LCPLL_1350:
8920                 id = DPLL_ID_LCPLL_1350;
8921                 break;
8922         case PORT_CLK_SEL_LCPLL_2700:
8923                 id = DPLL_ID_LCPLL_2700;
8924                 break;
8925         default:
8926                 MISSING_CASE(ddi_pll_sel);
8927                 /* fall through */
8928         case PORT_CLK_SEL_NONE:
8929                 return;
8930         }
8931
8932         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8933 }
8934
8935 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8936                                      struct intel_crtc_state *pipe_config,
8937                                      u64 *power_domain_mask)
8938 {
8939         struct drm_device *dev = crtc->base.dev;
8940         struct drm_i915_private *dev_priv = to_i915(dev);
8941         enum intel_display_power_domain power_domain;
8942         u32 tmp;
8943
8944         /*
8945          * The pipe->transcoder mapping is fixed with the exception of the eDP
8946          * transcoder handled below.
8947          */
8948         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8949
8950         /*
8951          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8952          * consistency and less surprising code; it's in always on power).
8953          */
8954         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8955         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8956                 enum pipe trans_edp_pipe;
8957                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8958                 default:
8959                         WARN(1, "unknown pipe linked to edp transcoder\n");
8960                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8961                 case TRANS_DDI_EDP_INPUT_A_ON:
8962                         trans_edp_pipe = PIPE_A;
8963                         break;
8964                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8965                         trans_edp_pipe = PIPE_B;
8966                         break;
8967                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8968                         trans_edp_pipe = PIPE_C;
8969                         break;
8970                 }
8971
8972                 if (trans_edp_pipe == crtc->pipe)
8973                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8974         }
8975
8976         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8977         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8978                 return false;
8979         *power_domain_mask |= BIT_ULL(power_domain);
8980
8981         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8982
8983         return tmp & PIPECONF_ENABLE;
8984 }
8985
8986 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8987                                          struct intel_crtc_state *pipe_config,
8988                                          u64 *power_domain_mask)
8989 {
8990         struct drm_device *dev = crtc->base.dev;
8991         struct drm_i915_private *dev_priv = to_i915(dev);
8992         enum intel_display_power_domain power_domain;
8993         enum port port;
8994         enum transcoder cpu_transcoder;
8995         u32 tmp;
8996
8997         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8998                 if (port == PORT_A)
8999                         cpu_transcoder = TRANSCODER_DSI_A;
9000                 else
9001                         cpu_transcoder = TRANSCODER_DSI_C;
9002
9003                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9004                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9005                         continue;
9006                 *power_domain_mask |= BIT_ULL(power_domain);
9007
9008                 /*
9009                  * The PLL needs to be enabled with a valid divider
9010                  * configuration, otherwise accessing DSI registers will hang
9011                  * the machine. See BSpec North Display Engine
9012                  * registers/MIPI[BXT]. We can break out here early, since we
9013                  * need the same DSI PLL to be enabled for both DSI ports.
9014                  */
9015                 if (!intel_dsi_pll_is_enabled(dev_priv))
9016                         break;
9017
9018                 /* XXX: this works for video mode only */
9019                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9020                 if (!(tmp & DPI_ENABLE))
9021                         continue;
9022
9023                 tmp = I915_READ(MIPI_CTRL(port));
9024                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9025                         continue;
9026
9027                 pipe_config->cpu_transcoder = cpu_transcoder;
9028                 break;
9029         }
9030
9031         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9032 }
9033
9034 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9035                                        struct intel_crtc_state *pipe_config)
9036 {
9037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9038         struct intel_shared_dpll *pll;
9039         enum port port;
9040         uint32_t tmp;
9041
9042         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9043
9044         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9045
9046         if (IS_GEN9_BC(dev_priv))
9047                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9048         else if (IS_GEN9_LP(dev_priv))
9049                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9050         else
9051                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9052
9053         pll = pipe_config->shared_dpll;
9054         if (pll) {
9055                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9056                                                  &pipe_config->dpll_hw_state));
9057         }
9058
9059         /*
9060          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9061          * DDI E. So just check whether this pipe is wired to DDI E and whether
9062          * the PCH transcoder is on.
9063          */
9064         if (INTEL_GEN(dev_priv) < 9 &&
9065             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9066                 pipe_config->has_pch_encoder = true;
9067
9068                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9069                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9070                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9071
9072                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9073         }
9074 }
9075
9076 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9077                                     struct intel_crtc_state *pipe_config)
9078 {
9079         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9080         enum intel_display_power_domain power_domain;
9081         u64 power_domain_mask;
9082         bool active;
9083
9084         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9085         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9086                 return false;
9087         power_domain_mask = BIT_ULL(power_domain);
9088
9089         pipe_config->shared_dpll = NULL;
9090
9091         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9092
9093         if (IS_GEN9_LP(dev_priv) &&
9094             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9095                 WARN_ON(active);
9096                 active = true;
9097         }
9098
9099         if (!active)
9100                 goto out;
9101
9102         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9103                 haswell_get_ddi_port_state(crtc, pipe_config);
9104                 intel_get_pipe_timings(crtc, pipe_config);
9105         }
9106
9107         intel_get_pipe_src_size(crtc, pipe_config);
9108
9109         pipe_config->gamma_mode =
9110                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9111
9112         if (INTEL_GEN(dev_priv) >= 9) {
9113                 intel_crtc_init_scalers(crtc, pipe_config);
9114
9115                 pipe_config->scaler_state.scaler_id = -1;
9116                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9117         }
9118
9119         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9120         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9121                 power_domain_mask |= BIT_ULL(power_domain);
9122                 if (INTEL_GEN(dev_priv) >= 9)
9123                         skylake_get_pfit_config(crtc, pipe_config);
9124                 else
9125                         ironlake_get_pfit_config(crtc, pipe_config);
9126         }
9127
9128         if (IS_HASWELL(dev_priv))
9129                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9130                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9131
9132         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9133             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9134                 pipe_config->pixel_multiplier =
9135                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9136         } else {
9137                 pipe_config->pixel_multiplier = 1;
9138         }
9139
9140 out:
9141         for_each_power_domain(power_domain, power_domain_mask)
9142                 intel_display_power_put(dev_priv, power_domain);
9143
9144         return active;
9145 }
9146
9147 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9148                            const struct intel_plane_state *plane_state)
9149 {
9150         unsigned int width = plane_state->base.crtc_w;
9151         unsigned int stride = roundup_pow_of_two(width) * 4;
9152
9153         switch (stride) {
9154         default:
9155                 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9156                           width, stride);
9157                 stride = 256;
9158                 /* fallthrough */
9159         case 256:
9160         case 512:
9161         case 1024:
9162         case 2048:
9163                 break;
9164         }
9165
9166         return CURSOR_ENABLE |
9167                 CURSOR_GAMMA_ENABLE |
9168                 CURSOR_FORMAT_ARGB |
9169                 CURSOR_STRIDE(stride);
9170 }
9171
9172 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9173                                const struct intel_plane_state *plane_state)
9174 {
9175         struct drm_device *dev = crtc->dev;
9176         struct drm_i915_private *dev_priv = to_i915(dev);
9177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9178         uint32_t cntl = 0, size = 0;
9179
9180         if (plane_state && plane_state->base.visible) {
9181                 unsigned int width = plane_state->base.crtc_w;
9182                 unsigned int height = plane_state->base.crtc_h;
9183
9184                 cntl = plane_state->ctl;
9185                 size = (height << 12) | width;
9186         }
9187
9188         if (intel_crtc->cursor_cntl != 0 &&
9189             (intel_crtc->cursor_base != base ||
9190              intel_crtc->cursor_size != size ||
9191              intel_crtc->cursor_cntl != cntl)) {
9192                 /* On these chipsets we can only modify the base/size/stride
9193                  * whilst the cursor is disabled.
9194                  */
9195                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9196                 POSTING_READ_FW(CURCNTR(PIPE_A));
9197                 intel_crtc->cursor_cntl = 0;
9198         }
9199
9200         if (intel_crtc->cursor_base != base) {
9201                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9202                 intel_crtc->cursor_base = base;
9203         }
9204
9205         if (intel_crtc->cursor_size != size) {
9206                 I915_WRITE_FW(CURSIZE, size);
9207                 intel_crtc->cursor_size = size;
9208         }
9209
9210         if (intel_crtc->cursor_cntl != cntl) {
9211                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9212                 POSTING_READ_FW(CURCNTR(PIPE_A));
9213                 intel_crtc->cursor_cntl = cntl;
9214         }
9215 }
9216
9217 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9218                            const struct intel_plane_state *plane_state)
9219 {
9220         struct drm_i915_private *dev_priv =
9221                 to_i915(plane_state->base.plane->dev);
9222         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9223         enum pipe pipe = crtc->pipe;
9224         u32 cntl;
9225
9226         cntl = MCURSOR_GAMMA_ENABLE;
9227
9228         if (HAS_DDI(dev_priv))
9229                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9230
9231         cntl |= pipe << 28; /* Connect to correct pipe */
9232
9233         switch (plane_state->base.crtc_w) {
9234         case 64:
9235                 cntl |= CURSOR_MODE_64_ARGB_AX;
9236                 break;
9237         case 128:
9238                 cntl |= CURSOR_MODE_128_ARGB_AX;
9239                 break;
9240         case 256:
9241                 cntl |= CURSOR_MODE_256_ARGB_AX;
9242                 break;
9243         default:
9244                 MISSING_CASE(plane_state->base.crtc_w);
9245                 return 0;
9246         }
9247
9248         if (plane_state->base.rotation & DRM_ROTATE_180)
9249                 cntl |= CURSOR_ROTATE_180;
9250
9251         return cntl;
9252 }
9253
9254 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9255                                const struct intel_plane_state *plane_state)
9256 {
9257         struct drm_device *dev = crtc->dev;
9258         struct drm_i915_private *dev_priv = to_i915(dev);
9259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9260         int pipe = intel_crtc->pipe;
9261         uint32_t cntl = 0;
9262
9263         if (plane_state && plane_state->base.visible)
9264                 cntl = plane_state->ctl;
9265
9266         if (intel_crtc->cursor_cntl != cntl) {
9267                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9268                 POSTING_READ_FW(CURCNTR(pipe));
9269                 intel_crtc->cursor_cntl = cntl;
9270         }
9271
9272         /* and commit changes on next vblank */
9273         I915_WRITE_FW(CURBASE(pipe), base);
9274         POSTING_READ_FW(CURBASE(pipe));
9275
9276         intel_crtc->cursor_base = base;
9277 }
9278
9279 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9280 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9281                                      const struct intel_plane_state *plane_state)
9282 {
9283         struct drm_device *dev = crtc->dev;
9284         struct drm_i915_private *dev_priv = to_i915(dev);
9285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9286         int pipe = intel_crtc->pipe;
9287         u32 base = intel_crtc->cursor_addr;
9288         unsigned long irqflags;
9289         u32 pos = 0;
9290
9291         if (plane_state) {
9292                 int x = plane_state->base.crtc_x;
9293                 int y = plane_state->base.crtc_y;
9294
9295                 if (x < 0) {
9296                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9297                         x = -x;
9298                 }
9299                 pos |= x << CURSOR_X_SHIFT;
9300
9301                 if (y < 0) {
9302                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9303                         y = -y;
9304                 }
9305                 pos |= y << CURSOR_Y_SHIFT;
9306
9307                 /* ILK+ do this automagically */
9308                 if (HAS_GMCH_DISPLAY(dev_priv) &&
9309                     plane_state->base.rotation & DRM_ROTATE_180) {
9310                         base += (plane_state->base.crtc_h *
9311                                  plane_state->base.crtc_w - 1) * 4;
9312                 }
9313         }
9314
9315         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9316
9317         I915_WRITE_FW(CURPOS(pipe), pos);
9318
9319         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9320                 i845_update_cursor(crtc, base, plane_state);
9321         else
9322                 i9xx_update_cursor(crtc, base, plane_state);
9323
9324         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9325 }
9326
9327 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9328                            uint32_t width, uint32_t height)
9329 {
9330         if (width == 0 || height == 0)
9331                 return false;
9332
9333         /*
9334          * 845g/865g are special in that they are only limited by
9335          * the width of their cursors, the height is arbitrary up to
9336          * the precision of the register. Everything else requires
9337          * square cursors, limited to a few power-of-two sizes.
9338          */
9339         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9340                 if ((width & 63) != 0)
9341                         return false;
9342
9343                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9344                         return false;
9345
9346                 if (height > 1023)
9347                         return false;
9348         } else {
9349                 switch (width | height) {
9350                 case 256:
9351                 case 128:
9352                         if (IS_GEN2(dev_priv))
9353                                 return false;
9354                 case 64:
9355                         break;
9356                 default:
9357                         return false;
9358                 }
9359         }
9360
9361         return true;
9362 }
9363
9364 /* VESA 640x480x72Hz mode to set on the pipe */
9365 static struct drm_display_mode load_detect_mode = {
9366         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9367                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9368 };
9369
9370 struct drm_framebuffer *
9371 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9372                          struct drm_mode_fb_cmd2 *mode_cmd)
9373 {
9374         struct intel_framebuffer *intel_fb;
9375         int ret;
9376
9377         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9378         if (!intel_fb)
9379                 return ERR_PTR(-ENOMEM);
9380
9381         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9382         if (ret)
9383                 goto err;
9384
9385         return &intel_fb->base;
9386
9387 err:
9388         kfree(intel_fb);
9389         return ERR_PTR(ret);
9390 }
9391
9392 static u32
9393 intel_framebuffer_pitch_for_width(int width, int bpp)
9394 {
9395         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9396         return ALIGN(pitch, 64);
9397 }
9398
9399 static u32
9400 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9401 {
9402         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9403         return PAGE_ALIGN(pitch * mode->vdisplay);
9404 }
9405
9406 static struct drm_framebuffer *
9407 intel_framebuffer_create_for_mode(struct drm_device *dev,
9408                                   struct drm_display_mode *mode,
9409                                   int depth, int bpp)
9410 {
9411         struct drm_framebuffer *fb;
9412         struct drm_i915_gem_object *obj;
9413         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9414
9415         obj = i915_gem_object_create(to_i915(dev),
9416                                     intel_framebuffer_size_for_mode(mode, bpp));
9417         if (IS_ERR(obj))
9418                 return ERR_CAST(obj);
9419
9420         mode_cmd.width = mode->hdisplay;
9421         mode_cmd.height = mode->vdisplay;
9422         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9423                                                                 bpp);
9424         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9425
9426         fb = intel_framebuffer_create(obj, &mode_cmd);
9427         if (IS_ERR(fb))
9428                 i915_gem_object_put(obj);
9429
9430         return fb;
9431 }
9432
9433 static struct drm_framebuffer *
9434 mode_fits_in_fbdev(struct drm_device *dev,
9435                    struct drm_display_mode *mode)
9436 {
9437 #ifdef CONFIG_DRM_FBDEV_EMULATION
9438         struct drm_i915_private *dev_priv = to_i915(dev);
9439         struct drm_i915_gem_object *obj;
9440         struct drm_framebuffer *fb;
9441
9442         if (!dev_priv->fbdev)
9443                 return NULL;
9444
9445         if (!dev_priv->fbdev->fb)
9446                 return NULL;
9447
9448         obj = dev_priv->fbdev->fb->obj;
9449         BUG_ON(!obj);
9450
9451         fb = &dev_priv->fbdev->fb->base;
9452         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9453                                                                fb->format->cpp[0] * 8))
9454                 return NULL;
9455
9456         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9457                 return NULL;
9458
9459         drm_framebuffer_reference(fb);
9460         return fb;
9461 #else
9462         return NULL;
9463 #endif
9464 }
9465
9466 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9467                                            struct drm_crtc *crtc,
9468                                            struct drm_display_mode *mode,
9469                                            struct drm_framebuffer *fb,
9470                                            int x, int y)
9471 {
9472         struct drm_plane_state *plane_state;
9473         int hdisplay, vdisplay;
9474         int ret;
9475
9476         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9477         if (IS_ERR(plane_state))
9478                 return PTR_ERR(plane_state);
9479
9480         if (mode)
9481                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9482         else
9483                 hdisplay = vdisplay = 0;
9484
9485         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9486         if (ret)
9487                 return ret;
9488         drm_atomic_set_fb_for_plane(plane_state, fb);
9489         plane_state->crtc_x = 0;
9490         plane_state->crtc_y = 0;
9491         plane_state->crtc_w = hdisplay;
9492         plane_state->crtc_h = vdisplay;
9493         plane_state->src_x = x << 16;
9494         plane_state->src_y = y << 16;
9495         plane_state->src_w = hdisplay << 16;
9496         plane_state->src_h = vdisplay << 16;
9497
9498         return 0;
9499 }
9500
9501 int intel_get_load_detect_pipe(struct drm_connector *connector,
9502                                struct drm_display_mode *mode,
9503                                struct intel_load_detect_pipe *old,
9504                                struct drm_modeset_acquire_ctx *ctx)
9505 {
9506         struct intel_crtc *intel_crtc;
9507         struct intel_encoder *intel_encoder =
9508                 intel_attached_encoder(connector);
9509         struct drm_crtc *possible_crtc;
9510         struct drm_encoder *encoder = &intel_encoder->base;
9511         struct drm_crtc *crtc = NULL;
9512         struct drm_device *dev = encoder->dev;
9513         struct drm_i915_private *dev_priv = to_i915(dev);
9514         struct drm_framebuffer *fb;
9515         struct drm_mode_config *config = &dev->mode_config;
9516         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9517         struct drm_connector_state *connector_state;
9518         struct intel_crtc_state *crtc_state;
9519         int ret, i = -1;
9520
9521         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9522                       connector->base.id, connector->name,
9523                       encoder->base.id, encoder->name);
9524
9525         old->restore_state = NULL;
9526
9527         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9528
9529         /*
9530          * Algorithm gets a little messy:
9531          *
9532          *   - if the connector already has an assigned crtc, use it (but make
9533          *     sure it's on first)
9534          *
9535          *   - try to find the first unused crtc that can drive this connector,
9536          *     and use that if we find one
9537          */
9538
9539         /* See if we already have a CRTC for this connector */
9540         if (connector->state->crtc) {
9541                 crtc = connector->state->crtc;
9542
9543                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9544                 if (ret)
9545                         goto fail;
9546
9547                 /* Make sure the crtc and connector are running */
9548                 goto found;
9549         }
9550
9551         /* Find an unused one (if possible) */
9552         for_each_crtc(dev, possible_crtc) {
9553                 i++;
9554                 if (!(encoder->possible_crtcs & (1 << i)))
9555                         continue;
9556
9557                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9558                 if (ret)
9559                         goto fail;
9560
9561                 if (possible_crtc->state->enable) {
9562                         drm_modeset_unlock(&possible_crtc->mutex);
9563                         continue;
9564                 }
9565
9566                 crtc = possible_crtc;
9567                 break;
9568         }
9569
9570         /*
9571          * If we didn't find an unused CRTC, don't use any.
9572          */
9573         if (!crtc) {
9574                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9575                 goto fail;
9576         }
9577
9578 found:
9579         intel_crtc = to_intel_crtc(crtc);
9580
9581         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9582         if (ret)
9583                 goto fail;
9584
9585         state = drm_atomic_state_alloc(dev);
9586         restore_state = drm_atomic_state_alloc(dev);
9587         if (!state || !restore_state) {
9588                 ret = -ENOMEM;
9589                 goto fail;
9590         }
9591
9592         state->acquire_ctx = ctx;
9593         restore_state->acquire_ctx = ctx;
9594
9595         connector_state = drm_atomic_get_connector_state(state, connector);
9596         if (IS_ERR(connector_state)) {
9597                 ret = PTR_ERR(connector_state);
9598                 goto fail;
9599         }
9600
9601         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9602         if (ret)
9603                 goto fail;
9604
9605         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9606         if (IS_ERR(crtc_state)) {
9607                 ret = PTR_ERR(crtc_state);
9608                 goto fail;
9609         }
9610
9611         crtc_state->base.active = crtc_state->base.enable = true;
9612
9613         if (!mode)
9614                 mode = &load_detect_mode;
9615
9616         /* We need a framebuffer large enough to accommodate all accesses
9617          * that the plane may generate whilst we perform load detection.
9618          * We can not rely on the fbcon either being present (we get called
9619          * during its initialisation to detect all boot displays, or it may
9620          * not even exist) or that it is large enough to satisfy the
9621          * requested mode.
9622          */
9623         fb = mode_fits_in_fbdev(dev, mode);
9624         if (fb == NULL) {
9625                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9626                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9627         } else
9628                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9629         if (IS_ERR(fb)) {
9630                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9631                 goto fail;
9632         }
9633
9634         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9635         if (ret)
9636                 goto fail;
9637
9638         drm_framebuffer_unreference(fb);
9639
9640         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9641         if (ret)
9642                 goto fail;
9643
9644         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9645         if (!ret)
9646                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9647         if (!ret)
9648                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9649         if (ret) {
9650                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9651                 goto fail;
9652         }
9653
9654         ret = drm_atomic_commit(state);
9655         if (ret) {
9656                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9657                 goto fail;
9658         }
9659
9660         old->restore_state = restore_state;
9661         drm_atomic_state_put(state);
9662
9663         /* let the connector get through one full cycle before testing */
9664         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9665         return true;
9666
9667 fail:
9668         if (state) {
9669                 drm_atomic_state_put(state);
9670                 state = NULL;
9671         }
9672         if (restore_state) {
9673                 drm_atomic_state_put(restore_state);
9674                 restore_state = NULL;
9675         }
9676
9677         if (ret == -EDEADLK)
9678                 return ret;
9679
9680         return false;
9681 }
9682
9683 void intel_release_load_detect_pipe(struct drm_connector *connector,
9684                                     struct intel_load_detect_pipe *old,
9685                                     struct drm_modeset_acquire_ctx *ctx)
9686 {
9687         struct intel_encoder *intel_encoder =
9688                 intel_attached_encoder(connector);
9689         struct drm_encoder *encoder = &intel_encoder->base;
9690         struct drm_atomic_state *state = old->restore_state;
9691         int ret;
9692
9693         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9694                       connector->base.id, connector->name,
9695                       encoder->base.id, encoder->name);
9696
9697         if (!state)
9698                 return;
9699
9700         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9701         if (ret)
9702                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9703         drm_atomic_state_put(state);
9704 }
9705
9706 static int i9xx_pll_refclk(struct drm_device *dev,
9707                            const struct intel_crtc_state *pipe_config)
9708 {
9709         struct drm_i915_private *dev_priv = to_i915(dev);
9710         u32 dpll = pipe_config->dpll_hw_state.dpll;
9711
9712         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9713                 return dev_priv->vbt.lvds_ssc_freq;
9714         else if (HAS_PCH_SPLIT(dev_priv))
9715                 return 120000;
9716         else if (!IS_GEN2(dev_priv))
9717                 return 96000;
9718         else
9719                 return 48000;
9720 }
9721
9722 /* Returns the clock of the currently programmed mode of the given pipe. */
9723 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9724                                 struct intel_crtc_state *pipe_config)
9725 {
9726         struct drm_device *dev = crtc->base.dev;
9727         struct drm_i915_private *dev_priv = to_i915(dev);
9728         int pipe = pipe_config->cpu_transcoder;
9729         u32 dpll = pipe_config->dpll_hw_state.dpll;
9730         u32 fp;
9731         struct dpll clock;
9732         int port_clock;
9733         int refclk = i9xx_pll_refclk(dev, pipe_config);
9734
9735         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9736                 fp = pipe_config->dpll_hw_state.fp0;
9737         else
9738                 fp = pipe_config->dpll_hw_state.fp1;
9739
9740         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9741         if (IS_PINEVIEW(dev_priv)) {
9742                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9743                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9744         } else {
9745                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9746                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9747         }
9748
9749         if (!IS_GEN2(dev_priv)) {
9750                 if (IS_PINEVIEW(dev_priv))
9751                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9752                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9753                 else
9754                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9755                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9756
9757                 switch (dpll & DPLL_MODE_MASK) {
9758                 case DPLLB_MODE_DAC_SERIAL:
9759                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9760                                 5 : 10;
9761                         break;
9762                 case DPLLB_MODE_LVDS:
9763                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9764                                 7 : 14;
9765                         break;
9766                 default:
9767                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9768                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9769                         return;
9770                 }
9771
9772                 if (IS_PINEVIEW(dev_priv))
9773                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9774                 else
9775                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9776         } else {
9777                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9778                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9779
9780                 if (is_lvds) {
9781                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9782                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9783
9784                         if (lvds & LVDS_CLKB_POWER_UP)
9785                                 clock.p2 = 7;
9786                         else
9787                                 clock.p2 = 14;
9788                 } else {
9789                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9790                                 clock.p1 = 2;
9791                         else {
9792                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9793                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9794                         }
9795                         if (dpll & PLL_P2_DIVIDE_BY_4)
9796                                 clock.p2 = 4;
9797                         else
9798                                 clock.p2 = 2;
9799                 }
9800
9801                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9802         }
9803
9804         /*
9805          * This value includes pixel_multiplier. We will use
9806          * port_clock to compute adjusted_mode.crtc_clock in the
9807          * encoder's get_config() function.
9808          */
9809         pipe_config->port_clock = port_clock;
9810 }
9811
9812 int intel_dotclock_calculate(int link_freq,
9813                              const struct intel_link_m_n *m_n)
9814 {
9815         /*
9816          * The calculation for the data clock is:
9817          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9818          * But we want to avoid losing precison if possible, so:
9819          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9820          *
9821          * and the link clock is simpler:
9822          * link_clock = (m * link_clock) / n
9823          */
9824
9825         if (!m_n->link_n)
9826                 return 0;
9827
9828         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9829 }
9830
9831 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9832                                    struct intel_crtc_state *pipe_config)
9833 {
9834         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9835
9836         /* read out port_clock from the DPLL */
9837         i9xx_crtc_clock_get(crtc, pipe_config);
9838
9839         /*
9840          * In case there is an active pipe without active ports,
9841          * we may need some idea for the dotclock anyway.
9842          * Calculate one based on the FDI configuration.
9843          */
9844         pipe_config->base.adjusted_mode.crtc_clock =
9845                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9846                                          &pipe_config->fdi_m_n);
9847 }
9848
9849 /** Returns the currently programmed mode of the given pipe. */
9850 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9851                                              struct drm_crtc *crtc)
9852 {
9853         struct drm_i915_private *dev_priv = to_i915(dev);
9854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9855         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9856         struct drm_display_mode *mode;
9857         struct intel_crtc_state *pipe_config;
9858         int htot = I915_READ(HTOTAL(cpu_transcoder));
9859         int hsync = I915_READ(HSYNC(cpu_transcoder));
9860         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9861         int vsync = I915_READ(VSYNC(cpu_transcoder));
9862         enum pipe pipe = intel_crtc->pipe;
9863
9864         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9865         if (!mode)
9866                 return NULL;
9867
9868         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9869         if (!pipe_config) {
9870                 kfree(mode);
9871                 return NULL;
9872         }
9873
9874         /*
9875          * Construct a pipe_config sufficient for getting the clock info
9876          * back out of crtc_clock_get.
9877          *
9878          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9879          * to use a real value here instead.
9880          */
9881         pipe_config->cpu_transcoder = (enum transcoder) pipe;
9882         pipe_config->pixel_multiplier = 1;
9883         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9884         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9885         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9886         i9xx_crtc_clock_get(intel_crtc, pipe_config);
9887
9888         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9889         mode->hdisplay = (htot & 0xffff) + 1;
9890         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9891         mode->hsync_start = (hsync & 0xffff) + 1;
9892         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9893         mode->vdisplay = (vtot & 0xffff) + 1;
9894         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9895         mode->vsync_start = (vsync & 0xffff) + 1;
9896         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9897
9898         drm_mode_set_name(mode);
9899
9900         kfree(pipe_config);
9901
9902         return mode;
9903 }
9904
9905 static void intel_crtc_destroy(struct drm_crtc *crtc)
9906 {
9907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9908         struct drm_device *dev = crtc->dev;
9909         struct intel_flip_work *work;
9910
9911         spin_lock_irq(&dev->event_lock);
9912         work = intel_crtc->flip_work;
9913         intel_crtc->flip_work = NULL;
9914         spin_unlock_irq(&dev->event_lock);
9915
9916         if (work) {
9917                 cancel_work_sync(&work->mmio_work);
9918                 cancel_work_sync(&work->unpin_work);
9919                 kfree(work);
9920         }
9921
9922         drm_crtc_cleanup(crtc);
9923
9924         kfree(intel_crtc);
9925 }
9926
9927 static void intel_unpin_work_fn(struct work_struct *__work)
9928 {
9929         struct intel_flip_work *work =
9930                 container_of(__work, struct intel_flip_work, unpin_work);
9931         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9932         struct drm_device *dev = crtc->base.dev;
9933         struct drm_plane *primary = crtc->base.primary;
9934
9935         if (is_mmio_work(work))
9936                 flush_work(&work->mmio_work);
9937
9938         mutex_lock(&dev->struct_mutex);
9939         intel_unpin_fb_vma(work->old_vma);
9940         i915_gem_object_put(work->pending_flip_obj);
9941         mutex_unlock(&dev->struct_mutex);
9942
9943         i915_gem_request_put(work->flip_queued_req);
9944
9945         intel_frontbuffer_flip_complete(to_i915(dev),
9946                                         to_intel_plane(primary)->frontbuffer_bit);
9947         intel_fbc_post_update(crtc);
9948         drm_framebuffer_unreference(work->old_fb);
9949
9950         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9951         atomic_dec(&crtc->unpin_work_count);
9952
9953         kfree(work);
9954 }
9955
9956 /* Is 'a' after or equal to 'b'? */
9957 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9958 {
9959         return !((a - b) & 0x80000000);
9960 }
9961
9962 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9963                                    struct intel_flip_work *work)
9964 {
9965         struct drm_device *dev = crtc->base.dev;
9966         struct drm_i915_private *dev_priv = to_i915(dev);
9967
9968         if (abort_flip_on_reset(crtc))
9969                 return true;
9970
9971         /*
9972          * The relevant registers doen't exist on pre-ctg.
9973          * As the flip done interrupt doesn't trigger for mmio
9974          * flips on gmch platforms, a flip count check isn't
9975          * really needed there. But since ctg has the registers,
9976          * include it in the check anyway.
9977          */
9978         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9979                 return true;
9980
9981         /*
9982          * BDW signals flip done immediately if the plane
9983          * is disabled, even if the plane enable is already
9984          * armed to occur at the next vblank :(
9985          */
9986
9987         /*
9988          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9989          * used the same base address. In that case the mmio flip might
9990          * have completed, but the CS hasn't even executed the flip yet.
9991          *
9992          * A flip count check isn't enough as the CS might have updated
9993          * the base address just after start of vblank, but before we
9994          * managed to process the interrupt. This means we'd complete the
9995          * CS flip too soon.
9996          *
9997          * Combining both checks should get us a good enough result. It may
9998          * still happen that the CS flip has been executed, but has not
9999          * yet actually completed. But in case the base address is the same
10000          * anyway, we don't really care.
10001          */
10002         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10003                 crtc->flip_work->gtt_offset &&
10004                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10005                                     crtc->flip_work->flip_count);
10006 }
10007
10008 static bool
10009 __pageflip_finished_mmio(struct intel_crtc *crtc,
10010                                struct intel_flip_work *work)
10011 {
10012         /*
10013          * MMIO work completes when vblank is different from
10014          * flip_queued_vblank.
10015          *
10016          * Reset counter value doesn't matter, this is handled by
10017          * i915_wait_request finishing early, so no need to handle
10018          * reset here.
10019          */
10020         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10021 }
10022
10023
10024 static bool pageflip_finished(struct intel_crtc *crtc,
10025                               struct intel_flip_work *work)
10026 {
10027         if (!atomic_read(&work->pending))
10028                 return false;
10029
10030         smp_rmb();
10031
10032         if (is_mmio_work(work))
10033                 return __pageflip_finished_mmio(crtc, work);
10034         else
10035                 return __pageflip_finished_cs(crtc, work);
10036 }
10037
10038 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10039 {
10040         struct drm_device *dev = &dev_priv->drm;
10041         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10042         struct intel_flip_work *work;
10043         unsigned long flags;
10044
10045         /* Ignore early vblank irqs */
10046         if (!crtc)
10047                 return;
10048
10049         /*
10050          * This is called both by irq handlers and the reset code (to complete
10051          * lost pageflips) so needs the full irqsave spinlocks.
10052          */
10053         spin_lock_irqsave(&dev->event_lock, flags);
10054         work = crtc->flip_work;
10055
10056         if (work != NULL &&
10057             !is_mmio_work(work) &&
10058             pageflip_finished(crtc, work))
10059                 page_flip_completed(crtc);
10060
10061         spin_unlock_irqrestore(&dev->event_lock, flags);
10062 }
10063
10064 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10065 {
10066         struct drm_device *dev = &dev_priv->drm;
10067         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10068         struct intel_flip_work *work;
10069         unsigned long flags;
10070
10071         /* Ignore early vblank irqs */
10072         if (!crtc)
10073                 return;
10074
10075         /*
10076          * This is called both by irq handlers and the reset code (to complete
10077          * lost pageflips) so needs the full irqsave spinlocks.
10078          */
10079         spin_lock_irqsave(&dev->event_lock, flags);
10080         work = crtc->flip_work;
10081
10082         if (work != NULL &&
10083             is_mmio_work(work) &&
10084             pageflip_finished(crtc, work))
10085                 page_flip_completed(crtc);
10086
10087         spin_unlock_irqrestore(&dev->event_lock, flags);
10088 }
10089
10090 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10091                                                struct intel_flip_work *work)
10092 {
10093         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10094
10095         /* Ensure that the work item is consistent when activating it ... */
10096         smp_mb__before_atomic();
10097         atomic_set(&work->pending, 1);
10098 }
10099
10100 static int intel_gen2_queue_flip(struct drm_device *dev,
10101                                  struct drm_crtc *crtc,
10102                                  struct drm_framebuffer *fb,
10103                                  struct drm_i915_gem_object *obj,
10104                                  struct drm_i915_gem_request *req,
10105                                  uint32_t flags)
10106 {
10107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10108         u32 flip_mask, *cs;
10109
10110         cs = intel_ring_begin(req, 6);
10111         if (IS_ERR(cs))
10112                 return PTR_ERR(cs);
10113
10114         /* Can't queue multiple flips, so wait for the previous
10115          * one to finish before executing the next.
10116          */
10117         if (intel_crtc->plane)
10118                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10119         else
10120                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10121         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10122         *cs++ = MI_NOOP;
10123         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10124         *cs++ = fb->pitches[0];
10125         *cs++ = intel_crtc->flip_work->gtt_offset;
10126         *cs++ = 0; /* aux display base address, unused */
10127
10128         return 0;
10129 }
10130
10131 static int intel_gen3_queue_flip(struct drm_device *dev,
10132                                  struct drm_crtc *crtc,
10133                                  struct drm_framebuffer *fb,
10134                                  struct drm_i915_gem_object *obj,
10135                                  struct drm_i915_gem_request *req,
10136                                  uint32_t flags)
10137 {
10138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10139         u32 flip_mask, *cs;
10140
10141         cs = intel_ring_begin(req, 6);
10142         if (IS_ERR(cs))
10143                 return PTR_ERR(cs);
10144
10145         if (intel_crtc->plane)
10146                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10147         else
10148                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10149         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10150         *cs++ = MI_NOOP;
10151         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10152         *cs++ = fb->pitches[0];
10153         *cs++ = intel_crtc->flip_work->gtt_offset;
10154         *cs++ = MI_NOOP;
10155
10156         return 0;
10157 }
10158
10159 static int intel_gen4_queue_flip(struct drm_device *dev,
10160                                  struct drm_crtc *crtc,
10161                                  struct drm_framebuffer *fb,
10162                                  struct drm_i915_gem_object *obj,
10163                                  struct drm_i915_gem_request *req,
10164                                  uint32_t flags)
10165 {
10166         struct drm_i915_private *dev_priv = to_i915(dev);
10167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10168         u32 pf, pipesrc, *cs;
10169
10170         cs = intel_ring_begin(req, 4);
10171         if (IS_ERR(cs))
10172                 return PTR_ERR(cs);
10173
10174         /* i965+ uses the linear or tiled offsets from the
10175          * Display Registers (which do not change across a page-flip)
10176          * so we need only reprogram the base address.
10177          */
10178         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10179         *cs++ = fb->pitches[0];
10180         *cs++ = intel_crtc->flip_work->gtt_offset |
10181                 intel_fb_modifier_to_tiling(fb->modifier);
10182
10183         /* XXX Enabling the panel-fitter across page-flip is so far
10184          * untested on non-native modes, so ignore it for now.
10185          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10186          */
10187         pf = 0;
10188         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10189         *cs++ = pf | pipesrc;
10190
10191         return 0;
10192 }
10193
10194 static int intel_gen6_queue_flip(struct drm_device *dev,
10195                                  struct drm_crtc *crtc,
10196                                  struct drm_framebuffer *fb,
10197                                  struct drm_i915_gem_object *obj,
10198                                  struct drm_i915_gem_request *req,
10199                                  uint32_t flags)
10200 {
10201         struct drm_i915_private *dev_priv = to_i915(dev);
10202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10203         u32 pf, pipesrc, *cs;
10204
10205         cs = intel_ring_begin(req, 4);
10206         if (IS_ERR(cs))
10207                 return PTR_ERR(cs);
10208
10209         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10210         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10211         *cs++ = intel_crtc->flip_work->gtt_offset;
10212
10213         /* Contrary to the suggestions in the documentation,
10214          * "Enable Panel Fitter" does not seem to be required when page
10215          * flipping with a non-native mode, and worse causes a normal
10216          * modeset to fail.
10217          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10218          */
10219         pf = 0;
10220         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10221         *cs++ = pf | pipesrc;
10222
10223         return 0;
10224 }
10225
10226 static int intel_gen7_queue_flip(struct drm_device *dev,
10227                                  struct drm_crtc *crtc,
10228                                  struct drm_framebuffer *fb,
10229                                  struct drm_i915_gem_object *obj,
10230                                  struct drm_i915_gem_request *req,
10231                                  uint32_t flags)
10232 {
10233         struct drm_i915_private *dev_priv = to_i915(dev);
10234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10235         u32 *cs, plane_bit = 0;
10236         int len, ret;
10237
10238         switch (intel_crtc->plane) {
10239         case PLANE_A:
10240                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10241                 break;
10242         case PLANE_B:
10243                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10244                 break;
10245         case PLANE_C:
10246                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10247                 break;
10248         default:
10249                 WARN_ONCE(1, "unknown plane in flip command\n");
10250                 return -ENODEV;
10251         }
10252
10253         len = 4;
10254         if (req->engine->id == RCS) {
10255                 len += 6;
10256                 /*
10257                  * On Gen 8, SRM is now taking an extra dword to accommodate
10258                  * 48bits addresses, and we need a NOOP for the batch size to
10259                  * stay even.
10260                  */
10261                 if (IS_GEN8(dev_priv))
10262                         len += 2;
10263         }
10264
10265         /*
10266          * BSpec MI_DISPLAY_FLIP for IVB:
10267          * "The full packet must be contained within the same cache line."
10268          *
10269          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10270          * cacheline, if we ever start emitting more commands before
10271          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10272          * then do the cacheline alignment, and finally emit the
10273          * MI_DISPLAY_FLIP.
10274          */
10275         ret = intel_ring_cacheline_align(req);
10276         if (ret)
10277                 return ret;
10278
10279         cs = intel_ring_begin(req, len);
10280         if (IS_ERR(cs))
10281                 return PTR_ERR(cs);
10282
10283         /* Unmask the flip-done completion message. Note that the bspec says that
10284          * we should do this for both the BCS and RCS, and that we must not unmask
10285          * more than one flip event at any time (or ensure that one flip message
10286          * can be sent by waiting for flip-done prior to queueing new flips).
10287          * Experimentation says that BCS works despite DERRMR masking all
10288          * flip-done completion events and that unmasking all planes at once
10289          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10290          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10291          */
10292         if (req->engine->id == RCS) {
10293                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10294                 *cs++ = i915_mmio_reg_offset(DERRMR);
10295                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10296                           DERRMR_PIPEB_PRI_FLIP_DONE |
10297                           DERRMR_PIPEC_PRI_FLIP_DONE);
10298                 if (IS_GEN8(dev_priv))
10299                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10300                                 MI_SRM_LRM_GLOBAL_GTT;
10301                 else
10302                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10303                 *cs++ = i915_mmio_reg_offset(DERRMR);
10304                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10305                 if (IS_GEN8(dev_priv)) {
10306                         *cs++ = 0;
10307                         *cs++ = MI_NOOP;
10308                 }
10309         }
10310
10311         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10312         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10313         *cs++ = intel_crtc->flip_work->gtt_offset;
10314         *cs++ = MI_NOOP;
10315
10316         return 0;
10317 }
10318
10319 static bool use_mmio_flip(struct intel_engine_cs *engine,
10320                           struct drm_i915_gem_object *obj)
10321 {
10322         /*
10323          * This is not being used for older platforms, because
10324          * non-availability of flip done interrupt forces us to use
10325          * CS flips. Older platforms derive flip done using some clever
10326          * tricks involving the flip_pending status bits and vblank irqs.
10327          * So using MMIO flips there would disrupt this mechanism.
10328          */
10329
10330         if (engine == NULL)
10331                 return true;
10332
10333         if (INTEL_GEN(engine->i915) < 5)
10334                 return false;
10335
10336         if (i915.use_mmio_flip < 0)
10337                 return false;
10338         else if (i915.use_mmio_flip > 0)
10339                 return true;
10340         else if (i915.enable_execlists)
10341                 return true;
10342
10343         return engine != i915_gem_object_last_write_engine(obj);
10344 }
10345
10346 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10347                              unsigned int rotation,
10348                              struct intel_flip_work *work)
10349 {
10350         struct drm_device *dev = intel_crtc->base.dev;
10351         struct drm_i915_private *dev_priv = to_i915(dev);
10352         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10353         const enum pipe pipe = intel_crtc->pipe;
10354         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10355
10356         ctl = I915_READ(PLANE_CTL(pipe, 0));
10357         ctl &= ~PLANE_CTL_TILED_MASK;
10358         switch (fb->modifier) {
10359         case DRM_FORMAT_MOD_LINEAR:
10360                 break;
10361         case I915_FORMAT_MOD_X_TILED:
10362                 ctl |= PLANE_CTL_TILED_X;
10363                 break;
10364         case I915_FORMAT_MOD_Y_TILED:
10365                 ctl |= PLANE_CTL_TILED_Y;
10366                 break;
10367         case I915_FORMAT_MOD_Yf_TILED:
10368                 ctl |= PLANE_CTL_TILED_YF;
10369                 break;
10370         default:
10371                 MISSING_CASE(fb->modifier);
10372         }
10373
10374         /*
10375          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10376          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10377          */
10378         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10379         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10380
10381         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10382         POSTING_READ(PLANE_SURF(pipe, 0));
10383 }
10384
10385 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10386                              struct intel_flip_work *work)
10387 {
10388         struct drm_device *dev = intel_crtc->base.dev;
10389         struct drm_i915_private *dev_priv = to_i915(dev);
10390         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10391         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10392         u32 dspcntr;
10393
10394         dspcntr = I915_READ(reg);
10395
10396         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10397                 dspcntr |= DISPPLANE_TILED;
10398         else
10399                 dspcntr &= ~DISPPLANE_TILED;
10400
10401         I915_WRITE(reg, dspcntr);
10402
10403         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10404         POSTING_READ(DSPSURF(intel_crtc->plane));
10405 }
10406
10407 static void intel_mmio_flip_work_func(struct work_struct *w)
10408 {
10409         struct intel_flip_work *work =
10410                 container_of(w, struct intel_flip_work, mmio_work);
10411         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10412         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10413         struct intel_framebuffer *intel_fb =
10414                 to_intel_framebuffer(crtc->base.primary->fb);
10415         struct drm_i915_gem_object *obj = intel_fb->obj;
10416
10417         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10418
10419         intel_pipe_update_start(crtc);
10420
10421         if (INTEL_GEN(dev_priv) >= 9)
10422                 skl_do_mmio_flip(crtc, work->rotation, work);
10423         else
10424                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10425                 ilk_do_mmio_flip(crtc, work);
10426
10427         intel_pipe_update_end(crtc, work);
10428 }
10429
10430 static int intel_default_queue_flip(struct drm_device *dev,
10431                                     struct drm_crtc *crtc,
10432                                     struct drm_framebuffer *fb,
10433                                     struct drm_i915_gem_object *obj,
10434                                     struct drm_i915_gem_request *req,
10435                                     uint32_t flags)
10436 {
10437         return -ENODEV;
10438 }
10439
10440 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10441                                       struct intel_crtc *intel_crtc,
10442                                       struct intel_flip_work *work)
10443 {
10444         u32 addr, vblank;
10445
10446         if (!atomic_read(&work->pending))
10447                 return false;
10448
10449         smp_rmb();
10450
10451         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10452         if (work->flip_ready_vblank == 0) {
10453                 if (work->flip_queued_req &&
10454                     !i915_gem_request_completed(work->flip_queued_req))
10455                         return false;
10456
10457                 work->flip_ready_vblank = vblank;
10458         }
10459
10460         if (vblank - work->flip_ready_vblank < 3)
10461                 return false;
10462
10463         /* Potential stall - if we see that the flip has happened,
10464          * assume a missed interrupt. */
10465         if (INTEL_GEN(dev_priv) >= 4)
10466                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10467         else
10468                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10469
10470         /* There is a potential issue here with a false positive after a flip
10471          * to the same address. We could address this by checking for a
10472          * non-incrementing frame counter.
10473          */
10474         return addr == work->gtt_offset;
10475 }
10476
10477 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10478 {
10479         struct drm_device *dev = &dev_priv->drm;
10480         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10481         struct intel_flip_work *work;
10482
10483         WARN_ON(!in_interrupt());
10484
10485         if (crtc == NULL)
10486                 return;
10487
10488         spin_lock(&dev->event_lock);
10489         work = crtc->flip_work;
10490
10491         if (work != NULL && !is_mmio_work(work) &&
10492             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10493                 WARN_ONCE(1,
10494                           "Kicking stuck page flip: queued at %d, now %d\n",
10495                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10496                 page_flip_completed(crtc);
10497                 work = NULL;
10498         }
10499
10500         if (work != NULL && !is_mmio_work(work) &&
10501             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10502                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10503         spin_unlock(&dev->event_lock);
10504 }
10505
10506 __maybe_unused
10507 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10508                                 struct drm_framebuffer *fb,
10509                                 struct drm_pending_vblank_event *event,
10510                                 uint32_t page_flip_flags)
10511 {
10512         struct drm_device *dev = crtc->dev;
10513         struct drm_i915_private *dev_priv = to_i915(dev);
10514         struct drm_framebuffer *old_fb = crtc->primary->fb;
10515         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10517         struct drm_plane *primary = crtc->primary;
10518         enum pipe pipe = intel_crtc->pipe;
10519         struct intel_flip_work *work;
10520         struct intel_engine_cs *engine;
10521         bool mmio_flip;
10522         struct drm_i915_gem_request *request;
10523         struct i915_vma *vma;
10524         int ret;
10525
10526         /*
10527          * drm_mode_page_flip_ioctl() should already catch this, but double
10528          * check to be safe.  In the future we may enable pageflipping from
10529          * a disabled primary plane.
10530          */
10531         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10532                 return -EBUSY;
10533
10534         /* Can't change pixel format via MI display flips. */
10535         if (fb->format != crtc->primary->fb->format)
10536                 return -EINVAL;
10537
10538         /*
10539          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10540          * Note that pitch changes could also affect these register.
10541          */
10542         if (INTEL_GEN(dev_priv) > 3 &&
10543             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10544              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10545                 return -EINVAL;
10546
10547         if (i915_terminally_wedged(&dev_priv->gpu_error))
10548                 goto out_hang;
10549
10550         work = kzalloc(sizeof(*work), GFP_KERNEL);
10551         if (work == NULL)
10552                 return -ENOMEM;
10553
10554         work->event = event;
10555         work->crtc = crtc;
10556         work->old_fb = old_fb;
10557         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10558
10559         ret = drm_crtc_vblank_get(crtc);
10560         if (ret)
10561                 goto free_work;
10562
10563         /* We borrow the event spin lock for protecting flip_work */
10564         spin_lock_irq(&dev->event_lock);
10565         if (intel_crtc->flip_work) {
10566                 /* Before declaring the flip queue wedged, check if
10567                  * the hardware completed the operation behind our backs.
10568                  */
10569                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10570                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10571                         page_flip_completed(intel_crtc);
10572                 } else {
10573                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10574                         spin_unlock_irq(&dev->event_lock);
10575
10576                         drm_crtc_vblank_put(crtc);
10577                         kfree(work);
10578                         return -EBUSY;
10579                 }
10580         }
10581         intel_crtc->flip_work = work;
10582         spin_unlock_irq(&dev->event_lock);
10583
10584         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10585                 flush_workqueue(dev_priv->wq);
10586
10587         /* Reference the objects for the scheduled work. */
10588         drm_framebuffer_reference(work->old_fb);
10589
10590         crtc->primary->fb = fb;
10591         update_state_fb(crtc->primary);
10592
10593         work->pending_flip_obj = i915_gem_object_get(obj);
10594
10595         ret = i915_mutex_lock_interruptible(dev);
10596         if (ret)
10597                 goto cleanup;
10598
10599         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10600         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10601                 ret = -EIO;
10602                 goto unlock;
10603         }
10604
10605         atomic_inc(&intel_crtc->unpin_work_count);
10606
10607         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10608                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10609
10610         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10611                 engine = dev_priv->engine[BCS];
10612                 if (fb->modifier != old_fb->modifier)
10613                         /* vlv: DISPLAY_FLIP fails to change tiling */
10614                         engine = NULL;
10615         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10616                 engine = dev_priv->engine[BCS];
10617         } else if (INTEL_GEN(dev_priv) >= 7) {
10618                 engine = i915_gem_object_last_write_engine(obj);
10619                 if (engine == NULL || engine->id != RCS)
10620                         engine = dev_priv->engine[BCS];
10621         } else {
10622                 engine = dev_priv->engine[RCS];
10623         }
10624
10625         mmio_flip = use_mmio_flip(engine, obj);
10626
10627         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10628         if (IS_ERR(vma)) {
10629                 ret = PTR_ERR(vma);
10630                 goto cleanup_pending;
10631         }
10632
10633         work->old_vma = to_intel_plane_state(primary->state)->vma;
10634         to_intel_plane_state(primary->state)->vma = vma;
10635
10636         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10637         work->rotation = crtc->primary->state->rotation;
10638
10639         /*
10640          * There's the potential that the next frame will not be compatible with
10641          * FBC, so we want to call pre_update() before the actual page flip.
10642          * The problem is that pre_update() caches some information about the fb
10643          * object, so we want to do this only after the object is pinned. Let's
10644          * be on the safe side and do this immediately before scheduling the
10645          * flip.
10646          */
10647         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10648                              to_intel_plane_state(primary->state));
10649
10650         if (mmio_flip) {
10651                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10652                 queue_work(system_unbound_wq, &work->mmio_work);
10653         } else {
10654                 request = i915_gem_request_alloc(engine,
10655                                                  dev_priv->kernel_context);
10656                 if (IS_ERR(request)) {
10657                         ret = PTR_ERR(request);
10658                         goto cleanup_unpin;
10659                 }
10660
10661                 ret = i915_gem_request_await_object(request, obj, false);
10662                 if (ret)
10663                         goto cleanup_request;
10664
10665                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10666                                                    page_flip_flags);
10667                 if (ret)
10668                         goto cleanup_request;
10669
10670                 intel_mark_page_flip_active(intel_crtc, work);
10671
10672                 work->flip_queued_req = i915_gem_request_get(request);
10673                 i915_add_request(request);
10674         }
10675
10676         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10677         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10678                           to_intel_plane(primary)->frontbuffer_bit);
10679         mutex_unlock(&dev->struct_mutex);
10680
10681         intel_frontbuffer_flip_prepare(to_i915(dev),
10682                                        to_intel_plane(primary)->frontbuffer_bit);
10683
10684         trace_i915_flip_request(intel_crtc->plane, obj);
10685
10686         return 0;
10687
10688 cleanup_request:
10689         i915_add_request(request);
10690 cleanup_unpin:
10691         to_intel_plane_state(primary->state)->vma = work->old_vma;
10692         intel_unpin_fb_vma(vma);
10693 cleanup_pending:
10694         atomic_dec(&intel_crtc->unpin_work_count);
10695 unlock:
10696         mutex_unlock(&dev->struct_mutex);
10697 cleanup:
10698         crtc->primary->fb = old_fb;
10699         update_state_fb(crtc->primary);
10700
10701         i915_gem_object_put(obj);
10702         drm_framebuffer_unreference(work->old_fb);
10703
10704         spin_lock_irq(&dev->event_lock);
10705         intel_crtc->flip_work = NULL;
10706         spin_unlock_irq(&dev->event_lock);
10707
10708         drm_crtc_vblank_put(crtc);
10709 free_work:
10710         kfree(work);
10711
10712         if (ret == -EIO) {
10713                 struct drm_atomic_state *state;
10714                 struct drm_plane_state *plane_state;
10715
10716 out_hang:
10717                 state = drm_atomic_state_alloc(dev);
10718                 if (!state)
10719                         return -ENOMEM;
10720                 state->acquire_ctx = dev->mode_config.acquire_ctx;
10721
10722 retry:
10723                 plane_state = drm_atomic_get_plane_state(state, primary);
10724                 ret = PTR_ERR_OR_ZERO(plane_state);
10725                 if (!ret) {
10726                         drm_atomic_set_fb_for_plane(plane_state, fb);
10727
10728                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10729                         if (!ret)
10730                                 ret = drm_atomic_commit(state);
10731                 }
10732
10733                 if (ret == -EDEADLK) {
10734                         drm_modeset_backoff(state->acquire_ctx);
10735                         drm_atomic_state_clear(state);
10736                         goto retry;
10737                 }
10738
10739                 drm_atomic_state_put(state);
10740
10741                 if (ret == 0 && event) {
10742                         spin_lock_irq(&dev->event_lock);
10743                         drm_crtc_send_vblank_event(crtc, event);
10744                         spin_unlock_irq(&dev->event_lock);
10745                 }
10746         }
10747         return ret;
10748 }
10749
10750
10751 /**
10752  * intel_wm_need_update - Check whether watermarks need updating
10753  * @plane: drm plane
10754  * @state: new plane state
10755  *
10756  * Check current plane state versus the new one to determine whether
10757  * watermarks need to be recalculated.
10758  *
10759  * Returns true or false.
10760  */
10761 static bool intel_wm_need_update(struct drm_plane *plane,
10762                                  struct drm_plane_state *state)
10763 {
10764         struct intel_plane_state *new = to_intel_plane_state(state);
10765         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10766
10767         /* Update watermarks on tiling or size changes. */
10768         if (new->base.visible != cur->base.visible)
10769                 return true;
10770
10771         if (!cur->base.fb || !new->base.fb)
10772                 return false;
10773
10774         if (cur->base.fb->modifier != new->base.fb->modifier ||
10775             cur->base.rotation != new->base.rotation ||
10776             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10777             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10778             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10779             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10780                 return true;
10781
10782         return false;
10783 }
10784
10785 static bool needs_scaling(struct intel_plane_state *state)
10786 {
10787         int src_w = drm_rect_width(&state->base.src) >> 16;
10788         int src_h = drm_rect_height(&state->base.src) >> 16;
10789         int dst_w = drm_rect_width(&state->base.dst);
10790         int dst_h = drm_rect_height(&state->base.dst);
10791
10792         return (src_w != dst_w || src_h != dst_h);
10793 }
10794
10795 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10796                                     struct drm_plane_state *plane_state)
10797 {
10798         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10799         struct drm_crtc *crtc = crtc_state->crtc;
10800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10801         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10802         struct drm_device *dev = crtc->dev;
10803         struct drm_i915_private *dev_priv = to_i915(dev);
10804         struct intel_plane_state *old_plane_state =
10805                 to_intel_plane_state(plane->base.state);
10806         bool mode_changed = needs_modeset(crtc_state);
10807         bool was_crtc_enabled = crtc->state->active;
10808         bool is_crtc_enabled = crtc_state->active;
10809         bool turn_off, turn_on, visible, was_visible;
10810         struct drm_framebuffer *fb = plane_state->fb;
10811         int ret;
10812
10813         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10814                 ret = skl_update_scaler_plane(
10815                         to_intel_crtc_state(crtc_state),
10816                         to_intel_plane_state(plane_state));
10817                 if (ret)
10818                         return ret;
10819         }
10820
10821         was_visible = old_plane_state->base.visible;
10822         visible = plane_state->visible;
10823
10824         if (!was_crtc_enabled && WARN_ON(was_visible))
10825                 was_visible = false;
10826
10827         /*
10828          * Visibility is calculated as if the crtc was on, but
10829          * after scaler setup everything depends on it being off
10830          * when the crtc isn't active.
10831          *
10832          * FIXME this is wrong for watermarks. Watermarks should also
10833          * be computed as if the pipe would be active. Perhaps move
10834          * per-plane wm computation to the .check_plane() hook, and
10835          * only combine the results from all planes in the current place?
10836          */
10837         if (!is_crtc_enabled) {
10838                 plane_state->visible = visible = false;
10839                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10840         }
10841
10842         if (!was_visible && !visible)
10843                 return 0;
10844
10845         if (fb != old_plane_state->base.fb)
10846                 pipe_config->fb_changed = true;
10847
10848         turn_off = was_visible && (!visible || mode_changed);
10849         turn_on = visible && (!was_visible || mode_changed);
10850
10851         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10852                          intel_crtc->base.base.id, intel_crtc->base.name,
10853                          plane->base.base.id, plane->base.name,
10854                          fb ? fb->base.id : -1);
10855
10856         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10857                          plane->base.base.id, plane->base.name,
10858                          was_visible, visible,
10859                          turn_off, turn_on, mode_changed);
10860
10861         if (turn_on) {
10862                 if (INTEL_GEN(dev_priv) < 5)
10863                         pipe_config->update_wm_pre = true;
10864
10865                 /* must disable cxsr around plane enable/disable */
10866                 if (plane->id != PLANE_CURSOR)
10867                         pipe_config->disable_cxsr = true;
10868         } else if (turn_off) {
10869                 if (INTEL_GEN(dev_priv) < 5)
10870                         pipe_config->update_wm_post = true;
10871
10872                 /* must disable cxsr around plane enable/disable */
10873                 if (plane->id != PLANE_CURSOR)
10874                         pipe_config->disable_cxsr = true;
10875         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10876                 if (INTEL_GEN(dev_priv) < 5) {
10877                         /* FIXME bollocks */
10878                         pipe_config->update_wm_pre = true;
10879                         pipe_config->update_wm_post = true;
10880                 }
10881         }
10882
10883         if (visible || was_visible)
10884                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10885
10886         /*
10887          * WaCxSRDisabledForSpriteScaling:ivb
10888          *
10889          * cstate->update_wm was already set above, so this flag will
10890          * take effect when we commit and program watermarks.
10891          */
10892         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10893             needs_scaling(to_intel_plane_state(plane_state)) &&
10894             !needs_scaling(old_plane_state))
10895                 pipe_config->disable_lp_wm = true;
10896
10897         return 0;
10898 }
10899
10900 static bool encoders_cloneable(const struct intel_encoder *a,
10901                                const struct intel_encoder *b)
10902 {
10903         /* masks could be asymmetric, so check both ways */
10904         return a == b || (a->cloneable & (1 << b->type) &&
10905                           b->cloneable & (1 << a->type));
10906 }
10907
10908 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10909                                          struct intel_crtc *crtc,
10910                                          struct intel_encoder *encoder)
10911 {
10912         struct intel_encoder *source_encoder;
10913         struct drm_connector *connector;
10914         struct drm_connector_state *connector_state;
10915         int i;
10916
10917         for_each_new_connector_in_state(state, connector, connector_state, i) {
10918                 if (connector_state->crtc != &crtc->base)
10919                         continue;
10920
10921                 source_encoder =
10922                         to_intel_encoder(connector_state->best_encoder);
10923                 if (!encoders_cloneable(encoder, source_encoder))
10924                         return false;
10925         }
10926
10927         return true;
10928 }
10929
10930 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10931                                    struct drm_crtc_state *crtc_state)
10932 {
10933         struct drm_device *dev = crtc->dev;
10934         struct drm_i915_private *dev_priv = to_i915(dev);
10935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10936         struct intel_crtc_state *pipe_config =
10937                 to_intel_crtc_state(crtc_state);
10938         struct drm_atomic_state *state = crtc_state->state;
10939         int ret;
10940         bool mode_changed = needs_modeset(crtc_state);
10941
10942         if (mode_changed && !crtc_state->active)
10943                 pipe_config->update_wm_post = true;
10944
10945         if (mode_changed && crtc_state->enable &&
10946             dev_priv->display.crtc_compute_clock &&
10947             !WARN_ON(pipe_config->shared_dpll)) {
10948                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10949                                                            pipe_config);
10950                 if (ret)
10951                         return ret;
10952         }
10953
10954         if (crtc_state->color_mgmt_changed) {
10955                 ret = intel_color_check(crtc, crtc_state);
10956                 if (ret)
10957                         return ret;
10958
10959                 /*
10960                  * Changing color management on Intel hardware is
10961                  * handled as part of planes update.
10962                  */
10963                 crtc_state->planes_changed = true;
10964         }
10965
10966         ret = 0;
10967         if (dev_priv->display.compute_pipe_wm) {
10968                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10969                 if (ret) {
10970                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10971                         return ret;
10972                 }
10973         }
10974
10975         if (dev_priv->display.compute_intermediate_wm &&
10976             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10977                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10978                         return 0;
10979
10980                 /*
10981                  * Calculate 'intermediate' watermarks that satisfy both the
10982                  * old state and the new state.  We can program these
10983                  * immediately.
10984                  */
10985                 ret = dev_priv->display.compute_intermediate_wm(dev,
10986                                                                 intel_crtc,
10987                                                                 pipe_config);
10988                 if (ret) {
10989                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10990                         return ret;
10991                 }
10992         } else if (dev_priv->display.compute_intermediate_wm) {
10993                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10994                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10995         }
10996
10997         if (INTEL_GEN(dev_priv) >= 9) {
10998                 if (mode_changed)
10999                         ret = skl_update_scaler_crtc(pipe_config);
11000
11001                 if (!ret)
11002                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11003                                                          pipe_config);
11004         }
11005
11006         return ret;
11007 }
11008
11009 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11010         .atomic_begin = intel_begin_crtc_commit,
11011         .atomic_flush = intel_finish_crtc_commit,
11012         .atomic_check = intel_crtc_atomic_check,
11013 };
11014
11015 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11016 {
11017         struct intel_connector *connector;
11018         struct drm_connector_list_iter conn_iter;
11019
11020         drm_connector_list_iter_begin(dev, &conn_iter);
11021         for_each_intel_connector_iter(connector, &conn_iter) {
11022                 if (connector->base.state->crtc)
11023                         drm_connector_unreference(&connector->base);
11024
11025                 if (connector->base.encoder) {
11026                         connector->base.state->best_encoder =
11027                                 connector->base.encoder;
11028                         connector->base.state->crtc =
11029                                 connector->base.encoder->crtc;
11030
11031                         drm_connector_reference(&connector->base);
11032                 } else {
11033                         connector->base.state->best_encoder = NULL;
11034                         connector->base.state->crtc = NULL;
11035                 }
11036         }
11037         drm_connector_list_iter_end(&conn_iter);
11038 }
11039
11040 static void
11041 connected_sink_compute_bpp(struct intel_connector *connector,
11042                            struct intel_crtc_state *pipe_config)
11043 {
11044         const struct drm_display_info *info = &connector->base.display_info;
11045         int bpp = pipe_config->pipe_bpp;
11046
11047         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11048                       connector->base.base.id,
11049                       connector->base.name);
11050
11051         /* Don't use an invalid EDID bpc value */
11052         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11053                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11054                               bpp, info->bpc * 3);
11055                 pipe_config->pipe_bpp = info->bpc * 3;
11056         }
11057
11058         /* Clamp bpp to 8 on screens without EDID 1.4 */
11059         if (info->bpc == 0 && bpp > 24) {
11060                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11061                               bpp);
11062                 pipe_config->pipe_bpp = 24;
11063         }
11064 }
11065
11066 static int
11067 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11068                           struct intel_crtc_state *pipe_config)
11069 {
11070         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11071         struct drm_atomic_state *state;
11072         struct drm_connector *connector;
11073         struct drm_connector_state *connector_state;
11074         int bpp, i;
11075
11076         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11077             IS_CHERRYVIEW(dev_priv)))
11078                 bpp = 10*3;
11079         else if (INTEL_GEN(dev_priv) >= 5)
11080                 bpp = 12*3;
11081         else
11082                 bpp = 8*3;
11083
11084
11085         pipe_config->pipe_bpp = bpp;
11086
11087         state = pipe_config->base.state;
11088
11089         /* Clamp display bpp to EDID value */
11090         for_each_new_connector_in_state(state, connector, connector_state, i) {
11091                 if (connector_state->crtc != &crtc->base)
11092                         continue;
11093
11094                 connected_sink_compute_bpp(to_intel_connector(connector),
11095                                            pipe_config);
11096         }
11097
11098         return bpp;
11099 }
11100
11101 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11102 {
11103         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11104                         "type: 0x%x flags: 0x%x\n",
11105                 mode->crtc_clock,
11106                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11107                 mode->crtc_hsync_end, mode->crtc_htotal,
11108                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11109                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11110 }
11111
11112 static inline void
11113 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11114                       unsigned int lane_count, struct intel_link_m_n *m_n)
11115 {
11116         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11117                       id, lane_count,
11118                       m_n->gmch_m, m_n->gmch_n,
11119                       m_n->link_m, m_n->link_n, m_n->tu);
11120 }
11121
11122 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11123                                    struct intel_crtc_state *pipe_config,
11124                                    const char *context)
11125 {
11126         struct drm_device *dev = crtc->base.dev;
11127         struct drm_i915_private *dev_priv = to_i915(dev);
11128         struct drm_plane *plane;
11129         struct intel_plane *intel_plane;
11130         struct intel_plane_state *state;
11131         struct drm_framebuffer *fb;
11132
11133         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11134                       crtc->base.base.id, crtc->base.name, context);
11135
11136         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11137                       transcoder_name(pipe_config->cpu_transcoder),
11138                       pipe_config->pipe_bpp, pipe_config->dither);
11139
11140         if (pipe_config->has_pch_encoder)
11141                 intel_dump_m_n_config(pipe_config, "fdi",
11142                                       pipe_config->fdi_lanes,
11143                                       &pipe_config->fdi_m_n);
11144
11145         if (intel_crtc_has_dp_encoder(pipe_config)) {
11146                 intel_dump_m_n_config(pipe_config, "dp m_n",
11147                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11148                 if (pipe_config->has_drrs)
11149                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11150                                               pipe_config->lane_count,
11151                                               &pipe_config->dp_m2_n2);
11152         }
11153
11154         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11155                       pipe_config->has_audio, pipe_config->has_infoframe);
11156
11157         DRM_DEBUG_KMS("requested mode:\n");
11158         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11159         DRM_DEBUG_KMS("adjusted mode:\n");
11160         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11161         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11162         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11163                       pipe_config->port_clock,
11164                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11165                       pipe_config->pixel_rate);
11166
11167         if (INTEL_GEN(dev_priv) >= 9)
11168                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11169                               crtc->num_scalers,
11170                               pipe_config->scaler_state.scaler_users,
11171                               pipe_config->scaler_state.scaler_id);
11172
11173         if (HAS_GMCH_DISPLAY(dev_priv))
11174                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11175                               pipe_config->gmch_pfit.control,
11176                               pipe_config->gmch_pfit.pgm_ratios,
11177                               pipe_config->gmch_pfit.lvds_border_bits);
11178         else
11179                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11180                               pipe_config->pch_pfit.pos,
11181                               pipe_config->pch_pfit.size,
11182                               enableddisabled(pipe_config->pch_pfit.enabled));
11183
11184         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11185                       pipe_config->ips_enabled, pipe_config->double_wide);
11186
11187         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11188
11189         DRM_DEBUG_KMS("planes on this crtc\n");
11190         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11191                 struct drm_format_name_buf format_name;
11192                 intel_plane = to_intel_plane(plane);
11193                 if (intel_plane->pipe != crtc->pipe)
11194                         continue;
11195
11196                 state = to_intel_plane_state(plane->state);
11197                 fb = state->base.fb;
11198                 if (!fb) {
11199                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11200                                       plane->base.id, plane->name, state->scaler_id);
11201                         continue;
11202                 }
11203
11204                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11205                               plane->base.id, plane->name,
11206                               fb->base.id, fb->width, fb->height,
11207                               drm_get_format_name(fb->format->format, &format_name));
11208                 if (INTEL_GEN(dev_priv) >= 9)
11209                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11210                                       state->scaler_id,
11211                                       state->base.src.x1 >> 16,
11212                                       state->base.src.y1 >> 16,
11213                                       drm_rect_width(&state->base.src) >> 16,
11214                                       drm_rect_height(&state->base.src) >> 16,
11215                                       state->base.dst.x1, state->base.dst.y1,
11216                                       drm_rect_width(&state->base.dst),
11217                                       drm_rect_height(&state->base.dst));
11218         }
11219 }
11220
11221 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11222 {
11223         struct drm_device *dev = state->dev;
11224         struct drm_connector *connector;
11225         unsigned int used_ports = 0;
11226         unsigned int used_mst_ports = 0;
11227
11228         /*
11229          * Walk the connector list instead of the encoder
11230          * list to detect the problem on ddi platforms
11231          * where there's just one encoder per digital port.
11232          */
11233         drm_for_each_connector(connector, dev) {
11234                 struct drm_connector_state *connector_state;
11235                 struct intel_encoder *encoder;
11236
11237                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11238                 if (!connector_state)
11239                         connector_state = connector->state;
11240
11241                 if (!connector_state->best_encoder)
11242                         continue;
11243
11244                 encoder = to_intel_encoder(connector_state->best_encoder);
11245
11246                 WARN_ON(!connector_state->crtc);
11247
11248                 switch (encoder->type) {
11249                         unsigned int port_mask;
11250                 case INTEL_OUTPUT_UNKNOWN:
11251                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11252                                 break;
11253                 case INTEL_OUTPUT_DP:
11254                 case INTEL_OUTPUT_HDMI:
11255                 case INTEL_OUTPUT_EDP:
11256                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11257
11258                         /* the same port mustn't appear more than once */
11259                         if (used_ports & port_mask)
11260                                 return false;
11261
11262                         used_ports |= port_mask;
11263                         break;
11264                 case INTEL_OUTPUT_DP_MST:
11265                         used_mst_ports |=
11266                                 1 << enc_to_mst(&encoder->base)->primary->port;
11267                         break;
11268                 default:
11269                         break;
11270                 }
11271         }
11272
11273         /* can't mix MST and SST/HDMI on the same port */
11274         if (used_ports & used_mst_ports)
11275                 return false;
11276
11277         return true;
11278 }
11279
11280 static void
11281 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11282 {
11283         struct drm_i915_private *dev_priv =
11284                 to_i915(crtc_state->base.crtc->dev);
11285         struct intel_crtc_scaler_state scaler_state;
11286         struct intel_dpll_hw_state dpll_hw_state;
11287         struct intel_shared_dpll *shared_dpll;
11288         struct intel_crtc_wm_state wm_state;
11289         bool force_thru;
11290
11291         /* FIXME: before the switch to atomic started, a new pipe_config was
11292          * kzalloc'd. Code that depends on any field being zero should be
11293          * fixed, so that the crtc_state can be safely duplicated. For now,
11294          * only fields that are know to not cause problems are preserved. */
11295
11296         scaler_state = crtc_state->scaler_state;
11297         shared_dpll = crtc_state->shared_dpll;
11298         dpll_hw_state = crtc_state->dpll_hw_state;
11299         force_thru = crtc_state->pch_pfit.force_thru;
11300         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11301                 wm_state = crtc_state->wm;
11302
11303         /* Keep base drm_crtc_state intact, only clear our extended struct */
11304         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11305         memset(&crtc_state->base + 1, 0,
11306                sizeof(*crtc_state) - sizeof(crtc_state->base));
11307
11308         crtc_state->scaler_state = scaler_state;
11309         crtc_state->shared_dpll = shared_dpll;
11310         crtc_state->dpll_hw_state = dpll_hw_state;
11311         crtc_state->pch_pfit.force_thru = force_thru;
11312         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11313                 crtc_state->wm = wm_state;
11314 }
11315
11316 static int
11317 intel_modeset_pipe_config(struct drm_crtc *crtc,
11318                           struct intel_crtc_state *pipe_config)
11319 {
11320         struct drm_atomic_state *state = pipe_config->base.state;
11321         struct intel_encoder *encoder;
11322         struct drm_connector *connector;
11323         struct drm_connector_state *connector_state;
11324         int base_bpp, ret = -EINVAL;
11325         int i;
11326         bool retry = true;
11327
11328         clear_intel_crtc_state(pipe_config);
11329
11330         pipe_config->cpu_transcoder =
11331                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11332
11333         /*
11334          * Sanitize sync polarity flags based on requested ones. If neither
11335          * positive or negative polarity is requested, treat this as meaning
11336          * negative polarity.
11337          */
11338         if (!(pipe_config->base.adjusted_mode.flags &
11339               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11340                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11341
11342         if (!(pipe_config->base.adjusted_mode.flags &
11343               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11344                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11345
11346         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11347                                              pipe_config);
11348         if (base_bpp < 0)
11349                 goto fail;
11350
11351         /*
11352          * Determine the real pipe dimensions. Note that stereo modes can
11353          * increase the actual pipe size due to the frame doubling and
11354          * insertion of additional space for blanks between the frame. This
11355          * is stored in the crtc timings. We use the requested mode to do this
11356          * computation to clearly distinguish it from the adjusted mode, which
11357          * can be changed by the connectors in the below retry loop.
11358          */
11359         drm_mode_get_hv_timing(&pipe_config->base.mode,
11360                                &pipe_config->pipe_src_w,
11361                                &pipe_config->pipe_src_h);
11362
11363         for_each_new_connector_in_state(state, connector, connector_state, i) {
11364                 if (connector_state->crtc != crtc)
11365                         continue;
11366
11367                 encoder = to_intel_encoder(connector_state->best_encoder);
11368
11369                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11370                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11371                         goto fail;
11372                 }
11373
11374                 /*
11375                  * Determine output_types before calling the .compute_config()
11376                  * hooks so that the hooks can use this information safely.
11377                  */
11378                 pipe_config->output_types |= 1 << encoder->type;
11379         }
11380
11381 encoder_retry:
11382         /* Ensure the port clock defaults are reset when retrying. */
11383         pipe_config->port_clock = 0;
11384         pipe_config->pixel_multiplier = 1;
11385
11386         /* Fill in default crtc timings, allow encoders to overwrite them. */
11387         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11388                               CRTC_STEREO_DOUBLE);
11389
11390         /* Pass our mode to the connectors and the CRTC to give them a chance to
11391          * adjust it according to limitations or connector properties, and also
11392          * a chance to reject the mode entirely.
11393          */
11394         for_each_new_connector_in_state(state, connector, connector_state, i) {
11395                 if (connector_state->crtc != crtc)
11396                         continue;
11397
11398                 encoder = to_intel_encoder(connector_state->best_encoder);
11399
11400                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11401                         DRM_DEBUG_KMS("Encoder config failure\n");
11402                         goto fail;
11403                 }
11404         }
11405
11406         /* Set default port clock if not overwritten by the encoder. Needs to be
11407          * done afterwards in case the encoder adjusts the mode. */
11408         if (!pipe_config->port_clock)
11409                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11410                         * pipe_config->pixel_multiplier;
11411
11412         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11413         if (ret < 0) {
11414                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11415                 goto fail;
11416         }
11417
11418         if (ret == RETRY) {
11419                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11420                         ret = -EINVAL;
11421                         goto fail;
11422                 }
11423
11424                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11425                 retry = false;
11426                 goto encoder_retry;
11427         }
11428
11429         /* Dithering seems to not pass-through bits correctly when it should, so
11430          * only enable it on 6bpc panels and when its not a compliance
11431          * test requesting 6bpc video pattern.
11432          */
11433         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11434                 !pipe_config->dither_force_disable;
11435         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11436                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11437
11438 fail:
11439         return ret;
11440 }
11441
11442 static void
11443 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11444 {
11445         struct drm_crtc *crtc;
11446         struct drm_crtc_state *new_crtc_state;
11447         int i;
11448
11449         /* Double check state. */
11450         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11451                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11452
11453                 /* Update hwmode for vblank functions */
11454                 if (new_crtc_state->active)
11455                         crtc->hwmode = new_crtc_state->adjusted_mode;
11456                 else
11457                         crtc->hwmode.crtc_clock = 0;
11458
11459                 /*
11460                  * Update legacy state to satisfy fbc code. This can
11461                  * be removed when fbc uses the atomic state.
11462                  */
11463                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11464                         struct drm_plane_state *plane_state = crtc->primary->state;
11465
11466                         crtc->primary->fb = plane_state->fb;
11467                         crtc->x = plane_state->src_x >> 16;
11468                         crtc->y = plane_state->src_y >> 16;
11469                 }
11470         }
11471 }
11472
11473 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11474 {
11475         int diff;
11476
11477         if (clock1 == clock2)
11478                 return true;
11479
11480         if (!clock1 || !clock2)
11481                 return false;
11482
11483         diff = abs(clock1 - clock2);
11484
11485         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11486                 return true;
11487
11488         return false;
11489 }
11490
11491 static bool
11492 intel_compare_m_n(unsigned int m, unsigned int n,
11493                   unsigned int m2, unsigned int n2,
11494                   bool exact)
11495 {
11496         if (m == m2 && n == n2)
11497                 return true;
11498
11499         if (exact || !m || !n || !m2 || !n2)
11500                 return false;
11501
11502         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11503
11504         if (n > n2) {
11505                 while (n > n2) {
11506                         m2 <<= 1;
11507                         n2 <<= 1;
11508                 }
11509         } else if (n < n2) {
11510                 while (n < n2) {
11511                         m <<= 1;
11512                         n <<= 1;
11513                 }
11514         }
11515
11516         if (n != n2)
11517                 return false;
11518
11519         return intel_fuzzy_clock_check(m, m2);
11520 }
11521
11522 static bool
11523 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11524                        struct intel_link_m_n *m2_n2,
11525                        bool adjust)
11526 {
11527         if (m_n->tu == m2_n2->tu &&
11528             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11529                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11530             intel_compare_m_n(m_n->link_m, m_n->link_n,
11531                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11532                 if (adjust)
11533                         *m2_n2 = *m_n;
11534
11535                 return true;
11536         }
11537
11538         return false;
11539 }
11540
11541 static void __printf(3, 4)
11542 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11543 {
11544         char *level;
11545         unsigned int category;
11546         struct va_format vaf;
11547         va_list args;
11548
11549         if (adjust) {
11550                 level = KERN_DEBUG;
11551                 category = DRM_UT_KMS;
11552         } else {
11553                 level = KERN_ERR;
11554                 category = DRM_UT_NONE;
11555         }
11556
11557         va_start(args, format);
11558         vaf.fmt = format;
11559         vaf.va = &args;
11560
11561         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11562
11563         va_end(args);
11564 }
11565
11566 static bool
11567 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11568                           struct intel_crtc_state *current_config,
11569                           struct intel_crtc_state *pipe_config,
11570                           bool adjust)
11571 {
11572         bool ret = true;
11573
11574 #define PIPE_CONF_CHECK_X(name) \
11575         if (current_config->name != pipe_config->name) { \
11576                 pipe_config_err(adjust, __stringify(name), \
11577                           "(expected 0x%08x, found 0x%08x)\n", \
11578                           current_config->name, \
11579                           pipe_config->name); \
11580                 ret = false; \
11581         }
11582
11583 #define PIPE_CONF_CHECK_I(name) \
11584         if (current_config->name != pipe_config->name) { \
11585                 pipe_config_err(adjust, __stringify(name), \
11586                           "(expected %i, found %i)\n", \
11587                           current_config->name, \
11588                           pipe_config->name); \
11589                 ret = false; \
11590         }
11591
11592 #define PIPE_CONF_CHECK_P(name) \
11593         if (current_config->name != pipe_config->name) { \
11594                 pipe_config_err(adjust, __stringify(name), \
11595                           "(expected %p, found %p)\n", \
11596                           current_config->name, \
11597                           pipe_config->name); \
11598                 ret = false; \
11599         }
11600
11601 #define PIPE_CONF_CHECK_M_N(name) \
11602         if (!intel_compare_link_m_n(&current_config->name, \
11603                                     &pipe_config->name,\
11604                                     adjust)) { \
11605                 pipe_config_err(adjust, __stringify(name), \
11606                           "(expected tu %i gmch %i/%i link %i/%i, " \
11607                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11608                           current_config->name.tu, \
11609                           current_config->name.gmch_m, \
11610                           current_config->name.gmch_n, \
11611                           current_config->name.link_m, \
11612                           current_config->name.link_n, \
11613                           pipe_config->name.tu, \
11614                           pipe_config->name.gmch_m, \
11615                           pipe_config->name.gmch_n, \
11616                           pipe_config->name.link_m, \
11617                           pipe_config->name.link_n); \
11618                 ret = false; \
11619         }
11620
11621 /* This is required for BDW+ where there is only one set of registers for
11622  * switching between high and low RR.
11623  * This macro can be used whenever a comparison has to be made between one
11624  * hw state and multiple sw state variables.
11625  */
11626 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11627         if (!intel_compare_link_m_n(&current_config->name, \
11628                                     &pipe_config->name, adjust) && \
11629             !intel_compare_link_m_n(&current_config->alt_name, \
11630                                     &pipe_config->name, adjust)) { \
11631                 pipe_config_err(adjust, __stringify(name), \
11632                           "(expected tu %i gmch %i/%i link %i/%i, " \
11633                           "or tu %i gmch %i/%i link %i/%i, " \
11634                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11635                           current_config->name.tu, \
11636                           current_config->name.gmch_m, \
11637                           current_config->name.gmch_n, \
11638                           current_config->name.link_m, \
11639                           current_config->name.link_n, \
11640                           current_config->alt_name.tu, \
11641                           current_config->alt_name.gmch_m, \
11642                           current_config->alt_name.gmch_n, \
11643                           current_config->alt_name.link_m, \
11644                           current_config->alt_name.link_n, \
11645                           pipe_config->name.tu, \
11646                           pipe_config->name.gmch_m, \
11647                           pipe_config->name.gmch_n, \
11648                           pipe_config->name.link_m, \
11649                           pipe_config->name.link_n); \
11650                 ret = false; \
11651         }
11652
11653 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11654         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11655                 pipe_config_err(adjust, __stringify(name), \
11656                           "(%x) (expected %i, found %i)\n", \
11657                           (mask), \
11658                           current_config->name & (mask), \
11659                           pipe_config->name & (mask)); \
11660                 ret = false; \
11661         }
11662
11663 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11664         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11665                 pipe_config_err(adjust, __stringify(name), \
11666                           "(expected %i, found %i)\n", \
11667                           current_config->name, \
11668                           pipe_config->name); \
11669                 ret = false; \
11670         }
11671
11672 #define PIPE_CONF_QUIRK(quirk)  \
11673         ((current_config->quirks | pipe_config->quirks) & (quirk))
11674
11675         PIPE_CONF_CHECK_I(cpu_transcoder);
11676
11677         PIPE_CONF_CHECK_I(has_pch_encoder);
11678         PIPE_CONF_CHECK_I(fdi_lanes);
11679         PIPE_CONF_CHECK_M_N(fdi_m_n);
11680
11681         PIPE_CONF_CHECK_I(lane_count);
11682         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11683
11684         if (INTEL_GEN(dev_priv) < 8) {
11685                 PIPE_CONF_CHECK_M_N(dp_m_n);
11686
11687                 if (current_config->has_drrs)
11688                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11689         } else
11690                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11691
11692         PIPE_CONF_CHECK_X(output_types);
11693
11694         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11695         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11696         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11697         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11698         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11699         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11700
11701         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11702         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11703         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11704         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11705         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11706         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11707
11708         PIPE_CONF_CHECK_I(pixel_multiplier);
11709         PIPE_CONF_CHECK_I(has_hdmi_sink);
11710         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11711             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11712                 PIPE_CONF_CHECK_I(limited_color_range);
11713
11714         PIPE_CONF_CHECK_I(hdmi_scrambling);
11715         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11716         PIPE_CONF_CHECK_I(has_infoframe);
11717
11718         PIPE_CONF_CHECK_I(has_audio);
11719
11720         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11721                               DRM_MODE_FLAG_INTERLACE);
11722
11723         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11724                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11725                                       DRM_MODE_FLAG_PHSYNC);
11726                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11727                                       DRM_MODE_FLAG_NHSYNC);
11728                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11729                                       DRM_MODE_FLAG_PVSYNC);
11730                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11731                                       DRM_MODE_FLAG_NVSYNC);
11732         }
11733
11734         PIPE_CONF_CHECK_X(gmch_pfit.control);
11735         /* pfit ratios are autocomputed by the hw on gen4+ */
11736         if (INTEL_GEN(dev_priv) < 4)
11737                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11738         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11739
11740         if (!adjust) {
11741                 PIPE_CONF_CHECK_I(pipe_src_w);
11742                 PIPE_CONF_CHECK_I(pipe_src_h);
11743
11744                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11745                 if (current_config->pch_pfit.enabled) {
11746                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11747                         PIPE_CONF_CHECK_X(pch_pfit.size);
11748                 }
11749
11750                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11751                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11752         }
11753
11754         /* BDW+ don't expose a synchronous way to read the state */
11755         if (IS_HASWELL(dev_priv))
11756                 PIPE_CONF_CHECK_I(ips_enabled);
11757
11758         PIPE_CONF_CHECK_I(double_wide);
11759
11760         PIPE_CONF_CHECK_P(shared_dpll);
11761         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11762         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11763         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11764         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11765         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11766         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11767         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11768         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11769         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11770
11771         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11772         PIPE_CONF_CHECK_X(dsi_pll.div);
11773
11774         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11775                 PIPE_CONF_CHECK_I(pipe_bpp);
11776
11777         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11778         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11779
11780 #undef PIPE_CONF_CHECK_X
11781 #undef PIPE_CONF_CHECK_I
11782 #undef PIPE_CONF_CHECK_P
11783 #undef PIPE_CONF_CHECK_FLAGS
11784 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11785 #undef PIPE_CONF_QUIRK
11786
11787         return ret;
11788 }
11789
11790 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11791                                            const struct intel_crtc_state *pipe_config)
11792 {
11793         if (pipe_config->has_pch_encoder) {
11794                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11795                                                             &pipe_config->fdi_m_n);
11796                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11797
11798                 /*
11799                  * FDI already provided one idea for the dotclock.
11800                  * Yell if the encoder disagrees.
11801                  */
11802                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11803                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11804                      fdi_dotclock, dotclock);
11805         }
11806 }
11807
11808 static void verify_wm_state(struct drm_crtc *crtc,
11809                             struct drm_crtc_state *new_state)
11810 {
11811         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11812         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11813         struct skl_pipe_wm hw_wm, *sw_wm;
11814         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11815         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11817         const enum pipe pipe = intel_crtc->pipe;
11818         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11819
11820         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11821                 return;
11822
11823         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11824         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11825
11826         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11827         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11828
11829         /* planes */
11830         for_each_universal_plane(dev_priv, pipe, plane) {
11831                 hw_plane_wm = &hw_wm.planes[plane];
11832                 sw_plane_wm = &sw_wm->planes[plane];
11833
11834                 /* Watermarks */
11835                 for (level = 0; level <= max_level; level++) {
11836                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11837                                                 &sw_plane_wm->wm[level]))
11838                                 continue;
11839
11840                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11841                                   pipe_name(pipe), plane + 1, level,
11842                                   sw_plane_wm->wm[level].plane_en,
11843                                   sw_plane_wm->wm[level].plane_res_b,
11844                                   sw_plane_wm->wm[level].plane_res_l,
11845                                   hw_plane_wm->wm[level].plane_en,
11846                                   hw_plane_wm->wm[level].plane_res_b,
11847                                   hw_plane_wm->wm[level].plane_res_l);
11848                 }
11849
11850                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11851                                          &sw_plane_wm->trans_wm)) {
11852                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11853                                   pipe_name(pipe), plane + 1,
11854                                   sw_plane_wm->trans_wm.plane_en,
11855                                   sw_plane_wm->trans_wm.plane_res_b,
11856                                   sw_plane_wm->trans_wm.plane_res_l,
11857                                   hw_plane_wm->trans_wm.plane_en,
11858                                   hw_plane_wm->trans_wm.plane_res_b,
11859                                   hw_plane_wm->trans_wm.plane_res_l);
11860                 }
11861
11862                 /* DDB */
11863                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11864                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11865
11866                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11867                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11868                                   pipe_name(pipe), plane + 1,
11869                                   sw_ddb_entry->start, sw_ddb_entry->end,
11870                                   hw_ddb_entry->start, hw_ddb_entry->end);
11871                 }
11872         }
11873
11874         /*
11875          * cursor
11876          * If the cursor plane isn't active, we may not have updated it's ddb
11877          * allocation. In that case since the ddb allocation will be updated
11878          * once the plane becomes visible, we can skip this check
11879          */
11880         if (intel_crtc->cursor_addr) {
11881                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11882                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11883
11884                 /* Watermarks */
11885                 for (level = 0; level <= max_level; level++) {
11886                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11887                                                 &sw_plane_wm->wm[level]))
11888                                 continue;
11889
11890                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11891                                   pipe_name(pipe), level,
11892                                   sw_plane_wm->wm[level].plane_en,
11893                                   sw_plane_wm->wm[level].plane_res_b,
11894                                   sw_plane_wm->wm[level].plane_res_l,
11895                                   hw_plane_wm->wm[level].plane_en,
11896                                   hw_plane_wm->wm[level].plane_res_b,
11897                                   hw_plane_wm->wm[level].plane_res_l);
11898                 }
11899
11900                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11901                                          &sw_plane_wm->trans_wm)) {
11902                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11903                                   pipe_name(pipe),
11904                                   sw_plane_wm->trans_wm.plane_en,
11905                                   sw_plane_wm->trans_wm.plane_res_b,
11906                                   sw_plane_wm->trans_wm.plane_res_l,
11907                                   hw_plane_wm->trans_wm.plane_en,
11908                                   hw_plane_wm->trans_wm.plane_res_b,
11909                                   hw_plane_wm->trans_wm.plane_res_l);
11910                 }
11911
11912                 /* DDB */
11913                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11914                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11915
11916                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11917                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11918                                   pipe_name(pipe),
11919                                   sw_ddb_entry->start, sw_ddb_entry->end,
11920                                   hw_ddb_entry->start, hw_ddb_entry->end);
11921                 }
11922         }
11923 }
11924
11925 static void
11926 verify_connector_state(struct drm_device *dev,
11927                        struct drm_atomic_state *state,
11928                        struct drm_crtc *crtc)
11929 {
11930         struct drm_connector *connector;
11931         struct drm_connector_state *new_conn_state;
11932         int i;
11933
11934         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11935                 struct drm_encoder *encoder = connector->encoder;
11936
11937                 if (new_conn_state->crtc != crtc)
11938                         continue;
11939
11940                 intel_connector_verify_state(to_intel_connector(connector));
11941
11942                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11943                      "connector's atomic encoder doesn't match legacy encoder\n");
11944         }
11945 }
11946
11947 static void
11948 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11949 {
11950         struct intel_encoder *encoder;
11951         struct drm_connector *connector;
11952         struct drm_connector_state *old_conn_state, *new_conn_state;
11953         int i;
11954
11955         for_each_intel_encoder(dev, encoder) {
11956                 bool enabled = false, found = false;
11957                 enum pipe pipe;
11958
11959                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11960                               encoder->base.base.id,
11961                               encoder->base.name);
11962
11963                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11964                                                    new_conn_state, i) {
11965                         if (old_conn_state->best_encoder == &encoder->base)
11966                                 found = true;
11967
11968                         if (new_conn_state->best_encoder != &encoder->base)
11969                                 continue;
11970                         found = enabled = true;
11971
11972                         I915_STATE_WARN(new_conn_state->crtc !=
11973                                         encoder->base.crtc,
11974                              "connector's crtc doesn't match encoder crtc\n");
11975                 }
11976
11977                 if (!found)
11978                         continue;
11979
11980                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11981                      "encoder's enabled state mismatch "
11982                      "(expected %i, found %i)\n",
11983                      !!encoder->base.crtc, enabled);
11984
11985                 if (!encoder->base.crtc) {
11986                         bool active;
11987
11988                         active = encoder->get_hw_state(encoder, &pipe);
11989                         I915_STATE_WARN(active,
11990                              "encoder detached but still enabled on pipe %c.\n",
11991                              pipe_name(pipe));
11992                 }
11993         }
11994 }
11995
11996 static void
11997 verify_crtc_state(struct drm_crtc *crtc,
11998                   struct drm_crtc_state *old_crtc_state,
11999                   struct drm_crtc_state *new_crtc_state)
12000 {
12001         struct drm_device *dev = crtc->dev;
12002         struct drm_i915_private *dev_priv = to_i915(dev);
12003         struct intel_encoder *encoder;
12004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12005         struct intel_crtc_state *pipe_config, *sw_config;
12006         struct drm_atomic_state *old_state;
12007         bool active;
12008
12009         old_state = old_crtc_state->state;
12010         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12011         pipe_config = to_intel_crtc_state(old_crtc_state);
12012         memset(pipe_config, 0, sizeof(*pipe_config));
12013         pipe_config->base.crtc = crtc;
12014         pipe_config->base.state = old_state;
12015
12016         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12017
12018         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12019
12020         /* hw state is inconsistent with the pipe quirk */
12021         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12022             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12023                 active = new_crtc_state->active;
12024
12025         I915_STATE_WARN(new_crtc_state->active != active,
12026              "crtc active state doesn't match with hw state "
12027              "(expected %i, found %i)\n", new_crtc_state->active, active);
12028
12029         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12030              "transitional active state does not match atomic hw state "
12031              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12032
12033         for_each_encoder_on_crtc(dev, crtc, encoder) {
12034                 enum pipe pipe;
12035
12036                 active = encoder->get_hw_state(encoder, &pipe);
12037                 I915_STATE_WARN(active != new_crtc_state->active,
12038                         "[ENCODER:%i] active %i with crtc active %i\n",
12039                         encoder->base.base.id, active, new_crtc_state->active);
12040
12041                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12042                                 "Encoder connected to wrong pipe %c\n",
12043                                 pipe_name(pipe));
12044
12045                 if (active) {
12046                         pipe_config->output_types |= 1 << encoder->type;
12047                         encoder->get_config(encoder, pipe_config);
12048                 }
12049         }
12050
12051         intel_crtc_compute_pixel_rate(pipe_config);
12052
12053         if (!new_crtc_state->active)
12054                 return;
12055
12056         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12057
12058         sw_config = to_intel_crtc_state(crtc->state);
12059         if (!intel_pipe_config_compare(dev_priv, sw_config,
12060                                        pipe_config, false)) {
12061                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12062                 intel_dump_pipe_config(intel_crtc, pipe_config,
12063                                        "[hw state]");
12064                 intel_dump_pipe_config(intel_crtc, sw_config,
12065                                        "[sw state]");
12066         }
12067 }
12068
12069 static void
12070 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12071                          struct intel_shared_dpll *pll,
12072                          struct drm_crtc *crtc,
12073                          struct drm_crtc_state *new_state)
12074 {
12075         struct intel_dpll_hw_state dpll_hw_state;
12076         unsigned crtc_mask;
12077         bool active;
12078
12079         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12080
12081         DRM_DEBUG_KMS("%s\n", pll->name);
12082
12083         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12084
12085         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12086                 I915_STATE_WARN(!pll->on && pll->active_mask,
12087                      "pll in active use but not on in sw tracking\n");
12088                 I915_STATE_WARN(pll->on && !pll->active_mask,
12089                      "pll is on but not used by any active crtc\n");
12090                 I915_STATE_WARN(pll->on != active,
12091                      "pll on state mismatch (expected %i, found %i)\n",
12092                      pll->on, active);
12093         }
12094
12095         if (!crtc) {
12096                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12097                                 "more active pll users than references: %x vs %x\n",
12098                                 pll->active_mask, pll->state.crtc_mask);
12099
12100                 return;
12101         }
12102
12103         crtc_mask = 1 << drm_crtc_index(crtc);
12104
12105         if (new_state->active)
12106                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12107                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12108                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12109         else
12110                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12111                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12112                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12113
12114         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12115                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12116                         crtc_mask, pll->state.crtc_mask);
12117
12118         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12119                                           &dpll_hw_state,
12120                                           sizeof(dpll_hw_state)),
12121                         "pll hw state mismatch\n");
12122 }
12123
12124 static void
12125 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12126                          struct drm_crtc_state *old_crtc_state,
12127                          struct drm_crtc_state *new_crtc_state)
12128 {
12129         struct drm_i915_private *dev_priv = to_i915(dev);
12130         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12131         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12132
12133         if (new_state->shared_dpll)
12134                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12135
12136         if (old_state->shared_dpll &&
12137             old_state->shared_dpll != new_state->shared_dpll) {
12138                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12139                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12140
12141                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12142                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12143                                 pipe_name(drm_crtc_index(crtc)));
12144                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12145                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12146                                 pipe_name(drm_crtc_index(crtc)));
12147         }
12148 }
12149
12150 static void
12151 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12152                           struct drm_atomic_state *state,
12153                           struct drm_crtc_state *old_state,
12154                           struct drm_crtc_state *new_state)
12155 {
12156         if (!needs_modeset(new_state) &&
12157             !to_intel_crtc_state(new_state)->update_pipe)
12158                 return;
12159
12160         verify_wm_state(crtc, new_state);
12161         verify_connector_state(crtc->dev, state, crtc);
12162         verify_crtc_state(crtc, old_state, new_state);
12163         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12164 }
12165
12166 static void
12167 verify_disabled_dpll_state(struct drm_device *dev)
12168 {
12169         struct drm_i915_private *dev_priv = to_i915(dev);
12170         int i;
12171
12172         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12173                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12174 }
12175
12176 static void
12177 intel_modeset_verify_disabled(struct drm_device *dev,
12178                               struct drm_atomic_state *state)
12179 {
12180         verify_encoder_state(dev, state);
12181         verify_connector_state(dev, state, NULL);
12182         verify_disabled_dpll_state(dev);
12183 }
12184
12185 static void update_scanline_offset(struct intel_crtc *crtc)
12186 {
12187         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12188
12189         /*
12190          * The scanline counter increments at the leading edge of hsync.
12191          *
12192          * On most platforms it starts counting from vtotal-1 on the
12193          * first active line. That means the scanline counter value is
12194          * always one less than what we would expect. Ie. just after
12195          * start of vblank, which also occurs at start of hsync (on the
12196          * last active line), the scanline counter will read vblank_start-1.
12197          *
12198          * On gen2 the scanline counter starts counting from 1 instead
12199          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12200          * to keep the value positive), instead of adding one.
12201          *
12202          * On HSW+ the behaviour of the scanline counter depends on the output
12203          * type. For DP ports it behaves like most other platforms, but on HDMI
12204          * there's an extra 1 line difference. So we need to add two instead of
12205          * one to the value.
12206          *
12207          * On VLV/CHV DSI the scanline counter would appear to increment
12208          * approx. 1/3 of a scanline before start of vblank. Unfortunately
12209          * that means we can't tell whether we're in vblank or not while
12210          * we're on that particular line. We must still set scanline_offset
12211          * to 1 so that the vblank timestamps come out correct when we query
12212          * the scanline counter from within the vblank interrupt handler.
12213          * However if queried just before the start of vblank we'll get an
12214          * answer that's slightly in the future.
12215          */
12216         if (IS_GEN2(dev_priv)) {
12217                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12218                 int vtotal;
12219
12220                 vtotal = adjusted_mode->crtc_vtotal;
12221                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12222                         vtotal /= 2;
12223
12224                 crtc->scanline_offset = vtotal - 1;
12225         } else if (HAS_DDI(dev_priv) &&
12226                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12227                 crtc->scanline_offset = 2;
12228         } else
12229                 crtc->scanline_offset = 1;
12230 }
12231
12232 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12233 {
12234         struct drm_device *dev = state->dev;
12235         struct drm_i915_private *dev_priv = to_i915(dev);
12236         struct drm_crtc *crtc;
12237         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12238         int i;
12239
12240         if (!dev_priv->display.crtc_compute_clock)
12241                 return;
12242
12243         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12244                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12245                 struct intel_shared_dpll *old_dpll =
12246                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12247
12248                 if (!needs_modeset(new_crtc_state))
12249                         continue;
12250
12251                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12252
12253                 if (!old_dpll)
12254                         continue;
12255
12256                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12257         }
12258 }
12259
12260 /*
12261  * This implements the workaround described in the "notes" section of the mode
12262  * set sequence documentation. When going from no pipes or single pipe to
12263  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12264  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12265  */
12266 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12267 {
12268         struct drm_crtc_state *crtc_state;
12269         struct intel_crtc *intel_crtc;
12270         struct drm_crtc *crtc;
12271         struct intel_crtc_state *first_crtc_state = NULL;
12272         struct intel_crtc_state *other_crtc_state = NULL;
12273         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12274         int i;
12275
12276         /* look at all crtc's that are going to be enabled in during modeset */
12277         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12278                 intel_crtc = to_intel_crtc(crtc);
12279
12280                 if (!crtc_state->active || !needs_modeset(crtc_state))
12281                         continue;
12282
12283                 if (first_crtc_state) {
12284                         other_crtc_state = to_intel_crtc_state(crtc_state);
12285                         break;
12286                 } else {
12287                         first_crtc_state = to_intel_crtc_state(crtc_state);
12288                         first_pipe = intel_crtc->pipe;
12289                 }
12290         }
12291
12292         /* No workaround needed? */
12293         if (!first_crtc_state)
12294                 return 0;
12295
12296         /* w/a possibly needed, check how many crtc's are already enabled. */
12297         for_each_intel_crtc(state->dev, intel_crtc) {
12298                 struct intel_crtc_state *pipe_config;
12299
12300                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12301                 if (IS_ERR(pipe_config))
12302                         return PTR_ERR(pipe_config);
12303
12304                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12305
12306                 if (!pipe_config->base.active ||
12307                     needs_modeset(&pipe_config->base))
12308                         continue;
12309
12310                 /* 2 or more enabled crtcs means no need for w/a */
12311                 if (enabled_pipe != INVALID_PIPE)
12312                         return 0;
12313
12314                 enabled_pipe = intel_crtc->pipe;
12315         }
12316
12317         if (enabled_pipe != INVALID_PIPE)
12318                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12319         else if (other_crtc_state)
12320                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12321
12322         return 0;
12323 }
12324
12325 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12326 {
12327         struct drm_crtc *crtc;
12328
12329         /* Add all pipes to the state */
12330         for_each_crtc(state->dev, crtc) {
12331                 struct drm_crtc_state *crtc_state;
12332
12333                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12334                 if (IS_ERR(crtc_state))
12335                         return PTR_ERR(crtc_state);
12336         }
12337
12338         return 0;
12339 }
12340
12341 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12342 {
12343         struct drm_crtc *crtc;
12344
12345         /*
12346          * Add all pipes to the state, and force
12347          * a modeset on all the active ones.
12348          */
12349         for_each_crtc(state->dev, crtc) {
12350                 struct drm_crtc_state *crtc_state;
12351                 int ret;
12352
12353                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12354                 if (IS_ERR(crtc_state))
12355                         return PTR_ERR(crtc_state);
12356
12357                 if (!crtc_state->active || needs_modeset(crtc_state))
12358                         continue;
12359
12360                 crtc_state->mode_changed = true;
12361
12362                 ret = drm_atomic_add_affected_connectors(state, crtc);
12363                 if (ret)
12364                         return ret;
12365
12366                 ret = drm_atomic_add_affected_planes(state, crtc);
12367                 if (ret)
12368                         return ret;
12369         }
12370
12371         return 0;
12372 }
12373
12374 static int intel_modeset_checks(struct drm_atomic_state *state)
12375 {
12376         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12377         struct drm_i915_private *dev_priv = to_i915(state->dev);
12378         struct drm_crtc *crtc;
12379         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12380         int ret = 0, i;
12381
12382         if (!check_digital_port_conflicts(state)) {
12383                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12384                 return -EINVAL;
12385         }
12386
12387         intel_state->modeset = true;
12388         intel_state->active_crtcs = dev_priv->active_crtcs;
12389         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12390         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12391
12392         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12393                 if (new_crtc_state->active)
12394                         intel_state->active_crtcs |= 1 << i;
12395                 else
12396                         intel_state->active_crtcs &= ~(1 << i);
12397
12398                 if (old_crtc_state->active != new_crtc_state->active)
12399                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12400         }
12401
12402         /*
12403          * See if the config requires any additional preparation, e.g.
12404          * to adjust global state with pipes off.  We need to do this
12405          * here so we can get the modeset_pipe updated config for the new
12406          * mode set on this crtc.  For other crtcs we need to use the
12407          * adjusted_mode bits in the crtc directly.
12408          */
12409         if (dev_priv->display.modeset_calc_cdclk) {
12410                 ret = dev_priv->display.modeset_calc_cdclk(state);
12411                 if (ret < 0)
12412                         return ret;
12413
12414                 /*
12415                  * Writes to dev_priv->cdclk.logical must protected by
12416                  * holding all the crtc locks, even if we don't end up
12417                  * touching the hardware
12418                  */
12419                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12420                                                &intel_state->cdclk.logical)) {
12421                         ret = intel_lock_all_pipes(state);
12422                         if (ret < 0)
12423                                 return ret;
12424                 }
12425
12426                 /* All pipes must be switched off while we change the cdclk. */
12427                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12428                                                &intel_state->cdclk.actual)) {
12429                         ret = intel_modeset_all_pipes(state);
12430                         if (ret < 0)
12431                                 return ret;
12432                 }
12433
12434                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12435                               intel_state->cdclk.logical.cdclk,
12436                               intel_state->cdclk.actual.cdclk);
12437         } else {
12438                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12439         }
12440
12441         intel_modeset_clear_plls(state);
12442
12443         if (IS_HASWELL(dev_priv))
12444                 return haswell_mode_set_planes_workaround(state);
12445
12446         return 0;
12447 }
12448
12449 /*
12450  * Handle calculation of various watermark data at the end of the atomic check
12451  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12452  * handlers to ensure that all derived state has been updated.
12453  */
12454 static int calc_watermark_data(struct drm_atomic_state *state)
12455 {
12456         struct drm_device *dev = state->dev;
12457         struct drm_i915_private *dev_priv = to_i915(dev);
12458
12459         /* Is there platform-specific watermark information to calculate? */
12460         if (dev_priv->display.compute_global_watermarks)
12461                 return dev_priv->display.compute_global_watermarks(state);
12462
12463         return 0;
12464 }
12465
12466 /**
12467  * intel_atomic_check - validate state object
12468  * @dev: drm device
12469  * @state: state to validate
12470  */
12471 static int intel_atomic_check(struct drm_device *dev,
12472                               struct drm_atomic_state *state)
12473 {
12474         struct drm_i915_private *dev_priv = to_i915(dev);
12475         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12476         struct drm_crtc *crtc;
12477         struct drm_crtc_state *old_crtc_state, *crtc_state;
12478         int ret, i;
12479         bool any_ms = false;
12480
12481         ret = drm_atomic_helper_check_modeset(dev, state);
12482         if (ret)
12483                 return ret;
12484
12485         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12486                 struct intel_crtc_state *pipe_config =
12487                         to_intel_crtc_state(crtc_state);
12488
12489                 /* Catch I915_MODE_FLAG_INHERITED */
12490                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12491                         crtc_state->mode_changed = true;
12492
12493                 if (!needs_modeset(crtc_state))
12494                         continue;
12495
12496                 if (!crtc_state->enable) {
12497                         any_ms = true;
12498                         continue;
12499                 }
12500
12501                 /* FIXME: For only active_changed we shouldn't need to do any
12502                  * state recomputation at all. */
12503
12504                 ret = drm_atomic_add_affected_connectors(state, crtc);
12505                 if (ret)
12506                         return ret;
12507
12508                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12509                 if (ret) {
12510                         intel_dump_pipe_config(to_intel_crtc(crtc),
12511                                                pipe_config, "[failed]");
12512                         return ret;
12513                 }
12514
12515                 if (i915.fastboot &&
12516                     intel_pipe_config_compare(dev_priv,
12517                                         to_intel_crtc_state(old_crtc_state),
12518                                         pipe_config, true)) {
12519                         crtc_state->mode_changed = false;
12520                         pipe_config->update_pipe = true;
12521                 }
12522
12523                 if (needs_modeset(crtc_state))
12524                         any_ms = true;
12525
12526                 ret = drm_atomic_add_affected_planes(state, crtc);
12527                 if (ret)
12528                         return ret;
12529
12530                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12531                                        needs_modeset(crtc_state) ?
12532                                        "[modeset]" : "[fastset]");
12533         }
12534
12535         if (any_ms) {
12536                 ret = intel_modeset_checks(state);
12537
12538                 if (ret)
12539                         return ret;
12540         } else {
12541                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12542         }
12543
12544         ret = drm_atomic_helper_check_planes(dev, state);
12545         if (ret)
12546                 return ret;
12547
12548         intel_fbc_choose_crtc(dev_priv, state);
12549         return calc_watermark_data(state);
12550 }
12551
12552 static int intel_atomic_prepare_commit(struct drm_device *dev,
12553                                        struct drm_atomic_state *state)
12554 {
12555         struct drm_i915_private *dev_priv = to_i915(dev);
12556         struct drm_crtc_state *crtc_state;
12557         struct drm_crtc *crtc;
12558         int i, ret;
12559
12560         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12561                 if (state->legacy_cursor_update)
12562                         continue;
12563
12564                 ret = intel_crtc_wait_for_pending_flips(crtc);
12565                 if (ret)
12566                         return ret;
12567
12568                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12569                         flush_workqueue(dev_priv->wq);
12570         }
12571
12572         ret = mutex_lock_interruptible(&dev->struct_mutex);
12573         if (ret)
12574                 return ret;
12575
12576         ret = drm_atomic_helper_prepare_planes(dev, state);
12577         mutex_unlock(&dev->struct_mutex);
12578
12579         return ret;
12580 }
12581
12582 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12583 {
12584         struct drm_device *dev = crtc->base.dev;
12585
12586         if (!dev->max_vblank_count)
12587                 return drm_accurate_vblank_count(&crtc->base);
12588
12589         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12590 }
12591
12592 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12593                                           struct drm_i915_private *dev_priv,
12594                                           unsigned crtc_mask)
12595 {
12596         unsigned last_vblank_count[I915_MAX_PIPES];
12597         enum pipe pipe;
12598         int ret;
12599
12600         if (!crtc_mask)
12601                 return;
12602
12603         for_each_pipe(dev_priv, pipe) {
12604                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12605                                                                   pipe);
12606
12607                 if (!((1 << pipe) & crtc_mask))
12608                         continue;
12609
12610                 ret = drm_crtc_vblank_get(&crtc->base);
12611                 if (WARN_ON(ret != 0)) {
12612                         crtc_mask &= ~(1 << pipe);
12613                         continue;
12614                 }
12615
12616                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12617         }
12618
12619         for_each_pipe(dev_priv, pipe) {
12620                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12621                                                                   pipe);
12622                 long lret;
12623
12624                 if (!((1 << pipe) & crtc_mask))
12625                         continue;
12626
12627                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12628                                 last_vblank_count[pipe] !=
12629                                         drm_crtc_vblank_count(&crtc->base),
12630                                 msecs_to_jiffies(50));
12631
12632                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12633
12634                 drm_crtc_vblank_put(&crtc->base);
12635         }
12636 }
12637
12638 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12639 {
12640         /* fb updated, need to unpin old fb */
12641         if (crtc_state->fb_changed)
12642                 return true;
12643
12644         /* wm changes, need vblank before final wm's */
12645         if (crtc_state->update_wm_post)
12646                 return true;
12647
12648         if (crtc_state->wm.need_postvbl_update)
12649                 return true;
12650
12651         return false;
12652 }
12653
12654 static void intel_update_crtc(struct drm_crtc *crtc,
12655                               struct drm_atomic_state *state,
12656                               struct drm_crtc_state *old_crtc_state,
12657                               struct drm_crtc_state *new_crtc_state,
12658                               unsigned int *crtc_vblank_mask)
12659 {
12660         struct drm_device *dev = crtc->dev;
12661         struct drm_i915_private *dev_priv = to_i915(dev);
12662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12663         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12664         bool modeset = needs_modeset(new_crtc_state);
12665
12666         if (modeset) {
12667                 update_scanline_offset(intel_crtc);
12668                 dev_priv->display.crtc_enable(pipe_config, state);
12669         } else {
12670                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12671                                        pipe_config);
12672         }
12673
12674         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12675                 intel_fbc_enable(
12676                     intel_crtc, pipe_config,
12677                     to_intel_plane_state(crtc->primary->state));
12678         }
12679
12680         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12681
12682         if (needs_vblank_wait(pipe_config))
12683                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12684 }
12685
12686 static void intel_update_crtcs(struct drm_atomic_state *state,
12687                                unsigned int *crtc_vblank_mask)
12688 {
12689         struct drm_crtc *crtc;
12690         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12691         int i;
12692
12693         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12694                 if (!new_crtc_state->active)
12695                         continue;
12696
12697                 intel_update_crtc(crtc, state, old_crtc_state,
12698                                   new_crtc_state, crtc_vblank_mask);
12699         }
12700 }
12701
12702 static void skl_update_crtcs(struct drm_atomic_state *state,
12703                              unsigned int *crtc_vblank_mask)
12704 {
12705         struct drm_i915_private *dev_priv = to_i915(state->dev);
12706         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12707         struct drm_crtc *crtc;
12708         struct intel_crtc *intel_crtc;
12709         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12710         struct intel_crtc_state *cstate;
12711         unsigned int updated = 0;
12712         bool progress;
12713         enum pipe pipe;
12714         int i;
12715
12716         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12717
12718         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12719                 /* ignore allocations for crtc's that have been turned off. */
12720                 if (new_crtc_state->active)
12721                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12722
12723         /*
12724          * Whenever the number of active pipes changes, we need to make sure we
12725          * update the pipes in the right order so that their ddb allocations
12726          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12727          * cause pipe underruns and other bad stuff.
12728          */
12729         do {
12730                 progress = false;
12731
12732                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12733                         bool vbl_wait = false;
12734                         unsigned int cmask = drm_crtc_mask(crtc);
12735
12736                         intel_crtc = to_intel_crtc(crtc);
12737                         cstate = to_intel_crtc_state(crtc->state);
12738                         pipe = intel_crtc->pipe;
12739
12740                         if (updated & cmask || !cstate->base.active)
12741                                 continue;
12742
12743                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12744                                 continue;
12745
12746                         updated |= cmask;
12747                         entries[i] = &cstate->wm.skl.ddb;
12748
12749                         /*
12750                          * If this is an already active pipe, it's DDB changed,
12751                          * and this isn't the last pipe that needs updating
12752                          * then we need to wait for a vblank to pass for the
12753                          * new ddb allocation to take effect.
12754                          */
12755                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12756                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12757                             !new_crtc_state->active_changed &&
12758                             intel_state->wm_results.dirty_pipes != updated)
12759                                 vbl_wait = true;
12760
12761                         intel_update_crtc(crtc, state, old_crtc_state,
12762                                           new_crtc_state, crtc_vblank_mask);
12763
12764                         if (vbl_wait)
12765                                 intel_wait_for_vblank(dev_priv, pipe);
12766
12767                         progress = true;
12768                 }
12769         } while (progress);
12770 }
12771
12772 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12773 {
12774         struct intel_atomic_state *state, *next;
12775         struct llist_node *freed;
12776
12777         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12778         llist_for_each_entry_safe(state, next, freed, freed)
12779                 drm_atomic_state_put(&state->base);
12780 }
12781
12782 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12783 {
12784         struct drm_i915_private *dev_priv =
12785                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12786
12787         intel_atomic_helper_free_state(dev_priv);
12788 }
12789
12790 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12791 {
12792         struct drm_device *dev = state->dev;
12793         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12794         struct drm_i915_private *dev_priv = to_i915(dev);
12795         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12796         struct drm_crtc *crtc;
12797         struct intel_crtc_state *intel_cstate;
12798         bool hw_check = intel_state->modeset;
12799         u64 put_domains[I915_MAX_PIPES] = {};
12800         unsigned crtc_vblank_mask = 0;
12801         int i;
12802
12803         drm_atomic_helper_wait_for_dependencies(state);
12804
12805         if (intel_state->modeset)
12806                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12807
12808         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12809                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12810
12811                 if (needs_modeset(new_crtc_state) ||
12812                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12813                         hw_check = true;
12814
12815                         put_domains[to_intel_crtc(crtc)->pipe] =
12816                                 modeset_get_crtc_power_domains(crtc,
12817                                         to_intel_crtc_state(new_crtc_state));
12818                 }
12819
12820                 if (!needs_modeset(new_crtc_state))
12821                         continue;
12822
12823                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12824                                        to_intel_crtc_state(new_crtc_state));
12825
12826                 if (old_crtc_state->active) {
12827                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12828                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12829                         intel_crtc->active = false;
12830                         intel_fbc_disable(intel_crtc);
12831                         intel_disable_shared_dpll(intel_crtc);
12832
12833                         /*
12834                          * Underruns don't always raise
12835                          * interrupts, so check manually.
12836                          */
12837                         intel_check_cpu_fifo_underruns(dev_priv);
12838                         intel_check_pch_fifo_underruns(dev_priv);
12839
12840                         if (!crtc->state->active) {
12841                                 /*
12842                                  * Make sure we don't call initial_watermarks
12843                                  * for ILK-style watermark updates.
12844                                  *
12845                                  * No clue what this is supposed to achieve.
12846                                  */
12847                                 if (INTEL_GEN(dev_priv) >= 9)
12848                                         dev_priv->display.initial_watermarks(intel_state,
12849                                                                              to_intel_crtc_state(crtc->state));
12850                         }
12851                 }
12852         }
12853
12854         /* Only after disabling all output pipelines that will be changed can we
12855          * update the the output configuration. */
12856         intel_modeset_update_crtc_state(state);
12857
12858         if (intel_state->modeset) {
12859                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12860
12861                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12862
12863                 /*
12864                  * SKL workaround: bspec recommends we disable the SAGV when we
12865                  * have more then one pipe enabled
12866                  */
12867                 if (!intel_can_enable_sagv(state))
12868                         intel_disable_sagv(dev_priv);
12869
12870                 intel_modeset_verify_disabled(dev, state);
12871         }
12872
12873         /* Complete the events for pipes that have now been disabled */
12874         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12875                 bool modeset = needs_modeset(new_crtc_state);
12876
12877                 /* Complete events for now disable pipes here. */
12878                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12879                         spin_lock_irq(&dev->event_lock);
12880                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12881                         spin_unlock_irq(&dev->event_lock);
12882
12883                         new_crtc_state->event = NULL;
12884                 }
12885         }
12886
12887         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12888         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12889
12890         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12891          * already, but still need the state for the delayed optimization. To
12892          * fix this:
12893          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12894          * - schedule that vblank worker _before_ calling hw_done
12895          * - at the start of commit_tail, cancel it _synchrously
12896          * - switch over to the vblank wait helper in the core after that since
12897          *   we don't need out special handling any more.
12898          */
12899         if (!state->legacy_cursor_update)
12900                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12901
12902         /*
12903          * Now that the vblank has passed, we can go ahead and program the
12904          * optimal watermarks on platforms that need two-step watermark
12905          * programming.
12906          *
12907          * TODO: Move this (and other cleanup) to an async worker eventually.
12908          */
12909         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12910                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12911
12912                 if (dev_priv->display.optimize_watermarks)
12913                         dev_priv->display.optimize_watermarks(intel_state,
12914                                                               intel_cstate);
12915         }
12916
12917         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12918                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12919
12920                 if (put_domains[i])
12921                         modeset_put_power_domains(dev_priv, put_domains[i]);
12922
12923                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12924         }
12925
12926         if (intel_state->modeset && intel_can_enable_sagv(state))
12927                 intel_enable_sagv(dev_priv);
12928
12929         drm_atomic_helper_commit_hw_done(state);
12930
12931         if (intel_state->modeset)
12932                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12933
12934         mutex_lock(&dev->struct_mutex);
12935         drm_atomic_helper_cleanup_planes(dev, state);
12936         mutex_unlock(&dev->struct_mutex);
12937
12938         drm_atomic_helper_commit_cleanup_done(state);
12939
12940         drm_atomic_state_put(state);
12941
12942         /* As one of the primary mmio accessors, KMS has a high likelihood
12943          * of triggering bugs in unclaimed access. After we finish
12944          * modesetting, see if an error has been flagged, and if so
12945          * enable debugging for the next modeset - and hope we catch
12946          * the culprit.
12947          *
12948          * XXX note that we assume display power is on at this point.
12949          * This might hold true now but we need to add pm helper to check
12950          * unclaimed only when the hardware is on, as atomic commits
12951          * can happen also when the device is completely off.
12952          */
12953         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12954
12955         intel_atomic_helper_free_state(dev_priv);
12956 }
12957
12958 static void intel_atomic_commit_work(struct work_struct *work)
12959 {
12960         struct drm_atomic_state *state =
12961                 container_of(work, struct drm_atomic_state, commit_work);
12962
12963         intel_atomic_commit_tail(state);
12964 }
12965
12966 static int __i915_sw_fence_call
12967 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12968                           enum i915_sw_fence_notify notify)
12969 {
12970         struct intel_atomic_state *state =
12971                 container_of(fence, struct intel_atomic_state, commit_ready);
12972
12973         switch (notify) {
12974         case FENCE_COMPLETE:
12975                 if (state->base.commit_work.func)
12976                         queue_work(system_unbound_wq, &state->base.commit_work);
12977                 break;
12978
12979         case FENCE_FREE:
12980                 {
12981                         struct intel_atomic_helper *helper =
12982                                 &to_i915(state->base.dev)->atomic_helper;
12983
12984                         if (llist_add(&state->freed, &helper->free_list))
12985                                 schedule_work(&helper->free_work);
12986                         break;
12987                 }
12988         }
12989
12990         return NOTIFY_DONE;
12991 }
12992
12993 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12994 {
12995         struct drm_plane_state *old_plane_state, *new_plane_state;
12996         struct drm_plane *plane;
12997         int i;
12998
12999         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13000                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13001                                   intel_fb_obj(new_plane_state->fb),
13002                                   to_intel_plane(plane)->frontbuffer_bit);
13003 }
13004
13005 /**
13006  * intel_atomic_commit - commit validated state object
13007  * @dev: DRM device
13008  * @state: the top-level driver state object
13009  * @nonblock: nonblocking commit
13010  *
13011  * This function commits a top-level state object that has been validated
13012  * with drm_atomic_helper_check().
13013  *
13014  * RETURNS
13015  * Zero for success or -errno.
13016  */
13017 static int intel_atomic_commit(struct drm_device *dev,
13018                                struct drm_atomic_state *state,
13019                                bool nonblock)
13020 {
13021         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13022         struct drm_i915_private *dev_priv = to_i915(dev);
13023         int ret = 0;
13024
13025         ret = drm_atomic_helper_setup_commit(state, nonblock);
13026         if (ret)
13027                 return ret;
13028
13029         drm_atomic_state_get(state);
13030         i915_sw_fence_init(&intel_state->commit_ready,
13031                            intel_atomic_commit_ready);
13032
13033         ret = intel_atomic_prepare_commit(dev, state);
13034         if (ret) {
13035                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13036                 i915_sw_fence_commit(&intel_state->commit_ready);
13037                 return ret;
13038         }
13039
13040         /*
13041          * The intel_legacy_cursor_update() fast path takes care
13042          * of avoiding the vblank waits for simple cursor
13043          * movement and flips. For cursor on/off and size changes,
13044          * we want to perform the vblank waits so that watermark
13045          * updates happen during the correct frames. Gen9+ have
13046          * double buffered watermarks and so shouldn't need this.
13047          *
13048          * Do this after drm_atomic_helper_setup_commit() and
13049          * intel_atomic_prepare_commit() because we still want
13050          * to skip the flip and fb cleanup waits. Although that
13051          * does risk yanking the mapping from under the display
13052          * engine.
13053          *
13054          * FIXME doing watermarks and fb cleanup from a vblank worker
13055          * (assuming we had any) would solve these problems.
13056          */
13057         if (INTEL_GEN(dev_priv) < 9)
13058                 state->legacy_cursor_update = false;
13059
13060         drm_atomic_helper_swap_state(state, true);
13061         dev_priv->wm.distrust_bios_wm = false;
13062         intel_shared_dpll_swap_state(state);
13063         intel_atomic_track_fbs(state);
13064
13065         if (intel_state->modeset) {
13066                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13067                        sizeof(intel_state->min_pixclk));
13068                 dev_priv->active_crtcs = intel_state->active_crtcs;
13069                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13070                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13071         }
13072
13073         drm_atomic_state_get(state);
13074         INIT_WORK(&state->commit_work,
13075                   nonblock ? intel_atomic_commit_work : NULL);
13076
13077         i915_sw_fence_commit(&intel_state->commit_ready);
13078         if (!nonblock) {
13079                 i915_sw_fence_wait(&intel_state->commit_ready);
13080                 intel_atomic_commit_tail(state);
13081         }
13082
13083         return 0;
13084 }
13085
13086 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13087 {
13088         struct drm_device *dev = crtc->dev;
13089         struct drm_atomic_state *state;
13090         struct drm_crtc_state *crtc_state;
13091         int ret;
13092
13093         state = drm_atomic_state_alloc(dev);
13094         if (!state) {
13095                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13096                               crtc->base.id, crtc->name);
13097                 return;
13098         }
13099
13100         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
13101
13102 retry:
13103         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13104         ret = PTR_ERR_OR_ZERO(crtc_state);
13105         if (!ret) {
13106                 if (!crtc_state->active)
13107                         goto out;
13108
13109                 crtc_state->mode_changed = true;
13110                 ret = drm_atomic_commit(state);
13111         }
13112
13113         if (ret == -EDEADLK) {
13114                 drm_atomic_state_clear(state);
13115                 drm_modeset_backoff(state->acquire_ctx);
13116                 goto retry;
13117         }
13118
13119 out:
13120         drm_atomic_state_put(state);
13121 }
13122
13123 static const struct drm_crtc_funcs intel_crtc_funcs = {
13124         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13125         .set_config = drm_atomic_helper_set_config,
13126         .set_property = drm_atomic_helper_crtc_set_property,
13127         .destroy = intel_crtc_destroy,
13128         .page_flip = drm_atomic_helper_page_flip,
13129         .atomic_duplicate_state = intel_crtc_duplicate_state,
13130         .atomic_destroy_state = intel_crtc_destroy_state,
13131         .set_crc_source = intel_crtc_set_crc_source,
13132 };
13133
13134 /**
13135  * intel_prepare_plane_fb - Prepare fb for usage on plane
13136  * @plane: drm plane to prepare for
13137  * @fb: framebuffer to prepare for presentation
13138  *
13139  * Prepares a framebuffer for usage on a display plane.  Generally this
13140  * involves pinning the underlying object and updating the frontbuffer tracking
13141  * bits.  Some older platforms need special physical address handling for
13142  * cursor planes.
13143  *
13144  * Must be called with struct_mutex held.
13145  *
13146  * Returns 0 on success, negative error code on failure.
13147  */
13148 int
13149 intel_prepare_plane_fb(struct drm_plane *plane,
13150                        struct drm_plane_state *new_state)
13151 {
13152         struct intel_atomic_state *intel_state =
13153                 to_intel_atomic_state(new_state->state);
13154         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13155         struct drm_framebuffer *fb = new_state->fb;
13156         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13157         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13158         int ret;
13159
13160         if (obj) {
13161                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13162                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13163                         const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13164
13165                         ret = i915_gem_object_attach_phys(obj, align);
13166                         if (ret) {
13167                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13168                                 return ret;
13169                         }
13170                 } else {
13171                         struct i915_vma *vma;
13172
13173                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13174                         if (IS_ERR(vma)) {
13175                                 DRM_DEBUG_KMS("failed to pin object\n");
13176                                 return PTR_ERR(vma);
13177                         }
13178
13179                         to_intel_plane_state(new_state)->vma = vma;
13180                 }
13181         }
13182
13183         if (!obj && !old_obj)
13184                 return 0;
13185
13186         if (old_obj) {
13187                 struct drm_crtc_state *crtc_state =
13188                         drm_atomic_get_existing_crtc_state(new_state->state,
13189                                                            plane->state->crtc);
13190
13191                 /* Big Hammer, we also need to ensure that any pending
13192                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13193                  * current scanout is retired before unpinning the old
13194                  * framebuffer. Note that we rely on userspace rendering
13195                  * into the buffer attached to the pipe they are waiting
13196                  * on. If not, userspace generates a GPU hang with IPEHR
13197                  * point to the MI_WAIT_FOR_EVENT.
13198                  *
13199                  * This should only fail upon a hung GPU, in which case we
13200                  * can safely continue.
13201                  */
13202                 if (needs_modeset(crtc_state)) {
13203                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13204                                                               old_obj->resv, NULL,
13205                                                               false, 0,
13206                                                               GFP_KERNEL);
13207                         if (ret < 0)
13208                                 return ret;
13209                 }
13210         }
13211
13212         if (new_state->fence) { /* explicit fencing */
13213                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13214                                                     new_state->fence,
13215                                                     I915_FENCE_TIMEOUT,
13216                                                     GFP_KERNEL);
13217                 if (ret < 0)
13218                         return ret;
13219         }
13220
13221         if (!obj)
13222                 return 0;
13223
13224         if (!new_state->fence) { /* implicit fencing */
13225                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13226                                                       obj->resv, NULL,
13227                                                       false, I915_FENCE_TIMEOUT,
13228                                                       GFP_KERNEL);
13229                 if (ret < 0)
13230                         return ret;
13231
13232                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13233         }
13234
13235         return 0;
13236 }
13237
13238 /**
13239  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13240  * @plane: drm plane to clean up for
13241  * @fb: old framebuffer that was on plane
13242  *
13243  * Cleans up a framebuffer that has just been removed from a plane.
13244  *
13245  * Must be called with struct_mutex held.
13246  */
13247 void
13248 intel_cleanup_plane_fb(struct drm_plane *plane,
13249                        struct drm_plane_state *old_state)
13250 {
13251         struct i915_vma *vma;
13252
13253         /* Should only be called after a successful intel_prepare_plane_fb()! */
13254         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13255         if (vma)
13256                 intel_unpin_fb_vma(vma);
13257 }
13258
13259 int
13260 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13261 {
13262         struct drm_i915_private *dev_priv;
13263         int max_scale;
13264         int crtc_clock, max_dotclk;
13265
13266         if (!intel_crtc || !crtc_state->base.enable)
13267                 return DRM_PLANE_HELPER_NO_SCALING;
13268
13269         dev_priv = to_i915(intel_crtc->base.dev);
13270
13271         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13272         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13273
13274         if (IS_GEMINILAKE(dev_priv))
13275                 max_dotclk *= 2;
13276
13277         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13278                 return DRM_PLANE_HELPER_NO_SCALING;
13279
13280         /*
13281          * skl max scale is lower of:
13282          *    close to 3 but not 3, -1 is for that purpose
13283          *            or
13284          *    cdclk/crtc_clock
13285          */
13286         max_scale = min((1 << 16) * 3 - 1,
13287                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13288
13289         return max_scale;
13290 }
13291
13292 static int
13293 intel_check_primary_plane(struct drm_plane *plane,
13294                           struct intel_crtc_state *crtc_state,
13295                           struct intel_plane_state *state)
13296 {
13297         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13298         struct drm_crtc *crtc = state->base.crtc;
13299         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13300         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13301         bool can_position = false;
13302         int ret;
13303
13304         if (INTEL_GEN(dev_priv) >= 9) {
13305                 /* use scaler when colorkey is not required */
13306                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13307                         min_scale = 1;
13308                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13309                 }
13310                 can_position = true;
13311         }
13312
13313         ret = drm_plane_helper_check_state(&state->base,
13314                                            &state->clip,
13315                                            min_scale, max_scale,
13316                                            can_position, true);
13317         if (ret)
13318                 return ret;
13319
13320         if (!state->base.fb)
13321                 return 0;
13322
13323         if (INTEL_GEN(dev_priv) >= 9) {
13324                 ret = skl_check_plane_surface(state);
13325                 if (ret)
13326                         return ret;
13327
13328                 state->ctl = skl_plane_ctl(crtc_state, state);
13329         } else {
13330                 ret = i9xx_check_plane_surface(state);
13331                 if (ret)
13332                         return ret;
13333
13334                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13335         }
13336
13337         return 0;
13338 }
13339
13340 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13341                                     struct drm_crtc_state *old_crtc_state)
13342 {
13343         struct drm_device *dev = crtc->dev;
13344         struct drm_i915_private *dev_priv = to_i915(dev);
13345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13346         struct intel_crtc_state *intel_cstate =
13347                 to_intel_crtc_state(crtc->state);
13348         struct intel_crtc_state *old_intel_cstate =
13349                 to_intel_crtc_state(old_crtc_state);
13350         struct intel_atomic_state *old_intel_state =
13351                 to_intel_atomic_state(old_crtc_state->state);
13352         bool modeset = needs_modeset(crtc->state);
13353
13354         if (!modeset &&
13355             (intel_cstate->base.color_mgmt_changed ||
13356              intel_cstate->update_pipe)) {
13357                 intel_color_set_csc(crtc->state);
13358                 intel_color_load_luts(crtc->state);
13359         }
13360
13361         /* Perform vblank evasion around commit operation */
13362         intel_pipe_update_start(intel_crtc);
13363
13364         if (modeset)
13365                 goto out;
13366
13367         if (intel_cstate->update_pipe)
13368                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13369         else if (INTEL_GEN(dev_priv) >= 9)
13370                 skl_detach_scalers(intel_crtc);
13371
13372 out:
13373         if (dev_priv->display.atomic_update_watermarks)
13374                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13375                                                            intel_cstate);
13376 }
13377
13378 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13379                                      struct drm_crtc_state *old_crtc_state)
13380 {
13381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13382
13383         intel_pipe_update_end(intel_crtc, NULL);
13384 }
13385
13386 /**
13387  * intel_plane_destroy - destroy a plane
13388  * @plane: plane to destroy
13389  *
13390  * Common destruction function for all types of planes (primary, cursor,
13391  * sprite).
13392  */
13393 void intel_plane_destroy(struct drm_plane *plane)
13394 {
13395         drm_plane_cleanup(plane);
13396         kfree(to_intel_plane(plane));
13397 }
13398
13399 const struct drm_plane_funcs intel_plane_funcs = {
13400         .update_plane = drm_atomic_helper_update_plane,
13401         .disable_plane = drm_atomic_helper_disable_plane,
13402         .destroy = intel_plane_destroy,
13403         .set_property = drm_atomic_helper_plane_set_property,
13404         .atomic_get_property = intel_plane_atomic_get_property,
13405         .atomic_set_property = intel_plane_atomic_set_property,
13406         .atomic_duplicate_state = intel_plane_duplicate_state,
13407         .atomic_destroy_state = intel_plane_destroy_state,
13408 };
13409
13410 static int
13411 intel_legacy_cursor_update(struct drm_plane *plane,
13412                            struct drm_crtc *crtc,
13413                            struct drm_framebuffer *fb,
13414                            int crtc_x, int crtc_y,
13415                            unsigned int crtc_w, unsigned int crtc_h,
13416                            uint32_t src_x, uint32_t src_y,
13417                            uint32_t src_w, uint32_t src_h,
13418                            struct drm_modeset_acquire_ctx *ctx)
13419 {
13420         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13421         int ret;
13422         struct drm_plane_state *old_plane_state, *new_plane_state;
13423         struct intel_plane *intel_plane = to_intel_plane(plane);
13424         struct drm_framebuffer *old_fb;
13425         struct drm_crtc_state *crtc_state = crtc->state;
13426         struct i915_vma *old_vma;
13427
13428         /*
13429          * When crtc is inactive or there is a modeset pending,
13430          * wait for it to complete in the slowpath
13431          */
13432         if (!crtc_state->active || needs_modeset(crtc_state) ||
13433             to_intel_crtc_state(crtc_state)->update_pipe)
13434                 goto slow;
13435
13436         old_plane_state = plane->state;
13437
13438         /*
13439          * If any parameters change that may affect watermarks,
13440          * take the slowpath. Only changing fb or position should be
13441          * in the fastpath.
13442          */
13443         if (old_plane_state->crtc != crtc ||
13444             old_plane_state->src_w != src_w ||
13445             old_plane_state->src_h != src_h ||
13446             old_plane_state->crtc_w != crtc_w ||
13447             old_plane_state->crtc_h != crtc_h ||
13448             !old_plane_state->fb != !fb)
13449                 goto slow;
13450
13451         new_plane_state = intel_plane_duplicate_state(plane);
13452         if (!new_plane_state)
13453                 return -ENOMEM;
13454
13455         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13456
13457         new_plane_state->src_x = src_x;
13458         new_plane_state->src_y = src_y;
13459         new_plane_state->src_w = src_w;
13460         new_plane_state->src_h = src_h;
13461         new_plane_state->crtc_x = crtc_x;
13462         new_plane_state->crtc_y = crtc_y;
13463         new_plane_state->crtc_w = crtc_w;
13464         new_plane_state->crtc_h = crtc_h;
13465
13466         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13467                                                   to_intel_plane_state(new_plane_state));
13468         if (ret)
13469                 goto out_free;
13470
13471         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13472         if (ret)
13473                 goto out_free;
13474
13475         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13476                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13477
13478                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13479                 if (ret) {
13480                         DRM_DEBUG_KMS("failed to attach phys object\n");
13481                         goto out_unlock;
13482                 }
13483         } else {
13484                 struct i915_vma *vma;
13485
13486                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13487                 if (IS_ERR(vma)) {
13488                         DRM_DEBUG_KMS("failed to pin object\n");
13489
13490                         ret = PTR_ERR(vma);
13491                         goto out_unlock;
13492                 }
13493
13494                 to_intel_plane_state(new_plane_state)->vma = vma;
13495         }
13496
13497         old_fb = old_plane_state->fb;
13498         old_vma = to_intel_plane_state(old_plane_state)->vma;
13499
13500         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13501                           intel_plane->frontbuffer_bit);
13502
13503         /* Swap plane state */
13504         new_plane_state->fence = old_plane_state->fence;
13505         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13506         new_plane_state->fence = NULL;
13507         new_plane_state->fb = old_fb;
13508         to_intel_plane_state(new_plane_state)->vma = old_vma;
13509
13510         if (plane->state->visible) {
13511                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13512                 intel_plane->update_plane(plane,
13513                                           to_intel_crtc_state(crtc->state),
13514                                           to_intel_plane_state(plane->state));
13515         } else {
13516                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13517                 intel_plane->disable_plane(plane, crtc);
13518         }
13519
13520         intel_cleanup_plane_fb(plane, new_plane_state);
13521
13522 out_unlock:
13523         mutex_unlock(&dev_priv->drm.struct_mutex);
13524 out_free:
13525         intel_plane_destroy_state(plane, new_plane_state);
13526         return ret;
13527
13528 slow:
13529         return drm_atomic_helper_update_plane(plane, crtc, fb,
13530                                               crtc_x, crtc_y, crtc_w, crtc_h,
13531                                               src_x, src_y, src_w, src_h, ctx);
13532 }
13533
13534 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13535         .update_plane = intel_legacy_cursor_update,
13536         .disable_plane = drm_atomic_helper_disable_plane,
13537         .destroy = intel_plane_destroy,
13538         .set_property = drm_atomic_helper_plane_set_property,
13539         .atomic_get_property = intel_plane_atomic_get_property,
13540         .atomic_set_property = intel_plane_atomic_set_property,
13541         .atomic_duplicate_state = intel_plane_duplicate_state,
13542         .atomic_destroy_state = intel_plane_destroy_state,
13543 };
13544
13545 static struct intel_plane *
13546 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13547 {
13548         struct intel_plane *primary = NULL;
13549         struct intel_plane_state *state = NULL;
13550         const uint32_t *intel_primary_formats;
13551         unsigned int supported_rotations;
13552         unsigned int num_formats;
13553         int ret;
13554
13555         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13556         if (!primary) {
13557                 ret = -ENOMEM;
13558                 goto fail;
13559         }
13560
13561         state = intel_create_plane_state(&primary->base);
13562         if (!state) {
13563                 ret = -ENOMEM;
13564                 goto fail;
13565         }
13566
13567         primary->base.state = &state->base;
13568
13569         primary->can_scale = false;
13570         primary->max_downscale = 1;
13571         if (INTEL_GEN(dev_priv) >= 9) {
13572                 primary->can_scale = true;
13573                 state->scaler_id = -1;
13574         }
13575         primary->pipe = pipe;
13576         /*
13577          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13578          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13579          */
13580         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13581                 primary->plane = (enum plane) !pipe;
13582         else
13583                 primary->plane = (enum plane) pipe;
13584         primary->id = PLANE_PRIMARY;
13585         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13586         primary->check_plane = intel_check_primary_plane;
13587
13588         if (INTEL_GEN(dev_priv) >= 9) {
13589                 intel_primary_formats = skl_primary_formats;
13590                 num_formats = ARRAY_SIZE(skl_primary_formats);
13591
13592                 primary->update_plane = skylake_update_primary_plane;
13593                 primary->disable_plane = skylake_disable_primary_plane;
13594         } else if (INTEL_GEN(dev_priv) >= 4) {
13595                 intel_primary_formats = i965_primary_formats;
13596                 num_formats = ARRAY_SIZE(i965_primary_formats);
13597
13598                 primary->update_plane = i9xx_update_primary_plane;
13599                 primary->disable_plane = i9xx_disable_primary_plane;
13600         } else {
13601                 intel_primary_formats = i8xx_primary_formats;
13602                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13603
13604                 primary->update_plane = i9xx_update_primary_plane;
13605                 primary->disable_plane = i9xx_disable_primary_plane;
13606         }
13607
13608         if (INTEL_GEN(dev_priv) >= 9)
13609                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13610                                                0, &intel_plane_funcs,
13611                                                intel_primary_formats, num_formats,
13612                                                DRM_PLANE_TYPE_PRIMARY,
13613                                                "plane 1%c", pipe_name(pipe));
13614         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13615                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13616                                                0, &intel_plane_funcs,
13617                                                intel_primary_formats, num_formats,
13618                                                DRM_PLANE_TYPE_PRIMARY,
13619                                                "primary %c", pipe_name(pipe));
13620         else
13621                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13622                                                0, &intel_plane_funcs,
13623                                                intel_primary_formats, num_formats,
13624                                                DRM_PLANE_TYPE_PRIMARY,
13625                                                "plane %c", plane_name(primary->plane));
13626         if (ret)
13627                 goto fail;
13628
13629         if (INTEL_GEN(dev_priv) >= 9) {
13630                 supported_rotations =
13631                         DRM_ROTATE_0 | DRM_ROTATE_90 |
13632                         DRM_ROTATE_180 | DRM_ROTATE_270;
13633         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13634                 supported_rotations =
13635                         DRM_ROTATE_0 | DRM_ROTATE_180 |
13636                         DRM_REFLECT_X;
13637         } else if (INTEL_GEN(dev_priv) >= 4) {
13638                 supported_rotations =
13639                         DRM_ROTATE_0 | DRM_ROTATE_180;
13640         } else {
13641                 supported_rotations = DRM_ROTATE_0;
13642         }
13643
13644         if (INTEL_GEN(dev_priv) >= 4)
13645                 drm_plane_create_rotation_property(&primary->base,
13646                                                    DRM_ROTATE_0,
13647                                                    supported_rotations);
13648
13649         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13650
13651         return primary;
13652
13653 fail:
13654         kfree(state);
13655         kfree(primary);
13656
13657         return ERR_PTR(ret);
13658 }
13659
13660 static int
13661 intel_check_cursor_plane(struct drm_plane *plane,
13662                          struct intel_crtc_state *crtc_state,
13663                          struct intel_plane_state *state)
13664 {
13665         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13666         struct drm_framebuffer *fb = state->base.fb;
13667         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13668         enum pipe pipe = to_intel_plane(plane)->pipe;
13669         unsigned stride;
13670         int ret;
13671
13672         ret = drm_plane_helper_check_state(&state->base,
13673                                            &state->clip,
13674                                            DRM_PLANE_HELPER_NO_SCALING,
13675                                            DRM_PLANE_HELPER_NO_SCALING,
13676                                            true, true);
13677         if (ret)
13678                 return ret;
13679
13680         /* if we want to turn off the cursor ignore width and height */
13681         if (!obj)
13682                 return 0;
13683
13684         /* Check for which cursor types we support */
13685         if (!cursor_size_ok(dev_priv, state->base.crtc_w,
13686                             state->base.crtc_h)) {
13687                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13688                           state->base.crtc_w, state->base.crtc_h);
13689                 return -EINVAL;
13690         }
13691
13692         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13693         if (obj->base.size < stride * state->base.crtc_h) {
13694                 DRM_DEBUG_KMS("buffer is too small\n");
13695                 return -ENOMEM;
13696         }
13697
13698         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
13699                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13700                 return -EINVAL;
13701         }
13702
13703         /*
13704          * There's something wrong with the cursor on CHV pipe C.
13705          * If it straddles the left edge of the screen then
13706          * moving it away from the edge or disabling it often
13707          * results in a pipe underrun, and often that can lead to
13708          * dead pipe (constant underrun reported, and it scans
13709          * out just a solid color). To recover from that, the
13710          * display power well must be turned off and on again.
13711          * Refuse the put the cursor into that compromised position.
13712          */
13713         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
13714             state->base.visible && state->base.crtc_x < 0) {
13715                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13716                 return -EINVAL;
13717         }
13718
13719         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
13720                 state->ctl = i845_cursor_ctl(crtc_state, state);
13721         else
13722                 state->ctl = i9xx_cursor_ctl(crtc_state, state);
13723
13724         return 0;
13725 }
13726
13727 static void
13728 intel_disable_cursor_plane(struct drm_plane *plane,
13729                            struct drm_crtc *crtc)
13730 {
13731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13732
13733         intel_crtc->cursor_addr = 0;
13734         intel_crtc_update_cursor(crtc, NULL);
13735 }
13736
13737 static void
13738 intel_update_cursor_plane(struct drm_plane *plane,
13739                           const struct intel_crtc_state *crtc_state,
13740                           const struct intel_plane_state *state)
13741 {
13742         struct drm_crtc *crtc = crtc_state->base.crtc;
13743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13744         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13745         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13746         uint32_t addr;
13747
13748         if (!obj)
13749                 addr = 0;
13750         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13751                 addr = intel_plane_ggtt_offset(state);
13752         else
13753                 addr = obj->phys_handle->busaddr;
13754
13755         intel_crtc->cursor_addr = addr;
13756         intel_crtc_update_cursor(crtc, state);
13757 }
13758
13759 static struct intel_plane *
13760 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13761 {
13762         struct intel_plane *cursor = NULL;
13763         struct intel_plane_state *state = NULL;
13764         int ret;
13765
13766         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13767         if (!cursor) {
13768                 ret = -ENOMEM;
13769                 goto fail;
13770         }
13771
13772         state = intel_create_plane_state(&cursor->base);
13773         if (!state) {
13774                 ret = -ENOMEM;
13775                 goto fail;
13776         }
13777
13778         cursor->base.state = &state->base;
13779
13780         cursor->can_scale = false;
13781         cursor->max_downscale = 1;
13782         cursor->pipe = pipe;
13783         cursor->plane = pipe;
13784         cursor->id = PLANE_CURSOR;
13785         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13786         cursor->check_plane = intel_check_cursor_plane;
13787         cursor->update_plane = intel_update_cursor_plane;
13788         cursor->disable_plane = intel_disable_cursor_plane;
13789
13790         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13791                                        0, &intel_cursor_plane_funcs,
13792                                        intel_cursor_formats,
13793                                        ARRAY_SIZE(intel_cursor_formats),
13794                                        DRM_PLANE_TYPE_CURSOR,
13795                                        "cursor %c", pipe_name(pipe));
13796         if (ret)
13797                 goto fail;
13798
13799         if (INTEL_GEN(dev_priv) >= 4)
13800                 drm_plane_create_rotation_property(&cursor->base,
13801                                                    DRM_ROTATE_0,
13802                                                    DRM_ROTATE_0 |
13803                                                    DRM_ROTATE_180);
13804
13805         if (INTEL_GEN(dev_priv) >= 9)
13806                 state->scaler_id = -1;
13807
13808         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13809
13810         return cursor;
13811
13812 fail:
13813         kfree(state);
13814         kfree(cursor);
13815
13816         return ERR_PTR(ret);
13817 }
13818
13819 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13820                                     struct intel_crtc_state *crtc_state)
13821 {
13822         struct intel_crtc_scaler_state *scaler_state =
13823                 &crtc_state->scaler_state;
13824         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13825         int i;
13826
13827         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13828         if (!crtc->num_scalers)
13829                 return;
13830
13831         for (i = 0; i < crtc->num_scalers; i++) {
13832                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13833
13834                 scaler->in_use = 0;
13835                 scaler->mode = PS_SCALER_MODE_DYN;
13836         }
13837
13838         scaler_state->scaler_id = -1;
13839 }
13840
13841 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13842 {
13843         struct intel_crtc *intel_crtc;
13844         struct intel_crtc_state *crtc_state = NULL;
13845         struct intel_plane *primary = NULL;
13846         struct intel_plane *cursor = NULL;
13847         int sprite, ret;
13848
13849         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13850         if (!intel_crtc)
13851                 return -ENOMEM;
13852
13853         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13854         if (!crtc_state) {
13855                 ret = -ENOMEM;
13856                 goto fail;
13857         }
13858         intel_crtc->config = crtc_state;
13859         intel_crtc->base.state = &crtc_state->base;
13860         crtc_state->base.crtc = &intel_crtc->base;
13861
13862         primary = intel_primary_plane_create(dev_priv, pipe);
13863         if (IS_ERR(primary)) {
13864                 ret = PTR_ERR(primary);
13865                 goto fail;
13866         }
13867         intel_crtc->plane_ids_mask |= BIT(primary->id);
13868
13869         for_each_sprite(dev_priv, pipe, sprite) {
13870                 struct intel_plane *plane;
13871
13872                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13873                 if (IS_ERR(plane)) {
13874                         ret = PTR_ERR(plane);
13875                         goto fail;
13876                 }
13877                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13878         }
13879
13880         cursor = intel_cursor_plane_create(dev_priv, pipe);
13881         if (IS_ERR(cursor)) {
13882                 ret = PTR_ERR(cursor);
13883                 goto fail;
13884         }
13885         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13886
13887         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13888                                         &primary->base, &cursor->base,
13889                                         &intel_crtc_funcs,
13890                                         "pipe %c", pipe_name(pipe));
13891         if (ret)
13892                 goto fail;
13893
13894         intel_crtc->pipe = pipe;
13895         intel_crtc->plane = primary->plane;
13896
13897         intel_crtc->cursor_base = ~0;
13898         intel_crtc->cursor_cntl = ~0;
13899         intel_crtc->cursor_size = ~0;
13900
13901         /* initialize shared scalers */
13902         intel_crtc_init_scalers(intel_crtc, crtc_state);
13903
13904         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13905                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13906         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13907         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13908
13909         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13910
13911         intel_color_init(&intel_crtc->base);
13912
13913         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13914
13915         return 0;
13916
13917 fail:
13918         /*
13919          * drm_mode_config_cleanup() will free up any
13920          * crtcs/planes already initialized.
13921          */
13922         kfree(crtc_state);
13923         kfree(intel_crtc);
13924
13925         return ret;
13926 }
13927
13928 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13929 {
13930         struct drm_device *dev = connector->base.dev;
13931
13932         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13933
13934         if (!connector->base.state->crtc)
13935                 return INVALID_PIPE;
13936
13937         return to_intel_crtc(connector->base.state->crtc)->pipe;
13938 }
13939
13940 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13941                                 struct drm_file *file)
13942 {
13943         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13944         struct drm_crtc *drmmode_crtc;
13945         struct intel_crtc *crtc;
13946
13947         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13948         if (!drmmode_crtc)
13949                 return -ENOENT;
13950
13951         crtc = to_intel_crtc(drmmode_crtc);
13952         pipe_from_crtc_id->pipe = crtc->pipe;
13953
13954         return 0;
13955 }
13956
13957 static int intel_encoder_clones(struct intel_encoder *encoder)
13958 {
13959         struct drm_device *dev = encoder->base.dev;
13960         struct intel_encoder *source_encoder;
13961         int index_mask = 0;
13962         int entry = 0;
13963
13964         for_each_intel_encoder(dev, source_encoder) {
13965                 if (encoders_cloneable(encoder, source_encoder))
13966                         index_mask |= (1 << entry);
13967
13968                 entry++;
13969         }
13970
13971         return index_mask;
13972 }
13973
13974 static bool has_edp_a(struct drm_i915_private *dev_priv)
13975 {
13976         if (!IS_MOBILE(dev_priv))
13977                 return false;
13978
13979         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13980                 return false;
13981
13982         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13983                 return false;
13984
13985         return true;
13986 }
13987
13988 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13989 {
13990         if (INTEL_GEN(dev_priv) >= 9)
13991                 return false;
13992
13993         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13994                 return false;
13995
13996         if (IS_CHERRYVIEW(dev_priv))
13997                 return false;
13998
13999         if (HAS_PCH_LPT_H(dev_priv) &&
14000             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14001                 return false;
14002
14003         /* DDI E can't be used if DDI A requires 4 lanes */
14004         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14005                 return false;
14006
14007         if (!dev_priv->vbt.int_crt_support)
14008                 return false;
14009
14010         return true;
14011 }
14012
14013 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14014 {
14015         int pps_num;
14016         int pps_idx;
14017
14018         if (HAS_DDI(dev_priv))
14019                 return;
14020         /*
14021          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14022          * everywhere where registers can be write protected.
14023          */
14024         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14025                 pps_num = 2;
14026         else
14027                 pps_num = 1;
14028
14029         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14030                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14031
14032                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14033                 I915_WRITE(PP_CONTROL(pps_idx), val);
14034         }
14035 }
14036
14037 static void intel_pps_init(struct drm_i915_private *dev_priv)
14038 {
14039         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14040                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14041         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14042                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14043         else
14044                 dev_priv->pps_mmio_base = PPS_BASE;
14045
14046         intel_pps_unlock_regs_wa(dev_priv);
14047 }
14048
14049 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14050 {
14051         struct intel_encoder *encoder;
14052         bool dpd_is_edp = false;
14053
14054         intel_pps_init(dev_priv);
14055
14056         /*
14057          * intel_edp_init_connector() depends on this completing first, to
14058          * prevent the registeration of both eDP and LVDS and the incorrect
14059          * sharing of the PPS.
14060          */
14061         intel_lvds_init(dev_priv);
14062
14063         if (intel_crt_present(dev_priv))
14064                 intel_crt_init(dev_priv);
14065
14066         if (IS_GEN9_LP(dev_priv)) {
14067                 /*
14068                  * FIXME: Broxton doesn't support port detection via the
14069                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14070                  * detect the ports.
14071                  */
14072                 intel_ddi_init(dev_priv, PORT_A);
14073                 intel_ddi_init(dev_priv, PORT_B);
14074                 intel_ddi_init(dev_priv, PORT_C);
14075
14076                 intel_dsi_init(dev_priv);
14077         } else if (HAS_DDI(dev_priv)) {
14078                 int found;
14079
14080                 /*
14081                  * Haswell uses DDI functions to detect digital outputs.
14082                  * On SKL pre-D0 the strap isn't connected, so we assume
14083                  * it's there.
14084                  */
14085                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14086                 /* WaIgnoreDDIAStrap: skl */
14087                 if (found || IS_GEN9_BC(dev_priv))
14088                         intel_ddi_init(dev_priv, PORT_A);
14089
14090                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14091                  * register */
14092                 found = I915_READ(SFUSE_STRAP);
14093
14094                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14095                         intel_ddi_init(dev_priv, PORT_B);
14096                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14097                         intel_ddi_init(dev_priv, PORT_C);
14098                 if (found & SFUSE_STRAP_DDID_DETECTED)
14099                         intel_ddi_init(dev_priv, PORT_D);
14100                 /*
14101                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14102                  */
14103                 if (IS_GEN9_BC(dev_priv) &&
14104                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14105                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14106                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14107                         intel_ddi_init(dev_priv, PORT_E);
14108
14109         } else if (HAS_PCH_SPLIT(dev_priv)) {
14110                 int found;
14111                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14112
14113                 if (has_edp_a(dev_priv))
14114                         intel_dp_init(dev_priv, DP_A, PORT_A);
14115
14116                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14117                         /* PCH SDVOB multiplex with HDMIB */
14118                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14119                         if (!found)
14120                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14121                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14122                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14123                 }
14124
14125                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14126                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14127
14128                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14129                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14130
14131                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14132                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14133
14134                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14135                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14136         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14137                 bool has_edp, has_port;
14138
14139                 /*
14140                  * The DP_DETECTED bit is the latched state of the DDC
14141                  * SDA pin at boot. However since eDP doesn't require DDC
14142                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14143                  * eDP ports may have been muxed to an alternate function.
14144                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14145                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14146                  * detect eDP ports.
14147                  *
14148                  * Sadly the straps seem to be missing sometimes even for HDMI
14149                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14150                  * and VBT for the presence of the port. Additionally we can't
14151                  * trust the port type the VBT declares as we've seen at least
14152                  * HDMI ports that the VBT claim are DP or eDP.
14153                  */
14154                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14155                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14156                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14157                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14158                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14159                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14160
14161                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14162                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14163                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14164                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14165                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14166                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14167
14168                 if (IS_CHERRYVIEW(dev_priv)) {
14169                         /*
14170                          * eDP not supported on port D,
14171                          * so no need to worry about it
14172                          */
14173                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14174                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14175                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14176                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14177                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14178                 }
14179
14180                 intel_dsi_init(dev_priv);
14181         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14182                 bool found = false;
14183
14184                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14185                         DRM_DEBUG_KMS("probing SDVOB\n");
14186                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14187                         if (!found && IS_G4X(dev_priv)) {
14188                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14189                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14190                         }
14191
14192                         if (!found && IS_G4X(dev_priv))
14193                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14194                 }
14195
14196                 /* Before G4X SDVOC doesn't have its own detect register */
14197
14198                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14199                         DRM_DEBUG_KMS("probing SDVOC\n");
14200                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14201                 }
14202
14203                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14204
14205                         if (IS_G4X(dev_priv)) {
14206                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14207                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14208                         }
14209                         if (IS_G4X(dev_priv))
14210                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14211                 }
14212
14213                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14214                         intel_dp_init(dev_priv, DP_D, PORT_D);
14215         } else if (IS_GEN2(dev_priv))
14216                 intel_dvo_init(dev_priv);
14217
14218         if (SUPPORTS_TV(dev_priv))
14219                 intel_tv_init(dev_priv);
14220
14221         intel_psr_init(dev_priv);
14222
14223         for_each_intel_encoder(&dev_priv->drm, encoder) {
14224                 encoder->base.possible_crtcs = encoder->crtc_mask;
14225                 encoder->base.possible_clones =
14226                         intel_encoder_clones(encoder);
14227         }
14228
14229         intel_init_pch_refclk(dev_priv);
14230
14231         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14232 }
14233
14234 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14235 {
14236         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14237
14238         drm_framebuffer_cleanup(fb);
14239
14240         i915_gem_object_lock(intel_fb->obj);
14241         WARN_ON(!intel_fb->obj->framebuffer_references--);
14242         i915_gem_object_unlock(intel_fb->obj);
14243
14244         i915_gem_object_put(intel_fb->obj);
14245
14246         kfree(intel_fb);
14247 }
14248
14249 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14250                                                 struct drm_file *file,
14251                                                 unsigned int *handle)
14252 {
14253         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14254         struct drm_i915_gem_object *obj = intel_fb->obj;
14255
14256         if (obj->userptr.mm) {
14257                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14258                 return -EINVAL;
14259         }
14260
14261         return drm_gem_handle_create(file, &obj->base, handle);
14262 }
14263
14264 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14265                                         struct drm_file *file,
14266                                         unsigned flags, unsigned color,
14267                                         struct drm_clip_rect *clips,
14268                                         unsigned num_clips)
14269 {
14270         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14271
14272         i915_gem_object_flush_if_display(obj);
14273         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14274
14275         return 0;
14276 }
14277
14278 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14279         .destroy = intel_user_framebuffer_destroy,
14280         .create_handle = intel_user_framebuffer_create_handle,
14281         .dirty = intel_user_framebuffer_dirty,
14282 };
14283
14284 static
14285 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14286                          uint64_t fb_modifier, uint32_t pixel_format)
14287 {
14288         u32 gen = INTEL_GEN(dev_priv);
14289
14290         if (gen >= 9) {
14291                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14292
14293                 /* "The stride in bytes must not exceed the of the size of 8K
14294                  *  pixels and 32K bytes."
14295                  */
14296                 return min(8192 * cpp, 32768);
14297         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14298                 return 32*1024;
14299         } else if (gen >= 4) {
14300                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14301                         return 16*1024;
14302                 else
14303                         return 32*1024;
14304         } else if (gen >= 3) {
14305                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14306                         return 8*1024;
14307                 else
14308                         return 16*1024;
14309         } else {
14310                 /* XXX DSPC is limited to 4k tiled */
14311                 return 8*1024;
14312         }
14313 }
14314
14315 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14316                                   struct drm_i915_gem_object *obj,
14317                                   struct drm_mode_fb_cmd2 *mode_cmd)
14318 {
14319         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14320         struct drm_format_name_buf format_name;
14321         u32 pitch_limit, stride_alignment;
14322         unsigned int tiling, stride;
14323         int ret = -EINVAL;
14324
14325         i915_gem_object_lock(obj);
14326         obj->framebuffer_references++;
14327         tiling = i915_gem_object_get_tiling(obj);
14328         stride = i915_gem_object_get_stride(obj);
14329         i915_gem_object_unlock(obj);
14330
14331         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14332                 /*
14333                  * If there's a fence, enforce that
14334                  * the fb modifier and tiling mode match.
14335                  */
14336                 if (tiling != I915_TILING_NONE &&
14337                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14338                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14339                         goto err;
14340                 }
14341         } else {
14342                 if (tiling == I915_TILING_X) {
14343                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14344                 } else if (tiling == I915_TILING_Y) {
14345                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14346                         goto err;
14347                 }
14348         }
14349
14350         /* Passed in modifier sanity checking. */
14351         switch (mode_cmd->modifier[0]) {
14352         case I915_FORMAT_MOD_Y_TILED:
14353         case I915_FORMAT_MOD_Yf_TILED:
14354                 if (INTEL_GEN(dev_priv) < 9) {
14355                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14356                                       mode_cmd->modifier[0]);
14357                         goto err;
14358                 }
14359         case DRM_FORMAT_MOD_LINEAR:
14360         case I915_FORMAT_MOD_X_TILED:
14361                 break;
14362         default:
14363                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14364                               mode_cmd->modifier[0]);
14365                 goto err;
14366         }
14367
14368         /*
14369          * gen2/3 display engine uses the fence if present,
14370          * so the tiling mode must match the fb modifier exactly.
14371          */
14372         if (INTEL_INFO(dev_priv)->gen < 4 &&
14373             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14374                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14375                 goto err;
14376         }
14377
14378         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14379                                            mode_cmd->pixel_format);
14380         if (mode_cmd->pitches[0] > pitch_limit) {
14381                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14382                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14383                               "tiled" : "linear",
14384                               mode_cmd->pitches[0], pitch_limit);
14385                 goto err;
14386         }
14387
14388         /*
14389          * If there's a fence, enforce that
14390          * the fb pitch and fence stride match.
14391          */
14392         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14393                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14394                               mode_cmd->pitches[0], stride);
14395                 goto err;
14396         }
14397
14398         /* Reject formats not supported by any plane early. */
14399         switch (mode_cmd->pixel_format) {
14400         case DRM_FORMAT_C8:
14401         case DRM_FORMAT_RGB565:
14402         case DRM_FORMAT_XRGB8888:
14403         case DRM_FORMAT_ARGB8888:
14404                 break;
14405         case DRM_FORMAT_XRGB1555:
14406                 if (INTEL_GEN(dev_priv) > 3) {
14407                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14408                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14409                         goto err;
14410                 }
14411                 break;
14412         case DRM_FORMAT_ABGR8888:
14413                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14414                     INTEL_GEN(dev_priv) < 9) {
14415                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14416                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14417                         goto err;
14418                 }
14419                 break;
14420         case DRM_FORMAT_XBGR8888:
14421         case DRM_FORMAT_XRGB2101010:
14422         case DRM_FORMAT_XBGR2101010:
14423                 if (INTEL_GEN(dev_priv) < 4) {
14424                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14425                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14426                         goto err;
14427                 }
14428                 break;
14429         case DRM_FORMAT_ABGR2101010:
14430                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14431                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14432                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14433                         goto err;
14434                 }
14435                 break;
14436         case DRM_FORMAT_YUYV:
14437         case DRM_FORMAT_UYVY:
14438         case DRM_FORMAT_YVYU:
14439         case DRM_FORMAT_VYUY:
14440                 if (INTEL_GEN(dev_priv) < 5) {
14441                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14442                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14443                         goto err;
14444                 }
14445                 break;
14446         default:
14447                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14448                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14449                 goto err;
14450         }
14451
14452         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14453         if (mode_cmd->offsets[0] != 0)
14454                 goto err;
14455
14456         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14457                                        &intel_fb->base, mode_cmd);
14458
14459         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14460         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14461                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14462                               mode_cmd->pitches[0], stride_alignment);
14463                 goto err;
14464         }
14465
14466         intel_fb->obj = obj;
14467
14468         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14469         if (ret)
14470                 goto err;
14471
14472         ret = drm_framebuffer_init(obj->base.dev,
14473                                    &intel_fb->base,
14474                                    &intel_fb_funcs);
14475         if (ret) {
14476                 DRM_ERROR("framebuffer init failed %d\n", ret);
14477                 goto err;
14478         }
14479
14480         return 0;
14481
14482 err:
14483         i915_gem_object_lock(obj);
14484         obj->framebuffer_references--;
14485         i915_gem_object_unlock(obj);
14486         return ret;
14487 }
14488
14489 static struct drm_framebuffer *
14490 intel_user_framebuffer_create(struct drm_device *dev,
14491                               struct drm_file *filp,
14492                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14493 {
14494         struct drm_framebuffer *fb;
14495         struct drm_i915_gem_object *obj;
14496         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14497
14498         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14499         if (!obj)
14500                 return ERR_PTR(-ENOENT);
14501
14502         fb = intel_framebuffer_create(obj, &mode_cmd);
14503         if (IS_ERR(fb))
14504                 i915_gem_object_put(obj);
14505
14506         return fb;
14507 }
14508
14509 static void intel_atomic_state_free(struct drm_atomic_state *state)
14510 {
14511         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14512
14513         drm_atomic_state_default_release(state);
14514
14515         i915_sw_fence_fini(&intel_state->commit_ready);
14516
14517         kfree(state);
14518 }
14519
14520 static const struct drm_mode_config_funcs intel_mode_funcs = {
14521         .fb_create = intel_user_framebuffer_create,
14522         .output_poll_changed = intel_fbdev_output_poll_changed,
14523         .atomic_check = intel_atomic_check,
14524         .atomic_commit = intel_atomic_commit,
14525         .atomic_state_alloc = intel_atomic_state_alloc,
14526         .atomic_state_clear = intel_atomic_state_clear,
14527         .atomic_state_free = intel_atomic_state_free,
14528 };
14529
14530 /**
14531  * intel_init_display_hooks - initialize the display modesetting hooks
14532  * @dev_priv: device private
14533  */
14534 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14535 {
14536         intel_init_cdclk_hooks(dev_priv);
14537
14538         if (INTEL_INFO(dev_priv)->gen >= 9) {
14539                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14540                 dev_priv->display.get_initial_plane_config =
14541                         skylake_get_initial_plane_config;
14542                 dev_priv->display.crtc_compute_clock =
14543                         haswell_crtc_compute_clock;
14544                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14545                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14546         } else if (HAS_DDI(dev_priv)) {
14547                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14548                 dev_priv->display.get_initial_plane_config =
14549                         ironlake_get_initial_plane_config;
14550                 dev_priv->display.crtc_compute_clock =
14551                         haswell_crtc_compute_clock;
14552                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14553                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14554         } else if (HAS_PCH_SPLIT(dev_priv)) {
14555                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14556                 dev_priv->display.get_initial_plane_config =
14557                         ironlake_get_initial_plane_config;
14558                 dev_priv->display.crtc_compute_clock =
14559                         ironlake_crtc_compute_clock;
14560                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14561                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14562         } else if (IS_CHERRYVIEW(dev_priv)) {
14563                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14564                 dev_priv->display.get_initial_plane_config =
14565                         i9xx_get_initial_plane_config;
14566                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14567                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14568                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14569         } else if (IS_VALLEYVIEW(dev_priv)) {
14570                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14571                 dev_priv->display.get_initial_plane_config =
14572                         i9xx_get_initial_plane_config;
14573                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14574                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14575                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14576         } else if (IS_G4X(dev_priv)) {
14577                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14578                 dev_priv->display.get_initial_plane_config =
14579                         i9xx_get_initial_plane_config;
14580                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14581                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14582                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14583         } else if (IS_PINEVIEW(dev_priv)) {
14584                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14585                 dev_priv->display.get_initial_plane_config =
14586                         i9xx_get_initial_plane_config;
14587                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14588                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14589                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14590         } else if (!IS_GEN2(dev_priv)) {
14591                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14592                 dev_priv->display.get_initial_plane_config =
14593                         i9xx_get_initial_plane_config;
14594                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14595                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14596                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14597         } else {
14598                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14599                 dev_priv->display.get_initial_plane_config =
14600                         i9xx_get_initial_plane_config;
14601                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14602                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14603                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14604         }
14605
14606         if (IS_GEN5(dev_priv)) {
14607                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14608         } else if (IS_GEN6(dev_priv)) {
14609                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14610         } else if (IS_IVYBRIDGE(dev_priv)) {
14611                 /* FIXME: detect B0+ stepping and use auto training */
14612                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14613         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14614                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14615         }
14616
14617         if (dev_priv->info.gen >= 9)
14618                 dev_priv->display.update_crtcs = skl_update_crtcs;
14619         else
14620                 dev_priv->display.update_crtcs = intel_update_crtcs;
14621
14622         switch (INTEL_INFO(dev_priv)->gen) {
14623         case 2:
14624                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14625                 break;
14626
14627         case 3:
14628                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14629                 break;
14630
14631         case 4:
14632         case 5:
14633                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14634                 break;
14635
14636         case 6:
14637                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14638                 break;
14639         case 7:
14640         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14641                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14642                 break;
14643         case 9:
14644                 /* Drop through - unsupported since execlist only. */
14645         default:
14646                 /* Default just returns -ENODEV to indicate unsupported */
14647                 dev_priv->display.queue_flip = intel_default_queue_flip;
14648         }
14649 }
14650
14651 /*
14652  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14653  * resume, or other times.  This quirk makes sure that's the case for
14654  * affected systems.
14655  */
14656 static void quirk_pipea_force(struct drm_device *dev)
14657 {
14658         struct drm_i915_private *dev_priv = to_i915(dev);
14659
14660         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14661         DRM_INFO("applying pipe a force quirk\n");
14662 }
14663
14664 static void quirk_pipeb_force(struct drm_device *dev)
14665 {
14666         struct drm_i915_private *dev_priv = to_i915(dev);
14667
14668         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14669         DRM_INFO("applying pipe b force quirk\n");
14670 }
14671
14672 /*
14673  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14674  */
14675 static void quirk_ssc_force_disable(struct drm_device *dev)
14676 {
14677         struct drm_i915_private *dev_priv = to_i915(dev);
14678         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14679         DRM_INFO("applying lvds SSC disable quirk\n");
14680 }
14681
14682 /*
14683  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14684  * brightness value
14685  */
14686 static void quirk_invert_brightness(struct drm_device *dev)
14687 {
14688         struct drm_i915_private *dev_priv = to_i915(dev);
14689         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14690         DRM_INFO("applying inverted panel brightness quirk\n");
14691 }
14692
14693 /* Some VBT's incorrectly indicate no backlight is present */
14694 static void quirk_backlight_present(struct drm_device *dev)
14695 {
14696         struct drm_i915_private *dev_priv = to_i915(dev);
14697         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14698         DRM_INFO("applying backlight present quirk\n");
14699 }
14700
14701 struct intel_quirk {
14702         int device;
14703         int subsystem_vendor;
14704         int subsystem_device;
14705         void (*hook)(struct drm_device *dev);
14706 };
14707
14708 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14709 struct intel_dmi_quirk {
14710         void (*hook)(struct drm_device *dev);
14711         const struct dmi_system_id (*dmi_id_list)[];
14712 };
14713
14714 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14715 {
14716         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14717         return 1;
14718 }
14719
14720 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14721         {
14722                 .dmi_id_list = &(const struct dmi_system_id[]) {
14723                         {
14724                                 .callback = intel_dmi_reverse_brightness,
14725                                 .ident = "NCR Corporation",
14726                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14727                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14728                                 },
14729                         },
14730                         { }  /* terminating entry */
14731                 },
14732                 .hook = quirk_invert_brightness,
14733         },
14734 };
14735
14736 static struct intel_quirk intel_quirks[] = {
14737         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14738         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14739
14740         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14741         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14742
14743         /* 830 needs to leave pipe A & dpll A up */
14744         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14745
14746         /* 830 needs to leave pipe B & dpll B up */
14747         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14748
14749         /* Lenovo U160 cannot use SSC on LVDS */
14750         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14751
14752         /* Sony Vaio Y cannot use SSC on LVDS */
14753         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14754
14755         /* Acer Aspire 5734Z must invert backlight brightness */
14756         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14757
14758         /* Acer/eMachines G725 */
14759         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14760
14761         /* Acer/eMachines e725 */
14762         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14763
14764         /* Acer/Packard Bell NCL20 */
14765         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14766
14767         /* Acer Aspire 4736Z */
14768         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14769
14770         /* Acer Aspire 5336 */
14771         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14772
14773         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14774         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14775
14776         /* Acer C720 Chromebook (Core i3 4005U) */
14777         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14778
14779         /* Apple Macbook 2,1 (Core 2 T7400) */
14780         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14781
14782         /* Apple Macbook 4,1 */
14783         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14784
14785         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14786         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14787
14788         /* HP Chromebook 14 (Celeron 2955U) */
14789         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14790
14791         /* Dell Chromebook 11 */
14792         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14793
14794         /* Dell Chromebook 11 (2015 version) */
14795         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14796 };
14797
14798 static void intel_init_quirks(struct drm_device *dev)
14799 {
14800         struct pci_dev *d = dev->pdev;
14801         int i;
14802
14803         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14804                 struct intel_quirk *q = &intel_quirks[i];
14805
14806                 if (d->device == q->device &&
14807                     (d->subsystem_vendor == q->subsystem_vendor ||
14808                      q->subsystem_vendor == PCI_ANY_ID) &&
14809                     (d->subsystem_device == q->subsystem_device ||
14810                      q->subsystem_device == PCI_ANY_ID))
14811                         q->hook(dev);
14812         }
14813         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14814                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14815                         intel_dmi_quirks[i].hook(dev);
14816         }
14817 }
14818
14819 /* Disable the VGA plane that we never use */
14820 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14821 {
14822         struct pci_dev *pdev = dev_priv->drm.pdev;
14823         u8 sr1;
14824         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14825
14826         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14827         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14828         outb(SR01, VGA_SR_INDEX);
14829         sr1 = inb(VGA_SR_DATA);
14830         outb(sr1 | 1<<5, VGA_SR_DATA);
14831         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14832         udelay(300);
14833
14834         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14835         POSTING_READ(vga_reg);
14836 }
14837
14838 void intel_modeset_init_hw(struct drm_device *dev)
14839 {
14840         struct drm_i915_private *dev_priv = to_i915(dev);
14841
14842         intel_update_cdclk(dev_priv);
14843         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14844
14845         intel_init_clock_gating(dev_priv);
14846 }
14847
14848 /*
14849  * Calculate what we think the watermarks should be for the state we've read
14850  * out of the hardware and then immediately program those watermarks so that
14851  * we ensure the hardware settings match our internal state.
14852  *
14853  * We can calculate what we think WM's should be by creating a duplicate of the
14854  * current state (which was constructed during hardware readout) and running it
14855  * through the atomic check code to calculate new watermark values in the
14856  * state object.
14857  */
14858 static void sanitize_watermarks(struct drm_device *dev)
14859 {
14860         struct drm_i915_private *dev_priv = to_i915(dev);
14861         struct drm_atomic_state *state;
14862         struct intel_atomic_state *intel_state;
14863         struct drm_crtc *crtc;
14864         struct drm_crtc_state *cstate;
14865         struct drm_modeset_acquire_ctx ctx;
14866         int ret;
14867         int i;
14868
14869         /* Only supported on platforms that use atomic watermark design */
14870         if (!dev_priv->display.optimize_watermarks)
14871                 return;
14872
14873         /*
14874          * We need to hold connection_mutex before calling duplicate_state so
14875          * that the connector loop is protected.
14876          */
14877         drm_modeset_acquire_init(&ctx, 0);
14878 retry:
14879         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14880         if (ret == -EDEADLK) {
14881                 drm_modeset_backoff(&ctx);
14882                 goto retry;
14883         } else if (WARN_ON(ret)) {
14884                 goto fail;
14885         }
14886
14887         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14888         if (WARN_ON(IS_ERR(state)))
14889                 goto fail;
14890
14891         intel_state = to_intel_atomic_state(state);
14892
14893         /*
14894          * Hardware readout is the only time we don't want to calculate
14895          * intermediate watermarks (since we don't trust the current
14896          * watermarks).
14897          */
14898         if (!HAS_GMCH_DISPLAY(dev_priv))
14899                 intel_state->skip_intermediate_wm = true;
14900
14901         ret = intel_atomic_check(dev, state);
14902         if (ret) {
14903                 /*
14904                  * If we fail here, it means that the hardware appears to be
14905                  * programmed in a way that shouldn't be possible, given our
14906                  * understanding of watermark requirements.  This might mean a
14907                  * mistake in the hardware readout code or a mistake in the
14908                  * watermark calculations for a given platform.  Raise a WARN
14909                  * so that this is noticeable.
14910                  *
14911                  * If this actually happens, we'll have to just leave the
14912                  * BIOS-programmed watermarks untouched and hope for the best.
14913                  */
14914                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14915                 goto put_state;
14916         }
14917
14918         /* Write calculated watermark values back */
14919         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14920                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14921
14922                 cs->wm.need_postvbl_update = true;
14923                 dev_priv->display.optimize_watermarks(intel_state, cs);
14924         }
14925
14926 put_state:
14927         drm_atomic_state_put(state);
14928 fail:
14929         drm_modeset_drop_locks(&ctx);
14930         drm_modeset_acquire_fini(&ctx);
14931 }
14932
14933 int intel_modeset_init(struct drm_device *dev)
14934 {
14935         struct drm_i915_private *dev_priv = to_i915(dev);
14936         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14937         enum pipe pipe;
14938         struct intel_crtc *crtc;
14939
14940         drm_mode_config_init(dev);
14941
14942         dev->mode_config.min_width = 0;
14943         dev->mode_config.min_height = 0;
14944
14945         dev->mode_config.preferred_depth = 24;
14946         dev->mode_config.prefer_shadow = 1;
14947
14948         dev->mode_config.allow_fb_modifiers = true;
14949
14950         dev->mode_config.funcs = &intel_mode_funcs;
14951
14952         INIT_WORK(&dev_priv->atomic_helper.free_work,
14953                   intel_atomic_helper_free_state_worker);
14954
14955         intel_init_quirks(dev);
14956
14957         intel_init_pm(dev_priv);
14958
14959         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14960                 return 0;
14961
14962         /*
14963          * There may be no VBT; and if the BIOS enabled SSC we can
14964          * just keep using it to avoid unnecessary flicker.  Whereas if the
14965          * BIOS isn't using it, don't assume it will work even if the VBT
14966          * indicates as much.
14967          */
14968         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14969                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14970                                             DREF_SSC1_ENABLE);
14971
14972                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14973                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14974                                      bios_lvds_use_ssc ? "en" : "dis",
14975                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14976                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14977                 }
14978         }
14979
14980         if (IS_GEN2(dev_priv)) {
14981                 dev->mode_config.max_width = 2048;
14982                 dev->mode_config.max_height = 2048;
14983         } else if (IS_GEN3(dev_priv)) {
14984                 dev->mode_config.max_width = 4096;
14985                 dev->mode_config.max_height = 4096;
14986         } else {
14987                 dev->mode_config.max_width = 8192;
14988                 dev->mode_config.max_height = 8192;
14989         }
14990
14991         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14992                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14993                 dev->mode_config.cursor_height = 1023;
14994         } else if (IS_GEN2(dev_priv)) {
14995                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14996                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14997         } else {
14998                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14999                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15000         }
15001
15002         dev->mode_config.fb_base = ggtt->mappable_base;
15003
15004         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15005                       INTEL_INFO(dev_priv)->num_pipes,
15006                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15007
15008         for_each_pipe(dev_priv, pipe) {
15009                 int ret;
15010
15011                 ret = intel_crtc_init(dev_priv, pipe);
15012                 if (ret) {
15013                         drm_mode_config_cleanup(dev);
15014                         return ret;
15015                 }
15016         }
15017
15018         intel_shared_dpll_init(dev);
15019
15020         intel_update_czclk(dev_priv);
15021         intel_modeset_init_hw(dev);
15022
15023         if (dev_priv->max_cdclk_freq == 0)
15024                 intel_update_max_cdclk(dev_priv);
15025
15026         /* Just disable it once at startup */
15027         i915_disable_vga(dev_priv);
15028         intel_setup_outputs(dev_priv);
15029
15030         drm_modeset_lock_all(dev);
15031         intel_modeset_setup_hw_state(dev);
15032         drm_modeset_unlock_all(dev);
15033
15034         for_each_intel_crtc(dev, crtc) {
15035                 struct intel_initial_plane_config plane_config = {};
15036
15037                 if (!crtc->active)
15038                         continue;
15039
15040                 /*
15041                  * Note that reserving the BIOS fb up front prevents us
15042                  * from stuffing other stolen allocations like the ring
15043                  * on top.  This prevents some ugliness at boot time, and
15044                  * can even allow for smooth boot transitions if the BIOS
15045                  * fb is large enough for the active pipe configuration.
15046                  */
15047                 dev_priv->display.get_initial_plane_config(crtc,
15048                                                            &plane_config);
15049
15050                 /*
15051                  * If the fb is shared between multiple heads, we'll
15052                  * just get the first one.
15053                  */
15054                 intel_find_initial_plane_obj(crtc, &plane_config);
15055         }
15056
15057         /*
15058          * Make sure hardware watermarks really match the state we read out.
15059          * Note that we need to do this after reconstructing the BIOS fb's
15060          * since the watermark calculation done here will use pstate->fb.
15061          */
15062         if (!HAS_GMCH_DISPLAY(dev_priv))
15063                 sanitize_watermarks(dev);
15064
15065         return 0;
15066 }
15067
15068 static void intel_enable_pipe_a(struct drm_device *dev)
15069 {
15070         struct intel_connector *connector;
15071         struct drm_connector_list_iter conn_iter;
15072         struct drm_connector *crt = NULL;
15073         struct intel_load_detect_pipe load_detect_temp;
15074         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15075         int ret;
15076
15077         /* We can't just switch on the pipe A, we need to set things up with a
15078          * proper mode and output configuration. As a gross hack, enable pipe A
15079          * by enabling the load detect pipe once. */
15080         drm_connector_list_iter_begin(dev, &conn_iter);
15081         for_each_intel_connector_iter(connector, &conn_iter) {
15082                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15083                         crt = &connector->base;
15084                         break;
15085                 }
15086         }
15087         drm_connector_list_iter_end(&conn_iter);
15088
15089         if (!crt)
15090                 return;
15091
15092         ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx);
15093         WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n");
15094
15095         if (ret > 0)
15096                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15097 }
15098
15099 static bool
15100 intel_check_plane_mapping(struct intel_crtc *crtc)
15101 {
15102         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15103         u32 val;
15104
15105         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15106                 return true;
15107
15108         val = I915_READ(DSPCNTR(!crtc->plane));
15109
15110         if ((val & DISPLAY_PLANE_ENABLE) &&
15111             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15112                 return false;
15113
15114         return true;
15115 }
15116
15117 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15118 {
15119         struct drm_device *dev = crtc->base.dev;
15120         struct intel_encoder *encoder;
15121
15122         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15123                 return true;
15124
15125         return false;
15126 }
15127
15128 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15129 {
15130         struct drm_device *dev = encoder->base.dev;
15131         struct intel_connector *connector;
15132
15133         for_each_connector_on_encoder(dev, &encoder->base, connector)
15134                 return connector;
15135
15136         return NULL;
15137 }
15138
15139 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15140                               enum transcoder pch_transcoder)
15141 {
15142         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15143                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15144 }
15145
15146 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15147 {
15148         struct drm_device *dev = crtc->base.dev;
15149         struct drm_i915_private *dev_priv = to_i915(dev);
15150         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15151
15152         /* Clear any frame start delays used for debugging left by the BIOS */
15153         if (!transcoder_is_dsi(cpu_transcoder)) {
15154                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15155
15156                 I915_WRITE(reg,
15157                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15158         }
15159
15160         /* restore vblank interrupts to correct state */
15161         drm_crtc_vblank_reset(&crtc->base);
15162         if (crtc->active) {
15163                 struct intel_plane *plane;
15164
15165                 drm_crtc_vblank_on(&crtc->base);
15166
15167                 /* Disable everything but the primary plane */
15168                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15169                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15170                                 continue;
15171
15172                         trace_intel_disable_plane(&plane->base, crtc);
15173                         plane->disable_plane(&plane->base, &crtc->base);
15174                 }
15175         }
15176
15177         /* We need to sanitize the plane -> pipe mapping first because this will
15178          * disable the crtc (and hence change the state) if it is wrong. Note
15179          * that gen4+ has a fixed plane -> pipe mapping.  */
15180         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15181                 bool plane;
15182
15183                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15184                               crtc->base.base.id, crtc->base.name);
15185
15186                 /* Pipe has the wrong plane attached and the plane is active.
15187                  * Temporarily change the plane mapping and disable everything
15188                  * ...  */
15189                 plane = crtc->plane;
15190                 crtc->base.primary->state->visible = true;
15191                 crtc->plane = !plane;
15192                 intel_crtc_disable_noatomic(&crtc->base);
15193                 crtc->plane = plane;
15194         }
15195
15196         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15197             crtc->pipe == PIPE_A && !crtc->active) {
15198                 /* BIOS forgot to enable pipe A, this mostly happens after
15199                  * resume. Force-enable the pipe to fix this, the update_dpms
15200                  * call below we restore the pipe to the right state, but leave
15201                  * the required bits on. */
15202                 intel_enable_pipe_a(dev);
15203         }
15204
15205         /* Adjust the state of the output pipe according to whether we
15206          * have active connectors/encoders. */
15207         if (crtc->active && !intel_crtc_has_encoders(crtc))
15208                 intel_crtc_disable_noatomic(&crtc->base);
15209
15210         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15211                 /*
15212                  * We start out with underrun reporting disabled to avoid races.
15213                  * For correct bookkeeping mark this on active crtcs.
15214                  *
15215                  * Also on gmch platforms we dont have any hardware bits to
15216                  * disable the underrun reporting. Which means we need to start
15217                  * out with underrun reporting disabled also on inactive pipes,
15218                  * since otherwise we'll complain about the garbage we read when
15219                  * e.g. coming up after runtime pm.
15220                  *
15221                  * No protection against concurrent access is required - at
15222                  * worst a fifo underrun happens which also sets this to false.
15223                  */
15224                 crtc->cpu_fifo_underrun_disabled = true;
15225                 /*
15226                  * We track the PCH trancoder underrun reporting state
15227                  * within the crtc. With crtc for pipe A housing the underrun
15228                  * reporting state for PCH transcoder A, crtc for pipe B housing
15229                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15230                  * and marking underrun reporting as disabled for the non-existing
15231                  * PCH transcoders B and C would prevent enabling the south
15232                  * error interrupt (see cpt_can_enable_serr_int()).
15233                  */
15234                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15235                         crtc->pch_fifo_underrun_disabled = true;
15236         }
15237 }
15238
15239 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15240 {
15241         struct intel_connector *connector;
15242
15243         /* We need to check both for a crtc link (meaning that the
15244          * encoder is active and trying to read from a pipe) and the
15245          * pipe itself being active. */
15246         bool has_active_crtc = encoder->base.crtc &&
15247                 to_intel_crtc(encoder->base.crtc)->active;
15248
15249         connector = intel_encoder_find_connector(encoder);
15250         if (connector && !has_active_crtc) {
15251                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15252                               encoder->base.base.id,
15253                               encoder->base.name);
15254
15255                 /* Connector is active, but has no active pipe. This is
15256                  * fallout from our resume register restoring. Disable
15257                  * the encoder manually again. */
15258                 if (encoder->base.crtc) {
15259                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15260
15261                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15262                                       encoder->base.base.id,
15263                                       encoder->base.name);
15264                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15265                         if (encoder->post_disable)
15266                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15267                 }
15268                 encoder->base.crtc = NULL;
15269
15270                 /* Inconsistent output/port/pipe state happens presumably due to
15271                  * a bug in one of the get_hw_state functions. Or someplace else
15272                  * in our code, like the register restore mess on resume. Clamp
15273                  * things to off as a safer default. */
15274
15275                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15276                 connector->base.encoder = NULL;
15277         }
15278         /* Enabled encoders without active connectors will be fixed in
15279          * the crtc fixup. */
15280 }
15281
15282 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15283 {
15284         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15285
15286         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15287                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15288                 i915_disable_vga(dev_priv);
15289         }
15290 }
15291
15292 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15293 {
15294         /* This function can be called both from intel_modeset_setup_hw_state or
15295          * at a very early point in our resume sequence, where the power well
15296          * structures are not yet restored. Since this function is at a very
15297          * paranoid "someone might have enabled VGA while we were not looking"
15298          * level, just check if the power well is enabled instead of trying to
15299          * follow the "don't touch the power well if we don't need it" policy
15300          * the rest of the driver uses. */
15301         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15302                 return;
15303
15304         i915_redisable_vga_power_on(dev_priv);
15305
15306         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15307 }
15308
15309 static bool primary_get_hw_state(struct intel_plane *plane)
15310 {
15311         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15312
15313         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15314 }
15315
15316 /* FIXME read out full plane state for all planes */
15317 static void readout_plane_state(struct intel_crtc *crtc)
15318 {
15319         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15320         bool visible;
15321
15322         visible = crtc->active && primary_get_hw_state(primary);
15323
15324         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15325                                 to_intel_plane_state(primary->base.state),
15326                                 visible);
15327 }
15328
15329 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15330 {
15331         struct drm_i915_private *dev_priv = to_i915(dev);
15332         enum pipe pipe;
15333         struct intel_crtc *crtc;
15334         struct intel_encoder *encoder;
15335         struct intel_connector *connector;
15336         struct drm_connector_list_iter conn_iter;
15337         int i;
15338
15339         dev_priv->active_crtcs = 0;
15340
15341         for_each_intel_crtc(dev, crtc) {
15342                 struct intel_crtc_state *crtc_state =
15343                         to_intel_crtc_state(crtc->base.state);
15344
15345                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15346                 memset(crtc_state, 0, sizeof(*crtc_state));
15347                 crtc_state->base.crtc = &crtc->base;
15348
15349                 crtc_state->base.active = crtc_state->base.enable =
15350                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15351
15352                 crtc->base.enabled = crtc_state->base.enable;
15353                 crtc->active = crtc_state->base.active;
15354
15355                 if (crtc_state->base.active)
15356                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15357
15358                 readout_plane_state(crtc);
15359
15360                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15361                               crtc->base.base.id, crtc->base.name,
15362                               enableddisabled(crtc_state->base.active));
15363         }
15364
15365         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15366                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15367
15368                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15369                                                   &pll->state.hw_state);
15370                 pll->state.crtc_mask = 0;
15371                 for_each_intel_crtc(dev, crtc) {
15372                         struct intel_crtc_state *crtc_state =
15373                                 to_intel_crtc_state(crtc->base.state);
15374
15375                         if (crtc_state->base.active &&
15376                             crtc_state->shared_dpll == pll)
15377                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15378                 }
15379                 pll->active_mask = pll->state.crtc_mask;
15380
15381                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15382                               pll->name, pll->state.crtc_mask, pll->on);
15383         }
15384
15385         for_each_intel_encoder(dev, encoder) {
15386                 pipe = 0;
15387
15388                 if (encoder->get_hw_state(encoder, &pipe)) {
15389                         struct intel_crtc_state *crtc_state;
15390
15391                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15392                         crtc_state = to_intel_crtc_state(crtc->base.state);
15393
15394                         encoder->base.crtc = &crtc->base;
15395                         crtc_state->output_types |= 1 << encoder->type;
15396                         encoder->get_config(encoder, crtc_state);
15397                 } else {
15398                         encoder->base.crtc = NULL;
15399                 }
15400
15401                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15402                               encoder->base.base.id, encoder->base.name,
15403                               enableddisabled(encoder->base.crtc),
15404                               pipe_name(pipe));
15405         }
15406
15407         drm_connector_list_iter_begin(dev, &conn_iter);
15408         for_each_intel_connector_iter(connector, &conn_iter) {
15409                 if (connector->get_hw_state(connector)) {
15410                         connector->base.dpms = DRM_MODE_DPMS_ON;
15411
15412                         encoder = connector->encoder;
15413                         connector->base.encoder = &encoder->base;
15414
15415                         if (encoder->base.crtc &&
15416                             encoder->base.crtc->state->active) {
15417                                 /*
15418                                  * This has to be done during hardware readout
15419                                  * because anything calling .crtc_disable may
15420                                  * rely on the connector_mask being accurate.
15421                                  */
15422                                 encoder->base.crtc->state->connector_mask |=
15423                                         1 << drm_connector_index(&connector->base);
15424                                 encoder->base.crtc->state->encoder_mask |=
15425                                         1 << drm_encoder_index(&encoder->base);
15426                         }
15427
15428                 } else {
15429                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15430                         connector->base.encoder = NULL;
15431                 }
15432                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15433                               connector->base.base.id, connector->base.name,
15434                               enableddisabled(connector->base.encoder));
15435         }
15436         drm_connector_list_iter_end(&conn_iter);
15437
15438         for_each_intel_crtc(dev, crtc) {
15439                 struct intel_crtc_state *crtc_state =
15440                         to_intel_crtc_state(crtc->base.state);
15441                 int pixclk = 0;
15442
15443                 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15444
15445                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15446                 if (crtc_state->base.active) {
15447                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15448                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15449                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15450
15451                         /*
15452                          * The initial mode needs to be set in order to keep
15453                          * the atomic core happy. It wants a valid mode if the
15454                          * crtc's enabled, so we do the above call.
15455                          *
15456                          * But we don't set all the derived state fully, hence
15457                          * set a flag to indicate that a full recalculation is
15458                          * needed on the next commit.
15459                          */
15460                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15461
15462                         intel_crtc_compute_pixel_rate(crtc_state);
15463
15464                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15465                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15466                                 pixclk = crtc_state->pixel_rate;
15467                         else
15468                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15469
15470                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15471                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15472                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15473
15474                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15475                         update_scanline_offset(crtc);
15476                 }
15477
15478                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15479
15480                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15481         }
15482 }
15483
15484 static void
15485 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15486 {
15487         struct intel_encoder *encoder;
15488
15489         for_each_intel_encoder(&dev_priv->drm, encoder) {
15490                 u64 get_domains;
15491                 enum intel_display_power_domain domain;
15492
15493                 if (!encoder->get_power_domains)
15494                         continue;
15495
15496                 get_domains = encoder->get_power_domains(encoder);
15497                 for_each_power_domain(domain, get_domains)
15498                         intel_display_power_get(dev_priv, domain);
15499         }
15500 }
15501
15502 /* Scan out the current hw modeset state,
15503  * and sanitizes it to the current state
15504  */
15505 static void
15506 intel_modeset_setup_hw_state(struct drm_device *dev)
15507 {
15508         struct drm_i915_private *dev_priv = to_i915(dev);
15509         enum pipe pipe;
15510         struct intel_crtc *crtc;
15511         struct intel_encoder *encoder;
15512         int i;
15513
15514         intel_modeset_readout_hw_state(dev);
15515
15516         /* HW state is read out, now we need to sanitize this mess. */
15517         get_encoder_power_domains(dev_priv);
15518
15519         for_each_intel_encoder(dev, encoder) {
15520                 intel_sanitize_encoder(encoder);
15521         }
15522
15523         for_each_pipe(dev_priv, pipe) {
15524                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15525
15526                 intel_sanitize_crtc(crtc);
15527                 intel_dump_pipe_config(crtc, crtc->config,
15528                                        "[setup_hw_state]");
15529         }
15530
15531         intel_modeset_update_connector_atomic_state(dev);
15532
15533         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15534                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15535
15536                 if (!pll->on || pll->active_mask)
15537                         continue;
15538
15539                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15540
15541                 pll->funcs.disable(dev_priv, pll);
15542                 pll->on = false;
15543         }
15544
15545         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15546                 vlv_wm_get_hw_state(dev);
15547                 vlv_wm_sanitize(dev_priv);
15548         } else if (IS_GEN9(dev_priv)) {
15549                 skl_wm_get_hw_state(dev);
15550         } else if (HAS_PCH_SPLIT(dev_priv)) {
15551                 ilk_wm_get_hw_state(dev);
15552         }
15553
15554         for_each_intel_crtc(dev, crtc) {
15555                 u64 put_domains;
15556
15557                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15558                 if (WARN_ON(put_domains))
15559                         modeset_put_power_domains(dev_priv, put_domains);
15560         }
15561         intel_display_set_init_power(dev_priv, false);
15562
15563         intel_power_domains_verify_state(dev_priv);
15564
15565         intel_fbc_init_pipe_state(dev_priv);
15566 }
15567
15568 void intel_display_resume(struct drm_device *dev)
15569 {
15570         struct drm_i915_private *dev_priv = to_i915(dev);
15571         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15572         struct drm_modeset_acquire_ctx ctx;
15573         int ret;
15574
15575         dev_priv->modeset_restore_state = NULL;
15576         if (state)
15577                 state->acquire_ctx = &ctx;
15578
15579         /*
15580          * This is a cludge because with real atomic modeset mode_config.mutex
15581          * won't be taken. Unfortunately some probed state like
15582          * audio_codec_enable is still protected by mode_config.mutex, so lock
15583          * it here for now.
15584          */
15585         mutex_lock(&dev->mode_config.mutex);
15586         drm_modeset_acquire_init(&ctx, 0);
15587
15588         while (1) {
15589                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15590                 if (ret != -EDEADLK)
15591                         break;
15592
15593                 drm_modeset_backoff(&ctx);
15594         }
15595
15596         if (!ret)
15597                 ret = __intel_display_resume(dev, state, &ctx);
15598
15599         drm_modeset_drop_locks(&ctx);
15600         drm_modeset_acquire_fini(&ctx);
15601         mutex_unlock(&dev->mode_config.mutex);
15602
15603         if (ret)
15604                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15605         if (state)
15606                 drm_atomic_state_put(state);
15607 }
15608
15609 void intel_modeset_gem_init(struct drm_device *dev)
15610 {
15611         struct drm_i915_private *dev_priv = to_i915(dev);
15612
15613         intel_init_gt_powersave(dev_priv);
15614
15615         intel_setup_overlay(dev_priv);
15616 }
15617
15618 int intel_connector_register(struct drm_connector *connector)
15619 {
15620         struct intel_connector *intel_connector = to_intel_connector(connector);
15621         int ret;
15622
15623         ret = intel_backlight_device_register(intel_connector);
15624         if (ret)
15625                 goto err;
15626
15627         return 0;
15628
15629 err:
15630         return ret;
15631 }
15632
15633 void intel_connector_unregister(struct drm_connector *connector)
15634 {
15635         struct intel_connector *intel_connector = to_intel_connector(connector);
15636
15637         intel_backlight_device_unregister(intel_connector);
15638         intel_panel_destroy_backlight(connector);
15639 }
15640
15641 void intel_modeset_cleanup(struct drm_device *dev)
15642 {
15643         struct drm_i915_private *dev_priv = to_i915(dev);
15644
15645         flush_work(&dev_priv->atomic_helper.free_work);
15646         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15647
15648         intel_disable_gt_powersave(dev_priv);
15649
15650         /*
15651          * Interrupts and polling as the first thing to avoid creating havoc.
15652          * Too much stuff here (turning of connectors, ...) would
15653          * experience fancy races otherwise.
15654          */
15655         intel_irq_uninstall(dev_priv);
15656
15657         /*
15658          * Due to the hpd irq storm handling the hotplug work can re-arm the
15659          * poll handlers. Hence disable polling after hpd handling is shut down.
15660          */
15661         drm_kms_helper_poll_fini(dev);
15662
15663         intel_unregister_dsm_handler();
15664
15665         intel_fbc_global_disable(dev_priv);
15666
15667         /* flush any delayed tasks or pending work */
15668         flush_scheduled_work();
15669
15670         drm_mode_config_cleanup(dev);
15671
15672         intel_cleanup_overlay(dev_priv);
15673
15674         intel_cleanup_gt_powersave(dev_priv);
15675
15676         intel_teardown_gmbus(dev_priv);
15677 }
15678
15679 void intel_connector_attach_encoder(struct intel_connector *connector,
15680                                     struct intel_encoder *encoder)
15681 {
15682         connector->encoder = encoder;
15683         drm_mode_connector_attach_encoder(&connector->base,
15684                                           &encoder->base);
15685 }
15686
15687 /*
15688  * set vga decode state - true == enable VGA decode
15689  */
15690 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15691 {
15692         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15693         u16 gmch_ctrl;
15694
15695         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15696                 DRM_ERROR("failed to read control word\n");
15697                 return -EIO;
15698         }
15699
15700         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15701                 return 0;
15702
15703         if (state)
15704                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15705         else
15706                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15707
15708         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15709                 DRM_ERROR("failed to write control word\n");
15710                 return -EIO;
15711         }
15712
15713         return 0;
15714 }
15715
15716 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15717
15718 struct intel_display_error_state {
15719
15720         u32 power_well_driver;
15721
15722         int num_transcoders;
15723
15724         struct intel_cursor_error_state {
15725                 u32 control;
15726                 u32 position;
15727                 u32 base;
15728                 u32 size;
15729         } cursor[I915_MAX_PIPES];
15730
15731         struct intel_pipe_error_state {
15732                 bool power_domain_on;
15733                 u32 source;
15734                 u32 stat;
15735         } pipe[I915_MAX_PIPES];
15736
15737         struct intel_plane_error_state {
15738                 u32 control;
15739                 u32 stride;
15740                 u32 size;
15741                 u32 pos;
15742                 u32 addr;
15743                 u32 surface;
15744                 u32 tile_offset;
15745         } plane[I915_MAX_PIPES];
15746
15747         struct intel_transcoder_error_state {
15748                 bool power_domain_on;
15749                 enum transcoder cpu_transcoder;
15750
15751                 u32 conf;
15752
15753                 u32 htotal;
15754                 u32 hblank;
15755                 u32 hsync;
15756                 u32 vtotal;
15757                 u32 vblank;
15758                 u32 vsync;
15759         } transcoder[4];
15760 };
15761
15762 struct intel_display_error_state *
15763 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15764 {
15765         struct intel_display_error_state *error;
15766         int transcoders[] = {
15767                 TRANSCODER_A,
15768                 TRANSCODER_B,
15769                 TRANSCODER_C,
15770                 TRANSCODER_EDP,
15771         };
15772         int i;
15773
15774         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15775                 return NULL;
15776
15777         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15778         if (error == NULL)
15779                 return NULL;
15780
15781         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15782                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15783
15784         for_each_pipe(dev_priv, i) {
15785                 error->pipe[i].power_domain_on =
15786                         __intel_display_power_is_enabled(dev_priv,
15787                                                          POWER_DOMAIN_PIPE(i));
15788                 if (!error->pipe[i].power_domain_on)
15789                         continue;
15790
15791                 error->cursor[i].control = I915_READ(CURCNTR(i));
15792                 error->cursor[i].position = I915_READ(CURPOS(i));
15793                 error->cursor[i].base = I915_READ(CURBASE(i));
15794
15795                 error->plane[i].control = I915_READ(DSPCNTR(i));
15796                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15797                 if (INTEL_GEN(dev_priv) <= 3) {
15798                         error->plane[i].size = I915_READ(DSPSIZE(i));
15799                         error->plane[i].pos = I915_READ(DSPPOS(i));
15800                 }
15801                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15802                         error->plane[i].addr = I915_READ(DSPADDR(i));
15803                 if (INTEL_GEN(dev_priv) >= 4) {
15804                         error->plane[i].surface = I915_READ(DSPSURF(i));
15805                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15806                 }
15807
15808                 error->pipe[i].source = I915_READ(PIPESRC(i));
15809
15810                 if (HAS_GMCH_DISPLAY(dev_priv))
15811                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15812         }
15813
15814         /* Note: this does not include DSI transcoders. */
15815         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15816         if (HAS_DDI(dev_priv))
15817                 error->num_transcoders++; /* Account for eDP. */
15818
15819         for (i = 0; i < error->num_transcoders; i++) {
15820                 enum transcoder cpu_transcoder = transcoders[i];
15821
15822                 error->transcoder[i].power_domain_on =
15823                         __intel_display_power_is_enabled(dev_priv,
15824                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15825                 if (!error->transcoder[i].power_domain_on)
15826                         continue;
15827
15828                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15829
15830                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15831                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15832                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15833                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15834                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15835                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15836                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15837         }
15838
15839         return error;
15840 }
15841
15842 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15843
15844 void
15845 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15846                                 struct intel_display_error_state *error)
15847 {
15848         struct drm_i915_private *dev_priv = m->i915;
15849         int i;
15850
15851         if (!error)
15852                 return;
15853
15854         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15855         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15856                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15857                            error->power_well_driver);
15858         for_each_pipe(dev_priv, i) {
15859                 err_printf(m, "Pipe [%d]:\n", i);
15860                 err_printf(m, "  Power: %s\n",
15861                            onoff(error->pipe[i].power_domain_on));
15862                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15863                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15864
15865                 err_printf(m, "Plane [%d]:\n", i);
15866                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15867                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15868                 if (INTEL_GEN(dev_priv) <= 3) {
15869                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15870                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15871                 }
15872                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15873                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15874                 if (INTEL_GEN(dev_priv) >= 4) {
15875                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15876                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15877                 }
15878
15879                 err_printf(m, "Cursor [%d]:\n", i);
15880                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15881                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15882                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15883         }
15884
15885         for (i = 0; i < error->num_transcoders; i++) {
15886                 err_printf(m, "CPU transcoder: %s\n",
15887                            transcoder_name(error->transcoder[i].cpu_transcoder));
15888                 err_printf(m, "  Power: %s\n",
15889                            onoff(error->transcoder[i].power_domain_on));
15890                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15891                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15892                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15893                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15894                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15895                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15896                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15897         }
15898 }
15899
15900 #endif