2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
42 #include "drm_crtc_helper.h"
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
119 .find_pll = intel_find_best_PLL,
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
133 .find_pll = intel_find_best_PLL,
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
147 .find_pll = intel_find_best_PLL,
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
161 .find_pll = intel_find_best_PLL,
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
178 .find_pll = intel_g4x_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
192 .find_pll = intel_g4x_find_best_PLL,
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
207 .find_pll = intel_g4x_find_best_PLL,
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
222 .find_pll = intel_g4x_find_best_PLL,
225 static const intel_limit_t intel_limits_g4x_display_port = {
226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
235 .p2_slow = 10, .p2_fast = 10 },
236 .find_pll = intel_find_pll_g4x_dp,
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
242 /* Pineview's Ncounter is a ring counter */
243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
245 /* Pineview only has one combined m divider, which we treat as m2. */
246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 .find_pll = intel_find_best_PLL,
255 static const intel_limit_t intel_limits_pineview_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
266 .find_pll = intel_find_best_PLL,
269 /* Ironlake / Sandybridge
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
274 static const intel_limit_t intel_limits_ironlake_dac = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
285 .find_pll = intel_g4x_find_best_PLL,
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
299 .find_pll = intel_g4x_find_best_PLL,
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 .find_pll = intel_g4x_find_best_PLL,
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 .find_pll = intel_g4x_find_best_PLL,
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
339 .p1 = { .min = 2, .max = 6 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 .find_pll = intel_g4x_find_best_PLL,
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 10, .p2_fast = 10 },
356 .find_pll = intel_find_pll_ironlake_dp,
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 const intel_limit_t *limit;
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
370 if (refclk == 100000)
371 limit = &intel_limits_ironlake_dual_lvds_100m;
373 limit = &intel_limits_ironlake_dual_lvds;
375 if (refclk == 100000)
376 limit = &intel_limits_ironlake_single_lvds_100m;
378 limit = &intel_limits_ironlake_single_lvds;
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
382 limit = &intel_limits_ironlake_display_port;
384 limit = &intel_limits_ironlake_dac;
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
398 /* LVDS with dual channel */
399 limit = &intel_limits_g4x_dual_channel_lvds;
401 /* LVDS with dual channel */
402 limit = &intel_limits_g4x_single_channel_lvds;
403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405 limit = &intel_limits_g4x_hdmi;
406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407 limit = &intel_limits_g4x_sdvo;
408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409 limit = &intel_limits_g4x_display_port;
410 } else /* The option is for other outputs */
411 limit = &intel_limits_i9xx_sdvo;
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
421 if (HAS_PCH_SPLIT(dev))
422 limit = intel_ironlake_limit(crtc, refclk);
423 else if (IS_G4X(dev)) {
424 limit = intel_g4x_limit(crtc);
425 } else if (IS_PINEVIEW(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_pineview_lvds;
429 limit = &intel_limits_pineview_sdvo;
430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
434 limit = &intel_limits_i9xx_sdvo;
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437 limit = &intel_limits_i8xx_lvds;
439 limit = &intel_limits_i8xx_dvo;
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
466 * Returns whether any output on the specified pipe is of the specified type
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
481 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
492 INTELPllInvalid("p1 out of range\n");
493 if (clock->p < limit->p.min || limit->p.max < clock->p)
494 INTELPllInvalid("p out of range\n");
495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
496 INTELPllInvalid("m2 out of range\n");
497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
498 INTELPllInvalid("m1 out of range\n");
499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500 INTELPllInvalid("m1 <= m2\n");
501 if (clock->m < limit->m.min || limit->m.max < clock->m)
502 INTELPllInvalid("m out of range\n");
503 if (clock->n < limit->n.min || limit->n.max < clock->n)
504 INTELPllInvalid("n out of range\n");
505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506 INTELPllInvalid("vco out of range\n");
507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511 INTELPllInvalid("dot out of range\n");
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527 (I915_READ(LVDS)) != 0) {
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
536 clock.p2 = limit->p2.p2_fast;
538 clock.p2 = limit->p2.p2_slow;
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
543 clock.p2 = limit->p2.p2_fast;
546 memset(best_clock, 0, sizeof(*best_clock));
548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
561 intel_clock(dev, refclk, &clock);
562 if (!intel_PLL_is_valid(dev, limit,
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
576 return (err != target);
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
595 if (HAS_PCH_SPLIT(dev))
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
601 clock.p2 = limit->p2.p2_fast;
603 clock.p2 = limit->p2.p2_slow;
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
608 clock.p2 = limit->p2.p2_fast;
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
613 /* based on hardware requirement, prefer smaller n to precision */
614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615 /* based on hardware requirement, prefere larger m1,m2 */
616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
624 intel_clock(dev, refclk, &clock);
625 if (!intel_PLL_is_valid(dev, limit,
629 this_err = abs(clock.dot - target);
630 if (this_err < err_most) {
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
647 struct drm_device *dev = crtc->dev;
650 if (target < 200000) {
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
674 if (target < 200000) {
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
696 * intel_wait_for_vblank - wait for vblank on a given pipe
698 * @pipe: pipe to wait for
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 int pipestat_reg = PIPESTAT(pipe);
708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
724 /* Wait for vblank interrupt bit to set */
725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
728 DRM_DEBUG_KMS("vblank wait timed out\n");
732 * intel_wait_for_pipe_off - wait for pipe to turn off
734 * @pipe: pipe to wait for
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
741 * wait for the pipe register state bit to turn off
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
750 struct drm_i915_private *dev_priv = dev->dev_private;
752 if (INTEL_INFO(dev)->gen >= 4) {
753 int reg = PIPECONF(pipe);
755 /* Wait for the Pipe State to go off */
756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
761 int reg = PIPEDSL(pipe);
762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
764 /* Wait for the display line to settle */
766 last_line = I915_READ(reg) & DSL_LINEMASK;
768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
775 static const char *state_string(bool enabled)
777 return enabled ? "on" : "off";
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
806 reg = PCH_DPLL(pipe);
807 val = I915_READ(reg);
808 cur_state = !!(val & DPLL_VCO_ENABLE);
809 WARN(cur_state != state,
810 "PCH PLL state assertion failure (expected %s, current %s)\n",
811 state_string(state), state_string(cur_state));
813 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
814 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
816 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
817 enum pipe pipe, bool state)
823 reg = FDI_TX_CTL(pipe);
824 val = I915_READ(reg);
825 cur_state = !!(val & FDI_TX_ENABLE);
826 WARN(cur_state != state,
827 "FDI TX state assertion failure (expected %s, current %s)\n",
828 state_string(state), state_string(cur_state));
830 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
831 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
833 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
834 enum pipe pipe, bool state)
840 reg = FDI_RX_CTL(pipe);
841 val = I915_READ(reg);
842 cur_state = !!(val & FDI_RX_ENABLE);
843 WARN(cur_state != state,
844 "FDI RX state assertion failure (expected %s, current %s)\n",
845 state_string(state), state_string(cur_state));
847 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
848 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
850 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
856 /* ILK FDI PLL is always enabled */
857 if (dev_priv->info->gen == 5)
860 reg = FDI_TX_CTL(pipe);
861 val = I915_READ(reg);
862 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
865 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
871 reg = FDI_RX_CTL(pipe);
872 val = I915_READ(reg);
873 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
876 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
879 int pp_reg, lvds_reg;
881 enum pipe panel_pipe = PIPE_A;
884 if (HAS_PCH_SPLIT(dev_priv->dev)) {
885 pp_reg = PCH_PP_CONTROL;
892 val = I915_READ(pp_reg);
893 if (!(val & PANEL_POWER_ON) ||
894 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
897 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
900 WARN(panel_pipe == pipe && locked,
901 "panel assertion failure, pipe %c regs locked\n",
905 static void assert_pipe(struct drm_i915_private *dev_priv,
906 enum pipe pipe, bool state)
912 reg = PIPECONF(pipe);
913 val = I915_READ(reg);
914 cur_state = !!(val & PIPECONF_ENABLE);
915 WARN(cur_state != state,
916 "pipe %c assertion failure (expected %s, current %s)\n",
917 pipe_name(pipe), state_string(state), state_string(cur_state));
919 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
920 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
922 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
928 reg = DSPCNTR(plane);
929 val = I915_READ(reg);
930 WARN(!(val & DISPLAY_PLANE_ENABLE),
931 "plane %c assertion failure, should be active but is disabled\n",
935 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
942 /* Planes are fixed to pipes on ILK+ */
943 if (HAS_PCH_SPLIT(dev_priv->dev))
946 /* Need to check both planes against the pipe */
947 for (i = 0; i < 2; i++) {
949 val = I915_READ(reg);
950 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
951 DISPPLANE_SEL_PIPE_SHIFT;
952 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
953 "plane %c assertion failure, should be off on pipe %c but is still active\n",
954 plane_name(i), pipe_name(pipe));
958 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
963 val = I915_READ(PCH_DREF_CONTROL);
964 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
965 DREF_SUPERSPREAD_SOURCE_MASK));
966 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
969 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
976 reg = TRANSCONF(pipe);
977 val = I915_READ(reg);
978 enabled = !!(val & TRANS_ENABLE);
980 "transcoder assertion failed, should be off on pipe %c but is still active\n",
984 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
985 enum pipe pipe, u32 port_sel, u32 val)
987 if ((val & DP_PORT_EN) == 0)
990 if (HAS_PCH_CPT(dev_priv->dev)) {
991 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
992 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
993 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
996 if ((val & DP_PIPE_MASK) != (pipe << 30))
1002 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1003 enum pipe pipe, u32 val)
1005 if ((val & PORT_ENABLE) == 0)
1008 if (HAS_PCH_CPT(dev_priv->dev)) {
1009 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1012 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1018 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, u32 val)
1021 if ((val & LVDS_PORT_EN) == 0)
1024 if (HAS_PCH_CPT(dev_priv->dev)) {
1025 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1028 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1034 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, u32 val)
1037 if ((val & ADPA_DAC_ENABLE) == 0)
1039 if (HAS_PCH_CPT(dev_priv->dev)) {
1040 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1043 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1049 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1050 enum pipe pipe, int reg, u32 port_sel)
1052 u32 val = I915_READ(reg);
1053 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1054 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1055 reg, pipe_name(pipe));
1058 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, int reg)
1061 u32 val = I915_READ(reg);
1062 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1063 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1064 reg, pipe_name(pipe));
1067 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1073 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1074 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1075 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1078 val = I915_READ(reg);
1079 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1080 "PCH VGA enabled on transcoder %c, should be disabled\n",
1084 val = I915_READ(reg);
1085 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1086 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1089 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1090 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1091 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1095 * intel_enable_pll - enable a PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1099 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1100 * make sure the PLL reg is writable first though, since the panel write
1101 * protect mechanism may be enabled.
1103 * Note! This is for pre-ILK only.
1105 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1110 /* No really, not for ILK+ */
1111 BUG_ON(dev_priv->info->gen >= 5);
1113 /* PLL is protected by panel, make sure we can write it */
1114 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1115 assert_panel_unlocked(dev_priv, pipe);
1118 val = I915_READ(reg);
1119 val |= DPLL_VCO_ENABLE;
1121 /* We do this three times for luck */
1122 I915_WRITE(reg, val);
1124 udelay(150); /* wait for warmup */
1125 I915_WRITE(reg, val);
1127 udelay(150); /* wait for warmup */
1128 I915_WRITE(reg, val);
1130 udelay(150); /* wait for warmup */
1134 * intel_disable_pll - disable a PLL
1135 * @dev_priv: i915 private structure
1136 * @pipe: pipe PLL to disable
1138 * Disable the PLL for @pipe, making sure the pipe is off first.
1140 * Note! This is for pre-ILK only.
1142 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1147 /* Don't disable pipe A or pipe A PLLs if needed */
1148 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1151 /* Make sure the pipe isn't still relying on us */
1152 assert_pipe_disabled(dev_priv, pipe);
1155 val = I915_READ(reg);
1156 val &= ~DPLL_VCO_ENABLE;
1157 I915_WRITE(reg, val);
1162 * intel_enable_pch_pll - enable PCH PLL
1163 * @dev_priv: i915 private structure
1164 * @pipe: pipe PLL to enable
1166 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1167 * drives the transcoder clock.
1169 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1178 /* PCH only available on ILK+ */
1179 BUG_ON(dev_priv->info->gen < 5);
1181 /* PCH refclock must be enabled first */
1182 assert_pch_refclk_enabled(dev_priv);
1184 reg = PCH_DPLL(pipe);
1185 val = I915_READ(reg);
1186 val |= DPLL_VCO_ENABLE;
1187 I915_WRITE(reg, val);
1192 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1201 /* PCH only available on ILK+ */
1202 BUG_ON(dev_priv->info->gen < 5);
1204 /* Make sure transcoder isn't still depending on us */
1205 assert_transcoder_disabled(dev_priv, pipe);
1207 reg = PCH_DPLL(pipe);
1208 val = I915_READ(reg);
1209 val &= ~DPLL_VCO_ENABLE;
1210 I915_WRITE(reg, val);
1215 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1221 /* PCH only available on ILK+ */
1222 BUG_ON(dev_priv->info->gen < 5);
1224 /* Make sure PCH DPLL is enabled */
1225 assert_pch_pll_enabled(dev_priv, pipe);
1227 /* FDI must be feeding us bits for PCH ports */
1228 assert_fdi_tx_enabled(dev_priv, pipe);
1229 assert_fdi_rx_enabled(dev_priv, pipe);
1231 reg = TRANSCONF(pipe);
1232 val = I915_READ(reg);
1234 if (HAS_PCH_IBX(dev_priv->dev)) {
1236 * make the BPC in transcoder be consistent with
1237 * that in pipeconf reg.
1239 val &= ~PIPE_BPC_MASK;
1240 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1242 I915_WRITE(reg, val | TRANS_ENABLE);
1243 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1244 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1247 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1253 /* FDI relies on the transcoder */
1254 assert_fdi_tx_disabled(dev_priv, pipe);
1255 assert_fdi_rx_disabled(dev_priv, pipe);
1257 /* Ports must be off as well */
1258 assert_pch_ports_disabled(dev_priv, pipe);
1260 reg = TRANSCONF(pipe);
1261 val = I915_READ(reg);
1262 val &= ~TRANS_ENABLE;
1263 I915_WRITE(reg, val);
1264 /* wait for PCH transcoder off, transcoder state */
1265 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1266 DRM_ERROR("failed to disable transcoder\n");
1270 * intel_enable_pipe - enable a pipe, asserting requirements
1271 * @dev_priv: i915 private structure
1272 * @pipe: pipe to enable
1273 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1275 * Enable @pipe, making sure that various hardware specific requirements
1276 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1278 * @pipe should be %PIPE_A or %PIPE_B.
1280 * Will wait until the pipe is actually running (i.e. first vblank) before
1283 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1290 * A pipe without a PLL won't actually be able to drive bits from
1291 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1294 if (!HAS_PCH_SPLIT(dev_priv->dev))
1295 assert_pll_enabled(dev_priv, pipe);
1298 /* if driving the PCH, we need FDI enabled */
1299 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1300 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1302 /* FIXME: assert CPU port conditions for SNB+ */
1305 reg = PIPECONF(pipe);
1306 val = I915_READ(reg);
1307 if (val & PIPECONF_ENABLE)
1310 I915_WRITE(reg, val | PIPECONF_ENABLE);
1311 intel_wait_for_vblank(dev_priv->dev, pipe);
1315 * intel_disable_pipe - disable a pipe, asserting requirements
1316 * @dev_priv: i915 private structure
1317 * @pipe: pipe to disable
1319 * Disable @pipe, making sure that various hardware specific requirements
1320 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1322 * @pipe should be %PIPE_A or %PIPE_B.
1324 * Will wait until the pipe has shut down before returning.
1326 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1333 * Make sure planes won't keep trying to pump pixels to us,
1334 * or we might hang the display.
1336 assert_planes_disabled(dev_priv, pipe);
1338 /* Don't disable pipe A or pipe A PLLs if needed */
1339 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1342 reg = PIPECONF(pipe);
1343 val = I915_READ(reg);
1344 if ((val & PIPECONF_ENABLE) == 0)
1347 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1348 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1352 * Plane regs are double buffered, going from enabled->disabled needs a
1353 * trigger in order to latch. The display address reg provides this.
1355 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1358 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1359 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1363 * intel_enable_plane - enable a display plane on a given pipe
1364 * @dev_priv: i915 private structure
1365 * @plane: plane to enable
1366 * @pipe: pipe being fed
1368 * Enable @plane on @pipe, making sure that @pipe is running first.
1370 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1371 enum plane plane, enum pipe pipe)
1376 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1377 assert_pipe_enabled(dev_priv, pipe);
1379 reg = DSPCNTR(plane);
1380 val = I915_READ(reg);
1381 if (val & DISPLAY_PLANE_ENABLE)
1384 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1385 intel_flush_display_plane(dev_priv, plane);
1386 intel_wait_for_vblank(dev_priv->dev, pipe);
1390 * intel_disable_plane - disable a display plane
1391 * @dev_priv: i915 private structure
1392 * @plane: plane to disable
1393 * @pipe: pipe consuming the data
1395 * Disable @plane; should be an independent operation.
1397 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1398 enum plane plane, enum pipe pipe)
1403 reg = DSPCNTR(plane);
1404 val = I915_READ(reg);
1405 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1408 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1409 intel_flush_display_plane(dev_priv, plane);
1410 intel_wait_for_vblank(dev_priv->dev, pipe);
1413 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, int reg, u32 port_sel)
1416 u32 val = I915_READ(reg);
1417 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1418 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1419 I915_WRITE(reg, val & ~DP_PORT_EN);
1423 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1424 enum pipe pipe, int reg)
1426 u32 val = I915_READ(reg);
1427 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1428 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1430 I915_WRITE(reg, val & ~PORT_ENABLE);
1434 /* Disable any ports connected to this transcoder */
1435 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1440 val = I915_READ(PCH_PP_CONTROL);
1441 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1443 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1444 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1445 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1448 val = I915_READ(reg);
1449 if (adpa_pipe_enabled(dev_priv, val, pipe))
1450 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1453 val = I915_READ(reg);
1454 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1455 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1456 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1461 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1462 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1463 disable_pch_hdmi(dev_priv, pipe, HDMID);
1466 static void i8xx_disable_fbc(struct drm_device *dev)
1468 struct drm_i915_private *dev_priv = dev->dev_private;
1471 /* Disable compression */
1472 fbc_ctl = I915_READ(FBC_CONTROL);
1473 if ((fbc_ctl & FBC_CTL_EN) == 0)
1476 fbc_ctl &= ~FBC_CTL_EN;
1477 I915_WRITE(FBC_CONTROL, fbc_ctl);
1479 /* Wait for compressing bit to clear */
1480 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1481 DRM_DEBUG_KMS("FBC idle timed out\n");
1485 DRM_DEBUG_KMS("disabled FBC\n");
1488 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1490 struct drm_device *dev = crtc->dev;
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 struct drm_framebuffer *fb = crtc->fb;
1493 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1494 struct drm_i915_gem_object *obj = intel_fb->obj;
1495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1498 u32 fbc_ctl, fbc_ctl2;
1500 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1501 if (fb->pitch < cfb_pitch)
1502 cfb_pitch = fb->pitch;
1504 /* FBC_CTL wants 64B units */
1505 cfb_pitch = (cfb_pitch / 64) - 1;
1506 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1508 /* Clear old tags */
1509 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1510 I915_WRITE(FBC_TAG + (i * 4), 0);
1513 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1515 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1516 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1519 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1521 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1522 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1523 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1524 fbc_ctl |= obj->fence_reg;
1525 I915_WRITE(FBC_CONTROL, fbc_ctl);
1527 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1528 cfb_pitch, crtc->y, intel_crtc->plane);
1531 static bool i8xx_fbc_enabled(struct drm_device *dev)
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1535 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1538 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1540 struct drm_device *dev = crtc->dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_framebuffer *fb = crtc->fb;
1543 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1544 struct drm_i915_gem_object *obj = intel_fb->obj;
1545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1546 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1547 unsigned long stall_watermark = 200;
1550 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1551 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1552 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1554 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1555 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1556 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1557 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1560 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1562 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1565 static void g4x_disable_fbc(struct drm_device *dev)
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1570 /* Disable compression */
1571 dpfc_ctl = I915_READ(DPFC_CONTROL);
1572 if (dpfc_ctl & DPFC_CTL_EN) {
1573 dpfc_ctl &= ~DPFC_CTL_EN;
1574 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1576 DRM_DEBUG_KMS("disabled FBC\n");
1580 static bool g4x_fbc_enabled(struct drm_device *dev)
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1584 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1587 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1592 /* Make sure blitter notifies FBC of writes */
1593 gen6_gt_force_wake_get(dev_priv);
1594 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1595 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1596 GEN6_BLITTER_LOCK_SHIFT;
1597 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1598 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1599 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1600 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1601 GEN6_BLITTER_LOCK_SHIFT);
1602 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1603 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1604 gen6_gt_force_wake_put(dev_priv);
1607 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1609 struct drm_device *dev = crtc->dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 struct drm_framebuffer *fb = crtc->fb;
1612 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1613 struct drm_i915_gem_object *obj = intel_fb->obj;
1614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1615 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1616 unsigned long stall_watermark = 200;
1619 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1620 dpfc_ctl &= DPFC_RESERVED;
1621 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1622 /* Set persistent mode for front-buffer rendering, ala X. */
1623 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1624 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1625 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1627 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1628 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1629 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1630 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1631 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1633 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1636 I915_WRITE(SNB_DPFC_CTL_SA,
1637 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1638 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1639 sandybridge_blit_fbc_update(dev);
1642 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1645 static void ironlake_disable_fbc(struct drm_device *dev)
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1650 /* Disable compression */
1651 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1652 if (dpfc_ctl & DPFC_CTL_EN) {
1653 dpfc_ctl &= ~DPFC_CTL_EN;
1654 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1656 DRM_DEBUG_KMS("disabled FBC\n");
1660 static bool ironlake_fbc_enabled(struct drm_device *dev)
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1664 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1667 bool intel_fbc_enabled(struct drm_device *dev)
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1671 if (!dev_priv->display.fbc_enabled)
1674 return dev_priv->display.fbc_enabled(dev);
1677 static void intel_fbc_work_fn(struct work_struct *__work)
1679 struct intel_fbc_work *work =
1680 container_of(to_delayed_work(__work),
1681 struct intel_fbc_work, work);
1682 struct drm_device *dev = work->crtc->dev;
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1685 mutex_lock(&dev->struct_mutex);
1686 if (work == dev_priv->fbc_work) {
1687 /* Double check that we haven't switched fb without cancelling
1690 if (work->crtc->fb == work->fb) {
1691 dev_priv->display.enable_fbc(work->crtc,
1694 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1695 dev_priv->cfb_fb = work->crtc->fb->base.id;
1696 dev_priv->cfb_y = work->crtc->y;
1699 dev_priv->fbc_work = NULL;
1701 mutex_unlock(&dev->struct_mutex);
1706 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1708 if (dev_priv->fbc_work == NULL)
1711 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1713 /* Synchronisation is provided by struct_mutex and checking of
1714 * dev_priv->fbc_work, so we can perform the cancellation
1715 * entirely asynchronously.
1717 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1718 /* tasklet was killed before being run, clean up */
1719 kfree(dev_priv->fbc_work);
1721 /* Mark the work as no longer wanted so that if it does
1722 * wake-up (because the work was already running and waiting
1723 * for our mutex), it will discover that is no longer
1726 dev_priv->fbc_work = NULL;
1729 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1731 struct intel_fbc_work *work;
1732 struct drm_device *dev = crtc->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1735 if (!dev_priv->display.enable_fbc)
1738 intel_cancel_fbc_work(dev_priv);
1740 work = kzalloc(sizeof *work, GFP_KERNEL);
1742 dev_priv->display.enable_fbc(crtc, interval);
1747 work->fb = crtc->fb;
1748 work->interval = interval;
1749 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1751 dev_priv->fbc_work = work;
1753 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1755 /* Delay the actual enabling to let pageflipping cease and the
1756 * display to settle before starting the compression. Note that
1757 * this delay also serves a second purpose: it allows for a
1758 * vblank to pass after disabling the FBC before we attempt
1759 * to modify the control registers.
1761 * A more complicated solution would involve tracking vblanks
1762 * following the termination of the page-flipping sequence
1763 * and indeed performing the enable as a co-routine and not
1764 * waiting synchronously upon the vblank.
1766 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1769 void intel_disable_fbc(struct drm_device *dev)
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1773 intel_cancel_fbc_work(dev_priv);
1775 if (!dev_priv->display.disable_fbc)
1778 dev_priv->display.disable_fbc(dev);
1779 dev_priv->cfb_plane = -1;
1783 * intel_update_fbc - enable/disable FBC as needed
1784 * @dev: the drm_device
1786 * Set up the framebuffer compression hardware at mode set time. We
1787 * enable it if possible:
1788 * - plane A only (on pre-965)
1789 * - no pixel mulitply/line duplication
1790 * - no alpha buffer discard
1792 * - framebuffer <= 2048 in width, 1536 in height
1794 * We can't assume that any compression will take place (worst case),
1795 * so the compressed buffer has to be the same size as the uncompressed
1796 * one. It also must reside (along with the line length buffer) in
1799 * We need to enable/disable FBC on a global basis.
1801 static void intel_update_fbc(struct drm_device *dev)
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct drm_crtc *crtc = NULL, *tmp_crtc;
1805 struct intel_crtc *intel_crtc;
1806 struct drm_framebuffer *fb;
1807 struct intel_framebuffer *intel_fb;
1808 struct drm_i915_gem_object *obj;
1811 DRM_DEBUG_KMS("\n");
1813 if (!i915_powersave)
1816 if (!I915_HAS_FBC(dev))
1820 * If FBC is already on, we just have to verify that we can
1821 * keep it that way...
1822 * Need to disable if:
1823 * - more than one pipe is active
1824 * - changing FBC params (stride, fence, mode)
1825 * - new fb is too large to fit in compressed buffer
1826 * - going to an unsupported config (interlace, pixel multiply, etc.)
1828 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1829 if (tmp_crtc->enabled && tmp_crtc->fb) {
1831 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1832 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1839 if (!crtc || crtc->fb == NULL) {
1840 DRM_DEBUG_KMS("no output, disabling\n");
1841 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1845 intel_crtc = to_intel_crtc(crtc);
1847 intel_fb = to_intel_framebuffer(fb);
1848 obj = intel_fb->obj;
1850 enable_fbc = i915_enable_fbc;
1851 if (enable_fbc < 0) {
1852 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1854 if (INTEL_INFO(dev)->gen <= 5)
1858 DRM_DEBUG_KMS("fbc disabled per module param\n");
1859 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1862 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1863 DRM_DEBUG_KMS("framebuffer too large, disabling "
1865 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1868 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1869 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1870 DRM_DEBUG_KMS("mode incompatible with compression, "
1872 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1875 if ((crtc->mode.hdisplay > 2048) ||
1876 (crtc->mode.vdisplay > 1536)) {
1877 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1878 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1881 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1882 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1883 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1887 /* The use of a CPU fence is mandatory in order to detect writes
1888 * by the CPU to the scanout and trigger updates to the FBC.
1890 if (obj->tiling_mode != I915_TILING_X ||
1891 obj->fence_reg == I915_FENCE_REG_NONE) {
1892 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1893 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1897 /* If the kernel debugger is active, always disable compression */
1898 if (in_dbg_master())
1901 /* If the scanout has not changed, don't modify the FBC settings.
1902 * Note that we make the fundamental assumption that the fb->obj
1903 * cannot be unpinned (and have its GTT offset and fence revoked)
1904 * without first being decoupled from the scanout and FBC disabled.
1906 if (dev_priv->cfb_plane == intel_crtc->plane &&
1907 dev_priv->cfb_fb == fb->base.id &&
1908 dev_priv->cfb_y == crtc->y)
1911 if (intel_fbc_enabled(dev)) {
1912 /* We update FBC along two paths, after changing fb/crtc
1913 * configuration (modeswitching) and after page-flipping
1914 * finishes. For the latter, we know that not only did
1915 * we disable the FBC at the start of the page-flip
1916 * sequence, but also more than one vblank has passed.
1918 * For the former case of modeswitching, it is possible
1919 * to switch between two FBC valid configurations
1920 * instantaneously so we do need to disable the FBC
1921 * before we can modify its control registers. We also
1922 * have to wait for the next vblank for that to take
1923 * effect. However, since we delay enabling FBC we can
1924 * assume that a vblank has passed since disabling and
1925 * that we can safely alter the registers in the deferred
1928 * In the scenario that we go from a valid to invalid
1929 * and then back to valid FBC configuration we have
1930 * no strict enforcement that a vblank occurred since
1931 * disabling the FBC. However, along all current pipe
1932 * disabling paths we do need to wait for a vblank at
1933 * some point. And we wait before enabling FBC anyway.
1935 DRM_DEBUG_KMS("disabling active FBC for update\n");
1936 intel_disable_fbc(dev);
1939 intel_enable_fbc(crtc, 500);
1943 /* Multiple disables should be harmless */
1944 if (intel_fbc_enabled(dev)) {
1945 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1946 intel_disable_fbc(dev);
1951 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1952 struct drm_i915_gem_object *obj,
1953 struct intel_ring_buffer *pipelined)
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1959 switch (obj->tiling_mode) {
1960 case I915_TILING_NONE:
1961 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1962 alignment = 128 * 1024;
1963 else if (INTEL_INFO(dev)->gen >= 4)
1964 alignment = 4 * 1024;
1966 alignment = 64 * 1024;
1969 /* pin() will align the object as required by fence */
1973 /* FIXME: Is this true? */
1974 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1980 dev_priv->mm.interruptible = false;
1981 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1983 goto err_interruptible;
1985 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1986 * fence, whereas 965+ only requires a fence if using
1987 * framebuffer compression. For simplicity, we always install
1988 * a fence as the cost is not that onerous.
1990 if (obj->tiling_mode != I915_TILING_NONE) {
1991 ret = i915_gem_object_get_fence(obj, pipelined);
1996 dev_priv->mm.interruptible = true;
2000 i915_gem_object_unpin(obj);
2002 dev_priv->mm.interruptible = true;
2006 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2009 struct drm_device *dev = crtc->dev;
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2012 struct intel_framebuffer *intel_fb;
2013 struct drm_i915_gem_object *obj;
2014 int plane = intel_crtc->plane;
2015 unsigned long Start, Offset;
2024 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2028 intel_fb = to_intel_framebuffer(fb);
2029 obj = intel_fb->obj;
2031 reg = DSPCNTR(plane);
2032 dspcntr = I915_READ(reg);
2033 /* Mask out pixel format bits in case we change it */
2034 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2035 switch (fb->bits_per_pixel) {
2037 dspcntr |= DISPPLANE_8BPP;
2040 if (fb->depth == 15)
2041 dspcntr |= DISPPLANE_15_16BPP;
2043 dspcntr |= DISPPLANE_16BPP;
2047 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2050 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2053 if (INTEL_INFO(dev)->gen >= 4) {
2054 if (obj->tiling_mode != I915_TILING_NONE)
2055 dspcntr |= DISPPLANE_TILED;
2057 dspcntr &= ~DISPPLANE_TILED;
2060 I915_WRITE(reg, dspcntr);
2062 Start = obj->gtt_offset;
2063 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2065 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2066 Start, Offset, x, y, fb->pitch);
2067 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2068 if (INTEL_INFO(dev)->gen >= 4) {
2069 I915_WRITE(DSPSURF(plane), Start);
2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071 I915_WRITE(DSPADDR(plane), Offset);
2073 I915_WRITE(DSPADDR(plane), Start + Offset);
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long Start, Offset;
2098 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109 switch (fb->bits_per_pixel) {
2111 dspcntr |= DISPPLANE_8BPP;
2114 if (fb->depth != 16)
2117 dspcntr |= DISPPLANE_16BPP;
2121 if (fb->depth == 24)
2122 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2123 else if (fb->depth == 30)
2124 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2129 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2133 if (obj->tiling_mode != I915_TILING_NONE)
2134 dspcntr |= DISPPLANE_TILED;
2136 dspcntr &= ~DISPPLANE_TILED;
2139 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2141 I915_WRITE(reg, dspcntr);
2143 Start = obj->gtt_offset;
2144 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2146 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2147 Start, Offset, x, y, fb->pitch);
2148 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2149 I915_WRITE(DSPSURF(plane), Start);
2150 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2151 I915_WRITE(DSPADDR(plane), Offset);
2157 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2159 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2160 int x, int y, enum mode_set_atomic state)
2162 struct drm_device *dev = crtc->dev;
2163 struct drm_i915_private *dev_priv = dev->dev_private;
2166 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2170 intel_update_fbc(dev);
2171 intel_increase_pllclock(crtc);
2177 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2178 struct drm_framebuffer *old_fb)
2180 struct drm_device *dev = crtc->dev;
2181 struct drm_i915_master_private *master_priv;
2182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2187 DRM_ERROR("No FB bound\n");
2191 switch (intel_crtc->plane) {
2196 if (IS_IVYBRIDGE(dev))
2198 /* fall through otherwise */
2200 DRM_ERROR("no plane for crtc\n");
2204 mutex_lock(&dev->struct_mutex);
2205 ret = intel_pin_and_fence_fb_obj(dev,
2206 to_intel_framebuffer(crtc->fb)->obj,
2209 mutex_unlock(&dev->struct_mutex);
2210 DRM_ERROR("pin & fence failed\n");
2215 struct drm_i915_private *dev_priv = dev->dev_private;
2216 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2218 wait_event(dev_priv->pending_flip_queue,
2219 atomic_read(&dev_priv->mm.wedged) ||
2220 atomic_read(&obj->pending_flip) == 0);
2222 /* Big Hammer, we also need to ensure that any pending
2223 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2224 * current scanout is retired before unpinning the old
2227 * This should only fail upon a hung GPU, in which case we
2228 * can safely continue.
2230 ret = i915_gem_object_finish_gpu(obj);
2234 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2235 LEAVE_ATOMIC_MODE_SET);
2237 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2238 mutex_unlock(&dev->struct_mutex);
2239 DRM_ERROR("failed to update base address\n");
2244 intel_wait_for_vblank(dev, intel_crtc->pipe);
2245 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2248 mutex_unlock(&dev->struct_mutex);
2250 if (!dev->primary->master)
2253 master_priv = dev->primary->master->driver_priv;
2254 if (!master_priv->sarea_priv)
2257 if (intel_crtc->pipe) {
2258 master_priv->sarea_priv->pipeB_x = x;
2259 master_priv->sarea_priv->pipeB_y = y;
2261 master_priv->sarea_priv->pipeA_x = x;
2262 master_priv->sarea_priv->pipeA_y = y;
2268 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2274 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2275 dpa_ctl = I915_READ(DP_A);
2276 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2278 if (clock < 200000) {
2280 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2281 /* workaround for 160Mhz:
2282 1) program 0x4600c bits 15:0 = 0x8124
2283 2) program 0x46010 bit 0 = 1
2284 3) program 0x46034 bit 24 = 1
2285 4) program 0x64000 bit 14 = 1
2287 temp = I915_READ(0x4600c);
2289 I915_WRITE(0x4600c, temp | 0x8124);
2291 temp = I915_READ(0x46010);
2292 I915_WRITE(0x46010, temp | 1);
2294 temp = I915_READ(0x46034);
2295 I915_WRITE(0x46034, temp | (1 << 24));
2297 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2299 I915_WRITE(DP_A, dpa_ctl);
2305 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2307 struct drm_device *dev = crtc->dev;
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2310 int pipe = intel_crtc->pipe;
2313 /* enable normal train */
2314 reg = FDI_TX_CTL(pipe);
2315 temp = I915_READ(reg);
2316 if (IS_IVYBRIDGE(dev)) {
2317 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2318 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2323 I915_WRITE(reg, temp);
2325 reg = FDI_RX_CTL(pipe);
2326 temp = I915_READ(reg);
2327 if (HAS_PCH_CPT(dev)) {
2328 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2329 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2331 temp &= ~FDI_LINK_TRAIN_NONE;
2332 temp |= FDI_LINK_TRAIN_NONE;
2334 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2336 /* wait one idle pattern time */
2340 /* IVB wants error correction enabled */
2341 if (IS_IVYBRIDGE(dev))
2342 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2343 FDI_FE_ERRC_ENABLE);
2346 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 u32 flags = I915_READ(SOUTH_CHICKEN1);
2351 flags |= FDI_PHASE_SYNC_OVR(pipe);
2352 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2353 flags |= FDI_PHASE_SYNC_EN(pipe);
2354 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2355 POSTING_READ(SOUTH_CHICKEN1);
2358 /* The FDI link training functions for ILK/Ibexpeak. */
2359 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2361 struct drm_device *dev = crtc->dev;
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364 int pipe = intel_crtc->pipe;
2365 int plane = intel_crtc->plane;
2366 u32 reg, temp, tries;
2368 /* FDI needs bits from pipe & plane first */
2369 assert_pipe_enabled(dev_priv, pipe);
2370 assert_plane_enabled(dev_priv, plane);
2372 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2374 reg = FDI_RX_IMR(pipe);
2375 temp = I915_READ(reg);
2376 temp &= ~FDI_RX_SYMBOL_LOCK;
2377 temp &= ~FDI_RX_BIT_LOCK;
2378 I915_WRITE(reg, temp);
2382 /* enable CPU FDI TX and PCH FDI RX */
2383 reg = FDI_TX_CTL(pipe);
2384 temp = I915_READ(reg);
2386 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2387 temp &= ~FDI_LINK_TRAIN_NONE;
2388 temp |= FDI_LINK_TRAIN_PATTERN_1;
2389 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2391 reg = FDI_RX_CTL(pipe);
2392 temp = I915_READ(reg);
2393 temp &= ~FDI_LINK_TRAIN_NONE;
2394 temp |= FDI_LINK_TRAIN_PATTERN_1;
2395 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400 /* Ironlake workaround, enable clock pointer after FDI enable*/
2401 if (HAS_PCH_IBX(dev)) {
2402 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2403 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2404 FDI_RX_PHASE_SYNC_POINTER_EN);
2407 reg = FDI_RX_IIR(pipe);
2408 for (tries = 0; tries < 5; tries++) {
2409 temp = I915_READ(reg);
2410 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412 if ((temp & FDI_RX_BIT_LOCK)) {
2413 DRM_DEBUG_KMS("FDI train 1 done.\n");
2414 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419 DRM_ERROR("FDI train 1 fail!\n");
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_2;
2426 I915_WRITE(reg, temp);
2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_2;
2432 I915_WRITE(reg, temp);
2437 reg = FDI_RX_IIR(pipe);
2438 for (tries = 0; tries < 5; tries++) {
2439 temp = I915_READ(reg);
2440 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2442 if (temp & FDI_RX_SYMBOL_LOCK) {
2443 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2444 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 DRM_ERROR("FDI train 2 fail!\n");
2451 DRM_DEBUG_KMS("FDI train done\n");
2455 static const int snb_b_fdi_train_param[] = {
2456 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2457 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2458 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2459 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2462 /* The FDI link training functions for SNB/Cougarpoint. */
2463 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 int pipe = intel_crtc->pipe;
2471 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2473 reg = FDI_RX_IMR(pipe);
2474 temp = I915_READ(reg);
2475 temp &= ~FDI_RX_SYMBOL_LOCK;
2476 temp &= ~FDI_RX_BIT_LOCK;
2477 I915_WRITE(reg, temp);
2482 /* enable CPU FDI TX and PCH FDI RX */
2483 reg = FDI_TX_CTL(pipe);
2484 temp = I915_READ(reg);
2486 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2487 temp &= ~FDI_LINK_TRAIN_NONE;
2488 temp |= FDI_LINK_TRAIN_PATTERN_1;
2489 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2491 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2492 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494 reg = FDI_RX_CTL(pipe);
2495 temp = I915_READ(reg);
2496 if (HAS_PCH_CPT(dev)) {
2497 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2503 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508 if (HAS_PCH_CPT(dev))
2509 cpt_phase_pointer_enable(dev, pipe);
2511 for (i = 0; i < 4; i++) {
2512 reg = FDI_TX_CTL(pipe);
2513 temp = I915_READ(reg);
2514 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2515 temp |= snb_b_fdi_train_param[i];
2516 I915_WRITE(reg, temp);
2521 reg = FDI_RX_IIR(pipe);
2522 temp = I915_READ(reg);
2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2525 if (temp & FDI_RX_BIT_LOCK) {
2526 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2527 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 DRM_ERROR("FDI train 1 fail!\n");
2535 reg = FDI_TX_CTL(pipe);
2536 temp = I915_READ(reg);
2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_PATTERN_2;
2540 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2542 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2544 I915_WRITE(reg, temp);
2546 reg = FDI_RX_CTL(pipe);
2547 temp = I915_READ(reg);
2548 if (HAS_PCH_CPT(dev)) {
2549 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2552 temp &= ~FDI_LINK_TRAIN_NONE;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2;
2555 I915_WRITE(reg, temp);
2560 for (i = 0; i < 4; i++) {
2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
2563 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564 temp |= snb_b_fdi_train_param[i];
2565 I915_WRITE(reg, temp);
2570 reg = FDI_RX_IIR(pipe);
2571 temp = I915_READ(reg);
2572 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574 if (temp & FDI_RX_SYMBOL_LOCK) {
2575 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2576 DRM_DEBUG_KMS("FDI train 2 done.\n");
2581 DRM_ERROR("FDI train 2 fail!\n");
2583 DRM_DEBUG_KMS("FDI train done.\n");
2586 /* Manual link training for Ivy Bridge A0 parts */
2587 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2589 struct drm_device *dev = crtc->dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2592 int pipe = intel_crtc->pipe;
2595 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2597 reg = FDI_RX_IMR(pipe);
2598 temp = I915_READ(reg);
2599 temp &= ~FDI_RX_SYMBOL_LOCK;
2600 temp &= ~FDI_RX_BIT_LOCK;
2601 I915_WRITE(reg, temp);
2606 /* enable CPU FDI TX and PCH FDI RX */
2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
2610 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2611 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2612 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2615 temp |= FDI_COMPOSITE_SYNC;
2616 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2618 reg = FDI_RX_CTL(pipe);
2619 temp = I915_READ(reg);
2620 temp &= ~FDI_LINK_TRAIN_AUTO;
2621 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2623 temp |= FDI_COMPOSITE_SYNC;
2624 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2629 if (HAS_PCH_CPT(dev))
2630 cpt_phase_pointer_enable(dev, pipe);
2632 for (i = 0; i < 4; i++) {
2633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
2635 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2636 temp |= snb_b_fdi_train_param[i];
2637 I915_WRITE(reg, temp);
2642 reg = FDI_RX_IIR(pipe);
2643 temp = I915_READ(reg);
2644 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2646 if (temp & FDI_RX_BIT_LOCK ||
2647 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2648 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2649 DRM_DEBUG_KMS("FDI train 1 done.\n");
2654 DRM_ERROR("FDI train 1 fail!\n");
2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2660 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663 I915_WRITE(reg, temp);
2665 reg = FDI_RX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2669 I915_WRITE(reg, temp);
2674 for (i = 0; i < 4; i++) {
2675 reg = FDI_TX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 temp |= snb_b_fdi_train_param[i];
2679 I915_WRITE(reg, temp);
2684 reg = FDI_RX_IIR(pipe);
2685 temp = I915_READ(reg);
2686 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2688 if (temp & FDI_RX_SYMBOL_LOCK) {
2689 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2690 DRM_DEBUG_KMS("FDI train 2 done.\n");
2695 DRM_ERROR("FDI train 2 fail!\n");
2697 DRM_DEBUG_KMS("FDI train done.\n");
2700 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2702 struct drm_device *dev = crtc->dev;
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2705 int pipe = intel_crtc->pipe;
2708 /* Write the TU size bits so error detection works */
2709 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2710 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2712 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~((0x7 << 19) | (0x7 << 16));
2716 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2717 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2718 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2723 /* Switch from Rawclk to PCDclk */
2724 temp = I915_READ(reg);
2725 I915_WRITE(reg, temp | FDI_PCDCLK);
2730 /* Enable CPU FDI TX PLL, always on for Ironlake */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2734 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2741 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 u32 flags = I915_READ(SOUTH_CHICKEN1);
2746 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2747 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2748 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2749 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2750 POSTING_READ(SOUTH_CHICKEN1);
2752 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2754 struct drm_device *dev = crtc->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2757 int pipe = intel_crtc->pipe;
2760 /* disable CPU FDI tx and PCH FDI rx */
2761 reg = FDI_TX_CTL(pipe);
2762 temp = I915_READ(reg);
2763 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2766 reg = FDI_RX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 temp &= ~(0x7 << 16);
2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2770 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2775 /* Ironlake workaround, disable clock pointer after downing FDI */
2776 if (HAS_PCH_IBX(dev)) {
2777 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2778 I915_WRITE(FDI_RX_CHICKEN(pipe),
2779 I915_READ(FDI_RX_CHICKEN(pipe) &
2780 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2781 } else if (HAS_PCH_CPT(dev)) {
2782 cpt_phase_pointer_disable(dev, pipe);
2785 /* still set train pattern 1 */
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 temp &= ~FDI_LINK_TRAIN_NONE;
2789 temp |= FDI_LINK_TRAIN_PATTERN_1;
2790 I915_WRITE(reg, temp);
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 if (HAS_PCH_CPT(dev)) {
2795 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2796 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2798 temp &= ~FDI_LINK_TRAIN_NONE;
2799 temp |= FDI_LINK_TRAIN_PATTERN_1;
2801 /* BPC in FDI rx is consistent with that in PIPECONF */
2802 temp &= ~(0x07 << 16);
2803 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2804 I915_WRITE(reg, temp);
2811 * When we disable a pipe, we need to clear any pending scanline wait events
2812 * to avoid hanging the ring, which we assume we are waiting on.
2814 static void intel_clear_scanline_wait(struct drm_device *dev)
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2817 struct intel_ring_buffer *ring;
2821 /* Can't break the hang on i8xx */
2824 ring = LP_RING(dev_priv);
2825 tmp = I915_READ_CTL(ring);
2826 if (tmp & RING_WAIT)
2827 I915_WRITE_CTL(ring, tmp);
2830 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2832 struct drm_i915_gem_object *obj;
2833 struct drm_i915_private *dev_priv;
2835 if (crtc->fb == NULL)
2838 obj = to_intel_framebuffer(crtc->fb)->obj;
2839 dev_priv = crtc->dev->dev_private;
2840 wait_event(dev_priv->pending_flip_queue,
2841 atomic_read(&obj->pending_flip) == 0);
2844 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2846 struct drm_device *dev = crtc->dev;
2847 struct drm_mode_config *mode_config = &dev->mode_config;
2848 struct intel_encoder *encoder;
2851 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2852 * must be driven by its own crtc; no sharing is possible.
2854 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2855 if (encoder->base.crtc != crtc)
2858 switch (encoder->type) {
2859 case INTEL_OUTPUT_EDP:
2860 if (!intel_encoder_is_pch_edp(&encoder->base))
2870 * Enable PCH resources required for PCH ports:
2872 * - FDI training & RX/TX
2873 * - update transcoder timings
2874 * - DP transcoding bits
2877 static void ironlake_pch_enable(struct drm_crtc *crtc)
2879 struct drm_device *dev = crtc->dev;
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2882 int pipe = intel_crtc->pipe;
2885 /* For PCH output, training FDI link */
2886 dev_priv->display.fdi_link_train(crtc);
2888 intel_enable_pch_pll(dev_priv, pipe);
2890 if (HAS_PCH_CPT(dev)) {
2891 /* Be sure PCH DPLL SEL is set */
2892 temp = I915_READ(PCH_DPLL_SEL);
2893 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2894 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2895 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2896 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2897 else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
2898 temp |= (TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2899 I915_WRITE(PCH_DPLL_SEL, temp);
2902 /* set transcoder timing, panel must allow it */
2903 assert_panel_unlocked(dev_priv, pipe);
2904 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2905 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2906 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2908 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2909 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2910 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2912 intel_fdi_normal_train(crtc);
2914 /* For PCH DP, enable TRANS_DP_CTL */
2915 if (HAS_PCH_CPT(dev) &&
2916 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2917 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2918 reg = TRANS_DP_CTL(pipe);
2919 temp = I915_READ(reg);
2920 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2921 TRANS_DP_SYNC_MASK |
2923 temp |= (TRANS_DP_OUTPUT_ENABLE |
2924 TRANS_DP_ENH_FRAMING);
2925 temp |= bpc << 9; /* same format but at 11:9 */
2927 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2928 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2929 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2930 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2932 switch (intel_trans_dp_port_sel(crtc)) {
2934 temp |= TRANS_DP_PORT_SEL_B;
2937 temp |= TRANS_DP_PORT_SEL_C;
2940 temp |= TRANS_DP_PORT_SEL_D;
2943 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2944 temp |= TRANS_DP_PORT_SEL_B;
2948 I915_WRITE(reg, temp);
2951 intel_enable_transcoder(dev_priv, pipe);
2954 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2956 struct drm_device *dev = crtc->dev;
2957 struct drm_i915_private *dev_priv = dev->dev_private;
2958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2959 int pipe = intel_crtc->pipe;
2960 int plane = intel_crtc->plane;
2964 if (intel_crtc->active)
2967 intel_crtc->active = true;
2968 intel_update_watermarks(dev);
2970 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2971 temp = I915_READ(PCH_LVDS);
2972 if ((temp & LVDS_PORT_EN) == 0)
2973 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2976 is_pch_port = intel_crtc_driving_pch(crtc);
2979 ironlake_fdi_pll_enable(crtc);
2981 ironlake_fdi_disable(crtc);
2983 /* Enable panel fitting for LVDS */
2984 if (dev_priv->pch_pf_size &&
2985 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2986 /* Force use of hard-coded filter coefficients
2987 * as some pre-programmed values are broken,
2990 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2991 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2992 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2996 * On ILK+ LUT must be loaded before the pipe is running but with
2999 intel_crtc_load_lut(crtc);
3001 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3002 intel_enable_plane(dev_priv, plane, pipe);
3005 ironlake_pch_enable(crtc);
3007 mutex_lock(&dev->struct_mutex);
3008 intel_update_fbc(dev);
3009 mutex_unlock(&dev->struct_mutex);
3011 intel_crtc_update_cursor(crtc, true);
3014 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3016 struct drm_device *dev = crtc->dev;
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019 int pipe = intel_crtc->pipe;
3020 int plane = intel_crtc->plane;
3023 if (!intel_crtc->active)
3026 intel_crtc_wait_for_pending_flips(crtc);
3027 drm_vblank_off(dev, pipe);
3028 intel_crtc_update_cursor(crtc, false);
3030 intel_disable_plane(dev_priv, plane, pipe);
3032 if (dev_priv->cfb_plane == plane)
3033 intel_disable_fbc(dev);
3035 intel_disable_pipe(dev_priv, pipe);
3038 I915_WRITE(PF_CTL(pipe), 0);
3039 I915_WRITE(PF_WIN_SZ(pipe), 0);
3041 ironlake_fdi_disable(crtc);
3043 /* This is a horrible layering violation; we should be doing this in
3044 * the connector/encoder ->prepare instead, but we don't always have
3045 * enough information there about the config to know whether it will
3046 * actually be necessary or just cause undesired flicker.
3048 intel_disable_pch_ports(dev_priv, pipe);
3050 intel_disable_transcoder(dev_priv, pipe);
3052 if (HAS_PCH_CPT(dev)) {
3053 /* disable TRANS_DP_CTL */
3054 reg = TRANS_DP_CTL(pipe);
3055 temp = I915_READ(reg);
3056 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3057 temp |= TRANS_DP_PORT_SEL_NONE;
3058 I915_WRITE(reg, temp);
3060 /* disable DPLL_SEL */
3061 temp = I915_READ(PCH_DPLL_SEL);
3064 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3067 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3070 /* FIXME: manage transcoder PLLs? */
3071 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3076 I915_WRITE(PCH_DPLL_SEL, temp);
3079 /* disable PCH DPLL */
3080 intel_disable_pch_pll(dev_priv, pipe);
3082 /* Switch from PCDclk to Rawclk */
3083 reg = FDI_RX_CTL(pipe);
3084 temp = I915_READ(reg);
3085 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3087 /* Disable CPU FDI TX PLL */
3088 reg = FDI_TX_CTL(pipe);
3089 temp = I915_READ(reg);
3090 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3095 reg = FDI_RX_CTL(pipe);
3096 temp = I915_READ(reg);
3097 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3099 /* Wait for the clocks to turn off. */
3103 intel_crtc->active = false;
3104 intel_update_watermarks(dev);
3106 mutex_lock(&dev->struct_mutex);
3107 intel_update_fbc(dev);
3108 intel_clear_scanline_wait(dev);
3109 mutex_unlock(&dev->struct_mutex);
3112 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3115 int pipe = intel_crtc->pipe;
3116 int plane = intel_crtc->plane;
3118 /* XXX: When our outputs are all unaware of DPMS modes other than off
3119 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3122 case DRM_MODE_DPMS_ON:
3123 case DRM_MODE_DPMS_STANDBY:
3124 case DRM_MODE_DPMS_SUSPEND:
3125 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3126 ironlake_crtc_enable(crtc);
3129 case DRM_MODE_DPMS_OFF:
3130 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3131 ironlake_crtc_disable(crtc);
3136 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3138 if (!enable && intel_crtc->overlay) {
3139 struct drm_device *dev = intel_crtc->base.dev;
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3142 mutex_lock(&dev->struct_mutex);
3143 dev_priv->mm.interruptible = false;
3144 (void) intel_overlay_switch_off(intel_crtc->overlay);
3145 dev_priv->mm.interruptible = true;
3146 mutex_unlock(&dev->struct_mutex);
3149 /* Let userspace switch the overlay on again. In most cases userspace
3150 * has to recompute where to put it anyway.
3154 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3156 struct drm_device *dev = crtc->dev;
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159 int pipe = intel_crtc->pipe;
3160 int plane = intel_crtc->plane;
3162 if (intel_crtc->active)
3165 intel_crtc->active = true;
3166 intel_update_watermarks(dev);
3168 intel_enable_pll(dev_priv, pipe);
3169 intel_enable_pipe(dev_priv, pipe, false);
3170 intel_enable_plane(dev_priv, plane, pipe);
3172 intel_crtc_load_lut(crtc);
3173 intel_update_fbc(dev);
3175 /* Give the overlay scaler a chance to enable if it's on this pipe */
3176 intel_crtc_dpms_overlay(intel_crtc, true);
3177 intel_crtc_update_cursor(crtc, true);
3180 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3182 struct drm_device *dev = crtc->dev;
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3185 int pipe = intel_crtc->pipe;
3186 int plane = intel_crtc->plane;
3188 if (!intel_crtc->active)
3191 /* Give the overlay scaler a chance to disable if it's on this pipe */
3192 intel_crtc_wait_for_pending_flips(crtc);
3193 drm_vblank_off(dev, pipe);
3194 intel_crtc_dpms_overlay(intel_crtc, false);
3195 intel_crtc_update_cursor(crtc, false);
3197 if (dev_priv->cfb_plane == plane)
3198 intel_disable_fbc(dev);
3200 intel_disable_plane(dev_priv, plane, pipe);
3201 intel_disable_pipe(dev_priv, pipe);
3202 intel_disable_pll(dev_priv, pipe);
3204 intel_crtc->active = false;
3205 intel_update_fbc(dev);
3206 intel_update_watermarks(dev);
3207 intel_clear_scanline_wait(dev);
3210 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3212 /* XXX: When our outputs are all unaware of DPMS modes other than off
3213 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3216 case DRM_MODE_DPMS_ON:
3217 case DRM_MODE_DPMS_STANDBY:
3218 case DRM_MODE_DPMS_SUSPEND:
3219 i9xx_crtc_enable(crtc);
3221 case DRM_MODE_DPMS_OFF:
3222 i9xx_crtc_disable(crtc);
3228 * Sets the power management mode of the pipe and plane.
3230 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3232 struct drm_device *dev = crtc->dev;
3233 struct drm_i915_private *dev_priv = dev->dev_private;
3234 struct drm_i915_master_private *master_priv;
3235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3236 int pipe = intel_crtc->pipe;
3239 if (intel_crtc->dpms_mode == mode)
3242 intel_crtc->dpms_mode = mode;
3244 dev_priv->display.dpms(crtc, mode);
3246 if (!dev->primary->master)
3249 master_priv = dev->primary->master->driver_priv;
3250 if (!master_priv->sarea_priv)
3253 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3257 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3258 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3261 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3262 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3265 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3270 static void intel_crtc_disable(struct drm_crtc *crtc)
3272 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3273 struct drm_device *dev = crtc->dev;
3275 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3278 mutex_lock(&dev->struct_mutex);
3279 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3280 mutex_unlock(&dev->struct_mutex);
3284 /* Prepare for a mode set.
3286 * Note we could be a lot smarter here. We need to figure out which outputs
3287 * will be enabled, which disabled (in short, how the config will changes)
3288 * and perform the minimum necessary steps to accomplish that, e.g. updating
3289 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3290 * panel fitting is in the proper state, etc.
3292 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3294 i9xx_crtc_disable(crtc);
3297 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3299 i9xx_crtc_enable(crtc);
3302 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3304 ironlake_crtc_disable(crtc);
3307 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3309 ironlake_crtc_enable(crtc);
3312 void intel_encoder_prepare(struct drm_encoder *encoder)
3314 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3315 /* lvds has its own version of prepare see intel_lvds_prepare */
3316 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3319 void intel_encoder_commit(struct drm_encoder *encoder)
3321 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3322 /* lvds has its own version of commit see intel_lvds_commit */
3323 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3326 void intel_encoder_destroy(struct drm_encoder *encoder)
3328 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3330 drm_encoder_cleanup(encoder);
3331 kfree(intel_encoder);
3334 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3335 struct drm_display_mode *mode,
3336 struct drm_display_mode *adjusted_mode)
3338 struct drm_device *dev = crtc->dev;
3340 if (HAS_PCH_SPLIT(dev)) {
3341 /* FDI link clock is fixed at 2.7G */
3342 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3346 /* XXX some encoders set the crtcinfo, others don't.
3347 * Obviously we need some form of conflict resolution here...
3349 if (adjusted_mode->crtc_htotal == 0)
3350 drm_mode_set_crtcinfo(adjusted_mode, 0);
3355 static int i945_get_display_clock_speed(struct drm_device *dev)
3360 static int i915_get_display_clock_speed(struct drm_device *dev)
3365 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3370 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3374 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3376 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3379 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3380 case GC_DISPLAY_CLOCK_333_MHZ:
3383 case GC_DISPLAY_CLOCK_190_200_MHZ:
3389 static int i865_get_display_clock_speed(struct drm_device *dev)
3394 static int i855_get_display_clock_speed(struct drm_device *dev)
3397 /* Assume that the hardware is in the high speed state. This
3398 * should be the default.
3400 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3401 case GC_CLOCK_133_200:
3402 case GC_CLOCK_100_200:
3404 case GC_CLOCK_166_250:
3406 case GC_CLOCK_100_133:
3410 /* Shouldn't happen */
3414 static int i830_get_display_clock_speed(struct drm_device *dev)
3428 fdi_reduce_ratio(u32 *num, u32 *den)
3430 while (*num > 0xffffff || *den > 0xffffff) {
3437 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3438 int link_clock, struct fdi_m_n *m_n)
3440 m_n->tu = 64; /* default size */
3442 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3443 m_n->gmch_m = bits_per_pixel * pixel_clock;
3444 m_n->gmch_n = link_clock * nlanes * 8;
3445 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3447 m_n->link_m = pixel_clock;
3448 m_n->link_n = link_clock;
3449 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3453 struct intel_watermark_params {
3454 unsigned long fifo_size;
3455 unsigned long max_wm;
3456 unsigned long default_wm;
3457 unsigned long guard_size;
3458 unsigned long cacheline_size;
3461 /* Pineview has different values for various configs */
3462 static const struct intel_watermark_params pineview_display_wm = {
3463 PINEVIEW_DISPLAY_FIFO,
3467 PINEVIEW_FIFO_LINE_SIZE
3469 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3470 PINEVIEW_DISPLAY_FIFO,
3472 PINEVIEW_DFT_HPLLOFF_WM,
3474 PINEVIEW_FIFO_LINE_SIZE
3476 static const struct intel_watermark_params pineview_cursor_wm = {
3477 PINEVIEW_CURSOR_FIFO,
3478 PINEVIEW_CURSOR_MAX_WM,
3479 PINEVIEW_CURSOR_DFT_WM,
3480 PINEVIEW_CURSOR_GUARD_WM,
3481 PINEVIEW_FIFO_LINE_SIZE,
3483 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3484 PINEVIEW_CURSOR_FIFO,
3485 PINEVIEW_CURSOR_MAX_WM,
3486 PINEVIEW_CURSOR_DFT_WM,
3487 PINEVIEW_CURSOR_GUARD_WM,
3488 PINEVIEW_FIFO_LINE_SIZE
3490 static const struct intel_watermark_params g4x_wm_info = {
3497 static const struct intel_watermark_params g4x_cursor_wm_info = {
3504 static const struct intel_watermark_params i965_cursor_wm_info = {
3509 I915_FIFO_LINE_SIZE,
3511 static const struct intel_watermark_params i945_wm_info = {
3518 static const struct intel_watermark_params i915_wm_info = {
3525 static const struct intel_watermark_params i855_wm_info = {
3532 static const struct intel_watermark_params i830_wm_info = {
3540 static const struct intel_watermark_params ironlake_display_wm_info = {
3547 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3554 static const struct intel_watermark_params ironlake_display_srwm_info = {
3555 ILK_DISPLAY_SR_FIFO,
3556 ILK_DISPLAY_MAX_SRWM,
3557 ILK_DISPLAY_DFT_SRWM,
3561 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3563 ILK_CURSOR_MAX_SRWM,
3564 ILK_CURSOR_DFT_SRWM,
3569 static const struct intel_watermark_params sandybridge_display_wm_info = {
3576 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3583 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3584 SNB_DISPLAY_SR_FIFO,
3585 SNB_DISPLAY_MAX_SRWM,
3586 SNB_DISPLAY_DFT_SRWM,
3590 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3592 SNB_CURSOR_MAX_SRWM,
3593 SNB_CURSOR_DFT_SRWM,
3600 * intel_calculate_wm - calculate watermark level
3601 * @clock_in_khz: pixel clock
3602 * @wm: chip FIFO params
3603 * @pixel_size: display pixel size
3604 * @latency_ns: memory latency for the platform
3606 * Calculate the watermark level (the level at which the display plane will
3607 * start fetching from memory again). Each chip has a different display
3608 * FIFO size and allocation, so the caller needs to figure that out and pass
3609 * in the correct intel_watermark_params structure.
3611 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3612 * on the pixel size. When it reaches the watermark level, it'll start
3613 * fetching FIFO line sized based chunks from memory until the FIFO fills
3614 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3615 * will occur, and a display engine hang could result.
3617 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3618 const struct intel_watermark_params *wm,
3621 unsigned long latency_ns)
3623 long entries_required, wm_size;
3626 * Note: we need to make sure we don't overflow for various clock &
3628 * clocks go from a few thousand to several hundred thousand.
3629 * latency is usually a few thousand
3631 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3633 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3635 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3637 wm_size = fifo_size - (entries_required + wm->guard_size);
3639 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3641 /* Don't promote wm_size to unsigned... */
3642 if (wm_size > (long)wm->max_wm)
3643 wm_size = wm->max_wm;
3645 wm_size = wm->default_wm;
3649 struct cxsr_latency {
3652 unsigned long fsb_freq;
3653 unsigned long mem_freq;
3654 unsigned long display_sr;
3655 unsigned long display_hpll_disable;
3656 unsigned long cursor_sr;
3657 unsigned long cursor_hpll_disable;
3660 static const struct cxsr_latency cxsr_latency_table[] = {
3661 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3662 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3663 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3664 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3665 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3667 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3668 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3669 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3670 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3671 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3673 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3674 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3675 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3676 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3677 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3679 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3680 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3681 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3682 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3683 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3685 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3686 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3687 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3688 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3689 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3691 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3692 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3693 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3694 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3695 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3698 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3703 const struct cxsr_latency *latency;
3706 if (fsb == 0 || mem == 0)
3709 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3710 latency = &cxsr_latency_table[i];
3711 if (is_desktop == latency->is_desktop &&
3712 is_ddr3 == latency->is_ddr3 &&
3713 fsb == latency->fsb_freq && mem == latency->mem_freq)
3717 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3722 static void pineview_disable_cxsr(struct drm_device *dev)
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3726 /* deactivate cxsr */
3727 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3731 * Latency for FIFO fetches is dependent on several factors:
3732 * - memory configuration (speed, channels)
3734 * - current MCH state
3735 * It can be fairly high in some situations, so here we assume a fairly
3736 * pessimal value. It's a tradeoff between extra memory fetches (if we
3737 * set this value too high, the FIFO will fetch frequently to stay full)
3738 * and power consumption (set it too low to save power and we might see
3739 * FIFO underruns and display "flicker").
3741 * A value of 5us seems to be a good balance; safe for very low end
3742 * platforms but not overly aggressive on lower latency configs.
3744 static const int latency_ns = 5000;
3746 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 uint32_t dsparb = I915_READ(DSPARB);
3752 size = dsparb & 0x7f;
3754 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3756 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3757 plane ? "B" : "A", size);
3762 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 uint32_t dsparb = I915_READ(DSPARB);
3768 size = dsparb & 0x1ff;
3770 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3771 size >>= 1; /* Convert to cachelines */
3773 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3774 plane ? "B" : "A", size);
3779 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 uint32_t dsparb = I915_READ(DSPARB);
3785 size = dsparb & 0x7f;
3786 size >>= 2; /* Convert to cachelines */
3788 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3795 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 uint32_t dsparb = I915_READ(DSPARB);
3801 size = dsparb & 0x7f;
3802 size >>= 1; /* Convert to cachelines */
3804 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3805 plane ? "B" : "A", size);
3810 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3812 struct drm_crtc *crtc, *enabled = NULL;
3814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3815 if (crtc->enabled && crtc->fb) {
3825 static void pineview_update_wm(struct drm_device *dev)
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct drm_crtc *crtc;
3829 const struct cxsr_latency *latency;
3833 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3834 dev_priv->fsb_freq, dev_priv->mem_freq);
3836 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3837 pineview_disable_cxsr(dev);
3841 crtc = single_enabled_crtc(dev);
3843 int clock = crtc->mode.clock;
3844 int pixel_size = crtc->fb->bits_per_pixel / 8;
3847 wm = intel_calculate_wm(clock, &pineview_display_wm,
3848 pineview_display_wm.fifo_size,
3849 pixel_size, latency->display_sr);
3850 reg = I915_READ(DSPFW1);
3851 reg &= ~DSPFW_SR_MASK;
3852 reg |= wm << DSPFW_SR_SHIFT;
3853 I915_WRITE(DSPFW1, reg);
3854 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3857 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3858 pineview_display_wm.fifo_size,
3859 pixel_size, latency->cursor_sr);
3860 reg = I915_READ(DSPFW3);
3861 reg &= ~DSPFW_CURSOR_SR_MASK;
3862 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3863 I915_WRITE(DSPFW3, reg);
3865 /* Display HPLL off SR */
3866 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3867 pineview_display_hplloff_wm.fifo_size,
3868 pixel_size, latency->display_hpll_disable);
3869 reg = I915_READ(DSPFW3);
3870 reg &= ~DSPFW_HPLL_SR_MASK;
3871 reg |= wm & DSPFW_HPLL_SR_MASK;
3872 I915_WRITE(DSPFW3, reg);
3874 /* cursor HPLL off SR */
3875 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3876 pineview_display_hplloff_wm.fifo_size,
3877 pixel_size, latency->cursor_hpll_disable);
3878 reg = I915_READ(DSPFW3);
3879 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3880 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3881 I915_WRITE(DSPFW3, reg);
3882 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3886 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3887 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3889 pineview_disable_cxsr(dev);
3890 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3894 static bool g4x_compute_wm0(struct drm_device *dev,
3896 const struct intel_watermark_params *display,
3897 int display_latency_ns,
3898 const struct intel_watermark_params *cursor,
3899 int cursor_latency_ns,
3903 struct drm_crtc *crtc;
3904 int htotal, hdisplay, clock, pixel_size;
3905 int line_time_us, line_count;
3906 int entries, tlb_miss;
3908 crtc = intel_get_crtc_for_plane(dev, plane);
3909 if (crtc->fb == NULL || !crtc->enabled) {
3910 *cursor_wm = cursor->guard_size;
3911 *plane_wm = display->guard_size;
3915 htotal = crtc->mode.htotal;
3916 hdisplay = crtc->mode.hdisplay;
3917 clock = crtc->mode.clock;
3918 pixel_size = crtc->fb->bits_per_pixel / 8;
3920 /* Use the small buffer method to calculate plane watermark */
3921 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3922 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3924 entries += tlb_miss;
3925 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3926 *plane_wm = entries + display->guard_size;
3927 if (*plane_wm > (int)display->max_wm)
3928 *plane_wm = display->max_wm;
3930 /* Use the large buffer method to calculate cursor watermark */
3931 line_time_us = ((htotal * 1000) / clock);
3932 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3933 entries = line_count * 64 * pixel_size;
3934 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3936 entries += tlb_miss;
3937 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3938 *cursor_wm = entries + cursor->guard_size;
3939 if (*cursor_wm > (int)cursor->max_wm)
3940 *cursor_wm = (int)cursor->max_wm;
3946 * Check the wm result.
3948 * If any calculated watermark values is larger than the maximum value that
3949 * can be programmed into the associated watermark register, that watermark
3952 static bool g4x_check_srwm(struct drm_device *dev,
3953 int display_wm, int cursor_wm,
3954 const struct intel_watermark_params *display,
3955 const struct intel_watermark_params *cursor)
3957 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3958 display_wm, cursor_wm);
3960 if (display_wm > display->max_wm) {
3961 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3962 display_wm, display->max_wm);
3966 if (cursor_wm > cursor->max_wm) {
3967 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3968 cursor_wm, cursor->max_wm);
3972 if (!(display_wm || cursor_wm)) {
3973 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3980 static bool g4x_compute_srwm(struct drm_device *dev,
3983 const struct intel_watermark_params *display,
3984 const struct intel_watermark_params *cursor,
3985 int *display_wm, int *cursor_wm)
3987 struct drm_crtc *crtc;
3988 int hdisplay, htotal, pixel_size, clock;
3989 unsigned long line_time_us;
3990 int line_count, line_size;
3995 *display_wm = *cursor_wm = 0;
3999 crtc = intel_get_crtc_for_plane(dev, plane);
4000 hdisplay = crtc->mode.hdisplay;
4001 htotal = crtc->mode.htotal;
4002 clock = crtc->mode.clock;
4003 pixel_size = crtc->fb->bits_per_pixel / 8;
4005 line_time_us = (htotal * 1000) / clock;
4006 line_count = (latency_ns / line_time_us + 1000) / 1000;
4007 line_size = hdisplay * pixel_size;
4009 /* Use the minimum of the small and large buffer method for primary */
4010 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4011 large = line_count * line_size;
4013 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4014 *display_wm = entries + display->guard_size;
4016 /* calculate the self-refresh watermark for display cursor */
4017 entries = line_count * pixel_size * 64;
4018 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4019 *cursor_wm = entries + cursor->guard_size;
4021 return g4x_check_srwm(dev,
4022 *display_wm, *cursor_wm,
4026 #define single_plane_enabled(mask) is_power_of_2(mask)
4028 static void g4x_update_wm(struct drm_device *dev)
4030 static const int sr_latency_ns = 12000;
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4033 int plane_sr, cursor_sr;
4034 unsigned int enabled = 0;
4036 if (g4x_compute_wm0(dev, 0,
4037 &g4x_wm_info, latency_ns,
4038 &g4x_cursor_wm_info, latency_ns,
4039 &planea_wm, &cursora_wm))
4042 if (g4x_compute_wm0(dev, 1,
4043 &g4x_wm_info, latency_ns,
4044 &g4x_cursor_wm_info, latency_ns,
4045 &planeb_wm, &cursorb_wm))
4048 plane_sr = cursor_sr = 0;
4049 if (single_plane_enabled(enabled) &&
4050 g4x_compute_srwm(dev, ffs(enabled) - 1,
4053 &g4x_cursor_wm_info,
4054 &plane_sr, &cursor_sr))
4055 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4057 I915_WRITE(FW_BLC_SELF,
4058 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4060 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4061 planea_wm, cursora_wm,
4062 planeb_wm, cursorb_wm,
4063 plane_sr, cursor_sr);
4066 (plane_sr << DSPFW_SR_SHIFT) |
4067 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4068 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4071 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4072 (cursora_wm << DSPFW_CURSORA_SHIFT));
4073 /* HPLL off in SR has some issues on G4x... disable it */
4075 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4076 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4079 static void i965_update_wm(struct drm_device *dev)
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 struct drm_crtc *crtc;
4086 /* Calc sr entries for one plane configs */
4087 crtc = single_enabled_crtc(dev);
4089 /* self-refresh has much higher latency */
4090 static const int sr_latency_ns = 12000;
4091 int clock = crtc->mode.clock;
4092 int htotal = crtc->mode.htotal;
4093 int hdisplay = crtc->mode.hdisplay;
4094 int pixel_size = crtc->fb->bits_per_pixel / 8;
4095 unsigned long line_time_us;
4098 line_time_us = ((htotal * 1000) / clock);
4100 /* Use ns/us then divide to preserve precision */
4101 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4102 pixel_size * hdisplay;
4103 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4104 srwm = I965_FIFO_SIZE - entries;
4108 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4111 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4113 entries = DIV_ROUND_UP(entries,
4114 i965_cursor_wm_info.cacheline_size);
4115 cursor_sr = i965_cursor_wm_info.fifo_size -
4116 (entries + i965_cursor_wm_info.guard_size);
4118 if (cursor_sr > i965_cursor_wm_info.max_wm)
4119 cursor_sr = i965_cursor_wm_info.max_wm;
4121 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4122 "cursor %d\n", srwm, cursor_sr);
4124 if (IS_CRESTLINE(dev))
4125 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4127 /* Turn off self refresh if both pipes are enabled */
4128 if (IS_CRESTLINE(dev))
4129 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4133 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4136 /* 965 has limitations... */
4137 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4138 (8 << 16) | (8 << 8) | (8 << 0));
4139 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4140 /* update cursor SR watermark */
4141 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4144 static void i9xx_update_wm(struct drm_device *dev)
4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147 const struct intel_watermark_params *wm_info;
4152 int planea_wm, planeb_wm;
4153 struct drm_crtc *crtc, *enabled = NULL;
4156 wm_info = &i945_wm_info;
4157 else if (!IS_GEN2(dev))
4158 wm_info = &i915_wm_info;
4160 wm_info = &i855_wm_info;
4162 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4163 crtc = intel_get_crtc_for_plane(dev, 0);
4164 if (crtc->enabled && crtc->fb) {
4165 planea_wm = intel_calculate_wm(crtc->mode.clock,
4167 crtc->fb->bits_per_pixel / 8,
4171 planea_wm = fifo_size - wm_info->guard_size;
4173 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4174 crtc = intel_get_crtc_for_plane(dev, 1);
4175 if (crtc->enabled && crtc->fb) {
4176 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4178 crtc->fb->bits_per_pixel / 8,
4180 if (enabled == NULL)
4185 planeb_wm = fifo_size - wm_info->guard_size;
4187 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4190 * Overlay gets an aggressive default since video jitter is bad.
4194 /* Play safe and disable self-refresh before adjusting watermarks. */
4195 if (IS_I945G(dev) || IS_I945GM(dev))
4196 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4197 else if (IS_I915GM(dev))
4198 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4200 /* Calc sr entries for one plane configs */
4201 if (HAS_FW_BLC(dev) && enabled) {
4202 /* self-refresh has much higher latency */
4203 static const int sr_latency_ns = 6000;
4204 int clock = enabled->mode.clock;
4205 int htotal = enabled->mode.htotal;
4206 int hdisplay = enabled->mode.hdisplay;
4207 int pixel_size = enabled->fb->bits_per_pixel / 8;
4208 unsigned long line_time_us;
4211 line_time_us = (htotal * 1000) / clock;
4213 /* Use ns/us then divide to preserve precision */
4214 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4215 pixel_size * hdisplay;
4216 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4217 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4218 srwm = wm_info->fifo_size - entries;
4222 if (IS_I945G(dev) || IS_I945GM(dev))
4223 I915_WRITE(FW_BLC_SELF,
4224 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4225 else if (IS_I915GM(dev))
4226 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4229 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4230 planea_wm, planeb_wm, cwm, srwm);
4232 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4233 fwater_hi = (cwm & 0x1f);
4235 /* Set request length to 8 cachelines per fetch */
4236 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4237 fwater_hi = fwater_hi | (1 << 8);
4239 I915_WRITE(FW_BLC, fwater_lo);
4240 I915_WRITE(FW_BLC2, fwater_hi);
4242 if (HAS_FW_BLC(dev)) {
4244 if (IS_I945G(dev) || IS_I945GM(dev))
4245 I915_WRITE(FW_BLC_SELF,
4246 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4247 else if (IS_I915GM(dev))
4248 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4249 DRM_DEBUG_KMS("memory self refresh enabled\n");
4251 DRM_DEBUG_KMS("memory self refresh disabled\n");
4255 static void i830_update_wm(struct drm_device *dev)
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 struct drm_crtc *crtc;
4262 crtc = single_enabled_crtc(dev);
4266 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4267 dev_priv->display.get_fifo_size(dev, 0),
4268 crtc->fb->bits_per_pixel / 8,
4270 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4271 fwater_lo |= (3<<8) | planea_wm;
4273 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4275 I915_WRITE(FW_BLC, fwater_lo);
4278 #define ILK_LP0_PLANE_LATENCY 700
4279 #define ILK_LP0_CURSOR_LATENCY 1300
4282 * Check the wm result.
4284 * If any calculated watermark values is larger than the maximum value that
4285 * can be programmed into the associated watermark register, that watermark
4288 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4289 int fbc_wm, int display_wm, int cursor_wm,
4290 const struct intel_watermark_params *display,
4291 const struct intel_watermark_params *cursor)
4293 struct drm_i915_private *dev_priv = dev->dev_private;
4295 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4296 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4298 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4299 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4300 fbc_wm, SNB_FBC_MAX_SRWM, level);
4302 /* fbc has it's own way to disable FBC WM */
4303 I915_WRITE(DISP_ARB_CTL,
4304 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4308 if (display_wm > display->max_wm) {
4309 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4310 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4314 if (cursor_wm > cursor->max_wm) {
4315 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4316 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4320 if (!(fbc_wm || display_wm || cursor_wm)) {
4321 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4329 * Compute watermark values of WM[1-3],
4331 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4333 const struct intel_watermark_params *display,
4334 const struct intel_watermark_params *cursor,
4335 int *fbc_wm, int *display_wm, int *cursor_wm)
4337 struct drm_crtc *crtc;
4338 unsigned long line_time_us;
4339 int hdisplay, htotal, pixel_size, clock;
4340 int line_count, line_size;
4345 *fbc_wm = *display_wm = *cursor_wm = 0;
4349 crtc = intel_get_crtc_for_plane(dev, plane);
4350 hdisplay = crtc->mode.hdisplay;
4351 htotal = crtc->mode.htotal;
4352 clock = crtc->mode.clock;
4353 pixel_size = crtc->fb->bits_per_pixel / 8;
4355 line_time_us = (htotal * 1000) / clock;
4356 line_count = (latency_ns / line_time_us + 1000) / 1000;
4357 line_size = hdisplay * pixel_size;
4359 /* Use the minimum of the small and large buffer method for primary */
4360 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4361 large = line_count * line_size;
4363 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4364 *display_wm = entries + display->guard_size;
4368 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4370 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4372 /* calculate the self-refresh watermark for display cursor */
4373 entries = line_count * pixel_size * 64;
4374 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4375 *cursor_wm = entries + cursor->guard_size;
4377 return ironlake_check_srwm(dev, level,
4378 *fbc_wm, *display_wm, *cursor_wm,
4382 static void ironlake_update_wm(struct drm_device *dev)
4384 struct drm_i915_private *dev_priv = dev->dev_private;
4385 int fbc_wm, plane_wm, cursor_wm;
4386 unsigned int enabled;
4389 if (g4x_compute_wm0(dev, 0,
4390 &ironlake_display_wm_info,
4391 ILK_LP0_PLANE_LATENCY,
4392 &ironlake_cursor_wm_info,
4393 ILK_LP0_CURSOR_LATENCY,
4394 &plane_wm, &cursor_wm)) {
4395 I915_WRITE(WM0_PIPEA_ILK,
4396 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4397 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4398 " plane %d, " "cursor: %d\n",
4399 plane_wm, cursor_wm);
4403 if (g4x_compute_wm0(dev, 1,
4404 &ironlake_display_wm_info,
4405 ILK_LP0_PLANE_LATENCY,
4406 &ironlake_cursor_wm_info,
4407 ILK_LP0_CURSOR_LATENCY,
4408 &plane_wm, &cursor_wm)) {
4409 I915_WRITE(WM0_PIPEB_ILK,
4410 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4411 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4412 " plane %d, cursor: %d\n",
4413 plane_wm, cursor_wm);
4418 * Calculate and update the self-refresh watermark only when one
4419 * display plane is used.
4421 I915_WRITE(WM3_LP_ILK, 0);
4422 I915_WRITE(WM2_LP_ILK, 0);
4423 I915_WRITE(WM1_LP_ILK, 0);
4425 if (!single_plane_enabled(enabled))
4427 enabled = ffs(enabled) - 1;
4430 if (!ironlake_compute_srwm(dev, 1, enabled,
4431 ILK_READ_WM1_LATENCY() * 500,
4432 &ironlake_display_srwm_info,
4433 &ironlake_cursor_srwm_info,
4434 &fbc_wm, &plane_wm, &cursor_wm))
4437 I915_WRITE(WM1_LP_ILK,
4439 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4440 (fbc_wm << WM1_LP_FBC_SHIFT) |
4441 (plane_wm << WM1_LP_SR_SHIFT) |
4445 if (!ironlake_compute_srwm(dev, 2, enabled,
4446 ILK_READ_WM2_LATENCY() * 500,
4447 &ironlake_display_srwm_info,
4448 &ironlake_cursor_srwm_info,
4449 &fbc_wm, &plane_wm, &cursor_wm))
4452 I915_WRITE(WM2_LP_ILK,
4454 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4455 (fbc_wm << WM1_LP_FBC_SHIFT) |
4456 (plane_wm << WM1_LP_SR_SHIFT) |
4460 * WM3 is unsupported on ILK, probably because we don't have latency
4461 * data for that power state
4465 static void sandybridge_update_wm(struct drm_device *dev)
4467 struct drm_i915_private *dev_priv = dev->dev_private;
4468 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4469 int fbc_wm, plane_wm, cursor_wm;
4470 unsigned int enabled;
4473 if (g4x_compute_wm0(dev, 0,
4474 &sandybridge_display_wm_info, latency,
4475 &sandybridge_cursor_wm_info, latency,
4476 &plane_wm, &cursor_wm)) {
4477 I915_WRITE(WM0_PIPEA_ILK,
4478 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4479 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4480 " plane %d, " "cursor: %d\n",
4481 plane_wm, cursor_wm);
4485 if (g4x_compute_wm0(dev, 1,
4486 &sandybridge_display_wm_info, latency,
4487 &sandybridge_cursor_wm_info, latency,
4488 &plane_wm, &cursor_wm)) {
4489 I915_WRITE(WM0_PIPEB_ILK,
4490 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4491 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4492 " plane %d, cursor: %d\n",
4493 plane_wm, cursor_wm);
4498 * Calculate and update the self-refresh watermark only when one
4499 * display plane is used.
4501 * SNB support 3 levels of watermark.
4503 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4504 * and disabled in the descending order
4507 I915_WRITE(WM3_LP_ILK, 0);
4508 I915_WRITE(WM2_LP_ILK, 0);
4509 I915_WRITE(WM1_LP_ILK, 0);
4511 if (!single_plane_enabled(enabled))
4513 enabled = ffs(enabled) - 1;
4516 if (!ironlake_compute_srwm(dev, 1, enabled,
4517 SNB_READ_WM1_LATENCY() * 500,
4518 &sandybridge_display_srwm_info,
4519 &sandybridge_cursor_srwm_info,
4520 &fbc_wm, &plane_wm, &cursor_wm))
4523 I915_WRITE(WM1_LP_ILK,
4525 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4526 (fbc_wm << WM1_LP_FBC_SHIFT) |
4527 (plane_wm << WM1_LP_SR_SHIFT) |
4531 if (!ironlake_compute_srwm(dev, 2, enabled,
4532 SNB_READ_WM2_LATENCY() * 500,
4533 &sandybridge_display_srwm_info,
4534 &sandybridge_cursor_srwm_info,
4535 &fbc_wm, &plane_wm, &cursor_wm))
4538 I915_WRITE(WM2_LP_ILK,
4540 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4541 (fbc_wm << WM1_LP_FBC_SHIFT) |
4542 (plane_wm << WM1_LP_SR_SHIFT) |
4546 if (!ironlake_compute_srwm(dev, 3, enabled,
4547 SNB_READ_WM3_LATENCY() * 500,
4548 &sandybridge_display_srwm_info,
4549 &sandybridge_cursor_srwm_info,
4550 &fbc_wm, &plane_wm, &cursor_wm))
4553 I915_WRITE(WM3_LP_ILK,
4555 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4556 (fbc_wm << WM1_LP_FBC_SHIFT) |
4557 (plane_wm << WM1_LP_SR_SHIFT) |
4562 * intel_update_watermarks - update FIFO watermark values based on current modes
4564 * Calculate watermark values for the various WM regs based on current mode
4565 * and plane configuration.
4567 * There are several cases to deal with here:
4568 * - normal (i.e. non-self-refresh)
4569 * - self-refresh (SR) mode
4570 * - lines are large relative to FIFO size (buffer can hold up to 2)
4571 * - lines are small relative to FIFO size (buffer can hold more than 2
4572 * lines), so need to account for TLB latency
4574 * The normal calculation is:
4575 * watermark = dotclock * bytes per pixel * latency
4576 * where latency is platform & configuration dependent (we assume pessimal
4579 * The SR calculation is:
4580 * watermark = (trunc(latency/line time)+1) * surface width *
4583 * line time = htotal / dotclock
4584 * surface width = hdisplay for normal plane and 64 for cursor
4585 * and latency is assumed to be high, as above.
4587 * The final value programmed to the register should always be rounded up,
4588 * and include an extra 2 entries to account for clock crossings.
4590 * We don't use the sprite, so we can ignore that. And on Crestline we have
4591 * to set the non-SR watermarks to 8.
4593 static void intel_update_watermarks(struct drm_device *dev)
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4597 if (dev_priv->display.update_wm)
4598 dev_priv->display.update_wm(dev);
4601 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4603 if (i915_panel_use_ssc >= 0)
4604 return i915_panel_use_ssc != 0;
4605 return dev_priv->lvds_use_ssc
4606 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4610 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4611 * @crtc: CRTC structure
4613 * A pipe may be connected to one or more outputs. Based on the depth of the
4614 * attached framebuffer, choose a good color depth to use on the pipe.
4616 * If possible, match the pipe depth to the fb depth. In some cases, this
4617 * isn't ideal, because the connected output supports a lesser or restricted
4618 * set of depths. Resolve that here:
4619 * LVDS typically supports only 6bpc, so clamp down in that case
4620 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4621 * Displays may support a restricted set as well, check EDID and clamp as
4625 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4626 * true if they don't match).
4628 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4629 unsigned int *pipe_bpp)
4631 struct drm_device *dev = crtc->dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633 struct drm_encoder *encoder;
4634 struct drm_connector *connector;
4635 unsigned int display_bpc = UINT_MAX, bpc;
4637 /* Walk the encoders & connectors on this crtc, get min bpc */
4638 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4639 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4641 if (encoder->crtc != crtc)
4644 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4645 unsigned int lvds_bpc;
4647 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4653 if (lvds_bpc < display_bpc) {
4654 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4655 display_bpc = lvds_bpc;
4660 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4661 /* Use VBT settings if we have an eDP panel */
4662 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4664 if (edp_bpc < display_bpc) {
4665 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4666 display_bpc = edp_bpc;
4671 /* Not one of the known troublemakers, check the EDID */
4672 list_for_each_entry(connector, &dev->mode_config.connector_list,
4674 if (connector->encoder != encoder)
4677 /* Don't use an invalid EDID bpc value */
4678 if (connector->display_info.bpc &&
4679 connector->display_info.bpc < display_bpc) {
4680 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4681 display_bpc = connector->display_info.bpc;
4686 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4687 * through, clamp it down. (Note: >12bpc will be caught below.)
4689 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4690 if (display_bpc > 8 && display_bpc < 12) {
4691 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4694 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4701 * We could just drive the pipe at the highest bpc all the time and
4702 * enable dithering as needed, but that costs bandwidth. So choose
4703 * the minimum value that expresses the full color range of the fb but
4704 * also stays within the max display bpc discovered above.
4707 switch (crtc->fb->depth) {
4709 bpc = 8; /* since we go through a colormap */
4713 bpc = 6; /* min is 18bpp */
4725 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4726 bpc = min((unsigned int)8, display_bpc);
4730 display_bpc = min(display_bpc, bpc);
4732 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4735 *pipe_bpp = display_bpc * 3;
4737 return display_bpc != bpc;
4740 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4741 struct drm_display_mode *mode,
4742 struct drm_display_mode *adjusted_mode,
4744 struct drm_framebuffer *old_fb)
4746 struct drm_device *dev = crtc->dev;
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4749 int pipe = intel_crtc->pipe;
4750 int plane = intel_crtc->plane;
4751 int refclk, num_connectors = 0;
4752 intel_clock_t clock, reduced_clock;
4753 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4754 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4755 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4756 struct drm_mode_config *mode_config = &dev->mode_config;
4757 struct intel_encoder *encoder;
4758 const intel_limit_t *limit;
4763 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4764 if (encoder->base.crtc != crtc)
4767 switch (encoder->type) {
4768 case INTEL_OUTPUT_LVDS:
4771 case INTEL_OUTPUT_SDVO:
4772 case INTEL_OUTPUT_HDMI:
4774 if (encoder->needs_tv_clock)
4777 case INTEL_OUTPUT_DVO:
4780 case INTEL_OUTPUT_TVOUT:
4783 case INTEL_OUTPUT_ANALOG:
4786 case INTEL_OUTPUT_DISPLAYPORT:
4794 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4795 refclk = dev_priv->lvds_ssc_freq * 1000;
4796 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4798 } else if (!IS_GEN2(dev)) {
4805 * Returns a set of divisors for the desired target clock with the given
4806 * refclk, or FALSE. The returned values represent the clock equation:
4807 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4809 limit = intel_limit(crtc, refclk);
4810 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4812 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4816 /* Ensure that the cursor is valid for the new mode before changing... */
4817 intel_crtc_update_cursor(crtc, true);
4819 if (is_lvds && dev_priv->lvds_downclock_avail) {
4820 has_reduced_clock = limit->find_pll(limit, crtc,
4821 dev_priv->lvds_downclock,
4824 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4826 * If the different P is found, it means that we can't
4827 * switch the display clock by using the FP0/FP1.
4828 * In such case we will disable the LVDS downclock
4831 DRM_DEBUG_KMS("Different P is found for "
4832 "LVDS clock/downclock\n");
4833 has_reduced_clock = 0;
4836 /* SDVO TV has fixed PLL values depend on its clock range,
4837 this mirrors vbios setting. */
4838 if (is_sdvo && is_tv) {
4839 if (adjusted_mode->clock >= 100000
4840 && adjusted_mode->clock < 140500) {
4846 } else if (adjusted_mode->clock >= 140500
4847 && adjusted_mode->clock <= 200000) {
4856 if (IS_PINEVIEW(dev)) {
4857 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4858 if (has_reduced_clock)
4859 fp2 = (1 << reduced_clock.n) << 16 |
4860 reduced_clock.m1 << 8 | reduced_clock.m2;
4862 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4863 if (has_reduced_clock)
4864 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4868 dpll = DPLL_VGA_MODE_DIS;
4870 if (!IS_GEN2(dev)) {
4872 dpll |= DPLLB_MODE_LVDS;
4874 dpll |= DPLLB_MODE_DAC_SERIAL;
4876 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4877 if (pixel_multiplier > 1) {
4878 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4879 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4881 dpll |= DPLL_DVO_HIGH_SPEED;
4884 dpll |= DPLL_DVO_HIGH_SPEED;
4886 /* compute bitmask from p1 value */
4887 if (IS_PINEVIEW(dev))
4888 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4890 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4891 if (IS_G4X(dev) && has_reduced_clock)
4892 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4896 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4899 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4902 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4905 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4908 if (INTEL_INFO(dev)->gen >= 4)
4909 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4912 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4915 dpll |= PLL_P1_DIVIDE_BY_TWO;
4917 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4919 dpll |= PLL_P2_DIVIDE_BY_4;
4923 if (is_sdvo && is_tv)
4924 dpll |= PLL_REF_INPUT_TVCLKINBC;
4926 /* XXX: just matching BIOS for now */
4927 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4929 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4930 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4932 dpll |= PLL_REF_INPUT_DREFCLK;
4934 /* setup pipeconf */
4935 pipeconf = I915_READ(PIPECONF(pipe));
4937 /* Set up the display plane register */
4938 dspcntr = DISPPLANE_GAMMA_ENABLE;
4940 /* Ironlake's plane is forced to pipe, bit 24 is to
4941 enable color space conversion */
4943 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4945 dspcntr |= DISPPLANE_SEL_PIPE_B;
4947 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4948 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4951 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4955 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4956 pipeconf |= PIPECONF_DOUBLE_WIDE;
4958 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4961 dpll |= DPLL_VCO_ENABLE;
4963 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4964 drm_mode_debug_printmodeline(mode);
4966 I915_WRITE(FP0(pipe), fp);
4967 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4969 POSTING_READ(DPLL(pipe));
4972 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4973 * This is an exception to the general rule that mode_set doesn't turn
4977 temp = I915_READ(LVDS);
4978 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4980 temp |= LVDS_PIPEB_SELECT;
4982 temp &= ~LVDS_PIPEB_SELECT;
4984 /* set the corresponsding LVDS_BORDER bit */
4985 temp |= dev_priv->lvds_border_bits;
4986 /* Set the B0-B3 data pairs corresponding to whether we're going to
4987 * set the DPLLs for dual-channel mode or not.
4990 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4992 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4994 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4995 * appropriately here, but we need to look more thoroughly into how
4996 * panels behave in the two modes.
4998 /* set the dithering flag on LVDS as needed */
4999 if (INTEL_INFO(dev)->gen >= 4) {
5000 if (dev_priv->lvds_dither)
5001 temp |= LVDS_ENABLE_DITHER;
5003 temp &= ~LVDS_ENABLE_DITHER;
5005 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5006 lvds_sync |= LVDS_HSYNC_POLARITY;
5007 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5008 lvds_sync |= LVDS_VSYNC_POLARITY;
5009 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5011 char flags[2] = "-+";
5012 DRM_INFO("Changing LVDS panel from "
5013 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5014 flags[!(temp & LVDS_HSYNC_POLARITY)],
5015 flags[!(temp & LVDS_VSYNC_POLARITY)],
5016 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5017 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5018 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5021 I915_WRITE(LVDS, temp);
5025 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5028 I915_WRITE(DPLL(pipe), dpll);
5030 /* Wait for the clocks to stabilize. */
5031 POSTING_READ(DPLL(pipe));
5034 if (INTEL_INFO(dev)->gen >= 4) {
5037 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5039 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5043 I915_WRITE(DPLL_MD(pipe), temp);
5045 /* The pixel multiplier can only be updated once the
5046 * DPLL is enabled and the clocks are stable.
5048 * So write it again.
5050 I915_WRITE(DPLL(pipe), dpll);
5053 intel_crtc->lowfreq_avail = false;
5054 if (is_lvds && has_reduced_clock && i915_powersave) {
5055 I915_WRITE(FP1(pipe), fp2);
5056 intel_crtc->lowfreq_avail = true;
5057 if (HAS_PIPE_CXSR(dev)) {
5058 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5059 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5062 I915_WRITE(FP1(pipe), fp);
5063 if (HAS_PIPE_CXSR(dev)) {
5064 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5065 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5069 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5070 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5071 /* the chip adds 2 halflines automatically */
5072 adjusted_mode->crtc_vdisplay -= 1;
5073 adjusted_mode->crtc_vtotal -= 1;
5074 adjusted_mode->crtc_vblank_start -= 1;
5075 adjusted_mode->crtc_vblank_end -= 1;
5076 adjusted_mode->crtc_vsync_end -= 1;
5077 adjusted_mode->crtc_vsync_start -= 1;
5079 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5081 I915_WRITE(HTOTAL(pipe),
5082 (adjusted_mode->crtc_hdisplay - 1) |
5083 ((adjusted_mode->crtc_htotal - 1) << 16));
5084 I915_WRITE(HBLANK(pipe),
5085 (adjusted_mode->crtc_hblank_start - 1) |
5086 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5087 I915_WRITE(HSYNC(pipe),
5088 (adjusted_mode->crtc_hsync_start - 1) |
5089 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5091 I915_WRITE(VTOTAL(pipe),
5092 (adjusted_mode->crtc_vdisplay - 1) |
5093 ((adjusted_mode->crtc_vtotal - 1) << 16));
5094 I915_WRITE(VBLANK(pipe),
5095 (adjusted_mode->crtc_vblank_start - 1) |
5096 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5097 I915_WRITE(VSYNC(pipe),
5098 (adjusted_mode->crtc_vsync_start - 1) |
5099 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5101 /* pipesrc and dspsize control the size that is scaled from,
5102 * which should always be the user's requested size.
5104 I915_WRITE(DSPSIZE(plane),
5105 ((mode->vdisplay - 1) << 16) |
5106 (mode->hdisplay - 1));
5107 I915_WRITE(DSPPOS(plane), 0);
5108 I915_WRITE(PIPESRC(pipe),
5109 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5111 I915_WRITE(PIPECONF(pipe), pipeconf);
5112 POSTING_READ(PIPECONF(pipe));
5113 intel_enable_pipe(dev_priv, pipe, false);
5115 intel_wait_for_vblank(dev, pipe);
5117 I915_WRITE(DSPCNTR(plane), dspcntr);
5118 POSTING_READ(DSPCNTR(plane));
5119 intel_enable_plane(dev_priv, plane, pipe);
5121 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5123 intel_update_watermarks(dev);
5129 * Initialize reference clocks when the driver loads
5131 void ironlake_init_pch_refclk(struct drm_device *dev)
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 struct drm_mode_config *mode_config = &dev->mode_config;
5135 struct intel_encoder *encoder;
5137 bool has_lvds = false;
5138 bool has_cpu_edp = false;
5139 bool has_pch_edp = false;
5140 bool has_panel = false;
5141 bool has_ck505 = false;
5142 bool can_ssc = false;
5144 /* We need to take the global config into account */
5145 list_for_each_entry(encoder, &mode_config->encoder_list,
5147 switch (encoder->type) {
5148 case INTEL_OUTPUT_LVDS:
5152 case INTEL_OUTPUT_EDP:
5154 if (intel_encoder_is_pch_edp(&encoder->base))
5162 if (HAS_PCH_IBX(dev)) {
5163 has_ck505 = dev_priv->display_clock_mode;
5164 can_ssc = has_ck505;
5170 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5171 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5174 /* Ironlake: try to setup display ref clock before DPLL
5175 * enabling. This is only under driver's control after
5176 * PCH B stepping, previous chipset stepping should be
5177 * ignoring this setting.
5179 temp = I915_READ(PCH_DREF_CONTROL);
5180 /* Always enable nonspread source */
5181 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5184 temp |= DREF_NONSPREAD_CK505_ENABLE;
5186 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5189 temp &= ~DREF_SSC_SOURCE_MASK;
5190 temp |= DREF_SSC_SOURCE_ENABLE;
5192 /* SSC must be turned on before enabling the CPU output */
5193 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5194 DRM_DEBUG_KMS("Using SSC on panel\n");
5195 temp |= DREF_SSC1_ENABLE;
5198 /* Get SSC going before enabling the outputs */
5199 I915_WRITE(PCH_DREF_CONTROL, temp);
5200 POSTING_READ(PCH_DREF_CONTROL);
5203 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5205 /* Enable CPU source on CPU attached eDP */
5207 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5208 DRM_DEBUG_KMS("Using SSC on eDP\n");
5209 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5212 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5214 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5216 I915_WRITE(PCH_DREF_CONTROL, temp);
5217 POSTING_READ(PCH_DREF_CONTROL);
5220 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5222 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5224 /* Turn off CPU output */
5225 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5227 I915_WRITE(PCH_DREF_CONTROL, temp);
5228 POSTING_READ(PCH_DREF_CONTROL);
5231 /* Turn off the SSC source */
5232 temp &= ~DREF_SSC_SOURCE_MASK;
5233 temp |= DREF_SSC_SOURCE_DISABLE;
5236 temp &= ~ DREF_SSC1_ENABLE;
5238 I915_WRITE(PCH_DREF_CONTROL, temp);
5239 POSTING_READ(PCH_DREF_CONTROL);
5244 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5245 struct drm_display_mode *mode,
5246 struct drm_display_mode *adjusted_mode,
5248 struct drm_framebuffer *old_fb)
5250 struct drm_device *dev = crtc->dev;
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5253 int pipe = intel_crtc->pipe;
5254 int plane = intel_crtc->plane;
5255 int refclk, num_connectors = 0;
5256 intel_clock_t clock, reduced_clock;
5257 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5258 bool ok, has_reduced_clock = false, is_sdvo = false;
5259 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5260 struct intel_encoder *has_edp_encoder = NULL;
5261 struct drm_mode_config *mode_config = &dev->mode_config;
5262 struct intel_encoder *encoder;
5263 const intel_limit_t *limit;
5265 struct fdi_m_n m_n = {0};
5268 int target_clock, pixel_multiplier, lane, link_bw, factor;
5269 unsigned int pipe_bpp;
5272 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5273 if (encoder->base.crtc != crtc)
5276 switch (encoder->type) {
5277 case INTEL_OUTPUT_LVDS:
5280 case INTEL_OUTPUT_SDVO:
5281 case INTEL_OUTPUT_HDMI:
5283 if (encoder->needs_tv_clock)
5286 case INTEL_OUTPUT_TVOUT:
5289 case INTEL_OUTPUT_ANALOG:
5292 case INTEL_OUTPUT_DISPLAYPORT:
5295 case INTEL_OUTPUT_EDP:
5296 has_edp_encoder = encoder;
5304 * Every reference clock in a PCH system is 120MHz
5309 * Returns a set of divisors for the desired target clock with the given
5310 * refclk, or FALSE. The returned values represent the clock equation:
5311 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5313 limit = intel_limit(crtc, refclk);
5314 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5316 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5320 /* Ensure that the cursor is valid for the new mode before changing... */
5321 intel_crtc_update_cursor(crtc, true);
5323 if (is_lvds && dev_priv->lvds_downclock_avail) {
5324 has_reduced_clock = limit->find_pll(limit, crtc,
5325 dev_priv->lvds_downclock,
5328 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5330 * If the different P is found, it means that we can't
5331 * switch the display clock by using the FP0/FP1.
5332 * In such case we will disable the LVDS downclock
5335 DRM_DEBUG_KMS("Different P is found for "
5336 "LVDS clock/downclock\n");
5337 has_reduced_clock = 0;
5340 /* SDVO TV has fixed PLL values depend on its clock range,
5341 this mirrors vbios setting. */
5342 if (is_sdvo && is_tv) {
5343 if (adjusted_mode->clock >= 100000
5344 && adjusted_mode->clock < 140500) {
5350 } else if (adjusted_mode->clock >= 140500
5351 && adjusted_mode->clock <= 200000) {
5361 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5363 /* CPU eDP doesn't require FDI link, so just set DP M/N
5364 according to current link config */
5365 if (has_edp_encoder &&
5366 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5367 target_clock = mode->clock;
5368 intel_edp_link_config(has_edp_encoder,
5371 /* [e]DP over FDI requires target mode clock
5372 instead of link clock */
5373 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5374 target_clock = mode->clock;
5376 target_clock = adjusted_mode->clock;
5378 /* FDI is a binary signal running at ~2.7GHz, encoding
5379 * each output octet as 10 bits. The actual frequency
5380 * is stored as a divider into a 100MHz clock, and the
5381 * mode pixel clock is stored in units of 1KHz.
5382 * Hence the bw of each lane in terms of the mode signal
5385 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5388 /* determine panel color depth */
5389 temp = I915_READ(PIPECONF(pipe));
5390 temp &= ~PIPE_BPC_MASK;
5391 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5406 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5413 intel_crtc->bpp = pipe_bpp;
5414 I915_WRITE(PIPECONF(pipe), temp);
5418 * Account for spread spectrum to avoid
5419 * oversubscribing the link. Max center spread
5420 * is 2.5%; use 5% for safety's sake.
5422 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5423 lane = bps / (link_bw * 8) + 1;
5426 intel_crtc->fdi_lanes = lane;
5428 if (pixel_multiplier > 1)
5429 link_bw *= pixel_multiplier;
5430 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5433 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5434 if (has_reduced_clock)
5435 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5438 /* Enable autotuning of the PLL clock (if permissible) */
5441 if ((intel_panel_use_ssc(dev_priv) &&
5442 dev_priv->lvds_ssc_freq == 100) ||
5443 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5445 } else if (is_sdvo && is_tv)
5448 if (clock.m < factor * clock.n)
5454 dpll |= DPLLB_MODE_LVDS;
5456 dpll |= DPLLB_MODE_DAC_SERIAL;
5458 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5459 if (pixel_multiplier > 1) {
5460 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5462 dpll |= DPLL_DVO_HIGH_SPEED;
5464 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5465 dpll |= DPLL_DVO_HIGH_SPEED;
5467 /* compute bitmask from p1 value */
5468 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5470 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5474 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5477 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5480 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5483 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5487 if (is_sdvo && is_tv)
5488 dpll |= PLL_REF_INPUT_TVCLKINBC;
5490 /* XXX: just matching BIOS for now */
5491 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5493 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5494 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5496 dpll |= PLL_REF_INPUT_DREFCLK;
5498 /* setup pipeconf */
5499 pipeconf = I915_READ(PIPECONF(pipe));
5501 /* Set up the display plane register */
5502 dspcntr = DISPPLANE_GAMMA_ENABLE;
5504 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5505 drm_mode_debug_printmodeline(mode);
5507 /* PCH eDP needs FDI, but CPU eDP does not */
5508 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5509 I915_WRITE(PCH_FP0(pipe), fp);
5510 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5512 POSTING_READ(PCH_DPLL(pipe));
5516 /* enable transcoder DPLL */
5517 if (HAS_PCH_CPT(dev)) {
5518 temp = I915_READ(PCH_DPLL_SEL);
5521 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5524 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5527 /* FIXME: manage transcoder PLLs? */
5528 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5533 I915_WRITE(PCH_DPLL_SEL, temp);
5535 POSTING_READ(PCH_DPLL_SEL);
5539 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5540 * This is an exception to the general rule that mode_set doesn't turn
5544 temp = I915_READ(PCH_LVDS);
5545 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5547 if (HAS_PCH_CPT(dev))
5548 temp |= PORT_TRANS_B_SEL_CPT;
5550 temp |= LVDS_PIPEB_SELECT;
5552 if (HAS_PCH_CPT(dev))
5553 temp &= ~PORT_TRANS_SEL_MASK;
5555 temp &= ~LVDS_PIPEB_SELECT;
5557 /* set the corresponsding LVDS_BORDER bit */
5558 temp |= dev_priv->lvds_border_bits;
5559 /* Set the B0-B3 data pairs corresponding to whether we're going to
5560 * set the DPLLs for dual-channel mode or not.
5563 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5565 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5567 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5568 * appropriately here, but we need to look more thoroughly into how
5569 * panels behave in the two modes.
5571 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5572 lvds_sync |= LVDS_HSYNC_POLARITY;
5573 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5574 lvds_sync |= LVDS_VSYNC_POLARITY;
5575 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5577 char flags[2] = "-+";
5578 DRM_INFO("Changing LVDS panel from "
5579 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5580 flags[!(temp & LVDS_HSYNC_POLARITY)],
5581 flags[!(temp & LVDS_VSYNC_POLARITY)],
5582 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5583 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5584 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5587 I915_WRITE(PCH_LVDS, temp);
5590 pipeconf &= ~PIPECONF_DITHER_EN;
5591 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5592 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5593 pipeconf |= PIPECONF_DITHER_EN;
5594 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5596 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5597 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5599 /* For non-DP output, clear any trans DP clock recovery setting.*/
5600 I915_WRITE(TRANSDATA_M1(pipe), 0);
5601 I915_WRITE(TRANSDATA_N1(pipe), 0);
5602 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5603 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5606 if (!has_edp_encoder ||
5607 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5608 I915_WRITE(PCH_DPLL(pipe), dpll);
5610 /* Wait for the clocks to stabilize. */
5611 POSTING_READ(PCH_DPLL(pipe));
5614 /* The pixel multiplier can only be updated once the
5615 * DPLL is enabled and the clocks are stable.
5617 * So write it again.
5619 I915_WRITE(PCH_DPLL(pipe), dpll);
5622 intel_crtc->lowfreq_avail = false;
5623 if (is_lvds && has_reduced_clock && i915_powersave) {
5624 I915_WRITE(PCH_FP1(pipe), fp2);
5625 intel_crtc->lowfreq_avail = true;
5626 if (HAS_PIPE_CXSR(dev)) {
5627 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5628 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5631 I915_WRITE(PCH_FP1(pipe), fp);
5632 if (HAS_PIPE_CXSR(dev)) {
5633 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5634 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5638 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5639 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5640 /* the chip adds 2 halflines automatically */
5641 adjusted_mode->crtc_vdisplay -= 1;
5642 adjusted_mode->crtc_vtotal -= 1;
5643 adjusted_mode->crtc_vblank_start -= 1;
5644 adjusted_mode->crtc_vblank_end -= 1;
5645 adjusted_mode->crtc_vsync_end -= 1;
5646 adjusted_mode->crtc_vsync_start -= 1;
5648 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5650 I915_WRITE(HTOTAL(pipe),
5651 (adjusted_mode->crtc_hdisplay - 1) |
5652 ((adjusted_mode->crtc_htotal - 1) << 16));
5653 I915_WRITE(HBLANK(pipe),
5654 (adjusted_mode->crtc_hblank_start - 1) |
5655 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5656 I915_WRITE(HSYNC(pipe),
5657 (adjusted_mode->crtc_hsync_start - 1) |
5658 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5660 I915_WRITE(VTOTAL(pipe),
5661 (adjusted_mode->crtc_vdisplay - 1) |
5662 ((adjusted_mode->crtc_vtotal - 1) << 16));
5663 I915_WRITE(VBLANK(pipe),
5664 (adjusted_mode->crtc_vblank_start - 1) |
5665 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5666 I915_WRITE(VSYNC(pipe),
5667 (adjusted_mode->crtc_vsync_start - 1) |
5668 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5670 /* pipesrc controls the size that is scaled from, which should
5671 * always be the user's requested size.
5673 I915_WRITE(PIPESRC(pipe),
5674 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5676 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5677 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5678 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5679 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5681 if (has_edp_encoder &&
5682 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5683 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5686 I915_WRITE(PIPECONF(pipe), pipeconf);
5687 POSTING_READ(PIPECONF(pipe));
5689 intel_wait_for_vblank(dev, pipe);
5692 /* enable address swizzle for tiling buffer */
5693 temp = I915_READ(DISP_ARB_CTL);
5694 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5697 I915_WRITE(DSPCNTR(plane), dspcntr);
5698 POSTING_READ(DSPCNTR(plane));
5700 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5702 intel_update_watermarks(dev);
5707 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5708 struct drm_display_mode *mode,
5709 struct drm_display_mode *adjusted_mode,
5711 struct drm_framebuffer *old_fb)
5713 struct drm_device *dev = crtc->dev;
5714 struct drm_i915_private *dev_priv = dev->dev_private;
5715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5716 int pipe = intel_crtc->pipe;
5719 drm_vblank_pre_modeset(dev, pipe);
5721 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5724 drm_vblank_post_modeset(dev, pipe);
5726 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5731 static void g4x_write_eld(struct drm_connector *connector,
5732 struct drm_crtc *crtc)
5734 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5735 uint8_t *eld = connector->eld;
5740 i = I915_READ(G4X_AUD_VID_DID);
5742 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5743 eldv = G4X_ELDV_DEVCL_DEVBLC;
5745 eldv = G4X_ELDV_DEVCTG;
5747 i = I915_READ(G4X_AUD_CNTL_ST);
5748 i &= ~(eldv | G4X_ELD_ADDR);
5749 len = (i >> 9) & 0x1f; /* ELD buffer size */
5750 I915_WRITE(G4X_AUD_CNTL_ST, i);
5755 len = min_t(uint8_t, eld[2], len);
5756 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5757 for (i = 0; i < len; i++)
5758 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5760 i = I915_READ(G4X_AUD_CNTL_ST);
5762 I915_WRITE(G4X_AUD_CNTL_ST, i);
5765 static void ironlake_write_eld(struct drm_connector *connector,
5766 struct drm_crtc *crtc)
5768 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5769 uint8_t *eld = connector->eld;
5777 if (IS_IVYBRIDGE(connector->dev)) {
5778 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5779 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5780 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5782 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5783 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5784 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5787 i = to_intel_crtc(crtc)->pipe;
5788 hdmiw_hdmiedid += i * 0x100;
5789 aud_cntl_st += i * 0x100;
5791 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5793 i = I915_READ(aud_cntl_st);
5794 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5796 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5797 /* operate blindly on all ports */
5798 eldv = GEN5_ELD_VALIDB;
5799 eldv |= GEN5_ELD_VALIDB << 4;
5800 eldv |= GEN5_ELD_VALIDB << 8;
5802 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5803 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5806 i = I915_READ(aud_cntrl_st2);
5808 I915_WRITE(aud_cntrl_st2, i);
5813 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5814 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5815 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5818 i = I915_READ(aud_cntl_st);
5819 i &= ~GEN5_ELD_ADDRESS;
5820 I915_WRITE(aud_cntl_st, i);
5822 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5823 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5824 for (i = 0; i < len; i++)
5825 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5827 i = I915_READ(aud_cntrl_st2);
5829 I915_WRITE(aud_cntrl_st2, i);
5832 void intel_write_eld(struct drm_encoder *encoder,
5833 struct drm_display_mode *mode)
5835 struct drm_crtc *crtc = encoder->crtc;
5836 struct drm_connector *connector;
5837 struct drm_device *dev = encoder->dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5840 connector = drm_select_eld(encoder, mode);
5844 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5846 drm_get_connector_name(connector),
5847 connector->encoder->base.id,
5848 drm_get_encoder_name(connector->encoder));
5850 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5852 if (dev_priv->display.write_eld)
5853 dev_priv->display.write_eld(connector, crtc);
5856 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5857 void intel_crtc_load_lut(struct drm_crtc *crtc)
5859 struct drm_device *dev = crtc->dev;
5860 struct drm_i915_private *dev_priv = dev->dev_private;
5861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5862 int palreg = PALETTE(intel_crtc->pipe);
5865 /* The clocks have to be on to load the palette. */
5869 /* use legacy palette for Ironlake */
5870 if (HAS_PCH_SPLIT(dev))
5871 palreg = LGC_PALETTE(intel_crtc->pipe);
5873 for (i = 0; i < 256; i++) {
5874 I915_WRITE(palreg + 4 * i,
5875 (intel_crtc->lut_r[i] << 16) |
5876 (intel_crtc->lut_g[i] << 8) |
5877 intel_crtc->lut_b[i]);
5881 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5883 struct drm_device *dev = crtc->dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5886 bool visible = base != 0;
5889 if (intel_crtc->cursor_visible == visible)
5892 cntl = I915_READ(_CURACNTR);
5894 /* On these chipsets we can only modify the base whilst
5895 * the cursor is disabled.
5897 I915_WRITE(_CURABASE, base);
5899 cntl &= ~(CURSOR_FORMAT_MASK);
5900 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5901 cntl |= CURSOR_ENABLE |
5902 CURSOR_GAMMA_ENABLE |
5905 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5906 I915_WRITE(_CURACNTR, cntl);
5908 intel_crtc->cursor_visible = visible;
5911 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5913 struct drm_device *dev = crtc->dev;
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916 int pipe = intel_crtc->pipe;
5917 bool visible = base != 0;
5919 if (intel_crtc->cursor_visible != visible) {
5920 uint32_t cntl = I915_READ(CURCNTR(pipe));
5922 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5923 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5924 cntl |= pipe << 28; /* Connect to correct pipe */
5926 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5927 cntl |= CURSOR_MODE_DISABLE;
5929 I915_WRITE(CURCNTR(pipe), cntl);
5931 intel_crtc->cursor_visible = visible;
5933 /* and commit changes on next vblank */
5934 I915_WRITE(CURBASE(pipe), base);
5937 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5938 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5941 struct drm_device *dev = crtc->dev;
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5944 int pipe = intel_crtc->pipe;
5945 int x = intel_crtc->cursor_x;
5946 int y = intel_crtc->cursor_y;
5952 if (on && crtc->enabled && crtc->fb) {
5953 base = intel_crtc->cursor_addr;
5954 if (x > (int) crtc->fb->width)
5957 if (y > (int) crtc->fb->height)
5963 if (x + intel_crtc->cursor_width < 0)
5966 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5969 pos |= x << CURSOR_X_SHIFT;
5972 if (y + intel_crtc->cursor_height < 0)
5975 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5978 pos |= y << CURSOR_Y_SHIFT;
5980 visible = base != 0;
5981 if (!visible && !intel_crtc->cursor_visible)
5984 I915_WRITE(CURPOS(pipe), pos);
5985 if (IS_845G(dev) || IS_I865G(dev))
5986 i845_update_cursor(crtc, base);
5988 i9xx_update_cursor(crtc, base);
5991 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5994 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5995 struct drm_file *file,
5997 uint32_t width, uint32_t height)
5999 struct drm_device *dev = crtc->dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002 struct drm_i915_gem_object *obj;
6006 DRM_DEBUG_KMS("\n");
6008 /* if we want to turn off the cursor ignore width and height */
6010 DRM_DEBUG_KMS("cursor off\n");
6013 mutex_lock(&dev->struct_mutex);
6017 /* Currently we only support 64x64 cursors */
6018 if (width != 64 || height != 64) {
6019 DRM_ERROR("we currently only support 64x64 cursors\n");
6023 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6024 if (&obj->base == NULL)
6027 if (obj->base.size < width * height * 4) {
6028 DRM_ERROR("buffer is to small\n");
6033 /* we only need to pin inside GTT if cursor is non-phy */
6034 mutex_lock(&dev->struct_mutex);
6035 if (!dev_priv->info->cursor_needs_physical) {
6036 if (obj->tiling_mode) {
6037 DRM_ERROR("cursor cannot be tiled\n");
6042 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6044 DRM_ERROR("failed to move cursor bo into the GTT\n");
6048 ret = i915_gem_object_put_fence(obj);
6050 DRM_ERROR("failed to release fence for cursor");
6054 addr = obj->gtt_offset;
6056 int align = IS_I830(dev) ? 16 * 1024 : 256;
6057 ret = i915_gem_attach_phys_object(dev, obj,
6058 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6061 DRM_ERROR("failed to attach phys object\n");
6064 addr = obj->phys_obj->handle->busaddr;
6068 I915_WRITE(CURSIZE, (height << 12) | width);
6071 if (intel_crtc->cursor_bo) {
6072 if (dev_priv->info->cursor_needs_physical) {
6073 if (intel_crtc->cursor_bo != obj)
6074 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6076 i915_gem_object_unpin(intel_crtc->cursor_bo);
6077 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6080 mutex_unlock(&dev->struct_mutex);
6082 intel_crtc->cursor_addr = addr;
6083 intel_crtc->cursor_bo = obj;
6084 intel_crtc->cursor_width = width;
6085 intel_crtc->cursor_height = height;
6087 intel_crtc_update_cursor(crtc, true);
6091 i915_gem_object_unpin(obj);
6093 mutex_unlock(&dev->struct_mutex);
6095 drm_gem_object_unreference_unlocked(&obj->base);
6099 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6103 intel_crtc->cursor_x = x;
6104 intel_crtc->cursor_y = y;
6106 intel_crtc_update_cursor(crtc, true);
6111 /** Sets the color ramps on behalf of RandR */
6112 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6113 u16 blue, int regno)
6115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6117 intel_crtc->lut_r[regno] = red >> 8;
6118 intel_crtc->lut_g[regno] = green >> 8;
6119 intel_crtc->lut_b[regno] = blue >> 8;
6122 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6123 u16 *blue, int regno)
6125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6127 *red = intel_crtc->lut_r[regno] << 8;
6128 *green = intel_crtc->lut_g[regno] << 8;
6129 *blue = intel_crtc->lut_b[regno] << 8;
6132 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6133 u16 *blue, uint32_t start, uint32_t size)
6135 int end = (start + size > 256) ? 256 : start + size, i;
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6138 for (i = start; i < end; i++) {
6139 intel_crtc->lut_r[i] = red[i] >> 8;
6140 intel_crtc->lut_g[i] = green[i] >> 8;
6141 intel_crtc->lut_b[i] = blue[i] >> 8;
6144 intel_crtc_load_lut(crtc);
6148 * Get a pipe with a simple mode set on it for doing load-based monitor
6151 * It will be up to the load-detect code to adjust the pipe as appropriate for
6152 * its requirements. The pipe will be connected to no other encoders.
6154 * Currently this code will only succeed if there is a pipe with no encoders
6155 * configured for it. In the future, it could choose to temporarily disable
6156 * some outputs to free up a pipe for its use.
6158 * \return crtc, or NULL if no pipes are available.
6161 /* VESA 640x480x72Hz mode to set on the pipe */
6162 static struct drm_display_mode load_detect_mode = {
6163 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6164 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6167 static struct drm_framebuffer *
6168 intel_framebuffer_create(struct drm_device *dev,
6169 struct drm_mode_fb_cmd *mode_cmd,
6170 struct drm_i915_gem_object *obj)
6172 struct intel_framebuffer *intel_fb;
6175 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6177 drm_gem_object_unreference_unlocked(&obj->base);
6178 return ERR_PTR(-ENOMEM);
6181 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6183 drm_gem_object_unreference_unlocked(&obj->base);
6185 return ERR_PTR(ret);
6188 return &intel_fb->base;
6192 intel_framebuffer_pitch_for_width(int width, int bpp)
6194 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6195 return ALIGN(pitch, 64);
6199 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6201 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6202 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6205 static struct drm_framebuffer *
6206 intel_framebuffer_create_for_mode(struct drm_device *dev,
6207 struct drm_display_mode *mode,
6210 struct drm_i915_gem_object *obj;
6211 struct drm_mode_fb_cmd mode_cmd;
6213 obj = i915_gem_alloc_object(dev,
6214 intel_framebuffer_size_for_mode(mode, bpp));
6216 return ERR_PTR(-ENOMEM);
6218 mode_cmd.width = mode->hdisplay;
6219 mode_cmd.height = mode->vdisplay;
6220 mode_cmd.depth = depth;
6222 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6224 return intel_framebuffer_create(dev, &mode_cmd, obj);
6227 static struct drm_framebuffer *
6228 mode_fits_in_fbdev(struct drm_device *dev,
6229 struct drm_display_mode *mode)
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232 struct drm_i915_gem_object *obj;
6233 struct drm_framebuffer *fb;
6235 if (dev_priv->fbdev == NULL)
6238 obj = dev_priv->fbdev->ifb.obj;
6242 fb = &dev_priv->fbdev->ifb.base;
6243 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6244 fb->bits_per_pixel))
6247 if (obj->base.size < mode->vdisplay * fb->pitch)
6253 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6254 struct drm_connector *connector,
6255 struct drm_display_mode *mode,
6256 struct intel_load_detect_pipe *old)
6258 struct intel_crtc *intel_crtc;
6259 struct drm_crtc *possible_crtc;
6260 struct drm_encoder *encoder = &intel_encoder->base;
6261 struct drm_crtc *crtc = NULL;
6262 struct drm_device *dev = encoder->dev;
6263 struct drm_framebuffer *old_fb;
6266 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6267 connector->base.id, drm_get_connector_name(connector),
6268 encoder->base.id, drm_get_encoder_name(encoder));
6271 * Algorithm gets a little messy:
6273 * - if the connector already has an assigned crtc, use it (but make
6274 * sure it's on first)
6276 * - try to find the first unused crtc that can drive this connector,
6277 * and use that if we find one
6280 /* See if we already have a CRTC for this connector */
6281 if (encoder->crtc) {
6282 crtc = encoder->crtc;
6284 intel_crtc = to_intel_crtc(crtc);
6285 old->dpms_mode = intel_crtc->dpms_mode;
6286 old->load_detect_temp = false;
6288 /* Make sure the crtc and connector are running */
6289 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6290 struct drm_encoder_helper_funcs *encoder_funcs;
6291 struct drm_crtc_helper_funcs *crtc_funcs;
6293 crtc_funcs = crtc->helper_private;
6294 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6296 encoder_funcs = encoder->helper_private;
6297 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6303 /* Find an unused one (if possible) */
6304 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6306 if (!(encoder->possible_crtcs & (1 << i)))
6308 if (!possible_crtc->enabled) {
6309 crtc = possible_crtc;
6315 * If we didn't find an unused CRTC, don't use any.
6318 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6322 encoder->crtc = crtc;
6323 connector->encoder = encoder;
6325 intel_crtc = to_intel_crtc(crtc);
6326 old->dpms_mode = intel_crtc->dpms_mode;
6327 old->load_detect_temp = true;
6328 old->release_fb = NULL;
6331 mode = &load_detect_mode;
6335 /* We need a framebuffer large enough to accommodate all accesses
6336 * that the plane may generate whilst we perform load detection.
6337 * We can not rely on the fbcon either being present (we get called
6338 * during its initialisation to detect all boot displays, or it may
6339 * not even exist) or that it is large enough to satisfy the
6342 crtc->fb = mode_fits_in_fbdev(dev, mode);
6343 if (crtc->fb == NULL) {
6344 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6345 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6346 old->release_fb = crtc->fb;
6348 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6349 if (IS_ERR(crtc->fb)) {
6350 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6355 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6356 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6357 if (old->release_fb)
6358 old->release_fb->funcs->destroy(old->release_fb);
6363 /* let the connector get through one full cycle before testing */
6364 intel_wait_for_vblank(dev, intel_crtc->pipe);
6369 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6370 struct drm_connector *connector,
6371 struct intel_load_detect_pipe *old)
6373 struct drm_encoder *encoder = &intel_encoder->base;
6374 struct drm_device *dev = encoder->dev;
6375 struct drm_crtc *crtc = encoder->crtc;
6376 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6377 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6380 connector->base.id, drm_get_connector_name(connector),
6381 encoder->base.id, drm_get_encoder_name(encoder));
6383 if (old->load_detect_temp) {
6384 connector->encoder = NULL;
6385 drm_helper_disable_unused_functions(dev);
6387 if (old->release_fb)
6388 old->release_fb->funcs->destroy(old->release_fb);
6393 /* Switch crtc and encoder back off if necessary */
6394 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6395 encoder_funcs->dpms(encoder, old->dpms_mode);
6396 crtc_funcs->dpms(crtc, old->dpms_mode);
6400 /* Returns the clock of the currently programmed mode of the given pipe. */
6401 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405 int pipe = intel_crtc->pipe;
6406 u32 dpll = I915_READ(DPLL(pipe));
6408 intel_clock_t clock;
6410 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6411 fp = I915_READ(FP0(pipe));
6413 fp = I915_READ(FP1(pipe));
6415 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6416 if (IS_PINEVIEW(dev)) {
6417 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6418 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6420 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6421 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6424 if (!IS_GEN2(dev)) {
6425 if (IS_PINEVIEW(dev))
6426 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6427 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6429 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6430 DPLL_FPA01_P1_POST_DIV_SHIFT);
6432 switch (dpll & DPLL_MODE_MASK) {
6433 case DPLLB_MODE_DAC_SERIAL:
6434 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6437 case DPLLB_MODE_LVDS:
6438 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6442 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6443 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6447 /* XXX: Handle the 100Mhz refclk */
6448 intel_clock(dev, 96000, &clock);
6450 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6453 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6454 DPLL_FPA01_P1_POST_DIV_SHIFT);
6457 if ((dpll & PLL_REF_INPUT_MASK) ==
6458 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6459 /* XXX: might not be 66MHz */
6460 intel_clock(dev, 66000, &clock);
6462 intel_clock(dev, 48000, &clock);
6464 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6467 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6468 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6470 if (dpll & PLL_P2_DIVIDE_BY_4)
6475 intel_clock(dev, 48000, &clock);
6479 /* XXX: It would be nice to validate the clocks, but we can't reuse
6480 * i830PllIsValid() because it relies on the xf86_config connector
6481 * configuration being accurate, which it isn't necessarily.
6487 /** Returns the currently programmed mode of the given pipe. */
6488 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6489 struct drm_crtc *crtc)
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6493 int pipe = intel_crtc->pipe;
6494 struct drm_display_mode *mode;
6495 int htot = I915_READ(HTOTAL(pipe));
6496 int hsync = I915_READ(HSYNC(pipe));
6497 int vtot = I915_READ(VTOTAL(pipe));
6498 int vsync = I915_READ(VSYNC(pipe));
6500 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6504 mode->clock = intel_crtc_clock_get(dev, crtc);
6505 mode->hdisplay = (htot & 0xffff) + 1;
6506 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6507 mode->hsync_start = (hsync & 0xffff) + 1;
6508 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6509 mode->vdisplay = (vtot & 0xffff) + 1;
6510 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6511 mode->vsync_start = (vsync & 0xffff) + 1;
6512 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6514 drm_mode_set_name(mode);
6515 drm_mode_set_crtcinfo(mode, 0);
6520 #define GPU_IDLE_TIMEOUT 500 /* ms */
6522 /* When this timer fires, we've been idle for awhile */
6523 static void intel_gpu_idle_timer(unsigned long arg)
6525 struct drm_device *dev = (struct drm_device *)arg;
6526 drm_i915_private_t *dev_priv = dev->dev_private;
6528 if (!list_empty(&dev_priv->mm.active_list)) {
6529 /* Still processing requests, so just re-arm the timer. */
6530 mod_timer(&dev_priv->idle_timer, jiffies +
6531 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6535 dev_priv->busy = false;
6536 queue_work(dev_priv->wq, &dev_priv->idle_work);
6539 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6541 static void intel_crtc_idle_timer(unsigned long arg)
6543 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6544 struct drm_crtc *crtc = &intel_crtc->base;
6545 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6546 struct intel_framebuffer *intel_fb;
6548 intel_fb = to_intel_framebuffer(crtc->fb);
6549 if (intel_fb && intel_fb->obj->active) {
6550 /* The framebuffer is still being accessed by the GPU. */
6551 mod_timer(&intel_crtc->idle_timer, jiffies +
6552 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6556 intel_crtc->busy = false;
6557 queue_work(dev_priv->wq, &dev_priv->idle_work);
6560 static void intel_increase_pllclock(struct drm_crtc *crtc)
6562 struct drm_device *dev = crtc->dev;
6563 drm_i915_private_t *dev_priv = dev->dev_private;
6564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6565 int pipe = intel_crtc->pipe;
6566 int dpll_reg = DPLL(pipe);
6569 if (HAS_PCH_SPLIT(dev))
6572 if (!dev_priv->lvds_downclock_avail)
6575 dpll = I915_READ(dpll_reg);
6576 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6577 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6579 /* Unlock panel regs */
6580 I915_WRITE(PP_CONTROL,
6581 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6583 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6584 I915_WRITE(dpll_reg, dpll);
6585 intel_wait_for_vblank(dev, pipe);
6587 dpll = I915_READ(dpll_reg);
6588 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6589 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6591 /* ...and lock them again */
6592 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6595 /* Schedule downclock */
6596 mod_timer(&intel_crtc->idle_timer, jiffies +
6597 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6600 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6602 struct drm_device *dev = crtc->dev;
6603 drm_i915_private_t *dev_priv = dev->dev_private;
6604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6605 int pipe = intel_crtc->pipe;
6606 int dpll_reg = DPLL(pipe);
6607 int dpll = I915_READ(dpll_reg);
6609 if (HAS_PCH_SPLIT(dev))
6612 if (!dev_priv->lvds_downclock_avail)
6616 * Since this is called by a timer, we should never get here in
6619 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6620 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6622 /* Unlock panel regs */
6623 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6626 dpll |= DISPLAY_RATE_SELECT_FPA1;
6627 I915_WRITE(dpll_reg, dpll);
6628 intel_wait_for_vblank(dev, pipe);
6629 dpll = I915_READ(dpll_reg);
6630 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6631 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6633 /* ...and lock them again */
6634 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6640 * intel_idle_update - adjust clocks for idleness
6641 * @work: work struct
6643 * Either the GPU or display (or both) went idle. Check the busy status
6644 * here and adjust the CRTC and GPU clocks as necessary.
6646 static void intel_idle_update(struct work_struct *work)
6648 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6650 struct drm_device *dev = dev_priv->dev;
6651 struct drm_crtc *crtc;
6652 struct intel_crtc *intel_crtc;
6654 if (!i915_powersave)
6657 mutex_lock(&dev->struct_mutex);
6659 i915_update_gfx_val(dev_priv);
6661 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6662 /* Skip inactive CRTCs */
6666 intel_crtc = to_intel_crtc(crtc);
6667 if (!intel_crtc->busy)
6668 intel_decrease_pllclock(crtc);
6672 mutex_unlock(&dev->struct_mutex);
6676 * intel_mark_busy - mark the GPU and possibly the display busy
6678 * @obj: object we're operating on
6680 * Callers can use this function to indicate that the GPU is busy processing
6681 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6682 * buffer), we'll also mark the display as busy, so we know to increase its
6685 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6687 drm_i915_private_t *dev_priv = dev->dev_private;
6688 struct drm_crtc *crtc = NULL;
6689 struct intel_framebuffer *intel_fb;
6690 struct intel_crtc *intel_crtc;
6692 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6695 if (!dev_priv->busy)
6696 dev_priv->busy = true;
6698 mod_timer(&dev_priv->idle_timer, jiffies +
6699 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6701 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6705 intel_crtc = to_intel_crtc(crtc);
6706 intel_fb = to_intel_framebuffer(crtc->fb);
6707 if (intel_fb->obj == obj) {
6708 if (!intel_crtc->busy) {
6709 /* Non-busy -> busy, upclock */
6710 intel_increase_pllclock(crtc);
6711 intel_crtc->busy = true;
6713 /* Busy -> busy, put off timer */
6714 mod_timer(&intel_crtc->idle_timer, jiffies +
6715 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6721 static void intel_crtc_destroy(struct drm_crtc *crtc)
6723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6724 struct drm_device *dev = crtc->dev;
6725 struct intel_unpin_work *work;
6726 unsigned long flags;
6728 spin_lock_irqsave(&dev->event_lock, flags);
6729 work = intel_crtc->unpin_work;
6730 intel_crtc->unpin_work = NULL;
6731 spin_unlock_irqrestore(&dev->event_lock, flags);
6734 cancel_work_sync(&work->work);
6738 drm_crtc_cleanup(crtc);
6743 static void intel_unpin_work_fn(struct work_struct *__work)
6745 struct intel_unpin_work *work =
6746 container_of(__work, struct intel_unpin_work, work);
6748 mutex_lock(&work->dev->struct_mutex);
6749 i915_gem_object_unpin(work->old_fb_obj);
6750 drm_gem_object_unreference(&work->pending_flip_obj->base);
6751 drm_gem_object_unreference(&work->old_fb_obj->base);
6753 intel_update_fbc(work->dev);
6754 mutex_unlock(&work->dev->struct_mutex);
6758 static void do_intel_finish_page_flip(struct drm_device *dev,
6759 struct drm_crtc *crtc)
6761 drm_i915_private_t *dev_priv = dev->dev_private;
6762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6763 struct intel_unpin_work *work;
6764 struct drm_i915_gem_object *obj;
6765 struct drm_pending_vblank_event *e;
6766 struct timeval tnow, tvbl;
6767 unsigned long flags;
6769 /* Ignore early vblank irqs */
6770 if (intel_crtc == NULL)
6773 do_gettimeofday(&tnow);
6775 spin_lock_irqsave(&dev->event_lock, flags);
6776 work = intel_crtc->unpin_work;
6777 if (work == NULL || !work->pending) {
6778 spin_unlock_irqrestore(&dev->event_lock, flags);
6782 intel_crtc->unpin_work = NULL;
6786 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6788 /* Called before vblank count and timestamps have
6789 * been updated for the vblank interval of flip
6790 * completion? Need to increment vblank count and
6791 * add one videorefresh duration to returned timestamp
6792 * to account for this. We assume this happened if we
6793 * get called over 0.9 frame durations after the last
6794 * timestamped vblank.
6796 * This calculation can not be used with vrefresh rates
6797 * below 5Hz (10Hz to be on the safe side) without
6798 * promoting to 64 integers.
6800 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6801 9 * crtc->framedur_ns) {
6802 e->event.sequence++;
6803 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6807 e->event.tv_sec = tvbl.tv_sec;
6808 e->event.tv_usec = tvbl.tv_usec;
6810 list_add_tail(&e->base.link,
6811 &e->base.file_priv->event_list);
6812 wake_up_interruptible(&e->base.file_priv->event_wait);
6815 drm_vblank_put(dev, intel_crtc->pipe);
6817 spin_unlock_irqrestore(&dev->event_lock, flags);
6819 obj = work->old_fb_obj;
6821 atomic_clear_mask(1 << intel_crtc->plane,
6822 &obj->pending_flip.counter);
6823 if (atomic_read(&obj->pending_flip) == 0)
6824 wake_up(&dev_priv->pending_flip_queue);
6826 schedule_work(&work->work);
6828 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6831 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6833 drm_i915_private_t *dev_priv = dev->dev_private;
6834 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6836 do_intel_finish_page_flip(dev, crtc);
6839 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6841 drm_i915_private_t *dev_priv = dev->dev_private;
6842 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6844 do_intel_finish_page_flip(dev, crtc);
6847 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6849 drm_i915_private_t *dev_priv = dev->dev_private;
6850 struct intel_crtc *intel_crtc =
6851 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6852 unsigned long flags;
6854 spin_lock_irqsave(&dev->event_lock, flags);
6855 if (intel_crtc->unpin_work) {
6856 if ((++intel_crtc->unpin_work->pending) > 1)
6857 DRM_ERROR("Prepared flip multiple times\n");
6859 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6861 spin_unlock_irqrestore(&dev->event_lock, flags);
6864 static int intel_gen2_queue_flip(struct drm_device *dev,
6865 struct drm_crtc *crtc,
6866 struct drm_framebuffer *fb,
6867 struct drm_i915_gem_object *obj)
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871 unsigned long offset;
6875 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6879 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6880 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6882 ret = BEGIN_LP_RING(6);
6886 /* Can't queue multiple flips, so wait for the previous
6887 * one to finish before executing the next.
6889 if (intel_crtc->plane)
6890 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6892 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6893 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6895 OUT_RING(MI_DISPLAY_FLIP |
6896 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6897 OUT_RING(fb->pitch);
6898 OUT_RING(obj->gtt_offset + offset);
6905 static int intel_gen3_queue_flip(struct drm_device *dev,
6906 struct drm_crtc *crtc,
6907 struct drm_framebuffer *fb,
6908 struct drm_i915_gem_object *obj)
6910 struct drm_i915_private *dev_priv = dev->dev_private;
6911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6912 unsigned long offset;
6916 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6920 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6921 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6923 ret = BEGIN_LP_RING(6);
6927 if (intel_crtc->plane)
6928 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6930 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6931 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6933 OUT_RING(MI_DISPLAY_FLIP_I915 |
6934 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6935 OUT_RING(fb->pitch);
6936 OUT_RING(obj->gtt_offset + offset);
6944 static int intel_gen4_queue_flip(struct drm_device *dev,
6945 struct drm_crtc *crtc,
6946 struct drm_framebuffer *fb,
6947 struct drm_i915_gem_object *obj)
6949 struct drm_i915_private *dev_priv = dev->dev_private;
6950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6951 uint32_t pf, pipesrc;
6954 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6958 ret = BEGIN_LP_RING(4);
6962 /* i965+ uses the linear or tiled offsets from the
6963 * Display Registers (which do not change across a page-flip)
6964 * so we need only reprogram the base address.
6966 OUT_RING(MI_DISPLAY_FLIP |
6967 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6968 OUT_RING(fb->pitch);
6969 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6971 /* XXX Enabling the panel-fitter across page-flip is so far
6972 * untested on non-native modes, so ignore it for now.
6973 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6976 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6977 OUT_RING(pf | pipesrc);
6983 static int intel_gen6_queue_flip(struct drm_device *dev,
6984 struct drm_crtc *crtc,
6985 struct drm_framebuffer *fb,
6986 struct drm_i915_gem_object *obj)
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990 uint32_t pf, pipesrc;
6993 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6997 ret = BEGIN_LP_RING(4);
7001 OUT_RING(MI_DISPLAY_FLIP |
7002 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7003 OUT_RING(fb->pitch | obj->tiling_mode);
7004 OUT_RING(obj->gtt_offset);
7006 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7007 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7008 OUT_RING(pf | pipesrc);
7015 * On gen7 we currently use the blit ring because (in early silicon at least)
7016 * the render ring doesn't give us interrpts for page flip completion, which
7017 * means clients will hang after the first flip is queued. Fortunately the
7018 * blit ring generates interrupts properly, so use it instead.
7020 static int intel_gen7_queue_flip(struct drm_device *dev,
7021 struct drm_crtc *crtc,
7022 struct drm_framebuffer *fb,
7023 struct drm_i915_gem_object *obj)
7025 struct drm_i915_private *dev_priv = dev->dev_private;
7026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7027 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7030 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7034 ret = intel_ring_begin(ring, 4);
7038 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7039 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7040 intel_ring_emit(ring, (obj->gtt_offset));
7041 intel_ring_emit(ring, (MI_NOOP));
7042 intel_ring_advance(ring);
7047 static int intel_default_queue_flip(struct drm_device *dev,
7048 struct drm_crtc *crtc,
7049 struct drm_framebuffer *fb,
7050 struct drm_i915_gem_object *obj)
7055 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7056 struct drm_framebuffer *fb,
7057 struct drm_pending_vblank_event *event)
7059 struct drm_device *dev = crtc->dev;
7060 struct drm_i915_private *dev_priv = dev->dev_private;
7061 struct intel_framebuffer *intel_fb;
7062 struct drm_i915_gem_object *obj;
7063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7064 struct intel_unpin_work *work;
7065 unsigned long flags;
7068 work = kzalloc(sizeof *work, GFP_KERNEL);
7072 work->event = event;
7073 work->dev = crtc->dev;
7074 intel_fb = to_intel_framebuffer(crtc->fb);
7075 work->old_fb_obj = intel_fb->obj;
7076 INIT_WORK(&work->work, intel_unpin_work_fn);
7078 /* We borrow the event spin lock for protecting unpin_work */
7079 spin_lock_irqsave(&dev->event_lock, flags);
7080 if (intel_crtc->unpin_work) {
7081 spin_unlock_irqrestore(&dev->event_lock, flags);
7084 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7087 intel_crtc->unpin_work = work;
7088 spin_unlock_irqrestore(&dev->event_lock, flags);
7090 intel_fb = to_intel_framebuffer(fb);
7091 obj = intel_fb->obj;
7093 mutex_lock(&dev->struct_mutex);
7095 /* Reference the objects for the scheduled work. */
7096 drm_gem_object_reference(&work->old_fb_obj->base);
7097 drm_gem_object_reference(&obj->base);
7101 ret = drm_vblank_get(dev, intel_crtc->pipe);
7105 work->pending_flip_obj = obj;
7107 work->enable_stall_check = true;
7109 /* Block clients from rendering to the new back buffer until
7110 * the flip occurs and the object is no longer visible.
7112 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7114 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7116 goto cleanup_pending;
7118 intel_disable_fbc(dev);
7119 mutex_unlock(&dev->struct_mutex);
7121 trace_i915_flip_request(intel_crtc->plane, obj);
7126 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7128 drm_gem_object_unreference(&work->old_fb_obj->base);
7129 drm_gem_object_unreference(&obj->base);
7130 mutex_unlock(&dev->struct_mutex);
7132 spin_lock_irqsave(&dev->event_lock, flags);
7133 intel_crtc->unpin_work = NULL;
7134 spin_unlock_irqrestore(&dev->event_lock, flags);
7141 static void intel_sanitize_modesetting(struct drm_device *dev,
7142 int pipe, int plane)
7144 struct drm_i915_private *dev_priv = dev->dev_private;
7147 if (HAS_PCH_SPLIT(dev))
7150 /* Who knows what state these registers were left in by the BIOS or
7153 * If we leave the registers in a conflicting state (e.g. with the
7154 * display plane reading from the other pipe than the one we intend
7155 * to use) then when we attempt to teardown the active mode, we will
7156 * not disable the pipes and planes in the correct order -- leaving
7157 * a plane reading from a disabled pipe and possibly leading to
7158 * undefined behaviour.
7161 reg = DSPCNTR(plane);
7162 val = I915_READ(reg);
7164 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7166 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7169 /* This display plane is active and attached to the other CPU pipe. */
7172 /* Disable the plane and wait for it to stop reading from the pipe. */
7173 intel_disable_plane(dev_priv, plane, pipe);
7174 intel_disable_pipe(dev_priv, pipe);
7177 static void intel_crtc_reset(struct drm_crtc *crtc)
7179 struct drm_device *dev = crtc->dev;
7180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7182 /* Reset flags back to the 'unknown' status so that they
7183 * will be correctly set on the initial modeset.
7185 intel_crtc->dpms_mode = -1;
7187 /* We need to fix up any BIOS configuration that conflicts with
7190 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7193 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7194 .dpms = intel_crtc_dpms,
7195 .mode_fixup = intel_crtc_mode_fixup,
7196 .mode_set = intel_crtc_mode_set,
7197 .mode_set_base = intel_pipe_set_base,
7198 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7199 .load_lut = intel_crtc_load_lut,
7200 .disable = intel_crtc_disable,
7203 static const struct drm_crtc_funcs intel_crtc_funcs = {
7204 .reset = intel_crtc_reset,
7205 .cursor_set = intel_crtc_cursor_set,
7206 .cursor_move = intel_crtc_cursor_move,
7207 .gamma_set = intel_crtc_gamma_set,
7208 .set_config = drm_crtc_helper_set_config,
7209 .destroy = intel_crtc_destroy,
7210 .page_flip = intel_crtc_page_flip,
7213 static void intel_crtc_init(struct drm_device *dev, int pipe)
7215 drm_i915_private_t *dev_priv = dev->dev_private;
7216 struct intel_crtc *intel_crtc;
7219 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7220 if (intel_crtc == NULL)
7223 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7225 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7226 for (i = 0; i < 256; i++) {
7227 intel_crtc->lut_r[i] = i;
7228 intel_crtc->lut_g[i] = i;
7229 intel_crtc->lut_b[i] = i;
7232 /* Swap pipes & planes for FBC on pre-965 */
7233 intel_crtc->pipe = pipe;
7234 intel_crtc->plane = pipe;
7235 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7236 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7237 intel_crtc->plane = !pipe;
7240 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7241 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7242 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7243 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7245 intel_crtc_reset(&intel_crtc->base);
7246 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7247 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7249 if (HAS_PCH_SPLIT(dev)) {
7250 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7251 intel_helper_funcs.commit = ironlake_crtc_commit;
7253 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7254 intel_helper_funcs.commit = i9xx_crtc_commit;
7257 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7259 intel_crtc->busy = false;
7261 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7262 (unsigned long)intel_crtc);
7265 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7266 struct drm_file *file)
7268 drm_i915_private_t *dev_priv = dev->dev_private;
7269 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7270 struct drm_mode_object *drmmode_obj;
7271 struct intel_crtc *crtc;
7274 DRM_ERROR("called with no initialization\n");
7278 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7279 DRM_MODE_OBJECT_CRTC);
7282 DRM_ERROR("no such CRTC id\n");
7286 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7287 pipe_from_crtc_id->pipe = crtc->pipe;
7292 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7294 struct intel_encoder *encoder;
7298 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7299 if (type_mask & encoder->clone_mask)
7300 index_mask |= (1 << entry);
7307 static bool has_edp_a(struct drm_device *dev)
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7311 if (!IS_MOBILE(dev))
7314 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7318 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7324 static void intel_setup_outputs(struct drm_device *dev)
7326 struct drm_i915_private *dev_priv = dev->dev_private;
7327 struct intel_encoder *encoder;
7328 bool dpd_is_edp = false;
7329 bool has_lvds = false;
7331 if (IS_MOBILE(dev) && !IS_I830(dev))
7332 has_lvds = intel_lvds_init(dev);
7333 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7334 /* disable the panel fitter on everything but LVDS */
7335 I915_WRITE(PFIT_CONTROL, 0);
7338 if (HAS_PCH_SPLIT(dev)) {
7339 dpd_is_edp = intel_dpd_is_edp(dev);
7342 intel_dp_init(dev, DP_A);
7344 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7345 intel_dp_init(dev, PCH_DP_D);
7348 intel_crt_init(dev);
7350 if (HAS_PCH_SPLIT(dev)) {
7353 if (I915_READ(HDMIB) & PORT_DETECTED) {
7354 /* PCH SDVOB multiplex with HDMIB */
7355 found = intel_sdvo_init(dev, PCH_SDVOB);
7357 intel_hdmi_init(dev, HDMIB);
7358 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7359 intel_dp_init(dev, PCH_DP_B);
7362 if (I915_READ(HDMIC) & PORT_DETECTED)
7363 intel_hdmi_init(dev, HDMIC);
7365 if (I915_READ(HDMID) & PORT_DETECTED)
7366 intel_hdmi_init(dev, HDMID);
7368 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7369 intel_dp_init(dev, PCH_DP_C);
7371 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7372 intel_dp_init(dev, PCH_DP_D);
7374 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7377 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7378 DRM_DEBUG_KMS("probing SDVOB\n");
7379 found = intel_sdvo_init(dev, SDVOB);
7380 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7381 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7382 intel_hdmi_init(dev, SDVOB);
7385 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7386 DRM_DEBUG_KMS("probing DP_B\n");
7387 intel_dp_init(dev, DP_B);
7391 /* Before G4X SDVOC doesn't have its own detect register */
7393 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7394 DRM_DEBUG_KMS("probing SDVOC\n");
7395 found = intel_sdvo_init(dev, SDVOC);
7398 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7400 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7401 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7402 intel_hdmi_init(dev, SDVOC);
7404 if (SUPPORTS_INTEGRATED_DP(dev)) {
7405 DRM_DEBUG_KMS("probing DP_C\n");
7406 intel_dp_init(dev, DP_C);
7410 if (SUPPORTS_INTEGRATED_DP(dev) &&
7411 (I915_READ(DP_D) & DP_DETECTED)) {
7412 DRM_DEBUG_KMS("probing DP_D\n");
7413 intel_dp_init(dev, DP_D);
7415 } else if (IS_GEN2(dev))
7416 intel_dvo_init(dev);
7418 if (SUPPORTS_TV(dev))
7421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7422 encoder->base.possible_crtcs = encoder->crtc_mask;
7423 encoder->base.possible_clones =
7424 intel_encoder_clones(dev, encoder->clone_mask);
7427 /* disable all the possible outputs/crtcs before entering KMS mode */
7428 drm_helper_disable_unused_functions(dev);
7430 if (HAS_PCH_SPLIT(dev))
7431 ironlake_init_pch_refclk(dev);
7434 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7436 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7438 drm_framebuffer_cleanup(fb);
7439 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7444 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7445 struct drm_file *file,
7446 unsigned int *handle)
7448 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7449 struct drm_i915_gem_object *obj = intel_fb->obj;
7451 return drm_gem_handle_create(file, &obj->base, handle);
7454 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7455 .destroy = intel_user_framebuffer_destroy,
7456 .create_handle = intel_user_framebuffer_create_handle,
7459 int intel_framebuffer_init(struct drm_device *dev,
7460 struct intel_framebuffer *intel_fb,
7461 struct drm_mode_fb_cmd *mode_cmd,
7462 struct drm_i915_gem_object *obj)
7466 if (obj->tiling_mode == I915_TILING_Y)
7469 if (mode_cmd->pitch & 63)
7472 switch (mode_cmd->bpp) {
7475 /* Only pre-ILK can handle 5:5:5 */
7476 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7487 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7489 DRM_ERROR("framebuffer init failed %d\n", ret);
7493 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7494 intel_fb->obj = obj;
7498 static struct drm_framebuffer *
7499 intel_user_framebuffer_create(struct drm_device *dev,
7500 struct drm_file *filp,
7501 struct drm_mode_fb_cmd *mode_cmd)
7503 struct drm_i915_gem_object *obj;
7505 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7506 if (&obj->base == NULL)
7507 return ERR_PTR(-ENOENT);
7509 return intel_framebuffer_create(dev, mode_cmd, obj);
7512 static const struct drm_mode_config_funcs intel_mode_funcs = {
7513 .fb_create = intel_user_framebuffer_create,
7514 .output_poll_changed = intel_fb_output_poll_changed,
7517 static struct drm_i915_gem_object *
7518 intel_alloc_context_page(struct drm_device *dev)
7520 struct drm_i915_gem_object *ctx;
7523 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7525 ctx = i915_gem_alloc_object(dev, 4096);
7527 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7531 ret = i915_gem_object_pin(ctx, 4096, true);
7533 DRM_ERROR("failed to pin power context: %d\n", ret);
7537 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7539 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7546 i915_gem_object_unpin(ctx);
7548 drm_gem_object_unreference(&ctx->base);
7549 mutex_unlock(&dev->struct_mutex);
7553 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7555 struct drm_i915_private *dev_priv = dev->dev_private;
7558 rgvswctl = I915_READ16(MEMSWCTL);
7559 if (rgvswctl & MEMCTL_CMD_STS) {
7560 DRM_DEBUG("gpu busy, RCS change rejected\n");
7561 return false; /* still busy with another command */
7564 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7565 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7566 I915_WRITE16(MEMSWCTL, rgvswctl);
7567 POSTING_READ16(MEMSWCTL);
7569 rgvswctl |= MEMCTL_CMD_STS;
7570 I915_WRITE16(MEMSWCTL, rgvswctl);
7575 void ironlake_enable_drps(struct drm_device *dev)
7577 struct drm_i915_private *dev_priv = dev->dev_private;
7578 u32 rgvmodectl = I915_READ(MEMMODECTL);
7579 u8 fmax, fmin, fstart, vstart;
7581 /* Enable temp reporting */
7582 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7583 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7585 /* 100ms RC evaluation intervals */
7586 I915_WRITE(RCUPEI, 100000);
7587 I915_WRITE(RCDNEI, 100000);
7589 /* Set max/min thresholds to 90ms and 80ms respectively */
7590 I915_WRITE(RCBMAXAVG, 90000);
7591 I915_WRITE(RCBMINAVG, 80000);
7593 I915_WRITE(MEMIHYST, 1);
7595 /* Set up min, max, and cur for interrupt handling */
7596 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7597 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7598 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7599 MEMMODE_FSTART_SHIFT;
7601 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7604 dev_priv->fmax = fmax; /* IPS callback will increase this */
7605 dev_priv->fstart = fstart;
7607 dev_priv->max_delay = fstart;
7608 dev_priv->min_delay = fmin;
7609 dev_priv->cur_delay = fstart;
7611 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7612 fmax, fmin, fstart);
7614 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7617 * Interrupts will be enabled in ironlake_irq_postinstall
7620 I915_WRITE(VIDSTART, vstart);
7621 POSTING_READ(VIDSTART);
7623 rgvmodectl |= MEMMODE_SWMODE_EN;
7624 I915_WRITE(MEMMODECTL, rgvmodectl);
7626 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7627 DRM_ERROR("stuck trying to change perf mode\n");
7630 ironlake_set_drps(dev, fstart);
7632 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7634 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7635 dev_priv->last_count2 = I915_READ(0x112f4);
7636 getrawmonotonic(&dev_priv->last_time2);
7639 void ironlake_disable_drps(struct drm_device *dev)
7641 struct drm_i915_private *dev_priv = dev->dev_private;
7642 u16 rgvswctl = I915_READ16(MEMSWCTL);
7644 /* Ack interrupts, disable EFC interrupt */
7645 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7646 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7647 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7648 I915_WRITE(DEIIR, DE_PCU_EVENT);
7649 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7651 /* Go back to the starting frequency */
7652 ironlake_set_drps(dev, dev_priv->fstart);
7654 rgvswctl |= MEMCTL_CMD_STS;
7655 I915_WRITE(MEMSWCTL, rgvswctl);
7660 void gen6_set_rps(struct drm_device *dev, u8 val)
7662 struct drm_i915_private *dev_priv = dev->dev_private;
7665 swreq = (val & 0x3ff) << 25;
7666 I915_WRITE(GEN6_RPNSWREQ, swreq);
7669 void gen6_disable_rps(struct drm_device *dev)
7671 struct drm_i915_private *dev_priv = dev->dev_private;
7673 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7674 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7675 I915_WRITE(GEN6_PMIER, 0);
7676 /* Complete PM interrupt masking here doesn't race with the rps work
7677 * item again unmasking PM interrupts because that is using a different
7678 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7679 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7681 spin_lock_irq(&dev_priv->rps_lock);
7682 dev_priv->pm_iir = 0;
7683 spin_unlock_irq(&dev_priv->rps_lock);
7685 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7688 static unsigned long intel_pxfreq(u32 vidfreq)
7691 int div = (vidfreq & 0x3f0000) >> 16;
7692 int post = (vidfreq & 0x3000) >> 12;
7693 int pre = (vidfreq & 0x7);
7698 freq = ((div * 133333) / ((1<<post) * pre));
7703 void intel_init_emon(struct drm_device *dev)
7705 struct drm_i915_private *dev_priv = dev->dev_private;
7710 /* Disable to program */
7714 /* Program energy weights for various events */
7715 I915_WRITE(SDEW, 0x15040d00);
7716 I915_WRITE(CSIEW0, 0x007f0000);
7717 I915_WRITE(CSIEW1, 0x1e220004);
7718 I915_WRITE(CSIEW2, 0x04000004);
7720 for (i = 0; i < 5; i++)
7721 I915_WRITE(PEW + (i * 4), 0);
7722 for (i = 0; i < 3; i++)
7723 I915_WRITE(DEW + (i * 4), 0);
7725 /* Program P-state weights to account for frequency power adjustment */
7726 for (i = 0; i < 16; i++) {
7727 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7728 unsigned long freq = intel_pxfreq(pxvidfreq);
7729 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7734 val *= (freq / 1000);
7736 val /= (127*127*900);
7738 DRM_ERROR("bad pxval: %ld\n", val);
7741 /* Render standby states get 0 weight */
7745 for (i = 0; i < 4; i++) {
7746 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7747 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7748 I915_WRITE(PXW + (i * 4), val);
7751 /* Adjust magic regs to magic values (more experimental results) */
7752 I915_WRITE(OGW0, 0);
7753 I915_WRITE(OGW1, 0);
7754 I915_WRITE(EG0, 0x00007f00);
7755 I915_WRITE(EG1, 0x0000000e);
7756 I915_WRITE(EG2, 0x000e0000);
7757 I915_WRITE(EG3, 0x68000300);
7758 I915_WRITE(EG4, 0x42000000);
7759 I915_WRITE(EG5, 0x00140031);
7763 for (i = 0; i < 8; i++)
7764 I915_WRITE(PXWL + (i * 4), 0);
7766 /* Enable PMON + select events */
7767 I915_WRITE(ECR, 0x80000019);
7769 lcfuse = I915_READ(LCFUSE02);
7771 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7774 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7776 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7777 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7778 u32 pcu_mbox, rc6_mask = 0;
7779 int cur_freq, min_freq, max_freq;
7782 /* Here begins a magic sequence of register writes to enable
7783 * auto-downclocking.
7785 * Perhaps there might be some value in exposing these to
7788 I915_WRITE(GEN6_RC_STATE, 0);
7789 mutex_lock(&dev_priv->dev->struct_mutex);
7790 gen6_gt_force_wake_get(dev_priv);
7792 /* disable the counters and set deterministic thresholds */
7793 I915_WRITE(GEN6_RC_CONTROL, 0);
7795 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7796 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7797 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7798 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7799 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7801 for (i = 0; i < I915_NUM_RINGS; i++)
7802 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7804 I915_WRITE(GEN6_RC_SLEEP, 0);
7805 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7806 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7807 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7808 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7810 if (i915_enable_rc6)
7811 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7812 GEN6_RC_CTL_RC6_ENABLE;
7814 I915_WRITE(GEN6_RC_CONTROL,
7816 GEN6_RC_CTL_EI_MODE(1) |
7817 GEN6_RC_CTL_HW_ENABLE);
7819 I915_WRITE(GEN6_RPNSWREQ,
7820 GEN6_FREQUENCY(10) |
7822 GEN6_AGGRESSIVE_TURBO);
7823 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7824 GEN6_FREQUENCY(12));
7826 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7827 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7830 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7831 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7832 I915_WRITE(GEN6_RP_UP_EI, 100000);
7833 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7834 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7835 I915_WRITE(GEN6_RP_CONTROL,
7836 GEN6_RP_MEDIA_TURBO |
7837 GEN6_RP_USE_NORMAL_FREQ |
7838 GEN6_RP_MEDIA_IS_GFX |
7840 GEN6_RP_UP_BUSY_AVG |
7841 GEN6_RP_DOWN_IDLE_CONT);
7843 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7845 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7847 I915_WRITE(GEN6_PCODE_DATA, 0);
7848 I915_WRITE(GEN6_PCODE_MAILBOX,
7850 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7851 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7853 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7855 min_freq = (rp_state_cap & 0xff0000) >> 16;
7856 max_freq = rp_state_cap & 0xff;
7857 cur_freq = (gt_perf_status & 0xff00) >> 8;
7859 /* Check for overclock support */
7860 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7862 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7863 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7864 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7865 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7867 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7868 if (pcu_mbox & (1<<31)) { /* OC supported */
7869 max_freq = pcu_mbox & 0xff;
7870 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7873 /* In units of 100MHz */
7874 dev_priv->max_delay = max_freq;
7875 dev_priv->min_delay = min_freq;
7876 dev_priv->cur_delay = cur_freq;
7878 /* requires MSI enabled */
7879 I915_WRITE(GEN6_PMIER,
7880 GEN6_PM_MBOX_EVENT |
7881 GEN6_PM_THERMAL_EVENT |
7882 GEN6_PM_RP_DOWN_TIMEOUT |
7883 GEN6_PM_RP_UP_THRESHOLD |
7884 GEN6_PM_RP_DOWN_THRESHOLD |
7885 GEN6_PM_RP_UP_EI_EXPIRED |
7886 GEN6_PM_RP_DOWN_EI_EXPIRED);
7887 spin_lock_irq(&dev_priv->rps_lock);
7888 WARN_ON(dev_priv->pm_iir != 0);
7889 I915_WRITE(GEN6_PMIMR, 0);
7890 spin_unlock_irq(&dev_priv->rps_lock);
7891 /* enable all PM interrupts */
7892 I915_WRITE(GEN6_PMINTRMSK, 0);
7894 gen6_gt_force_wake_put(dev_priv);
7895 mutex_unlock(&dev_priv->dev->struct_mutex);
7898 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7901 int gpu_freq, ia_freq, max_ia_freq;
7902 int scaling_factor = 180;
7904 max_ia_freq = cpufreq_quick_get_max(0);
7906 * Default to measured freq if none found, PCU will ensure we don't go
7910 max_ia_freq = tsc_khz;
7912 /* Convert from kHz to MHz */
7913 max_ia_freq /= 1000;
7915 mutex_lock(&dev_priv->dev->struct_mutex);
7918 * For each potential GPU frequency, load a ring frequency we'd like
7919 * to use for memory access. We do this by specifying the IA frequency
7920 * the PCU should use as a reference to determine the ring frequency.
7922 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7924 int diff = dev_priv->max_delay - gpu_freq;
7927 * For GPU frequencies less than 750MHz, just use the lowest
7930 if (gpu_freq < min_freq)
7933 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7934 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7936 I915_WRITE(GEN6_PCODE_DATA,
7937 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7939 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7940 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7941 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7942 GEN6_PCODE_READY) == 0, 10)) {
7943 DRM_ERROR("pcode write of freq table timed out\n");
7948 mutex_unlock(&dev_priv->dev->struct_mutex);
7951 static void ironlake_init_clock_gating(struct drm_device *dev)
7953 struct drm_i915_private *dev_priv = dev->dev_private;
7954 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7956 /* Required for FBC */
7957 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7958 DPFCRUNIT_CLOCK_GATE_DISABLE |
7959 DPFDUNIT_CLOCK_GATE_DISABLE;
7960 /* Required for CxSR */
7961 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7963 I915_WRITE(PCH_3DCGDIS0,
7964 MARIUNIT_CLOCK_GATE_DISABLE |
7965 SVSMUNIT_CLOCK_GATE_DISABLE);
7966 I915_WRITE(PCH_3DCGDIS1,
7967 VFMUNIT_CLOCK_GATE_DISABLE);
7969 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7972 * According to the spec the following bits should be set in
7973 * order to enable memory self-refresh
7974 * The bit 22/21 of 0x42004
7975 * The bit 5 of 0x42020
7976 * The bit 15 of 0x45000
7978 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7979 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7980 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7981 I915_WRITE(ILK_DSPCLK_GATE,
7982 (I915_READ(ILK_DSPCLK_GATE) |
7983 ILK_DPARB_CLK_GATE));
7984 I915_WRITE(DISP_ARB_CTL,
7985 (I915_READ(DISP_ARB_CTL) |
7987 I915_WRITE(WM3_LP_ILK, 0);
7988 I915_WRITE(WM2_LP_ILK, 0);
7989 I915_WRITE(WM1_LP_ILK, 0);
7992 * Based on the document from hardware guys the following bits
7993 * should be set unconditionally in order to enable FBC.
7994 * The bit 22 of 0x42000
7995 * The bit 22 of 0x42004
7996 * The bit 7,8,9 of 0x42020.
7998 if (IS_IRONLAKE_M(dev)) {
7999 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8000 I915_READ(ILK_DISPLAY_CHICKEN1) |
8002 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8003 I915_READ(ILK_DISPLAY_CHICKEN2) |
8005 I915_WRITE(ILK_DSPCLK_GATE,
8006 I915_READ(ILK_DSPCLK_GATE) |
8012 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8013 I915_READ(ILK_DISPLAY_CHICKEN2) |
8014 ILK_ELPIN_409_SELECT);
8015 I915_WRITE(_3D_CHICKEN2,
8016 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8017 _3D_CHICKEN2_WM_READ_PIPELINED);
8020 static void gen6_init_clock_gating(struct drm_device *dev)
8022 struct drm_i915_private *dev_priv = dev->dev_private;
8024 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8026 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8028 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8029 I915_READ(ILK_DISPLAY_CHICKEN2) |
8030 ILK_ELPIN_409_SELECT);
8032 I915_WRITE(WM3_LP_ILK, 0);
8033 I915_WRITE(WM2_LP_ILK, 0);
8034 I915_WRITE(WM1_LP_ILK, 0);
8037 * According to the spec the following bits should be
8038 * set in order to enable memory self-refresh and fbc:
8039 * The bit21 and bit22 of 0x42000
8040 * The bit21 and bit22 of 0x42004
8041 * The bit5 and bit7 of 0x42020
8042 * The bit14 of 0x70180
8043 * The bit14 of 0x71180
8045 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8046 I915_READ(ILK_DISPLAY_CHICKEN1) |
8047 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8048 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8049 I915_READ(ILK_DISPLAY_CHICKEN2) |
8050 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8051 I915_WRITE(ILK_DSPCLK_GATE,
8052 I915_READ(ILK_DSPCLK_GATE) |
8053 ILK_DPARB_CLK_GATE |
8056 for_each_pipe(pipe) {
8057 I915_WRITE(DSPCNTR(pipe),
8058 I915_READ(DSPCNTR(pipe)) |
8059 DISPPLANE_TRICKLE_FEED_DISABLE);
8060 intel_flush_display_plane(dev_priv, pipe);
8064 static void ivybridge_init_clock_gating(struct drm_device *dev)
8066 struct drm_i915_private *dev_priv = dev->dev_private;
8068 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8070 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8072 I915_WRITE(WM3_LP_ILK, 0);
8073 I915_WRITE(WM2_LP_ILK, 0);
8074 I915_WRITE(WM1_LP_ILK, 0);
8076 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8078 for_each_pipe(pipe) {
8079 I915_WRITE(DSPCNTR(pipe),
8080 I915_READ(DSPCNTR(pipe)) |
8081 DISPPLANE_TRICKLE_FEED_DISABLE);
8082 intel_flush_display_plane(dev_priv, pipe);
8086 static void g4x_init_clock_gating(struct drm_device *dev)
8088 struct drm_i915_private *dev_priv = dev->dev_private;
8089 uint32_t dspclk_gate;
8091 I915_WRITE(RENCLK_GATE_D1, 0);
8092 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8093 GS_UNIT_CLOCK_GATE_DISABLE |
8094 CL_UNIT_CLOCK_GATE_DISABLE);
8095 I915_WRITE(RAMCLK_GATE_D, 0);
8096 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8097 OVRUNIT_CLOCK_GATE_DISABLE |
8098 OVCUNIT_CLOCK_GATE_DISABLE;
8100 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8101 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8104 static void crestline_init_clock_gating(struct drm_device *dev)
8106 struct drm_i915_private *dev_priv = dev->dev_private;
8108 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8109 I915_WRITE(RENCLK_GATE_D2, 0);
8110 I915_WRITE(DSPCLK_GATE_D, 0);
8111 I915_WRITE(RAMCLK_GATE_D, 0);
8112 I915_WRITE16(DEUC, 0);
8115 static void broadwater_init_clock_gating(struct drm_device *dev)
8117 struct drm_i915_private *dev_priv = dev->dev_private;
8119 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8120 I965_RCC_CLOCK_GATE_DISABLE |
8121 I965_RCPB_CLOCK_GATE_DISABLE |
8122 I965_ISC_CLOCK_GATE_DISABLE |
8123 I965_FBC_CLOCK_GATE_DISABLE);
8124 I915_WRITE(RENCLK_GATE_D2, 0);
8127 static void gen3_init_clock_gating(struct drm_device *dev)
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8130 u32 dstate = I915_READ(D_STATE);
8132 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8133 DSTATE_DOT_CLOCK_GATING;
8134 I915_WRITE(D_STATE, dstate);
8137 static void i85x_init_clock_gating(struct drm_device *dev)
8139 struct drm_i915_private *dev_priv = dev->dev_private;
8141 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8144 static void i830_init_clock_gating(struct drm_device *dev)
8146 struct drm_i915_private *dev_priv = dev->dev_private;
8148 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8151 static void ibx_init_clock_gating(struct drm_device *dev)
8153 struct drm_i915_private *dev_priv = dev->dev_private;
8156 * On Ibex Peak and Cougar Point, we need to disable clock
8157 * gating for the panel power sequencer or it will fail to
8158 * start up when no ports are active.
8160 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8163 static void cpt_init_clock_gating(struct drm_device *dev)
8165 struct drm_i915_private *dev_priv = dev->dev_private;
8169 * On Ibex Peak and Cougar Point, we need to disable clock
8170 * gating for the panel power sequencer or it will fail to
8171 * start up when no ports are active.
8173 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8174 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8175 DPLS_EDP_PPS_FIX_DIS);
8176 /* Without this, mode sets may fail silently on FDI */
8178 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8181 static void ironlake_teardown_rc6(struct drm_device *dev)
8183 struct drm_i915_private *dev_priv = dev->dev_private;
8185 if (dev_priv->renderctx) {
8186 i915_gem_object_unpin(dev_priv->renderctx);
8187 drm_gem_object_unreference(&dev_priv->renderctx->base);
8188 dev_priv->renderctx = NULL;
8191 if (dev_priv->pwrctx) {
8192 i915_gem_object_unpin(dev_priv->pwrctx);
8193 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8194 dev_priv->pwrctx = NULL;
8198 static void ironlake_disable_rc6(struct drm_device *dev)
8200 struct drm_i915_private *dev_priv = dev->dev_private;
8202 if (I915_READ(PWRCTXA)) {
8203 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8204 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8205 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8208 I915_WRITE(PWRCTXA, 0);
8209 POSTING_READ(PWRCTXA);
8211 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8212 POSTING_READ(RSTDBYCTL);
8215 ironlake_teardown_rc6(dev);
8218 static int ironlake_setup_rc6(struct drm_device *dev)
8220 struct drm_i915_private *dev_priv = dev->dev_private;
8222 if (dev_priv->renderctx == NULL)
8223 dev_priv->renderctx = intel_alloc_context_page(dev);
8224 if (!dev_priv->renderctx)
8227 if (dev_priv->pwrctx == NULL)
8228 dev_priv->pwrctx = intel_alloc_context_page(dev);
8229 if (!dev_priv->pwrctx) {
8230 ironlake_teardown_rc6(dev);
8237 void ironlake_enable_rc6(struct drm_device *dev)
8239 struct drm_i915_private *dev_priv = dev->dev_private;
8242 /* rc6 disabled by default due to repeated reports of hanging during
8245 if (!i915_enable_rc6)
8248 mutex_lock(&dev->struct_mutex);
8249 ret = ironlake_setup_rc6(dev);
8251 mutex_unlock(&dev->struct_mutex);
8256 * GPU can automatically power down the render unit if given a page
8259 ret = BEGIN_LP_RING(6);
8261 ironlake_teardown_rc6(dev);
8262 mutex_unlock(&dev->struct_mutex);
8266 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8267 OUT_RING(MI_SET_CONTEXT);
8268 OUT_RING(dev_priv->renderctx->gtt_offset |
8270 MI_SAVE_EXT_STATE_EN |
8271 MI_RESTORE_EXT_STATE_EN |
8272 MI_RESTORE_INHIBIT);
8273 OUT_RING(MI_SUSPEND_FLUSH);
8279 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8280 * does an implicit flush, combined with MI_FLUSH above, it should be
8281 * safe to assume that renderctx is valid
8283 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8285 DRM_ERROR("failed to enable ironlake power power savings\n");
8286 ironlake_teardown_rc6(dev);
8287 mutex_unlock(&dev->struct_mutex);
8291 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8292 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8293 mutex_unlock(&dev->struct_mutex);
8296 void intel_init_clock_gating(struct drm_device *dev)
8298 struct drm_i915_private *dev_priv = dev->dev_private;
8300 dev_priv->display.init_clock_gating(dev);
8302 if (dev_priv->display.init_pch_clock_gating)
8303 dev_priv->display.init_pch_clock_gating(dev);
8306 /* Set up chip specific display functions */
8307 static void intel_init_display(struct drm_device *dev)
8309 struct drm_i915_private *dev_priv = dev->dev_private;
8311 /* We always want a DPMS function */
8312 if (HAS_PCH_SPLIT(dev)) {
8313 dev_priv->display.dpms = ironlake_crtc_dpms;
8314 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8315 dev_priv->display.update_plane = ironlake_update_plane;
8317 dev_priv->display.dpms = i9xx_crtc_dpms;
8318 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8319 dev_priv->display.update_plane = i9xx_update_plane;
8322 if (I915_HAS_FBC(dev)) {
8323 if (HAS_PCH_SPLIT(dev)) {
8324 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8325 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8326 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8327 } else if (IS_GM45(dev)) {
8328 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8329 dev_priv->display.enable_fbc = g4x_enable_fbc;
8330 dev_priv->display.disable_fbc = g4x_disable_fbc;
8331 } else if (IS_CRESTLINE(dev)) {
8332 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8333 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8334 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8336 /* 855GM needs testing */
8339 /* Returns the core display clock speed */
8340 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8341 dev_priv->display.get_display_clock_speed =
8342 i945_get_display_clock_speed;
8343 else if (IS_I915G(dev))
8344 dev_priv->display.get_display_clock_speed =
8345 i915_get_display_clock_speed;
8346 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8347 dev_priv->display.get_display_clock_speed =
8348 i9xx_misc_get_display_clock_speed;
8349 else if (IS_I915GM(dev))
8350 dev_priv->display.get_display_clock_speed =
8351 i915gm_get_display_clock_speed;
8352 else if (IS_I865G(dev))
8353 dev_priv->display.get_display_clock_speed =
8354 i865_get_display_clock_speed;
8355 else if (IS_I85X(dev))
8356 dev_priv->display.get_display_clock_speed =
8357 i855_get_display_clock_speed;
8359 dev_priv->display.get_display_clock_speed =
8360 i830_get_display_clock_speed;
8362 /* For FIFO watermark updates */
8363 if (HAS_PCH_SPLIT(dev)) {
8364 if (HAS_PCH_IBX(dev))
8365 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8366 else if (HAS_PCH_CPT(dev))
8367 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8370 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8371 dev_priv->display.update_wm = ironlake_update_wm;
8373 DRM_DEBUG_KMS("Failed to get proper latency. "
8375 dev_priv->display.update_wm = NULL;
8377 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8378 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8379 dev_priv->display.write_eld = ironlake_write_eld;
8380 } else if (IS_GEN6(dev)) {
8381 if (SNB_READ_WM0_LATENCY()) {
8382 dev_priv->display.update_wm = sandybridge_update_wm;
8384 DRM_DEBUG_KMS("Failed to read display plane latency. "
8386 dev_priv->display.update_wm = NULL;
8388 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8389 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8390 dev_priv->display.write_eld = ironlake_write_eld;
8391 } else if (IS_IVYBRIDGE(dev)) {
8392 /* FIXME: detect B0+ stepping and use auto training */
8393 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8394 if (SNB_READ_WM0_LATENCY()) {
8395 dev_priv->display.update_wm = sandybridge_update_wm;
8397 DRM_DEBUG_KMS("Failed to read display plane latency. "
8399 dev_priv->display.update_wm = NULL;
8401 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8402 dev_priv->display.write_eld = ironlake_write_eld;
8404 dev_priv->display.update_wm = NULL;
8405 } else if (IS_PINEVIEW(dev)) {
8406 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8409 dev_priv->mem_freq)) {
8410 DRM_INFO("failed to find known CxSR latency "
8411 "(found ddr%s fsb freq %d, mem freq %d), "
8413 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8414 dev_priv->fsb_freq, dev_priv->mem_freq);
8415 /* Disable CxSR and never update its watermark again */
8416 pineview_disable_cxsr(dev);
8417 dev_priv->display.update_wm = NULL;
8419 dev_priv->display.update_wm = pineview_update_wm;
8420 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8421 } else if (IS_G4X(dev)) {
8422 dev_priv->display.write_eld = g4x_write_eld;
8423 dev_priv->display.update_wm = g4x_update_wm;
8424 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8425 } else if (IS_GEN4(dev)) {
8426 dev_priv->display.update_wm = i965_update_wm;
8427 if (IS_CRESTLINE(dev))
8428 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8429 else if (IS_BROADWATER(dev))
8430 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8431 } else if (IS_GEN3(dev)) {
8432 dev_priv->display.update_wm = i9xx_update_wm;
8433 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8434 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8435 } else if (IS_I865G(dev)) {
8436 dev_priv->display.update_wm = i830_update_wm;
8437 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8438 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8439 } else if (IS_I85X(dev)) {
8440 dev_priv->display.update_wm = i9xx_update_wm;
8441 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8442 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8444 dev_priv->display.update_wm = i830_update_wm;
8445 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8447 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8449 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8452 /* Default just returns -ENODEV to indicate unsupported */
8453 dev_priv->display.queue_flip = intel_default_queue_flip;
8455 switch (INTEL_INFO(dev)->gen) {
8457 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8461 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8466 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8470 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8473 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8479 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8480 * resume, or other times. This quirk makes sure that's the case for
8483 static void quirk_pipea_force(struct drm_device *dev)
8485 struct drm_i915_private *dev_priv = dev->dev_private;
8487 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8488 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8492 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8494 static void quirk_ssc_force_disable(struct drm_device *dev)
8496 struct drm_i915_private *dev_priv = dev->dev_private;
8497 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8500 struct intel_quirk {
8502 int subsystem_vendor;
8503 int subsystem_device;
8504 void (*hook)(struct drm_device *dev);
8507 struct intel_quirk intel_quirks[] = {
8508 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8509 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8510 /* HP Mini needs pipe A force quirk (LP: #322104) */
8511 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8513 /* Thinkpad R31 needs pipe A force quirk */
8514 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8515 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8516 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8518 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8519 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8520 /* ThinkPad X40 needs pipe A force quirk */
8522 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8523 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8525 /* 855 & before need to leave pipe A & dpll A up */
8526 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8527 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8529 /* Lenovo U160 cannot use SSC on LVDS */
8530 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8532 /* Sony Vaio Y cannot use SSC on LVDS */
8533 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8536 static void intel_init_quirks(struct drm_device *dev)
8538 struct pci_dev *d = dev->pdev;
8541 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8542 struct intel_quirk *q = &intel_quirks[i];
8544 if (d->device == q->device &&
8545 (d->subsystem_vendor == q->subsystem_vendor ||
8546 q->subsystem_vendor == PCI_ANY_ID) &&
8547 (d->subsystem_device == q->subsystem_device ||
8548 q->subsystem_device == PCI_ANY_ID))
8553 /* Disable the VGA plane that we never use */
8554 static void i915_disable_vga(struct drm_device *dev)
8556 struct drm_i915_private *dev_priv = dev->dev_private;
8560 if (HAS_PCH_SPLIT(dev))
8561 vga_reg = CPU_VGACNTRL;
8565 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8566 outb(1, VGA_SR_INDEX);
8567 sr1 = inb(VGA_SR_DATA);
8568 outb(sr1 | 1<<5, VGA_SR_DATA);
8569 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8572 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8573 POSTING_READ(vga_reg);
8576 void intel_modeset_init(struct drm_device *dev)
8578 struct drm_i915_private *dev_priv = dev->dev_private;
8581 drm_mode_config_init(dev);
8583 dev->mode_config.min_width = 0;
8584 dev->mode_config.min_height = 0;
8586 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8588 intel_init_quirks(dev);
8590 intel_init_display(dev);
8593 dev->mode_config.max_width = 2048;
8594 dev->mode_config.max_height = 2048;
8595 } else if (IS_GEN3(dev)) {
8596 dev->mode_config.max_width = 4096;
8597 dev->mode_config.max_height = 4096;
8599 dev->mode_config.max_width = 8192;
8600 dev->mode_config.max_height = 8192;
8602 dev->mode_config.fb_base = dev->agp->base;
8604 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8605 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8607 for (i = 0; i < dev_priv->num_pipe; i++) {
8608 intel_crtc_init(dev, i);
8611 /* Just disable it once at startup */
8612 i915_disable_vga(dev);
8613 intel_setup_outputs(dev);
8615 intel_init_clock_gating(dev);
8617 if (IS_IRONLAKE_M(dev)) {
8618 ironlake_enable_drps(dev);
8619 intel_init_emon(dev);
8622 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8623 gen6_enable_rps(dev_priv);
8624 gen6_update_ring_freq(dev_priv);
8627 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8628 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8629 (unsigned long)dev);
8632 void intel_modeset_gem_init(struct drm_device *dev)
8634 if (IS_IRONLAKE_M(dev))
8635 ironlake_enable_rc6(dev);
8637 intel_setup_overlay(dev);
8640 void intel_modeset_cleanup(struct drm_device *dev)
8642 struct drm_i915_private *dev_priv = dev->dev_private;
8643 struct drm_crtc *crtc;
8644 struct intel_crtc *intel_crtc;
8646 drm_kms_helper_poll_fini(dev);
8647 mutex_lock(&dev->struct_mutex);
8649 intel_unregister_dsm_handler();
8652 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8653 /* Skip inactive CRTCs */
8657 intel_crtc = to_intel_crtc(crtc);
8658 intel_increase_pllclock(crtc);
8661 intel_disable_fbc(dev);
8663 if (IS_IRONLAKE_M(dev))
8664 ironlake_disable_drps(dev);
8665 if (IS_GEN6(dev) || IS_GEN7(dev))
8666 gen6_disable_rps(dev);
8668 if (IS_IRONLAKE_M(dev))
8669 ironlake_disable_rc6(dev);
8671 mutex_unlock(&dev->struct_mutex);
8673 /* Disable the irq before mode object teardown, for the irq might
8674 * enqueue unpin/hotplug work. */
8675 drm_irq_uninstall(dev);
8676 cancel_work_sync(&dev_priv->hotplug_work);
8677 cancel_work_sync(&dev_priv->rps_work);
8679 /* flush any delayed tasks or pending work */
8680 flush_scheduled_work();
8682 /* Shut off idle work before the crtcs get freed. */
8683 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8684 intel_crtc = to_intel_crtc(crtc);
8685 del_timer_sync(&intel_crtc->idle_timer);
8687 del_timer_sync(&dev_priv->idle_timer);
8688 cancel_work_sync(&dev_priv->idle_work);
8690 drm_mode_config_cleanup(dev);
8694 * Return which encoder is currently attached for connector.
8696 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8698 return &intel_attached_encoder(connector)->base;
8701 void intel_connector_attach_encoder(struct intel_connector *connector,
8702 struct intel_encoder *encoder)
8704 connector->encoder = encoder;
8705 drm_mode_connector_attach_encoder(&connector->base,
8710 * set vga decode state - true == enable VGA decode
8712 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8714 struct drm_i915_private *dev_priv = dev->dev_private;
8717 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8719 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8721 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8722 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8726 #ifdef CONFIG_DEBUG_FS
8727 #include <linux/seq_file.h>
8729 struct intel_display_error_state {
8730 struct intel_cursor_error_state {
8737 struct intel_pipe_error_state {
8749 struct intel_plane_error_state {
8760 struct intel_display_error_state *
8761 intel_display_capture_error_state(struct drm_device *dev)
8763 drm_i915_private_t *dev_priv = dev->dev_private;
8764 struct intel_display_error_state *error;
8767 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8771 for (i = 0; i < 2; i++) {
8772 error->cursor[i].control = I915_READ(CURCNTR(i));
8773 error->cursor[i].position = I915_READ(CURPOS(i));
8774 error->cursor[i].base = I915_READ(CURBASE(i));
8776 error->plane[i].control = I915_READ(DSPCNTR(i));
8777 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8778 error->plane[i].size = I915_READ(DSPSIZE(i));
8779 error->plane[i].pos = I915_READ(DSPPOS(i));
8780 error->plane[i].addr = I915_READ(DSPADDR(i));
8781 if (INTEL_INFO(dev)->gen >= 4) {
8782 error->plane[i].surface = I915_READ(DSPSURF(i));
8783 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8786 error->pipe[i].conf = I915_READ(PIPECONF(i));
8787 error->pipe[i].source = I915_READ(PIPESRC(i));
8788 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8789 error->pipe[i].hblank = I915_READ(HBLANK(i));
8790 error->pipe[i].hsync = I915_READ(HSYNC(i));
8791 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8792 error->pipe[i].vblank = I915_READ(VBLANK(i));
8793 error->pipe[i].vsync = I915_READ(VSYNC(i));
8800 intel_display_print_error_state(struct seq_file *m,
8801 struct drm_device *dev,
8802 struct intel_display_error_state *error)
8806 for (i = 0; i < 2; i++) {
8807 seq_printf(m, "Pipe [%d]:\n", i);
8808 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8809 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8810 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8811 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8812 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8813 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8814 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8815 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8817 seq_printf(m, "Plane [%d]:\n", i);
8818 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8819 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8820 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8821 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8822 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8823 if (INTEL_INFO(dev)->gen >= 4) {
8824 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8825 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8828 seq_printf(m, "Cursor [%d]:\n", i);
8829 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8830 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8831 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);