drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int err_most = 47;
 867         int err_min = 10000;
 868
 869         /* eDP has only 2 clock choice, no n/m/p setting */
 870         if (HAS_eDP)
 871                 return true;
 872
 873         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 874                 return intel_find_pll_igdng_dp(limit, crtc, target,
 875                                                refclk, best_clock);
 876
 877         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 878                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 879                     LVDS_CLKB_POWER_UP)
 880                         clock.p2 = limit->p2.p2_fast;
 881                 else
 882                         clock.p2 = limit->p2.p2_slow;
 883         } else {
 884                 if (target < limit->p2.dot_limit)
 885                         clock.p2 = limit->p2.p2_slow;
 886                 else
 887                         clock.p2 = limit->p2.p2_fast;
 888         }
 889
 890         memset(best_clock, 0, sizeof(*best_clock));
 891         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 892                 /* based on hardware requriment prefer smaller n to precision */
 893                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 894                         /* based on hardware requirment prefere larger m1,m2 */
 895                         for (clock.m1 = limit->m1.max;
 896                              clock.m1 >= limit->m1.min; clock.m1--) {
 897                                 for (clock.m2 = limit->m2.max;
 898                                      clock.m2 >= limit->m2.min; clock.m2--) {
 899                                         int this_err;
 900
 901                                         intel_clock(dev, refclk, &clock);
 902                                         if (!intel_PLL_is_valid(crtc, &clock))
 903                                                 continue;
 904                                         this_err = abs((10000 - (target*10000/clock.dot)));
 905                                         if (this_err < err_most) {
 906                                                 *best_clock = clock;
 907                                                 /* found on first matching */
 908                                                 goto out;
 909                                         } else if (this_err < err_min) {
 910                                                 *best_clock = clock;
 911                                                 err_min = this_err;
 912                                         }
 913                                 }
 914                         }
 915                 }
 916         }
 917 out:
 918         return true;
 919 }
 920
 921 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 922 static bool
 923 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 924                       int target, int refclk, intel_clock_t *best_clock)
 925 {
 926     intel_clock_t clock;
 927     if (target < 200000) {
 928         clock.p1 = 2;
 929         clock.p2 = 10;
 930         clock.n = 2;
 931         clock.m1 = 23;
 932         clock.m2 = 8;
 933     } else {
 934         clock.p1 = 1;
 935         clock.p2 = 10;
 936         clock.n = 1;
 937         clock.m1 = 14;
 938         clock.m2 = 2;
 939     }
 940     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 941     clock.p = (clock.p1 * clock.p2);
 942     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 943     clock.vco = 0;
 944     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 945     return true;
 946 }
 947
 948 void
 949 intel_wait_for_vblank(struct drm_device *dev)
 950 {
 951         /* Wait for 20ms, i.e. one cycle at 50hz. */
 952         mdelay(20);
 953 }
 954
 955 /* Parameters have changed, update FBC info */
 956 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 957 {
 958         struct drm_device *dev = crtc->dev;
 959         struct drm_i915_private *dev_priv = dev->dev_private;
 960         struct drm_framebuffer *fb = crtc->fb;
 961         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 962         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 964         int plane, i;
 965         u32 fbc_ctl, fbc_ctl2;
 966
 967         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 968
 969         if (fb->pitch < dev_priv->cfb_pitch)
 970                 dev_priv->cfb_pitch = fb->pitch;
 971
 972         /* FBC_CTL wants 64B units */
 973         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 974         dev_priv->cfb_fence = obj_priv->fence_reg;
 975         dev_priv->cfb_plane = intel_crtc->plane;
 976         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 977
 978         /* Clear old tags */
 979         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 980                 I915_WRITE(FBC_TAG + (i * 4), 0);
 981
 982         /* Set it up... */
 983         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 984         if (obj_priv->tiling_mode != I915_TILING_NONE)
 985                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 986         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 987         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 988
 989         /* enable it... */
 990         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 991         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 992         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 993         if (obj_priv->tiling_mode != I915_TILING_NONE)
 994                 fbc_ctl |= dev_priv->cfb_fence;
 995         I915_WRITE(FBC_CONTROL, fbc_ctl);
 996
 997         DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 998                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
 999 }
1000
1001 void i8xx_disable_fbc(struct drm_device *dev)
1002 {
1003         struct drm_i915_private *dev_priv = dev->dev_private;
1004         u32 fbc_ctl;
1005
1006         if (!I915_HAS_FBC(dev))
1007                 return;
1008
1009         /* Disable compression */
1010         fbc_ctl = I915_READ(FBC_CONTROL);
1011         fbc_ctl &= ~FBC_CTL_EN;
1012         I915_WRITE(FBC_CONTROL, fbc_ctl);
1013
1014         /* Wait for compressing bit to clear */
1015         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1016                 ; /* nothing */
1017
1018         intel_wait_for_vblank(dev);
1019
1020         DRM_DEBUG("disabled FBC\n");
1021 }
1022
1023 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1024 {
1025         struct drm_device *dev = crtc->dev;
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027
1028         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1029 }
1030
1031 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1032 {
1033         struct drm_device *dev = crtc->dev;
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         struct drm_framebuffer *fb = crtc->fb;
1036         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1037         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1039         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1040                      DPFC_CTL_PLANEB);
1041         unsigned long stall_watermark = 200;
1042         u32 dpfc_ctl;
1043
1044         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1045         dev_priv->cfb_fence = obj_priv->fence_reg;
1046         dev_priv->cfb_plane = intel_crtc->plane;
1047
1048         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1049         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1050                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1051                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1052         } else {
1053                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1054         }
1055
1056         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1057         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1058                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1059                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1060         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1061
1062         /* enable it... */
1063         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1064
1065         DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
1066 }
1067
1068 void g4x_disable_fbc(struct drm_device *dev)
1069 {
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         u32 dpfc_ctl;
1072
1073         /* Disable compression */
1074         dpfc_ctl = I915_READ(DPFC_CONTROL);
1075         dpfc_ctl &= ~DPFC_CTL_EN;
1076         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1077         intel_wait_for_vblank(dev);
1078
1079         DRM_DEBUG("disabled FBC\n");
1080 }
1081
1082 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1083 {
1084         struct drm_device *dev = crtc->dev;
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086
1087         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1088 }
1089
1090 /**
1091  * intel_update_fbc - enable/disable FBC as needed
1092  * @crtc: CRTC to point the compressor at
1093  * @mode: mode in use
1094  *
1095  * Set up the framebuffer compression hardware at mode set time.  We
1096  * enable it if possible:
1097  *   - plane A only (on pre-965)
1098  *   - no pixel mulitply/line duplication
1099  *   - no alpha buffer discard
1100  *   - no dual wide
1101  *   - framebuffer <= 2048 in width, 1536 in height
1102  *
1103  * We can't assume that any compression will take place (worst case),
1104  * so the compressed buffer has to be the same size as the uncompressed
1105  * one.  It also must reside (along with the line length buffer) in
1106  * stolen memory.
1107  *
1108  * We need to enable/disable FBC on a global basis.
1109  */
1110 static void intel_update_fbc(struct drm_crtc *crtc,
1111                              struct drm_display_mode *mode)
1112 {
1113         struct drm_device *dev = crtc->dev;
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         struct drm_framebuffer *fb = crtc->fb;
1116         struct intel_framebuffer *intel_fb;
1117         struct drm_i915_gem_object *obj_priv;
1118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1119         int plane = intel_crtc->plane;
1120
1121         if (!i915_powersave)
1122                 return;
1123
1124         if (!dev_priv->display.fbc_enabled ||
1125             !dev_priv->display.enable_fbc ||
1126             !dev_priv->display.disable_fbc)
1127                 return;
1128
1129         if (!crtc->fb)
1130                 return;
1131
1132         intel_fb = to_intel_framebuffer(fb);
1133         obj_priv = intel_fb->obj->driver_private;
1134
1135         /*
1136          * If FBC is already on, we just have to verify that we can
1137          * keep it that way...
1138          * Need to disable if:
1139          *   - changing FBC params (stride, fence, mode)
1140          *   - new fb is too large to fit in compressed buffer
1141          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1142          */
1143         if (intel_fb->obj->size > dev_priv->cfb_size) {
1144                 DRM_DEBUG("framebuffer too large, disabling compression\n");
1145                 goto out_disable;
1146         }
1147         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1148             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1149                 DRM_DEBUG("mode incompatible with compression, disabling\n");
1150                 goto out_disable;
1151         }
1152         if ((mode->hdisplay > 2048) ||
1153             (mode->vdisplay > 1536)) {
1154                 DRM_DEBUG("mode too large for compression, disabling\n");
1155                 goto out_disable;
1156         }
1157         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1158                 DRM_DEBUG("plane not 0, disabling compression\n");
1159                 goto out_disable;
1160         }
1161         if (obj_priv->tiling_mode != I915_TILING_X) {
1162                 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1163                 goto out_disable;
1164         }
1165
1166         if (dev_priv->display.fbc_enabled(crtc)) {
1167                 /* We can re-enable it in this case, but need to update pitch */
1168                 if (fb->pitch > dev_priv->cfb_pitch)
1169                         dev_priv->display.disable_fbc(dev);
1170                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1171                         dev_priv->display.disable_fbc(dev);
1172                 if (plane != dev_priv->cfb_plane)
1173                         dev_priv->display.disable_fbc(dev);
1174         }
1175
1176         if (!dev_priv->display.fbc_enabled(crtc)) {
1177                 /* Now try to turn it back on if possible */
1178                 dev_priv->display.enable_fbc(crtc, 500);
1179         }
1180
1181         return;
1182
1183 out_disable:
1184         DRM_DEBUG("unsupported config, disabling FBC\n");
1185         /* Multiple disables should be harmless */
1186         if (dev_priv->display.fbc_enabled(crtc))
1187                 dev_priv->display.disable_fbc(dev);
1188 }
1189
1190 static int
1191 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1192                     struct drm_framebuffer *old_fb)
1193 {
1194         struct drm_device *dev = crtc->dev;
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         struct drm_i915_master_private *master_priv;
1197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1198         struct intel_framebuffer *intel_fb;
1199         struct drm_i915_gem_object *obj_priv;
1200         struct drm_gem_object *obj;
1201         int pipe = intel_crtc->pipe;
1202         int plane = intel_crtc->plane;
1203         unsigned long Start, Offset;
1204         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1205         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1206         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1207         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1208         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1209         u32 dspcntr, alignment;
1210         int ret;
1211
1212         /* no fb bound */
1213         if (!crtc->fb) {
1214                 DRM_DEBUG("No FB bound\n");
1215                 return 0;
1216         }
1217
1218         switch (plane) {
1219         case 0:
1220         case 1:
1221                 break;
1222         default:
1223                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1224                 return -EINVAL;
1225         }
1226
1227         intel_fb = to_intel_framebuffer(crtc->fb);
1228         obj = intel_fb->obj;
1229         obj_priv = obj->driver_private;
1230
1231         switch (obj_priv->tiling_mode) {
1232         case I915_TILING_NONE:
1233                 alignment = 64 * 1024;
1234                 break;
1235         case I915_TILING_X:
1236                 /* pin() will align the object as required by fence */
1237                 alignment = 0;
1238                 break;
1239         case I915_TILING_Y:
1240                 /* FIXME: Is this true? */
1241                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1242                 return -EINVAL;
1243         default:
1244                 BUG();
1245         }
1246
1247         mutex_lock(&dev->struct_mutex);
1248         ret = i915_gem_object_pin(obj, alignment);
1249         if (ret != 0) {
1250                 mutex_unlock(&dev->struct_mutex);
1251                 return ret;
1252         }
1253
1254         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1255         if (ret != 0) {
1256                 i915_gem_object_unpin(obj);
1257                 mutex_unlock(&dev->struct_mutex);
1258                 return ret;
1259         }
1260
1261         /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1262          * whereas 965+ only requires a fence if using framebuffer compression.
1263          * For simplicity, we always install a fence as the cost is not that onerous.
1264          */
1265         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1266             obj_priv->tiling_mode != I915_TILING_NONE) {
1267                 ret = i915_gem_object_get_fence_reg(obj);
1268                 if (ret != 0) {
1269                         i915_gem_object_unpin(obj);
1270                         mutex_unlock(&dev->struct_mutex);
1271                         return ret;
1272                 }
1273         }
1274
1275         dspcntr = I915_READ(dspcntr_reg);
1276         /* Mask out pixel format bits in case we change it */
1277         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1278         switch (crtc->fb->bits_per_pixel) {
1279         case 8:
1280                 dspcntr |= DISPPLANE_8BPP;
1281                 break;
1282         case 16:
1283                 if (crtc->fb->depth == 15)
1284                         dspcntr |= DISPPLANE_15_16BPP;
1285                 else
1286                         dspcntr |= DISPPLANE_16BPP;
1287                 break;
1288         case 24:
1289         case 32:
1290                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1291                 break;
1292         default:
1293                 DRM_ERROR("Unknown color depth\n");
1294                 i915_gem_object_unpin(obj);
1295                 mutex_unlock(&dev->struct_mutex);
1296                 return -EINVAL;
1297         }
1298         if (IS_I965G(dev)) {
1299                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1300                         dspcntr |= DISPPLANE_TILED;
1301                 else
1302                         dspcntr &= ~DISPPLANE_TILED;
1303         }
1304
1305         if (IS_IGDNG(dev))
1306                 /* must disable */
1307                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1308
1309         I915_WRITE(dspcntr_reg, dspcntr);
1310
1311         Start = obj_priv->gtt_offset;
1312         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1313
1314         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1315         I915_WRITE(dspstride, crtc->fb->pitch);
1316         if (IS_I965G(dev)) {
1317                 I915_WRITE(dspbase, Offset);
1318                 I915_READ(dspbase);
1319                 I915_WRITE(dspsurf, Start);
1320                 I915_READ(dspsurf);
1321                 I915_WRITE(dsptileoff, (y << 16) | x);
1322         } else {
1323                 I915_WRITE(dspbase, Start + Offset);
1324                 I915_READ(dspbase);
1325         }
1326
1327         if ((IS_I965G(dev) || plane == 0))
1328                 intel_update_fbc(crtc, &crtc->mode);
1329
1330         intel_wait_for_vblank(dev);
1331
1332         if (old_fb) {
1333                 intel_fb = to_intel_framebuffer(old_fb);
1334                 obj_priv = intel_fb->obj->driver_private;
1335                 i915_gem_object_unpin(intel_fb->obj);
1336         }
1337         intel_increase_pllclock(crtc, true);
1338
1339         mutex_unlock(&dev->struct_mutex);
1340
1341         if (!dev->primary->master)
1342                 return 0;
1343
1344         master_priv = dev->primary->master->driver_priv;
1345         if (!master_priv->sarea_priv)
1346                 return 0;
1347
1348         if (pipe) {
1349                 master_priv->sarea_priv->pipeB_x = x;
1350                 master_priv->sarea_priv->pipeB_y = y;
1351         } else {
1352                 master_priv->sarea_priv->pipeA_x = x;
1353                 master_priv->sarea_priv->pipeA_y = y;
1354         }
1355
1356         return 0;
1357 }
1358
1359 /* Disable the VGA plane that we never use */
1360 static void i915_disable_vga (struct drm_device *dev)
1361 {
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         u8 sr1;
1364         u32 vga_reg;
1365
1366         if (IS_IGDNG(dev))
1367                 vga_reg = CPU_VGACNTRL;
1368         else
1369                 vga_reg = VGACNTRL;
1370
1371         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1372                 return;
1373
1374         I915_WRITE8(VGA_SR_INDEX, 1);
1375         sr1 = I915_READ8(VGA_SR_DATA);
1376         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1377         udelay(100);
1378
1379         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1380 }
1381
1382 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1383 {
1384         struct drm_device *dev = crtc->dev;
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386         u32 dpa_ctl;
1387
1388         DRM_DEBUG("\n");
1389         dpa_ctl = I915_READ(DP_A);
1390         dpa_ctl &= ~DP_PLL_ENABLE;
1391         I915_WRITE(DP_A, dpa_ctl);
1392 }
1393
1394 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1395 {
1396         struct drm_device *dev = crtc->dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         u32 dpa_ctl;
1399
1400         dpa_ctl = I915_READ(DP_A);
1401         dpa_ctl |= DP_PLL_ENABLE;
1402         I915_WRITE(DP_A, dpa_ctl);
1403         udelay(200);
1404 }
1405
1406
1407 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1408 {
1409         struct drm_device *dev = crtc->dev;
1410         struct drm_i915_private *dev_priv = dev->dev_private;
1411         u32 dpa_ctl;
1412
1413         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1414         dpa_ctl = I915_READ(DP_A);
1415         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1416
1417         if (clock < 200000) {
1418                 u32 temp;
1419                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1420                 /* workaround for 160Mhz:
1421                    1) program 0x4600c bits 15:0 = 0x8124
1422                    2) program 0x46010 bit 0 = 1
1423                    3) program 0x46034 bit 24 = 1
1424                    4) program 0x64000 bit 14 = 1
1425                    */
1426                 temp = I915_READ(0x4600c);
1427                 temp &= 0xffff0000;
1428                 I915_WRITE(0x4600c, temp | 0x8124);
1429
1430                 temp = I915_READ(0x46010);
1431                 I915_WRITE(0x46010, temp | 1);
1432
1433                 temp = I915_READ(0x46034);
1434                 I915_WRITE(0x46034, temp | (1 << 24));
1435         } else {
1436                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1437         }
1438         I915_WRITE(DP_A, dpa_ctl);
1439
1440         udelay(500);
1441 }
1442
1443 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1444 {
1445         struct drm_device *dev = crtc->dev;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1448         int pipe = intel_crtc->pipe;
1449         int plane = intel_crtc->plane;
1450         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1451         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1452         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1453         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1454         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1455         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1456         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1457         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1458         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1459         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1460         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1461         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1462         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1463         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1464         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1465         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1466         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1467         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1468         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1469         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1470         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1471         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1472         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1473         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1474         u32 temp;
1475         int tries = 5, j, n;
1476
1477         /* XXX: When our outputs are all unaware of DPMS modes other than off
1478          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1479          */
1480         switch (mode) {
1481         case DRM_MODE_DPMS_ON:
1482         case DRM_MODE_DPMS_STANDBY:
1483         case DRM_MODE_DPMS_SUSPEND:
1484                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1485                 if (HAS_eDP) {
1486                         /* enable eDP PLL */
1487                         igdng_enable_pll_edp(crtc);
1488                 } else {
1489                         /* enable PCH DPLL */
1490                         temp = I915_READ(pch_dpll_reg);
1491                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1492                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1493                                 I915_READ(pch_dpll_reg);
1494                         }
1495
1496                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1497                         temp = I915_READ(fdi_rx_reg);
1498                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1499                                         FDI_SEL_PCDCLK |
1500                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1501                         I915_READ(fdi_rx_reg);
1502                         udelay(200);
1503
1504                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1505                         temp = I915_READ(fdi_tx_reg);
1506                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1507                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1508                                 I915_READ(fdi_tx_reg);
1509                                 udelay(100);
1510                         }
1511                 }
1512
1513                 /* Enable panel fitting for LVDS */
1514                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1515                         temp = I915_READ(pf_ctl_reg);
1516                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1517
1518                         /* currently full aspect */
1519                         I915_WRITE(pf_win_pos, 0);
1520
1521                         I915_WRITE(pf_win_size,
1522                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1523                                    (dev_priv->panel_fixed_mode->vdisplay));
1524                 }
1525
1526                 /* Enable CPU pipe */
1527                 temp = I915_READ(pipeconf_reg);
1528                 if ((temp & PIPEACONF_ENABLE) == 0) {
1529                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1530                         I915_READ(pipeconf_reg);
1531                         udelay(100);
1532                 }
1533
1534                 /* configure and enable CPU plane */
1535                 temp = I915_READ(dspcntr_reg);
1536                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1537                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1538                         /* Flush the plane changes */
1539                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1540                 }
1541
1542                 if (!HAS_eDP) {
1543                         /* enable CPU FDI TX and PCH FDI RX */
1544                         temp = I915_READ(fdi_tx_reg);
1545                         temp |= FDI_TX_ENABLE;
1546                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1547                         temp &= ~FDI_LINK_TRAIN_NONE;
1548                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1549                         I915_WRITE(fdi_tx_reg, temp);
1550                         I915_READ(fdi_tx_reg);
1551
1552                         temp = I915_READ(fdi_rx_reg);
1553                         temp &= ~FDI_LINK_TRAIN_NONE;
1554                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1555                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1556                         I915_READ(fdi_rx_reg);
1557
1558                         udelay(150);
1559
1560                         /* Train FDI. */
1561                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1562                            for train result */
1563                         temp = I915_READ(fdi_rx_imr_reg);
1564                         temp &= ~FDI_RX_SYMBOL_LOCK;
1565                         temp &= ~FDI_RX_BIT_LOCK;
1566                         I915_WRITE(fdi_rx_imr_reg, temp);
1567                         I915_READ(fdi_rx_imr_reg);
1568                         udelay(150);
1569
1570                         temp = I915_READ(fdi_rx_iir_reg);
1571                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1572
1573                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1574                                 for (j = 0; j < tries; j++) {
1575                                         temp = I915_READ(fdi_rx_iir_reg);
1576                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1577                                         if (temp & FDI_RX_BIT_LOCK)
1578                                                 break;
1579                                         udelay(200);
1580                                 }
1581                                 if (j != tries)
1582                                         I915_WRITE(fdi_rx_iir_reg,
1583                                                         temp | FDI_RX_BIT_LOCK);
1584                                 else
1585                                         DRM_DEBUG("train 1 fail\n");
1586                         } else {
1587                                 I915_WRITE(fdi_rx_iir_reg,
1588                                                 temp | FDI_RX_BIT_LOCK);
1589                                 DRM_DEBUG("train 1 ok 2!\n");
1590                         }
1591                         temp = I915_READ(fdi_tx_reg);
1592                         temp &= ~FDI_LINK_TRAIN_NONE;
1593                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1594                         I915_WRITE(fdi_tx_reg, temp);
1595
1596                         temp = I915_READ(fdi_rx_reg);
1597                         temp &= ~FDI_LINK_TRAIN_NONE;
1598                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1599                         I915_WRITE(fdi_rx_reg, temp);
1600
1601                         udelay(150);
1602
1603                         temp = I915_READ(fdi_rx_iir_reg);
1604                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1605
1606                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1607                                 for (j = 0; j < tries; j++) {
1608                                         temp = I915_READ(fdi_rx_iir_reg);
1609                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1610                                         if (temp & FDI_RX_SYMBOL_LOCK)
1611                                                 break;
1612                                         udelay(200);
1613                                 }
1614                                 if (j != tries) {
1615                                         I915_WRITE(fdi_rx_iir_reg,
1616                                                         temp | FDI_RX_SYMBOL_LOCK);
1617                                         DRM_DEBUG("train 2 ok 1!\n");
1618                                 } else
1619                                         DRM_DEBUG("train 2 fail\n");
1620                         } else {
1621                                 I915_WRITE(fdi_rx_iir_reg,
1622                                                 temp | FDI_RX_SYMBOL_LOCK);
1623                                 DRM_DEBUG("train 2 ok 2!\n");
1624                         }
1625                         DRM_DEBUG("train done\n");
1626
1627                         /* set transcoder timing */
1628                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1629                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1630                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1631
1632                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1633                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1634                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1635
1636                         /* enable PCH transcoder */
1637                         temp = I915_READ(transconf_reg);
1638                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1639                         I915_READ(transconf_reg);
1640
1641                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1642                                 ;
1643
1644                         /* enable normal */
1645
1646                         temp = I915_READ(fdi_tx_reg);
1647                         temp &= ~FDI_LINK_TRAIN_NONE;
1648                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1649                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1650                         I915_READ(fdi_tx_reg);
1651
1652                         temp = I915_READ(fdi_rx_reg);
1653                         temp &= ~FDI_LINK_TRAIN_NONE;
1654                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1655                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1656                         I915_READ(fdi_rx_reg);
1657
1658                         /* wait one idle pattern time */
1659                         udelay(100);
1660
1661                 }
1662
1663                 intel_crtc_load_lut(crtc);
1664
1665         break;
1666         case DRM_MODE_DPMS_OFF:
1667                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1668
1669                 i915_disable_vga(dev);
1670
1671                 /* Disable display plane */
1672                 temp = I915_READ(dspcntr_reg);
1673                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1674                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1675                         /* Flush the plane changes */
1676                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1677                         I915_READ(dspbase_reg);
1678                 }
1679
1680                 /* disable cpu pipe, disable after all planes disabled */
1681                 temp = I915_READ(pipeconf_reg);
1682                 if ((temp & PIPEACONF_ENABLE) != 0) {
1683                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1684                         I915_READ(pipeconf_reg);
1685                         n = 0;
1686                         /* wait for cpu pipe off, pipe state */
1687                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1688                                 n++;
1689                                 if (n < 60) {
1690                                         udelay(500);
1691                                         continue;
1692                                 } else {
1693                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1694                                         break;
1695                                 }
1696                         }
1697                 } else
1698                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1699
1700                 if (HAS_eDP) {
1701                         igdng_disable_pll_edp(crtc);
1702                 }
1703
1704                 /* disable CPU FDI tx and PCH FDI rx */
1705                 temp = I915_READ(fdi_tx_reg);
1706                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1707                 I915_READ(fdi_tx_reg);
1708
1709                 temp = I915_READ(fdi_rx_reg);
1710                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1711                 I915_READ(fdi_rx_reg);
1712
1713                 udelay(100);
1714
1715                 /* still set train pattern 1 */
1716                 temp = I915_READ(fdi_tx_reg);
1717                 temp &= ~FDI_LINK_TRAIN_NONE;
1718                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1719                 I915_WRITE(fdi_tx_reg, temp);
1720
1721                 temp = I915_READ(fdi_rx_reg);
1722                 temp &= ~FDI_LINK_TRAIN_NONE;
1723                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1724                 I915_WRITE(fdi_rx_reg, temp);
1725
1726                 udelay(100);
1727
1728                 /* disable PCH transcoder */
1729                 temp = I915_READ(transconf_reg);
1730                 if ((temp & TRANS_ENABLE) != 0) {
1731                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1732                         I915_READ(transconf_reg);
1733                         n = 0;
1734                         /* wait for PCH transcoder off, transcoder state */
1735                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1736                                 n++;
1737                                 if (n < 60) {
1738                                         udelay(500);
1739                                         continue;
1740                                 } else {
1741                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1742                                         break;
1743                                 }
1744                         }
1745                 }
1746
1747                 /* disable PCH DPLL */
1748                 temp = I915_READ(pch_dpll_reg);
1749                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1750                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1751                         I915_READ(pch_dpll_reg);
1752                 }
1753
1754                 temp = I915_READ(fdi_rx_reg);
1755                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1756                         temp &= ~FDI_SEL_PCDCLK;
1757                         temp &= ~FDI_RX_PLL_ENABLE;
1758                         I915_WRITE(fdi_rx_reg, temp);
1759                         I915_READ(fdi_rx_reg);
1760                 }
1761
1762                 /* Disable CPU FDI TX PLL */
1763                 temp = I915_READ(fdi_tx_reg);
1764                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1765                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1766                         I915_READ(fdi_tx_reg);
1767                         udelay(100);
1768                 }
1769
1770                 /* Disable PF */
1771                 temp = I915_READ(pf_ctl_reg);
1772                 if ((temp & PF_ENABLE) != 0) {
1773                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1774                         I915_READ(pf_ctl_reg);
1775                 }
1776                 I915_WRITE(pf_win_size, 0);
1777
1778                 /* Wait for the clocks to turn off. */
1779                 udelay(150);
1780                 break;
1781         }
1782 }
1783
1784 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1785 {
1786         struct intel_overlay *overlay;
1787
1788         if (!enable && intel_crtc->overlay) {
1789                 overlay = intel_crtc->overlay;
1790                 mutex_lock(&overlay->dev->struct_mutex);
1791                 intel_overlay_switch_off(overlay);
1792                 mutex_unlock(&overlay->dev->struct_mutex);
1793         }
1794         /* Let userspace switch the overlay on again. In most cases userspace
1795          * has to recompute where to put it anyway. */
1796
1797         return;
1798 }
1799
1800 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1801 {
1802         struct drm_device *dev = crtc->dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1805         int pipe = intel_crtc->pipe;
1806         int plane = intel_crtc->plane;
1807         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1808         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1809         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1810         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1811         u32 temp;
1812
1813         /* XXX: When our outputs are all unaware of DPMS modes other than off
1814          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1815          */
1816         switch (mode) {
1817         case DRM_MODE_DPMS_ON:
1818         case DRM_MODE_DPMS_STANDBY:
1819         case DRM_MODE_DPMS_SUSPEND:
1820                 intel_update_watermarks(dev);
1821
1822                 /* Enable the DPLL */
1823                 temp = I915_READ(dpll_reg);
1824                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1825                         I915_WRITE(dpll_reg, temp);
1826                         I915_READ(dpll_reg);
1827                         /* Wait for the clocks to stabilize. */
1828                         udelay(150);
1829                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1830                         I915_READ(dpll_reg);
1831                         /* Wait for the clocks to stabilize. */
1832                         udelay(150);
1833                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1834                         I915_READ(dpll_reg);
1835                         /* Wait for the clocks to stabilize. */
1836                         udelay(150);
1837                 }
1838
1839                 /* Enable the pipe */
1840                 temp = I915_READ(pipeconf_reg);
1841                 if ((temp & PIPEACONF_ENABLE) == 0)
1842                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1843
1844                 /* Enable the plane */
1845                 temp = I915_READ(dspcntr_reg);
1846                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1847                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1848                         /* Flush the plane changes */
1849                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1850                 }
1851
1852                 intel_crtc_load_lut(crtc);
1853
1854                 if ((IS_I965G(dev) || plane == 0))
1855                         intel_update_fbc(crtc, &crtc->mode);
1856
1857                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1858                 intel_crtc_dpms_overlay(intel_crtc, true);
1859         break;
1860         case DRM_MODE_DPMS_OFF:
1861                 intel_update_watermarks(dev);
1862
1863                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1864                 intel_crtc_dpms_overlay(intel_crtc, false);
1865
1866                 if (dev_priv->cfb_plane == plane &&
1867                     dev_priv->display.disable_fbc)
1868                         dev_priv->display.disable_fbc(dev);
1869
1870                 /* Disable the VGA plane that we never use */
1871                 i915_disable_vga(dev);
1872
1873                 /* Disable display plane */
1874                 temp = I915_READ(dspcntr_reg);
1875                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1876                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1877                         /* Flush the plane changes */
1878                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1879                         I915_READ(dspbase_reg);
1880                 }
1881
1882                 if (!IS_I9XX(dev)) {
1883                         /* Wait for vblank for the disable to take effect */
1884                         intel_wait_for_vblank(dev);
1885                 }
1886
1887                 /* Next, disable display pipes */
1888                 temp = I915_READ(pipeconf_reg);
1889                 if ((temp & PIPEACONF_ENABLE) != 0) {
1890                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1891                         I915_READ(pipeconf_reg);
1892                 }
1893
1894                 /* Wait for vblank for the disable to take effect. */
1895                 intel_wait_for_vblank(dev);
1896
1897                 temp = I915_READ(dpll_reg);
1898                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1899                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1900                         I915_READ(dpll_reg);
1901                 }
1902
1903                 /* Wait for the clocks to turn off. */
1904                 udelay(150);
1905                 break;
1906         }
1907 }
1908
1909 /**
1910  * Sets the power management mode of the pipe and plane.
1911  *
1912  * This code should probably grow support for turning the cursor off and back
1913  * on appropriately at the same time as we're turning the pipe off/on.
1914  */
1915 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1916 {
1917         struct drm_device *dev = crtc->dev;
1918         struct drm_i915_private *dev_priv = dev->dev_private;
1919         struct drm_i915_master_private *master_priv;
1920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1921         int pipe = intel_crtc->pipe;
1922         bool enabled;
1923
1924         dev_priv->display.dpms(crtc, mode);
1925
1926         intel_crtc->dpms_mode = mode;
1927
1928         if (!dev->primary->master)
1929                 return;
1930
1931         master_priv = dev->primary->master->driver_priv;
1932         if (!master_priv->sarea_priv)
1933                 return;
1934
1935         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1936
1937         switch (pipe) {
1938         case 0:
1939                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1940                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1941                 break;
1942         case 1:
1943                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1944                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1945                 break;
1946         default:
1947                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1948                 break;
1949         }
1950 }
1951
1952 static void intel_crtc_prepare (struct drm_crtc *crtc)
1953 {
1954         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1955         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1956 }
1957
1958 static void intel_crtc_commit (struct drm_crtc *crtc)
1959 {
1960         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1961         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1962 }
1963
1964 void intel_encoder_prepare (struct drm_encoder *encoder)
1965 {
1966         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1967         /* lvds has its own version of prepare see intel_lvds_prepare */
1968         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1969 }
1970
1971 void intel_encoder_commit (struct drm_encoder *encoder)
1972 {
1973         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1974         /* lvds has its own version of commit see intel_lvds_commit */
1975         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1976 }
1977
1978 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1979                                   struct drm_display_mode *mode,
1980                                   struct drm_display_mode *adjusted_mode)
1981 {
1982         struct drm_device *dev = crtc->dev;
1983         if (IS_IGDNG(dev)) {
1984                 /* FDI link clock is fixed at 2.7G */
1985                 if (mode->clock * 3 > 27000 * 4)
1986                         return MODE_CLOCK_HIGH;
1987         }
1988         return true;
1989 }
1990
1991 static int i945_get_display_clock_speed(struct drm_device *dev)
1992 {
1993         return 400000;
1994 }
1995
1996 static int i915_get_display_clock_speed(struct drm_device *dev)
1997 {
1998         return 333000;
1999 }
2000
2001 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2002 {
2003         return 200000;
2004 }
2005
2006 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2007 {
2008         u16 gcfgc = 0;
2009
2010         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2011
2012         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2013                 return 133000;
2014         else {
2015                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2016                 case GC_DISPLAY_CLOCK_333_MHZ:
2017                         return 333000;
2018                 default:
2019                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2020                         return 190000;
2021                 }
2022         }
2023 }
2024
2025 static int i865_get_display_clock_speed(struct drm_device *dev)
2026 {
2027         return 266000;
2028 }
2029
2030 static int i855_get_display_clock_speed(struct drm_device *dev)
2031 {
2032         u16 hpllcc = 0;
2033         /* Assume that the hardware is in the high speed state.  This
2034          * should be the default.
2035          */
2036         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2037         case GC_CLOCK_133_200:
2038         case GC_CLOCK_100_200:
2039                 return 200000;
2040         case GC_CLOCK_166_250:
2041                 return 250000;
2042         case GC_CLOCK_100_133:
2043                 return 133000;
2044         }
2045
2046         /* Shouldn't happen */
2047         return 0;
2048 }
2049
2050 static int i830_get_display_clock_speed(struct drm_device *dev)
2051 {
2052         return 133000;
2053 }
2054
2055 /**
2056  * Return the pipe currently connected to the panel fitter,
2057  * or -1 if the panel fitter is not present or not in use
2058  */
2059 int intel_panel_fitter_pipe (struct drm_device *dev)
2060 {
2061         struct drm_i915_private *dev_priv = dev->dev_private;
2062         u32  pfit_control;
2063
2064         /* i830 doesn't have a panel fitter */
2065         if (IS_I830(dev))
2066                 return -1;
2067
2068         pfit_control = I915_READ(PFIT_CONTROL);
2069
2070         /* See if the panel fitter is in use */
2071         if ((pfit_control & PFIT_ENABLE) == 0)
2072                 return -1;
2073
2074         /* 965 can place panel fitter on either pipe */
2075         if (IS_I965G(dev))
2076                 return (pfit_control >> 29) & 0x3;
2077
2078         /* older chips can only use pipe 1 */
2079         return 1;
2080 }
2081
2082 struct fdi_m_n {
2083         u32        tu;
2084         u32        gmch_m;
2085         u32        gmch_n;
2086         u32        link_m;
2087         u32        link_n;
2088 };
2089
2090 static void
2091 fdi_reduce_ratio(u32 *num, u32 *den)
2092 {
2093         while (*num > 0xffffff || *den > 0xffffff) {
2094                 *num >>= 1;
2095                 *den >>= 1;
2096         }
2097 }
2098
2099 #define DATA_N 0x800000
2100 #define LINK_N 0x80000
2101
2102 static void
2103 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2104                 int pixel_clock, int link_clock,
2105                 struct fdi_m_n *m_n)
2106 {
2107         u64 temp;
2108
2109         m_n->tu = 64; /* default size */
2110
2111         temp = (u64) DATA_N * pixel_clock;
2112         temp = div_u64(temp, link_clock);
2113         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2114         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2115         m_n->gmch_n = DATA_N;
2116         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2117
2118         temp = (u64) LINK_N * pixel_clock;
2119         m_n->link_m = div_u64(temp, link_clock);
2120         m_n->link_n = LINK_N;
2121         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2122 }
2123
2124
2125 struct intel_watermark_params {
2126         unsigned long fifo_size;
2127         unsigned long max_wm;
2128         unsigned long default_wm;
2129         unsigned long guard_size;
2130         unsigned long cacheline_size;
2131 };
2132
2133 /* IGD has different values for various configs */
2134 static struct intel_watermark_params igd_display_wm = {
2135         IGD_DISPLAY_FIFO,
2136         IGD_MAX_WM,
2137         IGD_DFT_WM,
2138         IGD_GUARD_WM,
2139         IGD_FIFO_LINE_SIZE
2140 };
2141 static struct intel_watermark_params igd_display_hplloff_wm = {
2142         IGD_DISPLAY_FIFO,
2143         IGD_MAX_WM,
2144         IGD_DFT_HPLLOFF_WM,
2145         IGD_GUARD_WM,
2146         IGD_FIFO_LINE_SIZE
2147 };
2148 static struct intel_watermark_params igd_cursor_wm = {
2149         IGD_CURSOR_FIFO,
2150         IGD_CURSOR_MAX_WM,
2151         IGD_CURSOR_DFT_WM,
2152         IGD_CURSOR_GUARD_WM,
2153         IGD_FIFO_LINE_SIZE,
2154 };
2155 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2156         IGD_CURSOR_FIFO,
2157         IGD_CURSOR_MAX_WM,
2158         IGD_CURSOR_DFT_WM,
2159         IGD_CURSOR_GUARD_WM,
2160         IGD_FIFO_LINE_SIZE
2161 };
2162 static struct intel_watermark_params g4x_wm_info = {
2163         G4X_FIFO_SIZE,
2164         G4X_MAX_WM,
2165         G4X_MAX_WM,
2166         2,
2167         G4X_FIFO_LINE_SIZE,
2168 };
2169 static struct intel_watermark_params i945_wm_info = {
2170         I945_FIFO_SIZE,
2171         I915_MAX_WM,
2172         1,
2173         2,
2174         I915_FIFO_LINE_SIZE
2175 };
2176 static struct intel_watermark_params i915_wm_info = {
2177         I915_FIFO_SIZE,
2178         I915_MAX_WM,
2179         1,
2180         2,
2181         I915_FIFO_LINE_SIZE
2182 };
2183 static struct intel_watermark_params i855_wm_info = {
2184         I855GM_FIFO_SIZE,
2185         I915_MAX_WM,
2186         1,
2187         2,
2188         I830_FIFO_LINE_SIZE
2189 };
2190 static struct intel_watermark_params i830_wm_info = {
2191         I830_FIFO_SIZE,
2192         I915_MAX_WM,
2193         1,
2194         2,
2195         I830_FIFO_LINE_SIZE
2196 };
2197
2198 /**
2199  * intel_calculate_wm - calculate watermark level
2200  * @clock_in_khz: pixel clock
2201  * @wm: chip FIFO params
2202  * @pixel_size: display pixel size
2203  * @latency_ns: memory latency for the platform
2204  *
2205  * Calculate the watermark level (the level at which the display plane will
2206  * start fetching from memory again).  Each chip has a different display
2207  * FIFO size and allocation, so the caller needs to figure that out and pass
2208  * in the correct intel_watermark_params structure.
2209  *
2210  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2211  * on the pixel size.  When it reaches the watermark level, it'll start
2212  * fetching FIFO line sized based chunks from memory until the FIFO fills
2213  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2214  * will occur, and a display engine hang could result.
2215  */
2216 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2217                                         struct intel_watermark_params *wm,
2218                                         int pixel_size,
2219                                         unsigned long latency_ns)
2220 {
2221         long entries_required, wm_size;
2222
2223         /*
2224          * Note: we need to make sure we don't overflow for various clock &
2225          * latency values.
2226          * clocks go from a few thousand to several hundred thousand.
2227          * latency is usually a few thousand
2228          */
2229         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2230                 1000;
2231         entries_required /= wm->cacheline_size;
2232
2233         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2234
2235         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2236
2237         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2238
2239         /* Don't promote wm_size to unsigned... */
2240         if (wm_size > (long)wm->max_wm)
2241                 wm_size = wm->max_wm;
2242         if (wm_size <= 0)
2243                 wm_size = wm->default_wm;
2244         return wm_size;
2245 }
2246
2247 struct cxsr_latency {
2248         int is_desktop;
2249         unsigned long fsb_freq;
2250         unsigned long mem_freq;
2251         unsigned long display_sr;
2252         unsigned long display_hpll_disable;
2253         unsigned long cursor_sr;
2254         unsigned long cursor_hpll_disable;
2255 };
2256
2257 static struct cxsr_latency cxsr_latency_table[] = {
2258         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2259         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2260         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2261
2262         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2263         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2264         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2265
2266         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2267         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2268         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2269
2270         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2271         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2272         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2273
2274         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2275         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2276         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2277
2278         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2279         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2280         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2281 };
2282
2283 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2284                                                    int mem)
2285 {
2286         int i;
2287         struct cxsr_latency *latency;
2288
2289         if (fsb == 0 || mem == 0)
2290                 return NULL;
2291
2292         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2293                 latency = &cxsr_latency_table[i];
2294                 if (is_desktop == latency->is_desktop &&
2295                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2296                         return latency;
2297         }
2298
2299         DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2300
2301         return NULL;
2302 }
2303
2304 static void igd_disable_cxsr(struct drm_device *dev)
2305 {
2306         struct drm_i915_private *dev_priv = dev->dev_private;
2307         u32 reg;
2308
2309         /* deactivate cxsr */
2310         reg = I915_READ(DSPFW3);
2311         reg &= ~(IGD_SELF_REFRESH_EN);
2312         I915_WRITE(DSPFW3, reg);
2313         DRM_INFO("Big FIFO is disabled\n");
2314 }
2315
2316 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2317                             int pixel_size)
2318 {
2319         struct drm_i915_private *dev_priv = dev->dev_private;
2320         u32 reg;
2321         unsigned long wm;
2322         struct cxsr_latency *latency;
2323
2324         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2325                 dev_priv->mem_freq);
2326         if (!latency) {
2327                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2328                 igd_disable_cxsr(dev);
2329                 return;
2330         }
2331
2332         /* Display SR */
2333         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2334                                 latency->display_sr);
2335         reg = I915_READ(DSPFW1);
2336         reg &= 0x7fffff;
2337         reg |= wm << 23;
2338         I915_WRITE(DSPFW1, reg);
2339         DRM_DEBUG("DSPFW1 register is %x\n", reg);
2340
2341         /* cursor SR */
2342         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2343                                 latency->cursor_sr);
2344         reg = I915_READ(DSPFW3);
2345         reg &= ~(0x3f << 24);
2346         reg |= (wm & 0x3f) << 24;
2347         I915_WRITE(DSPFW3, reg);
2348
2349         /* Display HPLL off SR */
2350         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2351                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2352         reg = I915_READ(DSPFW3);
2353         reg &= 0xfffffe00;
2354         reg |= wm & 0x1ff;
2355         I915_WRITE(DSPFW3, reg);
2356
2357         /* cursor HPLL off SR */
2358         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2359                                 latency->cursor_hpll_disable);
2360         reg = I915_READ(DSPFW3);
2361         reg &= ~(0x3f << 16);
2362         reg |= (wm & 0x3f) << 16;
2363         I915_WRITE(DSPFW3, reg);
2364         DRM_DEBUG("DSPFW3 register is %x\n", reg);
2365
2366         /* activate cxsr */
2367         reg = I915_READ(DSPFW3);
2368         reg |= IGD_SELF_REFRESH_EN;
2369         I915_WRITE(DSPFW3, reg);
2370
2371         DRM_INFO("Big FIFO is enabled\n");
2372
2373         return;
2374 }
2375
2376 /*
2377  * Latency for FIFO fetches is dependent on several factors:
2378  *   - memory configuration (speed, channels)
2379  *   - chipset
2380  *   - current MCH state
2381  * It can be fairly high in some situations, so here we assume a fairly
2382  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2383  * set this value too high, the FIFO will fetch frequently to stay full)
2384  * and power consumption (set it too low to save power and we might see
2385  * FIFO underruns and display "flicker").
2386  *
2387  * A value of 5us seems to be a good balance; safe for very low end
2388  * platforms but not overly aggressive on lower latency configs.
2389  */
2390 const static int latency_ns = 5000;
2391
2392 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2393 {
2394         struct drm_i915_private *dev_priv = dev->dev_private;
2395         uint32_t dsparb = I915_READ(DSPARB);
2396         int size;
2397
2398         if (plane == 0)
2399                 size = dsparb & 0x7f;
2400         else
2401                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2402                         (dsparb & 0x7f);
2403
2404         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2405                   size);
2406
2407         return size;
2408 }
2409
2410 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2411 {
2412         struct drm_i915_private *dev_priv = dev->dev_private;
2413         uint32_t dsparb = I915_READ(DSPARB);
2414         int size;
2415
2416         if (plane == 0)
2417                 size = dsparb & 0x1ff;
2418         else
2419                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2420                         (dsparb & 0x1ff);
2421         size >>= 1; /* Convert to cachelines */
2422
2423         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2424                   size);
2425
2426         return size;
2427 }
2428
2429 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2430 {
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         uint32_t dsparb = I915_READ(DSPARB);
2433         int size;
2434
2435         size = dsparb & 0x7f;
2436         size >>= 2; /* Convert to cachelines */
2437
2438         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2439                   size);
2440
2441         return size;
2442 }
2443
2444 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2445 {
2446         struct drm_i915_private *dev_priv = dev->dev_private;
2447         uint32_t dsparb = I915_READ(DSPARB);
2448         int size;
2449
2450         size = dsparb & 0x7f;
2451         size >>= 1; /* Convert to cachelines */
2452
2453         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2454                   size);
2455
2456         return size;
2457 }
2458
2459 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2460                           int planeb_clock, int sr_hdisplay, int pixel_size)
2461 {
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         int total_size, cacheline_size;
2464         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2465         struct intel_watermark_params planea_params, planeb_params;
2466         unsigned long line_time_us;
2467         int sr_clock, sr_entries = 0, entries_required;
2468
2469         /* Create copies of the base settings for each pipe */
2470         planea_params = planeb_params = g4x_wm_info;
2471
2472         /* Grab a couple of global values before we overwrite them */
2473         total_size = planea_params.fifo_size;
2474         cacheline_size = planea_params.cacheline_size;
2475
2476         /*
2477          * Note: we need to make sure we don't overflow for various clock &
2478          * latency values.
2479          * clocks go from a few thousand to several hundred thousand.
2480          * latency is usually a few thousand
2481          */
2482         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2483                 1000;
2484         entries_required /= G4X_FIFO_LINE_SIZE;
2485         planea_wm = entries_required + planea_params.guard_size;
2486
2487         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2488                 1000;
2489         entries_required /= G4X_FIFO_LINE_SIZE;
2490         planeb_wm = entries_required + planeb_params.guard_size;
2491
2492         cursora_wm = cursorb_wm = 16;
2493         cursor_sr = 32;
2494
2495         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2496
2497         /* Calc sr entries for one plane configs */
2498         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2499                 /* self-refresh has much higher latency */
2500                 const static int sr_latency_ns = 12000;
2501
2502                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2503                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2504
2505                 /* Use ns/us then divide to preserve precision */
2506                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2507                               pixel_size * sr_hdisplay) / 1000;
2508                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2509                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2510                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2511         }
2512
2513         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2514                   planea_wm, planeb_wm, sr_entries);
2515
2516         planea_wm &= 0x3f;
2517         planeb_wm &= 0x3f;
2518
2519         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2520                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2521                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2522         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2523                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2524         /* HPLL off in SR has some issues on G4x... disable it */
2525         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2526                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2527 }
2528
2529 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2530                            int unused3, int unused4)
2531 {
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533
2534         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2535
2536         /* 965 has limitations... */
2537         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2538         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2539 }
2540
2541 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2542                            int planeb_clock, int sr_hdisplay, int pixel_size)
2543 {
2544         struct drm_i915_private *dev_priv = dev->dev_private;
2545         uint32_t fwater_lo;
2546         uint32_t fwater_hi;
2547         int total_size, cacheline_size, cwm, srwm = 1;
2548         int planea_wm, planeb_wm;
2549         struct intel_watermark_params planea_params, planeb_params;
2550         unsigned long line_time_us;
2551         int sr_clock, sr_entries = 0;
2552
2553         /* Create copies of the base settings for each pipe */
2554         if (IS_I965GM(dev) || IS_I945GM(dev))
2555                 planea_params = planeb_params = i945_wm_info;
2556         else if (IS_I9XX(dev))
2557                 planea_params = planeb_params = i915_wm_info;
2558         else
2559                 planea_params = planeb_params = i855_wm_info;
2560
2561         /* Grab a couple of global values before we overwrite them */
2562         total_size = planea_params.fifo_size;
2563         cacheline_size = planea_params.cacheline_size;
2564
2565         /* Update per-plane FIFO sizes */
2566         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2567         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2568
2569         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2570                                        pixel_size, latency_ns);
2571         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2572                                        pixel_size, latency_ns);
2573         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2574
2575         /*
2576          * Overlay gets an aggressive default since video jitter is bad.
2577          */
2578         cwm = 2;
2579
2580         /* Calc sr entries for one plane configs */
2581         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2582             (!planea_clock || !planeb_clock)) {
2583                 /* self-refresh has much higher latency */
2584                 const static int sr_latency_ns = 6000;
2585
2586                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2587                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2588
2589                 /* Use ns/us then divide to preserve precision */
2590                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2591                               pixel_size * sr_hdisplay) / 1000;
2592                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2593                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2594                 srwm = total_size - sr_entries;
2595                 if (srwm < 0)
2596                         srwm = 1;
2597                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2598         }
2599
2600         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2601                   planea_wm, planeb_wm, cwm, srwm);
2602
2603         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2604         fwater_hi = (cwm & 0x1f);
2605
2606         /* Set request length to 8 cachelines per fetch */
2607         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2608         fwater_hi = fwater_hi | (1 << 8);
2609
2610         I915_WRITE(FW_BLC, fwater_lo);
2611         I915_WRITE(FW_BLC2, fwater_hi);
2612 }
2613
2614 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2615                            int unused2, int pixel_size)
2616 {
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2619         int planea_wm;
2620
2621         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2622
2623         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2624                                        pixel_size, latency_ns);
2625         fwater_lo |= (3<<8) | planea_wm;
2626
2627         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2628
2629         I915_WRITE(FW_BLC, fwater_lo);
2630 }
2631
2632 /**
2633  * intel_update_watermarks - update FIFO watermark values based on current modes
2634  *
2635  * Calculate watermark values for the various WM regs based on current mode
2636  * and plane configuration.
2637  *
2638  * There are several cases to deal with here:
2639  *   - normal (i.e. non-self-refresh)
2640  *   - self-refresh (SR) mode
2641  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2642  *   - lines are small relative to FIFO size (buffer can hold more than 2
2643  *     lines), so need to account for TLB latency
2644  *
2645  *   The normal calculation is:
2646  *     watermark = dotclock * bytes per pixel * latency
2647  *   where latency is platform & configuration dependent (we assume pessimal
2648  *   values here).
2649  *
2650  *   The SR calculation is:
2651  *     watermark = (trunc(latency/line time)+1) * surface width *
2652  *       bytes per pixel
2653  *   where
2654  *     line time = htotal / dotclock
2655  *   and latency is assumed to be high, as above.
2656  *
2657  * The final value programmed to the register should always be rounded up,
2658  * and include an extra 2 entries to account for clock crossings.
2659  *
2660  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2661  * to set the non-SR watermarks to 8.
2662   */
2663 static void intel_update_watermarks(struct drm_device *dev)
2664 {
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         struct drm_crtc *crtc;
2667         struct intel_crtc *intel_crtc;
2668         int sr_hdisplay = 0;
2669         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2670         int enabled = 0, pixel_size = 0;
2671
2672         if (!dev_priv->display.update_wm)
2673                 return;
2674
2675         /* Get the clock config from both planes */
2676         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2677                 intel_crtc = to_intel_crtc(crtc);
2678                 if (crtc->enabled) {
2679                         enabled++;
2680                         if (intel_crtc->plane == 0) {
2681                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2682                                           intel_crtc->pipe, crtc->mode.clock);
2683                                 planea_clock = crtc->mode.clock;
2684                         } else {
2685                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2686                                           intel_crtc->pipe, crtc->mode.clock);
2687                                 planeb_clock = crtc->mode.clock;
2688                         }
2689                         sr_hdisplay = crtc->mode.hdisplay;
2690                         sr_clock = crtc->mode.clock;
2691                         if (crtc->fb)
2692                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2693                         else
2694                                 pixel_size = 4; /* by default */
2695                 }
2696         }
2697
2698         if (enabled <= 0)
2699                 return;
2700
2701         /* Single plane configs can enable self refresh */
2702         if (enabled == 1 && IS_IGD(dev))
2703                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2704         else if (IS_IGD(dev))
2705                 igd_disable_cxsr(dev);
2706
2707         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2708                                     sr_hdisplay, pixel_size);
2709 }
2710
2711 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2712                                struct drm_display_mode *mode,
2713                                struct drm_display_mode *adjusted_mode,
2714                                int x, int y,
2715                                struct drm_framebuffer *old_fb)
2716 {
2717         struct drm_device *dev = crtc->dev;
2718         struct drm_i915_private *dev_priv = dev->dev_private;
2719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2720         int pipe = intel_crtc->pipe;
2721         int plane = intel_crtc->plane;
2722         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2723         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2724         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2725         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2726         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2727         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2728         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2729         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2730         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2731         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2732         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2733         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2734         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2735         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2736         int refclk, num_outputs = 0;
2737         intel_clock_t clock, reduced_clock;
2738         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2739         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2740         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2741         bool is_edp = false;
2742         struct drm_mode_config *mode_config = &dev->mode_config;
2743         struct drm_connector *connector;
2744         const intel_limit_t *limit;
2745         int ret;
2746         struct fdi_m_n m_n = {0};
2747         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2748         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2749         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2750         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2751         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2752         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2753         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2754         int lvds_reg = LVDS;
2755         u32 temp;
2756         int sdvo_pixel_multiply;
2757         int target_clock;
2758
2759         drm_vblank_pre_modeset(dev, pipe);
2760
2761         list_for_each_entry(connector, &mode_config->connector_list, head) {
2762                 struct intel_output *intel_output = to_intel_output(connector);
2763
2764                 if (!connector->encoder || connector->encoder->crtc != crtc)
2765                         continue;
2766
2767                 switch (intel_output->type) {
2768                 case INTEL_OUTPUT_LVDS:
2769                         is_lvds = true;
2770                         break;
2771                 case INTEL_OUTPUT_SDVO:
2772                 case INTEL_OUTPUT_HDMI:
2773                         is_sdvo = true;
2774                         if (intel_output->needs_tv_clock)
2775                                 is_tv = true;
2776                         break;
2777                 case INTEL_OUTPUT_DVO:
2778                         is_dvo = true;
2779                         break;
2780                 case INTEL_OUTPUT_TVOUT:
2781                         is_tv = true;
2782                         break;
2783                 case INTEL_OUTPUT_ANALOG:
2784                         is_crt = true;
2785                         break;
2786                 case INTEL_OUTPUT_DISPLAYPORT:
2787                         is_dp = true;
2788                         break;
2789                 case INTEL_OUTPUT_EDP:
2790                         is_edp = true;
2791                         break;
2792                 }
2793
2794                 num_outputs++;
2795         }
2796
2797         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2798                 refclk = dev_priv->lvds_ssc_freq * 1000;
2799                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2800         } else if (IS_I9XX(dev)) {
2801                 refclk = 96000;
2802                 if (IS_IGDNG(dev))
2803                         refclk = 120000; /* 120Mhz refclk */
2804         } else {
2805                 refclk = 48000;
2806         }
2807
2808
2809         /*
2810          * Returns a set of divisors for the desired target clock with the given
2811          * refclk, or FALSE.  The returned values represent the clock equation:
2812          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2813          */
2814         limit = intel_limit(crtc);
2815         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2816         if (!ok) {
2817                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2818                 drm_vblank_post_modeset(dev, pipe);
2819                 return -EINVAL;
2820         }
2821
2822         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2823                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2824                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2825                                                             (adjusted_mode->clock*3/4),
2826                                                             refclk,
2827                                                             &reduced_clock);
2828         }
2829
2830         /* SDVO TV has fixed PLL values depend on its clock range,
2831            this mirrors vbios setting. */
2832         if (is_sdvo && is_tv) {
2833                 if (adjusted_mode->clock >= 100000
2834                                 && adjusted_mode->clock < 140500) {
2835                         clock.p1 = 2;
2836                         clock.p2 = 10;
2837                         clock.n = 3;
2838                         clock.m1 = 16;
2839                         clock.m2 = 8;
2840                 } else if (adjusted_mode->clock >= 140500
2841                                 && adjusted_mode->clock <= 200000) {
2842                         clock.p1 = 1;
2843                         clock.p2 = 10;
2844                         clock.n = 6;
2845                         clock.m1 = 12;
2846                         clock.m2 = 8;
2847                 }
2848         }
2849
2850         /* FDI link */
2851         if (IS_IGDNG(dev)) {
2852                 int lane, link_bw, bpp;
2853                 /* eDP doesn't require FDI link, so just set DP M/N
2854                    according to current link config */
2855                 if (is_edp) {
2856                         struct drm_connector *edp;
2857                         target_clock = mode->clock;
2858                         edp = intel_pipe_get_output(crtc);
2859                         intel_edp_link_config(to_intel_output(edp),
2860                                         &lane, &link_bw);
2861                 } else {
2862                         /* DP over FDI requires target mode clock
2863                            instead of link clock */
2864                         if (is_dp)
2865                                 target_clock = mode->clock;
2866                         else
2867                                 target_clock = adjusted_mode->clock;
2868                         lane = 4;
2869                         link_bw = 270000;
2870                 }
2871
2872                 /* determine panel color depth */
2873                 temp = I915_READ(pipeconf_reg);
2874
2875                 switch (temp & PIPE_BPC_MASK) {
2876                 case PIPE_8BPC:
2877                         bpp = 24;
2878                         break;
2879                 case PIPE_10BPC:
2880                         bpp = 30;
2881                         break;
2882                 case PIPE_6BPC:
2883                         bpp = 18;
2884                         break;
2885                 case PIPE_12BPC:
2886                         bpp = 36;
2887                         break;
2888                 default:
2889                         DRM_ERROR("unknown pipe bpc value\n");
2890                         bpp = 24;
2891                 }
2892
2893                 igdng_compute_m_n(bpp, lane, target_clock,
2894                                   link_bw, &m_n);
2895         }
2896
2897         /* Ironlake: try to setup display ref clock before DPLL
2898          * enabling. This is only under driver's control after
2899          * PCH B stepping, previous chipset stepping should be
2900          * ignoring this setting.
2901          */
2902         if (IS_IGDNG(dev)) {
2903                 temp = I915_READ(PCH_DREF_CONTROL);
2904                 /* Always enable nonspread source */
2905                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2906                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2907                 I915_WRITE(PCH_DREF_CONTROL, temp);
2908                 POSTING_READ(PCH_DREF_CONTROL);
2909
2910                 temp &= ~DREF_SSC_SOURCE_MASK;
2911                 temp |= DREF_SSC_SOURCE_ENABLE;
2912                 I915_WRITE(PCH_DREF_CONTROL, temp);
2913                 POSTING_READ(PCH_DREF_CONTROL);
2914
2915                 udelay(200);
2916
2917                 if (is_edp) {
2918                         if (dev_priv->lvds_use_ssc) {
2919                                 temp |= DREF_SSC1_ENABLE;
2920                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2921                                 POSTING_READ(PCH_DREF_CONTROL);
2922
2923                                 udelay(200);
2924
2925                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2926                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2927                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2928                                 POSTING_READ(PCH_DREF_CONTROL);
2929                         } else {
2930                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2931                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2932                                 POSTING_READ(PCH_DREF_CONTROL);
2933                         }
2934                 }
2935         }
2936
2937         if (IS_IGD(dev)) {
2938                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2939                 if (has_reduced_clock)
2940                         fp2 = (1 << reduced_clock.n) << 16 |
2941                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2942         } else {
2943                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2944                 if (has_reduced_clock)
2945                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2946                                 reduced_clock.m2;
2947         }
2948
2949         if (!IS_IGDNG(dev))
2950                 dpll = DPLL_VGA_MODE_DIS;
2951
2952         if (IS_I9XX(dev)) {
2953                 if (is_lvds)
2954                         dpll |= DPLLB_MODE_LVDS;
2955                 else
2956                         dpll |= DPLLB_MODE_DAC_SERIAL;
2957                 if (is_sdvo) {
2958                         dpll |= DPLL_DVO_HIGH_SPEED;
2959                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2960                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2961                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2962                         else if (IS_IGDNG(dev))
2963                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2964                 }
2965                 if (is_dp)
2966                         dpll |= DPLL_DVO_HIGH_SPEED;
2967
2968                 /* compute bitmask from p1 value */
2969                 if (IS_IGD(dev))
2970                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2971                 else {
2972                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2973                         /* also FPA1 */
2974                         if (IS_IGDNG(dev))
2975                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2976                         if (IS_G4X(dev) && has_reduced_clock)
2977                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2978                 }
2979                 switch (clock.p2) {
2980                 case 5:
2981                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2982                         break;
2983                 case 7:
2984                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2985                         break;
2986                 case 10:
2987                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2988                         break;
2989                 case 14:
2990                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2991                         break;
2992                 }
2993                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2994                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2995         } else {
2996                 if (is_lvds) {
2997                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2998                 } else {
2999                         if (clock.p1 == 2)
3000                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3001                         else
3002                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3003                         if (clock.p2 == 4)
3004                                 dpll |= PLL_P2_DIVIDE_BY_4;
3005                 }
3006         }
3007
3008         if (is_sdvo && is_tv)
3009                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3010         else if (is_tv)
3011                 /* XXX: just matching BIOS for now */
3012                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3013                 dpll |= 3;
3014         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3015                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3016         else
3017                 dpll |= PLL_REF_INPUT_DREFCLK;
3018
3019         /* setup pipeconf */
3020         pipeconf = I915_READ(pipeconf_reg);
3021
3022         /* Set up the display plane register */
3023         dspcntr = DISPPLANE_GAMMA_ENABLE;
3024
3025         /* IGDNG's plane is forced to pipe, bit 24 is to
3026            enable color space conversion */
3027         if (!IS_IGDNG(dev)) {
3028                 if (pipe == 0)
3029                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3030                 else
3031                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3032         }
3033
3034         if (pipe == 0 && !IS_I965G(dev)) {
3035                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3036                  * core speed.
3037                  *
3038                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3039                  * pipe == 0 check?
3040                  */
3041                 if (mode->clock >
3042                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3043                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3044                 else
3045                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3046         }
3047
3048         dspcntr |= DISPLAY_PLANE_ENABLE;
3049         pipeconf |= PIPEACONF_ENABLE;
3050         dpll |= DPLL_VCO_ENABLE;
3051
3052
3053         /* Disable the panel fitter if it was on our pipe */
3054         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3055                 I915_WRITE(PFIT_CONTROL, 0);
3056
3057         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3058         drm_mode_debug_printmodeline(mode);
3059
3060         /* assign to IGDNG registers */
3061         if (IS_IGDNG(dev)) {
3062                 fp_reg = pch_fp_reg;
3063                 dpll_reg = pch_dpll_reg;
3064         }
3065
3066         if (is_edp) {
3067                 igdng_disable_pll_edp(crtc);
3068         } else if ((dpll & DPLL_VCO_ENABLE)) {
3069                 I915_WRITE(fp_reg, fp);
3070                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3071                 I915_READ(dpll_reg);
3072                 udelay(150);
3073         }
3074
3075         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3076          * This is an exception to the general rule that mode_set doesn't turn
3077          * things on.
3078          */
3079         if (is_lvds) {
3080                 u32 lvds;
3081
3082                 if (IS_IGDNG(dev))
3083                         lvds_reg = PCH_LVDS;
3084
3085                 lvds = I915_READ(lvds_reg);
3086                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3087                 /* set the corresponsding LVDS_BORDER bit */
3088                 lvds |= dev_priv->lvds_border_bits;
3089                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3090                  * set the DPLLs for dual-channel mode or not.
3091                  */
3092                 if (clock.p2 == 7)
3093                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3094                 else
3095                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3096
3097                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3098                  * appropriately here, but we need to look more thoroughly into how
3099                  * panels behave in the two modes.
3100                  */
3101
3102                 I915_WRITE(lvds_reg, lvds);
3103                 I915_READ(lvds_reg);
3104         }
3105         if (is_dp)
3106                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3107
3108         if (!is_edp) {
3109                 I915_WRITE(fp_reg, fp);
3110                 I915_WRITE(dpll_reg, dpll);
3111                 I915_READ(dpll_reg);
3112                 /* Wait for the clocks to stabilize. */
3113                 udelay(150);
3114
3115                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3116                         if (is_sdvo) {
3117                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3118                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3119                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3120                         } else
3121                                 I915_WRITE(dpll_md_reg, 0);
3122                 } else {
3123                         /* write it again -- the BIOS does, after all */
3124                         I915_WRITE(dpll_reg, dpll);
3125                 }
3126                 I915_READ(dpll_reg);
3127                 /* Wait for the clocks to stabilize. */
3128                 udelay(150);
3129         }
3130
3131         if (is_lvds && has_reduced_clock && i915_powersave) {
3132                 I915_WRITE(fp_reg + 4, fp2);
3133                 intel_crtc->lowfreq_avail = true;
3134                 if (HAS_PIPE_CXSR(dev)) {
3135                         DRM_DEBUG("enabling CxSR downclocking\n");
3136                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3137                 }
3138         } else {
3139                 I915_WRITE(fp_reg + 4, fp);
3140                 intel_crtc->lowfreq_avail = false;
3141                 if (HAS_PIPE_CXSR(dev)) {
3142                         DRM_DEBUG("disabling CxSR downclocking\n");
3143                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3144                 }
3145         }
3146
3147         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3148                    ((adjusted_mode->crtc_htotal - 1) << 16));
3149         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3150                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3151         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3152                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3153         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3154                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3155         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3156                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3157         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3158                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3159         /* pipesrc and dspsize control the size that is scaled from, which should
3160          * always be the user's requested size.
3161          */
3162         if (!IS_IGDNG(dev)) {
3163                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3164                                 (mode->hdisplay - 1));
3165                 I915_WRITE(dsppos_reg, 0);
3166         }
3167         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3168
3169         if (IS_IGDNG(dev)) {
3170                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3171                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3172                 I915_WRITE(link_m1_reg, m_n.link_m);
3173                 I915_WRITE(link_n1_reg, m_n.link_n);
3174
3175                 if (is_edp) {
3176                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3177                 } else {
3178                         /* enable FDI RX PLL too */
3179                         temp = I915_READ(fdi_rx_reg);
3180                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3181                         udelay(200);
3182                 }
3183         }
3184
3185         I915_WRITE(pipeconf_reg, pipeconf);
3186         I915_READ(pipeconf_reg);
3187
3188         intel_wait_for_vblank(dev);
3189
3190         if (IS_IGDNG(dev)) {
3191                 /* enable address swizzle for tiling buffer */
3192                 temp = I915_READ(DISP_ARB_CTL);
3193                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3194         }
3195
3196         I915_WRITE(dspcntr_reg, dspcntr);
3197
3198         /* Flush the plane changes */
3199         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3200
3201         if ((IS_I965G(dev) || plane == 0))
3202                 intel_update_fbc(crtc, &crtc->mode);
3203
3204         intel_update_watermarks(dev);
3205
3206         drm_vblank_post_modeset(dev, pipe);
3207
3208         return ret;
3209 }
3210
3211 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3212 void intel_crtc_load_lut(struct drm_crtc *crtc)
3213 {
3214         struct drm_device *dev = crtc->dev;
3215         struct drm_i915_private *dev_priv = dev->dev_private;
3216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3217         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3218         int i;
3219
3220         /* The clocks have to be on to load the palette. */
3221         if (!crtc->enabled)
3222                 return;
3223
3224         /* use legacy palette for IGDNG */
3225         if (IS_IGDNG(dev))
3226                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3227                                                    LGC_PALETTE_B;
3228
3229         for (i = 0; i < 256; i++) {
3230                 I915_WRITE(palreg + 4 * i,
3231                            (intel_crtc->lut_r[i] << 16) |
3232                            (intel_crtc->lut_g[i] << 8) |
3233                            intel_crtc->lut_b[i]);
3234         }
3235 }
3236
3237 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3238                                  struct drm_file *file_priv,
3239                                  uint32_t handle,
3240                                  uint32_t width, uint32_t height)
3241 {
3242         struct drm_device *dev = crtc->dev;
3243         struct drm_i915_private *dev_priv = dev->dev_private;
3244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3245         struct drm_gem_object *bo;
3246         struct drm_i915_gem_object *obj_priv;
3247         int pipe = intel_crtc->pipe;
3248         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3249         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3250         uint32_t temp = I915_READ(control);
3251         size_t addr;
3252         int ret;
3253
3254         DRM_DEBUG("\n");
3255
3256         /* if we want to turn off the cursor ignore width and height */
3257         if (!handle) {
3258                 DRM_DEBUG("cursor off\n");
3259                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3260                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3261                         temp |= CURSOR_MODE_DISABLE;
3262                 } else {
3263                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3264                 }
3265                 addr = 0;
3266                 bo = NULL;
3267                 mutex_lock(&dev->struct_mutex);
3268                 goto finish;
3269         }
3270
3271         /* Currently we only support 64x64 cursors */
3272         if (width != 64 || height != 64) {
3273                 DRM_ERROR("we currently only support 64x64 cursors\n");
3274                 return -EINVAL;
3275         }
3276
3277         bo = drm_gem_object_lookup(dev, file_priv, handle);
3278         if (!bo)
3279                 return -ENOENT;
3280
3281         obj_priv = bo->driver_private;
3282
3283         if (bo->size < width * height * 4) {
3284                 DRM_ERROR("buffer is to small\n");
3285                 ret = -ENOMEM;
3286                 goto fail;
3287         }
3288
3289         /* we only need to pin inside GTT if cursor is non-phy */
3290         mutex_lock(&dev->struct_mutex);
3291         if (!dev_priv->cursor_needs_physical) {
3292                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3293                 if (ret) {
3294                         DRM_ERROR("failed to pin cursor bo\n");
3295                         goto fail_locked;
3296                 }
3297                 addr = obj_priv->gtt_offset;
3298         } else {
3299                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3300                 if (ret) {
3301                         DRM_ERROR("failed to attach phys object\n");
3302                         goto fail_locked;
3303                 }
3304                 addr = obj_priv->phys_obj->handle->busaddr;
3305         }
3306
3307         if (!IS_I9XX(dev))
3308                 I915_WRITE(CURSIZE, (height << 12) | width);
3309
3310         /* Hooray for CUR*CNTR differences */
3311         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3312                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3313                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3314                 temp |= (pipe << 28); /* Connect to correct pipe */
3315         } else {
3316                 temp &= ~(CURSOR_FORMAT_MASK);
3317                 temp |= CURSOR_ENABLE;
3318                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3319         }
3320
3321  finish:
3322         I915_WRITE(control, temp);
3323         I915_WRITE(base, addr);
3324
3325         if (intel_crtc->cursor_bo) {
3326                 if (dev_priv->cursor_needs_physical) {
3327                         if (intel_crtc->cursor_bo != bo)
3328                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3329                 } else
3330                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3331                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3332         }
3333
3334         mutex_unlock(&dev->struct_mutex);
3335
3336         intel_crtc->cursor_addr = addr;
3337         intel_crtc->cursor_bo = bo;
3338
3339         return 0;
3340 fail:
3341         mutex_lock(&dev->struct_mutex);
3342 fail_locked:
3343         drm_gem_object_unreference(bo);
3344         mutex_unlock(&dev->struct_mutex);
3345         return ret;
3346 }
3347
3348 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3349 {
3350         struct drm_device *dev = crtc->dev;
3351         struct drm_i915_private *dev_priv = dev->dev_private;
3352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353         struct intel_framebuffer *intel_fb;
3354         int pipe = intel_crtc->pipe;
3355         uint32_t temp = 0;
3356         uint32_t adder;
3357
3358         if (crtc->fb) {
3359                 intel_fb = to_intel_framebuffer(crtc->fb);
3360                 intel_mark_busy(dev, intel_fb->obj);
3361         }
3362
3363         if (x < 0) {
3364                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3365                 x = -x;
3366         }
3367         if (y < 0) {
3368                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3369                 y = -y;
3370         }
3371
3372         temp |= x << CURSOR_X_SHIFT;
3373         temp |= y << CURSOR_Y_SHIFT;
3374
3375         adder = intel_crtc->cursor_addr;
3376         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3377         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3378
3379         return 0;
3380 }
3381
3382 /** Sets the color ramps on behalf of RandR */
3383 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3384                                  u16 blue, int regno)
3385 {
3386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3387
3388         intel_crtc->lut_r[regno] = red >> 8;
3389         intel_crtc->lut_g[regno] = green >> 8;
3390         intel_crtc->lut_b[regno] = blue >> 8;
3391 }
3392
3393 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3394                              u16 *blue, int regno)
3395 {
3396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397
3398         *red = intel_crtc->lut_r[regno] << 8;
3399         *green = intel_crtc->lut_g[regno] << 8;
3400         *blue = intel_crtc->lut_b[regno] << 8;
3401 }
3402
3403 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3404                                  u16 *blue, uint32_t size)
3405 {
3406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407         int i;
3408
3409         if (size != 256)
3410                 return;
3411
3412         for (i = 0; i < 256; i++) {
3413                 intel_crtc->lut_r[i] = red[i] >> 8;
3414                 intel_crtc->lut_g[i] = green[i] >> 8;
3415                 intel_crtc->lut_b[i] = blue[i] >> 8;
3416         }
3417
3418         intel_crtc_load_lut(crtc);
3419 }
3420
3421 /**
3422  * Get a pipe with a simple mode set on it for doing load-based monitor
3423  * detection.
3424  *
3425  * It will be up to the load-detect code to adjust the pipe as appropriate for
3426  * its requirements.  The pipe will be connected to no other outputs.
3427  *
3428  * Currently this code will only succeed if there is a pipe with no outputs
3429  * configured for it.  In the future, it could choose to temporarily disable
3430  * some outputs to free up a pipe for its use.
3431  *
3432  * \return crtc, or NULL if no pipes are available.
3433  */
3434
3435 /* VESA 640x480x72Hz mode to set on the pipe */
3436 static struct drm_display_mode load_detect_mode = {
3437         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3438                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3439 };
3440
3441 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3442                                             struct drm_display_mode *mode,
3443                                             int *dpms_mode)
3444 {
3445         struct intel_crtc *intel_crtc;
3446         struct drm_crtc *possible_crtc;
3447         struct drm_crtc *supported_crtc =NULL;
3448         struct drm_encoder *encoder = &intel_output->enc;
3449         struct drm_crtc *crtc = NULL;
3450         struct drm_device *dev = encoder->dev;
3451         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3452         struct drm_crtc_helper_funcs *crtc_funcs;
3453         int i = -1;
3454
3455         /*
3456          * Algorithm gets a little messy:
3457          *   - if the connector already has an assigned crtc, use it (but make
3458          *     sure it's on first)
3459          *   - try to find the first unused crtc that can drive this connector,
3460          *     and use that if we find one
3461          *   - if there are no unused crtcs available, try to use the first
3462          *     one we found that supports the connector
3463          */
3464
3465         /* See if we already have a CRTC for this connector */
3466         if (encoder->crtc) {
3467                 crtc = encoder->crtc;
3468                 /* Make sure the crtc and connector are running */
3469                 intel_crtc = to_intel_crtc(crtc);
3470                 *dpms_mode = intel_crtc->dpms_mode;
3471                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3472                         crtc_funcs = crtc->helper_private;
3473                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3474                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3475                 }
3476                 return crtc;
3477         }
3478
3479         /* Find an unused one (if possible) */
3480         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3481                 i++;
3482                 if (!(encoder->possible_crtcs & (1 << i)))
3483                         continue;
3484                 if (!possible_crtc->enabled) {
3485                         crtc = possible_crtc;
3486                         break;
3487                 }
3488                 if (!supported_crtc)
3489                         supported_crtc = possible_crtc;
3490         }
3491
3492         /*
3493          * If we didn't find an unused CRTC, don't use any.
3494          */
3495         if (!crtc) {
3496                 return NULL;
3497         }
3498
3499         encoder->crtc = crtc;
3500         intel_output->base.encoder = encoder;
3501         intel_output->load_detect_temp = true;
3502
3503         intel_crtc = to_intel_crtc(crtc);
3504         *dpms_mode = intel_crtc->dpms_mode;
3505
3506         if (!crtc->enabled) {
3507                 if (!mode)
3508                         mode = &load_detect_mode;
3509                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3510         } else {
3511                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3512                         crtc_funcs = crtc->helper_private;
3513                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3514                 }
3515
3516                 /* Add this connector to the crtc */
3517                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3518                 encoder_funcs->commit(encoder);
3519         }
3520         /* let the connector get through one full cycle before testing */
3521         intel_wait_for_vblank(dev);
3522
3523         return crtc;
3524 }
3525
3526 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3527 {
3528         struct drm_encoder *encoder = &intel_output->enc;
3529         struct drm_device *dev = encoder->dev;
3530         struct drm_crtc *crtc = encoder->crtc;
3531         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3532         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3533
3534         if (intel_output->load_detect_temp) {
3535                 encoder->crtc = NULL;
3536                 intel_output->base.encoder = NULL;
3537                 intel_output->load_detect_temp = false;
3538                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3539                 drm_helper_disable_unused_functions(dev);
3540         }
3541
3542         /* Switch crtc and output back off if necessary */
3543         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3544                 if (encoder->crtc == crtc)
3545                         encoder_funcs->dpms(encoder, dpms_mode);
3546                 crtc_funcs->dpms(crtc, dpms_mode);
3547         }
3548 }
3549
3550 /* Returns the clock of the currently programmed mode of the given pipe. */
3551 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3552 {
3553         struct drm_i915_private *dev_priv = dev->dev_private;
3554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3555         int pipe = intel_crtc->pipe;
3556         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3557         u32 fp;
3558         intel_clock_t clock;
3559
3560         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3561                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3562         else
3563                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3564
3565         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3566         if (IS_IGD(dev)) {
3567                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3568                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3569         } else {
3570                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3571                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3572         }
3573
3574         if (IS_I9XX(dev)) {
3575                 if (IS_IGD(dev))
3576                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3577                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3578                 else
3579                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3580                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3581
3582                 switch (dpll & DPLL_MODE_MASK) {
3583                 case DPLLB_MODE_DAC_SERIAL:
3584                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3585                                 5 : 10;
3586                         break;
3587                 case DPLLB_MODE_LVDS:
3588                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3589                                 7 : 14;
3590                         break;
3591                 default:
3592                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3593                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3594                         return 0;
3595                 }
3596
3597                 /* XXX: Handle the 100Mhz refclk */
3598                 intel_clock(dev, 96000, &clock);
3599         } else {
3600                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3601
3602                 if (is_lvds) {
3603                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3604                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3605                         clock.p2 = 14;
3606
3607                         if ((dpll & PLL_REF_INPUT_MASK) ==
3608                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3609                                 /* XXX: might not be 66MHz */
3610                                 intel_clock(dev, 66000, &clock);
3611                         } else
3612                                 intel_clock(dev, 48000, &clock);
3613                 } else {
3614                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3615                                 clock.p1 = 2;
3616                         else {
3617                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3618                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3619                         }
3620                         if (dpll & PLL_P2_DIVIDE_BY_4)
3621                                 clock.p2 = 4;
3622                         else
3623                                 clock.p2 = 2;
3624
3625                         intel_clock(dev, 48000, &clock);
3626                 }
3627         }
3628
3629         /* XXX: It would be nice to validate the clocks, but we can't reuse
3630          * i830PllIsValid() because it relies on the xf86_config connector
3631          * configuration being accurate, which it isn't necessarily.
3632          */
3633
3634         return clock.dot;
3635 }
3636
3637 /** Returns the currently programmed mode of the given pipe. */
3638 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3639                                              struct drm_crtc *crtc)
3640 {
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643         int pipe = intel_crtc->pipe;
3644         struct drm_display_mode *mode;
3645         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3646         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3647         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3648         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3649
3650         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3651         if (!mode)
3652                 return NULL;
3653
3654         mode->clock = intel_crtc_clock_get(dev, crtc);
3655         mode->hdisplay = (htot & 0xffff) + 1;
3656         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3657         mode->hsync_start = (hsync & 0xffff) + 1;
3658         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3659         mode->vdisplay = (vtot & 0xffff) + 1;
3660         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3661         mode->vsync_start = (vsync & 0xffff) + 1;
3662         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3663
3664         drm_mode_set_name(mode);
3665         drm_mode_set_crtcinfo(mode, 0);
3666
3667         return mode;
3668 }
3669
3670 #define GPU_IDLE_TIMEOUT 500 /* ms */
3671
3672 /* When this timer fires, we've been idle for awhile */
3673 static void intel_gpu_idle_timer(unsigned long arg)
3674 {
3675         struct drm_device *dev = (struct drm_device *)arg;
3676         drm_i915_private_t *dev_priv = dev->dev_private;
3677
3678         DRM_DEBUG("idle timer fired, downclocking\n");
3679
3680         dev_priv->busy = false;
3681
3682         queue_work(dev_priv->wq, &dev_priv->idle_work);
3683 }
3684
3685 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3686 {
3687         drm_i915_private_t *dev_priv = dev->dev_private;
3688
3689         if (IS_IGDNG(dev))
3690                 return;
3691
3692         if (!dev_priv->render_reclock_avail) {
3693                 DRM_DEBUG("not reclocking render clock\n");
3694                 return;
3695         }
3696
3697         /* Restore render clock frequency to original value */
3698         if (IS_G4X(dev) || IS_I9XX(dev))
3699                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3700         else if (IS_I85X(dev))
3701                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3702         DRM_DEBUG("increasing render clock frequency\n");
3703
3704         /* Schedule downclock */
3705         if (schedule)
3706                 mod_timer(&dev_priv->idle_timer, jiffies +
3707                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3708 }
3709
3710 void intel_decrease_renderclock(struct drm_device *dev)
3711 {
3712         drm_i915_private_t *dev_priv = dev->dev_private;
3713
3714         if (IS_IGDNG(dev))
3715                 return;
3716
3717         if (!dev_priv->render_reclock_avail) {
3718                 DRM_DEBUG("not reclocking render clock\n");
3719                 return;
3720         }
3721
3722         if (IS_G4X(dev)) {
3723                 u16 gcfgc;
3724
3725                 /* Adjust render clock... */
3726                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3727
3728                 /* Down to minimum... */
3729                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3730                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3731
3732                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3733         } else if (IS_I965G(dev)) {
3734                 u16 gcfgc;
3735
3736                 /* Adjust render clock... */
3737                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3738
3739                 /* Down to minimum... */
3740                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3741                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3742
3743                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3744         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3745                 u16 gcfgc;
3746
3747                 /* Adjust render clock... */
3748                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3749
3750                 /* Down to minimum... */
3751                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3752                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3753
3754                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3755         } else if (IS_I915G(dev)) {
3756                 u16 gcfgc;
3757
3758                 /* Adjust render clock... */
3759                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3760
3761                 /* Down to minimum... */
3762                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3763                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3764
3765                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3766         } else if (IS_I85X(dev)) {
3767                 u16 hpllcc;
3768
3769                 /* Adjust render clock... */
3770                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3771
3772                 /* Up to maximum... */
3773                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3774                 hpllcc |= GC_CLOCK_133_200;
3775
3776                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3777         }
3778         DRM_DEBUG("decreasing render clock frequency\n");
3779 }
3780
3781 /* Note that no increase function is needed for this - increase_renderclock()
3782  *  will also rewrite these bits
3783  */
3784 void intel_decrease_displayclock(struct drm_device *dev)
3785 {
3786         if (IS_IGDNG(dev))
3787                 return;
3788
3789         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3790             IS_I915GM(dev)) {
3791                 u16 gcfgc;
3792
3793                 /* Adjust render clock... */
3794                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3795
3796                 /* Down to minimum... */
3797                 gcfgc &= ~0xf0;
3798                 gcfgc |= 0x80;
3799
3800                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3801         }
3802 }
3803
3804 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3805
3806 static void intel_crtc_idle_timer(unsigned long arg)
3807 {
3808         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3809         struct drm_crtc *crtc = &intel_crtc->base;
3810         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3811
3812         DRM_DEBUG("idle timer fired, downclocking\n");
3813
3814         intel_crtc->busy = false;
3815
3816         queue_work(dev_priv->wq, &dev_priv->idle_work);
3817 }
3818
3819 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         drm_i915_private_t *dev_priv = dev->dev_private;
3823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3824         int pipe = intel_crtc->pipe;
3825         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3826         int dpll = I915_READ(dpll_reg);
3827
3828         if (IS_IGDNG(dev))
3829                 return;
3830
3831         if (!dev_priv->lvds_downclock_avail)
3832                 return;
3833
3834         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3835                 DRM_DEBUG("upclocking LVDS\n");
3836
3837                 /* Unlock panel regs */
3838                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3839
3840                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3841                 I915_WRITE(dpll_reg, dpll);
3842                 dpll = I915_READ(dpll_reg);
3843                 intel_wait_for_vblank(dev);
3844                 dpll = I915_READ(dpll_reg);
3845                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3846                         DRM_DEBUG("failed to upclock LVDS!\n");
3847
3848                 /* ...and lock them again */
3849                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3850         }
3851
3852         /* Schedule downclock */
3853         if (schedule)
3854                 mod_timer(&intel_crtc->idle_timer, jiffies +
3855                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3856 }
3857
3858 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3859 {
3860         struct drm_device *dev = crtc->dev;
3861         drm_i915_private_t *dev_priv = dev->dev_private;
3862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3863         int pipe = intel_crtc->pipe;
3864         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3865         int dpll = I915_READ(dpll_reg);
3866
3867         if (IS_IGDNG(dev))
3868                 return;
3869
3870         if (!dev_priv->lvds_downclock_avail)
3871                 return;
3872
3873         /*
3874          * Since this is called by a timer, we should never get here in
3875          * the manual case.
3876          */
3877         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3878                 DRM_DEBUG("downclocking LVDS\n");
3879
3880                 /* Unlock panel regs */
3881                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3882
3883                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3884                 I915_WRITE(dpll_reg, dpll);
3885                 dpll = I915_READ(dpll_reg);
3886                 intel_wait_for_vblank(dev);
3887                 dpll = I915_READ(dpll_reg);
3888                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3889                         DRM_DEBUG("failed to downclock LVDS!\n");
3890
3891                 /* ...and lock them again */
3892                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3893         }
3894
3895 }
3896
3897 /**
3898  * intel_idle_update - adjust clocks for idleness
3899  * @work: work struct
3900  *
3901  * Either the GPU or display (or both) went idle.  Check the busy status
3902  * here and adjust the CRTC and GPU clocks as necessary.
3903  */
3904 static void intel_idle_update(struct work_struct *work)
3905 {
3906         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3907                                                     idle_work);
3908         struct drm_device *dev = dev_priv->dev;
3909         struct drm_crtc *crtc;
3910         struct intel_crtc *intel_crtc;
3911
3912         if (!i915_powersave)
3913                 return;
3914
3915         mutex_lock(&dev->struct_mutex);
3916
3917         /* GPU isn't processing, downclock it. */
3918         if (!dev_priv->busy) {
3919                 intel_decrease_renderclock(dev);
3920                 intel_decrease_displayclock(dev);
3921         }
3922
3923         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3924                 /* Skip inactive CRTCs */
3925                 if (!crtc->fb)
3926                         continue;
3927
3928                 intel_crtc = to_intel_crtc(crtc);
3929                 if (!intel_crtc->busy)
3930                         intel_decrease_pllclock(crtc);
3931         }
3932
3933         mutex_unlock(&dev->struct_mutex);
3934 }
3935
3936 /**
3937  * intel_mark_busy - mark the GPU and possibly the display busy
3938  * @dev: drm device
3939  * @obj: object we're operating on
3940  *
3941  * Callers can use this function to indicate that the GPU is busy processing
3942  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3943  * buffer), we'll also mark the display as busy, so we know to increase its
3944  * clock frequency.
3945  */
3946 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3947 {
3948         drm_i915_private_t *dev_priv = dev->dev_private;
3949         struct drm_crtc *crtc = NULL;
3950         struct intel_framebuffer *intel_fb;
3951         struct intel_crtc *intel_crtc;
3952
3953         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3954                 return;
3955
3956         dev_priv->busy = true;
3957         intel_increase_renderclock(dev, true);
3958
3959         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3960                 if (!crtc->fb)
3961                         continue;
3962
3963                 intel_crtc = to_intel_crtc(crtc);
3964                 intel_fb = to_intel_framebuffer(crtc->fb);
3965                 if (intel_fb->obj == obj) {
3966                         if (!intel_crtc->busy) {
3967                                 /* Non-busy -> busy, upclock */
3968                                 intel_increase_pllclock(crtc, true);
3969                                 intel_crtc->busy = true;
3970                         } else {
3971                                 /* Busy -> busy, put off timer */
3972                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3973                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3974                         }
3975                 }
3976         }
3977 }
3978
3979 static void intel_crtc_destroy(struct drm_crtc *crtc)
3980 {
3981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3982
3983         drm_crtc_cleanup(crtc);
3984         kfree(intel_crtc);
3985 }
3986
3987 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3988         .dpms = intel_crtc_dpms,
3989         .mode_fixup = intel_crtc_mode_fixup,
3990         .mode_set = intel_crtc_mode_set,
3991         .mode_set_base = intel_pipe_set_base,
3992         .prepare = intel_crtc_prepare,
3993         .commit = intel_crtc_commit,
3994         .load_lut = intel_crtc_load_lut,
3995 };
3996
3997 static const struct drm_crtc_funcs intel_crtc_funcs = {
3998         .cursor_set = intel_crtc_cursor_set,
3999         .cursor_move = intel_crtc_cursor_move,
4000         .gamma_set = intel_crtc_gamma_set,
4001         .set_config = drm_crtc_helper_set_config,
4002         .destroy = intel_crtc_destroy,
4003 };
4004
4005
4006 static void intel_crtc_init(struct drm_device *dev, int pipe)
4007 {
4008         struct intel_crtc *intel_crtc;
4009         int i;
4010
4011         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4012         if (intel_crtc == NULL)
4013                 return;
4014
4015         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4016
4017         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4018         intel_crtc->pipe = pipe;
4019         intel_crtc->plane = pipe;
4020         for (i = 0; i < 256; i++) {
4021                 intel_crtc->lut_r[i] = i;
4022                 intel_crtc->lut_g[i] = i;
4023                 intel_crtc->lut_b[i] = i;
4024         }
4025
4026         /* Swap pipes & planes for FBC on pre-965 */
4027         intel_crtc->pipe = pipe;
4028         intel_crtc->plane = pipe;
4029         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4030                 DRM_DEBUG("swapping pipes & planes for FBC\n");
4031                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4032         }
4033
4034         intel_crtc->cursor_addr = 0;
4035         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4036         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4037
4038         intel_crtc->busy = false;
4039
4040         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4041                     (unsigned long)intel_crtc);
4042 }
4043
4044 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4045                                 struct drm_file *file_priv)
4046 {
4047         drm_i915_private_t *dev_priv = dev->dev_private;
4048         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4049         struct drm_mode_object *drmmode_obj;
4050         struct intel_crtc *crtc;
4051
4052         if (!dev_priv) {
4053                 DRM_ERROR("called with no initialization\n");
4054                 return -EINVAL;
4055         }
4056
4057         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4058                         DRM_MODE_OBJECT_CRTC);
4059
4060         if (!drmmode_obj) {
4061                 DRM_ERROR("no such CRTC id\n");
4062                 return -EINVAL;
4063         }
4064
4065         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4066         pipe_from_crtc_id->pipe = crtc->pipe;
4067
4068         return 0;
4069 }
4070
4071 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4072 {
4073         struct drm_crtc *crtc = NULL;
4074
4075         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4076                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4077                 if (intel_crtc->pipe == pipe)
4078                         break;
4079         }
4080         return crtc;
4081 }
4082
4083 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4084 {
4085         int index_mask = 0;
4086         struct drm_connector *connector;
4087         int entry = 0;
4088
4089         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4090                 struct intel_output *intel_output = to_intel_output(connector);
4091                 if (type_mask & intel_output->clone_mask)
4092                         index_mask |= (1 << entry);
4093                 entry++;
4094         }
4095         return index_mask;
4096 }
4097
4098
4099 static void intel_setup_outputs(struct drm_device *dev)
4100 {
4101         struct drm_i915_private *dev_priv = dev->dev_private;
4102         struct drm_connector *connector;
4103
4104         intel_crt_init(dev);
4105
4106         /* Set up integrated LVDS */
4107         if (IS_MOBILE(dev) && !IS_I830(dev))
4108                 intel_lvds_init(dev);
4109
4110         if (IS_IGDNG(dev)) {
4111                 int found;
4112
4113                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4114                         intel_dp_init(dev, DP_A);
4115
4116                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4117                         /* check SDVOB */
4118                         /* found = intel_sdvo_init(dev, HDMIB); */
4119                         found = 0;
4120                         if (!found)
4121                                 intel_hdmi_init(dev, HDMIB);
4122                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4123                                 intel_dp_init(dev, PCH_DP_B);
4124                 }
4125
4126                 if (I915_READ(HDMIC) & PORT_DETECTED)
4127                         intel_hdmi_init(dev, HDMIC);
4128
4129                 if (I915_READ(HDMID) & PORT_DETECTED)
4130                         intel_hdmi_init(dev, HDMID);
4131
4132                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4133                         intel_dp_init(dev, PCH_DP_C);
4134
4135                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4136                         intel_dp_init(dev, PCH_DP_D);
4137
4138         } else if (IS_I9XX(dev)) {
4139                 bool found = false;
4140
4141                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4142                         found = intel_sdvo_init(dev, SDVOB);
4143                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4144                                 intel_hdmi_init(dev, SDVOB);
4145
4146                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4147                                 intel_dp_init(dev, DP_B);
4148                 }
4149
4150                 /* Before G4X SDVOC doesn't have its own detect register */
4151
4152                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4153                         found = intel_sdvo_init(dev, SDVOC);
4154
4155                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4156
4157                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4158                                 intel_hdmi_init(dev, SDVOC);
4159                         if (SUPPORTS_INTEGRATED_DP(dev))
4160                                 intel_dp_init(dev, DP_C);
4161                 }
4162
4163                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4164                         intel_dp_init(dev, DP_D);
4165         } else
4166                 intel_dvo_init(dev);
4167
4168         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4169                 intel_tv_init(dev);
4170
4171         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4172                 struct intel_output *intel_output = to_intel_output(connector);
4173                 struct drm_encoder *encoder = &intel_output->enc;
4174
4175                 encoder->possible_crtcs = intel_output->crtc_mask;
4176                 encoder->possible_clones = intel_connector_clones(dev,
4177                                                 intel_output->clone_mask);
4178         }
4179 }
4180
4181 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4182 {
4183         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4184         struct drm_device *dev = fb->dev;
4185
4186         if (fb->fbdev)
4187                 intelfb_remove(dev, fb);
4188
4189         drm_framebuffer_cleanup(fb);
4190         mutex_lock(&dev->struct_mutex);
4191         drm_gem_object_unreference(intel_fb->obj);
4192         mutex_unlock(&dev->struct_mutex);
4193
4194         kfree(intel_fb);
4195 }
4196
4197 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4198                                                 struct drm_file *file_priv,
4199                                                 unsigned int *handle)
4200 {
4201         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4202         struct drm_gem_object *object = intel_fb->obj;
4203
4204         return drm_gem_handle_create(file_priv, object, handle);
4205 }
4206
4207 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4208         .destroy = intel_user_framebuffer_destroy,
4209         .create_handle = intel_user_framebuffer_create_handle,
4210 };
4211
4212 int intel_framebuffer_create(struct drm_device *dev,
4213                              struct drm_mode_fb_cmd *mode_cmd,
4214                              struct drm_framebuffer **fb,
4215                              struct drm_gem_object *obj)
4216 {
4217         struct intel_framebuffer *intel_fb;
4218         int ret;
4219
4220         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4221         if (!intel_fb)
4222                 return -ENOMEM;
4223
4224         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4225         if (ret) {
4226                 DRM_ERROR("framebuffer init failed %d\n", ret);
4227                 return ret;
4228         }
4229
4230         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4231
4232         intel_fb->obj = obj;
4233
4234         *fb = &intel_fb->base;
4235
4236         return 0;
4237 }
4238
4239
4240 static struct drm_framebuffer *
4241 intel_user_framebuffer_create(struct drm_device *dev,
4242                               struct drm_file *filp,
4243                               struct drm_mode_fb_cmd *mode_cmd)
4244 {
4245         struct drm_gem_object *obj;
4246         struct drm_framebuffer *fb;
4247         int ret;
4248
4249         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4250         if (!obj)
4251                 return NULL;
4252
4253         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4254         if (ret) {
4255                 mutex_lock(&dev->struct_mutex);
4256                 drm_gem_object_unreference(obj);
4257                 mutex_unlock(&dev->struct_mutex);
4258                 return NULL;
4259         }
4260
4261         return fb;
4262 }
4263
4264 static const struct drm_mode_config_funcs intel_mode_funcs = {
4265         .fb_create = intel_user_framebuffer_create,
4266         .fb_changed = intelfb_probe,
4267 };
4268
4269 void intel_init_clock_gating(struct drm_device *dev)
4270 {
4271         struct drm_i915_private *dev_priv = dev->dev_private;
4272
4273         /*
4274          * Disable clock gating reported to work incorrectly according to the
4275          * specs, but enable as much else as we can.
4276          */
4277         if (IS_IGDNG(dev)) {
4278                 return;
4279         } else if (IS_G4X(dev)) {
4280                 uint32_t dspclk_gate;
4281                 I915_WRITE(RENCLK_GATE_D1, 0);
4282                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4283                        GS_UNIT_CLOCK_GATE_DISABLE |
4284                        CL_UNIT_CLOCK_GATE_DISABLE);
4285                 I915_WRITE(RAMCLK_GATE_D, 0);
4286                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4287                         OVRUNIT_CLOCK_GATE_DISABLE |
4288                         OVCUNIT_CLOCK_GATE_DISABLE;
4289                 if (IS_GM45(dev))
4290                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4291                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4292         } else if (IS_I965GM(dev)) {
4293                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4294                 I915_WRITE(RENCLK_GATE_D2, 0);
4295                 I915_WRITE(DSPCLK_GATE_D, 0);
4296                 I915_WRITE(RAMCLK_GATE_D, 0);
4297                 I915_WRITE16(DEUC, 0);
4298         } else if (IS_I965G(dev)) {
4299                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4300                        I965_RCC_CLOCK_GATE_DISABLE |
4301                        I965_RCPB_CLOCK_GATE_DISABLE |
4302                        I965_ISC_CLOCK_GATE_DISABLE |
4303                        I965_FBC_CLOCK_GATE_DISABLE);
4304                 I915_WRITE(RENCLK_GATE_D2, 0);
4305         } else if (IS_I9XX(dev)) {
4306                 u32 dstate = I915_READ(D_STATE);
4307
4308                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4309                         DSTATE_DOT_CLOCK_GATING;
4310                 I915_WRITE(D_STATE, dstate);
4311         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4312                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4313         } else if (IS_I830(dev)) {
4314                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4315         }
4316
4317         /*
4318          * GPU can automatically power down the render unit if given a page
4319          * to save state.
4320          */
4321         if (I915_HAS_RC6(dev)) {
4322                 struct drm_gem_object *pwrctx;
4323                 struct drm_i915_gem_object *obj_priv;
4324                 int ret;
4325
4326                 pwrctx = drm_gem_object_alloc(dev, 4096);
4327                 if (!pwrctx) {
4328                         DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4329                         goto out;
4330                 }
4331
4332                 ret = i915_gem_object_pin(pwrctx, 4096);
4333                 if (ret) {
4334                         DRM_ERROR("failed to pin power context: %d\n", ret);
4335                         drm_gem_object_unreference(pwrctx);
4336                         goto out;
4337                 }
4338
4339                 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4340
4341                 obj_priv = pwrctx->driver_private;
4342
4343                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4344                 I915_WRITE(MCHBAR_RENDER_STANDBY,
4345                            I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4346
4347                 dev_priv->pwrctx = pwrctx;
4348         }
4349
4350 out:
4351         return;
4352 }
4353
4354 /* Set up chip specific display functions */
4355 static void intel_init_display(struct drm_device *dev)
4356 {
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358
4359         /* We always want a DPMS function */
4360         if (IS_IGDNG(dev))
4361                 dev_priv->display.dpms = igdng_crtc_dpms;
4362         else
4363                 dev_priv->display.dpms = i9xx_crtc_dpms;
4364
4365         /* Only mobile has FBC, leave pointers NULL for other chips */
4366         if (IS_MOBILE(dev)) {
4367                 if (IS_GM45(dev)) {
4368                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4369                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4370                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4371                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4372                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4373                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4374                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4375                 }
4376                 /* 855GM needs testing */
4377         }
4378
4379         /* Returns the core display clock speed */
4380         if (IS_I945G(dev))
4381                 dev_priv->display.get_display_clock_speed =
4382                         i945_get_display_clock_speed;
4383         else if (IS_I915G(dev))
4384                 dev_priv->display.get_display_clock_speed =
4385                         i915_get_display_clock_speed;
4386         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4387                 dev_priv->display.get_display_clock_speed =
4388                         i9xx_misc_get_display_clock_speed;
4389         else if (IS_I915GM(dev))
4390                 dev_priv->display.get_display_clock_speed =
4391                         i915gm_get_display_clock_speed;
4392         else if (IS_I865G(dev))
4393                 dev_priv->display.get_display_clock_speed =
4394                         i865_get_display_clock_speed;
4395         else if (IS_I85X(dev))
4396                 dev_priv->display.get_display_clock_speed =
4397                         i855_get_display_clock_speed;
4398         else /* 852, 830 */
4399                 dev_priv->display.get_display_clock_speed =
4400                         i830_get_display_clock_speed;
4401
4402         /* For FIFO watermark updates */
4403         if (IS_IGDNG(dev))
4404                 dev_priv->display.update_wm = NULL;
4405         else if (IS_G4X(dev))
4406                 dev_priv->display.update_wm = g4x_update_wm;
4407         else if (IS_I965G(dev))
4408                 dev_priv->display.update_wm = i965_update_wm;
4409         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4410                 dev_priv->display.update_wm = i9xx_update_wm;
4411                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4412         } else {
4413                 if (IS_I85X(dev))
4414                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4415                 else if (IS_845G(dev))
4416                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4417                 else
4418                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4419                 dev_priv->display.update_wm = i830_update_wm;
4420         }
4421 }
4422
4423 void intel_modeset_init(struct drm_device *dev)
4424 {
4425         struct drm_i915_private *dev_priv = dev->dev_private;
4426         int num_pipe;
4427         int i;
4428
4429         drm_mode_config_init(dev);
4430
4431         dev->mode_config.min_width = 0;
4432         dev->mode_config.min_height = 0;
4433
4434         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4435
4436         intel_init_display(dev);
4437
4438         if (IS_I965G(dev)) {
4439                 dev->mode_config.max_width = 8192;
4440                 dev->mode_config.max_height = 8192;
4441         } else if (IS_I9XX(dev)) {
4442                 dev->mode_config.max_width = 4096;
4443                 dev->mode_config.max_height = 4096;
4444         } else {
4445                 dev->mode_config.max_width = 2048;
4446                 dev->mode_config.max_height = 2048;
4447         }
4448
4449         /* set memory base */
4450         if (IS_I9XX(dev))
4451                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4452         else
4453                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4454
4455         if (IS_MOBILE(dev) || IS_I9XX(dev))
4456                 num_pipe = 2;
4457         else
4458                 num_pipe = 1;
4459         DRM_DEBUG("%d display pipe%s available.\n",
4460                   num_pipe, num_pipe > 1 ? "s" : "");
4461
4462         if (IS_I85X(dev))
4463                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4464         else if (IS_I9XX(dev) || IS_G4X(dev))
4465                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4466
4467         for (i = 0; i < num_pipe; i++) {
4468                 intel_crtc_init(dev, i);
4469         }
4470
4471         intel_setup_outputs(dev);
4472
4473         intel_init_clock_gating(dev);
4474
4475         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4476         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4477                     (unsigned long)dev);
4478
4479         intel_setup_overlay(dev);
4480 }
4481
4482 void intel_modeset_cleanup(struct drm_device *dev)
4483 {
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485         struct drm_crtc *crtc;
4486         struct intel_crtc *intel_crtc;
4487
4488         mutex_lock(&dev->struct_mutex);
4489
4490         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4491                 /* Skip inactive CRTCs */
4492                 if (!crtc->fb)
4493                         continue;
4494
4495                 intel_crtc = to_intel_crtc(crtc);
4496                 intel_increase_pllclock(crtc, false);
4497                 del_timer_sync(&intel_crtc->idle_timer);
4498         }
4499
4500         intel_increase_renderclock(dev, false);
4501         del_timer_sync(&dev_priv->idle_timer);
4502
4503         mutex_unlock(&dev->struct_mutex);
4504
4505         if (dev_priv->display.disable_fbc)
4506                 dev_priv->display.disable_fbc(dev);
4507
4508         if (dev_priv->pwrctx) {
4509                 i915_gem_object_unpin(dev_priv->pwrctx);
4510                 drm_gem_object_unreference(dev_priv->pwrctx);
4511         }
4512
4513         drm_mode_config_cleanup(dev);
4514 }
4515
4516
4517 /* current intel driver doesn't take advantage of encoders
4518    always give back the encoder for the connector
4519 */
4520 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4521 {
4522         struct intel_output *intel_output = to_intel_output(connector);
4523
4524         return &intel_output->enc;
4525 }
4526
4527 /*
4528  * set vga decode state - true == enable VGA decode
4529  */
4530 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4531 {
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533         u16 gmch_ctrl;
4534
4535         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4536         if (state)
4537                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4538         else
4539                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4540         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4541         return 0;
4542 }