2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
68 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
84 static const uint32_t intel_cursor_formats[] = {
88 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
93 struct intel_crtc_state *pipe_config);
95 static int intel_framebuffer_init(struct drm_device *dev,
96 struct intel_framebuffer *ifb,
97 struct drm_mode_fb_cmd2 *mode_cmd,
98 struct drm_i915_gem_object *obj);
99 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void intel_set_pipe_csc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
117 static void skylake_pfit_enable(struct intel_crtc *crtc);
118 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
119 static void ironlake_pfit_enable(struct intel_crtc *crtc);
120 static void intel_modeset_setup_hw_state(struct drm_device *dev);
121 static void intel_pre_disable_primary(struct drm_crtc *crtc);
129 int p2_slow, p2_fast;
132 typedef struct intel_limit intel_limit_t;
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
138 /* returns HPLL frequency in kHz */
139 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
149 return vco_freq[hpll_freq] * 1000;
152 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg)
158 if (dev_priv->hpll_freq == 0)
159 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
161 mutex_lock(&dev_priv->sb_lock);
162 val = vlv_cck_read(dev_priv, reg);
163 mutex_unlock(&dev_priv->sb_lock);
165 divider = val & CCK_FREQUENCY_VALUES;
167 WARN((val & CCK_FREQUENCY_STATUS) !=
168 (divider << CCK_FREQUENCY_STATUS_SHIFT),
169 "%s change in progress\n", name);
171 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
175 intel_pch_rawclk(struct drm_device *dev)
177 struct drm_i915_private *dev_priv = dev->dev_private;
179 WARN_ON(!HAS_PCH_SPLIT(dev));
181 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
184 /* hrawclock is 1/4 the FSB frequency */
185 int intel_hrawclk(struct drm_device *dev)
187 struct drm_i915_private *dev_priv = dev->dev_private;
190 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
191 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
194 clkcfg = I915_READ(CLKCFG);
195 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_1067:
206 case CLKCFG_FSB_1333:
208 /* these two are just a guess; one of them might be right */
209 case CLKCFG_FSB_1600:
210 case CLKCFG_FSB_1600_ALT:
217 static void intel_update_czclk(struct drm_i915_private *dev_priv)
219 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
222 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
223 CCK_CZ_CLOCK_CONTROL);
225 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
228 static inline u32 /* units of 100MHz */
229 intel_fdi_link_freq(struct drm_device *dev)
232 struct drm_i915_private *dev_priv = dev->dev_private;
233 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
238 static const intel_limit_t intel_limits_i8xx_dac = {
239 .dot = { .min = 25000, .max = 350000 },
240 .vco = { .min = 908000, .max = 1512000 },
241 .n = { .min = 2, .max = 16 },
242 .m = { .min = 96, .max = 140 },
243 .m1 = { .min = 18, .max = 26 },
244 .m2 = { .min = 6, .max = 16 },
245 .p = { .min = 4, .max = 128 },
246 .p1 = { .min = 2, .max = 33 },
247 .p2 = { .dot_limit = 165000,
248 .p2_slow = 4, .p2_fast = 2 },
251 static const intel_limit_t intel_limits_i8xx_dvo = {
252 .dot = { .min = 25000, .max = 350000 },
253 .vco = { .min = 908000, .max = 1512000 },
254 .n = { .min = 2, .max = 16 },
255 .m = { .min = 96, .max = 140 },
256 .m1 = { .min = 18, .max = 26 },
257 .m2 = { .min = 6, .max = 16 },
258 .p = { .min = 4, .max = 128 },
259 .p1 = { .min = 2, .max = 33 },
260 .p2 = { .dot_limit = 165000,
261 .p2_slow = 4, .p2_fast = 4 },
264 static const intel_limit_t intel_limits_i8xx_lvds = {
265 .dot = { .min = 25000, .max = 350000 },
266 .vco = { .min = 908000, .max = 1512000 },
267 .n = { .min = 2, .max = 16 },
268 .m = { .min = 96, .max = 140 },
269 .m1 = { .min = 18, .max = 26 },
270 .m2 = { .min = 6, .max = 16 },
271 .p = { .min = 4, .max = 128 },
272 .p1 = { .min = 1, .max = 6 },
273 .p2 = { .dot_limit = 165000,
274 .p2_slow = 14, .p2_fast = 7 },
277 static const intel_limit_t intel_limits_i9xx_sdvo = {
278 .dot = { .min = 20000, .max = 400000 },
279 .vco = { .min = 1400000, .max = 2800000 },
280 .n = { .min = 1, .max = 6 },
281 .m = { .min = 70, .max = 120 },
282 .m1 = { .min = 8, .max = 18 },
283 .m2 = { .min = 3, .max = 7 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 200000,
287 .p2_slow = 10, .p2_fast = 5 },
290 static const intel_limit_t intel_limits_i9xx_lvds = {
291 .dot = { .min = 20000, .max = 400000 },
292 .vco = { .min = 1400000, .max = 2800000 },
293 .n = { .min = 1, .max = 6 },
294 .m = { .min = 70, .max = 120 },
295 .m1 = { .min = 8, .max = 18 },
296 .m2 = { .min = 3, .max = 7 },
297 .p = { .min = 7, .max = 98 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 112000,
300 .p2_slow = 14, .p2_fast = 7 },
304 static const intel_limit_t intel_limits_g4x_sdvo = {
305 .dot = { .min = 25000, .max = 270000 },
306 .vco = { .min = 1750000, .max = 3500000},
307 .n = { .min = 1, .max = 4 },
308 .m = { .min = 104, .max = 138 },
309 .m1 = { .min = 17, .max = 23 },
310 .m2 = { .min = 5, .max = 11 },
311 .p = { .min = 10, .max = 30 },
312 .p1 = { .min = 1, .max = 3},
313 .p2 = { .dot_limit = 270000,
319 static const intel_limit_t intel_limits_g4x_hdmi = {
320 .dot = { .min = 22000, .max = 400000 },
321 .vco = { .min = 1750000, .max = 3500000},
322 .n = { .min = 1, .max = 4 },
323 .m = { .min = 104, .max = 138 },
324 .m1 = { .min = 16, .max = 23 },
325 .m2 = { .min = 5, .max = 11 },
326 .p = { .min = 5, .max = 80 },
327 .p1 = { .min = 1, .max = 8},
328 .p2 = { .dot_limit = 165000,
329 .p2_slow = 10, .p2_fast = 5 },
332 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
333 .dot = { .min = 20000, .max = 115000 },
334 .vco = { .min = 1750000, .max = 3500000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 104, .max = 138 },
337 .m1 = { .min = 17, .max = 23 },
338 .m2 = { .min = 5, .max = 11 },
339 .p = { .min = 28, .max = 112 },
340 .p1 = { .min = 2, .max = 8 },
341 .p2 = { .dot_limit = 0,
342 .p2_slow = 14, .p2_fast = 14
346 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
347 .dot = { .min = 80000, .max = 224000 },
348 .vco = { .min = 1750000, .max = 3500000 },
349 .n = { .min = 1, .max = 3 },
350 .m = { .min = 104, .max = 138 },
351 .m1 = { .min = 17, .max = 23 },
352 .m2 = { .min = 5, .max = 11 },
353 .p = { .min = 14, .max = 42 },
354 .p1 = { .min = 2, .max = 6 },
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 7, .p2_fast = 7
360 static const intel_limit_t intel_limits_pineview_sdvo = {
361 .dot = { .min = 20000, .max = 400000},
362 .vco = { .min = 1700000, .max = 3500000 },
363 /* Pineview's Ncounter is a ring counter */
364 .n = { .min = 3, .max = 6 },
365 .m = { .min = 2, .max = 256 },
366 /* Pineview only has one combined m divider, which we treat as m2. */
367 .m1 = { .min = 0, .max = 0 },
368 .m2 = { .min = 0, .max = 254 },
369 .p = { .min = 5, .max = 80 },
370 .p1 = { .min = 1, .max = 8 },
371 .p2 = { .dot_limit = 200000,
372 .p2_slow = 10, .p2_fast = 5 },
375 static const intel_limit_t intel_limits_pineview_lvds = {
376 .dot = { .min = 20000, .max = 400000 },
377 .vco = { .min = 1700000, .max = 3500000 },
378 .n = { .min = 3, .max = 6 },
379 .m = { .min = 2, .max = 256 },
380 .m1 = { .min = 0, .max = 0 },
381 .m2 = { .min = 0, .max = 254 },
382 .p = { .min = 7, .max = 112 },
383 .p1 = { .min = 1, .max = 8 },
384 .p2 = { .dot_limit = 112000,
385 .p2_slow = 14, .p2_fast = 14 },
388 /* Ironlake / Sandybridge
390 * We calculate clock using (register_value + 2) for N/M1/M2, so here
391 * the range value for them is (actual_value - 2).
393 static const intel_limit_t intel_limits_ironlake_dac = {
394 .dot = { .min = 25000, .max = 350000 },
395 .vco = { .min = 1760000, .max = 3510000 },
396 .n = { .min = 1, .max = 5 },
397 .m = { .min = 79, .max = 127 },
398 .m1 = { .min = 12, .max = 22 },
399 .m2 = { .min = 5, .max = 9 },
400 .p = { .min = 5, .max = 80 },
401 .p1 = { .min = 1, .max = 8 },
402 .p2 = { .dot_limit = 225000,
403 .p2_slow = 10, .p2_fast = 5 },
406 static const intel_limit_t intel_limits_ironlake_single_lvds = {
407 .dot = { .min = 25000, .max = 350000 },
408 .vco = { .min = 1760000, .max = 3510000 },
409 .n = { .min = 1, .max = 3 },
410 .m = { .min = 79, .max = 118 },
411 .m1 = { .min = 12, .max = 22 },
412 .m2 = { .min = 5, .max = 9 },
413 .p = { .min = 28, .max = 112 },
414 .p1 = { .min = 2, .max = 8 },
415 .p2 = { .dot_limit = 225000,
416 .p2_slow = 14, .p2_fast = 14 },
419 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
420 .dot = { .min = 25000, .max = 350000 },
421 .vco = { .min = 1760000, .max = 3510000 },
422 .n = { .min = 1, .max = 3 },
423 .m = { .min = 79, .max = 127 },
424 .m1 = { .min = 12, .max = 22 },
425 .m2 = { .min = 5, .max = 9 },
426 .p = { .min = 14, .max = 56 },
427 .p1 = { .min = 2, .max = 8 },
428 .p2 = { .dot_limit = 225000,
429 .p2_slow = 7, .p2_fast = 7 },
432 /* LVDS 100mhz refclk limits. */
433 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
434 .dot = { .min = 25000, .max = 350000 },
435 .vco = { .min = 1760000, .max = 3510000 },
436 .n = { .min = 1, .max = 2 },
437 .m = { .min = 79, .max = 126 },
438 .m1 = { .min = 12, .max = 22 },
439 .m2 = { .min = 5, .max = 9 },
440 .p = { .min = 28, .max = 112 },
441 .p1 = { .min = 2, .max = 8 },
442 .p2 = { .dot_limit = 225000,
443 .p2_slow = 14, .p2_fast = 14 },
446 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
447 .dot = { .min = 25000, .max = 350000 },
448 .vco = { .min = 1760000, .max = 3510000 },
449 .n = { .min = 1, .max = 3 },
450 .m = { .min = 79, .max = 126 },
451 .m1 = { .min = 12, .max = 22 },
452 .m2 = { .min = 5, .max = 9 },
453 .p = { .min = 14, .max = 42 },
454 .p1 = { .min = 2, .max = 6 },
455 .p2 = { .dot_limit = 225000,
456 .p2_slow = 7, .p2_fast = 7 },
459 static const intel_limit_t intel_limits_vlv = {
461 * These are the data rate limits (measured in fast clocks)
462 * since those are the strictest limits we have. The fast
463 * clock and actual rate limits are more relaxed, so checking
464 * them would make no difference.
466 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
467 .vco = { .min = 4000000, .max = 6000000 },
468 .n = { .min = 1, .max = 7 },
469 .m1 = { .min = 2, .max = 3 },
470 .m2 = { .min = 11, .max = 156 },
471 .p1 = { .min = 2, .max = 3 },
472 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
475 static const intel_limit_t intel_limits_chv = {
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
482 .dot = { .min = 25000 * 5, .max = 540000 * 5},
483 .vco = { .min = 4800000, .max = 6480000 },
484 .n = { .min = 1, .max = 1 },
485 .m1 = { .min = 2, .max = 2 },
486 .m2 = { .min = 24 << 22, .max = 175 << 22 },
487 .p1 = { .min = 2, .max = 4 },
488 .p2 = { .p2_slow = 1, .p2_fast = 14 },
491 static const intel_limit_t intel_limits_bxt = {
492 /* FIXME: find real dot limits */
493 .dot = { .min = 0, .max = INT_MAX },
494 .vco = { .min = 4800000, .max = 6700000 },
495 .n = { .min = 1, .max = 1 },
496 .m1 = { .min = 2, .max = 2 },
497 /* FIXME: find real m2 limits */
498 .m2 = { .min = 2 << 22, .max = 255 << 22 },
499 .p1 = { .min = 2, .max = 4 },
500 .p2 = { .p2_slow = 1, .p2_fast = 20 },
504 needs_modeset(struct drm_crtc_state *state)
506 return drm_atomic_crtc_needs_modeset(state);
510 * Returns whether any output on the specified pipe is of the specified type
512 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
514 struct drm_device *dev = crtc->base.dev;
515 struct intel_encoder *encoder;
517 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
518 if (encoder->type == type)
525 * Returns whether any output on the specified pipe will have the specified
526 * type after a staged modeset is complete, i.e., the same as
527 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
530 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
533 struct drm_atomic_state *state = crtc_state->base.state;
534 struct drm_connector *connector;
535 struct drm_connector_state *connector_state;
536 struct intel_encoder *encoder;
537 int i, num_connectors = 0;
539 for_each_connector_in_state(state, connector, connector_state, i) {
540 if (connector_state->crtc != crtc_state->base.crtc)
545 encoder = to_intel_encoder(connector_state->best_encoder);
546 if (encoder->type == type)
550 WARN_ON(num_connectors == 0);
555 static const intel_limit_t *
556 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
558 struct drm_device *dev = crtc_state->base.crtc->dev;
559 const intel_limit_t *limit;
561 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
562 if (intel_is_dual_link_lvds(dev)) {
563 if (refclk == 100000)
564 limit = &intel_limits_ironlake_dual_lvds_100m;
566 limit = &intel_limits_ironlake_dual_lvds;
568 if (refclk == 100000)
569 limit = &intel_limits_ironlake_single_lvds_100m;
571 limit = &intel_limits_ironlake_single_lvds;
574 limit = &intel_limits_ironlake_dac;
579 static const intel_limit_t *
580 intel_g4x_limit(struct intel_crtc_state *crtc_state)
582 struct drm_device *dev = crtc_state->base.crtc->dev;
583 const intel_limit_t *limit;
585 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
586 if (intel_is_dual_link_lvds(dev))
587 limit = &intel_limits_g4x_dual_channel_lvds;
589 limit = &intel_limits_g4x_single_channel_lvds;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
591 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
592 limit = &intel_limits_g4x_hdmi;
593 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
594 limit = &intel_limits_g4x_sdvo;
595 } else /* The option is for other outputs */
596 limit = &intel_limits_i9xx_sdvo;
601 static const intel_limit_t *
602 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
604 struct drm_device *dev = crtc_state->base.crtc->dev;
605 const intel_limit_t *limit;
608 limit = &intel_limits_bxt;
609 else if (HAS_PCH_SPLIT(dev))
610 limit = intel_ironlake_limit(crtc_state, refclk);
611 else if (IS_G4X(dev)) {
612 limit = intel_g4x_limit(crtc_state);
613 } else if (IS_PINEVIEW(dev)) {
614 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
615 limit = &intel_limits_pineview_lvds;
617 limit = &intel_limits_pineview_sdvo;
618 } else if (IS_CHERRYVIEW(dev)) {
619 limit = &intel_limits_chv;
620 } else if (IS_VALLEYVIEW(dev)) {
621 limit = &intel_limits_vlv;
622 } else if (!IS_GEN2(dev)) {
623 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
624 limit = &intel_limits_i9xx_lvds;
626 limit = &intel_limits_i9xx_sdvo;
628 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
629 limit = &intel_limits_i8xx_lvds;
630 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
631 limit = &intel_limits_i8xx_dvo;
633 limit = &intel_limits_i8xx_dac;
639 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
640 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
641 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
642 * The helpers' return value is the rate of the clock that is fed to the
643 * display engine's pipe which can be the above fast dot clock rate or a
644 * divided-down version of it.
646 /* m1 is reserved as 0 in Pineview, n is a ring counter */
647 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
649 clock->m = clock->m2 + 2;
650 clock->p = clock->p1 * clock->p2;
651 if (WARN_ON(clock->n == 0 || clock->p == 0))
653 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
654 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
659 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
661 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
664 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
666 clock->m = i9xx_dpll_compute_m(clock);
667 clock->p = clock->p1 * clock->p2;
668 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
670 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
671 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
676 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
678 clock->m = clock->m1 * clock->m2;
679 clock->p = clock->p1 * clock->p2;
680 if (WARN_ON(clock->n == 0 || clock->p == 0))
682 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
683 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
685 return clock->dot / 5;
688 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
690 clock->m = clock->m1 * clock->m2;
691 clock->p = clock->p1 * clock->p2;
692 if (WARN_ON(clock->n == 0 || clock->p == 0))
694 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
696 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
698 return clock->dot / 5;
701 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
703 * Returns whether the given set of divisors are valid for a given refclk with
704 * the given connectors.
707 static bool intel_PLL_is_valid(struct drm_device *dev,
708 const intel_limit_t *limit,
709 const intel_clock_t *clock)
711 if (clock->n < limit->n.min || limit->n.max < clock->n)
712 INTELPllInvalid("n out of range\n");
713 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
714 INTELPllInvalid("p1 out of range\n");
715 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
716 INTELPllInvalid("m2 out of range\n");
717 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
718 INTELPllInvalid("m1 out of range\n");
720 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
721 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
722 if (clock->m1 <= clock->m2)
723 INTELPllInvalid("m1 <= m2\n");
725 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
726 if (clock->p < limit->p.min || limit->p.max < clock->p)
727 INTELPllInvalid("p out of range\n");
728 if (clock->m < limit->m.min || limit->m.max < clock->m)
729 INTELPllInvalid("m out of range\n");
732 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
733 INTELPllInvalid("vco out of range\n");
734 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
735 * connector, etc., rather than just a single range.
737 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
738 INTELPllInvalid("dot out of range\n");
744 i9xx_select_p2_div(const intel_limit_t *limit,
745 const struct intel_crtc_state *crtc_state,
748 struct drm_device *dev = crtc_state->base.crtc->dev;
750 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
752 * For LVDS just rely on its current settings for dual-channel.
753 * We haven't figured out how to reliably set up different
754 * single/dual channel state, if we even can.
756 if (intel_is_dual_link_lvds(dev))
757 return limit->p2.p2_fast;
759 return limit->p2.p2_slow;
761 if (target < limit->p2.dot_limit)
762 return limit->p2.p2_slow;
764 return limit->p2.p2_fast;
769 i9xx_find_best_dpll(const intel_limit_t *limit,
770 struct intel_crtc_state *crtc_state,
771 int target, int refclk, intel_clock_t *match_clock,
772 intel_clock_t *best_clock)
774 struct drm_device *dev = crtc_state->base.crtc->dev;
778 memset(best_clock, 0, sizeof(*best_clock));
780 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
782 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
784 for (clock.m2 = limit->m2.min;
785 clock.m2 <= limit->m2.max; clock.m2++) {
786 if (clock.m2 >= clock.m1)
788 for (clock.n = limit->n.min;
789 clock.n <= limit->n.max; clock.n++) {
790 for (clock.p1 = limit->p1.min;
791 clock.p1 <= limit->p1.max; clock.p1++) {
794 i9xx_calc_dpll_params(refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
799 clock.p != match_clock->p)
802 this_err = abs(clock.dot - target);
803 if (this_err < err) {
812 return (err != target);
816 pnv_find_best_dpll(const intel_limit_t *limit,
817 struct intel_crtc_state *crtc_state,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
821 struct drm_device *dev = crtc_state->base.crtc->dev;
825 memset(best_clock, 0, sizeof(*best_clock));
827 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
829 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
831 for (clock.m2 = limit->m2.min;
832 clock.m2 <= limit->m2.max; clock.m2++) {
833 for (clock.n = limit->n.min;
834 clock.n <= limit->n.max; clock.n++) {
835 for (clock.p1 = limit->p1.min;
836 clock.p1 <= limit->p1.max; clock.p1++) {
839 pnv_calc_dpll_params(refclk, &clock);
840 if (!intel_PLL_is_valid(dev, limit,
844 clock.p != match_clock->p)
847 this_err = abs(clock.dot - target);
848 if (this_err < err) {
857 return (err != target);
861 g4x_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
866 struct drm_device *dev = crtc_state->base.crtc->dev;
870 /* approximately equals target * 0.00585 */
871 int err_most = (target >> 8) + (target >> 9);
873 memset(best_clock, 0, sizeof(*best_clock));
875 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
877 max_n = limit->n.max;
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880 /* based on hardware requirement, prefere larger m1,m2 */
881 for (clock.m1 = limit->m1.max;
882 clock.m1 >= limit->m1.min; clock.m1--) {
883 for (clock.m2 = limit->m2.max;
884 clock.m2 >= limit->m2.min; clock.m2--) {
885 for (clock.p1 = limit->p1.max;
886 clock.p1 >= limit->p1.min; clock.p1--) {
889 i9xx_calc_dpll_params(refclk, &clock);
890 if (!intel_PLL_is_valid(dev, limit,
894 this_err = abs(clock.dot - target);
895 if (this_err < err_most) {
909 * Check if the calculated PLL configuration is more optimal compared to the
910 * best configuration and error found so far. Return the calculated error.
912 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
913 const intel_clock_t *calculated_clock,
914 const intel_clock_t *best_clock,
915 unsigned int best_error_ppm,
916 unsigned int *error_ppm)
919 * For CHV ignore the error and consider only the P value.
920 * Prefer a bigger P value based on HW requirements.
922 if (IS_CHERRYVIEW(dev)) {
925 return calculated_clock->p > best_clock->p;
928 if (WARN_ON_ONCE(!target_freq))
931 *error_ppm = div_u64(1000000ULL *
932 abs(target_freq - calculated_clock->dot),
935 * Prefer a better P value over a better (smaller) error if the error
936 * is small. Ensure this preference for future configurations too by
937 * setting the error to 0.
939 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
945 return *error_ppm + 10 < best_error_ppm;
949 vlv_find_best_dpll(const intel_limit_t *limit,
950 struct intel_crtc_state *crtc_state,
951 int target, int refclk, intel_clock_t *match_clock,
952 intel_clock_t *best_clock)
954 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
955 struct drm_device *dev = crtc->base.dev;
957 unsigned int bestppm = 1000000;
958 /* min update 19.2 MHz */
959 int max_n = min(limit->n.max, refclk / 19200);
962 target *= 5; /* fast clock */
964 memset(best_clock, 0, sizeof(*best_clock));
966 /* based on hardware requirement, prefer smaller n to precision */
967 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
968 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
969 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
970 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971 clock.p = clock.p1 * clock.p2;
972 /* based on hardware requirement, prefer bigger m1,m2 values */
973 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
976 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
979 vlv_calc_dpll_params(refclk, &clock);
981 if (!intel_PLL_is_valid(dev, limit,
985 if (!vlv_PLL_is_optimal(dev, target,
1003 chv_find_best_dpll(const intel_limit_t *limit,
1004 struct intel_crtc_state *crtc_state,
1005 int target, int refclk, intel_clock_t *match_clock,
1006 intel_clock_t *best_clock)
1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1009 struct drm_device *dev = crtc->base.dev;
1010 unsigned int best_error_ppm;
1011 intel_clock_t clock;
1015 memset(best_clock, 0, sizeof(*best_clock));
1016 best_error_ppm = 1000000;
1019 * Based on hardware doc, the n always set to 1, and m1 always
1020 * set to 2. If requires to support 200Mhz refclk, we need to
1021 * revisit this because n may not 1 anymore.
1023 clock.n = 1, clock.m1 = 2;
1024 target *= 5; /* fast clock */
1026 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1027 for (clock.p2 = limit->p2.p2_fast;
1028 clock.p2 >= limit->p2.p2_slow;
1029 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1030 unsigned int error_ppm;
1032 clock.p = clock.p1 * clock.p2;
1034 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1035 clock.n) << 22, refclk * clock.m1);
1037 if (m2 > INT_MAX/clock.m1)
1042 chv_calc_dpll_params(refclk, &clock);
1044 if (!intel_PLL_is_valid(dev, limit, &clock))
1047 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1048 best_error_ppm, &error_ppm))
1051 *best_clock = clock;
1052 best_error_ppm = error_ppm;
1060 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1061 intel_clock_t *best_clock)
1063 int refclk = i9xx_get_refclk(crtc_state, 0);
1065 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1066 target_clock, refclk, NULL, best_clock);
1069 bool intel_crtc_active(struct drm_crtc *crtc)
1071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073 /* Be paranoid as we can arrive here with only partial
1074 * state retrieved from the hardware during setup.
1076 * We can ditch the adjusted_mode.crtc_clock check as soon
1077 * as Haswell has gained clock readout/fastboot support.
1079 * We can ditch the crtc->primary->fb check as soon as we can
1080 * properly reconstruct framebuffers.
1082 * FIXME: The intel_crtc->active here should be switched to
1083 * crtc->state->active once we have proper CRTC states wired up
1086 return intel_crtc->active && crtc->primary->state->fb &&
1087 intel_crtc->config->base.adjusted_mode.crtc_clock;
1090 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1093 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1096 return intel_crtc->config->cpu_transcoder;
1099 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 i915_reg_t reg = PIPEDSL(pipe);
1107 line_mask = DSL_LINEMASK_GEN2;
1109 line_mask = DSL_LINEMASK_GEN3;
1111 line1 = I915_READ(reg) & line_mask;
1113 line2 = I915_READ(reg) & line_mask;
1115 return line1 == line2;
1119 * intel_wait_for_pipe_off - wait for pipe to turn off
1120 * @crtc: crtc whose pipe to wait for
1122 * After disabling a pipe, we can't wait for vblank in the usual way,
1123 * spinning on the vblank interrupt status bit, since we won't actually
1124 * see an interrupt when the pipe is disabled.
1126 * On Gen4 and above:
1127 * wait for the pipe register state bit to turn off
1130 * wait for the display line value to settle (it usually
1131 * ends up stopping at the start of the next frame).
1134 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1136 struct drm_device *dev = crtc->base.dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private;
1138 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1139 enum pipe pipe = crtc->pipe;
1141 if (INTEL_INFO(dev)->gen >= 4) {
1142 i915_reg_t reg = PIPECONF(cpu_transcoder);
1144 /* Wait for the Pipe State to go off */
1145 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1147 WARN(1, "pipe_off wait timed out\n");
1149 /* Wait for the display line to settle */
1150 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1151 WARN(1, "pipe_off wait timed out\n");
1155 static const char *state_string(bool enabled)
1157 return enabled ? "on" : "off";
1160 /* Only for pre-ILK configs */
1161 void assert_pll(struct drm_i915_private *dev_priv,
1162 enum pipe pipe, bool state)
1167 val = I915_READ(DPLL(pipe));
1168 cur_state = !!(val & DPLL_VCO_ENABLE);
1169 I915_STATE_WARN(cur_state != state,
1170 "PLL state assertion failure (expected %s, current %s)\n",
1171 state_string(state), state_string(cur_state));
1174 /* XXX: the dsi pll is shared between MIPI DSI ports */
1175 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1180 mutex_lock(&dev_priv->sb_lock);
1181 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1182 mutex_unlock(&dev_priv->sb_lock);
1184 cur_state = val & DSI_PLL_VCO_EN;
1185 I915_STATE_WARN(cur_state != state,
1186 "DSI PLL state assertion failure (expected %s, current %s)\n",
1187 state_string(state), state_string(cur_state));
1189 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1190 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1192 struct intel_shared_dpll *
1193 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1197 if (crtc->config->shared_dpll < 0)
1200 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1204 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1205 struct intel_shared_dpll *pll,
1209 struct intel_dpll_hw_state hw_state;
1212 "asserting DPLL %s with no DPLL\n", state_string(state)))
1215 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1216 I915_STATE_WARN(cur_state != state,
1217 "%s assertion failure (expected %s, current %s)\n",
1218 pll->name, state_string(state), state_string(cur_state));
1221 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 if (HAS_DDI(dev_priv->dev)) {
1229 /* DDI does not have a specific FDI_TX register */
1230 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1231 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1233 u32 val = I915_READ(FDI_TX_CTL(pipe));
1234 cur_state = !!(val & FDI_TX_ENABLE);
1236 I915_STATE_WARN(cur_state != state,
1237 "FDI TX state assertion failure (expected %s, current %s)\n",
1238 state_string(state), state_string(cur_state));
1240 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1241 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1243 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1244 enum pipe pipe, bool state)
1249 val = I915_READ(FDI_RX_CTL(pipe));
1250 cur_state = !!(val & FDI_RX_ENABLE);
1251 I915_STATE_WARN(cur_state != state,
1252 "FDI RX state assertion failure (expected %s, current %s)\n",
1253 state_string(state), state_string(cur_state));
1255 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1256 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1258 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1263 /* ILK FDI PLL is always enabled */
1264 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1267 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1268 if (HAS_DDI(dev_priv->dev))
1271 val = I915_READ(FDI_TX_CTL(pipe));
1272 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1275 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1276 enum pipe pipe, bool state)
1281 val = I915_READ(FDI_RX_CTL(pipe));
1282 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1283 I915_STATE_WARN(cur_state != state,
1284 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1285 state_string(state), state_string(cur_state));
1288 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1291 struct drm_device *dev = dev_priv->dev;
1294 enum pipe panel_pipe = PIPE_A;
1297 if (WARN_ON(HAS_DDI(dev)))
1300 if (HAS_PCH_SPLIT(dev)) {
1303 pp_reg = PCH_PP_CONTROL;
1304 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1306 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1307 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1308 panel_pipe = PIPE_B;
1309 /* XXX: else fix for eDP */
1310 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1311 /* presumably write lock depends on pipe, not port select */
1312 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1315 pp_reg = PP_CONTROL;
1316 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1317 panel_pipe = PIPE_B;
1320 val = I915_READ(pp_reg);
1321 if (!(val & PANEL_POWER_ON) ||
1322 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1325 I915_STATE_WARN(panel_pipe == pipe && locked,
1326 "panel assertion failure, pipe %c regs locked\n",
1330 static void assert_cursor(struct drm_i915_private *dev_priv,
1331 enum pipe pipe, bool state)
1333 struct drm_device *dev = dev_priv->dev;
1336 if (IS_845G(dev) || IS_I865G(dev))
1337 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1339 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1341 I915_STATE_WARN(cur_state != state,
1342 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1343 pipe_name(pipe), state_string(state), state_string(cur_state));
1345 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1346 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1348 void assert_pipe(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, bool state)
1352 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1355 /* if we need the pipe quirk it must be always on */
1356 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1357 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1360 if (!intel_display_power_is_enabled(dev_priv,
1361 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1364 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1365 cur_state = !!(val & PIPECONF_ENABLE);
1368 I915_STATE_WARN(cur_state != state,
1369 "pipe %c assertion failure (expected %s, current %s)\n",
1370 pipe_name(pipe), state_string(state), state_string(cur_state));
1373 static void assert_plane(struct drm_i915_private *dev_priv,
1374 enum plane plane, bool state)
1379 val = I915_READ(DSPCNTR(plane));
1380 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1381 I915_STATE_WARN(cur_state != state,
1382 "plane %c assertion failure (expected %s, current %s)\n",
1383 plane_name(plane), state_string(state), state_string(cur_state));
1386 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1387 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1389 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1392 struct drm_device *dev = dev_priv->dev;
1395 /* Primary planes are fixed to pipes on gen4+ */
1396 if (INTEL_INFO(dev)->gen >= 4) {
1397 u32 val = I915_READ(DSPCNTR(pipe));
1398 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1399 "plane %c assertion failure, should be disabled but not\n",
1404 /* Need to check both planes against the pipe */
1405 for_each_pipe(dev_priv, i) {
1406 u32 val = I915_READ(DSPCNTR(i));
1407 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1408 DISPPLANE_SEL_PIPE_SHIFT;
1409 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1410 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1411 plane_name(i), pipe_name(pipe));
1415 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1418 struct drm_device *dev = dev_priv->dev;
1421 if (INTEL_INFO(dev)->gen >= 9) {
1422 for_each_sprite(dev_priv, pipe, sprite) {
1423 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1424 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1425 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1426 sprite, pipe_name(pipe));
1428 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1429 for_each_sprite(dev_priv, pipe, sprite) {
1430 u32 val = I915_READ(SPCNTR(pipe, sprite));
1431 I915_STATE_WARN(val & SP_ENABLE,
1432 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1433 sprite_name(pipe, sprite), pipe_name(pipe));
1435 } else if (INTEL_INFO(dev)->gen >= 7) {
1436 u32 val = I915_READ(SPRCTL(pipe));
1437 I915_STATE_WARN(val & SPRITE_ENABLE,
1438 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1439 plane_name(pipe), pipe_name(pipe));
1440 } else if (INTEL_INFO(dev)->gen >= 5) {
1441 u32 val = I915_READ(DVSCNTR(pipe));
1442 I915_STATE_WARN(val & DVS_ENABLE,
1443 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1444 plane_name(pipe), pipe_name(pipe));
1448 static void assert_vblank_disabled(struct drm_crtc *crtc)
1450 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1451 drm_crtc_vblank_put(crtc);
1454 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1459 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1461 val = I915_READ(PCH_DREF_CONTROL);
1462 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1463 DREF_SUPERSPREAD_SOURCE_MASK));
1464 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1467 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1473 val = I915_READ(PCH_TRANSCONF(pipe));
1474 enabled = !!(val & TRANS_ENABLE);
1475 I915_STATE_WARN(enabled,
1476 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1480 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1481 enum pipe pipe, u32 port_sel, u32 val)
1483 if ((val & DP_PORT_EN) == 0)
1486 if (HAS_PCH_CPT(dev_priv->dev)) {
1487 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1488 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1490 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1491 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1494 if ((val & DP_PIPE_MASK) != (pipe << 30))
1500 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, u32 val)
1503 if ((val & SDVO_ENABLE) == 0)
1506 if (HAS_PCH_CPT(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1509 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1510 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1513 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1520 enum pipe pipe, u32 val)
1522 if ((val & LVDS_PORT_EN) == 0)
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1529 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1535 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, u32 val)
1538 if ((val & ADPA_DAC_ENABLE) == 0)
1540 if (HAS_PCH_CPT(dev_priv->dev)) {
1541 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1544 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1550 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe, i915_reg_t reg,
1554 u32 val = I915_READ(reg);
1555 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1556 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1557 i915_mmio_reg_offset(reg), pipe_name(pipe));
1559 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1560 && (val & DP_PIPEB_SELECT),
1561 "IBX PCH dp port still using transcoder B\n");
1564 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1565 enum pipe pipe, i915_reg_t reg)
1567 u32 val = I915_READ(reg);
1568 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1569 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1570 i915_mmio_reg_offset(reg), pipe_name(pipe));
1572 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1573 && (val & SDVO_PIPE_B_SELECT),
1574 "IBX PCH hdmi port still using transcoder B\n");
1577 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1582 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1583 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1584 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1586 val = I915_READ(PCH_ADPA);
1587 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1588 "PCH VGA enabled on transcoder %c, should be disabled\n",
1591 val = I915_READ(PCH_LVDS);
1592 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1593 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1596 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1597 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1598 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1601 static void vlv_enable_pll(struct intel_crtc *crtc,
1602 const struct intel_crtc_state *pipe_config)
1604 struct drm_device *dev = crtc->base.dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 i915_reg_t reg = DPLL(crtc->pipe);
1607 u32 dpll = pipe_config->dpll_hw_state.dpll;
1609 assert_pipe_disabled(dev_priv, crtc->pipe);
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev_priv->dev))
1613 assert_panel_unlocked(dev_priv, crtc->pipe);
1615 I915_WRITE(reg, dpll);
1619 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1620 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1623 POSTING_READ(DPLL_MD(crtc->pipe));
1625 /* We do this three times for luck */
1626 I915_WRITE(reg, dpll);
1628 udelay(150); /* wait for warmup */
1629 I915_WRITE(reg, dpll);
1631 udelay(150); /* wait for warmup */
1632 I915_WRITE(reg, dpll);
1634 udelay(150); /* wait for warmup */
1637 static void chv_enable_pll(struct intel_crtc *crtc,
1638 const struct intel_crtc_state *pipe_config)
1640 struct drm_device *dev = crtc->base.dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 int pipe = crtc->pipe;
1643 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1646 assert_pipe_disabled(dev_priv, crtc->pipe);
1648 mutex_lock(&dev_priv->sb_lock);
1650 /* Enable back the 10bit clock to display controller */
1651 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1652 tmp |= DPIO_DCLKP_EN;
1653 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655 mutex_unlock(&dev_priv->sb_lock);
1658 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1663 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665 /* Check PLL is locked */
1666 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1667 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669 /* not sure when this should be written */
1670 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1671 POSTING_READ(DPLL_MD(pipe));
1674 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 struct intel_crtc *crtc;
1679 for_each_intel_crtc(dev, crtc)
1680 count += crtc->base.state->active &&
1681 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1686 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 struct drm_device *dev = crtc->base.dev;
1689 struct drm_i915_private *dev_priv = dev->dev_private;
1690 i915_reg_t reg = DPLL(crtc->pipe);
1691 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693 assert_pipe_disabled(dev_priv, crtc->pipe);
1695 /* No really, not for ILK+ */
1696 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698 /* PLL is protected by panel, make sure we can write it */
1699 if (IS_MOBILE(dev) && !IS_I830(dev))
1700 assert_panel_unlocked(dev_priv, crtc->pipe);
1702 /* Enable DVO 2x clock on both PLLs if necessary */
1703 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 * It appears to be important that we don't enable this
1706 * for the current pipe before otherwise configuring the
1707 * PLL. No idea how this should be handled if multiple
1708 * DVO outputs are enabled simultaneosly.
1710 dpll |= DPLL_DVO_2X_MODE;
1711 I915_WRITE(DPLL(!crtc->pipe),
1712 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1716 * Apparently we need to have VGA mode enabled prior to changing
1717 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1718 * dividers, even though the register value does change.
1722 I915_WRITE(reg, dpll);
1724 /* Wait for the clocks to stabilize. */
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
1730 crtc->config->dpll_hw_state.dpll_md);
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1735 * So write it again.
1737 I915_WRITE(reg, dpll);
1740 /* We do this three times for luck */
1741 I915_WRITE(reg, dpll);
1743 udelay(150); /* wait for warmup */
1744 I915_WRITE(reg, dpll);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1749 udelay(150); /* wait for warmup */
1753 * i9xx_disable_pll - disable a PLL
1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 * Note! This is for pre-ILK only.
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770 !intel_num_dvo_pipes(dev)) {
1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786 POSTING_READ(DPLL(pipe));
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1800 val = DPLL_VGA_MODE_DIS;
1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
1816 /* Set PLL en = 0 */
1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
1824 mutex_lock(&dev_priv->sb_lock);
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831 mutex_unlock(&dev_priv->sb_lock);
1834 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1835 struct intel_digital_port *dport,
1836 unsigned int expected_mask)
1839 i915_reg_t dpll_reg;
1841 switch (dport->port) {
1843 port_mask = DPLL_PORTB_READY_MASK;
1847 port_mask = DPLL_PORTC_READY_MASK;
1849 expected_mask <<= 4;
1852 port_mask = DPLL_PORTD_READY_MASK;
1853 dpll_reg = DPIO_PHY_STATUS;
1859 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1860 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1861 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1864 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 struct drm_device *dev = crtc->base.dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
1868 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870 if (WARN_ON(pll == NULL))
1873 WARN_ON(!pll->config.crtc_mask);
1874 if (pll->active == 0) {
1875 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 assert_shared_dpll_disabled(dev_priv, pll);
1879 pll->mode_set(dev_priv, pll);
1884 * intel_enable_shared_dpll - enable PCH PLL
1885 * @dev_priv: i915 private structure
1886 * @pipe: pipe PLL to enable
1888 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1889 * drives the transcoder clock.
1891 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 struct drm_device *dev = crtc->base.dev;
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1895 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897 if (WARN_ON(pll == NULL))
1900 if (WARN_ON(pll->config.crtc_mask == 0))
1903 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1904 pll->name, pll->active, pll->on,
1905 crtc->base.base.id);
1907 if (pll->active++) {
1909 assert_shared_dpll_enabled(dev_priv, pll);
1914 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1917 pll->enable(dev_priv, pll);
1921 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 struct drm_device *dev = crtc->base.dev;
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927 /* PCH only available on ILK+ */
1928 if (INTEL_INFO(dev)->gen < 5)
1934 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1937 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1938 pll->name, pll->active, pll->on,
1939 crtc->base.base.id);
1941 if (WARN_ON(pll->active == 0)) {
1942 assert_shared_dpll_disabled(dev_priv, pll);
1946 assert_shared_dpll_enabled(dev_priv, pll);
1951 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1952 pll->disable(dev_priv, pll);
1955 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1958 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1961 struct drm_device *dev = dev_priv->dev;
1962 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965 uint32_t val, pipeconf_val;
1967 /* PCH only available on ILK+ */
1968 BUG_ON(!HAS_PCH_SPLIT(dev));
1970 /* Make sure PCH DPLL is enabled */
1971 assert_shared_dpll_enabled(dev_priv,
1972 intel_crtc_to_shared_dpll(intel_crtc));
1974 /* FDI must be feeding us bits for PCH ports */
1975 assert_fdi_tx_enabled(dev_priv, pipe);
1976 assert_fdi_rx_enabled(dev_priv, pipe);
1978 if (HAS_PCH_CPT(dev)) {
1979 /* Workaround: Set the timing override bit before enabling the
1980 * pch transcoder. */
1981 reg = TRANS_CHICKEN2(pipe);
1982 val = I915_READ(reg);
1983 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984 I915_WRITE(reg, val);
1987 reg = PCH_TRANSCONF(pipe);
1988 val = I915_READ(reg);
1989 pipeconf_val = I915_READ(PIPECONF(pipe));
1991 if (HAS_PCH_IBX(dev_priv->dev)) {
1993 * Make the BPC in transcoder be consistent with
1994 * that in pipeconf reg. For HDMI we must use 8bpc
1995 * here for both 8bpc and 12bpc.
1997 val &= ~PIPECONF_BPC_MASK;
1998 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999 val |= PIPECONF_8BPC;
2001 val |= pipeconf_val & PIPECONF_BPC_MASK;
2004 val &= ~TRANS_INTERLACE_MASK;
2005 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006 if (HAS_PCH_IBX(dev_priv->dev) &&
2007 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008 val |= TRANS_LEGACY_INTERLACED_ILK;
2010 val |= TRANS_INTERLACED;
2012 val |= TRANS_PROGRESSIVE;
2014 I915_WRITE(reg, val | TRANS_ENABLE);
2015 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020 enum transcoder cpu_transcoder)
2022 u32 val, pipeconf_val;
2024 /* PCH only available on ILK+ */
2025 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2027 /* FDI must be feeding us bits for PCH ports */
2028 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2031 /* Workaround: set timing override bit. */
2032 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2037 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2039 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040 PIPECONF_INTERLACED_ILK)
2041 val |= TRANS_INTERLACED;
2043 val |= TRANS_PROGRESSIVE;
2045 I915_WRITE(LPT_TRANSCONF, val);
2046 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047 DRM_ERROR("Failed to enable PCH transcoder\n");
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2053 struct drm_device *dev = dev_priv->dev;
2057 /* FDI relies on the transcoder */
2058 assert_fdi_tx_disabled(dev_priv, pipe);
2059 assert_fdi_rx_disabled(dev_priv, pipe);
2061 /* Ports must be off as well */
2062 assert_pch_ports_disabled(dev_priv, pipe);
2064 reg = PCH_TRANSCONF(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_ENABLE;
2067 I915_WRITE(reg, val);
2068 /* wait for PCH transcoder off, transcoder state */
2069 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2070 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2072 if (HAS_PCH_CPT(dev)) {
2073 /* Workaround: Clear the timing override chicken bit again. */
2074 reg = TRANS_CHICKEN2(pipe);
2075 val = I915_READ(reg);
2076 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2077 I915_WRITE(reg, val);
2081 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2085 val = I915_READ(LPT_TRANSCONF);
2086 val &= ~TRANS_ENABLE;
2087 I915_WRITE(LPT_TRANSCONF, val);
2088 /* wait for PCH transcoder off, transcoder state */
2089 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2090 DRM_ERROR("Failed to disable PCH transcoder\n");
2092 /* Workaround: clear timing override bit. */
2093 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2094 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2095 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2099 * intel_enable_pipe - enable a pipe, asserting requirements
2100 * @crtc: crtc responsible for the pipe
2102 * Enable @crtc's pipe, making sure that various hardware specific requirements
2103 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2105 static void intel_enable_pipe(struct intel_crtc *crtc)
2107 struct drm_device *dev = crtc->base.dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 enum pipe pipe = crtc->pipe;
2110 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2111 enum pipe pch_transcoder;
2115 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2117 assert_planes_disabled(dev_priv, pipe);
2118 assert_cursor_disabled(dev_priv, pipe);
2119 assert_sprites_disabled(dev_priv, pipe);
2121 if (HAS_PCH_LPT(dev_priv->dev))
2122 pch_transcoder = TRANSCODER_A;
2124 pch_transcoder = pipe;
2127 * A pipe without a PLL won't actually be able to drive bits from
2128 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2131 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132 if (crtc->config->has_dsi_encoder)
2133 assert_dsi_pll_enabled(dev_priv);
2135 assert_pll_enabled(dev_priv, pipe);
2137 if (crtc->config->has_pch_encoder) {
2138 /* if driving the PCH, we need FDI enabled */
2139 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140 assert_fdi_tx_pll_enabled(dev_priv,
2141 (enum pipe) cpu_transcoder);
2143 /* FIXME: assert CPU port conditions for SNB+ */
2146 reg = PIPECONF(cpu_transcoder);
2147 val = I915_READ(reg);
2148 if (val & PIPECONF_ENABLE) {
2149 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154 I915_WRITE(reg, val | PIPECONF_ENABLE);
2159 * intel_disable_pipe - disable a pipe, asserting requirements
2160 * @crtc: crtc whose pipes is to be disabled
2162 * Disable the pipe of @crtc, making sure that various hardware
2163 * specific requirements are met, if applicable, e.g. plane
2164 * disabled, panel fitter off, etc.
2166 * Will wait until the pipe has shut down before returning.
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2170 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172 enum pipe pipe = crtc->pipe;
2176 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2182 assert_planes_disabled(dev_priv, pipe);
2183 assert_cursor_disabled(dev_priv, pipe);
2184 assert_sprites_disabled(dev_priv, pipe);
2186 reg = PIPECONF(cpu_transcoder);
2187 val = I915_READ(reg);
2188 if ((val & PIPECONF_ENABLE) == 0)
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2195 if (crtc->config->double_wide)
2196 val &= ~PIPECONF_DOUBLE_WIDE;
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201 val &= ~PIPECONF_ENABLE;
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
2208 static bool need_vtd_wa(struct drm_device *dev)
2210 #ifdef CONFIG_INTEL_IOMMU
2211 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219 uint64_t fb_format_modifier, unsigned int plane)
2221 unsigned int tile_height;
2222 uint32_t pixel_bytes;
2224 switch (fb_format_modifier) {
2225 case DRM_FORMAT_MOD_NONE:
2228 case I915_FORMAT_MOD_X_TILED:
2229 tile_height = IS_GEN2(dev) ? 16 : 8;
2231 case I915_FORMAT_MOD_Y_TILED:
2234 case I915_FORMAT_MOD_Yf_TILED:
2235 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236 switch (pixel_bytes) {
2250 "128-bit pixels are not supported for display!");
2256 MISSING_CASE(fb_format_modifier);
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266 uint32_t pixel_format, uint64_t fb_format_modifier)
2268 return ALIGN(height, intel_tile_height(dev, pixel_format,
2269 fb_format_modifier, 0));
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274 const struct drm_plane_state *plane_state)
2276 struct intel_rotation_info *info = &view->params.rotation_info;
2277 unsigned int tile_height, tile_pitch;
2279 *view = i915_ggtt_view_normal;
2284 if (!intel_rotation_90_or_270(plane_state->rotation))
2287 *view = i915_ggtt_view_rotated;
2289 info->height = fb->height;
2290 info->pixel_format = fb->pixel_format;
2291 info->pitch = fb->pitches[0];
2292 info->uv_offset = fb->offsets[1];
2293 info->fb_modifier = fb->modifier[0];
2295 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296 fb->modifier[0], 0);
2297 tile_pitch = PAGE_SIZE / tile_height;
2298 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2302 if (info->pixel_format == DRM_FORMAT_NV12) {
2303 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304 fb->modifier[0], 1);
2305 tile_pitch = PAGE_SIZE / tile_height;
2306 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2309 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
2330 const struct drm_plane_state *plane_state)
2332 struct drm_device *dev = fb->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2335 struct i915_ggtt_view view;
2339 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341 switch (fb->modifier[0]) {
2342 case DRM_FORMAT_MOD_NONE:
2343 alignment = intel_linear_alignment(dev_priv);
2345 case I915_FORMAT_MOD_X_TILED:
2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2349 /* pin() will align the object as required by fence */
2353 case I915_FORMAT_MOD_Y_TILED:
2354 case I915_FORMAT_MOD_Yf_TILED:
2355 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2356 "Y tiling bo slipped through, driver bug!\n"))
2358 alignment = 1 * 1024 * 1024;
2361 MISSING_CASE(fb->modifier[0]);
2365 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2367 /* Note that the w/a also requires 64 PTE of padding following the
2368 * bo. We currently fill all unused PTE with the shadow page and so
2369 * we should always have valid PTE following the scanout preventing
2372 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2373 alignment = 256 * 1024;
2376 * Global gtt pte registers are special registers which actually forward
2377 * writes to a chunk of system memory. Which means that there is no risk
2378 * that the register values disappear as soon as we call
2379 * intel_runtime_pm_put(), so it is correct to wrap only the
2380 * pin/unpin/fence and not more.
2382 intel_runtime_pm_get(dev_priv);
2384 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2389 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2390 * fence, whereas 965+ only requires a fence if using
2391 * framebuffer compression. For simplicity, we always install
2392 * a fence as the cost is not that onerous.
2394 if (view.type == I915_GGTT_VIEW_NORMAL) {
2395 ret = i915_gem_object_get_fence(obj);
2396 if (ret == -EDEADLK) {
2398 * -EDEADLK means there are no free fences
2401 * This is propagated to atomic, but it uses
2402 * -EDEADLK to force a locking recovery, so
2403 * change the returned error to -EBUSY.
2410 i915_gem_object_pin_fence(obj);
2413 intel_runtime_pm_put(dev_priv);
2417 i915_gem_object_unpin_from_display_plane(obj, &view);
2419 intel_runtime_pm_put(dev_priv);
2423 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2424 const struct drm_plane_state *plane_state)
2426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2427 struct i915_ggtt_view view;
2429 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433 if (view.type == I915_GGTT_VIEW_NORMAL)
2434 i915_gem_object_unpin_fence(obj);
2436 i915_gem_object_unpin_from_display_plane(obj, &view);
2439 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2440 * is assumed to be a power-of-two. */
2441 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2443 unsigned int tiling_mode,
2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
2453 tiles = *x / (512/cpp);
2456 return tile_rows * pitch * 8 + tiles * 4096;
2458 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2459 unsigned int offset;
2461 offset = *y * pitch + *x * cpp;
2462 *y = (offset & alignment) / pitch;
2463 *x = ((offset & alignment) - *y * pitch) / cpp;
2464 return offset & ~alignment;
2468 static int i9xx_format_to_fourcc(int format)
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2489 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2498 return DRM_FORMAT_ABGR8888;
2500 return DRM_FORMAT_XBGR8888;
2503 return DRM_FORMAT_ARGB8888;
2505 return DRM_FORMAT_XRGB8888;
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2509 return DRM_FORMAT_XBGR2101010;
2511 return DRM_FORMAT_XRGB2101010;
2516 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_private *dev_priv = to_i915(dev);
2521 struct drm_i915_gem_object *obj = NULL;
2522 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2523 struct drm_framebuffer *fb = &plane_config->fb->base;
2524 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2525 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2528 size_aligned -= base_aligned;
2530 if (plane_config->size == 0)
2533 /* If the FB is too big, just don't use it since fbdev is not very
2534 * important and we should probably use that space with FBC or other
2536 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2539 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2546 obj->tiling_mode = plane_config->tiling;
2547 if (obj->tiling_mode == I915_TILING_X)
2548 obj->stride = fb->pitches[0];
2550 mode_cmd.pixel_format = fb->pixel_format;
2551 mode_cmd.width = fb->width;
2552 mode_cmd.height = fb->height;
2553 mode_cmd.pitches[0] = fb->pitches[0];
2554 mode_cmd.modifier[0] = fb->modifier[0];
2555 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557 mutex_lock(&dev->struct_mutex);
2558 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560 DRM_DEBUG_KMS("intel fb init failed\n");
2563 mutex_unlock(&dev->struct_mutex);
2565 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2569 drm_gem_object_unreference(&obj->base);
2570 mutex_unlock(&dev->struct_mutex);
2574 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 update_state_fb(struct drm_plane *plane)
2578 if (plane->fb == plane->state->fb)
2581 if (plane->state->fb)
2582 drm_framebuffer_unreference(plane->state->fb);
2583 plane->state->fb = plane->fb;
2584 if (plane->state->fb)
2585 drm_framebuffer_reference(plane->state->fb);
2589 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2590 struct intel_initial_plane_config *plane_config)
2592 struct drm_device *dev = intel_crtc->base.dev;
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct intel_crtc *i;
2596 struct drm_i915_gem_object *obj;
2597 struct drm_plane *primary = intel_crtc->base.primary;
2598 struct drm_plane_state *plane_state = primary->state;
2599 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2600 struct intel_plane *intel_plane = to_intel_plane(primary);
2601 struct drm_framebuffer *fb;
2603 if (!plane_config->fb)
2606 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2607 fb = &plane_config->fb->base;
2611 kfree(plane_config->fb);
2614 * Failed to alloc the obj, check to see if we should share
2615 * an fb with another CRTC instead
2617 for_each_crtc(dev, c) {
2618 i = to_intel_crtc(c);
2620 if (c == &intel_crtc->base)
2626 fb = c->primary->fb;
2630 obj = intel_fb_obj(fb);
2631 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2632 drm_framebuffer_reference(fb);
2638 * We've failed to reconstruct the BIOS FB. Current display state
2639 * indicates that the primary plane is visible, but has a NULL FB,
2640 * which will lead to problems later if we don't fix it up. The
2641 * simplest solution is to just disable the primary plane now and
2642 * pretend the BIOS never had it enabled.
2644 to_intel_plane_state(plane_state)->visible = false;
2645 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2646 intel_pre_disable_primary(&intel_crtc->base);
2647 intel_plane->disable_plane(primary, &intel_crtc->base);
2652 plane_state->src_x = 0;
2653 plane_state->src_y = 0;
2654 plane_state->src_w = fb->width << 16;
2655 plane_state->src_h = fb->height << 16;
2657 plane_state->crtc_x = 0;
2658 plane_state->crtc_y = 0;
2659 plane_state->crtc_w = fb->width;
2660 plane_state->crtc_h = fb->height;
2662 obj = intel_fb_obj(fb);
2663 if (obj->tiling_mode != I915_TILING_NONE)
2664 dev_priv->preserve_bios_swizzle = true;
2666 drm_framebuffer_reference(fb);
2667 primary->fb = primary->state->fb = fb;
2668 primary->crtc = primary->state->crtc = &intel_crtc->base;
2669 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2670 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2673 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2674 struct drm_framebuffer *fb,
2677 struct drm_device *dev = crtc->dev;
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2680 struct drm_plane *primary = crtc->primary;
2681 bool visible = to_intel_plane_state(primary->state)->visible;
2682 struct drm_i915_gem_object *obj;
2683 int plane = intel_crtc->plane;
2684 unsigned long linear_offset;
2686 i915_reg_t reg = DSPCNTR(plane);
2689 if (!visible || !fb) {
2691 if (INTEL_INFO(dev)->gen >= 4)
2692 I915_WRITE(DSPSURF(plane), 0);
2694 I915_WRITE(DSPADDR(plane), 0);
2699 obj = intel_fb_obj(fb);
2700 if (WARN_ON(obj == NULL))
2703 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2705 dspcntr = DISPPLANE_GAMMA_ENABLE;
2707 dspcntr |= DISPLAY_PLANE_ENABLE;
2709 if (INTEL_INFO(dev)->gen < 4) {
2710 if (intel_crtc->pipe == PIPE_B)
2711 dspcntr |= DISPPLANE_SEL_PIPE_B;
2713 /* pipesrc and dspsize control the size that is scaled from,
2714 * which should always be the user's requested size.
2716 I915_WRITE(DSPSIZE(plane),
2717 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2718 (intel_crtc->config->pipe_src_w - 1));
2719 I915_WRITE(DSPPOS(plane), 0);
2720 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2721 I915_WRITE(PRIMSIZE(plane),
2722 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723 (intel_crtc->config->pipe_src_w - 1));
2724 I915_WRITE(PRIMPOS(plane), 0);
2725 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2728 switch (fb->pixel_format) {
2730 dspcntr |= DISPPLANE_8BPP;
2732 case DRM_FORMAT_XRGB1555:
2733 dspcntr |= DISPPLANE_BGRX555;
2735 case DRM_FORMAT_RGB565:
2736 dspcntr |= DISPPLANE_BGRX565;
2738 case DRM_FORMAT_XRGB8888:
2739 dspcntr |= DISPPLANE_BGRX888;
2741 case DRM_FORMAT_XBGR8888:
2742 dspcntr |= DISPPLANE_RGBX888;
2744 case DRM_FORMAT_XRGB2101010:
2745 dspcntr |= DISPPLANE_BGRX101010;
2747 case DRM_FORMAT_XBGR2101010:
2748 dspcntr |= DISPPLANE_RGBX101010;
2754 if (INTEL_INFO(dev)->gen >= 4 &&
2755 obj->tiling_mode != I915_TILING_NONE)
2756 dspcntr |= DISPPLANE_TILED;
2759 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2761 linear_offset = y * fb->pitches[0] + x * pixel_size;
2763 if (INTEL_INFO(dev)->gen >= 4) {
2764 intel_crtc->dspaddr_offset =
2765 intel_gen4_compute_page_offset(dev_priv,
2766 &x, &y, obj->tiling_mode,
2769 linear_offset -= intel_crtc->dspaddr_offset;
2771 intel_crtc->dspaddr_offset = linear_offset;
2774 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2775 dspcntr |= DISPPLANE_ROTATE_180;
2777 x += (intel_crtc->config->pipe_src_w - 1);
2778 y += (intel_crtc->config->pipe_src_h - 1);
2780 /* Finding the last pixel of the last line of the display
2781 data and adding to linear_offset*/
2783 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2784 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2787 intel_crtc->adjusted_x = x;
2788 intel_crtc->adjusted_y = y;
2790 I915_WRITE(reg, dspcntr);
2792 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2793 if (INTEL_INFO(dev)->gen >= 4) {
2794 I915_WRITE(DSPSURF(plane),
2795 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2796 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2797 I915_WRITE(DSPLINOFF(plane), linear_offset);
2799 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2803 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2804 struct drm_framebuffer *fb,
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 struct drm_plane *primary = crtc->primary;
2811 bool visible = to_intel_plane_state(primary->state)->visible;
2812 struct drm_i915_gem_object *obj;
2813 int plane = intel_crtc->plane;
2814 unsigned long linear_offset;
2816 i915_reg_t reg = DSPCNTR(plane);
2819 if (!visible || !fb) {
2821 I915_WRITE(DSPSURF(plane), 0);
2826 obj = intel_fb_obj(fb);
2827 if (WARN_ON(obj == NULL))
2830 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2832 dspcntr = DISPPLANE_GAMMA_ENABLE;
2834 dspcntr |= DISPLAY_PLANE_ENABLE;
2836 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2837 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2839 switch (fb->pixel_format) {
2841 dspcntr |= DISPPLANE_8BPP;
2843 case DRM_FORMAT_RGB565:
2844 dspcntr |= DISPPLANE_BGRX565;
2846 case DRM_FORMAT_XRGB8888:
2847 dspcntr |= DISPPLANE_BGRX888;
2849 case DRM_FORMAT_XBGR8888:
2850 dspcntr |= DISPPLANE_RGBX888;
2852 case DRM_FORMAT_XRGB2101010:
2853 dspcntr |= DISPPLANE_BGRX101010;
2855 case DRM_FORMAT_XBGR2101010:
2856 dspcntr |= DISPPLANE_RGBX101010;
2862 if (obj->tiling_mode != I915_TILING_NONE)
2863 dspcntr |= DISPPLANE_TILED;
2865 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2866 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2868 linear_offset = y * fb->pitches[0] + x * pixel_size;
2869 intel_crtc->dspaddr_offset =
2870 intel_gen4_compute_page_offset(dev_priv,
2871 &x, &y, obj->tiling_mode,
2874 linear_offset -= intel_crtc->dspaddr_offset;
2875 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2876 dspcntr |= DISPPLANE_ROTATE_180;
2878 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2879 x += (intel_crtc->config->pipe_src_w - 1);
2880 y += (intel_crtc->config->pipe_src_h - 1);
2882 /* Finding the last pixel of the last line of the display
2883 data and adding to linear_offset*/
2885 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2886 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2890 intel_crtc->adjusted_x = x;
2891 intel_crtc->adjusted_y = y;
2893 I915_WRITE(reg, dspcntr);
2895 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2896 I915_WRITE(DSPSURF(plane),
2897 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2898 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2899 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2901 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2902 I915_WRITE(DSPLINOFF(plane), linear_offset);
2907 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2908 uint32_t pixel_format)
2910 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2913 * The stride is either expressed as a multiple of 64 bytes
2914 * chunks for linear buffers or in number of tiles for tiled
2917 switch (fb_modifier) {
2918 case DRM_FORMAT_MOD_NONE:
2920 case I915_FORMAT_MOD_X_TILED:
2921 if (INTEL_INFO(dev)->gen == 2)
2924 case I915_FORMAT_MOD_Y_TILED:
2925 /* No need to check for old gens and Y tiling since this is
2926 * about the display engine and those will be blocked before
2930 case I915_FORMAT_MOD_Yf_TILED:
2931 if (bits_per_pixel == 8)
2936 MISSING_CASE(fb_modifier);
2941 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2942 struct drm_i915_gem_object *obj,
2945 struct i915_ggtt_view view;
2946 struct i915_vma *vma;
2949 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2950 intel_plane->base.state);
2952 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2953 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2957 offset = vma->node.start;
2960 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2964 WARN_ON(upper_32_bits(offset));
2966 return lower_32_bits(offset);
2969 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2971 struct drm_device *dev = intel_crtc->base.dev;
2972 struct drm_i915_private *dev_priv = dev->dev_private;
2974 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2975 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2976 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2980 * This function detaches (aka. unbinds) unused scalers in hardware
2982 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2984 struct intel_crtc_scaler_state *scaler_state;
2987 scaler_state = &intel_crtc->config->scaler_state;
2989 /* loop through and disable scalers that aren't in use */
2990 for (i = 0; i < intel_crtc->num_scalers; i++) {
2991 if (!scaler_state->scalers[i].in_use)
2992 skl_detach_scaler(intel_crtc, i);
2996 u32 skl_plane_ctl_format(uint32_t pixel_format)
2998 switch (pixel_format) {
3000 return PLANE_CTL_FORMAT_INDEXED;
3001 case DRM_FORMAT_RGB565:
3002 return PLANE_CTL_FORMAT_RGB_565;
3003 case DRM_FORMAT_XBGR8888:
3004 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3005 case DRM_FORMAT_XRGB8888:
3006 return PLANE_CTL_FORMAT_XRGB_8888;
3008 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3009 * to be already pre-multiplied. We need to add a knob (or a different
3010 * DRM_FORMAT) for user-space to configure that.
3012 case DRM_FORMAT_ABGR8888:
3013 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3014 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3015 case DRM_FORMAT_ARGB8888:
3016 return PLANE_CTL_FORMAT_XRGB_8888 |
3017 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3018 case DRM_FORMAT_XRGB2101010:
3019 return PLANE_CTL_FORMAT_XRGB_2101010;
3020 case DRM_FORMAT_XBGR2101010:
3021 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3022 case DRM_FORMAT_YUYV:
3023 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3024 case DRM_FORMAT_YVYU:
3025 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3026 case DRM_FORMAT_UYVY:
3027 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3028 case DRM_FORMAT_VYUY:
3029 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3031 MISSING_CASE(pixel_format);
3037 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3039 switch (fb_modifier) {
3040 case DRM_FORMAT_MOD_NONE:
3042 case I915_FORMAT_MOD_X_TILED:
3043 return PLANE_CTL_TILED_X;
3044 case I915_FORMAT_MOD_Y_TILED:
3045 return PLANE_CTL_TILED_Y;
3046 case I915_FORMAT_MOD_Yf_TILED:
3047 return PLANE_CTL_TILED_YF;
3049 MISSING_CASE(fb_modifier);
3055 u32 skl_plane_ctl_rotation(unsigned int rotation)
3058 case BIT(DRM_ROTATE_0):
3061 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3062 * while i915 HW rotation is clockwise, thats why this swapping.
3064 case BIT(DRM_ROTATE_90):
3065 return PLANE_CTL_ROTATE_270;
3066 case BIT(DRM_ROTATE_180):
3067 return PLANE_CTL_ROTATE_180;
3068 case BIT(DRM_ROTATE_270):
3069 return PLANE_CTL_ROTATE_90;
3071 MISSING_CASE(rotation);
3077 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3078 struct drm_framebuffer *fb,
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 struct drm_plane *plane = crtc->primary;
3085 bool visible = to_intel_plane_state(plane->state)->visible;
3086 struct drm_i915_gem_object *obj;
3087 int pipe = intel_crtc->pipe;
3088 u32 plane_ctl, stride_div, stride;
3089 u32 tile_height, plane_offset, plane_size;
3090 unsigned int rotation;
3091 int x_offset, y_offset;
3093 struct intel_crtc_state *crtc_state = intel_crtc->config;
3094 struct intel_plane_state *plane_state;
3095 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3096 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3099 plane_state = to_intel_plane_state(plane->state);
3101 if (!visible || !fb) {
3102 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3103 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3104 POSTING_READ(PLANE_CTL(pipe, 0));
3108 plane_ctl = PLANE_CTL_ENABLE |
3109 PLANE_CTL_PIPE_GAMMA_ENABLE |
3110 PLANE_CTL_PIPE_CSC_ENABLE;
3112 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3113 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3114 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3116 rotation = plane->state->rotation;
3117 plane_ctl |= skl_plane_ctl_rotation(rotation);
3119 obj = intel_fb_obj(fb);
3120 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3122 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3124 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3126 scaler_id = plane_state->scaler_id;
3127 src_x = plane_state->src.x1 >> 16;
3128 src_y = plane_state->src.y1 >> 16;
3129 src_w = drm_rect_width(&plane_state->src) >> 16;
3130 src_h = drm_rect_height(&plane_state->src) >> 16;
3131 dst_x = plane_state->dst.x1;
3132 dst_y = plane_state->dst.y1;
3133 dst_w = drm_rect_width(&plane_state->dst);
3134 dst_h = drm_rect_height(&plane_state->dst);
3136 WARN_ON(x != src_x || y != src_y);
3138 if (intel_rotation_90_or_270(rotation)) {
3139 /* stride = Surface height in tiles */
3140 tile_height = intel_tile_height(dev, fb->pixel_format,
3141 fb->modifier[0], 0);
3142 stride = DIV_ROUND_UP(fb->height, tile_height);
3143 x_offset = stride * tile_height - y - src_h;
3145 plane_size = (src_w - 1) << 16 | (src_h - 1);
3147 stride = fb->pitches[0] / stride_div;
3150 plane_size = (src_h - 1) << 16 | (src_w - 1);
3152 plane_offset = y_offset << 16 | x_offset;
3154 intel_crtc->adjusted_x = x_offset;
3155 intel_crtc->adjusted_y = y_offset;
3157 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3158 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3159 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3160 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3162 if (scaler_id >= 0) {
3163 uint32_t ps_ctrl = 0;
3165 WARN_ON(!dst_w || !dst_h);
3166 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3167 crtc_state->scaler_state.scalers[scaler_id].mode;
3168 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3169 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3170 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3171 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3172 I915_WRITE(PLANE_POS(pipe, 0), 0);
3174 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3177 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3179 POSTING_READ(PLANE_SURF(pipe, 0));
3182 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3184 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3185 int x, int y, enum mode_set_atomic state)
3187 struct drm_device *dev = crtc->dev;
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3190 if (dev_priv->fbc.deactivate)
3191 dev_priv->fbc.deactivate(dev_priv);
3193 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3198 static void intel_complete_page_flips(struct drm_device *dev)
3200 struct drm_crtc *crtc;
3202 for_each_crtc(dev, crtc) {
3203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3204 enum plane plane = intel_crtc->plane;
3206 intel_prepare_page_flip(dev, plane);
3207 intel_finish_page_flip_plane(dev, plane);
3211 static void intel_update_primary_planes(struct drm_device *dev)
3213 struct drm_crtc *crtc;
3215 for_each_crtc(dev, crtc) {
3216 struct intel_plane *plane = to_intel_plane(crtc->primary);
3217 struct intel_plane_state *plane_state;
3219 drm_modeset_lock_crtc(crtc, &plane->base);
3220 plane_state = to_intel_plane_state(plane->base.state);
3222 if (crtc->state->active && plane_state->base.fb)
3223 plane->commit_plane(&plane->base, plane_state);
3225 drm_modeset_unlock_crtc(crtc);
3229 void intel_prepare_reset(struct drm_device *dev)
3231 /* no reset support for gen2 */
3235 /* reset doesn't touch the display */
3236 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3239 drm_modeset_lock_all(dev);
3241 * Disabling the crtcs gracefully seems nicer. Also the
3242 * g33 docs say we should at least disable all the planes.
3244 intel_display_suspend(dev);
3247 void intel_finish_reset(struct drm_device *dev)
3249 struct drm_i915_private *dev_priv = to_i915(dev);
3252 * Flips in the rings will be nuked by the reset,
3253 * so complete all pending flips so that user space
3254 * will get its events and not get stuck.
3256 intel_complete_page_flips(dev);
3258 /* no reset support for gen2 */
3262 /* reset doesn't touch the display */
3263 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3265 * Flips in the rings have been nuked by the reset,
3266 * so update the base address of all primary
3267 * planes to the the last fb to make sure we're
3268 * showing the correct fb after a reset.
3270 * FIXME: Atomic will make this obsolete since we won't schedule
3271 * CS-based flips (which might get lost in gpu resets) any more.
3273 intel_update_primary_planes(dev);
3278 * The display has been reset as well,
3279 * so need a full re-initialization.
3281 intel_runtime_pm_disable_interrupts(dev_priv);
3282 intel_runtime_pm_enable_interrupts(dev_priv);
3284 intel_modeset_init_hw(dev);
3286 spin_lock_irq(&dev_priv->irq_lock);
3287 if (dev_priv->display.hpd_irq_setup)
3288 dev_priv->display.hpd_irq_setup(dev);
3289 spin_unlock_irq(&dev_priv->irq_lock);
3291 intel_display_resume(dev);
3293 intel_hpd_init(dev_priv);
3295 drm_modeset_unlock_all(dev);
3298 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3300 struct drm_device *dev = crtc->dev;
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3305 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3306 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3309 spin_lock_irq(&dev->event_lock);
3310 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3311 spin_unlock_irq(&dev->event_lock);
3316 static void intel_update_pipe_config(struct intel_crtc *crtc,
3317 struct intel_crtc_state *old_crtc_state)
3319 struct drm_device *dev = crtc->base.dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 struct intel_crtc_state *pipe_config =
3322 to_intel_crtc_state(crtc->base.state);
3324 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3325 crtc->base.mode = crtc->base.state->mode;
3327 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3328 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3329 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3332 intel_set_pipe_csc(&crtc->base);
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3343 I915_WRITE(PIPESRC(crtc->pipe),
3344 ((pipe_config->pipe_src_w - 1) << 16) |
3345 (pipe_config->pipe_src_h - 1));
3347 /* on skylake this is done by detaching scalers */
3348 if (INTEL_INFO(dev)->gen >= 9) {
3349 skl_detach_scalers(crtc);
3351 if (pipe_config->pch_pfit.enabled)
3352 skylake_pfit_enable(crtc);
3353 } else if (HAS_PCH_SPLIT(dev)) {
3354 if (pipe_config->pch_pfit.enabled)
3355 ironlake_pfit_enable(crtc);
3356 else if (old_crtc_state->pch_pfit.enabled)
3357 ironlake_pfit_disable(crtc, true);
3361 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3363 struct drm_device *dev = crtc->dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 int pipe = intel_crtc->pipe;
3370 /* enable normal train */
3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 if (IS_IVYBRIDGE(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3375 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3380 I915_WRITE(reg, temp);
3382 reg = FDI_RX_CTL(pipe);
3383 temp = I915_READ(reg);
3384 if (HAS_PCH_CPT(dev)) {
3385 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3386 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3388 temp &= ~FDI_LINK_TRAIN_NONE;
3389 temp |= FDI_LINK_TRAIN_NONE;
3391 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3393 /* wait one idle pattern time */
3397 /* IVB wants error correction enabled */
3398 if (IS_IVYBRIDGE(dev))
3399 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3400 FDI_FE_ERRC_ENABLE);
3403 /* The FDI link training functions for ILK/Ibexpeak. */
3404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3406 struct drm_device *dev = crtc->dev;
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3409 int pipe = intel_crtc->pipe;
3413 /* FDI needs bits from pipe first */
3414 assert_pipe_enabled(dev_priv, pipe);
3416 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 reg = FDI_RX_IMR(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~FDI_RX_SYMBOL_LOCK;
3421 temp &= ~FDI_RX_BIT_LOCK;
3422 I915_WRITE(reg, temp);
3426 /* enable CPU FDI TX and PCH FDI RX */
3427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3430 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3431 temp &= ~FDI_LINK_TRAIN_NONE;
3432 temp |= FDI_LINK_TRAIN_PATTERN_1;
3433 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3435 reg = FDI_RX_CTL(pipe);
3436 temp = I915_READ(reg);
3437 temp &= ~FDI_LINK_TRAIN_NONE;
3438 temp |= FDI_LINK_TRAIN_PATTERN_1;
3439 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3444 /* Ironlake workaround, enable clock pointer after FDI enable*/
3445 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3447 FDI_RX_PHASE_SYNC_POINTER_EN);
3449 reg = FDI_RX_IIR(pipe);
3450 for (tries = 0; tries < 5; tries++) {
3451 temp = I915_READ(reg);
3452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454 if ((temp & FDI_RX_BIT_LOCK)) {
3455 DRM_DEBUG_KMS("FDI train 1 done.\n");
3456 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3461 DRM_ERROR("FDI train 1 fail!\n");
3464 reg = FDI_TX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~FDI_LINK_TRAIN_NONE;
3467 temp |= FDI_LINK_TRAIN_PATTERN_2;
3468 I915_WRITE(reg, temp);
3470 reg = FDI_RX_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~FDI_LINK_TRAIN_NONE;
3473 temp |= FDI_LINK_TRAIN_PATTERN_2;
3474 I915_WRITE(reg, temp);
3479 reg = FDI_RX_IIR(pipe);
3480 for (tries = 0; tries < 5; tries++) {
3481 temp = I915_READ(reg);
3482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484 if (temp & FDI_RX_SYMBOL_LOCK) {
3485 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3486 DRM_DEBUG_KMS("FDI train 2 done.\n");
3491 DRM_ERROR("FDI train 2 fail!\n");
3493 DRM_DEBUG_KMS("FDI train done\n");
3497 static const int snb_b_fdi_train_param[] = {
3498 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3499 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3500 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3501 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3504 /* The FDI link training functions for SNB/Cougarpoint. */
3505 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510 int pipe = intel_crtc->pipe;
3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
3520 I915_WRITE(reg, temp);
3525 /* enable CPU FDI TX and PCH FDI RX */
3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3554 for (i = 0; i < 4; i++) {
3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
3559 I915_WRITE(reg, temp);
3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3579 DRM_ERROR("FDI train 1 fail!\n");
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3591 I915_WRITE(reg, temp);
3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3602 I915_WRITE(reg, temp);
3607 for (i = 0; i < 4; i++) {
3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
3612 I915_WRITE(reg, temp);
3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3632 DRM_ERROR("FDI train 2 fail!\n");
3634 DRM_DEBUG_KMS("FDI train done.\n");
3637 /* Manual link training for Ivy Bridge A0 parts */
3638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
3647 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3649 reg = FDI_RX_IMR(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_RX_SYMBOL_LOCK;
3652 temp &= ~FDI_RX_BIT_LOCK;
3653 I915_WRITE(reg, temp);
3658 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3659 I915_READ(FDI_RX_IIR(pipe)));
3661 /* Try each vswing and preemphasis setting twice before moving on */
3662 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3663 /* disable first in case we need to retry */
3664 reg = FDI_TX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3667 temp &= ~FDI_TX_ENABLE;
3668 I915_WRITE(reg, temp);
3670 reg = FDI_RX_CTL(pipe);
3671 temp = I915_READ(reg);
3672 temp &= ~FDI_LINK_TRAIN_AUTO;
3673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674 temp &= ~FDI_RX_ENABLE;
3675 I915_WRITE(reg, temp);
3677 /* enable CPU FDI TX and PCH FDI RX */
3678 reg = FDI_TX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3682 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3684 temp |= snb_b_fdi_train_param[j/2];
3685 temp |= FDI_COMPOSITE_SYNC;
3686 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3688 I915_WRITE(FDI_RX_MISC(pipe),
3689 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3691 reg = FDI_RX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3694 temp |= FDI_COMPOSITE_SYNC;
3695 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3698 udelay(1); /* should be 0.5us */
3700 for (i = 0; i < 4; i++) {
3701 reg = FDI_RX_IIR(pipe);
3702 temp = I915_READ(reg);
3703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3705 if (temp & FDI_RX_BIT_LOCK ||
3706 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3707 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3708 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3712 udelay(1); /* should be 0.5us */
3715 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3720 reg = FDI_TX_CTL(pipe);
3721 temp = I915_READ(reg);
3722 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3723 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3724 I915_WRITE(reg, temp);
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3729 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3730 I915_WRITE(reg, temp);
3733 udelay(2); /* should be 1.5us */
3735 for (i = 0; i < 4; i++) {
3736 reg = FDI_RX_IIR(pipe);
3737 temp = I915_READ(reg);
3738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3740 if (temp & FDI_RX_SYMBOL_LOCK ||
3741 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3742 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3743 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3747 udelay(2); /* should be 1.5us */
3750 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3754 DRM_DEBUG_KMS("FDI train done.\n");
3757 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3759 struct drm_device *dev = intel_crtc->base.dev;
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 int pipe = intel_crtc->pipe;
3765 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3766 reg = FDI_RX_CTL(pipe);
3767 temp = I915_READ(reg);
3768 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3769 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3770 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3771 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3776 /* Switch from Rawclk to PCDclk */
3777 temp = I915_READ(reg);
3778 I915_WRITE(reg, temp | FDI_PCDCLK);
3783 /* Enable CPU FDI TX PLL, always on for Ironlake */
3784 reg = FDI_TX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3787 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3794 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3796 struct drm_device *dev = intel_crtc->base.dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 int pipe = intel_crtc->pipe;
3802 /* Switch from PCDclk to Rawclk */
3803 reg = FDI_RX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3807 /* Disable CPU FDI TX PLL */
3808 reg = FDI_TX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3819 /* Wait for the clocks to turn off. */
3824 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829 int pipe = intel_crtc->pipe;
3833 /* disable CPU FDI tx and PCH FDI rx */
3834 reg = FDI_TX_CTL(pipe);
3835 temp = I915_READ(reg);
3836 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3839 reg = FDI_RX_CTL(pipe);
3840 temp = I915_READ(reg);
3841 temp &= ~(0x7 << 16);
3842 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3843 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3848 /* Ironlake workaround, disable clock pointer after downing FDI */
3849 if (HAS_PCH_IBX(dev))
3850 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3852 /* still set train pattern 1 */
3853 reg = FDI_TX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 temp &= ~FDI_LINK_TRAIN_NONE;
3856 temp |= FDI_LINK_TRAIN_PATTERN_1;
3857 I915_WRITE(reg, temp);
3859 reg = FDI_RX_CTL(pipe);
3860 temp = I915_READ(reg);
3861 if (HAS_PCH_CPT(dev)) {
3862 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3865 temp &= ~FDI_LINK_TRAIN_NONE;
3866 temp |= FDI_LINK_TRAIN_PATTERN_1;
3868 /* BPC in FDI rx is consistent with that in PIPECONF */
3869 temp &= ~(0x07 << 16);
3870 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3871 I915_WRITE(reg, temp);
3877 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3879 struct intel_crtc *crtc;
3881 /* Note that we don't need to be called with mode_config.lock here
3882 * as our list of CRTC objects is static for the lifetime of the
3883 * device and so cannot disappear as we iterate. Similarly, we can
3884 * happily treat the predicates as racy, atomic checks as userspace
3885 * cannot claim and pin a new fb without at least acquring the
3886 * struct_mutex and so serialising with us.
3888 for_each_intel_crtc(dev, crtc) {
3889 if (atomic_read(&crtc->unpin_work_count) == 0)
3892 if (crtc->unpin_work)
3893 intel_wait_for_vblank(dev, crtc->pipe);
3901 static void page_flip_completed(struct intel_crtc *intel_crtc)
3903 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3904 struct intel_unpin_work *work = intel_crtc->unpin_work;
3906 /* ensure that the unpin work is consistent wrt ->pending. */
3908 intel_crtc->unpin_work = NULL;
3911 drm_send_vblank_event(intel_crtc->base.dev,
3915 drm_crtc_vblank_put(&intel_crtc->base);
3917 wake_up_all(&dev_priv->pending_flip_queue);
3918 queue_work(dev_priv->wq, &work->work);
3920 trace_i915_flip_complete(intel_crtc->plane,
3921 work->pending_flip_obj);
3924 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3930 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3932 ret = wait_event_interruptible_timeout(
3933 dev_priv->pending_flip_queue,
3934 !intel_crtc_has_pending_flip(crtc),
3941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3943 spin_lock_irq(&dev->event_lock);
3944 if (intel_crtc->unpin_work) {
3945 WARN_ONCE(1, "Removing stuck page flip\n");
3946 page_flip_completed(intel_crtc);
3948 spin_unlock_irq(&dev->event_lock);
3954 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3958 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3960 mutex_lock(&dev_priv->sb_lock);
3962 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3963 temp |= SBI_SSCCTL_DISABLE;
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3966 mutex_unlock(&dev_priv->sb_lock);
3969 /* Program iCLKIP clock to the desired frequency */
3970 static void lpt_program_iclkip(struct drm_crtc *crtc)
3972 struct drm_device *dev = crtc->dev;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3975 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3978 lpt_disable_iclkip(dev_priv);
3980 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3981 if (clock == 20000) {
3986 /* The iCLK virtual clock root frequency is in MHz,
3987 * but the adjusted_mode->crtc_clock in in KHz. To get the
3988 * divisors, it is necessary to divide one by another, so we
3989 * convert the virtual clock precision to KHz here for higher
3992 u32 iclk_virtual_root_freq = 172800 * 1000;
3993 u32 iclk_pi_range = 64;
3994 u32 desired_divisor, msb_divisor_value, pi_value;
3996 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3997 msb_divisor_value = desired_divisor / iclk_pi_range;
3998 pi_value = desired_divisor % iclk_pi_range;
4001 divsel = msb_divisor_value - 2;
4002 phaseinc = pi_value;
4005 /* This should not happen with any sane values */
4006 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4007 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4008 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4009 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4011 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4018 mutex_lock(&dev_priv->sb_lock);
4020 /* Program SSCDIVINTPHASE6 */
4021 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4022 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4023 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4024 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4025 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4026 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4027 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4028 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4030 /* Program SSCAUXDIV */
4031 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4032 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4033 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4034 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4036 /* Enable modulator and associated divider */
4037 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4038 temp &= ~SBI_SSCCTL_DISABLE;
4039 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4041 mutex_unlock(&dev_priv->sb_lock);
4043 /* Wait for initialization time */
4046 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4049 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4050 enum pipe pch_transcoder)
4052 struct drm_device *dev = crtc->base.dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4056 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4057 I915_READ(HTOTAL(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4059 I915_READ(HBLANK(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4061 I915_READ(HSYNC(cpu_transcoder)));
4063 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4064 I915_READ(VTOTAL(cpu_transcoder)));
4065 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4066 I915_READ(VBLANK(cpu_transcoder)));
4067 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4068 I915_READ(VSYNC(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4070 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4073 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4078 temp = I915_READ(SOUTH_CHICKEN1);
4079 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4085 temp &= ~FDI_BC_BIFURCATION_SELECT;
4087 temp |= FDI_BC_BIFURCATION_SELECT;
4089 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4090 I915_WRITE(SOUTH_CHICKEN1, temp);
4091 POSTING_READ(SOUTH_CHICKEN1);
4094 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4096 struct drm_device *dev = intel_crtc->base.dev;
4098 switch (intel_crtc->pipe) {
4102 if (intel_crtc->config->fdi_lanes > 2)
4103 cpt_set_fdi_bc_bifurcation(dev, false);
4105 cpt_set_fdi_bc_bifurcation(dev, true);
4109 cpt_set_fdi_bc_bifurcation(dev, true);
4117 /* Return which DP Port should be selected for Transcoder DP control */
4119 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4121 struct drm_device *dev = crtc->dev;
4122 struct intel_encoder *encoder;
4124 for_each_encoder_on_crtc(dev, crtc, encoder) {
4125 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4126 encoder->type == INTEL_OUTPUT_EDP)
4127 return enc_to_dig_port(&encoder->base)->port;
4134 * Enable PCH resources required for PCH ports:
4136 * - FDI training & RX/TX
4137 * - update transcoder timings
4138 * - DP transcoding bits
4141 static void ironlake_pch_enable(struct drm_crtc *crtc)
4143 struct drm_device *dev = crtc->dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4146 int pipe = intel_crtc->pipe;
4149 assert_pch_transcoder_disabled(dev_priv, pipe);
4151 if (IS_IVYBRIDGE(dev))
4152 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4154 /* Write the TU size bits before fdi link training, so that error
4155 * detection works. */
4156 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4157 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4160 * Sometimes spurious CPU pipe underruns happen during FDI
4161 * training, at least with VGA+HDMI cloning. Suppress them.
4163 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4165 /* For PCH output, training FDI link */
4166 dev_priv->display.fdi_link_train(crtc);
4168 /* We need to program the right clock selection before writing the pixel
4169 * mutliplier into the DPLL. */
4170 if (HAS_PCH_CPT(dev)) {
4173 temp = I915_READ(PCH_DPLL_SEL);
4174 temp |= TRANS_DPLL_ENABLE(pipe);
4175 sel = TRANS_DPLLB_SEL(pipe);
4176 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4180 I915_WRITE(PCH_DPLL_SEL, temp);
4183 /* XXX: pch pll's can be enabled any time before we enable the PCH
4184 * transcoder, and we actually should do this to not upset any PCH
4185 * transcoder that already use the clock when we share it.
4187 * Note that enable_shared_dpll tries to do the right thing, but
4188 * get_shared_dpll unconditionally resets the pll - we need that to have
4189 * the right LVDS enable sequence. */
4190 intel_enable_shared_dpll(intel_crtc);
4192 /* set transcoder timing, panel must allow it */
4193 assert_panel_unlocked(dev_priv, pipe);
4194 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4196 intel_fdi_normal_train(crtc);
4198 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4200 /* For PCH DP, enable TRANS_DP_CTL */
4201 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4202 const struct drm_display_mode *adjusted_mode =
4203 &intel_crtc->config->base.adjusted_mode;
4204 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4205 i915_reg_t reg = TRANS_DP_CTL(pipe);
4206 temp = I915_READ(reg);
4207 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4208 TRANS_DP_SYNC_MASK |
4210 temp |= TRANS_DP_OUTPUT_ENABLE;
4211 temp |= bpc << 9; /* same format but at 11:9 */
4213 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4214 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4215 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4216 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4218 switch (intel_trans_dp_port_sel(crtc)) {
4220 temp |= TRANS_DP_PORT_SEL_B;
4223 temp |= TRANS_DP_PORT_SEL_C;
4226 temp |= TRANS_DP_PORT_SEL_D;
4232 I915_WRITE(reg, temp);
4235 ironlake_enable_pch_transcoder(dev_priv, pipe);
4238 static void lpt_pch_enable(struct drm_crtc *crtc)
4240 struct drm_device *dev = crtc->dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4243 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4245 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4247 lpt_program_iclkip(crtc);
4249 /* Set transcoder timing. */
4250 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4252 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4255 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4256 struct intel_crtc_state *crtc_state)
4258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4259 struct intel_shared_dpll *pll;
4260 struct intel_shared_dpll_config *shared_dpll;
4261 enum intel_dpll_id i;
4262 int max = dev_priv->num_shared_dpll;
4264 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4266 if (HAS_PCH_IBX(dev_priv->dev)) {
4267 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4268 i = (enum intel_dpll_id) crtc->pipe;
4269 pll = &dev_priv->shared_dplls[i];
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
4274 WARN_ON(shared_dpll[i].crtc_mask);
4279 if (IS_BROXTON(dev_priv->dev)) {
4280 /* PLL is attached to port in bxt */
4281 struct intel_encoder *encoder;
4282 struct intel_digital_port *intel_dig_port;
4284 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4285 if (WARN_ON(!encoder))
4288 intel_dig_port = enc_to_dig_port(&encoder->base);
4289 /* 1:1 mapping between ports and PLLs */
4290 i = (enum intel_dpll_id)intel_dig_port->port;
4291 pll = &dev_priv->shared_dplls[i];
4292 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4293 crtc->base.base.id, pll->name);
4294 WARN_ON(shared_dpll[i].crtc_mask);
4297 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4298 /* Do not consider SPLL */
4301 for (i = 0; i < max; i++) {
4302 pll = &dev_priv->shared_dplls[i];
4304 /* Only want to check enabled timings first */
4305 if (shared_dpll[i].crtc_mask == 0)
4308 if (memcmp(&crtc_state->dpll_hw_state,
4309 &shared_dpll[i].hw_state,
4310 sizeof(crtc_state->dpll_hw_state)) == 0) {
4311 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4312 crtc->base.base.id, pll->name,
4313 shared_dpll[i].crtc_mask,
4319 /* Ok no matching timings, maybe there's a free one? */
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322 if (shared_dpll[i].crtc_mask == 0) {
4323 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4324 crtc->base.base.id, pll->name);
4332 if (shared_dpll[i].crtc_mask == 0)
4333 shared_dpll[i].hw_state =
4334 crtc_state->dpll_hw_state;
4336 crtc_state->shared_dpll = i;
4337 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4338 pipe_name(crtc->pipe));
4340 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4345 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4347 struct drm_i915_private *dev_priv = to_i915(state->dev);
4348 struct intel_shared_dpll_config *shared_dpll;
4349 struct intel_shared_dpll *pll;
4350 enum intel_dpll_id i;
4352 if (!to_intel_atomic_state(state)->dpll_set)
4355 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4356 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4357 pll = &dev_priv->shared_dplls[i];
4358 pll->config = shared_dpll[i];
4362 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4364 struct drm_i915_private *dev_priv = dev->dev_private;
4365 i915_reg_t dslreg = PIPEDSL(pipe);
4368 temp = I915_READ(dslreg);
4370 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4371 if (wait_for(I915_READ(dslreg) != temp, 5))
4372 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4377 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4378 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4379 int src_w, int src_h, int dst_w, int dst_h)
4381 struct intel_crtc_scaler_state *scaler_state =
4382 &crtc_state->scaler_state;
4383 struct intel_crtc *intel_crtc =
4384 to_intel_crtc(crtc_state->base.crtc);
4387 need_scaling = intel_rotation_90_or_270(rotation) ?
4388 (src_h != dst_w || src_w != dst_h):
4389 (src_w != dst_w || src_h != dst_h);
4392 * if plane is being disabled or scaler is no more required or force detach
4393 * - free scaler binded to this plane/crtc
4394 * - in order to do this, update crtc->scaler_usage
4396 * Here scaler state in crtc_state is set free so that
4397 * scaler can be assigned to other user. Actual register
4398 * update to free the scaler is done in plane/panel-fit programming.
4399 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4401 if (force_detach || !need_scaling) {
4402 if (*scaler_id >= 0) {
4403 scaler_state->scaler_users &= ~(1 << scaler_user);
4404 scaler_state->scalers[*scaler_id].in_use = 0;
4406 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4407 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4408 intel_crtc->pipe, scaler_user, *scaler_id,
4409 scaler_state->scaler_users);
4416 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4417 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4419 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4420 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4421 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4422 "size is out of scaler range\n",
4423 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4427 /* mark this plane as a scaler user in crtc_state */
4428 scaler_state->scaler_users |= (1 << scaler_user);
4429 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4430 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4431 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4432 scaler_state->scaler_users);
4438 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4440 * @state: crtc's scaler state
4443 * 0 - scaler_usage updated successfully
4444 * error - requested scaling cannot be supported or other error condition
4446 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4448 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4449 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4451 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4452 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4454 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4455 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4456 state->pipe_src_w, state->pipe_src_h,
4457 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4461 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4463 * @state: crtc's scaler state
4464 * @plane_state: atomic plane state to update
4467 * 0 - scaler_usage updated successfully
4468 * error - requested scaling cannot be supported or other error condition
4470 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4471 struct intel_plane_state *plane_state)
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4475 struct intel_plane *intel_plane =
4476 to_intel_plane(plane_state->base.plane);
4477 struct drm_framebuffer *fb = plane_state->base.fb;
4480 bool force_detach = !fb || !plane_state->visible;
4482 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4483 intel_plane->base.base.id, intel_crtc->pipe,
4484 drm_plane_index(&intel_plane->base));
4486 ret = skl_update_scaler(crtc_state, force_detach,
4487 drm_plane_index(&intel_plane->base),
4488 &plane_state->scaler_id,
4489 plane_state->base.rotation,
4490 drm_rect_width(&plane_state->src) >> 16,
4491 drm_rect_height(&plane_state->src) >> 16,
4492 drm_rect_width(&plane_state->dst),
4493 drm_rect_height(&plane_state->dst));
4495 if (ret || plane_state->scaler_id < 0)
4498 /* check colorkey */
4499 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4500 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4501 intel_plane->base.base.id);
4505 /* Check src format */
4506 switch (fb->pixel_format) {
4507 case DRM_FORMAT_RGB565:
4508 case DRM_FORMAT_XBGR8888:
4509 case DRM_FORMAT_XRGB8888:
4510 case DRM_FORMAT_ABGR8888:
4511 case DRM_FORMAT_ARGB8888:
4512 case DRM_FORMAT_XRGB2101010:
4513 case DRM_FORMAT_XBGR2101010:
4514 case DRM_FORMAT_YUYV:
4515 case DRM_FORMAT_YVYU:
4516 case DRM_FORMAT_UYVY:
4517 case DRM_FORMAT_VYUY:
4520 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4521 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4528 static void skylake_scaler_disable(struct intel_crtc *crtc)
4532 for (i = 0; i < crtc->num_scalers; i++)
4533 skl_detach_scaler(crtc, i);
4536 static void skylake_pfit_enable(struct intel_crtc *crtc)
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 int pipe = crtc->pipe;
4541 struct intel_crtc_scaler_state *scaler_state =
4542 &crtc->config->scaler_state;
4544 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4546 if (crtc->config->pch_pfit.enabled) {
4549 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4550 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4554 id = scaler_state->scaler_id;
4555 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4556 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4557 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4558 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4564 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566 struct drm_device *dev = crtc->base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 int pipe = crtc->pipe;
4570 if (crtc->config->pch_pfit.enabled) {
4571 /* Force use of hard-coded filter coefficients
4572 * as some pre-programmed values are broken,
4575 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4576 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4577 PF_PIPE_SEL_IVB(pipe));
4579 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4580 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4581 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4585 void hsw_enable_ips(struct intel_crtc *crtc)
4587 struct drm_device *dev = crtc->base.dev;
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4590 if (!crtc->config->ips_enabled)
4593 /* We can only enable IPS after we enable a plane and wait for a vblank */
4594 intel_wait_for_vblank(dev, crtc->pipe);
4596 assert_plane_enabled(dev_priv, crtc->plane);
4597 if (IS_BROADWELL(dev)) {
4598 mutex_lock(&dev_priv->rps.hw_lock);
4599 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4600 mutex_unlock(&dev_priv->rps.hw_lock);
4601 /* Quoting Art Runyan: "its not safe to expect any particular
4602 * value in IPS_CTL bit 31 after enabling IPS through the
4603 * mailbox." Moreover, the mailbox may return a bogus state,
4604 * so we need to just enable it and continue on.
4607 I915_WRITE(IPS_CTL, IPS_ENABLE);
4608 /* The bit only becomes 1 in the next vblank, so this wait here
4609 * is essentially intel_wait_for_vblank. If we don't have this
4610 * and don't wait for vblanks until the end of crtc_enable, then
4611 * the HW state readout code will complain that the expected
4612 * IPS_CTL value is not the one we read. */
4613 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4614 DRM_ERROR("Timed out waiting for IPS enable\n");
4618 void hsw_disable_ips(struct intel_crtc *crtc)
4620 struct drm_device *dev = crtc->base.dev;
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4623 if (!crtc->config->ips_enabled)
4626 assert_plane_enabled(dev_priv, crtc->plane);
4627 if (IS_BROADWELL(dev)) {
4628 mutex_lock(&dev_priv->rps.hw_lock);
4629 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4630 mutex_unlock(&dev_priv->rps.hw_lock);
4631 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4632 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4633 DRM_ERROR("Timed out waiting for IPS disable\n");
4635 I915_WRITE(IPS_CTL, 0);
4636 POSTING_READ(IPS_CTL);
4639 /* We need to wait for a vblank before we can disable the plane. */
4640 intel_wait_for_vblank(dev, crtc->pipe);
4643 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4644 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4646 struct drm_device *dev = crtc->dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 enum pipe pipe = intel_crtc->pipe;
4651 bool reenable_ips = false;
4653 /* The clocks have to be on to load the palette. */
4654 if (!crtc->state->active)
4657 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4658 if (intel_crtc->config->has_dsi_encoder)
4659 assert_dsi_pll_enabled(dev_priv);
4661 assert_pll_enabled(dev_priv, pipe);
4664 /* Workaround : Do not read or write the pipe palette/gamma data while
4665 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4667 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4668 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4669 GAMMA_MODE_MODE_SPLIT)) {
4670 hsw_disable_ips(intel_crtc);
4671 reenable_ips = true;
4674 for (i = 0; i < 256; i++) {
4677 if (HAS_GMCH_DISPLAY(dev))
4678 palreg = PALETTE(pipe, i);
4680 palreg = LGC_PALETTE(pipe, i);
4683 (intel_crtc->lut_r[i] << 16) |
4684 (intel_crtc->lut_g[i] << 8) |
4685 intel_crtc->lut_b[i]);
4689 hsw_enable_ips(intel_crtc);
4692 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4694 if (intel_crtc->overlay) {
4695 struct drm_device *dev = intel_crtc->base.dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4698 mutex_lock(&dev->struct_mutex);
4699 dev_priv->mm.interruptible = false;
4700 (void) intel_overlay_switch_off(intel_crtc->overlay);
4701 dev_priv->mm.interruptible = true;
4702 mutex_unlock(&dev->struct_mutex);
4705 /* Let userspace switch the overlay on again. In most cases userspace
4706 * has to recompute where to put it anyway.
4711 * intel_post_enable_primary - Perform operations after enabling primary plane
4712 * @crtc: the CRTC whose primary plane was just enabled
4714 * Performs potentially sleeping operations that must be done after the primary
4715 * plane is enabled, such as updating FBC and IPS. Note that this may be
4716 * called due to an explicit primary plane update, or due to an implicit
4717 * re-enable that is caused when a sprite plane is updated to no longer
4718 * completely hide the primary plane.
4721 intel_post_enable_primary(struct drm_crtc *crtc)
4723 struct drm_device *dev = crtc->dev;
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4726 int pipe = intel_crtc->pipe;
4729 * FIXME IPS should be fine as long as one plane is
4730 * enabled, but in practice it seems to have problems
4731 * when going from primary only to sprite only and vice
4734 hsw_enable_ips(intel_crtc);
4737 * Gen2 reports pipe underruns whenever all planes are disabled.
4738 * So don't enable underrun reporting before at least some planes
4740 * FIXME: Need to fix the logic to work when we turn off all planes
4741 * but leave the pipe running.
4744 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4746 /* Underruns don't always raise interrupts, so check manually. */
4747 intel_check_cpu_fifo_underruns(dev_priv);
4748 intel_check_pch_fifo_underruns(dev_priv);
4752 * intel_pre_disable_primary - Perform operations before disabling primary plane
4753 * @crtc: the CRTC whose primary plane is to be disabled
4755 * Performs potentially sleeping operations that must be done before the
4756 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4757 * be called due to an explicit primary plane update, or due to an implicit
4758 * disable that is caused when a sprite plane completely hides the primary
4762 intel_pre_disable_primary(struct drm_crtc *crtc)
4764 struct drm_device *dev = crtc->dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 int pipe = intel_crtc->pipe;
4770 * Gen2 reports pipe underruns whenever all planes are disabled.
4771 * So diasble underrun reporting before all the planes get disabled.
4772 * FIXME: Need to fix the logic to work when we turn off all planes
4773 * but leave the pipe running.
4776 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4779 * Vblank time updates from the shadow to live plane control register
4780 * are blocked if the memory self-refresh mode is active at that
4781 * moment. So to make sure the plane gets truly disabled, disable
4782 * first the self-refresh mode. The self-refresh enable bit in turn
4783 * will be checked/applied by the HW only at the next frame start
4784 * event which is after the vblank start event, so we need to have a
4785 * wait-for-vblank between disabling the plane and the pipe.
4787 if (HAS_GMCH_DISPLAY(dev)) {
4788 intel_set_memory_cxsr(dev_priv, false);
4789 dev_priv->wm.vlv.cxsr = false;
4790 intel_wait_for_vblank(dev, pipe);
4794 * FIXME IPS should be fine as long as one plane is
4795 * enabled, but in practice it seems to have problems
4796 * when going from primary only to sprite only and vice
4799 hsw_disable_ips(intel_crtc);
4802 static void intel_post_plane_update(struct intel_crtc *crtc)
4804 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4805 struct intel_crtc_state *pipe_config =
4806 to_intel_crtc_state(crtc->base.state);
4807 struct drm_device *dev = crtc->base.dev;
4809 if (atomic->wait_vblank)
4810 intel_wait_for_vblank(dev, crtc->pipe);
4812 intel_frontbuffer_flip(dev, atomic->fb_bits);
4814 crtc->wm.cxsr_allowed = true;
4816 if (pipe_config->wm_changed && pipe_config->base.active)
4817 intel_update_watermarks(&crtc->base);
4819 if (atomic->update_fbc)
4820 intel_fbc_update(crtc);
4822 if (atomic->post_enable_primary)
4823 intel_post_enable_primary(&crtc->base);
4825 memset(atomic, 0, sizeof(*atomic));
4828 static void intel_pre_plane_update(struct intel_crtc *crtc)
4830 struct drm_device *dev = crtc->base.dev;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4833 struct intel_crtc_state *pipe_config =
4834 to_intel_crtc_state(crtc->base.state);
4836 if (atomic->disable_fbc)
4837 intel_fbc_deactivate(crtc);
4839 if (crtc->atomic.disable_ips)
4840 hsw_disable_ips(crtc);
4842 if (atomic->pre_disable_primary)
4843 intel_pre_disable_primary(&crtc->base);
4845 if (pipe_config->disable_cxsr) {
4846 crtc->wm.cxsr_allowed = false;
4847 intel_set_memory_cxsr(dev_priv, false);
4850 if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4851 intel_update_watermarks(&crtc->base);
4854 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4856 struct drm_device *dev = crtc->dev;
4857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4858 struct drm_plane *p;
4859 int pipe = intel_crtc->pipe;
4861 intel_crtc_dpms_overlay_disable(intel_crtc);
4863 drm_for_each_plane_mask(p, dev, plane_mask)
4864 to_intel_plane(p)->disable_plane(p, crtc);
4867 * FIXME: Once we grow proper nuclear flip support out of this we need
4868 * to compute the mask of flip planes precisely. For the time being
4869 * consider this a flip to a NULL plane.
4871 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4874 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 struct intel_encoder *encoder;
4880 int pipe = intel_crtc->pipe;
4882 if (WARN_ON(intel_crtc->active))
4885 if (intel_crtc->config->has_pch_encoder)
4886 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4888 if (intel_crtc->config->has_pch_encoder)
4889 intel_prepare_shared_dpll(intel_crtc);
4891 if (intel_crtc->config->has_dp_encoder)
4892 intel_dp_set_m_n(intel_crtc, M1_N1);
4894 intel_set_pipe_timings(intel_crtc);
4896 if (intel_crtc->config->has_pch_encoder) {
4897 intel_cpu_transcoder_set_m_n(intel_crtc,
4898 &intel_crtc->config->fdi_m_n, NULL);
4901 ironlake_set_pipeconf(crtc);
4903 intel_crtc->active = true;
4905 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4907 for_each_encoder_on_crtc(dev, crtc, encoder)
4908 if (encoder->pre_enable)
4909 encoder->pre_enable(encoder);
4911 if (intel_crtc->config->has_pch_encoder) {
4912 /* Note: FDI PLL enabling _must_ be done before we enable the
4913 * cpu pipes, hence this is separate from all the other fdi/pch
4915 ironlake_fdi_pll_enable(intel_crtc);
4917 assert_fdi_tx_disabled(dev_priv, pipe);
4918 assert_fdi_rx_disabled(dev_priv, pipe);
4921 ironlake_pfit_enable(intel_crtc);
4924 * On ILK+ LUT must be loaded before the pipe is running but with
4927 intel_crtc_load_lut(crtc);
4929 intel_update_watermarks(crtc);
4930 intel_enable_pipe(intel_crtc);
4932 if (intel_crtc->config->has_pch_encoder)
4933 ironlake_pch_enable(crtc);
4935 assert_vblank_disabled(crtc);
4936 drm_crtc_vblank_on(crtc);
4938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 encoder->enable(encoder);
4941 if (HAS_PCH_CPT(dev))
4942 cpt_verify_modeset(dev, intel_crtc->pipe);
4944 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4945 if (intel_crtc->config->has_pch_encoder)
4946 intel_wait_for_vblank(dev, pipe);
4947 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4949 intel_fbc_enable(intel_crtc);
4952 /* IPS only exists on ULT machines and is tied to pipe A. */
4953 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4955 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4958 static void haswell_crtc_enable(struct drm_crtc *crtc)
4960 struct drm_device *dev = crtc->dev;
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4963 struct intel_encoder *encoder;
4964 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4965 struct intel_crtc_state *pipe_config =
4966 to_intel_crtc_state(crtc->state);
4968 if (WARN_ON(intel_crtc->active))
4971 if (intel_crtc->config->has_pch_encoder)
4972 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4975 if (intel_crtc_to_shared_dpll(intel_crtc))
4976 intel_enable_shared_dpll(intel_crtc);
4978 if (intel_crtc->config->has_dp_encoder)
4979 intel_dp_set_m_n(intel_crtc, M1_N1);
4981 intel_set_pipe_timings(intel_crtc);
4983 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4984 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4985 intel_crtc->config->pixel_multiplier - 1);
4988 if (intel_crtc->config->has_pch_encoder) {
4989 intel_cpu_transcoder_set_m_n(intel_crtc,
4990 &intel_crtc->config->fdi_m_n, NULL);
4993 haswell_set_pipeconf(crtc);
4995 intel_set_pipe_csc(crtc);
4997 intel_crtc->active = true;
4999 if (intel_crtc->config->has_pch_encoder)
5000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5004 for_each_encoder_on_crtc(dev, crtc, encoder) {
5005 if (encoder->pre_enable)
5006 encoder->pre_enable(encoder);
5009 if (intel_crtc->config->has_pch_encoder)
5010 dev_priv->display.fdi_link_train(crtc);
5012 if (!intel_crtc->config->has_dsi_encoder)
5013 intel_ddi_enable_pipe_clock(intel_crtc);
5015 if (INTEL_INFO(dev)->gen >= 9)
5016 skylake_pfit_enable(intel_crtc);
5018 ironlake_pfit_enable(intel_crtc);
5021 * On ILK+ LUT must be loaded before the pipe is running but with
5024 intel_crtc_load_lut(crtc);
5026 intel_ddi_set_pipe_settings(crtc);
5027 if (!intel_crtc->config->has_dsi_encoder)
5028 intel_ddi_enable_transcoder_func(crtc);
5030 intel_update_watermarks(crtc);
5031 intel_enable_pipe(intel_crtc);
5033 if (intel_crtc->config->has_pch_encoder)
5034 lpt_pch_enable(crtc);
5036 if (intel_crtc->config->dp_encoder_is_mst)
5037 intel_ddi_set_vc_payload_alloc(crtc, true);
5039 assert_vblank_disabled(crtc);
5040 drm_crtc_vblank_on(crtc);
5042 for_each_encoder_on_crtc(dev, crtc, encoder) {
5043 encoder->enable(encoder);
5044 intel_opregion_notify_encoder(encoder, true);
5047 if (intel_crtc->config->has_pch_encoder) {
5048 intel_wait_for_vblank(dev, pipe);
5049 intel_wait_for_vblank(dev, pipe);
5050 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5051 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5055 /* If we change the relative order between pipe/planes enabling, we need
5056 * to change the workaround. */
5057 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5058 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5059 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5060 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5063 intel_fbc_enable(intel_crtc);
5066 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5068 struct drm_device *dev = crtc->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 int pipe = crtc->pipe;
5072 /* To avoid upsetting the power well on haswell only disable the pfit if
5073 * it's in use. The hw state code will make sure we get this right. */
5074 if (force || crtc->config->pch_pfit.enabled) {
5075 I915_WRITE(PF_CTL(pipe), 0);
5076 I915_WRITE(PF_WIN_POS(pipe), 0);
5077 I915_WRITE(PF_WIN_SZ(pipe), 0);
5081 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5083 struct drm_device *dev = crtc->dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086 struct intel_encoder *encoder;
5087 int pipe = intel_crtc->pipe;
5089 if (intel_crtc->config->has_pch_encoder)
5090 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5092 for_each_encoder_on_crtc(dev, crtc, encoder)
5093 encoder->disable(encoder);
5095 drm_crtc_vblank_off(crtc);
5096 assert_vblank_disabled(crtc);
5099 * Sometimes spurious CPU pipe underruns happen when the
5100 * pipe is already disabled, but FDI RX/TX is still enabled.
5101 * Happens at least with VGA+HDMI cloning. Suppress them.
5103 if (intel_crtc->config->has_pch_encoder)
5104 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5106 intel_disable_pipe(intel_crtc);
5108 ironlake_pfit_disable(intel_crtc, false);
5110 if (intel_crtc->config->has_pch_encoder) {
5111 ironlake_fdi_disable(crtc);
5112 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
5119 if (intel_crtc->config->has_pch_encoder) {
5120 ironlake_disable_pch_transcoder(dev_priv, pipe);
5122 if (HAS_PCH_CPT(dev)) {
5126 /* disable TRANS_DP_CTL */
5127 reg = TRANS_DP_CTL(pipe);
5128 temp = I915_READ(reg);
5129 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5130 TRANS_DP_PORT_SEL_MASK);
5131 temp |= TRANS_DP_PORT_SEL_NONE;
5132 I915_WRITE(reg, temp);
5134 /* disable DPLL_SEL */
5135 temp = I915_READ(PCH_DPLL_SEL);
5136 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5137 I915_WRITE(PCH_DPLL_SEL, temp);
5140 ironlake_fdi_pll_disable(intel_crtc);
5143 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5145 intel_fbc_disable_crtc(intel_crtc);
5148 static void haswell_crtc_disable(struct drm_crtc *crtc)
5150 struct drm_device *dev = crtc->dev;
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153 struct intel_encoder *encoder;
5154 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5156 if (intel_crtc->config->has_pch_encoder)
5157 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5160 for_each_encoder_on_crtc(dev, crtc, encoder) {
5161 intel_opregion_notify_encoder(encoder, false);
5162 encoder->disable(encoder);
5165 drm_crtc_vblank_off(crtc);
5166 assert_vblank_disabled(crtc);
5168 intel_disable_pipe(intel_crtc);
5170 if (intel_crtc->config->dp_encoder_is_mst)
5171 intel_ddi_set_vc_payload_alloc(crtc, false);
5173 if (!intel_crtc->config->has_dsi_encoder)
5174 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5176 if (INTEL_INFO(dev)->gen >= 9)
5177 skylake_scaler_disable(intel_crtc);
5179 ironlake_pfit_disable(intel_crtc, false);
5181 if (!intel_crtc->config->has_dsi_encoder)
5182 intel_ddi_disable_pipe_clock(intel_crtc);
5184 for_each_encoder_on_crtc(dev, crtc, encoder)
5185 if (encoder->post_disable)
5186 encoder->post_disable(encoder);
5188 if (intel_crtc->config->has_pch_encoder) {
5189 lpt_disable_pch_transcoder(dev_priv);
5190 lpt_disable_iclkip(dev_priv);
5191 intel_ddi_fdi_disable(crtc);
5193 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5197 intel_fbc_disable_crtc(intel_crtc);
5200 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5202 struct drm_device *dev = crtc->base.dev;
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204 struct intel_crtc_state *pipe_config = crtc->config;
5206 if (!pipe_config->gmch_pfit.control)
5210 * The panel fitter should only be adjusted whilst the pipe is disabled,
5211 * according to register description and PRM.
5213 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5214 assert_pipe_disabled(dev_priv, crtc->pipe);
5216 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5217 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5219 /* Border color in case we don't scale up to the full screen. Black by
5220 * default, change to something else for debugging. */
5221 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5224 static enum intel_display_power_domain port_to_power_domain(enum port port)
5228 return POWER_DOMAIN_PORT_DDI_A_LANES;
5230 return POWER_DOMAIN_PORT_DDI_B_LANES;
5232 return POWER_DOMAIN_PORT_DDI_C_LANES;
5234 return POWER_DOMAIN_PORT_DDI_D_LANES;
5236 return POWER_DOMAIN_PORT_DDI_E_LANES;
5239 return POWER_DOMAIN_PORT_OTHER;
5243 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5247 return POWER_DOMAIN_AUX_A;
5249 return POWER_DOMAIN_AUX_B;
5251 return POWER_DOMAIN_AUX_C;
5253 return POWER_DOMAIN_AUX_D;
5255 /* FIXME: Check VBT for actual wiring of PORT E */
5256 return POWER_DOMAIN_AUX_D;
5259 return POWER_DOMAIN_AUX_A;
5263 enum intel_display_power_domain
5264 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5266 struct drm_device *dev = intel_encoder->base.dev;
5267 struct intel_digital_port *intel_dig_port;
5269 switch (intel_encoder->type) {
5270 case INTEL_OUTPUT_UNKNOWN:
5271 /* Only DDI platforms should ever use this output type */
5272 WARN_ON_ONCE(!HAS_DDI(dev));
5273 case INTEL_OUTPUT_DISPLAYPORT:
5274 case INTEL_OUTPUT_HDMI:
5275 case INTEL_OUTPUT_EDP:
5276 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5277 return port_to_power_domain(intel_dig_port->port);
5278 case INTEL_OUTPUT_DP_MST:
5279 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5280 return port_to_power_domain(intel_dig_port->port);
5281 case INTEL_OUTPUT_ANALOG:
5282 return POWER_DOMAIN_PORT_CRT;
5283 case INTEL_OUTPUT_DSI:
5284 return POWER_DOMAIN_PORT_DSI;
5286 return POWER_DOMAIN_PORT_OTHER;
5290 enum intel_display_power_domain
5291 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5293 struct drm_device *dev = intel_encoder->base.dev;
5294 struct intel_digital_port *intel_dig_port;
5296 switch (intel_encoder->type) {
5297 case INTEL_OUTPUT_UNKNOWN:
5298 case INTEL_OUTPUT_HDMI:
5300 * Only DDI platforms should ever use these output types.
5301 * We can get here after the HDMI detect code has already set
5302 * the type of the shared encoder. Since we can't be sure
5303 * what's the status of the given connectors, play safe and
5304 * run the DP detection too.
5306 WARN_ON_ONCE(!HAS_DDI(dev));
5307 case INTEL_OUTPUT_DISPLAYPORT:
5308 case INTEL_OUTPUT_EDP:
5309 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5310 return port_to_aux_power_domain(intel_dig_port->port);
5311 case INTEL_OUTPUT_DP_MST:
5312 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5313 return port_to_aux_power_domain(intel_dig_port->port);
5315 MISSING_CASE(intel_encoder->type);
5316 return POWER_DOMAIN_AUX_A;
5320 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5322 struct drm_device *dev = crtc->dev;
5323 struct intel_encoder *intel_encoder;
5324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5325 enum pipe pipe = intel_crtc->pipe;
5327 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5329 if (!crtc->state->active)
5332 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5333 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5334 if (intel_crtc->config->pch_pfit.enabled ||
5335 intel_crtc->config->pch_pfit.force_thru)
5336 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5338 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5339 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5344 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5346 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 enum intel_display_power_domain domain;
5349 unsigned long domains, new_domains, old_domains;
5351 old_domains = intel_crtc->enabled_power_domains;
5352 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5354 domains = new_domains & ~old_domains;
5356 for_each_power_domain(domain, domains)
5357 intel_display_power_get(dev_priv, domain);
5359 return old_domains & ~new_domains;
5362 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5363 unsigned long domains)
5365 enum intel_display_power_domain domain;
5367 for_each_power_domain(domain, domains)
5368 intel_display_power_put(dev_priv, domain);
5371 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5373 struct drm_device *dev = state->dev;
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 unsigned long put_domains[I915_MAX_PIPES] = {};
5376 struct drm_crtc_state *crtc_state;
5377 struct drm_crtc *crtc;
5380 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5381 if (needs_modeset(crtc->state))
5382 put_domains[to_intel_crtc(crtc)->pipe] =
5383 modeset_get_crtc_power_domains(crtc);
5386 if (dev_priv->display.modeset_commit_cdclk) {
5387 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5389 if (cdclk != dev_priv->cdclk_freq &&
5390 !WARN_ON(!state->allow_modeset))
5391 dev_priv->display.modeset_commit_cdclk(state);
5394 for (i = 0; i < I915_MAX_PIPES; i++)
5396 modeset_put_power_domains(dev_priv, put_domains[i]);
5399 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5401 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5403 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5404 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5405 return max_cdclk_freq;
5406 else if (IS_CHERRYVIEW(dev_priv))
5407 return max_cdclk_freq*95/100;
5408 else if (INTEL_INFO(dev_priv)->gen < 4)
5409 return 2*max_cdclk_freq*90/100;
5411 return max_cdclk_freq*90/100;
5414 static void intel_update_max_cdclk(struct drm_device *dev)
5416 struct drm_i915_private *dev_priv = dev->dev_private;
5418 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5419 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5421 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5422 dev_priv->max_cdclk_freq = 675000;
5423 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5424 dev_priv->max_cdclk_freq = 540000;
5425 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5426 dev_priv->max_cdclk_freq = 450000;
5428 dev_priv->max_cdclk_freq = 337500;
5429 } else if (IS_BROADWELL(dev)) {
5431 * FIXME with extra cooling we can allow
5432 * 540 MHz for ULX and 675 Mhz for ULT.
5433 * How can we know if extra cooling is
5434 * available? PCI ID, VTB, something else?
5436 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5437 dev_priv->max_cdclk_freq = 450000;
5438 else if (IS_BDW_ULX(dev))
5439 dev_priv->max_cdclk_freq = 450000;
5440 else if (IS_BDW_ULT(dev))
5441 dev_priv->max_cdclk_freq = 540000;
5443 dev_priv->max_cdclk_freq = 675000;
5444 } else if (IS_CHERRYVIEW(dev)) {
5445 dev_priv->max_cdclk_freq = 320000;
5446 } else if (IS_VALLEYVIEW(dev)) {
5447 dev_priv->max_cdclk_freq = 400000;
5449 /* otherwise assume cdclk is fixed */
5450 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5453 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5455 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5456 dev_priv->max_cdclk_freq);
5458 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5459 dev_priv->max_dotclk_freq);
5462 static void intel_update_cdclk(struct drm_device *dev)
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5466 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5467 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5468 dev_priv->cdclk_freq);
5471 * Program the gmbus_freq based on the cdclk frequency.
5472 * BSpec erroneously claims we should aim for 4MHz, but
5473 * in fact 1MHz is the correct frequency.
5475 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5477 * Program the gmbus_freq based on the cdclk frequency.
5478 * BSpec erroneously claims we should aim for 4MHz, but
5479 * in fact 1MHz is the correct frequency.
5481 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5484 if (dev_priv->max_cdclk_freq == 0)
5485 intel_update_max_cdclk(dev);
5488 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5493 uint32_t current_freq;
5496 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5497 switch (frequency) {
5499 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5500 ratio = BXT_DE_PLL_RATIO(60);
5503 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5504 ratio = BXT_DE_PLL_RATIO(60);
5507 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5508 ratio = BXT_DE_PLL_RATIO(60);
5511 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5512 ratio = BXT_DE_PLL_RATIO(60);
5515 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5516 ratio = BXT_DE_PLL_RATIO(65);
5520 * Bypass frequency with DE PLL disabled. Init ratio, divider
5521 * to suppress GCC warning.
5527 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5532 mutex_lock(&dev_priv->rps.hw_lock);
5533 /* Inform power controller of upcoming frequency change */
5534 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5536 mutex_unlock(&dev_priv->rps.hw_lock);
5539 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5544 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5545 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5546 current_freq = current_freq * 500 + 1000;
5549 * DE PLL has to be disabled when
5550 * - setting to 19.2MHz (bypass, PLL isn't used)
5551 * - before setting to 624MHz (PLL needs toggling)
5552 * - before setting to any frequency from 624MHz (PLL needs toggling)
5554 if (frequency == 19200 || frequency == 624000 ||
5555 current_freq == 624000) {
5556 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5558 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5560 DRM_ERROR("timout waiting for DE PLL unlock\n");
5563 if (frequency != 19200) {
5566 val = I915_READ(BXT_DE_PLL_CTL);
5567 val &= ~BXT_DE_PLL_RATIO_MASK;
5569 I915_WRITE(BXT_DE_PLL_CTL, val);
5571 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5573 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5574 DRM_ERROR("timeout waiting for DE PLL lock\n");
5576 val = I915_READ(CDCLK_CTL);
5577 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5580 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5583 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5584 if (frequency >= 500000)
5585 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5587 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5588 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5589 val |= (frequency - 1000) / 500;
5590 I915_WRITE(CDCLK_CTL, val);
5593 mutex_lock(&dev_priv->rps.hw_lock);
5594 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5595 DIV_ROUND_UP(frequency, 25000));
5596 mutex_unlock(&dev_priv->rps.hw_lock);
5599 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5604 intel_update_cdclk(dev);
5607 void broxton_init_cdclk(struct drm_device *dev)
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5613 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5614 * or else the reset will hang because there is no PCH to respond.
5615 * Move the handshake programming to initialization sequence.
5616 * Previously was left up to BIOS.
5618 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5619 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5620 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5622 /* Enable PG1 for cdclk */
5623 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5625 /* check if cd clock is enabled */
5626 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5627 DRM_DEBUG_KMS("Display already initialized\n");
5633 * - The initial CDCLK needs to be read from VBT.
5634 * Need to make this change after VBT has changes for BXT.
5635 * - check if setting the max (or any) cdclk freq is really necessary
5636 * here, it belongs to modeset time
5638 broxton_set_cdclk(dev, 624000);
5640 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5641 POSTING_READ(DBUF_CTL);
5645 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5646 DRM_ERROR("DBuf power enable timeout!\n");
5649 void broxton_uninit_cdclk(struct drm_device *dev)
5651 struct drm_i915_private *dev_priv = dev->dev_private;
5653 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5654 POSTING_READ(DBUF_CTL);
5658 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5659 DRM_ERROR("DBuf power disable timeout!\n");
5661 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5662 broxton_set_cdclk(dev, 19200);
5664 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5667 static const struct skl_cdclk_entry {
5670 } skl_cdclk_frequencies[] = {
5671 { .freq = 308570, .vco = 8640 },
5672 { .freq = 337500, .vco = 8100 },
5673 { .freq = 432000, .vco = 8640 },
5674 { .freq = 450000, .vco = 8100 },
5675 { .freq = 540000, .vco = 8100 },
5676 { .freq = 617140, .vco = 8640 },
5677 { .freq = 675000, .vco = 8100 },
5680 static unsigned int skl_cdclk_decimal(unsigned int freq)
5682 return (freq - 1000) / 500;
5685 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5689 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5690 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5692 if (e->freq == freq)
5700 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5702 unsigned int min_freq;
5705 /* select the minimum CDCLK before enabling DPLL 0 */
5706 val = I915_READ(CDCLK_CTL);
5707 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5708 val |= CDCLK_FREQ_337_308;
5710 if (required_vco == 8640)
5715 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5717 I915_WRITE(CDCLK_CTL, val);
5718 POSTING_READ(CDCLK_CTL);
5721 * We always enable DPLL0 with the lowest link rate possible, but still
5722 * taking into account the VCO required to operate the eDP panel at the
5723 * desired frequency. The usual DP link rates operate with a VCO of
5724 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5725 * The modeset code is responsible for the selection of the exact link
5726 * rate later on, with the constraint of choosing a frequency that
5727 * works with required_vco.
5729 val = I915_READ(DPLL_CTRL1);
5731 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5732 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5733 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5734 if (required_vco == 8640)
5735 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5738 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5741 I915_WRITE(DPLL_CTRL1, val);
5742 POSTING_READ(DPLL_CTRL1);
5744 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5746 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5747 DRM_ERROR("DPLL0 not locked\n");
5750 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5755 /* inform PCU we want to change CDCLK */
5756 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5757 mutex_lock(&dev_priv->rps.hw_lock);
5758 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5759 mutex_unlock(&dev_priv->rps.hw_lock);
5761 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5764 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5768 for (i = 0; i < 15; i++) {
5769 if (skl_cdclk_pcu_ready(dev_priv))
5777 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5779 struct drm_device *dev = dev_priv->dev;
5780 u32 freq_select, pcu_ack;
5782 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5784 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5785 DRM_ERROR("failed to inform PCU about cdclk change\n");
5793 freq_select = CDCLK_FREQ_450_432;
5797 freq_select = CDCLK_FREQ_540;
5803 freq_select = CDCLK_FREQ_337_308;
5808 freq_select = CDCLK_FREQ_675_617;
5813 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5814 POSTING_READ(CDCLK_CTL);
5816 /* inform PCU of the change */
5817 mutex_lock(&dev_priv->rps.hw_lock);
5818 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5819 mutex_unlock(&dev_priv->rps.hw_lock);
5821 intel_update_cdclk(dev);
5824 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5826 /* disable DBUF power */
5827 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5828 POSTING_READ(DBUF_CTL);
5832 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5833 DRM_ERROR("DBuf power disable timeout\n");
5836 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5837 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5838 DRM_ERROR("Couldn't disable DPLL0\n");
5841 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5843 unsigned int required_vco;
5845 /* DPLL0 not enabled (happens on early BIOS versions) */
5846 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5848 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5849 skl_dpll0_enable(dev_priv, required_vco);
5852 /* set CDCLK to the frequency the BIOS chose */
5853 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5855 /* enable DBUF power */
5856 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5857 POSTING_READ(DBUF_CTL);
5861 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5862 DRM_ERROR("DBuf power enable timeout\n");
5865 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5867 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5868 uint32_t cdctl = I915_READ(CDCLK_CTL);
5869 int freq = dev_priv->skl_boot_cdclk;
5872 * check if the pre-os intialized the display
5873 * There is SWF18 scratchpad register defined which is set by the
5874 * pre-os which can be used by the OS drivers to check the status
5876 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5879 /* Is PLL enabled and locked ? */
5880 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5883 /* DPLL okay; verify the cdclock
5885 * Noticed in some instances that the freq selection is correct but
5886 * decimal part is programmed wrong from BIOS where pre-os does not
5887 * enable display. Verify the same as well.
5889 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5890 /* All well; nothing to sanitize */
5894 * As of now initialize with max cdclk till
5895 * we get dynamic cdclk support
5897 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5898 skl_init_cdclk(dev_priv);
5900 /* we did have to sanitize */
5904 /* Adjust CDclk dividers to allow high res or save power if possible */
5905 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5907 struct drm_i915_private *dev_priv = dev->dev_private;
5910 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5911 != dev_priv->cdclk_freq);
5913 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5915 else if (cdclk == 266667)
5920 mutex_lock(&dev_priv->rps.hw_lock);
5921 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5922 val &= ~DSPFREQGUAR_MASK;
5923 val |= (cmd << DSPFREQGUAR_SHIFT);
5924 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5925 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5926 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5928 DRM_ERROR("timed out waiting for CDclk change\n");
5930 mutex_unlock(&dev_priv->rps.hw_lock);
5932 mutex_lock(&dev_priv->sb_lock);
5934 if (cdclk == 400000) {
5937 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5939 /* adjust cdclk divider */
5940 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5941 val &= ~CCK_FREQUENCY_VALUES;
5943 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5945 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5946 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5948 DRM_ERROR("timed out waiting for CDclk change\n");
5951 /* adjust self-refresh exit latency value */
5952 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5956 * For high bandwidth configs, we set a higher latency in the bunit
5957 * so that the core display fetch happens in time to avoid underruns.
5959 if (cdclk == 400000)
5960 val |= 4500 / 250; /* 4.5 usec */
5962 val |= 3000 / 250; /* 3.0 usec */
5963 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5965 mutex_unlock(&dev_priv->sb_lock);
5967 intel_update_cdclk(dev);
5970 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5975 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5976 != dev_priv->cdclk_freq);
5985 MISSING_CASE(cdclk);
5990 * Specs are full of misinformation, but testing on actual
5991 * hardware has shown that we just need to write the desired
5992 * CCK divider into the Punit register.
5994 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5996 mutex_lock(&dev_priv->rps.hw_lock);
5997 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5998 val &= ~DSPFREQGUAR_MASK_CHV;
5999 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6000 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6001 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6002 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6004 DRM_ERROR("timed out waiting for CDclk change\n");
6006 mutex_unlock(&dev_priv->rps.hw_lock);
6008 intel_update_cdclk(dev);
6011 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6014 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6015 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6018 * Really only a few cases to deal with, as only 4 CDclks are supported:
6021 * 320/333MHz (depends on HPLL freq)
6023 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6024 * of the lower bin and adjust if needed.
6026 * We seem to get an unstable or solid color picture at 200MHz.
6027 * Not sure what's wrong. For now use 200MHz only when all pipes
6030 if (!IS_CHERRYVIEW(dev_priv) &&
6031 max_pixclk > freq_320*limit/100)
6033 else if (max_pixclk > 266667*limit/100)
6035 else if (max_pixclk > 0)
6041 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6046 * - remove the guardband, it's not needed on BXT
6047 * - set 19.2MHz bypass frequency if there are no active pipes
6049 if (max_pixclk > 576000*9/10)
6051 else if (max_pixclk > 384000*9/10)
6053 else if (max_pixclk > 288000*9/10)
6055 else if (max_pixclk > 144000*9/10)
6061 /* Compute the max pixel clock for new configuration. Uses atomic state if
6062 * that's non-NULL, look at current state otherwise. */
6063 static int intel_mode_max_pixclk(struct drm_device *dev,
6064 struct drm_atomic_state *state)
6066 struct intel_crtc *intel_crtc;
6067 struct intel_crtc_state *crtc_state;
6070 for_each_intel_crtc(dev, intel_crtc) {
6071 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6072 if (IS_ERR(crtc_state))
6073 return PTR_ERR(crtc_state);
6075 if (!crtc_state->base.enable)
6078 max_pixclk = max(max_pixclk,
6079 crtc_state->base.adjusted_mode.crtc_clock);
6085 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6087 struct drm_device *dev = state->dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089 int max_pixclk = intel_mode_max_pixclk(dev, state);
6094 to_intel_atomic_state(state)->cdclk =
6095 valleyview_calc_cdclk(dev_priv, max_pixclk);
6100 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6102 struct drm_device *dev = state->dev;
6103 struct drm_i915_private *dev_priv = dev->dev_private;
6104 int max_pixclk = intel_mode_max_pixclk(dev, state);
6109 to_intel_atomic_state(state)->cdclk =
6110 broxton_calc_cdclk(dev_priv, max_pixclk);
6115 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6117 unsigned int credits, default_credits;
6119 if (IS_CHERRYVIEW(dev_priv))
6120 default_credits = PFI_CREDIT(12);
6122 default_credits = PFI_CREDIT(8);
6124 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6125 /* CHV suggested value is 31 or 63 */
6126 if (IS_CHERRYVIEW(dev_priv))
6127 credits = PFI_CREDIT_63;
6129 credits = PFI_CREDIT(15);
6131 credits = default_credits;
6135 * WA - write default credits before re-programming
6136 * FIXME: should we also set the resend bit here?
6138 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6141 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6142 credits | PFI_CREDIT_RESEND);
6145 * FIXME is this guaranteed to clear
6146 * immediately or should we poll for it?
6148 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6151 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6153 struct drm_device *dev = old_state->dev;
6154 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6158 * FIXME: We can end up here with all power domains off, yet
6159 * with a CDCLK frequency other than the minimum. To account
6160 * for this take the PIPE-A power domain, which covers the HW
6161 * blocks needed for the following programming. This can be
6162 * removed once it's guaranteed that we get here either with
6163 * the minimum CDCLK set, or the required power domains
6166 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6168 if (IS_CHERRYVIEW(dev))
6169 cherryview_set_cdclk(dev, req_cdclk);
6171 valleyview_set_cdclk(dev, req_cdclk);
6173 vlv_program_pfi_credits(dev_priv);
6175 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6178 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6180 struct drm_device *dev = crtc->dev;
6181 struct drm_i915_private *dev_priv = to_i915(dev);
6182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6183 struct intel_encoder *encoder;
6184 int pipe = intel_crtc->pipe;
6186 if (WARN_ON(intel_crtc->active))
6189 if (intel_crtc->config->has_dp_encoder)
6190 intel_dp_set_m_n(intel_crtc, M1_N1);
6192 intel_set_pipe_timings(intel_crtc);
6194 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6197 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6198 I915_WRITE(CHV_CANVAS(pipe), 0);
6201 i9xx_set_pipeconf(intel_crtc);
6203 intel_crtc->active = true;
6205 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6207 for_each_encoder_on_crtc(dev, crtc, encoder)
6208 if (encoder->pre_pll_enable)
6209 encoder->pre_pll_enable(encoder);
6211 if (!intel_crtc->config->has_dsi_encoder) {
6212 if (IS_CHERRYVIEW(dev)) {
6213 chv_prepare_pll(intel_crtc, intel_crtc->config);
6214 chv_enable_pll(intel_crtc, intel_crtc->config);
6216 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6217 vlv_enable_pll(intel_crtc, intel_crtc->config);
6221 for_each_encoder_on_crtc(dev, crtc, encoder)
6222 if (encoder->pre_enable)
6223 encoder->pre_enable(encoder);
6225 i9xx_pfit_enable(intel_crtc);
6227 intel_crtc_load_lut(crtc);
6229 intel_enable_pipe(intel_crtc);
6231 assert_vblank_disabled(crtc);
6232 drm_crtc_vblank_on(crtc);
6234 for_each_encoder_on_crtc(dev, crtc, encoder)
6235 encoder->enable(encoder);
6238 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6240 struct drm_device *dev = crtc->base.dev;
6241 struct drm_i915_private *dev_priv = dev->dev_private;
6243 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6244 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6247 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6249 struct drm_device *dev = crtc->dev;
6250 struct drm_i915_private *dev_priv = to_i915(dev);
6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252 struct intel_encoder *encoder;
6253 int pipe = intel_crtc->pipe;
6255 if (WARN_ON(intel_crtc->active))
6258 i9xx_set_pll_dividers(intel_crtc);
6260 if (intel_crtc->config->has_dp_encoder)
6261 intel_dp_set_m_n(intel_crtc, M1_N1);
6263 intel_set_pipe_timings(intel_crtc);
6265 i9xx_set_pipeconf(intel_crtc);
6267 intel_crtc->active = true;
6270 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6272 for_each_encoder_on_crtc(dev, crtc, encoder)
6273 if (encoder->pre_enable)
6274 encoder->pre_enable(encoder);
6276 i9xx_enable_pll(intel_crtc);
6278 i9xx_pfit_enable(intel_crtc);
6280 intel_crtc_load_lut(crtc);
6282 intel_update_watermarks(crtc);
6283 intel_enable_pipe(intel_crtc);
6285 assert_vblank_disabled(crtc);
6286 drm_crtc_vblank_on(crtc);
6288 for_each_encoder_on_crtc(dev, crtc, encoder)
6289 encoder->enable(encoder);
6291 intel_fbc_enable(intel_crtc);
6294 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6296 struct drm_device *dev = crtc->base.dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6299 if (!crtc->config->gmch_pfit.control)
6302 assert_pipe_disabled(dev_priv, crtc->pipe);
6304 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6305 I915_READ(PFIT_CONTROL));
6306 I915_WRITE(PFIT_CONTROL, 0);
6309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314 struct intel_encoder *encoder;
6315 int pipe = intel_crtc->pipe;
6318 * On gen2 planes are double buffered but the pipe isn't, so we must
6319 * wait for planes to fully turn off before disabling the pipe.
6320 * We also need to wait on all gmch platforms because of the
6321 * self-refresh mode constraint explained above.
6323 intel_wait_for_vblank(dev, pipe);
6325 for_each_encoder_on_crtc(dev, crtc, encoder)
6326 encoder->disable(encoder);
6328 drm_crtc_vblank_off(crtc);
6329 assert_vblank_disabled(crtc);
6331 intel_disable_pipe(intel_crtc);
6333 i9xx_pfit_disable(intel_crtc);
6335 for_each_encoder_on_crtc(dev, crtc, encoder)
6336 if (encoder->post_disable)
6337 encoder->post_disable(encoder);
6339 if (!intel_crtc->config->has_dsi_encoder) {
6340 if (IS_CHERRYVIEW(dev))
6341 chv_disable_pll(dev_priv, pipe);
6342 else if (IS_VALLEYVIEW(dev))
6343 vlv_disable_pll(dev_priv, pipe);
6345 i9xx_disable_pll(intel_crtc);
6348 for_each_encoder_on_crtc(dev, crtc, encoder)
6349 if (encoder->post_pll_disable)
6350 encoder->post_pll_disable(encoder);
6353 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6355 intel_fbc_disable_crtc(intel_crtc);
6358 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6362 enum intel_display_power_domain domain;
6363 unsigned long domains;
6365 if (!intel_crtc->active)
6368 if (to_intel_plane_state(crtc->primary->state)->visible) {
6369 WARN_ON(intel_crtc->unpin_work);
6371 intel_pre_disable_primary(crtc);
6373 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6374 to_intel_plane_state(crtc->primary->state)->visible = false;
6377 dev_priv->display.crtc_disable(crtc);
6378 intel_crtc->active = false;
6379 intel_update_watermarks(crtc);
6380 intel_disable_shared_dpll(intel_crtc);
6382 domains = intel_crtc->enabled_power_domains;
6383 for_each_power_domain(domain, domains)
6384 intel_display_power_put(dev_priv, domain);
6385 intel_crtc->enabled_power_domains = 0;
6389 * turn all crtc's off, but do not adjust state
6390 * This has to be paired with a call to intel_modeset_setup_hw_state.
6392 int intel_display_suspend(struct drm_device *dev)
6394 struct drm_mode_config *config = &dev->mode_config;
6395 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6396 struct drm_atomic_state *state;
6397 struct drm_crtc *crtc;
6398 unsigned crtc_mask = 0;
6404 lockdep_assert_held(&ctx->ww_ctx);
6405 state = drm_atomic_state_alloc(dev);
6406 if (WARN_ON(!state))
6409 state->acquire_ctx = ctx;
6410 state->allow_modeset = true;
6412 for_each_crtc(dev, crtc) {
6413 struct drm_crtc_state *crtc_state =
6414 drm_atomic_get_crtc_state(state, crtc);
6416 ret = PTR_ERR_OR_ZERO(crtc_state);
6420 if (!crtc_state->active)
6423 crtc_state->active = false;
6424 crtc_mask |= 1 << drm_crtc_index(crtc);
6428 ret = drm_atomic_commit(state);
6431 for_each_crtc(dev, crtc)
6432 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6433 crtc->state->active = true;
6441 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6442 drm_atomic_state_free(state);
6446 void intel_encoder_destroy(struct drm_encoder *encoder)
6448 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6450 drm_encoder_cleanup(encoder);
6451 kfree(intel_encoder);
6454 /* Cross check the actual hw state with our own modeset state tracking (and it's
6455 * internal consistency). */
6456 static void intel_connector_check_state(struct intel_connector *connector)
6458 struct drm_crtc *crtc = connector->base.state->crtc;
6460 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6461 connector->base.base.id,
6462 connector->base.name);
6464 if (connector->get_hw_state(connector)) {
6465 struct intel_encoder *encoder = connector->encoder;
6466 struct drm_connector_state *conn_state = connector->base.state;
6468 I915_STATE_WARN(!crtc,
6469 "connector enabled without attached crtc\n");
6474 I915_STATE_WARN(!crtc->state->active,
6475 "connector is active, but attached crtc isn't\n");
6477 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6480 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6481 "atomic encoder doesn't match attached encoder\n");
6483 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6484 "attached encoder crtc differs from connector crtc\n");
6486 I915_STATE_WARN(crtc && crtc->state->active,
6487 "attached crtc is active, but connector isn't\n");
6488 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6489 "best encoder set without crtc!\n");
6493 int intel_connector_init(struct intel_connector *connector)
6495 drm_atomic_helper_connector_reset(&connector->base);
6497 if (!connector->base.state)
6503 struct intel_connector *intel_connector_alloc(void)
6505 struct intel_connector *connector;
6507 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6511 if (intel_connector_init(connector) < 0) {
6519 /* Simple connector->get_hw_state implementation for encoders that support only
6520 * one connector and no cloning and hence the encoder state determines the state
6521 * of the connector. */
6522 bool intel_connector_get_hw_state(struct intel_connector *connector)
6525 struct intel_encoder *encoder = connector->encoder;
6527 return encoder->get_hw_state(encoder, &pipe);
6530 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6532 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6533 return crtc_state->fdi_lanes;
6538 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6539 struct intel_crtc_state *pipe_config)
6541 struct drm_atomic_state *state = pipe_config->base.state;
6542 struct intel_crtc *other_crtc;
6543 struct intel_crtc_state *other_crtc_state;
6545 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6546 pipe_name(pipe), pipe_config->fdi_lanes);
6547 if (pipe_config->fdi_lanes > 4) {
6548 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6549 pipe_name(pipe), pipe_config->fdi_lanes);
6553 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6554 if (pipe_config->fdi_lanes > 2) {
6555 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6556 pipe_config->fdi_lanes);
6563 if (INTEL_INFO(dev)->num_pipes == 2)
6566 /* Ivybridge 3 pipe is really complicated */
6571 if (pipe_config->fdi_lanes <= 2)
6574 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6576 intel_atomic_get_crtc_state(state, other_crtc);
6577 if (IS_ERR(other_crtc_state))
6578 return PTR_ERR(other_crtc_state);
6580 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6581 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6582 pipe_name(pipe), pipe_config->fdi_lanes);
6587 if (pipe_config->fdi_lanes > 2) {
6588 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6589 pipe_name(pipe), pipe_config->fdi_lanes);
6593 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6595 intel_atomic_get_crtc_state(state, other_crtc);
6596 if (IS_ERR(other_crtc_state))
6597 return PTR_ERR(other_crtc_state);
6599 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6600 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6610 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6611 struct intel_crtc_state *pipe_config)
6613 struct drm_device *dev = intel_crtc->base.dev;
6614 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6615 int lane, link_bw, fdi_dotclock, ret;
6616 bool needs_recompute = false;
6619 /* FDI is a binary signal running at ~2.7GHz, encoding
6620 * each output octet as 10 bits. The actual frequency
6621 * is stored as a divider into a 100MHz clock, and the
6622 * mode pixel clock is stored in units of 1KHz.
6623 * Hence the bw of each lane in terms of the mode signal
6626 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6628 fdi_dotclock = adjusted_mode->crtc_clock;
6630 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6631 pipe_config->pipe_bpp);
6633 pipe_config->fdi_lanes = lane;
6635 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6636 link_bw, &pipe_config->fdi_m_n);
6638 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6639 intel_crtc->pipe, pipe_config);
6640 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6641 pipe_config->pipe_bpp -= 2*3;
6642 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6643 pipe_config->pipe_bpp);
6644 needs_recompute = true;
6645 pipe_config->bw_constrained = true;
6650 if (needs_recompute)
6656 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6657 struct intel_crtc_state *pipe_config)
6659 if (pipe_config->pipe_bpp > 24)
6662 /* HSW can handle pixel rate up to cdclk? */
6663 if (IS_HASWELL(dev_priv->dev))
6667 * We compare against max which means we must take
6668 * the increased cdclk requirement into account when
6669 * calculating the new cdclk.
6671 * Should measure whether using a lower cdclk w/o IPS
6673 return ilk_pipe_pixel_rate(pipe_config) <=
6674 dev_priv->max_cdclk_freq * 95 / 100;
6677 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6678 struct intel_crtc_state *pipe_config)
6680 struct drm_device *dev = crtc->base.dev;
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6683 pipe_config->ips_enabled = i915.enable_ips &&
6684 hsw_crtc_supports_ips(crtc) &&
6685 pipe_config_supports_ips(dev_priv, pipe_config);
6688 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6690 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6692 /* GDG double wide on either pipe, otherwise pipe A only */
6693 return INTEL_INFO(dev_priv)->gen < 4 &&
6694 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6697 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6698 struct intel_crtc_state *pipe_config)
6700 struct drm_device *dev = crtc->base.dev;
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6702 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6704 /* FIXME should check pixel clock limits on all platforms */
6705 if (INTEL_INFO(dev)->gen < 4) {
6706 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6709 * Enable double wide mode when the dot clock
6710 * is > 90% of the (display) core speed.
6712 if (intel_crtc_supports_double_wide(crtc) &&
6713 adjusted_mode->crtc_clock > clock_limit) {
6715 pipe_config->double_wide = true;
6718 if (adjusted_mode->crtc_clock > clock_limit) {
6719 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6720 adjusted_mode->crtc_clock, clock_limit,
6721 yesno(pipe_config->double_wide));
6727 * Pipe horizontal size must be even in:
6729 * - LVDS dual channel mode
6730 * - Double wide pipe
6732 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6733 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6734 pipe_config->pipe_src_w &= ~1;
6736 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6737 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6739 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6740 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6744 hsw_compute_ips_config(crtc, pipe_config);
6746 if (pipe_config->has_pch_encoder)
6747 return ironlake_fdi_compute_config(crtc, pipe_config);
6752 static int skylake_get_display_clock_speed(struct drm_device *dev)
6754 struct drm_i915_private *dev_priv = to_i915(dev);
6755 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6756 uint32_t cdctl = I915_READ(CDCLK_CTL);
6759 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6760 return 24000; /* 24MHz is the cd freq with NSSC ref */
6762 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6765 linkrate = (I915_READ(DPLL_CTRL1) &
6766 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6768 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6769 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6771 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6772 case CDCLK_FREQ_450_432:
6774 case CDCLK_FREQ_337_308:
6776 case CDCLK_FREQ_675_617:
6779 WARN(1, "Unknown cd freq selection\n");
6783 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6784 case CDCLK_FREQ_450_432:
6786 case CDCLK_FREQ_337_308:
6788 case CDCLK_FREQ_675_617:
6791 WARN(1, "Unknown cd freq selection\n");
6795 /* error case, do as if DPLL0 isn't enabled */
6799 static int broxton_get_display_clock_speed(struct drm_device *dev)
6801 struct drm_i915_private *dev_priv = to_i915(dev);
6802 uint32_t cdctl = I915_READ(CDCLK_CTL);
6803 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6804 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6807 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6810 cdclk = 19200 * pll_ratio / 2;
6812 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6813 case BXT_CDCLK_CD2X_DIV_SEL_1:
6814 return cdclk; /* 576MHz or 624MHz */
6815 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6816 return cdclk * 2 / 3; /* 384MHz */
6817 case BXT_CDCLK_CD2X_DIV_SEL_2:
6818 return cdclk / 2; /* 288MHz */
6819 case BXT_CDCLK_CD2X_DIV_SEL_4:
6820 return cdclk / 4; /* 144MHz */
6823 /* error case, do as if DE PLL isn't enabled */
6827 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6829 struct drm_i915_private *dev_priv = dev->dev_private;
6830 uint32_t lcpll = I915_READ(LCPLL_CTL);
6831 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6833 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6835 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6837 else if (freq == LCPLL_CLK_FREQ_450)
6839 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6841 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6847 static int haswell_get_display_clock_speed(struct drm_device *dev)
6849 struct drm_i915_private *dev_priv = dev->dev_private;
6850 uint32_t lcpll = I915_READ(LCPLL_CTL);
6851 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6853 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6855 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6857 else if (freq == LCPLL_CLK_FREQ_450)
6859 else if (IS_HSW_ULT(dev))
6865 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6867 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6868 CCK_DISPLAY_CLOCK_CONTROL);
6871 static int ilk_get_display_clock_speed(struct drm_device *dev)
6876 static int i945_get_display_clock_speed(struct drm_device *dev)
6881 static int i915_get_display_clock_speed(struct drm_device *dev)
6886 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6891 static int pnv_get_display_clock_speed(struct drm_device *dev)
6895 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6897 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6898 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6900 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6902 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6904 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6907 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6908 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6910 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6915 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6919 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6921 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6924 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6925 case GC_DISPLAY_CLOCK_333_MHZ:
6928 case GC_DISPLAY_CLOCK_190_200_MHZ:
6934 static int i865_get_display_clock_speed(struct drm_device *dev)
6939 static int i85x_get_display_clock_speed(struct drm_device *dev)
6944 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6945 * encoding is different :(
6946 * FIXME is this the right way to detect 852GM/852GMV?
6948 if (dev->pdev->revision == 0x1)
6951 pci_bus_read_config_word(dev->pdev->bus,
6952 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6954 /* Assume that the hardware is in the high speed state. This
6955 * should be the default.
6957 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6958 case GC_CLOCK_133_200:
6959 case GC_CLOCK_133_200_2:
6960 case GC_CLOCK_100_200:
6962 case GC_CLOCK_166_250:
6964 case GC_CLOCK_100_133:
6966 case GC_CLOCK_133_266:
6967 case GC_CLOCK_133_266_2:
6968 case GC_CLOCK_166_266:
6972 /* Shouldn't happen */
6976 static int i830_get_display_clock_speed(struct drm_device *dev)
6981 static unsigned int intel_hpll_vco(struct drm_device *dev)
6983 struct drm_i915_private *dev_priv = dev->dev_private;
6984 static const unsigned int blb_vco[8] = {
6991 static const unsigned int pnv_vco[8] = {
6998 static const unsigned int cl_vco[8] = {
7007 static const unsigned int elk_vco[8] = {
7013 static const unsigned int ctg_vco[8] = {
7021 const unsigned int *vco_table;
7025 /* FIXME other chipsets? */
7027 vco_table = ctg_vco;
7028 else if (IS_G4X(dev))
7029 vco_table = elk_vco;
7030 else if (IS_CRESTLINE(dev))
7032 else if (IS_PINEVIEW(dev))
7033 vco_table = pnv_vco;
7034 else if (IS_G33(dev))
7035 vco_table = blb_vco;
7039 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7041 vco = vco_table[tmp & 0x7];
7043 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7045 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7050 static int gm45_get_display_clock_speed(struct drm_device *dev)
7052 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7055 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7057 cdclk_sel = (tmp >> 12) & 0x1;
7063 return cdclk_sel ? 333333 : 222222;
7065 return cdclk_sel ? 320000 : 228571;
7067 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7072 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7074 static const uint8_t div_3200[] = { 16, 10, 8 };
7075 static const uint8_t div_4000[] = { 20, 12, 10 };
7076 static const uint8_t div_5333[] = { 24, 16, 14 };
7077 const uint8_t *div_table;
7078 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7081 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7083 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7085 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7090 div_table = div_3200;
7093 div_table = div_4000;
7096 div_table = div_5333;
7102 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7105 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7109 static int g33_get_display_clock_speed(struct drm_device *dev)
7111 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7112 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7113 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7114 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7115 const uint8_t *div_table;
7116 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7119 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7121 cdclk_sel = (tmp >> 4) & 0x7;
7123 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7128 div_table = div_3200;
7131 div_table = div_4000;
7134 div_table = div_4800;
7137 div_table = div_5333;
7143 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7146 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7151 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7153 while (*num > DATA_LINK_M_N_MASK ||
7154 *den > DATA_LINK_M_N_MASK) {
7160 static void compute_m_n(unsigned int m, unsigned int n,
7161 uint32_t *ret_m, uint32_t *ret_n)
7163 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7164 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7165 intel_reduce_m_n_ratio(ret_m, ret_n);
7169 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7170 int pixel_clock, int link_clock,
7171 struct intel_link_m_n *m_n)
7175 compute_m_n(bits_per_pixel * pixel_clock,
7176 link_clock * nlanes * 8,
7177 &m_n->gmch_m, &m_n->gmch_n);
7179 compute_m_n(pixel_clock, link_clock,
7180 &m_n->link_m, &m_n->link_n);
7183 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7185 if (i915.panel_use_ssc >= 0)
7186 return i915.panel_use_ssc != 0;
7187 return dev_priv->vbt.lvds_use_ssc
7188 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7191 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7194 struct drm_device *dev = crtc_state->base.crtc->dev;
7195 struct drm_i915_private *dev_priv = dev->dev_private;
7198 WARN_ON(!crtc_state->base.state);
7200 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7202 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7203 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7204 refclk = dev_priv->vbt.lvds_ssc_freq;
7205 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7206 } else if (!IS_GEN2(dev)) {
7215 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7217 return (1 << dpll->n) << 16 | dpll->m2;
7220 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7222 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7225 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7226 struct intel_crtc_state *crtc_state,
7227 intel_clock_t *reduced_clock)
7229 struct drm_device *dev = crtc->base.dev;
7232 if (IS_PINEVIEW(dev)) {
7233 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7235 fp2 = pnv_dpll_compute_fp(reduced_clock);
7237 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7239 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7242 crtc_state->dpll_hw_state.fp0 = fp;
7244 crtc->lowfreq_avail = false;
7245 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7247 crtc_state->dpll_hw_state.fp1 = fp2;
7248 crtc->lowfreq_avail = true;
7250 crtc_state->dpll_hw_state.fp1 = fp;
7254 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7260 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7261 * and set it to a reasonable value instead.
7263 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7264 reg_val &= 0xffffff00;
7265 reg_val |= 0x00000030;
7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7268 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7269 reg_val &= 0x8cffffff;
7270 reg_val = 0x8c000000;
7271 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7273 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7274 reg_val &= 0xffffff00;
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7277 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7278 reg_val &= 0x00ffffff;
7279 reg_val |= 0xb0000000;
7280 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7283 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7284 struct intel_link_m_n *m_n)
7286 struct drm_device *dev = crtc->base.dev;
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 int pipe = crtc->pipe;
7290 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7291 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7292 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7293 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7296 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7297 struct intel_link_m_n *m_n,
7298 struct intel_link_m_n *m2_n2)
7300 struct drm_device *dev = crtc->base.dev;
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 int pipe = crtc->pipe;
7303 enum transcoder transcoder = crtc->config->cpu_transcoder;
7305 if (INTEL_INFO(dev)->gen >= 5) {
7306 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7307 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7308 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7309 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7310 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7311 * for gen < 8) and if DRRS is supported (to make sure the
7312 * registers are not unnecessarily accessed).
7314 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7315 crtc->config->has_drrs) {
7316 I915_WRITE(PIPE_DATA_M2(transcoder),
7317 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7318 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7319 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7320 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7323 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7324 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7325 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7326 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7330 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7332 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7335 dp_m_n = &crtc->config->dp_m_n;
7336 dp_m2_n2 = &crtc->config->dp_m2_n2;
7337 } else if (m_n == M2_N2) {
7340 * M2_N2 registers are not supported. Hence m2_n2 divider value
7341 * needs to be programmed into M1_N1.
7343 dp_m_n = &crtc->config->dp_m2_n2;
7345 DRM_ERROR("Unsupported divider value\n");
7349 if (crtc->config->has_pch_encoder)
7350 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7352 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7355 static void vlv_compute_dpll(struct intel_crtc *crtc,
7356 struct intel_crtc_state *pipe_config)
7361 * Enable DPIO clock input. We should never disable the reference
7362 * clock for pipe B, since VGA hotplug / manual detection depends
7365 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7366 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7367 /* We should never disable this, set it here for state tracking */
7368 if (crtc->pipe == PIPE_B)
7369 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7370 dpll |= DPLL_VCO_ENABLE;
7371 pipe_config->dpll_hw_state.dpll = dpll;
7373 dpll_md = (pipe_config->pixel_multiplier - 1)
7374 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7375 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7378 static void vlv_prepare_pll(struct intel_crtc *crtc,
7379 const struct intel_crtc_state *pipe_config)
7381 struct drm_device *dev = crtc->base.dev;
7382 struct drm_i915_private *dev_priv = dev->dev_private;
7383 int pipe = crtc->pipe;
7385 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7386 u32 coreclk, reg_val;
7388 mutex_lock(&dev_priv->sb_lock);
7390 bestn = pipe_config->dpll.n;
7391 bestm1 = pipe_config->dpll.m1;
7392 bestm2 = pipe_config->dpll.m2;
7393 bestp1 = pipe_config->dpll.p1;
7394 bestp2 = pipe_config->dpll.p2;
7396 /* See eDP HDMI DPIO driver vbios notes doc */
7398 /* PLL B needs special handling */
7400 vlv_pllb_recal_opamp(dev_priv, pipe);
7402 /* Set up Tx target for periodic Rcomp update */
7403 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7405 /* Disable target IRef on PLL */
7406 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7407 reg_val &= 0x00ffffff;
7408 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7410 /* Disable fast lock */
7411 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7413 /* Set idtafcrecal before PLL is enabled */
7414 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7415 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7416 mdiv |= ((bestn << DPIO_N_SHIFT));
7417 mdiv |= (1 << DPIO_K_SHIFT);
7420 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7421 * but we don't support that).
7422 * Note: don't use the DAC post divider as it seems unstable.
7424 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7425 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7427 mdiv |= DPIO_ENABLE_CALIBRATION;
7428 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7430 /* Set HBR and RBR LPF coefficients */
7431 if (pipe_config->port_clock == 162000 ||
7432 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7433 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7434 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7437 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7440 if (pipe_config->has_dp_encoder) {
7441 /* Use SSC source */
7443 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7446 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7448 } else { /* HDMI or VGA */
7449 /* Use bend source */
7451 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7454 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7458 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7459 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7460 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7461 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7462 coreclk |= 0x01000000;
7463 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7465 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7466 mutex_unlock(&dev_priv->sb_lock);
7469 static void chv_compute_dpll(struct intel_crtc *crtc,
7470 struct intel_crtc_state *pipe_config)
7472 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7473 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7475 if (crtc->pipe != PIPE_A)
7476 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7478 pipe_config->dpll_hw_state.dpll_md =
7479 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7482 static void chv_prepare_pll(struct intel_crtc *crtc,
7483 const struct intel_crtc_state *pipe_config)
7485 struct drm_device *dev = crtc->base.dev;
7486 struct drm_i915_private *dev_priv = dev->dev_private;
7487 int pipe = crtc->pipe;
7488 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7489 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7490 u32 loopfilter, tribuf_calcntr;
7491 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7495 bestn = pipe_config->dpll.n;
7496 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7497 bestm1 = pipe_config->dpll.m1;
7498 bestm2 = pipe_config->dpll.m2 >> 22;
7499 bestp1 = pipe_config->dpll.p1;
7500 bestp2 = pipe_config->dpll.p2;
7501 vco = pipe_config->dpll.vco;
7506 * Enable Refclk and SSC
7508 I915_WRITE(dpll_reg,
7509 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7511 mutex_lock(&dev_priv->sb_lock);
7513 /* p1 and p2 divider */
7514 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7515 5 << DPIO_CHV_S1_DIV_SHIFT |
7516 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7517 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7518 1 << DPIO_CHV_K_DIV_SHIFT);
7520 /* Feedback post-divider - m2 */
7521 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7523 /* Feedback refclk divider - n and m1 */
7524 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7525 DPIO_CHV_M1_DIV_BY_2 |
7526 1 << DPIO_CHV_N_DIV_SHIFT);
7528 /* M2 fraction division */
7529 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7531 /* M2 fraction division enable */
7532 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7533 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7534 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7536 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7537 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7539 /* Program digital lock detect threshold */
7540 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7541 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7542 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7543 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7545 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7546 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7549 if (vco == 5400000) {
7550 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7551 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7552 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7553 tribuf_calcntr = 0x9;
7554 } else if (vco <= 6200000) {
7555 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7556 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7557 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7558 tribuf_calcntr = 0x9;
7559 } else if (vco <= 6480000) {
7560 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7561 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7562 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7563 tribuf_calcntr = 0x8;
7565 /* Not supported. Apply the same limits as in the max case */
7566 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7567 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7568 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7571 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7573 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7574 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7575 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7576 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7579 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7580 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7583 mutex_unlock(&dev_priv->sb_lock);
7587 * vlv_force_pll_on - forcibly enable just the PLL
7588 * @dev_priv: i915 private structure
7589 * @pipe: pipe PLL to enable
7590 * @dpll: PLL configuration
7592 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7593 * in cases where we need the PLL enabled even when @pipe is not going to
7596 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7597 const struct dpll *dpll)
7599 struct intel_crtc *crtc =
7600 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7601 struct intel_crtc_state pipe_config = {
7602 .base.crtc = &crtc->base,
7603 .pixel_multiplier = 1,
7607 if (IS_CHERRYVIEW(dev)) {
7608 chv_compute_dpll(crtc, &pipe_config);
7609 chv_prepare_pll(crtc, &pipe_config);
7610 chv_enable_pll(crtc, &pipe_config);
7612 vlv_compute_dpll(crtc, &pipe_config);
7613 vlv_prepare_pll(crtc, &pipe_config);
7614 vlv_enable_pll(crtc, &pipe_config);
7619 * vlv_force_pll_off - forcibly disable just the PLL
7620 * @dev_priv: i915 private structure
7621 * @pipe: pipe PLL to disable
7623 * Disable the PLL for @pipe. To be used in cases where we need
7624 * the PLL enabled even when @pipe is not going to be enabled.
7626 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7628 if (IS_CHERRYVIEW(dev))
7629 chv_disable_pll(to_i915(dev), pipe);
7631 vlv_disable_pll(to_i915(dev), pipe);
7634 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7635 struct intel_crtc_state *crtc_state,
7636 intel_clock_t *reduced_clock,
7639 struct drm_device *dev = crtc->base.dev;
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7643 struct dpll *clock = &crtc_state->dpll;
7645 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7647 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7648 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7650 dpll = DPLL_VGA_MODE_DIS;
7652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7653 dpll |= DPLLB_MODE_LVDS;
7655 dpll |= DPLLB_MODE_DAC_SERIAL;
7657 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7658 dpll |= (crtc_state->pixel_multiplier - 1)
7659 << SDVO_MULTIPLIER_SHIFT_HIRES;
7663 dpll |= DPLL_SDVO_HIGH_SPEED;
7665 if (crtc_state->has_dp_encoder)
7666 dpll |= DPLL_SDVO_HIGH_SPEED;
7668 /* compute bitmask from p1 value */
7669 if (IS_PINEVIEW(dev))
7670 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7672 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7673 if (IS_G4X(dev) && reduced_clock)
7674 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7676 switch (clock->p2) {
7678 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7681 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7684 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7687 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7690 if (INTEL_INFO(dev)->gen >= 4)
7691 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7693 if (crtc_state->sdvo_tv_clock)
7694 dpll |= PLL_REF_INPUT_TVCLKINBC;
7695 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7696 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7697 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7699 dpll |= PLL_REF_INPUT_DREFCLK;
7701 dpll |= DPLL_VCO_ENABLE;
7702 crtc_state->dpll_hw_state.dpll = dpll;
7704 if (INTEL_INFO(dev)->gen >= 4) {
7705 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7706 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7707 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7711 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7712 struct intel_crtc_state *crtc_state,
7713 intel_clock_t *reduced_clock,
7716 struct drm_device *dev = crtc->base.dev;
7717 struct drm_i915_private *dev_priv = dev->dev_private;
7719 struct dpll *clock = &crtc_state->dpll;
7721 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7723 dpll = DPLL_VGA_MODE_DIS;
7725 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7726 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7729 dpll |= PLL_P1_DIVIDE_BY_TWO;
7731 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7733 dpll |= PLL_P2_DIVIDE_BY_4;
7736 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7737 dpll |= DPLL_DVO_2X_MODE;
7739 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7740 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7741 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7743 dpll |= PLL_REF_INPUT_DREFCLK;
7745 dpll |= DPLL_VCO_ENABLE;
7746 crtc_state->dpll_hw_state.dpll = dpll;
7749 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7751 struct drm_device *dev = intel_crtc->base.dev;
7752 struct drm_i915_private *dev_priv = dev->dev_private;
7753 enum pipe pipe = intel_crtc->pipe;
7754 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7755 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7756 uint32_t crtc_vtotal, crtc_vblank_end;
7759 /* We need to be careful not to changed the adjusted mode, for otherwise
7760 * the hw state checker will get angry at the mismatch. */
7761 crtc_vtotal = adjusted_mode->crtc_vtotal;
7762 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7764 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7765 /* the chip adds 2 halflines automatically */
7767 crtc_vblank_end -= 1;
7769 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7770 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7772 vsyncshift = adjusted_mode->crtc_hsync_start -
7773 adjusted_mode->crtc_htotal / 2;
7775 vsyncshift += adjusted_mode->crtc_htotal;
7778 if (INTEL_INFO(dev)->gen > 3)
7779 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7781 I915_WRITE(HTOTAL(cpu_transcoder),
7782 (adjusted_mode->crtc_hdisplay - 1) |
7783 ((adjusted_mode->crtc_htotal - 1) << 16));
7784 I915_WRITE(HBLANK(cpu_transcoder),
7785 (adjusted_mode->crtc_hblank_start - 1) |
7786 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7787 I915_WRITE(HSYNC(cpu_transcoder),
7788 (adjusted_mode->crtc_hsync_start - 1) |
7789 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7791 I915_WRITE(VTOTAL(cpu_transcoder),
7792 (adjusted_mode->crtc_vdisplay - 1) |
7793 ((crtc_vtotal - 1) << 16));
7794 I915_WRITE(VBLANK(cpu_transcoder),
7795 (adjusted_mode->crtc_vblank_start - 1) |
7796 ((crtc_vblank_end - 1) << 16));
7797 I915_WRITE(VSYNC(cpu_transcoder),
7798 (adjusted_mode->crtc_vsync_start - 1) |
7799 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7801 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7802 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7803 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7805 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7806 (pipe == PIPE_B || pipe == PIPE_C))
7807 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7809 /* pipesrc controls the size that is scaled from, which should
7810 * always be the user's requested size.
7812 I915_WRITE(PIPESRC(pipe),
7813 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7814 (intel_crtc->config->pipe_src_h - 1));
7817 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7818 struct intel_crtc_state *pipe_config)
7820 struct drm_device *dev = crtc->base.dev;
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7825 tmp = I915_READ(HTOTAL(cpu_transcoder));
7826 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7827 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7828 tmp = I915_READ(HBLANK(cpu_transcoder));
7829 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7830 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7831 tmp = I915_READ(HSYNC(cpu_transcoder));
7832 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7833 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7835 tmp = I915_READ(VTOTAL(cpu_transcoder));
7836 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7837 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7838 tmp = I915_READ(VBLANK(cpu_transcoder));
7839 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7840 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7841 tmp = I915_READ(VSYNC(cpu_transcoder));
7842 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7843 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7845 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7846 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7847 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7848 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7851 tmp = I915_READ(PIPESRC(crtc->pipe));
7852 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7853 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7855 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7856 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7859 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7860 struct intel_crtc_state *pipe_config)
7862 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7863 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7864 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7865 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7867 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7868 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7869 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7870 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7872 mode->flags = pipe_config->base.adjusted_mode.flags;
7873 mode->type = DRM_MODE_TYPE_DRIVER;
7875 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7876 mode->flags |= pipe_config->base.adjusted_mode.flags;
7878 mode->hsync = drm_mode_hsync(mode);
7879 mode->vrefresh = drm_mode_vrefresh(mode);
7880 drm_mode_set_name(mode);
7883 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7885 struct drm_device *dev = intel_crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7891 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7892 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7893 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7895 if (intel_crtc->config->double_wide)
7896 pipeconf |= PIPECONF_DOUBLE_WIDE;
7898 /* only g4x and later have fancy bpc/dither controls */
7899 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7900 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7901 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7902 pipeconf |= PIPECONF_DITHER_EN |
7903 PIPECONF_DITHER_TYPE_SP;
7905 switch (intel_crtc->config->pipe_bpp) {
7907 pipeconf |= PIPECONF_6BPC;
7910 pipeconf |= PIPECONF_8BPC;
7913 pipeconf |= PIPECONF_10BPC;
7916 /* Case prevented by intel_choose_pipe_bpp_dither. */
7921 if (HAS_PIPE_CXSR(dev)) {
7922 if (intel_crtc->lowfreq_avail) {
7923 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7924 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7926 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7930 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7931 if (INTEL_INFO(dev)->gen < 4 ||
7932 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7933 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7935 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7937 pipeconf |= PIPECONF_PROGRESSIVE;
7939 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7940 intel_crtc->config->limited_color_range)
7941 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7943 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7944 POSTING_READ(PIPECONF(intel_crtc->pipe));
7947 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7948 struct intel_crtc_state *crtc_state)
7950 struct drm_device *dev = crtc->base.dev;
7951 struct drm_i915_private *dev_priv = dev->dev_private;
7952 int refclk, num_connectors = 0;
7953 intel_clock_t clock;
7955 const intel_limit_t *limit;
7956 struct drm_atomic_state *state = crtc_state->base.state;
7957 struct drm_connector *connector;
7958 struct drm_connector_state *connector_state;
7961 memset(&crtc_state->dpll_hw_state, 0,
7962 sizeof(crtc_state->dpll_hw_state));
7964 if (crtc_state->has_dsi_encoder)
7967 for_each_connector_in_state(state, connector, connector_state, i) {
7968 if (connector_state->crtc == &crtc->base)
7972 if (!crtc_state->clock_set) {
7973 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7976 * Returns a set of divisors for the desired target clock with
7977 * the given refclk, or FALSE. The returned values represent
7978 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7981 limit = intel_limit(crtc_state, refclk);
7982 ok = dev_priv->display.find_dpll(limit, crtc_state,
7983 crtc_state->port_clock,
7984 refclk, NULL, &clock);
7986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7990 /* Compat-code for transition, will disappear. */
7991 crtc_state->dpll.n = clock.n;
7992 crtc_state->dpll.m1 = clock.m1;
7993 crtc_state->dpll.m2 = clock.m2;
7994 crtc_state->dpll.p1 = clock.p1;
7995 crtc_state->dpll.p2 = clock.p2;
7999 i8xx_compute_dpll(crtc, crtc_state, NULL,
8001 } else if (IS_CHERRYVIEW(dev)) {
8002 chv_compute_dpll(crtc, crtc_state);
8003 } else if (IS_VALLEYVIEW(dev)) {
8004 vlv_compute_dpll(crtc, crtc_state);
8006 i9xx_compute_dpll(crtc, crtc_state, NULL,
8013 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8014 struct intel_crtc_state *pipe_config)
8016 struct drm_device *dev = crtc->base.dev;
8017 struct drm_i915_private *dev_priv = dev->dev_private;
8020 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8023 tmp = I915_READ(PFIT_CONTROL);
8024 if (!(tmp & PFIT_ENABLE))
8027 /* Check whether the pfit is attached to our pipe. */
8028 if (INTEL_INFO(dev)->gen < 4) {
8029 if (crtc->pipe != PIPE_B)
8032 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8036 pipe_config->gmch_pfit.control = tmp;
8037 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8038 if (INTEL_INFO(dev)->gen < 5)
8039 pipe_config->gmch_pfit.lvds_border_bits =
8040 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8043 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8044 struct intel_crtc_state *pipe_config)
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 int pipe = pipe_config->cpu_transcoder;
8049 intel_clock_t clock;
8051 int refclk = 100000;
8053 /* In case of MIPI DPLL will not even be used */
8054 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8057 mutex_lock(&dev_priv->sb_lock);
8058 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8059 mutex_unlock(&dev_priv->sb_lock);
8061 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8062 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8063 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8064 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8065 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8067 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8071 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8072 struct intel_initial_plane_config *plane_config)
8074 struct drm_device *dev = crtc->base.dev;
8075 struct drm_i915_private *dev_priv = dev->dev_private;
8076 u32 val, base, offset;
8077 int pipe = crtc->pipe, plane = crtc->plane;
8078 int fourcc, pixel_format;
8079 unsigned int aligned_height;
8080 struct drm_framebuffer *fb;
8081 struct intel_framebuffer *intel_fb;
8083 val = I915_READ(DSPCNTR(plane));
8084 if (!(val & DISPLAY_PLANE_ENABLE))
8087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8089 DRM_DEBUG_KMS("failed to alloc fb\n");
8093 fb = &intel_fb->base;
8095 if (INTEL_INFO(dev)->gen >= 4) {
8096 if (val & DISPPLANE_TILED) {
8097 plane_config->tiling = I915_TILING_X;
8098 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8102 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8103 fourcc = i9xx_format_to_fourcc(pixel_format);
8104 fb->pixel_format = fourcc;
8105 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8107 if (INTEL_INFO(dev)->gen >= 4) {
8108 if (plane_config->tiling)
8109 offset = I915_READ(DSPTILEOFF(plane));
8111 offset = I915_READ(DSPLINOFF(plane));
8112 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8114 base = I915_READ(DSPADDR(plane));
8116 plane_config->base = base;
8118 val = I915_READ(PIPESRC(pipe));
8119 fb->width = ((val >> 16) & 0xfff) + 1;
8120 fb->height = ((val >> 0) & 0xfff) + 1;
8122 val = I915_READ(DSPSTRIDE(pipe));
8123 fb->pitches[0] = val & 0xffffffc0;
8125 aligned_height = intel_fb_align_height(dev, fb->height,
8129 plane_config->size = fb->pitches[0] * aligned_height;
8131 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8132 pipe_name(pipe), plane, fb->width, fb->height,
8133 fb->bits_per_pixel, base, fb->pitches[0],
8134 plane_config->size);
8136 plane_config->fb = intel_fb;
8139 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8140 struct intel_crtc_state *pipe_config)
8142 struct drm_device *dev = crtc->base.dev;
8143 struct drm_i915_private *dev_priv = dev->dev_private;
8144 int pipe = pipe_config->cpu_transcoder;
8145 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8146 intel_clock_t clock;
8147 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8148 int refclk = 100000;
8150 mutex_lock(&dev_priv->sb_lock);
8151 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8152 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8153 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8154 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8155 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8156 mutex_unlock(&dev_priv->sb_lock);
8158 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8159 clock.m2 = (pll_dw0 & 0xff) << 22;
8160 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8161 clock.m2 |= pll_dw2 & 0x3fffff;
8162 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8163 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8164 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8166 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8169 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8170 struct intel_crtc_state *pipe_config)
8172 struct drm_device *dev = crtc->base.dev;
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 enum intel_display_power_domain power_domain;
8178 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8179 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8182 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8183 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8187 tmp = I915_READ(PIPECONF(crtc->pipe));
8188 if (!(tmp & PIPECONF_ENABLE))
8191 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8192 switch (tmp & PIPECONF_BPC_MASK) {
8194 pipe_config->pipe_bpp = 18;
8197 pipe_config->pipe_bpp = 24;
8199 case PIPECONF_10BPC:
8200 pipe_config->pipe_bpp = 30;
8207 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8208 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8209 pipe_config->limited_color_range = true;
8211 if (INTEL_INFO(dev)->gen < 4)
8212 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8214 intel_get_pipe_timings(crtc, pipe_config);
8216 i9xx_get_pfit_config(crtc, pipe_config);
8218 if (INTEL_INFO(dev)->gen >= 4) {
8219 tmp = I915_READ(DPLL_MD(crtc->pipe));
8220 pipe_config->pixel_multiplier =
8221 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8222 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8223 pipe_config->dpll_hw_state.dpll_md = tmp;
8224 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8225 tmp = I915_READ(DPLL(crtc->pipe));
8226 pipe_config->pixel_multiplier =
8227 ((tmp & SDVO_MULTIPLIER_MASK)
8228 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8230 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8231 * port and will be fixed up in the encoder->get_config
8233 pipe_config->pixel_multiplier = 1;
8235 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8236 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8238 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8239 * on 830. Filter it out here so that we don't
8240 * report errors due to that.
8243 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8245 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8246 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8248 /* Mask out read-only status bits. */
8249 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8250 DPLL_PORTC_READY_MASK |
8251 DPLL_PORTB_READY_MASK);
8254 if (IS_CHERRYVIEW(dev))
8255 chv_crtc_clock_get(crtc, pipe_config);
8256 else if (IS_VALLEYVIEW(dev))
8257 vlv_crtc_clock_get(crtc, pipe_config);
8259 i9xx_crtc_clock_get(crtc, pipe_config);
8262 * Normally the dotclock is filled in by the encoder .get_config()
8263 * but in case the pipe is enabled w/o any ports we need a sane
8266 pipe_config->base.adjusted_mode.crtc_clock =
8267 pipe_config->port_clock / pipe_config->pixel_multiplier;
8272 intel_display_power_put(dev_priv, power_domain);
8277 static void ironlake_init_pch_refclk(struct drm_device *dev)
8279 struct drm_i915_private *dev_priv = dev->dev_private;
8280 struct intel_encoder *encoder;
8282 bool has_lvds = false;
8283 bool has_cpu_edp = false;
8284 bool has_panel = false;
8285 bool has_ck505 = false;
8286 bool can_ssc = false;
8288 /* We need to take the global config into account */
8289 for_each_intel_encoder(dev, encoder) {
8290 switch (encoder->type) {
8291 case INTEL_OUTPUT_LVDS:
8295 case INTEL_OUTPUT_EDP:
8297 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8305 if (HAS_PCH_IBX(dev)) {
8306 has_ck505 = dev_priv->vbt.display_clock_mode;
8307 can_ssc = has_ck505;
8313 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8314 has_panel, has_lvds, has_ck505);
8316 /* Ironlake: try to setup display ref clock before DPLL
8317 * enabling. This is only under driver's control after
8318 * PCH B stepping, previous chipset stepping should be
8319 * ignoring this setting.
8321 val = I915_READ(PCH_DREF_CONTROL);
8323 /* As we must carefully and slowly disable/enable each source in turn,
8324 * compute the final state we want first and check if we need to
8325 * make any changes at all.
8328 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8330 final |= DREF_NONSPREAD_CK505_ENABLE;
8332 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8334 final &= ~DREF_SSC_SOURCE_MASK;
8335 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8336 final &= ~DREF_SSC1_ENABLE;
8339 final |= DREF_SSC_SOURCE_ENABLE;
8341 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8342 final |= DREF_SSC1_ENABLE;
8345 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8346 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8348 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8350 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8352 final |= DREF_SSC_SOURCE_DISABLE;
8353 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8359 /* Always enable nonspread source */
8360 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8363 val |= DREF_NONSPREAD_CK505_ENABLE;
8365 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8368 val &= ~DREF_SSC_SOURCE_MASK;
8369 val |= DREF_SSC_SOURCE_ENABLE;
8371 /* SSC must be turned on before enabling the CPU output */
8372 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8373 DRM_DEBUG_KMS("Using SSC on panel\n");
8374 val |= DREF_SSC1_ENABLE;
8376 val &= ~DREF_SSC1_ENABLE;
8378 /* Get SSC going before enabling the outputs */
8379 I915_WRITE(PCH_DREF_CONTROL, val);
8380 POSTING_READ(PCH_DREF_CONTROL);
8383 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8385 /* Enable CPU source on CPU attached eDP */
8387 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8388 DRM_DEBUG_KMS("Using SSC on eDP\n");
8389 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8391 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8393 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8395 I915_WRITE(PCH_DREF_CONTROL, val);
8396 POSTING_READ(PCH_DREF_CONTROL);
8399 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8401 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8403 /* Turn off CPU output */
8404 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8406 I915_WRITE(PCH_DREF_CONTROL, val);
8407 POSTING_READ(PCH_DREF_CONTROL);
8410 /* Turn off the SSC source */
8411 val &= ~DREF_SSC_SOURCE_MASK;
8412 val |= DREF_SSC_SOURCE_DISABLE;
8415 val &= ~DREF_SSC1_ENABLE;
8417 I915_WRITE(PCH_DREF_CONTROL, val);
8418 POSTING_READ(PCH_DREF_CONTROL);
8422 BUG_ON(val != final);
8425 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8429 tmp = I915_READ(SOUTH_CHICKEN2);
8430 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8431 I915_WRITE(SOUTH_CHICKEN2, tmp);
8433 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8434 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8435 DRM_ERROR("FDI mPHY reset assert timeout\n");
8437 tmp = I915_READ(SOUTH_CHICKEN2);
8438 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8439 I915_WRITE(SOUTH_CHICKEN2, tmp);
8441 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8442 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8443 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8446 /* WaMPhyProgramming:hsw */
8447 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8451 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8452 tmp &= ~(0xFF << 24);
8453 tmp |= (0x12 << 24);
8454 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8456 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8458 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8460 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8462 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8464 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8465 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8466 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8468 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8469 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8470 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8472 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8475 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8477 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8480 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8482 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8485 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8487 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8490 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8492 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8493 tmp &= ~(0xFF << 16);
8494 tmp |= (0x1C << 16);
8495 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8497 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8498 tmp &= ~(0xFF << 16);
8499 tmp |= (0x1C << 16);
8500 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8502 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8504 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8506 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8508 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8510 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8511 tmp &= ~(0xF << 28);
8513 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8515 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8516 tmp &= ~(0xF << 28);
8518 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8521 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8522 * Programming" based on the parameters passed:
8523 * - Sequence to enable CLKOUT_DP
8524 * - Sequence to enable CLKOUT_DP without spread
8525 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8527 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8530 struct drm_i915_private *dev_priv = dev->dev_private;
8533 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8535 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8538 mutex_lock(&dev_priv->sb_lock);
8540 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8541 tmp &= ~SBI_SSCCTL_DISABLE;
8542 tmp |= SBI_SSCCTL_PATHALT;
8543 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8548 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8549 tmp &= ~SBI_SSCCTL_PATHALT;
8550 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8553 lpt_reset_fdi_mphy(dev_priv);
8554 lpt_program_fdi_mphy(dev_priv);
8558 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8559 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8560 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8561 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8563 mutex_unlock(&dev_priv->sb_lock);
8566 /* Sequence to disable CLKOUT_DP */
8567 static void lpt_disable_clkout_dp(struct drm_device *dev)
8569 struct drm_i915_private *dev_priv = dev->dev_private;
8572 mutex_lock(&dev_priv->sb_lock);
8574 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8575 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8576 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8577 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8579 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8580 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8581 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8582 tmp |= SBI_SSCCTL_PATHALT;
8583 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8586 tmp |= SBI_SSCCTL_DISABLE;
8587 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8590 mutex_unlock(&dev_priv->sb_lock);
8593 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8595 static const uint16_t sscdivintphase[] = {
8596 [BEND_IDX( 50)] = 0x3B23,
8597 [BEND_IDX( 45)] = 0x3B23,
8598 [BEND_IDX( 40)] = 0x3C23,
8599 [BEND_IDX( 35)] = 0x3C23,
8600 [BEND_IDX( 30)] = 0x3D23,
8601 [BEND_IDX( 25)] = 0x3D23,
8602 [BEND_IDX( 20)] = 0x3E23,
8603 [BEND_IDX( 15)] = 0x3E23,
8604 [BEND_IDX( 10)] = 0x3F23,
8605 [BEND_IDX( 5)] = 0x3F23,
8606 [BEND_IDX( 0)] = 0x0025,
8607 [BEND_IDX( -5)] = 0x0025,
8608 [BEND_IDX(-10)] = 0x0125,
8609 [BEND_IDX(-15)] = 0x0125,
8610 [BEND_IDX(-20)] = 0x0225,
8611 [BEND_IDX(-25)] = 0x0225,
8612 [BEND_IDX(-30)] = 0x0325,
8613 [BEND_IDX(-35)] = 0x0325,
8614 [BEND_IDX(-40)] = 0x0425,
8615 [BEND_IDX(-45)] = 0x0425,
8616 [BEND_IDX(-50)] = 0x0525,
8621 * steps -50 to 50 inclusive, in steps of 5
8622 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8623 * change in clock period = -(steps / 10) * 5.787 ps
8625 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8628 int idx = BEND_IDX(steps);
8630 if (WARN_ON(steps % 5 != 0))
8633 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8636 mutex_lock(&dev_priv->sb_lock);
8638 if (steps % 10 != 0)
8642 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8644 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8646 tmp |= sscdivintphase[idx];
8647 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8649 mutex_unlock(&dev_priv->sb_lock);
8654 static void lpt_init_pch_refclk(struct drm_device *dev)
8656 struct intel_encoder *encoder;
8657 bool has_vga = false;
8659 for_each_intel_encoder(dev, encoder) {
8660 switch (encoder->type) {
8661 case INTEL_OUTPUT_ANALOG:
8670 lpt_bend_clkout_dp(to_i915(dev), 0);
8671 lpt_enable_clkout_dp(dev, true, true);
8673 lpt_disable_clkout_dp(dev);
8678 * Initialize reference clocks when the driver loads
8680 void intel_init_pch_refclk(struct drm_device *dev)
8682 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8683 ironlake_init_pch_refclk(dev);
8684 else if (HAS_PCH_LPT(dev))
8685 lpt_init_pch_refclk(dev);
8688 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8690 struct drm_device *dev = crtc_state->base.crtc->dev;
8691 struct drm_i915_private *dev_priv = dev->dev_private;
8692 struct drm_atomic_state *state = crtc_state->base.state;
8693 struct drm_connector *connector;
8694 struct drm_connector_state *connector_state;
8695 struct intel_encoder *encoder;
8696 int num_connectors = 0, i;
8697 bool is_lvds = false;
8699 for_each_connector_in_state(state, connector, connector_state, i) {
8700 if (connector_state->crtc != crtc_state->base.crtc)
8703 encoder = to_intel_encoder(connector_state->best_encoder);
8705 switch (encoder->type) {
8706 case INTEL_OUTPUT_LVDS:
8715 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8716 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8717 dev_priv->vbt.lvds_ssc_freq);
8718 return dev_priv->vbt.lvds_ssc_freq;
8724 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8726 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8728 int pipe = intel_crtc->pipe;
8733 switch (intel_crtc->config->pipe_bpp) {
8735 val |= PIPECONF_6BPC;
8738 val |= PIPECONF_8BPC;
8741 val |= PIPECONF_10BPC;
8744 val |= PIPECONF_12BPC;
8747 /* Case prevented by intel_choose_pipe_bpp_dither. */
8751 if (intel_crtc->config->dither)
8752 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8754 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8755 val |= PIPECONF_INTERLACED_ILK;
8757 val |= PIPECONF_PROGRESSIVE;
8759 if (intel_crtc->config->limited_color_range)
8760 val |= PIPECONF_COLOR_RANGE_SELECT;
8762 I915_WRITE(PIPECONF(pipe), val);
8763 POSTING_READ(PIPECONF(pipe));
8767 * Set up the pipe CSC unit.
8769 * Currently only full range RGB to limited range RGB conversion
8770 * is supported, but eventually this should handle various
8771 * RGB<->YCbCr scenarios as well.
8773 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8775 struct drm_device *dev = crtc->dev;
8776 struct drm_i915_private *dev_priv = dev->dev_private;
8777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8778 int pipe = intel_crtc->pipe;
8779 uint16_t coeff = 0x7800; /* 1.0 */
8782 * TODO: Check what kind of values actually come out of the pipe
8783 * with these coeff/postoff values and adjust to get the best
8784 * accuracy. Perhaps we even need to take the bpc value into
8788 if (intel_crtc->config->limited_color_range)
8789 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8792 * GY/GU and RY/RU should be the other way around according
8793 * to BSpec, but reality doesn't agree. Just set them up in
8794 * a way that results in the correct picture.
8796 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8797 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8799 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8800 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8802 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8803 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8805 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8806 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8807 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8809 if (INTEL_INFO(dev)->gen > 6) {
8810 uint16_t postoff = 0;
8812 if (intel_crtc->config->limited_color_range)
8813 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8815 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8816 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8817 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8819 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8821 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8823 if (intel_crtc->config->limited_color_range)
8824 mode |= CSC_BLACK_SCREEN_OFFSET;
8826 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8830 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8832 struct drm_device *dev = crtc->dev;
8833 struct drm_i915_private *dev_priv = dev->dev_private;
8834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8835 enum pipe pipe = intel_crtc->pipe;
8836 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8841 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8842 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8844 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8845 val |= PIPECONF_INTERLACED_ILK;
8847 val |= PIPECONF_PROGRESSIVE;
8849 I915_WRITE(PIPECONF(cpu_transcoder), val);
8850 POSTING_READ(PIPECONF(cpu_transcoder));
8852 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8853 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8855 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8858 switch (intel_crtc->config->pipe_bpp) {
8860 val |= PIPEMISC_DITHER_6_BPC;
8863 val |= PIPEMISC_DITHER_8_BPC;
8866 val |= PIPEMISC_DITHER_10_BPC;
8869 val |= PIPEMISC_DITHER_12_BPC;
8872 /* Case prevented by pipe_config_set_bpp. */
8876 if (intel_crtc->config->dither)
8877 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8879 I915_WRITE(PIPEMISC(pipe), val);
8883 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8884 struct intel_crtc_state *crtc_state,
8885 intel_clock_t *clock,
8886 bool *has_reduced_clock,
8887 intel_clock_t *reduced_clock)
8889 struct drm_device *dev = crtc->dev;
8890 struct drm_i915_private *dev_priv = dev->dev_private;
8892 const intel_limit_t *limit;
8895 refclk = ironlake_get_refclk(crtc_state);
8898 * Returns a set of divisors for the desired target clock with the given
8899 * refclk, or FALSE. The returned values represent the clock equation:
8900 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8902 limit = intel_limit(crtc_state, refclk);
8903 ret = dev_priv->display.find_dpll(limit, crtc_state,
8904 crtc_state->port_clock,
8905 refclk, NULL, clock);
8912 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8915 * Account for spread spectrum to avoid
8916 * oversubscribing the link. Max center spread
8917 * is 2.5%; use 5% for safety's sake.
8919 u32 bps = target_clock * bpp * 21 / 20;
8920 return DIV_ROUND_UP(bps, link_bw * 8);
8923 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8925 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8928 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8929 struct intel_crtc_state *crtc_state,
8931 intel_clock_t *reduced_clock, u32 *fp2)
8933 struct drm_crtc *crtc = &intel_crtc->base;
8934 struct drm_device *dev = crtc->dev;
8935 struct drm_i915_private *dev_priv = dev->dev_private;
8936 struct drm_atomic_state *state = crtc_state->base.state;
8937 struct drm_connector *connector;
8938 struct drm_connector_state *connector_state;
8939 struct intel_encoder *encoder;
8941 int factor, num_connectors = 0, i;
8942 bool is_lvds = false, is_sdvo = false;
8944 for_each_connector_in_state(state, connector, connector_state, i) {
8945 if (connector_state->crtc != crtc_state->base.crtc)
8948 encoder = to_intel_encoder(connector_state->best_encoder);
8950 switch (encoder->type) {
8951 case INTEL_OUTPUT_LVDS:
8954 case INTEL_OUTPUT_SDVO:
8955 case INTEL_OUTPUT_HDMI:
8965 /* Enable autotuning of the PLL clock (if permissible) */
8968 if ((intel_panel_use_ssc(dev_priv) &&
8969 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8970 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8972 } else if (crtc_state->sdvo_tv_clock)
8975 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8978 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8984 dpll |= DPLLB_MODE_LVDS;
8986 dpll |= DPLLB_MODE_DAC_SERIAL;
8988 dpll |= (crtc_state->pixel_multiplier - 1)
8989 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8992 dpll |= DPLL_SDVO_HIGH_SPEED;
8993 if (crtc_state->has_dp_encoder)
8994 dpll |= DPLL_SDVO_HIGH_SPEED;
8996 /* compute bitmask from p1 value */
8997 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8999 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9001 switch (crtc_state->dpll.p2) {
9003 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9006 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9009 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9012 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9016 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9017 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9019 dpll |= PLL_REF_INPUT_DREFCLK;
9021 return dpll | DPLL_VCO_ENABLE;
9024 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9025 struct intel_crtc_state *crtc_state)
9027 struct drm_device *dev = crtc->base.dev;
9028 intel_clock_t clock, reduced_clock;
9029 u32 dpll = 0, fp = 0, fp2 = 0;
9030 bool ok, has_reduced_clock = false;
9031 bool is_lvds = false;
9032 struct intel_shared_dpll *pll;
9034 memset(&crtc_state->dpll_hw_state, 0,
9035 sizeof(crtc_state->dpll_hw_state));
9037 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9039 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9040 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9042 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9043 &has_reduced_clock, &reduced_clock);
9044 if (!ok && !crtc_state->clock_set) {
9045 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9048 /* Compat-code for transition, will disappear. */
9049 if (!crtc_state->clock_set) {
9050 crtc_state->dpll.n = clock.n;
9051 crtc_state->dpll.m1 = clock.m1;
9052 crtc_state->dpll.m2 = clock.m2;
9053 crtc_state->dpll.p1 = clock.p1;
9054 crtc_state->dpll.p2 = clock.p2;
9057 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9058 if (crtc_state->has_pch_encoder) {
9059 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9060 if (has_reduced_clock)
9061 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9063 dpll = ironlake_compute_dpll(crtc, crtc_state,
9064 &fp, &reduced_clock,
9065 has_reduced_clock ? &fp2 : NULL);
9067 crtc_state->dpll_hw_state.dpll = dpll;
9068 crtc_state->dpll_hw_state.fp0 = fp;
9069 if (has_reduced_clock)
9070 crtc_state->dpll_hw_state.fp1 = fp2;
9072 crtc_state->dpll_hw_state.fp1 = fp;
9074 pll = intel_get_shared_dpll(crtc, crtc_state);
9076 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9077 pipe_name(crtc->pipe));
9082 if (is_lvds && has_reduced_clock)
9083 crtc->lowfreq_avail = true;
9085 crtc->lowfreq_avail = false;
9090 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9091 struct intel_link_m_n *m_n)
9093 struct drm_device *dev = crtc->base.dev;
9094 struct drm_i915_private *dev_priv = dev->dev_private;
9095 enum pipe pipe = crtc->pipe;
9097 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9098 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9099 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9101 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9102 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9103 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9106 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9107 enum transcoder transcoder,
9108 struct intel_link_m_n *m_n,
9109 struct intel_link_m_n *m2_n2)
9111 struct drm_device *dev = crtc->base.dev;
9112 struct drm_i915_private *dev_priv = dev->dev_private;
9113 enum pipe pipe = crtc->pipe;
9115 if (INTEL_INFO(dev)->gen >= 5) {
9116 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9117 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9118 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9120 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9121 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9122 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9123 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9124 * gen < 8) and if DRRS is supported (to make sure the
9125 * registers are not unnecessarily read).
9127 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9128 crtc->config->has_drrs) {
9129 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9130 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9131 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9133 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9134 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9135 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9138 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9139 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9140 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9142 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9143 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9144 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9148 void intel_dp_get_m_n(struct intel_crtc *crtc,
9149 struct intel_crtc_state *pipe_config)
9151 if (pipe_config->has_pch_encoder)
9152 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9154 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9155 &pipe_config->dp_m_n,
9156 &pipe_config->dp_m2_n2);
9159 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9160 struct intel_crtc_state *pipe_config)
9162 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9163 &pipe_config->fdi_m_n, NULL);
9166 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9167 struct intel_crtc_state *pipe_config)
9169 struct drm_device *dev = crtc->base.dev;
9170 struct drm_i915_private *dev_priv = dev->dev_private;
9171 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9172 uint32_t ps_ctrl = 0;
9176 /* find scaler attached to this pipe */
9177 for (i = 0; i < crtc->num_scalers; i++) {
9178 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9179 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9181 pipe_config->pch_pfit.enabled = true;
9182 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9183 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9188 scaler_state->scaler_id = id;
9190 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9192 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9197 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9198 struct intel_initial_plane_config *plane_config)
9200 struct drm_device *dev = crtc->base.dev;
9201 struct drm_i915_private *dev_priv = dev->dev_private;
9202 u32 val, base, offset, stride_mult, tiling;
9203 int pipe = crtc->pipe;
9204 int fourcc, pixel_format;
9205 unsigned int aligned_height;
9206 struct drm_framebuffer *fb;
9207 struct intel_framebuffer *intel_fb;
9209 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9211 DRM_DEBUG_KMS("failed to alloc fb\n");
9215 fb = &intel_fb->base;
9217 val = I915_READ(PLANE_CTL(pipe, 0));
9218 if (!(val & PLANE_CTL_ENABLE))
9221 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9222 fourcc = skl_format_to_fourcc(pixel_format,
9223 val & PLANE_CTL_ORDER_RGBX,
9224 val & PLANE_CTL_ALPHA_MASK);
9225 fb->pixel_format = fourcc;
9226 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9228 tiling = val & PLANE_CTL_TILED_MASK;
9230 case PLANE_CTL_TILED_LINEAR:
9231 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9233 case PLANE_CTL_TILED_X:
9234 plane_config->tiling = I915_TILING_X;
9235 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9237 case PLANE_CTL_TILED_Y:
9238 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9240 case PLANE_CTL_TILED_YF:
9241 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9244 MISSING_CASE(tiling);
9248 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9249 plane_config->base = base;
9251 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9253 val = I915_READ(PLANE_SIZE(pipe, 0));
9254 fb->height = ((val >> 16) & 0xfff) + 1;
9255 fb->width = ((val >> 0) & 0x1fff) + 1;
9257 val = I915_READ(PLANE_STRIDE(pipe, 0));
9258 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9260 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9262 aligned_height = intel_fb_align_height(dev, fb->height,
9266 plane_config->size = fb->pitches[0] * aligned_height;
9268 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9269 pipe_name(pipe), fb->width, fb->height,
9270 fb->bits_per_pixel, base, fb->pitches[0],
9271 plane_config->size);
9273 plane_config->fb = intel_fb;
9280 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9281 struct intel_crtc_state *pipe_config)
9283 struct drm_device *dev = crtc->base.dev;
9284 struct drm_i915_private *dev_priv = dev->dev_private;
9287 tmp = I915_READ(PF_CTL(crtc->pipe));
9289 if (tmp & PF_ENABLE) {
9290 pipe_config->pch_pfit.enabled = true;
9291 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9292 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9294 /* We currently do not free assignements of panel fitters on
9295 * ivb/hsw (since we don't use the higher upscaling modes which
9296 * differentiates them) so just WARN about this case for now. */
9298 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9299 PF_PIPE_SEL_IVB(crtc->pipe));
9305 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9306 struct intel_initial_plane_config *plane_config)
9308 struct drm_device *dev = crtc->base.dev;
9309 struct drm_i915_private *dev_priv = dev->dev_private;
9310 u32 val, base, offset;
9311 int pipe = crtc->pipe;
9312 int fourcc, pixel_format;
9313 unsigned int aligned_height;
9314 struct drm_framebuffer *fb;
9315 struct intel_framebuffer *intel_fb;
9317 val = I915_READ(DSPCNTR(pipe));
9318 if (!(val & DISPLAY_PLANE_ENABLE))
9321 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9323 DRM_DEBUG_KMS("failed to alloc fb\n");
9327 fb = &intel_fb->base;
9329 if (INTEL_INFO(dev)->gen >= 4) {
9330 if (val & DISPPLANE_TILED) {
9331 plane_config->tiling = I915_TILING_X;
9332 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9336 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9337 fourcc = i9xx_format_to_fourcc(pixel_format);
9338 fb->pixel_format = fourcc;
9339 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9341 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9342 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9343 offset = I915_READ(DSPOFFSET(pipe));
9345 if (plane_config->tiling)
9346 offset = I915_READ(DSPTILEOFF(pipe));
9348 offset = I915_READ(DSPLINOFF(pipe));
9350 plane_config->base = base;
9352 val = I915_READ(PIPESRC(pipe));
9353 fb->width = ((val >> 16) & 0xfff) + 1;
9354 fb->height = ((val >> 0) & 0xfff) + 1;
9356 val = I915_READ(DSPSTRIDE(pipe));
9357 fb->pitches[0] = val & 0xffffffc0;
9359 aligned_height = intel_fb_align_height(dev, fb->height,
9363 plane_config->size = fb->pitches[0] * aligned_height;
9365 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9366 pipe_name(pipe), fb->width, fb->height,
9367 fb->bits_per_pixel, base, fb->pitches[0],
9368 plane_config->size);
9370 plane_config->fb = intel_fb;
9373 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9374 struct intel_crtc_state *pipe_config)
9376 struct drm_device *dev = crtc->base.dev;
9377 struct drm_i915_private *dev_priv = dev->dev_private;
9378 enum intel_display_power_domain power_domain;
9382 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9383 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9386 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9387 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9390 tmp = I915_READ(PIPECONF(crtc->pipe));
9391 if (!(tmp & PIPECONF_ENABLE))
9394 switch (tmp & PIPECONF_BPC_MASK) {
9396 pipe_config->pipe_bpp = 18;
9399 pipe_config->pipe_bpp = 24;
9401 case PIPECONF_10BPC:
9402 pipe_config->pipe_bpp = 30;
9404 case PIPECONF_12BPC:
9405 pipe_config->pipe_bpp = 36;
9411 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9412 pipe_config->limited_color_range = true;
9414 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9415 struct intel_shared_dpll *pll;
9417 pipe_config->has_pch_encoder = true;
9419 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9420 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9421 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9423 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9425 if (HAS_PCH_IBX(dev_priv->dev)) {
9426 pipe_config->shared_dpll =
9427 (enum intel_dpll_id) crtc->pipe;
9429 tmp = I915_READ(PCH_DPLL_SEL);
9430 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9431 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9433 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9436 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9438 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9439 &pipe_config->dpll_hw_state));
9441 tmp = pipe_config->dpll_hw_state.dpll;
9442 pipe_config->pixel_multiplier =
9443 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9444 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9446 ironlake_pch_clock_get(crtc, pipe_config);
9448 pipe_config->pixel_multiplier = 1;
9451 intel_get_pipe_timings(crtc, pipe_config);
9453 ironlake_get_pfit_config(crtc, pipe_config);
9458 intel_display_power_put(dev_priv, power_domain);
9463 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9465 struct drm_device *dev = dev_priv->dev;
9466 struct intel_crtc *crtc;
9468 for_each_intel_crtc(dev, crtc)
9469 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9470 pipe_name(crtc->pipe));
9472 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9473 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9474 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9475 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9476 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9477 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9478 "CPU PWM1 enabled\n");
9479 if (IS_HASWELL(dev))
9480 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9481 "CPU PWM2 enabled\n");
9482 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9483 "PCH PWM1 enabled\n");
9484 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9485 "Utility pin enabled\n");
9486 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9489 * In theory we can still leave IRQs enabled, as long as only the HPD
9490 * interrupts remain enabled. We used to check for that, but since it's
9491 * gen-specific and since we only disable LCPLL after we fully disable
9492 * the interrupts, the check below should be enough.
9494 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9497 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9499 struct drm_device *dev = dev_priv->dev;
9501 if (IS_HASWELL(dev))
9502 return I915_READ(D_COMP_HSW);
9504 return I915_READ(D_COMP_BDW);
9507 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9509 struct drm_device *dev = dev_priv->dev;
9511 if (IS_HASWELL(dev)) {
9512 mutex_lock(&dev_priv->rps.hw_lock);
9513 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9515 DRM_ERROR("Failed to write to D_COMP\n");
9516 mutex_unlock(&dev_priv->rps.hw_lock);
9518 I915_WRITE(D_COMP_BDW, val);
9519 POSTING_READ(D_COMP_BDW);
9524 * This function implements pieces of two sequences from BSpec:
9525 * - Sequence for display software to disable LCPLL
9526 * - Sequence for display software to allow package C8+
9527 * The steps implemented here are just the steps that actually touch the LCPLL
9528 * register. Callers should take care of disabling all the display engine
9529 * functions, doing the mode unset, fixing interrupts, etc.
9531 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9532 bool switch_to_fclk, bool allow_power_down)
9536 assert_can_disable_lcpll(dev_priv);
9538 val = I915_READ(LCPLL_CTL);
9540 if (switch_to_fclk) {
9541 val |= LCPLL_CD_SOURCE_FCLK;
9542 I915_WRITE(LCPLL_CTL, val);
9544 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9545 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9546 DRM_ERROR("Switching to FCLK failed\n");
9548 val = I915_READ(LCPLL_CTL);
9551 val |= LCPLL_PLL_DISABLE;
9552 I915_WRITE(LCPLL_CTL, val);
9553 POSTING_READ(LCPLL_CTL);
9555 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9556 DRM_ERROR("LCPLL still locked\n");
9558 val = hsw_read_dcomp(dev_priv);
9559 val |= D_COMP_COMP_DISABLE;
9560 hsw_write_dcomp(dev_priv, val);
9563 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9565 DRM_ERROR("D_COMP RCOMP still in progress\n");
9567 if (allow_power_down) {
9568 val = I915_READ(LCPLL_CTL);
9569 val |= LCPLL_POWER_DOWN_ALLOW;
9570 I915_WRITE(LCPLL_CTL, val);
9571 POSTING_READ(LCPLL_CTL);
9576 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9579 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9583 val = I915_READ(LCPLL_CTL);
9585 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9586 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9590 * Make sure we're not on PC8 state before disabling PC8, otherwise
9591 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9593 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9595 if (val & LCPLL_POWER_DOWN_ALLOW) {
9596 val &= ~LCPLL_POWER_DOWN_ALLOW;
9597 I915_WRITE(LCPLL_CTL, val);
9598 POSTING_READ(LCPLL_CTL);
9601 val = hsw_read_dcomp(dev_priv);
9602 val |= D_COMP_COMP_FORCE;
9603 val &= ~D_COMP_COMP_DISABLE;
9604 hsw_write_dcomp(dev_priv, val);
9606 val = I915_READ(LCPLL_CTL);
9607 val &= ~LCPLL_PLL_DISABLE;
9608 I915_WRITE(LCPLL_CTL, val);
9610 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9611 DRM_ERROR("LCPLL not locked yet\n");
9613 if (val & LCPLL_CD_SOURCE_FCLK) {
9614 val = I915_READ(LCPLL_CTL);
9615 val &= ~LCPLL_CD_SOURCE_FCLK;
9616 I915_WRITE(LCPLL_CTL, val);
9618 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9619 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9620 DRM_ERROR("Switching back to LCPLL failed\n");
9623 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9624 intel_update_cdclk(dev_priv->dev);
9628 * Package states C8 and deeper are really deep PC states that can only be
9629 * reached when all the devices on the system allow it, so even if the graphics
9630 * device allows PC8+, it doesn't mean the system will actually get to these
9631 * states. Our driver only allows PC8+ when going into runtime PM.
9633 * The requirements for PC8+ are that all the outputs are disabled, the power
9634 * well is disabled and most interrupts are disabled, and these are also
9635 * requirements for runtime PM. When these conditions are met, we manually do
9636 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9637 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9640 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9641 * the state of some registers, so when we come back from PC8+ we need to
9642 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9643 * need to take care of the registers kept by RC6. Notice that this happens even
9644 * if we don't put the device in PCI D3 state (which is what currently happens
9645 * because of the runtime PM support).
9647 * For more, read "Display Sequences for Package C8" on the hardware
9650 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9652 struct drm_device *dev = dev_priv->dev;
9655 DRM_DEBUG_KMS("Enabling package C8+\n");
9657 if (HAS_PCH_LPT_LP(dev)) {
9658 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9659 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9660 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9663 lpt_disable_clkout_dp(dev);
9664 hsw_disable_lcpll(dev_priv, true, true);
9667 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9669 struct drm_device *dev = dev_priv->dev;
9672 DRM_DEBUG_KMS("Disabling package C8+\n");
9674 hsw_restore_lcpll(dev_priv);
9675 lpt_init_pch_refclk(dev);
9677 if (HAS_PCH_LPT_LP(dev)) {
9678 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9679 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9680 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9683 intel_prepare_ddi(dev);
9686 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9688 struct drm_device *dev = old_state->dev;
9689 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9691 broxton_set_cdclk(dev, req_cdclk);
9694 /* compute the max rate for new configuration */
9695 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9697 struct intel_crtc *intel_crtc;
9698 struct intel_crtc_state *crtc_state;
9699 int max_pixel_rate = 0;
9701 for_each_intel_crtc(state->dev, intel_crtc) {
9704 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9705 if (IS_ERR(crtc_state))
9706 return PTR_ERR(crtc_state);
9708 if (!crtc_state->base.enable)
9711 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9713 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9714 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9715 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9717 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9720 return max_pixel_rate;
9723 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9725 struct drm_i915_private *dev_priv = dev->dev_private;
9729 if (WARN((I915_READ(LCPLL_CTL) &
9730 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9731 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9732 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9733 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9734 "trying to change cdclk frequency with cdclk not enabled\n"))
9737 mutex_lock(&dev_priv->rps.hw_lock);
9738 ret = sandybridge_pcode_write(dev_priv,
9739 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9740 mutex_unlock(&dev_priv->rps.hw_lock);
9742 DRM_ERROR("failed to inform pcode about cdclk change\n");
9746 val = I915_READ(LCPLL_CTL);
9747 val |= LCPLL_CD_SOURCE_FCLK;
9748 I915_WRITE(LCPLL_CTL, val);
9750 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9751 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9752 DRM_ERROR("Switching to FCLK failed\n");
9754 val = I915_READ(LCPLL_CTL);
9755 val &= ~LCPLL_CLK_FREQ_MASK;
9759 val |= LCPLL_CLK_FREQ_450;
9763 val |= LCPLL_CLK_FREQ_54O_BDW;
9767 val |= LCPLL_CLK_FREQ_337_5_BDW;
9771 val |= LCPLL_CLK_FREQ_675_BDW;
9775 WARN(1, "invalid cdclk frequency\n");
9779 I915_WRITE(LCPLL_CTL, val);
9781 val = I915_READ(LCPLL_CTL);
9782 val &= ~LCPLL_CD_SOURCE_FCLK;
9783 I915_WRITE(LCPLL_CTL, val);
9785 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9786 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9787 DRM_ERROR("Switching back to LCPLL failed\n");
9789 mutex_lock(&dev_priv->rps.hw_lock);
9790 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9791 mutex_unlock(&dev_priv->rps.hw_lock);
9793 intel_update_cdclk(dev);
9795 WARN(cdclk != dev_priv->cdclk_freq,
9796 "cdclk requested %d kHz but got %d kHz\n",
9797 cdclk, dev_priv->cdclk_freq);
9800 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9802 struct drm_i915_private *dev_priv = to_i915(state->dev);
9803 int max_pixclk = ilk_max_pixel_rate(state);
9807 * FIXME should also account for plane ratio
9808 * once 64bpp pixel formats are supported.
9810 if (max_pixclk > 540000)
9812 else if (max_pixclk > 450000)
9814 else if (max_pixclk > 337500)
9819 if (cdclk > dev_priv->max_cdclk_freq) {
9820 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9821 cdclk, dev_priv->max_cdclk_freq);
9825 to_intel_atomic_state(state)->cdclk = cdclk;
9830 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9832 struct drm_device *dev = old_state->dev;
9833 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9835 broadwell_set_cdclk(dev, req_cdclk);
9838 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9839 struct intel_crtc_state *crtc_state)
9841 if (!intel_ddi_pll_select(crtc, crtc_state))
9844 crtc->lowfreq_avail = false;
9849 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9851 struct intel_crtc_state *pipe_config)
9855 pipe_config->ddi_pll_sel = SKL_DPLL0;
9856 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9859 pipe_config->ddi_pll_sel = SKL_DPLL1;
9860 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9863 pipe_config->ddi_pll_sel = SKL_DPLL2;
9864 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9867 DRM_ERROR("Incorrect port type\n");
9871 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9873 struct intel_crtc_state *pipe_config)
9875 u32 temp, dpll_ctl1;
9877 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9878 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9880 switch (pipe_config->ddi_pll_sel) {
9883 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9884 * of the shared DPLL framework and thus needs to be read out
9887 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9888 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9891 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9894 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9897 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9902 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9904 struct intel_crtc_state *pipe_config)
9906 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9908 switch (pipe_config->ddi_pll_sel) {
9909 case PORT_CLK_SEL_WRPLL1:
9910 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9912 case PORT_CLK_SEL_WRPLL2:
9913 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9915 case PORT_CLK_SEL_SPLL:
9916 pipe_config->shared_dpll = DPLL_ID_SPLL;
9921 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9922 struct intel_crtc_state *pipe_config)
9924 struct drm_device *dev = crtc->base.dev;
9925 struct drm_i915_private *dev_priv = dev->dev_private;
9926 struct intel_shared_dpll *pll;
9930 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9932 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9934 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9935 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9936 else if (IS_BROXTON(dev))
9937 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9939 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9941 if (pipe_config->shared_dpll >= 0) {
9942 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9944 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9945 &pipe_config->dpll_hw_state));
9949 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9950 * DDI E. So just check whether this pipe is wired to DDI E and whether
9951 * the PCH transcoder is on.
9953 if (INTEL_INFO(dev)->gen < 9 &&
9954 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9955 pipe_config->has_pch_encoder = true;
9957 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9958 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9959 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9961 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9965 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9966 struct intel_crtc_state *pipe_config)
9968 struct drm_device *dev = crtc->base.dev;
9969 struct drm_i915_private *dev_priv = dev->dev_private;
9970 enum intel_display_power_domain power_domain;
9971 unsigned long power_domain_mask;
9975 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9976 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9978 power_domain_mask = BIT(power_domain);
9982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9983 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9985 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9986 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9987 enum pipe trans_edp_pipe;
9988 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9990 WARN(1, "unknown pipe linked to edp transcoder\n");
9991 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9992 case TRANS_DDI_EDP_INPUT_A_ON:
9993 trans_edp_pipe = PIPE_A;
9995 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9996 trans_edp_pipe = PIPE_B;
9998 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9999 trans_edp_pipe = PIPE_C;
10003 if (trans_edp_pipe == crtc->pipe)
10004 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10007 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10008 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10010 power_domain_mask |= BIT(power_domain);
10012 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10013 if (!(tmp & PIPECONF_ENABLE))
10016 haswell_get_ddi_port_state(crtc, pipe_config);
10018 intel_get_pipe_timings(crtc, pipe_config);
10020 if (INTEL_INFO(dev)->gen >= 9) {
10021 skl_init_scalers(dev, crtc, pipe_config);
10024 if (INTEL_INFO(dev)->gen >= 9) {
10025 pipe_config->scaler_state.scaler_id = -1;
10026 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10029 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10030 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10031 power_domain_mask |= BIT(power_domain);
10032 if (INTEL_INFO(dev)->gen >= 9)
10033 skylake_get_pfit_config(crtc, pipe_config);
10035 ironlake_get_pfit_config(crtc, pipe_config);
10038 if (IS_HASWELL(dev))
10039 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10040 (I915_READ(IPS_CTL) & IPS_ENABLE);
10042 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10043 pipe_config->pixel_multiplier =
10044 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10046 pipe_config->pixel_multiplier = 1;
10052 for_each_power_domain(power_domain, power_domain_mask)
10053 intel_display_power_put(dev_priv, power_domain);
10058 static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10060 struct drm_device *dev = crtc->dev;
10061 struct drm_i915_private *dev_priv = dev->dev_private;
10062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10063 uint32_t cntl = 0, size = 0;
10066 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10067 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
10068 unsigned int stride = roundup_pow_of_two(width) * 4;
10072 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10083 cntl |= CURSOR_ENABLE |
10084 CURSOR_GAMMA_ENABLE |
10085 CURSOR_FORMAT_ARGB |
10086 CURSOR_STRIDE(stride);
10088 size = (height << 12) | width;
10091 if (intel_crtc->cursor_cntl != 0 &&
10092 (intel_crtc->cursor_base != base ||
10093 intel_crtc->cursor_size != size ||
10094 intel_crtc->cursor_cntl != cntl)) {
10095 /* On these chipsets we can only modify the base/size/stride
10096 * whilst the cursor is disabled.
10098 I915_WRITE(CURCNTR(PIPE_A), 0);
10099 POSTING_READ(CURCNTR(PIPE_A));
10100 intel_crtc->cursor_cntl = 0;
10103 if (intel_crtc->cursor_base != base) {
10104 I915_WRITE(CURBASE(PIPE_A), base);
10105 intel_crtc->cursor_base = base;
10108 if (intel_crtc->cursor_size != size) {
10109 I915_WRITE(CURSIZE, size);
10110 intel_crtc->cursor_size = size;
10113 if (intel_crtc->cursor_cntl != cntl) {
10114 I915_WRITE(CURCNTR(PIPE_A), cntl);
10115 POSTING_READ(CURCNTR(PIPE_A));
10116 intel_crtc->cursor_cntl = cntl;
10120 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
10122 struct drm_device *dev = crtc->dev;
10123 struct drm_i915_private *dev_priv = dev->dev_private;
10124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10125 int pipe = intel_crtc->pipe;
10129 cntl = MCURSOR_GAMMA_ENABLE;
10130 switch (intel_crtc->base.cursor->state->crtc_w) {
10132 cntl |= CURSOR_MODE_64_ARGB_AX;
10135 cntl |= CURSOR_MODE_128_ARGB_AX;
10138 cntl |= CURSOR_MODE_256_ARGB_AX;
10141 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10144 cntl |= pipe << 28; /* Connect to correct pipe */
10147 cntl |= CURSOR_PIPE_CSC_ENABLE;
10150 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10151 cntl |= CURSOR_ROTATE_180;
10153 if (intel_crtc->cursor_cntl != cntl) {
10154 I915_WRITE(CURCNTR(pipe), cntl);
10155 POSTING_READ(CURCNTR(pipe));
10156 intel_crtc->cursor_cntl = cntl;
10159 /* and commit changes on next vblank */
10160 I915_WRITE(CURBASE(pipe), base);
10161 POSTING_READ(CURBASE(pipe));
10163 intel_crtc->cursor_base = base;
10166 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10167 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10170 struct drm_device *dev = crtc->dev;
10171 struct drm_i915_private *dev_priv = dev->dev_private;
10172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10173 int pipe = intel_crtc->pipe;
10174 struct drm_plane_state *cursor_state = crtc->cursor->state;
10175 int x = cursor_state->crtc_x;
10176 int y = cursor_state->crtc_y;
10177 u32 base = 0, pos = 0;
10179 base = intel_crtc->cursor_addr;
10181 if (x >= intel_crtc->config->pipe_src_w)
10184 if (y >= intel_crtc->config->pipe_src_h)
10188 if (x + cursor_state->crtc_w <= 0)
10191 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10194 pos |= x << CURSOR_X_SHIFT;
10197 if (y + cursor_state->crtc_h <= 0)
10200 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10203 pos |= y << CURSOR_Y_SHIFT;
10205 I915_WRITE(CURPOS(pipe), pos);
10207 /* ILK+ do this automagically */
10208 if (HAS_GMCH_DISPLAY(dev) &&
10209 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10210 base += (cursor_state->crtc_h *
10211 cursor_state->crtc_w - 1) * 4;
10214 if (IS_845G(dev) || IS_I865G(dev))
10215 i845_update_cursor(crtc, base, on);
10217 i9xx_update_cursor(crtc, base, on);
10220 static bool cursor_size_ok(struct drm_device *dev,
10221 uint32_t width, uint32_t height)
10223 if (width == 0 || height == 0)
10227 * 845g/865g are special in that they are only limited by
10228 * the width of their cursors, the height is arbitrary up to
10229 * the precision of the register. Everything else requires
10230 * square cursors, limited to a few power-of-two sizes.
10232 if (IS_845G(dev) || IS_I865G(dev)) {
10233 if ((width & 63) != 0)
10236 if (width > (IS_845G(dev) ? 64 : 512))
10242 switch (width | height) {
10257 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10258 u16 *blue, uint32_t start, uint32_t size)
10260 int end = (start + size > 256) ? 256 : start + size, i;
10261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10263 for (i = start; i < end; i++) {
10264 intel_crtc->lut_r[i] = red[i] >> 8;
10265 intel_crtc->lut_g[i] = green[i] >> 8;
10266 intel_crtc->lut_b[i] = blue[i] >> 8;
10269 intel_crtc_load_lut(crtc);
10272 /* VESA 640x480x72Hz mode to set on the pipe */
10273 static struct drm_display_mode load_detect_mode = {
10274 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10275 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10278 struct drm_framebuffer *
10279 __intel_framebuffer_create(struct drm_device *dev,
10280 struct drm_mode_fb_cmd2 *mode_cmd,
10281 struct drm_i915_gem_object *obj)
10283 struct intel_framebuffer *intel_fb;
10286 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10288 return ERR_PTR(-ENOMEM);
10290 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10294 return &intel_fb->base;
10298 return ERR_PTR(ret);
10301 static struct drm_framebuffer *
10302 intel_framebuffer_create(struct drm_device *dev,
10303 struct drm_mode_fb_cmd2 *mode_cmd,
10304 struct drm_i915_gem_object *obj)
10306 struct drm_framebuffer *fb;
10309 ret = i915_mutex_lock_interruptible(dev);
10311 return ERR_PTR(ret);
10312 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10313 mutex_unlock(&dev->struct_mutex);
10319 intel_framebuffer_pitch_for_width(int width, int bpp)
10321 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10322 return ALIGN(pitch, 64);
10326 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10328 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10329 return PAGE_ALIGN(pitch * mode->vdisplay);
10332 static struct drm_framebuffer *
10333 intel_framebuffer_create_for_mode(struct drm_device *dev,
10334 struct drm_display_mode *mode,
10335 int depth, int bpp)
10337 struct drm_framebuffer *fb;
10338 struct drm_i915_gem_object *obj;
10339 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10341 obj = i915_gem_alloc_object(dev,
10342 intel_framebuffer_size_for_mode(mode, bpp));
10344 return ERR_PTR(-ENOMEM);
10346 mode_cmd.width = mode->hdisplay;
10347 mode_cmd.height = mode->vdisplay;
10348 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10350 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10352 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10354 drm_gem_object_unreference_unlocked(&obj->base);
10359 static struct drm_framebuffer *
10360 mode_fits_in_fbdev(struct drm_device *dev,
10361 struct drm_display_mode *mode)
10363 #ifdef CONFIG_DRM_FBDEV_EMULATION
10364 struct drm_i915_private *dev_priv = dev->dev_private;
10365 struct drm_i915_gem_object *obj;
10366 struct drm_framebuffer *fb;
10368 if (!dev_priv->fbdev)
10371 if (!dev_priv->fbdev->fb)
10374 obj = dev_priv->fbdev->fb->obj;
10377 fb = &dev_priv->fbdev->fb->base;
10378 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10379 fb->bits_per_pixel))
10382 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10391 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10392 struct drm_crtc *crtc,
10393 struct drm_display_mode *mode,
10394 struct drm_framebuffer *fb,
10397 struct drm_plane_state *plane_state;
10398 int hdisplay, vdisplay;
10401 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10402 if (IS_ERR(plane_state))
10403 return PTR_ERR(plane_state);
10406 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10408 hdisplay = vdisplay = 0;
10410 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10413 drm_atomic_set_fb_for_plane(plane_state, fb);
10414 plane_state->crtc_x = 0;
10415 plane_state->crtc_y = 0;
10416 plane_state->crtc_w = hdisplay;
10417 plane_state->crtc_h = vdisplay;
10418 plane_state->src_x = x << 16;
10419 plane_state->src_y = y << 16;
10420 plane_state->src_w = hdisplay << 16;
10421 plane_state->src_h = vdisplay << 16;
10426 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10427 struct drm_display_mode *mode,
10428 struct intel_load_detect_pipe *old,
10429 struct drm_modeset_acquire_ctx *ctx)
10431 struct intel_crtc *intel_crtc;
10432 struct intel_encoder *intel_encoder =
10433 intel_attached_encoder(connector);
10434 struct drm_crtc *possible_crtc;
10435 struct drm_encoder *encoder = &intel_encoder->base;
10436 struct drm_crtc *crtc = NULL;
10437 struct drm_device *dev = encoder->dev;
10438 struct drm_framebuffer *fb;
10439 struct drm_mode_config *config = &dev->mode_config;
10440 struct drm_atomic_state *state = NULL;
10441 struct drm_connector_state *connector_state;
10442 struct intel_crtc_state *crtc_state;
10445 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10446 connector->base.id, connector->name,
10447 encoder->base.id, encoder->name);
10450 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10455 * Algorithm gets a little messy:
10457 * - if the connector already has an assigned crtc, use it (but make
10458 * sure it's on first)
10460 * - try to find the first unused crtc that can drive this connector,
10461 * and use that if we find one
10464 /* See if we already have a CRTC for this connector */
10465 if (encoder->crtc) {
10466 crtc = encoder->crtc;
10468 ret = drm_modeset_lock(&crtc->mutex, ctx);
10471 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10475 old->dpms_mode = connector->dpms;
10476 old->load_detect_temp = false;
10478 /* Make sure the crtc and connector are running */
10479 if (connector->dpms != DRM_MODE_DPMS_ON)
10480 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10485 /* Find an unused one (if possible) */
10486 for_each_crtc(dev, possible_crtc) {
10488 if (!(encoder->possible_crtcs & (1 << i)))
10490 if (possible_crtc->state->enable)
10493 crtc = possible_crtc;
10498 * If we didn't find an unused CRTC, don't use any.
10501 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10505 ret = drm_modeset_lock(&crtc->mutex, ctx);
10508 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10512 intel_crtc = to_intel_crtc(crtc);
10513 old->dpms_mode = connector->dpms;
10514 old->load_detect_temp = true;
10515 old->release_fb = NULL;
10517 state = drm_atomic_state_alloc(dev);
10521 state->acquire_ctx = ctx;
10523 connector_state = drm_atomic_get_connector_state(state, connector);
10524 if (IS_ERR(connector_state)) {
10525 ret = PTR_ERR(connector_state);
10529 connector_state->crtc = crtc;
10530 connector_state->best_encoder = &intel_encoder->base;
10532 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10533 if (IS_ERR(crtc_state)) {
10534 ret = PTR_ERR(crtc_state);
10538 crtc_state->base.active = crtc_state->base.enable = true;
10541 mode = &load_detect_mode;
10543 /* We need a framebuffer large enough to accommodate all accesses
10544 * that the plane may generate whilst we perform load detection.
10545 * We can not rely on the fbcon either being present (we get called
10546 * during its initialisation to detect all boot displays, or it may
10547 * not even exist) or that it is large enough to satisfy the
10550 fb = mode_fits_in_fbdev(dev, mode);
10552 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10553 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10554 old->release_fb = fb;
10556 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10558 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10562 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10566 drm_mode_copy(&crtc_state->base.mode, mode);
10568 if (drm_atomic_commit(state)) {
10569 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10570 if (old->release_fb)
10571 old->release_fb->funcs->destroy(old->release_fb);
10574 crtc->primary->crtc = crtc;
10576 /* let the connector get through one full cycle before testing */
10577 intel_wait_for_vblank(dev, intel_crtc->pipe);
10581 drm_atomic_state_free(state);
10584 if (ret == -EDEADLK) {
10585 drm_modeset_backoff(ctx);
10592 void intel_release_load_detect_pipe(struct drm_connector *connector,
10593 struct intel_load_detect_pipe *old,
10594 struct drm_modeset_acquire_ctx *ctx)
10596 struct drm_device *dev = connector->dev;
10597 struct intel_encoder *intel_encoder =
10598 intel_attached_encoder(connector);
10599 struct drm_encoder *encoder = &intel_encoder->base;
10600 struct drm_crtc *crtc = encoder->crtc;
10601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10602 struct drm_atomic_state *state;
10603 struct drm_connector_state *connector_state;
10604 struct intel_crtc_state *crtc_state;
10607 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10608 connector->base.id, connector->name,
10609 encoder->base.id, encoder->name);
10611 if (old->load_detect_temp) {
10612 state = drm_atomic_state_alloc(dev);
10616 state->acquire_ctx = ctx;
10618 connector_state = drm_atomic_get_connector_state(state, connector);
10619 if (IS_ERR(connector_state))
10622 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10623 if (IS_ERR(crtc_state))
10626 connector_state->best_encoder = NULL;
10627 connector_state->crtc = NULL;
10629 crtc_state->base.enable = crtc_state->base.active = false;
10631 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10636 ret = drm_atomic_commit(state);
10640 if (old->release_fb) {
10641 drm_framebuffer_unregister_private(old->release_fb);
10642 drm_framebuffer_unreference(old->release_fb);
10648 /* Switch crtc and encoder back off if necessary */
10649 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10650 connector->funcs->dpms(connector, old->dpms_mode);
10654 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10655 drm_atomic_state_free(state);
10658 static int i9xx_pll_refclk(struct drm_device *dev,
10659 const struct intel_crtc_state *pipe_config)
10661 struct drm_i915_private *dev_priv = dev->dev_private;
10662 u32 dpll = pipe_config->dpll_hw_state.dpll;
10664 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10665 return dev_priv->vbt.lvds_ssc_freq;
10666 else if (HAS_PCH_SPLIT(dev))
10668 else if (!IS_GEN2(dev))
10674 /* Returns the clock of the currently programmed mode of the given pipe. */
10675 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10676 struct intel_crtc_state *pipe_config)
10678 struct drm_device *dev = crtc->base.dev;
10679 struct drm_i915_private *dev_priv = dev->dev_private;
10680 int pipe = pipe_config->cpu_transcoder;
10681 u32 dpll = pipe_config->dpll_hw_state.dpll;
10683 intel_clock_t clock;
10685 int refclk = i9xx_pll_refclk(dev, pipe_config);
10687 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10688 fp = pipe_config->dpll_hw_state.fp0;
10690 fp = pipe_config->dpll_hw_state.fp1;
10692 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10693 if (IS_PINEVIEW(dev)) {
10694 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10695 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10697 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10698 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10701 if (!IS_GEN2(dev)) {
10702 if (IS_PINEVIEW(dev))
10703 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10704 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10706 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10707 DPLL_FPA01_P1_POST_DIV_SHIFT);
10709 switch (dpll & DPLL_MODE_MASK) {
10710 case DPLLB_MODE_DAC_SERIAL:
10711 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10714 case DPLLB_MODE_LVDS:
10715 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10719 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10720 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10724 if (IS_PINEVIEW(dev))
10725 port_clock = pnv_calc_dpll_params(refclk, &clock);
10727 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10729 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10730 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10733 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10734 DPLL_FPA01_P1_POST_DIV_SHIFT);
10736 if (lvds & LVDS_CLKB_POWER_UP)
10741 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10744 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10745 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10747 if (dpll & PLL_P2_DIVIDE_BY_4)
10753 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10757 * This value includes pixel_multiplier. We will use
10758 * port_clock to compute adjusted_mode.crtc_clock in the
10759 * encoder's get_config() function.
10761 pipe_config->port_clock = port_clock;
10764 int intel_dotclock_calculate(int link_freq,
10765 const struct intel_link_m_n *m_n)
10768 * The calculation for the data clock is:
10769 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10770 * But we want to avoid losing precison if possible, so:
10771 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10773 * and the link clock is simpler:
10774 * link_clock = (m * link_clock) / n
10780 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10783 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10784 struct intel_crtc_state *pipe_config)
10786 struct drm_device *dev = crtc->base.dev;
10788 /* read out port_clock from the DPLL */
10789 i9xx_crtc_clock_get(crtc, pipe_config);
10792 * This value does not include pixel_multiplier.
10793 * We will check that port_clock and adjusted_mode.crtc_clock
10794 * agree once we know their relationship in the encoder's
10795 * get_config() function.
10797 pipe_config->base.adjusted_mode.crtc_clock =
10798 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10799 &pipe_config->fdi_m_n);
10802 /** Returns the currently programmed mode of the given pipe. */
10803 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10804 struct drm_crtc *crtc)
10806 struct drm_i915_private *dev_priv = dev->dev_private;
10807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10808 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10809 struct drm_display_mode *mode;
10810 struct intel_crtc_state pipe_config;
10811 int htot = I915_READ(HTOTAL(cpu_transcoder));
10812 int hsync = I915_READ(HSYNC(cpu_transcoder));
10813 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10814 int vsync = I915_READ(VSYNC(cpu_transcoder));
10815 enum pipe pipe = intel_crtc->pipe;
10817 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10822 * Construct a pipe_config sufficient for getting the clock info
10823 * back out of crtc_clock_get.
10825 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10826 * to use a real value here instead.
10828 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10829 pipe_config.pixel_multiplier = 1;
10830 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10831 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10832 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10833 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10835 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10836 mode->hdisplay = (htot & 0xffff) + 1;
10837 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10838 mode->hsync_start = (hsync & 0xffff) + 1;
10839 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10840 mode->vdisplay = (vtot & 0xffff) + 1;
10841 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10842 mode->vsync_start = (vsync & 0xffff) + 1;
10843 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10845 drm_mode_set_name(mode);
10850 void intel_mark_busy(struct drm_device *dev)
10852 struct drm_i915_private *dev_priv = dev->dev_private;
10854 if (dev_priv->mm.busy)
10857 intel_runtime_pm_get(dev_priv);
10858 i915_update_gfx_val(dev_priv);
10859 if (INTEL_INFO(dev)->gen >= 6)
10860 gen6_rps_busy(dev_priv);
10861 dev_priv->mm.busy = true;
10864 void intel_mark_idle(struct drm_device *dev)
10866 struct drm_i915_private *dev_priv = dev->dev_private;
10868 if (!dev_priv->mm.busy)
10871 dev_priv->mm.busy = false;
10873 if (INTEL_INFO(dev)->gen >= 6)
10874 gen6_rps_idle(dev->dev_private);
10876 intel_runtime_pm_put(dev_priv);
10879 static void intel_crtc_destroy(struct drm_crtc *crtc)
10881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10882 struct drm_device *dev = crtc->dev;
10883 struct intel_unpin_work *work;
10885 spin_lock_irq(&dev->event_lock);
10886 work = intel_crtc->unpin_work;
10887 intel_crtc->unpin_work = NULL;
10888 spin_unlock_irq(&dev->event_lock);
10891 cancel_work_sync(&work->work);
10895 drm_crtc_cleanup(crtc);
10900 static void intel_unpin_work_fn(struct work_struct *__work)
10902 struct intel_unpin_work *work =
10903 container_of(__work, struct intel_unpin_work, work);
10904 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10905 struct drm_device *dev = crtc->base.dev;
10906 struct drm_plane *primary = crtc->base.primary;
10908 mutex_lock(&dev->struct_mutex);
10909 intel_unpin_fb_obj(work->old_fb, primary->state);
10910 drm_gem_object_unreference(&work->pending_flip_obj->base);
10912 if (work->flip_queued_req)
10913 i915_gem_request_assign(&work->flip_queued_req, NULL);
10914 mutex_unlock(&dev->struct_mutex);
10916 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10917 drm_framebuffer_unreference(work->old_fb);
10919 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10920 atomic_dec(&crtc->unpin_work_count);
10925 static void do_intel_finish_page_flip(struct drm_device *dev,
10926 struct drm_crtc *crtc)
10928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10929 struct intel_unpin_work *work;
10930 unsigned long flags;
10932 /* Ignore early vblank irqs */
10933 if (intel_crtc == NULL)
10937 * This is called both by irq handlers and the reset code (to complete
10938 * lost pageflips) so needs the full irqsave spinlocks.
10940 spin_lock_irqsave(&dev->event_lock, flags);
10941 work = intel_crtc->unpin_work;
10943 /* Ensure we don't miss a work->pending update ... */
10946 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10947 spin_unlock_irqrestore(&dev->event_lock, flags);
10951 page_flip_completed(intel_crtc);
10953 spin_unlock_irqrestore(&dev->event_lock, flags);
10956 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10958 struct drm_i915_private *dev_priv = dev->dev_private;
10959 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10961 do_intel_finish_page_flip(dev, crtc);
10964 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10966 struct drm_i915_private *dev_priv = dev->dev_private;
10967 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10969 do_intel_finish_page_flip(dev, crtc);
10972 /* Is 'a' after or equal to 'b'? */
10973 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10975 return !((a - b) & 0x80000000);
10978 static bool page_flip_finished(struct intel_crtc *crtc)
10980 struct drm_device *dev = crtc->base.dev;
10981 struct drm_i915_private *dev_priv = dev->dev_private;
10983 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10984 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10988 * The relevant registers doen't exist on pre-ctg.
10989 * As the flip done interrupt doesn't trigger for mmio
10990 * flips on gmch platforms, a flip count check isn't
10991 * really needed there. But since ctg has the registers,
10992 * include it in the check anyway.
10994 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10998 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10999 * used the same base address. In that case the mmio flip might
11000 * have completed, but the CS hasn't even executed the flip yet.
11002 * A flip count check isn't enough as the CS might have updated
11003 * the base address just after start of vblank, but before we
11004 * managed to process the interrupt. This means we'd complete the
11005 * CS flip too soon.
11007 * Combining both checks should get us a good enough result. It may
11008 * still happen that the CS flip has been executed, but has not
11009 * yet actually completed. But in case the base address is the same
11010 * anyway, we don't really care.
11012 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11013 crtc->unpin_work->gtt_offset &&
11014 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11015 crtc->unpin_work->flip_count);
11018 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11020 struct drm_i915_private *dev_priv = dev->dev_private;
11021 struct intel_crtc *intel_crtc =
11022 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11023 unsigned long flags;
11027 * This is called both by irq handlers and the reset code (to complete
11028 * lost pageflips) so needs the full irqsave spinlocks.
11030 * NB: An MMIO update of the plane base pointer will also
11031 * generate a page-flip completion irq, i.e. every modeset
11032 * is also accompanied by a spurious intel_prepare_page_flip().
11034 spin_lock_irqsave(&dev->event_lock, flags);
11035 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11036 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11037 spin_unlock_irqrestore(&dev->event_lock, flags);
11040 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11042 /* Ensure that the work item is consistent when activating it ... */
11044 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11045 /* and that it is marked active as soon as the irq could fire. */
11049 static int intel_gen2_queue_flip(struct drm_device *dev,
11050 struct drm_crtc *crtc,
11051 struct drm_framebuffer *fb,
11052 struct drm_i915_gem_object *obj,
11053 struct drm_i915_gem_request *req,
11056 struct intel_engine_cs *ring = req->ring;
11057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11061 ret = intel_ring_begin(req, 6);
11065 /* Can't queue multiple flips, so wait for the previous
11066 * one to finish before executing the next.
11068 if (intel_crtc->plane)
11069 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11071 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11072 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11073 intel_ring_emit(ring, MI_NOOP);
11074 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11075 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11076 intel_ring_emit(ring, fb->pitches[0]);
11077 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11078 intel_ring_emit(ring, 0); /* aux display base address, unused */
11080 intel_mark_page_flip_active(intel_crtc->unpin_work);
11084 static int intel_gen3_queue_flip(struct drm_device *dev,
11085 struct drm_crtc *crtc,
11086 struct drm_framebuffer *fb,
11087 struct drm_i915_gem_object *obj,
11088 struct drm_i915_gem_request *req,
11091 struct intel_engine_cs *ring = req->ring;
11092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11096 ret = intel_ring_begin(req, 6);
11100 if (intel_crtc->plane)
11101 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11103 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11104 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11105 intel_ring_emit(ring, MI_NOOP);
11106 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11107 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11108 intel_ring_emit(ring, fb->pitches[0]);
11109 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11110 intel_ring_emit(ring, MI_NOOP);
11112 intel_mark_page_flip_active(intel_crtc->unpin_work);
11116 static int intel_gen4_queue_flip(struct drm_device *dev,
11117 struct drm_crtc *crtc,
11118 struct drm_framebuffer *fb,
11119 struct drm_i915_gem_object *obj,
11120 struct drm_i915_gem_request *req,
11123 struct intel_engine_cs *ring = req->ring;
11124 struct drm_i915_private *dev_priv = dev->dev_private;
11125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11126 uint32_t pf, pipesrc;
11129 ret = intel_ring_begin(req, 4);
11133 /* i965+ uses the linear or tiled offsets from the
11134 * Display Registers (which do not change across a page-flip)
11135 * so we need only reprogram the base address.
11137 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11139 intel_ring_emit(ring, fb->pitches[0]);
11140 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11143 /* XXX Enabling the panel-fitter across page-flip is so far
11144 * untested on non-native modes, so ignore it for now.
11145 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11148 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11149 intel_ring_emit(ring, pf | pipesrc);
11151 intel_mark_page_flip_active(intel_crtc->unpin_work);
11155 static int intel_gen6_queue_flip(struct drm_device *dev,
11156 struct drm_crtc *crtc,
11157 struct drm_framebuffer *fb,
11158 struct drm_i915_gem_object *obj,
11159 struct drm_i915_gem_request *req,
11162 struct intel_engine_cs *ring = req->ring;
11163 struct drm_i915_private *dev_priv = dev->dev_private;
11164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11165 uint32_t pf, pipesrc;
11168 ret = intel_ring_begin(req, 4);
11172 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11173 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11174 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11175 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11177 /* Contrary to the suggestions in the documentation,
11178 * "Enable Panel Fitter" does not seem to be required when page
11179 * flipping with a non-native mode, and worse causes a normal
11181 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11184 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11185 intel_ring_emit(ring, pf | pipesrc);
11187 intel_mark_page_flip_active(intel_crtc->unpin_work);
11191 static int intel_gen7_queue_flip(struct drm_device *dev,
11192 struct drm_crtc *crtc,
11193 struct drm_framebuffer *fb,
11194 struct drm_i915_gem_object *obj,
11195 struct drm_i915_gem_request *req,
11198 struct intel_engine_cs *ring = req->ring;
11199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11200 uint32_t plane_bit = 0;
11203 switch (intel_crtc->plane) {
11205 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11208 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11211 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11214 WARN_ONCE(1, "unknown plane in flip command\n");
11219 if (ring->id == RCS) {
11222 * On Gen 8, SRM is now taking an extra dword to accommodate
11223 * 48bits addresses, and we need a NOOP for the batch size to
11231 * BSpec MI_DISPLAY_FLIP for IVB:
11232 * "The full packet must be contained within the same cache line."
11234 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11235 * cacheline, if we ever start emitting more commands before
11236 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11237 * then do the cacheline alignment, and finally emit the
11240 ret = intel_ring_cacheline_align(req);
11244 ret = intel_ring_begin(req, len);
11248 /* Unmask the flip-done completion message. Note that the bspec says that
11249 * we should do this for both the BCS and RCS, and that we must not unmask
11250 * more than one flip event at any time (or ensure that one flip message
11251 * can be sent by waiting for flip-done prior to queueing new flips).
11252 * Experimentation says that BCS works despite DERRMR masking all
11253 * flip-done completion events and that unmasking all planes at once
11254 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11255 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11257 if (ring->id == RCS) {
11258 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11259 intel_ring_emit_reg(ring, DERRMR);
11260 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11261 DERRMR_PIPEB_PRI_FLIP_DONE |
11262 DERRMR_PIPEC_PRI_FLIP_DONE));
11264 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11265 MI_SRM_LRM_GLOBAL_GTT);
11267 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11268 MI_SRM_LRM_GLOBAL_GTT);
11269 intel_ring_emit_reg(ring, DERRMR);
11270 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11271 if (IS_GEN8(dev)) {
11272 intel_ring_emit(ring, 0);
11273 intel_ring_emit(ring, MI_NOOP);
11277 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11278 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11279 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11280 intel_ring_emit(ring, (MI_NOOP));
11282 intel_mark_page_flip_active(intel_crtc->unpin_work);
11286 static bool use_mmio_flip(struct intel_engine_cs *ring,
11287 struct drm_i915_gem_object *obj)
11290 * This is not being used for older platforms, because
11291 * non-availability of flip done interrupt forces us to use
11292 * CS flips. Older platforms derive flip done using some clever
11293 * tricks involving the flip_pending status bits and vblank irqs.
11294 * So using MMIO flips there would disrupt this mechanism.
11300 if (INTEL_INFO(ring->dev)->gen < 5)
11303 if (i915.use_mmio_flip < 0)
11305 else if (i915.use_mmio_flip > 0)
11307 else if (i915.enable_execlists)
11309 else if (obj->base.dma_buf &&
11310 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11314 return ring != i915_gem_request_get_ring(obj->last_write_req);
11317 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11318 unsigned int rotation,
11319 struct intel_unpin_work *work)
11321 struct drm_device *dev = intel_crtc->base.dev;
11322 struct drm_i915_private *dev_priv = dev->dev_private;
11323 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11324 const enum pipe pipe = intel_crtc->pipe;
11325 u32 ctl, stride, tile_height;
11327 ctl = I915_READ(PLANE_CTL(pipe, 0));
11328 ctl &= ~PLANE_CTL_TILED_MASK;
11329 switch (fb->modifier[0]) {
11330 case DRM_FORMAT_MOD_NONE:
11332 case I915_FORMAT_MOD_X_TILED:
11333 ctl |= PLANE_CTL_TILED_X;
11335 case I915_FORMAT_MOD_Y_TILED:
11336 ctl |= PLANE_CTL_TILED_Y;
11338 case I915_FORMAT_MOD_Yf_TILED:
11339 ctl |= PLANE_CTL_TILED_YF;
11342 MISSING_CASE(fb->modifier[0]);
11346 * The stride is either expressed as a multiple of 64 bytes chunks for
11347 * linear buffers or in number of tiles for tiled buffers.
11349 if (intel_rotation_90_or_270(rotation)) {
11350 /* stride = Surface height in tiles */
11351 tile_height = intel_tile_height(dev, fb->pixel_format,
11352 fb->modifier[0], 0);
11353 stride = DIV_ROUND_UP(fb->height, tile_height);
11355 stride = fb->pitches[0] /
11356 intel_fb_stride_alignment(dev, fb->modifier[0],
11361 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11362 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11364 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11365 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11367 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11368 POSTING_READ(PLANE_SURF(pipe, 0));
11371 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11372 struct intel_unpin_work *work)
11374 struct drm_device *dev = intel_crtc->base.dev;
11375 struct drm_i915_private *dev_priv = dev->dev_private;
11376 struct intel_framebuffer *intel_fb =
11377 to_intel_framebuffer(intel_crtc->base.primary->fb);
11378 struct drm_i915_gem_object *obj = intel_fb->obj;
11379 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11382 dspcntr = I915_READ(reg);
11384 if (obj->tiling_mode != I915_TILING_NONE)
11385 dspcntr |= DISPPLANE_TILED;
11387 dspcntr &= ~DISPPLANE_TILED;
11389 I915_WRITE(reg, dspcntr);
11391 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11392 POSTING_READ(DSPSURF(intel_crtc->plane));
11396 * XXX: This is the temporary way to update the plane registers until we get
11397 * around to using the usual plane update functions for MMIO flips
11399 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11401 struct intel_crtc *crtc = mmio_flip->crtc;
11402 struct intel_unpin_work *work;
11404 spin_lock_irq(&crtc->base.dev->event_lock);
11405 work = crtc->unpin_work;
11406 spin_unlock_irq(&crtc->base.dev->event_lock);
11410 intel_mark_page_flip_active(work);
11412 intel_pipe_update_start(crtc);
11414 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11415 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11417 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11418 ilk_do_mmio_flip(crtc, work);
11420 intel_pipe_update_end(crtc);
11423 static void intel_mmio_flip_work_func(struct work_struct *work)
11425 struct intel_mmio_flip *mmio_flip =
11426 container_of(work, struct intel_mmio_flip, work);
11427 struct intel_framebuffer *intel_fb =
11428 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11429 struct drm_i915_gem_object *obj = intel_fb->obj;
11431 if (mmio_flip->req) {
11432 WARN_ON(__i915_wait_request(mmio_flip->req,
11433 mmio_flip->crtc->reset_counter,
11435 &mmio_flip->i915->rps.mmioflips));
11436 i915_gem_request_unreference__unlocked(mmio_flip->req);
11439 /* For framebuffer backed by dmabuf, wait for fence */
11440 if (obj->base.dma_buf)
11441 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11443 MAX_SCHEDULE_TIMEOUT) < 0);
11445 intel_do_mmio_flip(mmio_flip);
11449 static int intel_queue_mmio_flip(struct drm_device *dev,
11450 struct drm_crtc *crtc,
11451 struct drm_i915_gem_object *obj)
11453 struct intel_mmio_flip *mmio_flip;
11455 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11456 if (mmio_flip == NULL)
11459 mmio_flip->i915 = to_i915(dev);
11460 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11461 mmio_flip->crtc = to_intel_crtc(crtc);
11462 mmio_flip->rotation = crtc->primary->state->rotation;
11464 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11465 schedule_work(&mmio_flip->work);
11470 static int intel_default_queue_flip(struct drm_device *dev,
11471 struct drm_crtc *crtc,
11472 struct drm_framebuffer *fb,
11473 struct drm_i915_gem_object *obj,
11474 struct drm_i915_gem_request *req,
11480 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11481 struct drm_crtc *crtc)
11483 struct drm_i915_private *dev_priv = dev->dev_private;
11484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11485 struct intel_unpin_work *work = intel_crtc->unpin_work;
11488 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11491 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11494 if (!work->enable_stall_check)
11497 if (work->flip_ready_vblank == 0) {
11498 if (work->flip_queued_req &&
11499 !i915_gem_request_completed(work->flip_queued_req, true))
11502 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11505 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11508 /* Potential stall - if we see that the flip has happened,
11509 * assume a missed interrupt. */
11510 if (INTEL_INFO(dev)->gen >= 4)
11511 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11513 addr = I915_READ(DSPADDR(intel_crtc->plane));
11515 /* There is a potential issue here with a false positive after a flip
11516 * to the same address. We could address this by checking for a
11517 * non-incrementing frame counter.
11519 return addr == work->gtt_offset;
11522 void intel_check_page_flip(struct drm_device *dev, int pipe)
11524 struct drm_i915_private *dev_priv = dev->dev_private;
11525 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11527 struct intel_unpin_work *work;
11529 WARN_ON(!in_interrupt());
11534 spin_lock(&dev->event_lock);
11535 work = intel_crtc->unpin_work;
11536 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11537 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11538 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11539 page_flip_completed(intel_crtc);
11542 if (work != NULL &&
11543 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11544 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11545 spin_unlock(&dev->event_lock);
11548 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11549 struct drm_framebuffer *fb,
11550 struct drm_pending_vblank_event *event,
11551 uint32_t page_flip_flags)
11553 struct drm_device *dev = crtc->dev;
11554 struct drm_i915_private *dev_priv = dev->dev_private;
11555 struct drm_framebuffer *old_fb = crtc->primary->fb;
11556 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11558 struct drm_plane *primary = crtc->primary;
11559 enum pipe pipe = intel_crtc->pipe;
11560 struct intel_unpin_work *work;
11561 struct intel_engine_cs *ring;
11563 struct drm_i915_gem_request *request = NULL;
11567 * drm_mode_page_flip_ioctl() should already catch this, but double
11568 * check to be safe. In the future we may enable pageflipping from
11569 * a disabled primary plane.
11571 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11574 /* Can't change pixel format via MI display flips. */
11575 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11579 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11580 * Note that pitch changes could also affect these register.
11582 if (INTEL_INFO(dev)->gen > 3 &&
11583 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11584 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11587 if (i915_terminally_wedged(&dev_priv->gpu_error))
11590 work = kzalloc(sizeof(*work), GFP_KERNEL);
11594 work->event = event;
11596 work->old_fb = old_fb;
11597 INIT_WORK(&work->work, intel_unpin_work_fn);
11599 ret = drm_crtc_vblank_get(crtc);
11603 /* We borrow the event spin lock for protecting unpin_work */
11604 spin_lock_irq(&dev->event_lock);
11605 if (intel_crtc->unpin_work) {
11606 /* Before declaring the flip queue wedged, check if
11607 * the hardware completed the operation behind our backs.
11609 if (__intel_pageflip_stall_check(dev, crtc)) {
11610 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11611 page_flip_completed(intel_crtc);
11613 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11614 spin_unlock_irq(&dev->event_lock);
11616 drm_crtc_vblank_put(crtc);
11621 intel_crtc->unpin_work = work;
11622 spin_unlock_irq(&dev->event_lock);
11624 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11625 flush_workqueue(dev_priv->wq);
11627 /* Reference the objects for the scheduled work. */
11628 drm_framebuffer_reference(work->old_fb);
11629 drm_gem_object_reference(&obj->base);
11631 crtc->primary->fb = fb;
11632 update_state_fb(crtc->primary);
11634 work->pending_flip_obj = obj;
11636 ret = i915_mutex_lock_interruptible(dev);
11640 atomic_inc(&intel_crtc->unpin_work_count);
11641 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11643 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11644 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11646 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11647 ring = &dev_priv->ring[BCS];
11648 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11649 /* vlv: DISPLAY_FLIP fails to change tiling */
11651 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11652 ring = &dev_priv->ring[BCS];
11653 } else if (INTEL_INFO(dev)->gen >= 7) {
11654 ring = i915_gem_request_get_ring(obj->last_write_req);
11655 if (ring == NULL || ring->id != RCS)
11656 ring = &dev_priv->ring[BCS];
11658 ring = &dev_priv->ring[RCS];
11661 mmio_flip = use_mmio_flip(ring, obj);
11663 /* When using CS flips, we want to emit semaphores between rings.
11664 * However, when using mmio flips we will create a task to do the
11665 * synchronisation, so all we want here is to pin the framebuffer
11666 * into the display plane and skip any waits.
11669 ret = i915_gem_object_sync(obj, ring, &request);
11671 goto cleanup_pending;
11674 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11675 crtc->primary->state);
11677 goto cleanup_pending;
11679 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11681 work->gtt_offset += intel_crtc->dspaddr_offset;
11684 ret = intel_queue_mmio_flip(dev, crtc, obj);
11686 goto cleanup_unpin;
11688 i915_gem_request_assign(&work->flip_queued_req,
11689 obj->last_write_req);
11692 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11694 goto cleanup_unpin;
11697 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11700 goto cleanup_unpin;
11702 i915_gem_request_assign(&work->flip_queued_req, request);
11706 i915_add_request_no_flush(request);
11708 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11709 work->enable_stall_check = true;
11711 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11712 to_intel_plane(primary)->frontbuffer_bit);
11713 mutex_unlock(&dev->struct_mutex);
11715 intel_fbc_deactivate(intel_crtc);
11716 intel_frontbuffer_flip_prepare(dev,
11717 to_intel_plane(primary)->frontbuffer_bit);
11719 trace_i915_flip_request(intel_crtc->plane, obj);
11724 intel_unpin_fb_obj(fb, crtc->primary->state);
11727 i915_gem_request_cancel(request);
11728 atomic_dec(&intel_crtc->unpin_work_count);
11729 mutex_unlock(&dev->struct_mutex);
11731 crtc->primary->fb = old_fb;
11732 update_state_fb(crtc->primary);
11734 drm_gem_object_unreference_unlocked(&obj->base);
11735 drm_framebuffer_unreference(work->old_fb);
11737 spin_lock_irq(&dev->event_lock);
11738 intel_crtc->unpin_work = NULL;
11739 spin_unlock_irq(&dev->event_lock);
11741 drm_crtc_vblank_put(crtc);
11746 struct drm_atomic_state *state;
11747 struct drm_plane_state *plane_state;
11750 state = drm_atomic_state_alloc(dev);
11753 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11756 plane_state = drm_atomic_get_plane_state(state, primary);
11757 ret = PTR_ERR_OR_ZERO(plane_state);
11759 drm_atomic_set_fb_for_plane(plane_state, fb);
11761 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11763 ret = drm_atomic_commit(state);
11766 if (ret == -EDEADLK) {
11767 drm_modeset_backoff(state->acquire_ctx);
11768 drm_atomic_state_clear(state);
11773 drm_atomic_state_free(state);
11775 if (ret == 0 && event) {
11776 spin_lock_irq(&dev->event_lock);
11777 drm_send_vblank_event(dev, pipe, event);
11778 spin_unlock_irq(&dev->event_lock);
11786 * intel_wm_need_update - Check whether watermarks need updating
11787 * @plane: drm plane
11788 * @state: new plane state
11790 * Check current plane state versus the new one to determine whether
11791 * watermarks need to be recalculated.
11793 * Returns true or false.
11795 static bool intel_wm_need_update(struct drm_plane *plane,
11796 struct drm_plane_state *state)
11798 struct intel_plane_state *new = to_intel_plane_state(state);
11799 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11801 /* Update watermarks on tiling or size changes. */
11802 if (new->visible != cur->visible)
11805 if (!cur->base.fb || !new->base.fb)
11808 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11809 cur->base.rotation != new->base.rotation ||
11810 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11811 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11812 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11813 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11819 static bool needs_scaling(struct intel_plane_state *state)
11821 int src_w = drm_rect_width(&state->src) >> 16;
11822 int src_h = drm_rect_height(&state->src) >> 16;
11823 int dst_w = drm_rect_width(&state->dst);
11824 int dst_h = drm_rect_height(&state->dst);
11826 return (src_w != dst_w || src_h != dst_h);
11829 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11830 struct drm_plane_state *plane_state)
11832 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11833 struct drm_crtc *crtc = crtc_state->crtc;
11834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11835 struct drm_plane *plane = plane_state->plane;
11836 struct drm_device *dev = crtc->dev;
11837 struct drm_i915_private *dev_priv = dev->dev_private;
11838 struct intel_plane_state *old_plane_state =
11839 to_intel_plane_state(plane->state);
11840 int idx = intel_crtc->base.base.id, ret;
11841 int i = drm_plane_index(plane);
11842 bool mode_changed = needs_modeset(crtc_state);
11843 bool was_crtc_enabled = crtc->state->active;
11844 bool is_crtc_enabled = crtc_state->active;
11845 bool turn_off, turn_on, visible, was_visible;
11846 struct drm_framebuffer *fb = plane_state->fb;
11848 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11849 plane->type != DRM_PLANE_TYPE_CURSOR) {
11850 ret = skl_update_scaler_plane(
11851 to_intel_crtc_state(crtc_state),
11852 to_intel_plane_state(plane_state));
11857 was_visible = old_plane_state->visible;
11858 visible = to_intel_plane_state(plane_state)->visible;
11860 if (!was_crtc_enabled && WARN_ON(was_visible))
11861 was_visible = false;
11863 if (!is_crtc_enabled && WARN_ON(visible))
11866 if (!was_visible && !visible)
11869 turn_off = was_visible && (!visible || mode_changed);
11870 turn_on = visible && (!was_visible || mode_changed);
11872 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11873 plane->base.id, fb ? fb->base.id : -1);
11875 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11876 plane->base.id, was_visible, visible,
11877 turn_off, turn_on, mode_changed);
11879 if (turn_on || turn_off) {
11880 pipe_config->wm_changed = true;
11882 /* must disable cxsr around plane enable/disable */
11883 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11884 if (is_crtc_enabled)
11885 intel_crtc->atomic.wait_vblank = true;
11886 pipe_config->disable_cxsr = true;
11888 } else if (intel_wm_need_update(plane, plane_state)) {
11889 pipe_config->wm_changed = true;
11892 if (visible || was_visible)
11893 intel_crtc->atomic.fb_bits |=
11894 to_intel_plane(plane)->frontbuffer_bit;
11896 switch (plane->type) {
11897 case DRM_PLANE_TYPE_PRIMARY:
11898 intel_crtc->atomic.pre_disable_primary = turn_off;
11899 intel_crtc->atomic.post_enable_primary = turn_on;
11903 * FIXME: Actually if we will still have any other
11904 * plane enabled on the pipe we could let IPS enabled
11905 * still, but for now lets consider that when we make
11906 * primary invisible by setting DSPCNTR to 0 on
11907 * update_primary_plane function IPS needs to be
11910 intel_crtc->atomic.disable_ips = true;
11912 intel_crtc->atomic.disable_fbc = true;
11916 * FBC does not work on some platforms for rotated
11917 * planes, so disable it when rotation is not 0 and
11918 * update it when rotation is set back to 0.
11920 * FIXME: This is redundant with the fbc update done in
11921 * the primary plane enable function except that that
11922 * one is done too late. We eventually need to unify
11927 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11928 dev_priv->fbc.crtc == intel_crtc &&
11929 plane_state->rotation != BIT(DRM_ROTATE_0))
11930 intel_crtc->atomic.disable_fbc = true;
11933 * BDW signals flip done immediately if the plane
11934 * is disabled, even if the plane enable is already
11935 * armed to occur at the next vblank :(
11937 if (turn_on && IS_BROADWELL(dev))
11938 intel_crtc->atomic.wait_vblank = true;
11940 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11942 case DRM_PLANE_TYPE_CURSOR:
11944 case DRM_PLANE_TYPE_OVERLAY:
11946 * WaCxSRDisabledForSpriteScaling:ivb
11948 * cstate->update_wm was already set above, so this flag will
11949 * take effect when we commit and program watermarks.
11951 if (IS_IVYBRIDGE(dev) &&
11952 needs_scaling(to_intel_plane_state(plane_state)) &&
11953 !needs_scaling(old_plane_state)) {
11954 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11955 } else if (turn_off && !mode_changed) {
11956 intel_crtc->atomic.wait_vblank = true;
11957 intel_crtc->atomic.update_sprite_watermarks |=
11966 static bool encoders_cloneable(const struct intel_encoder *a,
11967 const struct intel_encoder *b)
11969 /* masks could be asymmetric, so check both ways */
11970 return a == b || (a->cloneable & (1 << b->type) &&
11971 b->cloneable & (1 << a->type));
11974 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11975 struct intel_crtc *crtc,
11976 struct intel_encoder *encoder)
11978 struct intel_encoder *source_encoder;
11979 struct drm_connector *connector;
11980 struct drm_connector_state *connector_state;
11983 for_each_connector_in_state(state, connector, connector_state, i) {
11984 if (connector_state->crtc != &crtc->base)
11988 to_intel_encoder(connector_state->best_encoder);
11989 if (!encoders_cloneable(encoder, source_encoder))
11996 static bool check_encoder_cloning(struct drm_atomic_state *state,
11997 struct intel_crtc *crtc)
11999 struct intel_encoder *encoder;
12000 struct drm_connector *connector;
12001 struct drm_connector_state *connector_state;
12004 for_each_connector_in_state(state, connector, connector_state, i) {
12005 if (connector_state->crtc != &crtc->base)
12008 encoder = to_intel_encoder(connector_state->best_encoder);
12009 if (!check_single_encoder_cloning(state, crtc, encoder))
12016 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12017 struct drm_crtc_state *crtc_state)
12019 struct drm_device *dev = crtc->dev;
12020 struct drm_i915_private *dev_priv = dev->dev_private;
12021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12022 struct intel_crtc_state *pipe_config =
12023 to_intel_crtc_state(crtc_state);
12024 struct drm_atomic_state *state = crtc_state->state;
12026 bool mode_changed = needs_modeset(crtc_state);
12028 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12029 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12033 if (mode_changed && !crtc_state->active)
12034 pipe_config->wm_changed = true;
12036 if (mode_changed && crtc_state->enable &&
12037 dev_priv->display.crtc_compute_clock &&
12038 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12039 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12046 if (dev_priv->display.compute_pipe_wm) {
12047 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12052 if (INTEL_INFO(dev)->gen >= 9) {
12054 ret = skl_update_scaler_crtc(pipe_config);
12057 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12064 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12065 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12066 .load_lut = intel_crtc_load_lut,
12067 .atomic_begin = intel_begin_crtc_commit,
12068 .atomic_flush = intel_finish_crtc_commit,
12069 .atomic_check = intel_crtc_atomic_check,
12072 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12074 struct intel_connector *connector;
12076 for_each_intel_connector(dev, connector) {
12077 if (connector->base.encoder) {
12078 connector->base.state->best_encoder =
12079 connector->base.encoder;
12080 connector->base.state->crtc =
12081 connector->base.encoder->crtc;
12083 connector->base.state->best_encoder = NULL;
12084 connector->base.state->crtc = NULL;
12090 connected_sink_compute_bpp(struct intel_connector *connector,
12091 struct intel_crtc_state *pipe_config)
12093 int bpp = pipe_config->pipe_bpp;
12095 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12096 connector->base.base.id,
12097 connector->base.name);
12099 /* Don't use an invalid EDID bpc value */
12100 if (connector->base.display_info.bpc &&
12101 connector->base.display_info.bpc * 3 < bpp) {
12102 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12103 bpp, connector->base.display_info.bpc*3);
12104 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12107 /* Clamp bpp to default limit on screens without EDID 1.4 */
12108 if (connector->base.display_info.bpc == 0) {
12109 int type = connector->base.connector_type;
12110 int clamp_bpp = 24;
12112 /* Fall back to 18 bpp when DP sink capability is unknown. */
12113 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12114 type == DRM_MODE_CONNECTOR_eDP)
12117 if (bpp > clamp_bpp) {
12118 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12120 pipe_config->pipe_bpp = clamp_bpp;
12126 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12127 struct intel_crtc_state *pipe_config)
12129 struct drm_device *dev = crtc->base.dev;
12130 struct drm_atomic_state *state;
12131 struct drm_connector *connector;
12132 struct drm_connector_state *connector_state;
12135 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12137 else if (INTEL_INFO(dev)->gen >= 5)
12143 pipe_config->pipe_bpp = bpp;
12145 state = pipe_config->base.state;
12147 /* Clamp display bpp to EDID value */
12148 for_each_connector_in_state(state, connector, connector_state, i) {
12149 if (connector_state->crtc != &crtc->base)
12152 connected_sink_compute_bpp(to_intel_connector(connector),
12159 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12161 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12162 "type: 0x%x flags: 0x%x\n",
12164 mode->crtc_hdisplay, mode->crtc_hsync_start,
12165 mode->crtc_hsync_end, mode->crtc_htotal,
12166 mode->crtc_vdisplay, mode->crtc_vsync_start,
12167 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12170 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12171 struct intel_crtc_state *pipe_config,
12172 const char *context)
12174 struct drm_device *dev = crtc->base.dev;
12175 struct drm_plane *plane;
12176 struct intel_plane *intel_plane;
12177 struct intel_plane_state *state;
12178 struct drm_framebuffer *fb;
12180 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12181 context, pipe_config, pipe_name(crtc->pipe));
12183 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12184 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12185 pipe_config->pipe_bpp, pipe_config->dither);
12186 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12187 pipe_config->has_pch_encoder,
12188 pipe_config->fdi_lanes,
12189 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12190 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12191 pipe_config->fdi_m_n.tu);
12192 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12193 pipe_config->has_dp_encoder,
12194 pipe_config->lane_count,
12195 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12196 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12197 pipe_config->dp_m_n.tu);
12199 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12200 pipe_config->has_dp_encoder,
12201 pipe_config->lane_count,
12202 pipe_config->dp_m2_n2.gmch_m,
12203 pipe_config->dp_m2_n2.gmch_n,
12204 pipe_config->dp_m2_n2.link_m,
12205 pipe_config->dp_m2_n2.link_n,
12206 pipe_config->dp_m2_n2.tu);
12208 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12209 pipe_config->has_audio,
12210 pipe_config->has_infoframe);
12212 DRM_DEBUG_KMS("requested mode:\n");
12213 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12214 DRM_DEBUG_KMS("adjusted mode:\n");
12215 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12216 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12217 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12218 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12219 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12220 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12222 pipe_config->scaler_state.scaler_users,
12223 pipe_config->scaler_state.scaler_id);
12224 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12225 pipe_config->gmch_pfit.control,
12226 pipe_config->gmch_pfit.pgm_ratios,
12227 pipe_config->gmch_pfit.lvds_border_bits);
12228 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12229 pipe_config->pch_pfit.pos,
12230 pipe_config->pch_pfit.size,
12231 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12232 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12233 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12235 if (IS_BROXTON(dev)) {
12236 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12237 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12238 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12239 pipe_config->ddi_pll_sel,
12240 pipe_config->dpll_hw_state.ebb0,
12241 pipe_config->dpll_hw_state.ebb4,
12242 pipe_config->dpll_hw_state.pll0,
12243 pipe_config->dpll_hw_state.pll1,
12244 pipe_config->dpll_hw_state.pll2,
12245 pipe_config->dpll_hw_state.pll3,
12246 pipe_config->dpll_hw_state.pll6,
12247 pipe_config->dpll_hw_state.pll8,
12248 pipe_config->dpll_hw_state.pll9,
12249 pipe_config->dpll_hw_state.pll10,
12250 pipe_config->dpll_hw_state.pcsdw12);
12251 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12252 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12253 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12254 pipe_config->ddi_pll_sel,
12255 pipe_config->dpll_hw_state.ctrl1,
12256 pipe_config->dpll_hw_state.cfgcr1,
12257 pipe_config->dpll_hw_state.cfgcr2);
12258 } else if (HAS_DDI(dev)) {
12259 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12260 pipe_config->ddi_pll_sel,
12261 pipe_config->dpll_hw_state.wrpll,
12262 pipe_config->dpll_hw_state.spll);
12264 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12265 "fp0: 0x%x, fp1: 0x%x\n",
12266 pipe_config->dpll_hw_state.dpll,
12267 pipe_config->dpll_hw_state.dpll_md,
12268 pipe_config->dpll_hw_state.fp0,
12269 pipe_config->dpll_hw_state.fp1);
12272 DRM_DEBUG_KMS("planes on this crtc\n");
12273 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12274 intel_plane = to_intel_plane(plane);
12275 if (intel_plane->pipe != crtc->pipe)
12278 state = to_intel_plane_state(plane->state);
12279 fb = state->base.fb;
12281 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12282 "disabled, scaler_id = %d\n",
12283 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12284 plane->base.id, intel_plane->pipe,
12285 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12286 drm_plane_index(plane), state->scaler_id);
12290 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12291 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12292 plane->base.id, intel_plane->pipe,
12293 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12294 drm_plane_index(plane));
12295 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12296 fb->base.id, fb->width, fb->height, fb->pixel_format);
12297 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12299 state->src.x1 >> 16, state->src.y1 >> 16,
12300 drm_rect_width(&state->src) >> 16,
12301 drm_rect_height(&state->src) >> 16,
12302 state->dst.x1, state->dst.y1,
12303 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12307 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12309 struct drm_device *dev = state->dev;
12310 struct drm_connector *connector;
12311 unsigned int used_ports = 0;
12314 * Walk the connector list instead of the encoder
12315 * list to detect the problem on ddi platforms
12316 * where there's just one encoder per digital port.
12318 drm_for_each_connector(connector, dev) {
12319 struct drm_connector_state *connector_state;
12320 struct intel_encoder *encoder;
12322 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12323 if (!connector_state)
12324 connector_state = connector->state;
12326 if (!connector_state->best_encoder)
12329 encoder = to_intel_encoder(connector_state->best_encoder);
12331 WARN_ON(!connector_state->crtc);
12333 switch (encoder->type) {
12334 unsigned int port_mask;
12335 case INTEL_OUTPUT_UNKNOWN:
12336 if (WARN_ON(!HAS_DDI(dev)))
12338 case INTEL_OUTPUT_DISPLAYPORT:
12339 case INTEL_OUTPUT_HDMI:
12340 case INTEL_OUTPUT_EDP:
12341 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12343 /* the same port mustn't appear more than once */
12344 if (used_ports & port_mask)
12347 used_ports |= port_mask;
12357 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12359 struct drm_crtc_state tmp_state;
12360 struct intel_crtc_scaler_state scaler_state;
12361 struct intel_dpll_hw_state dpll_hw_state;
12362 enum intel_dpll_id shared_dpll;
12363 uint32_t ddi_pll_sel;
12366 /* FIXME: before the switch to atomic started, a new pipe_config was
12367 * kzalloc'd. Code that depends on any field being zero should be
12368 * fixed, so that the crtc_state can be safely duplicated. For now,
12369 * only fields that are know to not cause problems are preserved. */
12371 tmp_state = crtc_state->base;
12372 scaler_state = crtc_state->scaler_state;
12373 shared_dpll = crtc_state->shared_dpll;
12374 dpll_hw_state = crtc_state->dpll_hw_state;
12375 ddi_pll_sel = crtc_state->ddi_pll_sel;
12376 force_thru = crtc_state->pch_pfit.force_thru;
12378 memset(crtc_state, 0, sizeof *crtc_state);
12380 crtc_state->base = tmp_state;
12381 crtc_state->scaler_state = scaler_state;
12382 crtc_state->shared_dpll = shared_dpll;
12383 crtc_state->dpll_hw_state = dpll_hw_state;
12384 crtc_state->ddi_pll_sel = ddi_pll_sel;
12385 crtc_state->pch_pfit.force_thru = force_thru;
12389 intel_modeset_pipe_config(struct drm_crtc *crtc,
12390 struct intel_crtc_state *pipe_config)
12392 struct drm_atomic_state *state = pipe_config->base.state;
12393 struct intel_encoder *encoder;
12394 struct drm_connector *connector;
12395 struct drm_connector_state *connector_state;
12396 int base_bpp, ret = -EINVAL;
12400 clear_intel_crtc_state(pipe_config);
12402 pipe_config->cpu_transcoder =
12403 (enum transcoder) to_intel_crtc(crtc)->pipe;
12406 * Sanitize sync polarity flags based on requested ones. If neither
12407 * positive or negative polarity is requested, treat this as meaning
12408 * negative polarity.
12410 if (!(pipe_config->base.adjusted_mode.flags &
12411 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12412 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12414 if (!(pipe_config->base.adjusted_mode.flags &
12415 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12416 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12418 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12424 * Determine the real pipe dimensions. Note that stereo modes can
12425 * increase the actual pipe size due to the frame doubling and
12426 * insertion of additional space for blanks between the frame. This
12427 * is stored in the crtc timings. We use the requested mode to do this
12428 * computation to clearly distinguish it from the adjusted mode, which
12429 * can be changed by the connectors in the below retry loop.
12431 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12432 &pipe_config->pipe_src_w,
12433 &pipe_config->pipe_src_h);
12436 /* Ensure the port clock defaults are reset when retrying. */
12437 pipe_config->port_clock = 0;
12438 pipe_config->pixel_multiplier = 1;
12440 /* Fill in default crtc timings, allow encoders to overwrite them. */
12441 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12442 CRTC_STEREO_DOUBLE);
12444 /* Pass our mode to the connectors and the CRTC to give them a chance to
12445 * adjust it according to limitations or connector properties, and also
12446 * a chance to reject the mode entirely.
12448 for_each_connector_in_state(state, connector, connector_state, i) {
12449 if (connector_state->crtc != crtc)
12452 encoder = to_intel_encoder(connector_state->best_encoder);
12454 if (!(encoder->compute_config(encoder, pipe_config))) {
12455 DRM_DEBUG_KMS("Encoder config failure\n");
12460 /* Set default port clock if not overwritten by the encoder. Needs to be
12461 * done afterwards in case the encoder adjusts the mode. */
12462 if (!pipe_config->port_clock)
12463 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12464 * pipe_config->pixel_multiplier;
12466 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12468 DRM_DEBUG_KMS("CRTC fixup failed\n");
12472 if (ret == RETRY) {
12473 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12478 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12480 goto encoder_retry;
12483 /* Dithering seems to not pass-through bits correctly when it should, so
12484 * only enable it on 6bpc panels. */
12485 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12486 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12487 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12494 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12496 struct drm_crtc *crtc;
12497 struct drm_crtc_state *crtc_state;
12500 /* Double check state. */
12501 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12502 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12504 /* Update hwmode for vblank functions */
12505 if (crtc->state->active)
12506 crtc->hwmode = crtc->state->adjusted_mode;
12508 crtc->hwmode.crtc_clock = 0;
12511 * Update legacy state to satisfy fbc code. This can
12512 * be removed when fbc uses the atomic state.
12514 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12515 struct drm_plane_state *plane_state = crtc->primary->state;
12517 crtc->primary->fb = plane_state->fb;
12518 crtc->x = plane_state->src_x >> 16;
12519 crtc->y = plane_state->src_y >> 16;
12524 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12528 if (clock1 == clock2)
12531 if (!clock1 || !clock2)
12534 diff = abs(clock1 - clock2);
12536 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12542 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12543 list_for_each_entry((intel_crtc), \
12544 &(dev)->mode_config.crtc_list, \
12546 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12549 intel_compare_m_n(unsigned int m, unsigned int n,
12550 unsigned int m2, unsigned int n2,
12553 if (m == m2 && n == n2)
12556 if (exact || !m || !n || !m2 || !n2)
12559 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12566 } else if (m < m2) {
12573 return m == m2 && n == n2;
12577 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12578 struct intel_link_m_n *m2_n2,
12581 if (m_n->tu == m2_n2->tu &&
12582 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12583 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12584 intel_compare_m_n(m_n->link_m, m_n->link_n,
12585 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12596 intel_pipe_config_compare(struct drm_device *dev,
12597 struct intel_crtc_state *current_config,
12598 struct intel_crtc_state *pipe_config,
12603 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12606 DRM_ERROR(fmt, ##__VA_ARGS__); \
12608 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12611 #define PIPE_CONF_CHECK_X(name) \
12612 if (current_config->name != pipe_config->name) { \
12613 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12614 "(expected 0x%08x, found 0x%08x)\n", \
12615 current_config->name, \
12616 pipe_config->name); \
12620 #define PIPE_CONF_CHECK_I(name) \
12621 if (current_config->name != pipe_config->name) { \
12622 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12623 "(expected %i, found %i)\n", \
12624 current_config->name, \
12625 pipe_config->name); \
12629 #define PIPE_CONF_CHECK_M_N(name) \
12630 if (!intel_compare_link_m_n(¤t_config->name, \
12631 &pipe_config->name,\
12633 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12634 "(expected tu %i gmch %i/%i link %i/%i, " \
12635 "found tu %i, gmch %i/%i link %i/%i)\n", \
12636 current_config->name.tu, \
12637 current_config->name.gmch_m, \
12638 current_config->name.gmch_n, \
12639 current_config->name.link_m, \
12640 current_config->name.link_n, \
12641 pipe_config->name.tu, \
12642 pipe_config->name.gmch_m, \
12643 pipe_config->name.gmch_n, \
12644 pipe_config->name.link_m, \
12645 pipe_config->name.link_n); \
12649 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12650 if (!intel_compare_link_m_n(¤t_config->name, \
12651 &pipe_config->name, adjust) && \
12652 !intel_compare_link_m_n(¤t_config->alt_name, \
12653 &pipe_config->name, adjust)) { \
12654 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12655 "(expected tu %i gmch %i/%i link %i/%i, " \
12656 "or tu %i gmch %i/%i link %i/%i, " \
12657 "found tu %i, gmch %i/%i link %i/%i)\n", \
12658 current_config->name.tu, \
12659 current_config->name.gmch_m, \
12660 current_config->name.gmch_n, \
12661 current_config->name.link_m, \
12662 current_config->name.link_n, \
12663 current_config->alt_name.tu, \
12664 current_config->alt_name.gmch_m, \
12665 current_config->alt_name.gmch_n, \
12666 current_config->alt_name.link_m, \
12667 current_config->alt_name.link_n, \
12668 pipe_config->name.tu, \
12669 pipe_config->name.gmch_m, \
12670 pipe_config->name.gmch_n, \
12671 pipe_config->name.link_m, \
12672 pipe_config->name.link_n); \
12676 /* This is required for BDW+ where there is only one set of registers for
12677 * switching between high and low RR.
12678 * This macro can be used whenever a comparison has to be made between one
12679 * hw state and multiple sw state variables.
12681 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12682 if ((current_config->name != pipe_config->name) && \
12683 (current_config->alt_name != pipe_config->name)) { \
12684 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12685 "(expected %i or %i, found %i)\n", \
12686 current_config->name, \
12687 current_config->alt_name, \
12688 pipe_config->name); \
12692 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12693 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12694 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12695 "(expected %i, found %i)\n", \
12696 current_config->name & (mask), \
12697 pipe_config->name & (mask)); \
12701 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12702 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12703 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12704 "(expected %i, found %i)\n", \
12705 current_config->name, \
12706 pipe_config->name); \
12710 #define PIPE_CONF_QUIRK(quirk) \
12711 ((current_config->quirks | pipe_config->quirks) & (quirk))
12713 PIPE_CONF_CHECK_I(cpu_transcoder);
12715 PIPE_CONF_CHECK_I(has_pch_encoder);
12716 PIPE_CONF_CHECK_I(fdi_lanes);
12717 PIPE_CONF_CHECK_M_N(fdi_m_n);
12719 PIPE_CONF_CHECK_I(has_dp_encoder);
12720 PIPE_CONF_CHECK_I(lane_count);
12722 if (INTEL_INFO(dev)->gen < 8) {
12723 PIPE_CONF_CHECK_M_N(dp_m_n);
12725 if (current_config->has_drrs)
12726 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12728 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12730 PIPE_CONF_CHECK_I(has_dsi_encoder);
12732 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12733 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12734 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12735 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12736 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12737 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12739 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12740 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12741 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12742 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12743 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12744 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12746 PIPE_CONF_CHECK_I(pixel_multiplier);
12747 PIPE_CONF_CHECK_I(has_hdmi_sink);
12748 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12749 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12750 PIPE_CONF_CHECK_I(limited_color_range);
12751 PIPE_CONF_CHECK_I(has_infoframe);
12753 PIPE_CONF_CHECK_I(has_audio);
12755 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12756 DRM_MODE_FLAG_INTERLACE);
12758 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12759 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12760 DRM_MODE_FLAG_PHSYNC);
12761 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12762 DRM_MODE_FLAG_NHSYNC);
12763 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12764 DRM_MODE_FLAG_PVSYNC);
12765 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12766 DRM_MODE_FLAG_NVSYNC);
12769 PIPE_CONF_CHECK_X(gmch_pfit.control);
12770 /* pfit ratios are autocomputed by the hw on gen4+ */
12771 if (INTEL_INFO(dev)->gen < 4)
12772 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12773 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12776 PIPE_CONF_CHECK_I(pipe_src_w);
12777 PIPE_CONF_CHECK_I(pipe_src_h);
12779 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12780 if (current_config->pch_pfit.enabled) {
12781 PIPE_CONF_CHECK_X(pch_pfit.pos);
12782 PIPE_CONF_CHECK_X(pch_pfit.size);
12785 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12788 /* BDW+ don't expose a synchronous way to read the state */
12789 if (IS_HASWELL(dev))
12790 PIPE_CONF_CHECK_I(ips_enabled);
12792 PIPE_CONF_CHECK_I(double_wide);
12794 PIPE_CONF_CHECK_X(ddi_pll_sel);
12796 PIPE_CONF_CHECK_I(shared_dpll);
12797 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12798 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12799 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12800 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12801 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12802 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12803 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12804 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12805 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12807 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12808 PIPE_CONF_CHECK_I(pipe_bpp);
12810 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12811 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12813 #undef PIPE_CONF_CHECK_X
12814 #undef PIPE_CONF_CHECK_I
12815 #undef PIPE_CONF_CHECK_I_ALT
12816 #undef PIPE_CONF_CHECK_FLAGS
12817 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12818 #undef PIPE_CONF_QUIRK
12819 #undef INTEL_ERR_OR_DBG_KMS
12824 static void check_wm_state(struct drm_device *dev)
12826 struct drm_i915_private *dev_priv = dev->dev_private;
12827 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12828 struct intel_crtc *intel_crtc;
12831 if (INTEL_INFO(dev)->gen < 9)
12834 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12835 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12837 for_each_intel_crtc(dev, intel_crtc) {
12838 struct skl_ddb_entry *hw_entry, *sw_entry;
12839 const enum pipe pipe = intel_crtc->pipe;
12841 if (!intel_crtc->active)
12845 for_each_plane(dev_priv, pipe, plane) {
12846 hw_entry = &hw_ddb.plane[pipe][plane];
12847 sw_entry = &sw_ddb->plane[pipe][plane];
12849 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12852 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12853 "(expected (%u,%u), found (%u,%u))\n",
12854 pipe_name(pipe), plane + 1,
12855 sw_entry->start, sw_entry->end,
12856 hw_entry->start, hw_entry->end);
12860 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12861 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12863 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12866 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12867 "(expected (%u,%u), found (%u,%u))\n",
12869 sw_entry->start, sw_entry->end,
12870 hw_entry->start, hw_entry->end);
12875 check_connector_state(struct drm_device *dev,
12876 struct drm_atomic_state *old_state)
12878 struct drm_connector_state *old_conn_state;
12879 struct drm_connector *connector;
12882 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12883 struct drm_encoder *encoder = connector->encoder;
12884 struct drm_connector_state *state = connector->state;
12886 /* This also checks the encoder/connector hw state with the
12887 * ->get_hw_state callbacks. */
12888 intel_connector_check_state(to_intel_connector(connector));
12890 I915_STATE_WARN(state->best_encoder != encoder,
12891 "connector's atomic encoder doesn't match legacy encoder\n");
12896 check_encoder_state(struct drm_device *dev)
12898 struct intel_encoder *encoder;
12899 struct intel_connector *connector;
12901 for_each_intel_encoder(dev, encoder) {
12902 bool enabled = false;
12905 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12906 encoder->base.base.id,
12907 encoder->base.name);
12909 for_each_intel_connector(dev, connector) {
12910 if (connector->base.state->best_encoder != &encoder->base)
12914 I915_STATE_WARN(connector->base.state->crtc !=
12915 encoder->base.crtc,
12916 "connector's crtc doesn't match encoder crtc\n");
12919 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12920 "encoder's enabled state mismatch "
12921 "(expected %i, found %i)\n",
12922 !!encoder->base.crtc, enabled);
12924 if (!encoder->base.crtc) {
12927 active = encoder->get_hw_state(encoder, &pipe);
12928 I915_STATE_WARN(active,
12929 "encoder detached but still enabled on pipe %c.\n",
12936 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12938 struct drm_i915_private *dev_priv = dev->dev_private;
12939 struct intel_encoder *encoder;
12940 struct drm_crtc_state *old_crtc_state;
12941 struct drm_crtc *crtc;
12944 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12946 struct intel_crtc_state *pipe_config, *sw_config;
12949 if (!needs_modeset(crtc->state) &&
12950 !to_intel_crtc_state(crtc->state)->update_pipe)
12953 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12954 pipe_config = to_intel_crtc_state(old_crtc_state);
12955 memset(pipe_config, 0, sizeof(*pipe_config));
12956 pipe_config->base.crtc = crtc;
12957 pipe_config->base.state = old_state;
12959 DRM_DEBUG_KMS("[CRTC:%d]\n",
12962 active = dev_priv->display.get_pipe_config(intel_crtc,
12965 /* hw state is inconsistent with the pipe quirk */
12966 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12967 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12968 active = crtc->state->active;
12970 I915_STATE_WARN(crtc->state->active != active,
12971 "crtc active state doesn't match with hw state "
12972 "(expected %i, found %i)\n", crtc->state->active, active);
12974 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12975 "transitional active state does not match atomic hw state "
12976 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12978 for_each_encoder_on_crtc(dev, crtc, encoder) {
12981 active = encoder->get_hw_state(encoder, &pipe);
12982 I915_STATE_WARN(active != crtc->state->active,
12983 "[ENCODER:%i] active %i with crtc active %i\n",
12984 encoder->base.base.id, active, crtc->state->active);
12986 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12987 "Encoder connected to wrong pipe %c\n",
12991 encoder->get_config(encoder, pipe_config);
12994 if (!crtc->state->active)
12997 sw_config = to_intel_crtc_state(crtc->state);
12998 if (!intel_pipe_config_compare(dev, sw_config,
12999 pipe_config, false)) {
13000 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13001 intel_dump_pipe_config(intel_crtc, pipe_config,
13003 intel_dump_pipe_config(intel_crtc, sw_config,
13010 check_shared_dpll_state(struct drm_device *dev)
13012 struct drm_i915_private *dev_priv = dev->dev_private;
13013 struct intel_crtc *crtc;
13014 struct intel_dpll_hw_state dpll_hw_state;
13017 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13018 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13019 int enabled_crtcs = 0, active_crtcs = 0;
13022 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13024 DRM_DEBUG_KMS("%s\n", pll->name);
13026 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13028 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13029 "more active pll users than references: %i vs %i\n",
13030 pll->active, hweight32(pll->config.crtc_mask));
13031 I915_STATE_WARN(pll->active && !pll->on,
13032 "pll in active use but not on in sw tracking\n");
13033 I915_STATE_WARN(pll->on && !pll->active,
13034 "pll in on but not on in use in sw tracking\n");
13035 I915_STATE_WARN(pll->on != active,
13036 "pll on state mismatch (expected %i, found %i)\n",
13039 for_each_intel_crtc(dev, crtc) {
13040 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13042 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13045 I915_STATE_WARN(pll->active != active_crtcs,
13046 "pll active crtcs mismatch (expected %i, found %i)\n",
13047 pll->active, active_crtcs);
13048 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13049 "pll enabled crtcs mismatch (expected %i, found %i)\n",
13050 hweight32(pll->config.crtc_mask), enabled_crtcs);
13052 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13053 sizeof(dpll_hw_state)),
13054 "pll hw state mismatch\n");
13059 intel_modeset_check_state(struct drm_device *dev,
13060 struct drm_atomic_state *old_state)
13062 check_wm_state(dev);
13063 check_connector_state(dev, old_state);
13064 check_encoder_state(dev);
13065 check_crtc_state(dev, old_state);
13066 check_shared_dpll_state(dev);
13069 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13073 * FDI already provided one idea for the dotclock.
13074 * Yell if the encoder disagrees.
13076 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13077 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13078 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13081 static void update_scanline_offset(struct intel_crtc *crtc)
13083 struct drm_device *dev = crtc->base.dev;
13086 * The scanline counter increments at the leading edge of hsync.
13088 * On most platforms it starts counting from vtotal-1 on the
13089 * first active line. That means the scanline counter value is
13090 * always one less than what we would expect. Ie. just after
13091 * start of vblank, which also occurs at start of hsync (on the
13092 * last active line), the scanline counter will read vblank_start-1.
13094 * On gen2 the scanline counter starts counting from 1 instead
13095 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13096 * to keep the value positive), instead of adding one.
13098 * On HSW+ the behaviour of the scanline counter depends on the output
13099 * type. For DP ports it behaves like most other platforms, but on HDMI
13100 * there's an extra 1 line difference. So we need to add two instead of
13101 * one to the value.
13103 if (IS_GEN2(dev)) {
13104 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13107 vtotal = adjusted_mode->crtc_vtotal;
13108 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13111 crtc->scanline_offset = vtotal - 1;
13112 } else if (HAS_DDI(dev) &&
13113 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13114 crtc->scanline_offset = 2;
13116 crtc->scanline_offset = 1;
13119 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13121 struct drm_device *dev = state->dev;
13122 struct drm_i915_private *dev_priv = to_i915(dev);
13123 struct intel_shared_dpll_config *shared_dpll = NULL;
13124 struct intel_crtc *intel_crtc;
13125 struct intel_crtc_state *intel_crtc_state;
13126 struct drm_crtc *crtc;
13127 struct drm_crtc_state *crtc_state;
13130 if (!dev_priv->display.crtc_compute_clock)
13133 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13136 intel_crtc = to_intel_crtc(crtc);
13137 intel_crtc_state = to_intel_crtc_state(crtc_state);
13138 dpll = intel_crtc_state->shared_dpll;
13140 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13143 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13146 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13148 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13153 * This implements the workaround described in the "notes" section of the mode
13154 * set sequence documentation. When going from no pipes or single pipe to
13155 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13156 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13158 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13160 struct drm_crtc_state *crtc_state;
13161 struct intel_crtc *intel_crtc;
13162 struct drm_crtc *crtc;
13163 struct intel_crtc_state *first_crtc_state = NULL;
13164 struct intel_crtc_state *other_crtc_state = NULL;
13165 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13168 /* look at all crtc's that are going to be enabled in during modeset */
13169 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13170 intel_crtc = to_intel_crtc(crtc);
13172 if (!crtc_state->active || !needs_modeset(crtc_state))
13175 if (first_crtc_state) {
13176 other_crtc_state = to_intel_crtc_state(crtc_state);
13179 first_crtc_state = to_intel_crtc_state(crtc_state);
13180 first_pipe = intel_crtc->pipe;
13184 /* No workaround needed? */
13185 if (!first_crtc_state)
13188 /* w/a possibly needed, check how many crtc's are already enabled. */
13189 for_each_intel_crtc(state->dev, intel_crtc) {
13190 struct intel_crtc_state *pipe_config;
13192 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13193 if (IS_ERR(pipe_config))
13194 return PTR_ERR(pipe_config);
13196 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13198 if (!pipe_config->base.active ||
13199 needs_modeset(&pipe_config->base))
13202 /* 2 or more enabled crtcs means no need for w/a */
13203 if (enabled_pipe != INVALID_PIPE)
13206 enabled_pipe = intel_crtc->pipe;
13209 if (enabled_pipe != INVALID_PIPE)
13210 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13211 else if (other_crtc_state)
13212 other_crtc_state->hsw_workaround_pipe = first_pipe;
13217 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13219 struct drm_crtc *crtc;
13220 struct drm_crtc_state *crtc_state;
13223 /* add all active pipes to the state */
13224 for_each_crtc(state->dev, crtc) {
13225 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13226 if (IS_ERR(crtc_state))
13227 return PTR_ERR(crtc_state);
13229 if (!crtc_state->active || needs_modeset(crtc_state))
13232 crtc_state->mode_changed = true;
13234 ret = drm_atomic_add_affected_connectors(state, crtc);
13238 ret = drm_atomic_add_affected_planes(state, crtc);
13246 static int intel_modeset_checks(struct drm_atomic_state *state)
13248 struct drm_device *dev = state->dev;
13249 struct drm_i915_private *dev_priv = dev->dev_private;
13252 if (!check_digital_port_conflicts(state)) {
13253 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13258 * See if the config requires any additional preparation, e.g.
13259 * to adjust global state with pipes off. We need to do this
13260 * here so we can get the modeset_pipe updated config for the new
13261 * mode set on this crtc. For other crtcs we need to use the
13262 * adjusted_mode bits in the crtc directly.
13264 if (dev_priv->display.modeset_calc_cdclk) {
13265 unsigned int cdclk;
13267 ret = dev_priv->display.modeset_calc_cdclk(state);
13269 cdclk = to_intel_atomic_state(state)->cdclk;
13270 if (!ret && cdclk != dev_priv->cdclk_freq)
13271 ret = intel_modeset_all_pipes(state);
13276 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13278 intel_modeset_clear_plls(state);
13280 if (IS_HASWELL(dev))
13281 return haswell_mode_set_planes_workaround(state);
13287 * Handle calculation of various watermark data at the end of the atomic check
13288 * phase. The code here should be run after the per-crtc and per-plane 'check'
13289 * handlers to ensure that all derived state has been updated.
13291 static void calc_watermark_data(struct drm_atomic_state *state)
13293 struct drm_device *dev = state->dev;
13294 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13295 struct drm_crtc *crtc;
13296 struct drm_crtc_state *cstate;
13297 struct drm_plane *plane;
13298 struct drm_plane_state *pstate;
13301 * Calculate watermark configuration details now that derived
13302 * plane/crtc state is all properly updated.
13304 drm_for_each_crtc(crtc, dev) {
13305 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13308 if (cstate->active)
13309 intel_state->wm_config.num_pipes_active++;
13311 drm_for_each_legacy_plane(plane, dev) {
13312 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13315 if (!to_intel_plane_state(pstate)->visible)
13318 intel_state->wm_config.sprites_enabled = true;
13319 if (pstate->crtc_w != pstate->src_w >> 16 ||
13320 pstate->crtc_h != pstate->src_h >> 16)
13321 intel_state->wm_config.sprites_scaled = true;
13326 * intel_atomic_check - validate state object
13328 * @state: state to validate
13330 static int intel_atomic_check(struct drm_device *dev,
13331 struct drm_atomic_state *state)
13333 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13334 struct drm_crtc *crtc;
13335 struct drm_crtc_state *crtc_state;
13337 bool any_ms = false;
13339 ret = drm_atomic_helper_check_modeset(dev, state);
13343 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13344 struct intel_crtc_state *pipe_config =
13345 to_intel_crtc_state(crtc_state);
13347 memset(&to_intel_crtc(crtc)->atomic, 0,
13348 sizeof(struct intel_crtc_atomic_commit));
13350 /* Catch I915_MODE_FLAG_INHERITED */
13351 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13352 crtc_state->mode_changed = true;
13354 if (!crtc_state->enable) {
13355 if (needs_modeset(crtc_state))
13360 if (!needs_modeset(crtc_state))
13363 /* FIXME: For only active_changed we shouldn't need to do any
13364 * state recomputation at all. */
13366 ret = drm_atomic_add_affected_connectors(state, crtc);
13370 ret = intel_modeset_pipe_config(crtc, pipe_config);
13374 if (i915.fastboot &&
13375 intel_pipe_config_compare(state->dev,
13376 to_intel_crtc_state(crtc->state),
13377 pipe_config, true)) {
13378 crtc_state->mode_changed = false;
13379 to_intel_crtc_state(crtc_state)->update_pipe = true;
13382 if (needs_modeset(crtc_state)) {
13385 ret = drm_atomic_add_affected_planes(state, crtc);
13390 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13391 needs_modeset(crtc_state) ?
13392 "[modeset]" : "[fastset]");
13396 ret = intel_modeset_checks(state);
13401 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13403 ret = drm_atomic_helper_check_planes(state->dev, state);
13407 calc_watermark_data(state);
13412 static int intel_atomic_prepare_commit(struct drm_device *dev,
13413 struct drm_atomic_state *state,
13416 struct drm_i915_private *dev_priv = dev->dev_private;
13417 struct drm_plane_state *plane_state;
13418 struct drm_crtc_state *crtc_state;
13419 struct drm_plane *plane;
13420 struct drm_crtc *crtc;
13424 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13428 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13429 ret = intel_crtc_wait_for_pending_flips(crtc);
13433 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13434 flush_workqueue(dev_priv->wq);
13437 ret = mutex_lock_interruptible(&dev->struct_mutex);
13441 ret = drm_atomic_helper_prepare_planes(dev, state);
13442 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13445 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13446 mutex_unlock(&dev->struct_mutex);
13448 for_each_plane_in_state(state, plane, plane_state, i) {
13449 struct intel_plane_state *intel_plane_state =
13450 to_intel_plane_state(plane_state);
13452 if (!intel_plane_state->wait_req)
13455 ret = __i915_wait_request(intel_plane_state->wait_req,
13456 reset_counter, true,
13459 /* Swallow -EIO errors to allow updates during hw lockup. */
13470 mutex_lock(&dev->struct_mutex);
13471 drm_atomic_helper_cleanup_planes(dev, state);
13474 mutex_unlock(&dev->struct_mutex);
13479 * intel_atomic_commit - commit validated state object
13481 * @state: the top-level driver state object
13482 * @async: asynchronous commit
13484 * This function commits a top-level state object that has been validated
13485 * with drm_atomic_helper_check().
13487 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13488 * we can only handle plane-related operations and do not yet support
13489 * asynchronous commit.
13492 * Zero for success or -errno.
13494 static int intel_atomic_commit(struct drm_device *dev,
13495 struct drm_atomic_state *state,
13498 struct drm_i915_private *dev_priv = dev->dev_private;
13499 struct drm_crtc_state *crtc_state;
13500 struct drm_crtc *crtc;
13503 bool any_ms = false;
13505 ret = intel_atomic_prepare_commit(dev, state, async);
13507 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13511 drm_atomic_helper_swap_state(dev, state);
13512 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13514 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13517 if (!needs_modeset(crtc->state))
13521 intel_pre_plane_update(intel_crtc);
13523 if (crtc_state->active) {
13524 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13525 dev_priv->display.crtc_disable(crtc);
13526 intel_crtc->active = false;
13527 intel_disable_shared_dpll(intel_crtc);
13530 * Underruns don't always raise
13531 * interrupts, so check manually.
13533 intel_check_cpu_fifo_underruns(dev_priv);
13534 intel_check_pch_fifo_underruns(dev_priv);
13536 if (!crtc->state->active)
13537 intel_update_watermarks(crtc);
13541 /* Only after disabling all output pipelines that will be changed can we
13542 * update the the output configuration. */
13543 intel_modeset_update_crtc_state(state);
13546 intel_shared_dpll_commit(state);
13548 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13549 modeset_update_crtc_power_domains(state);
13552 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13553 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13555 bool modeset = needs_modeset(crtc->state);
13556 bool update_pipe = !modeset &&
13557 to_intel_crtc_state(crtc->state)->update_pipe;
13558 unsigned long put_domains = 0;
13561 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13563 if (modeset && crtc->state->active) {
13564 update_scanline_offset(to_intel_crtc(crtc));
13565 dev_priv->display.crtc_enable(crtc);
13569 put_domains = modeset_get_crtc_power_domains(crtc);
13571 /* make sure intel_modeset_check_state runs */
13576 intel_pre_plane_update(intel_crtc);
13578 if (crtc->state->active &&
13579 (crtc->state->planes_changed || update_pipe))
13580 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13583 modeset_put_power_domains(dev_priv, put_domains);
13585 intel_post_plane_update(intel_crtc);
13588 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13591 /* FIXME: add subpixel order */
13593 drm_atomic_helper_wait_for_vblanks(dev, state);
13595 mutex_lock(&dev->struct_mutex);
13596 drm_atomic_helper_cleanup_planes(dev, state);
13597 mutex_unlock(&dev->struct_mutex);
13600 intel_modeset_check_state(dev, state);
13602 drm_atomic_state_free(state);
13607 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13609 struct drm_device *dev = crtc->dev;
13610 struct drm_atomic_state *state;
13611 struct drm_crtc_state *crtc_state;
13614 state = drm_atomic_state_alloc(dev);
13616 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13621 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13624 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13625 ret = PTR_ERR_OR_ZERO(crtc_state);
13627 if (!crtc_state->active)
13630 crtc_state->mode_changed = true;
13631 ret = drm_atomic_commit(state);
13634 if (ret == -EDEADLK) {
13635 drm_atomic_state_clear(state);
13636 drm_modeset_backoff(state->acquire_ctx);
13642 drm_atomic_state_free(state);
13645 #undef for_each_intel_crtc_masked
13647 static const struct drm_crtc_funcs intel_crtc_funcs = {
13648 .gamma_set = intel_crtc_gamma_set,
13649 .set_config = drm_atomic_helper_set_config,
13650 .destroy = intel_crtc_destroy,
13651 .page_flip = intel_crtc_page_flip,
13652 .atomic_duplicate_state = intel_crtc_duplicate_state,
13653 .atomic_destroy_state = intel_crtc_destroy_state,
13656 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13657 struct intel_shared_dpll *pll,
13658 struct intel_dpll_hw_state *hw_state)
13662 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
13665 val = I915_READ(PCH_DPLL(pll->id));
13666 hw_state->dpll = val;
13667 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13668 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13670 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
13672 return val & DPLL_VCO_ENABLE;
13675 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13676 struct intel_shared_dpll *pll)
13678 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13679 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13682 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13683 struct intel_shared_dpll *pll)
13685 /* PCH refclock must be enabled first */
13686 ibx_assert_pch_refclk_enabled(dev_priv);
13688 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13690 /* Wait for the clocks to stabilize. */
13691 POSTING_READ(PCH_DPLL(pll->id));
13694 /* The pixel multiplier can only be updated once the
13695 * DPLL is enabled and the clocks are stable.
13697 * So write it again.
13699 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13700 POSTING_READ(PCH_DPLL(pll->id));
13704 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13705 struct intel_shared_dpll *pll)
13707 struct drm_device *dev = dev_priv->dev;
13708 struct intel_crtc *crtc;
13710 /* Make sure no transcoder isn't still depending on us. */
13711 for_each_intel_crtc(dev, crtc) {
13712 if (intel_crtc_to_shared_dpll(crtc) == pll)
13713 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13716 I915_WRITE(PCH_DPLL(pll->id), 0);
13717 POSTING_READ(PCH_DPLL(pll->id));
13721 static char *ibx_pch_dpll_names[] = {
13726 static void ibx_pch_dpll_init(struct drm_device *dev)
13728 struct drm_i915_private *dev_priv = dev->dev_private;
13731 dev_priv->num_shared_dpll = 2;
13733 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13734 dev_priv->shared_dplls[i].id = i;
13735 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13736 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13737 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13738 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13739 dev_priv->shared_dplls[i].get_hw_state =
13740 ibx_pch_dpll_get_hw_state;
13744 static void intel_shared_dpll_init(struct drm_device *dev)
13746 struct drm_i915_private *dev_priv = dev->dev_private;
13749 intel_ddi_pll_init(dev);
13750 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13751 ibx_pch_dpll_init(dev);
13753 dev_priv->num_shared_dpll = 0;
13755 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13759 * intel_prepare_plane_fb - Prepare fb for usage on plane
13760 * @plane: drm plane to prepare for
13761 * @fb: framebuffer to prepare for presentation
13763 * Prepares a framebuffer for usage on a display plane. Generally this
13764 * involves pinning the underlying object and updating the frontbuffer tracking
13765 * bits. Some older platforms need special physical address handling for
13768 * Must be called with struct_mutex held.
13770 * Returns 0 on success, negative error code on failure.
13773 intel_prepare_plane_fb(struct drm_plane *plane,
13774 const struct drm_plane_state *new_state)
13776 struct drm_device *dev = plane->dev;
13777 struct drm_framebuffer *fb = new_state->fb;
13778 struct intel_plane *intel_plane = to_intel_plane(plane);
13779 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13780 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13783 if (!obj && !old_obj)
13787 struct drm_crtc_state *crtc_state =
13788 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13790 /* Big Hammer, we also need to ensure that any pending
13791 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13792 * current scanout is retired before unpinning the old
13793 * framebuffer. Note that we rely on userspace rendering
13794 * into the buffer attached to the pipe they are waiting
13795 * on. If not, userspace generates a GPU hang with IPEHR
13796 * point to the MI_WAIT_FOR_EVENT.
13798 * This should only fail upon a hung GPU, in which case we
13799 * can safely continue.
13801 if (needs_modeset(crtc_state))
13802 ret = i915_gem_object_wait_rendering(old_obj, true);
13804 /* Swallow -EIO errors to allow updates during hw lockup. */
13805 if (ret && ret != -EIO)
13809 /* For framebuffer backed by dmabuf, wait for fence */
13810 if (obj && obj->base.dma_buf) {
13813 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13815 MAX_SCHEDULE_TIMEOUT);
13816 if (lret == -ERESTARTSYS)
13819 WARN(lret < 0, "waiting returns %li\n", lret);
13824 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13825 INTEL_INFO(dev)->cursor_needs_physical) {
13826 int align = IS_I830(dev) ? 16 * 1024 : 256;
13827 ret = i915_gem_object_attach_phys(obj, align);
13829 DRM_DEBUG_KMS("failed to attach phys object\n");
13831 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13836 struct intel_plane_state *plane_state =
13837 to_intel_plane_state(new_state);
13839 i915_gem_request_assign(&plane_state->wait_req,
13840 obj->last_write_req);
13843 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13850 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13851 * @plane: drm plane to clean up for
13852 * @fb: old framebuffer that was on plane
13854 * Cleans up a framebuffer that has just been removed from a plane.
13856 * Must be called with struct_mutex held.
13859 intel_cleanup_plane_fb(struct drm_plane *plane,
13860 const struct drm_plane_state *old_state)
13862 struct drm_device *dev = plane->dev;
13863 struct intel_plane *intel_plane = to_intel_plane(plane);
13864 struct intel_plane_state *old_intel_state;
13865 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13866 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13868 old_intel_state = to_intel_plane_state(old_state);
13870 if (!obj && !old_obj)
13873 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13874 !INTEL_INFO(dev)->cursor_needs_physical))
13875 intel_unpin_fb_obj(old_state->fb, old_state);
13877 /* prepare_fb aborted? */
13878 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13879 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13880 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13882 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13887 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13890 struct drm_device *dev;
13891 struct drm_i915_private *dev_priv;
13892 int crtc_clock, cdclk;
13894 if (!intel_crtc || !crtc_state)
13895 return DRM_PLANE_HELPER_NO_SCALING;
13897 dev = intel_crtc->base.dev;
13898 dev_priv = dev->dev_private;
13899 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13900 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13902 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13903 return DRM_PLANE_HELPER_NO_SCALING;
13906 * skl max scale is lower of:
13907 * close to 3 but not 3, -1 is for that purpose
13911 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13917 intel_check_primary_plane(struct drm_plane *plane,
13918 struct intel_crtc_state *crtc_state,
13919 struct intel_plane_state *state)
13921 struct drm_crtc *crtc = state->base.crtc;
13922 struct drm_framebuffer *fb = state->base.fb;
13923 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13924 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13925 bool can_position = false;
13927 if (INTEL_INFO(plane->dev)->gen >= 9) {
13928 /* use scaler when colorkey is not required */
13929 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13931 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13933 can_position = true;
13936 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13937 &state->dst, &state->clip,
13938 min_scale, max_scale,
13939 can_position, true,
13944 intel_commit_primary_plane(struct drm_plane *plane,
13945 struct intel_plane_state *state)
13947 struct drm_crtc *crtc = state->base.crtc;
13948 struct drm_framebuffer *fb = state->base.fb;
13949 struct drm_device *dev = plane->dev;
13950 struct drm_i915_private *dev_priv = dev->dev_private;
13952 crtc = crtc ? crtc : plane->crtc;
13954 dev_priv->display.update_primary_plane(crtc, fb,
13955 state->src.x1 >> 16,
13956 state->src.y1 >> 16);
13960 intel_disable_primary_plane(struct drm_plane *plane,
13961 struct drm_crtc *crtc)
13963 struct drm_device *dev = plane->dev;
13964 struct drm_i915_private *dev_priv = dev->dev_private;
13966 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13969 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13970 struct drm_crtc_state *old_crtc_state)
13972 struct drm_device *dev = crtc->dev;
13973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13974 struct intel_crtc_state *old_intel_state =
13975 to_intel_crtc_state(old_crtc_state);
13976 bool modeset = needs_modeset(crtc->state);
13978 /* Perform vblank evasion around commit operation */
13979 intel_pipe_update_start(intel_crtc);
13984 if (to_intel_crtc_state(crtc->state)->update_pipe)
13985 intel_update_pipe_config(intel_crtc, old_intel_state);
13986 else if (INTEL_INFO(dev)->gen >= 9)
13987 skl_detach_scalers(intel_crtc);
13990 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13991 struct drm_crtc_state *old_crtc_state)
13993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13995 intel_pipe_update_end(intel_crtc);
13999 * intel_plane_destroy - destroy a plane
14000 * @plane: plane to destroy
14002 * Common destruction function for all types of planes (primary, cursor,
14005 void intel_plane_destroy(struct drm_plane *plane)
14007 struct intel_plane *intel_plane = to_intel_plane(plane);
14008 drm_plane_cleanup(plane);
14009 kfree(intel_plane);
14012 const struct drm_plane_funcs intel_plane_funcs = {
14013 .update_plane = drm_atomic_helper_update_plane,
14014 .disable_plane = drm_atomic_helper_disable_plane,
14015 .destroy = intel_plane_destroy,
14016 .set_property = drm_atomic_helper_plane_set_property,
14017 .atomic_get_property = intel_plane_atomic_get_property,
14018 .atomic_set_property = intel_plane_atomic_set_property,
14019 .atomic_duplicate_state = intel_plane_duplicate_state,
14020 .atomic_destroy_state = intel_plane_destroy_state,
14024 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14027 struct intel_plane *primary;
14028 struct intel_plane_state *state;
14029 const uint32_t *intel_primary_formats;
14030 unsigned int num_formats;
14032 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14033 if (primary == NULL)
14036 state = intel_create_plane_state(&primary->base);
14041 primary->base.state = &state->base;
14043 primary->can_scale = false;
14044 primary->max_downscale = 1;
14045 if (INTEL_INFO(dev)->gen >= 9) {
14046 primary->can_scale = true;
14047 state->scaler_id = -1;
14049 primary->pipe = pipe;
14050 primary->plane = pipe;
14051 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14052 primary->check_plane = intel_check_primary_plane;
14053 primary->commit_plane = intel_commit_primary_plane;
14054 primary->disable_plane = intel_disable_primary_plane;
14055 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14056 primary->plane = !pipe;
14058 if (INTEL_INFO(dev)->gen >= 9) {
14059 intel_primary_formats = skl_primary_formats;
14060 num_formats = ARRAY_SIZE(skl_primary_formats);
14061 } else if (INTEL_INFO(dev)->gen >= 4) {
14062 intel_primary_formats = i965_primary_formats;
14063 num_formats = ARRAY_SIZE(i965_primary_formats);
14065 intel_primary_formats = i8xx_primary_formats;
14066 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14069 drm_universal_plane_init(dev, &primary->base, 0,
14070 &intel_plane_funcs,
14071 intel_primary_formats, num_formats,
14072 DRM_PLANE_TYPE_PRIMARY, NULL);
14074 if (INTEL_INFO(dev)->gen >= 4)
14075 intel_create_rotation_property(dev, primary);
14077 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14079 return &primary->base;
14082 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14084 if (!dev->mode_config.rotation_property) {
14085 unsigned long flags = BIT(DRM_ROTATE_0) |
14086 BIT(DRM_ROTATE_180);
14088 if (INTEL_INFO(dev)->gen >= 9)
14089 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14091 dev->mode_config.rotation_property =
14092 drm_mode_create_rotation_property(dev, flags);
14094 if (dev->mode_config.rotation_property)
14095 drm_object_attach_property(&plane->base.base,
14096 dev->mode_config.rotation_property,
14097 plane->base.state->rotation);
14101 intel_check_cursor_plane(struct drm_plane *plane,
14102 struct intel_crtc_state *crtc_state,
14103 struct intel_plane_state *state)
14105 struct drm_crtc *crtc = crtc_state->base.crtc;
14106 struct drm_framebuffer *fb = state->base.fb;
14107 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14108 enum pipe pipe = to_intel_plane(plane)->pipe;
14112 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14113 &state->dst, &state->clip,
14114 DRM_PLANE_HELPER_NO_SCALING,
14115 DRM_PLANE_HELPER_NO_SCALING,
14116 true, true, &state->visible);
14120 /* if we want to turn off the cursor ignore width and height */
14124 /* Check for which cursor types we support */
14125 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14126 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14127 state->base.crtc_w, state->base.crtc_h);
14131 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14132 if (obj->base.size < stride * state->base.crtc_h) {
14133 DRM_DEBUG_KMS("buffer is too small\n");
14137 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14138 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14143 * There's something wrong with the cursor on CHV pipe C.
14144 * If it straddles the left edge of the screen then
14145 * moving it away from the edge or disabling it often
14146 * results in a pipe underrun, and often that can lead to
14147 * dead pipe (constant underrun reported, and it scans
14148 * out just a solid color). To recover from that, the
14149 * display power well must be turned off and on again.
14150 * Refuse the put the cursor into that compromised position.
14152 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14153 state->visible && state->base.crtc_x < 0) {
14154 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14162 intel_disable_cursor_plane(struct drm_plane *plane,
14163 struct drm_crtc *crtc)
14165 intel_crtc_update_cursor(crtc, false);
14169 intel_commit_cursor_plane(struct drm_plane *plane,
14170 struct intel_plane_state *state)
14172 struct drm_crtc *crtc = state->base.crtc;
14173 struct drm_device *dev = plane->dev;
14174 struct intel_crtc *intel_crtc;
14175 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14178 crtc = crtc ? crtc : plane->crtc;
14179 intel_crtc = to_intel_crtc(crtc);
14183 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14184 addr = i915_gem_obj_ggtt_offset(obj);
14186 addr = obj->phys_handle->busaddr;
14188 intel_crtc->cursor_addr = addr;
14190 if (crtc->state->active)
14191 intel_crtc_update_cursor(crtc, state->visible);
14194 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14197 struct intel_plane *cursor;
14198 struct intel_plane_state *state;
14200 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14201 if (cursor == NULL)
14204 state = intel_create_plane_state(&cursor->base);
14209 cursor->base.state = &state->base;
14211 cursor->can_scale = false;
14212 cursor->max_downscale = 1;
14213 cursor->pipe = pipe;
14214 cursor->plane = pipe;
14215 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14216 cursor->check_plane = intel_check_cursor_plane;
14217 cursor->commit_plane = intel_commit_cursor_plane;
14218 cursor->disable_plane = intel_disable_cursor_plane;
14220 drm_universal_plane_init(dev, &cursor->base, 0,
14221 &intel_plane_funcs,
14222 intel_cursor_formats,
14223 ARRAY_SIZE(intel_cursor_formats),
14224 DRM_PLANE_TYPE_CURSOR, NULL);
14226 if (INTEL_INFO(dev)->gen >= 4) {
14227 if (!dev->mode_config.rotation_property)
14228 dev->mode_config.rotation_property =
14229 drm_mode_create_rotation_property(dev,
14230 BIT(DRM_ROTATE_0) |
14231 BIT(DRM_ROTATE_180));
14232 if (dev->mode_config.rotation_property)
14233 drm_object_attach_property(&cursor->base.base,
14234 dev->mode_config.rotation_property,
14235 state->base.rotation);
14238 if (INTEL_INFO(dev)->gen >=9)
14239 state->scaler_id = -1;
14241 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14243 return &cursor->base;
14246 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14247 struct intel_crtc_state *crtc_state)
14250 struct intel_scaler *intel_scaler;
14251 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14253 for (i = 0; i < intel_crtc->num_scalers; i++) {
14254 intel_scaler = &scaler_state->scalers[i];
14255 intel_scaler->in_use = 0;
14256 intel_scaler->mode = PS_SCALER_MODE_DYN;
14259 scaler_state->scaler_id = -1;
14262 static void intel_crtc_init(struct drm_device *dev, int pipe)
14264 struct drm_i915_private *dev_priv = dev->dev_private;
14265 struct intel_crtc *intel_crtc;
14266 struct intel_crtc_state *crtc_state = NULL;
14267 struct drm_plane *primary = NULL;
14268 struct drm_plane *cursor = NULL;
14271 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14272 if (intel_crtc == NULL)
14275 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14278 intel_crtc->config = crtc_state;
14279 intel_crtc->base.state = &crtc_state->base;
14280 crtc_state->base.crtc = &intel_crtc->base;
14282 /* initialize shared scalers */
14283 if (INTEL_INFO(dev)->gen >= 9) {
14284 if (pipe == PIPE_C)
14285 intel_crtc->num_scalers = 1;
14287 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14289 skl_init_scalers(dev, intel_crtc, crtc_state);
14292 primary = intel_primary_plane_create(dev, pipe);
14296 cursor = intel_cursor_plane_create(dev, pipe);
14300 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14301 cursor, &intel_crtc_funcs, NULL);
14305 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14306 for (i = 0; i < 256; i++) {
14307 intel_crtc->lut_r[i] = i;
14308 intel_crtc->lut_g[i] = i;
14309 intel_crtc->lut_b[i] = i;
14313 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14314 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14316 intel_crtc->pipe = pipe;
14317 intel_crtc->plane = pipe;
14318 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14319 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14320 intel_crtc->plane = !pipe;
14323 intel_crtc->cursor_base = ~0;
14324 intel_crtc->cursor_cntl = ~0;
14325 intel_crtc->cursor_size = ~0;
14327 intel_crtc->wm.cxsr_allowed = true;
14329 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14330 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14331 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14332 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14334 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14336 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14341 drm_plane_cleanup(primary);
14343 drm_plane_cleanup(cursor);
14348 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14350 struct drm_encoder *encoder = connector->base.encoder;
14351 struct drm_device *dev = connector->base.dev;
14353 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14355 if (!encoder || WARN_ON(!encoder->crtc))
14356 return INVALID_PIPE;
14358 return to_intel_crtc(encoder->crtc)->pipe;
14361 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14362 struct drm_file *file)
14364 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14365 struct drm_crtc *drmmode_crtc;
14366 struct intel_crtc *crtc;
14368 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14370 if (!drmmode_crtc) {
14371 DRM_ERROR("no such CRTC id\n");
14375 crtc = to_intel_crtc(drmmode_crtc);
14376 pipe_from_crtc_id->pipe = crtc->pipe;
14381 static int intel_encoder_clones(struct intel_encoder *encoder)
14383 struct drm_device *dev = encoder->base.dev;
14384 struct intel_encoder *source_encoder;
14385 int index_mask = 0;
14388 for_each_intel_encoder(dev, source_encoder) {
14389 if (encoders_cloneable(encoder, source_encoder))
14390 index_mask |= (1 << entry);
14398 static bool has_edp_a(struct drm_device *dev)
14400 struct drm_i915_private *dev_priv = dev->dev_private;
14402 if (!IS_MOBILE(dev))
14405 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14408 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14414 static bool intel_crt_present(struct drm_device *dev)
14416 struct drm_i915_private *dev_priv = dev->dev_private;
14418 if (INTEL_INFO(dev)->gen >= 9)
14421 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14424 if (IS_CHERRYVIEW(dev))
14427 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14430 /* DDI E can't be used if DDI A requires 4 lanes */
14431 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14434 if (!dev_priv->vbt.int_crt_support)
14440 static void intel_setup_outputs(struct drm_device *dev)
14442 struct drm_i915_private *dev_priv = dev->dev_private;
14443 struct intel_encoder *encoder;
14444 bool dpd_is_edp = false;
14446 intel_lvds_init(dev);
14448 if (intel_crt_present(dev))
14449 intel_crt_init(dev);
14451 if (IS_BROXTON(dev)) {
14453 * FIXME: Broxton doesn't support port detection via the
14454 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14455 * detect the ports.
14457 intel_ddi_init(dev, PORT_A);
14458 intel_ddi_init(dev, PORT_B);
14459 intel_ddi_init(dev, PORT_C);
14460 } else if (HAS_DDI(dev)) {
14464 * Haswell uses DDI functions to detect digital outputs.
14465 * On SKL pre-D0 the strap isn't connected, so we assume
14468 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14469 /* WaIgnoreDDIAStrap: skl */
14470 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14471 intel_ddi_init(dev, PORT_A);
14473 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14475 found = I915_READ(SFUSE_STRAP);
14477 if (found & SFUSE_STRAP_DDIB_DETECTED)
14478 intel_ddi_init(dev, PORT_B);
14479 if (found & SFUSE_STRAP_DDIC_DETECTED)
14480 intel_ddi_init(dev, PORT_C);
14481 if (found & SFUSE_STRAP_DDID_DETECTED)
14482 intel_ddi_init(dev, PORT_D);
14484 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14486 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14487 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14488 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14489 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14490 intel_ddi_init(dev, PORT_E);
14492 } else if (HAS_PCH_SPLIT(dev)) {
14494 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14496 if (has_edp_a(dev))
14497 intel_dp_init(dev, DP_A, PORT_A);
14499 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14500 /* PCH SDVOB multiplex with HDMIB */
14501 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14503 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14504 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14505 intel_dp_init(dev, PCH_DP_B, PORT_B);
14508 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14509 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14511 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14512 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14514 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14515 intel_dp_init(dev, PCH_DP_C, PORT_C);
14517 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14518 intel_dp_init(dev, PCH_DP_D, PORT_D);
14519 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14521 * The DP_DETECTED bit is the latched state of the DDC
14522 * SDA pin at boot. However since eDP doesn't require DDC
14523 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14524 * eDP ports may have been muxed to an alternate function.
14525 * Thus we can't rely on the DP_DETECTED bit alone to detect
14526 * eDP ports. Consult the VBT as well as DP_DETECTED to
14527 * detect eDP ports.
14529 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14530 !intel_dp_is_edp(dev, PORT_B))
14531 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14532 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14533 intel_dp_is_edp(dev, PORT_B))
14534 intel_dp_init(dev, VLV_DP_B, PORT_B);
14536 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14537 !intel_dp_is_edp(dev, PORT_C))
14538 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14539 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14540 intel_dp_is_edp(dev, PORT_C))
14541 intel_dp_init(dev, VLV_DP_C, PORT_C);
14543 if (IS_CHERRYVIEW(dev)) {
14544 /* eDP not supported on port D, so don't check VBT */
14545 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14546 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14547 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14548 intel_dp_init(dev, CHV_DP_D, PORT_D);
14551 intel_dsi_init(dev);
14552 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14553 bool found = false;
14555 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14556 DRM_DEBUG_KMS("probing SDVOB\n");
14557 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14558 if (!found && IS_G4X(dev)) {
14559 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14560 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14563 if (!found && IS_G4X(dev))
14564 intel_dp_init(dev, DP_B, PORT_B);
14567 /* Before G4X SDVOC doesn't have its own detect register */
14569 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14570 DRM_DEBUG_KMS("probing SDVOC\n");
14571 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14574 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14577 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14578 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14581 intel_dp_init(dev, DP_C, PORT_C);
14585 (I915_READ(DP_D) & DP_DETECTED))
14586 intel_dp_init(dev, DP_D, PORT_D);
14587 } else if (IS_GEN2(dev))
14588 intel_dvo_init(dev);
14590 if (SUPPORTS_TV(dev))
14591 intel_tv_init(dev);
14593 intel_psr_init(dev);
14595 for_each_intel_encoder(dev, encoder) {
14596 encoder->base.possible_crtcs = encoder->crtc_mask;
14597 encoder->base.possible_clones =
14598 intel_encoder_clones(encoder);
14601 intel_init_pch_refclk(dev);
14603 drm_helper_move_panel_connectors_to_head(dev);
14606 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14608 struct drm_device *dev = fb->dev;
14609 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14611 drm_framebuffer_cleanup(fb);
14612 mutex_lock(&dev->struct_mutex);
14613 WARN_ON(!intel_fb->obj->framebuffer_references--);
14614 drm_gem_object_unreference(&intel_fb->obj->base);
14615 mutex_unlock(&dev->struct_mutex);
14619 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14620 struct drm_file *file,
14621 unsigned int *handle)
14623 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14624 struct drm_i915_gem_object *obj = intel_fb->obj;
14626 if (obj->userptr.mm) {
14627 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14631 return drm_gem_handle_create(file, &obj->base, handle);
14634 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14635 struct drm_file *file,
14636 unsigned flags, unsigned color,
14637 struct drm_clip_rect *clips,
14638 unsigned num_clips)
14640 struct drm_device *dev = fb->dev;
14641 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14642 struct drm_i915_gem_object *obj = intel_fb->obj;
14644 mutex_lock(&dev->struct_mutex);
14645 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14646 mutex_unlock(&dev->struct_mutex);
14651 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14652 .destroy = intel_user_framebuffer_destroy,
14653 .create_handle = intel_user_framebuffer_create_handle,
14654 .dirty = intel_user_framebuffer_dirty,
14658 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14659 uint32_t pixel_format)
14661 u32 gen = INTEL_INFO(dev)->gen;
14664 /* "The stride in bytes must not exceed the of the size of 8K
14665 * pixels and 32K bytes."
14667 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14668 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14670 } else if (gen >= 4) {
14671 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14675 } else if (gen >= 3) {
14676 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14681 /* XXX DSPC is limited to 4k tiled */
14686 static int intel_framebuffer_init(struct drm_device *dev,
14687 struct intel_framebuffer *intel_fb,
14688 struct drm_mode_fb_cmd2 *mode_cmd,
14689 struct drm_i915_gem_object *obj)
14691 unsigned int aligned_height;
14693 u32 pitch_limit, stride_alignment;
14695 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14697 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14698 /* Enforce that fb modifier and tiling mode match, but only for
14699 * X-tiled. This is needed for FBC. */
14700 if (!!(obj->tiling_mode == I915_TILING_X) !=
14701 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14702 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14706 if (obj->tiling_mode == I915_TILING_X)
14707 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14708 else if (obj->tiling_mode == I915_TILING_Y) {
14709 DRM_DEBUG("No Y tiling for legacy addfb\n");
14714 /* Passed in modifier sanity checking. */
14715 switch (mode_cmd->modifier[0]) {
14716 case I915_FORMAT_MOD_Y_TILED:
14717 case I915_FORMAT_MOD_Yf_TILED:
14718 if (INTEL_INFO(dev)->gen < 9) {
14719 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14720 mode_cmd->modifier[0]);
14723 case DRM_FORMAT_MOD_NONE:
14724 case I915_FORMAT_MOD_X_TILED:
14727 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14728 mode_cmd->modifier[0]);
14732 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14733 mode_cmd->pixel_format);
14734 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14735 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14736 mode_cmd->pitches[0], stride_alignment);
14740 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14741 mode_cmd->pixel_format);
14742 if (mode_cmd->pitches[0] > pitch_limit) {
14743 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14744 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14745 "tiled" : "linear",
14746 mode_cmd->pitches[0], pitch_limit);
14750 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14751 mode_cmd->pitches[0] != obj->stride) {
14752 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14753 mode_cmd->pitches[0], obj->stride);
14757 /* Reject formats not supported by any plane early. */
14758 switch (mode_cmd->pixel_format) {
14759 case DRM_FORMAT_C8:
14760 case DRM_FORMAT_RGB565:
14761 case DRM_FORMAT_XRGB8888:
14762 case DRM_FORMAT_ARGB8888:
14764 case DRM_FORMAT_XRGB1555:
14765 if (INTEL_INFO(dev)->gen > 3) {
14766 DRM_DEBUG("unsupported pixel format: %s\n",
14767 drm_get_format_name(mode_cmd->pixel_format));
14771 case DRM_FORMAT_ABGR8888:
14772 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14773 INTEL_INFO(dev)->gen < 9) {
14774 DRM_DEBUG("unsupported pixel format: %s\n",
14775 drm_get_format_name(mode_cmd->pixel_format));
14779 case DRM_FORMAT_XBGR8888:
14780 case DRM_FORMAT_XRGB2101010:
14781 case DRM_FORMAT_XBGR2101010:
14782 if (INTEL_INFO(dev)->gen < 4) {
14783 DRM_DEBUG("unsupported pixel format: %s\n",
14784 drm_get_format_name(mode_cmd->pixel_format));
14788 case DRM_FORMAT_ABGR2101010:
14789 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14790 DRM_DEBUG("unsupported pixel format: %s\n",
14791 drm_get_format_name(mode_cmd->pixel_format));
14795 case DRM_FORMAT_YUYV:
14796 case DRM_FORMAT_UYVY:
14797 case DRM_FORMAT_YVYU:
14798 case DRM_FORMAT_VYUY:
14799 if (INTEL_INFO(dev)->gen < 5) {
14800 DRM_DEBUG("unsupported pixel format: %s\n",
14801 drm_get_format_name(mode_cmd->pixel_format));
14806 DRM_DEBUG("unsupported pixel format: %s\n",
14807 drm_get_format_name(mode_cmd->pixel_format));
14811 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14812 if (mode_cmd->offsets[0] != 0)
14815 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14816 mode_cmd->pixel_format,
14817 mode_cmd->modifier[0]);
14818 /* FIXME drm helper for size checks (especially planar formats)? */
14819 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14822 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14823 intel_fb->obj = obj;
14824 intel_fb->obj->framebuffer_references++;
14826 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14828 DRM_ERROR("framebuffer init failed %d\n", ret);
14835 static struct drm_framebuffer *
14836 intel_user_framebuffer_create(struct drm_device *dev,
14837 struct drm_file *filp,
14838 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14840 struct drm_framebuffer *fb;
14841 struct drm_i915_gem_object *obj;
14842 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14844 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14845 mode_cmd.handles[0]));
14846 if (&obj->base == NULL)
14847 return ERR_PTR(-ENOENT);
14849 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14851 drm_gem_object_unreference_unlocked(&obj->base);
14856 #ifndef CONFIG_DRM_FBDEV_EMULATION
14857 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14862 static const struct drm_mode_config_funcs intel_mode_funcs = {
14863 .fb_create = intel_user_framebuffer_create,
14864 .output_poll_changed = intel_fbdev_output_poll_changed,
14865 .atomic_check = intel_atomic_check,
14866 .atomic_commit = intel_atomic_commit,
14867 .atomic_state_alloc = intel_atomic_state_alloc,
14868 .atomic_state_clear = intel_atomic_state_clear,
14871 /* Set up chip specific display functions */
14872 static void intel_init_display(struct drm_device *dev)
14874 struct drm_i915_private *dev_priv = dev->dev_private;
14876 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14877 dev_priv->display.find_dpll = g4x_find_best_dpll;
14878 else if (IS_CHERRYVIEW(dev))
14879 dev_priv->display.find_dpll = chv_find_best_dpll;
14880 else if (IS_VALLEYVIEW(dev))
14881 dev_priv->display.find_dpll = vlv_find_best_dpll;
14882 else if (IS_PINEVIEW(dev))
14883 dev_priv->display.find_dpll = pnv_find_best_dpll;
14885 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14887 if (INTEL_INFO(dev)->gen >= 9) {
14888 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14889 dev_priv->display.get_initial_plane_config =
14890 skylake_get_initial_plane_config;
14891 dev_priv->display.crtc_compute_clock =
14892 haswell_crtc_compute_clock;
14893 dev_priv->display.crtc_enable = haswell_crtc_enable;
14894 dev_priv->display.crtc_disable = haswell_crtc_disable;
14895 dev_priv->display.update_primary_plane =
14896 skylake_update_primary_plane;
14897 } else if (HAS_DDI(dev)) {
14898 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14899 dev_priv->display.get_initial_plane_config =
14900 ironlake_get_initial_plane_config;
14901 dev_priv->display.crtc_compute_clock =
14902 haswell_crtc_compute_clock;
14903 dev_priv->display.crtc_enable = haswell_crtc_enable;
14904 dev_priv->display.crtc_disable = haswell_crtc_disable;
14905 dev_priv->display.update_primary_plane =
14906 ironlake_update_primary_plane;
14907 } else if (HAS_PCH_SPLIT(dev)) {
14908 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14909 dev_priv->display.get_initial_plane_config =
14910 ironlake_get_initial_plane_config;
14911 dev_priv->display.crtc_compute_clock =
14912 ironlake_crtc_compute_clock;
14913 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14914 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14915 dev_priv->display.update_primary_plane =
14916 ironlake_update_primary_plane;
14917 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14918 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14919 dev_priv->display.get_initial_plane_config =
14920 i9xx_get_initial_plane_config;
14921 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14922 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14923 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14924 dev_priv->display.update_primary_plane =
14925 i9xx_update_primary_plane;
14927 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14928 dev_priv->display.get_initial_plane_config =
14929 i9xx_get_initial_plane_config;
14930 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14931 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14932 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14933 dev_priv->display.update_primary_plane =
14934 i9xx_update_primary_plane;
14937 /* Returns the core display clock speed */
14938 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14939 dev_priv->display.get_display_clock_speed =
14940 skylake_get_display_clock_speed;
14941 else if (IS_BROXTON(dev))
14942 dev_priv->display.get_display_clock_speed =
14943 broxton_get_display_clock_speed;
14944 else if (IS_BROADWELL(dev))
14945 dev_priv->display.get_display_clock_speed =
14946 broadwell_get_display_clock_speed;
14947 else if (IS_HASWELL(dev))
14948 dev_priv->display.get_display_clock_speed =
14949 haswell_get_display_clock_speed;
14950 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14951 dev_priv->display.get_display_clock_speed =
14952 valleyview_get_display_clock_speed;
14953 else if (IS_GEN5(dev))
14954 dev_priv->display.get_display_clock_speed =
14955 ilk_get_display_clock_speed;
14956 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14957 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14958 dev_priv->display.get_display_clock_speed =
14959 i945_get_display_clock_speed;
14960 else if (IS_GM45(dev))
14961 dev_priv->display.get_display_clock_speed =
14962 gm45_get_display_clock_speed;
14963 else if (IS_CRESTLINE(dev))
14964 dev_priv->display.get_display_clock_speed =
14965 i965gm_get_display_clock_speed;
14966 else if (IS_PINEVIEW(dev))
14967 dev_priv->display.get_display_clock_speed =
14968 pnv_get_display_clock_speed;
14969 else if (IS_G33(dev) || IS_G4X(dev))
14970 dev_priv->display.get_display_clock_speed =
14971 g33_get_display_clock_speed;
14972 else if (IS_I915G(dev))
14973 dev_priv->display.get_display_clock_speed =
14974 i915_get_display_clock_speed;
14975 else if (IS_I945GM(dev) || IS_845G(dev))
14976 dev_priv->display.get_display_clock_speed =
14977 i9xx_misc_get_display_clock_speed;
14978 else if (IS_I915GM(dev))
14979 dev_priv->display.get_display_clock_speed =
14980 i915gm_get_display_clock_speed;
14981 else if (IS_I865G(dev))
14982 dev_priv->display.get_display_clock_speed =
14983 i865_get_display_clock_speed;
14984 else if (IS_I85X(dev))
14985 dev_priv->display.get_display_clock_speed =
14986 i85x_get_display_clock_speed;
14988 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14989 dev_priv->display.get_display_clock_speed =
14990 i830_get_display_clock_speed;
14993 if (IS_GEN5(dev)) {
14994 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14995 } else if (IS_GEN6(dev)) {
14996 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14997 } else if (IS_IVYBRIDGE(dev)) {
14998 /* FIXME: detect B0+ stepping and use auto training */
14999 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15000 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
15001 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15002 if (IS_BROADWELL(dev)) {
15003 dev_priv->display.modeset_commit_cdclk =
15004 broadwell_modeset_commit_cdclk;
15005 dev_priv->display.modeset_calc_cdclk =
15006 broadwell_modeset_calc_cdclk;
15008 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15009 dev_priv->display.modeset_commit_cdclk =
15010 valleyview_modeset_commit_cdclk;
15011 dev_priv->display.modeset_calc_cdclk =
15012 valleyview_modeset_calc_cdclk;
15013 } else if (IS_BROXTON(dev)) {
15014 dev_priv->display.modeset_commit_cdclk =
15015 broxton_modeset_commit_cdclk;
15016 dev_priv->display.modeset_calc_cdclk =
15017 broxton_modeset_calc_cdclk;
15020 switch (INTEL_INFO(dev)->gen) {
15022 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15026 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15031 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15035 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15038 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15039 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15042 /* Drop through - unsupported since execlist only. */
15044 /* Default just returns -ENODEV to indicate unsupported */
15045 dev_priv->display.queue_flip = intel_default_queue_flip;
15048 mutex_init(&dev_priv->pps_mutex);
15052 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15053 * resume, or other times. This quirk makes sure that's the case for
15054 * affected systems.
15056 static void quirk_pipea_force(struct drm_device *dev)
15058 struct drm_i915_private *dev_priv = dev->dev_private;
15060 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15061 DRM_INFO("applying pipe a force quirk\n");
15064 static void quirk_pipeb_force(struct drm_device *dev)
15066 struct drm_i915_private *dev_priv = dev->dev_private;
15068 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15069 DRM_INFO("applying pipe b force quirk\n");
15073 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15075 static void quirk_ssc_force_disable(struct drm_device *dev)
15077 struct drm_i915_private *dev_priv = dev->dev_private;
15078 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15079 DRM_INFO("applying lvds SSC disable quirk\n");
15083 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15086 static void quirk_invert_brightness(struct drm_device *dev)
15088 struct drm_i915_private *dev_priv = dev->dev_private;
15089 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15090 DRM_INFO("applying inverted panel brightness quirk\n");
15093 /* Some VBT's incorrectly indicate no backlight is present */
15094 static void quirk_backlight_present(struct drm_device *dev)
15096 struct drm_i915_private *dev_priv = dev->dev_private;
15097 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15098 DRM_INFO("applying backlight present quirk\n");
15101 struct intel_quirk {
15103 int subsystem_vendor;
15104 int subsystem_device;
15105 void (*hook)(struct drm_device *dev);
15108 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15109 struct intel_dmi_quirk {
15110 void (*hook)(struct drm_device *dev);
15111 const struct dmi_system_id (*dmi_id_list)[];
15114 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15116 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15120 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15122 .dmi_id_list = &(const struct dmi_system_id[]) {
15124 .callback = intel_dmi_reverse_brightness,
15125 .ident = "NCR Corporation",
15126 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15127 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15130 { } /* terminating entry */
15132 .hook = quirk_invert_brightness,
15136 static struct intel_quirk intel_quirks[] = {
15137 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15138 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15140 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15141 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15143 /* 830 needs to leave pipe A & dpll A up */
15144 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15146 /* 830 needs to leave pipe B & dpll B up */
15147 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15149 /* Lenovo U160 cannot use SSC on LVDS */
15150 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15152 /* Sony Vaio Y cannot use SSC on LVDS */
15153 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15155 /* Acer Aspire 5734Z must invert backlight brightness */
15156 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15158 /* Acer/eMachines G725 */
15159 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15161 /* Acer/eMachines e725 */
15162 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15164 /* Acer/Packard Bell NCL20 */
15165 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15167 /* Acer Aspire 4736Z */
15168 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15170 /* Acer Aspire 5336 */
15171 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15173 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15174 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15176 /* Acer C720 Chromebook (Core i3 4005U) */
15177 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15179 /* Apple Macbook 2,1 (Core 2 T7400) */
15180 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15182 /* Apple Macbook 4,1 */
15183 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15185 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15186 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15188 /* HP Chromebook 14 (Celeron 2955U) */
15189 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15191 /* Dell Chromebook 11 */
15192 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15194 /* Dell Chromebook 11 (2015 version) */
15195 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15198 static void intel_init_quirks(struct drm_device *dev)
15200 struct pci_dev *d = dev->pdev;
15203 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15204 struct intel_quirk *q = &intel_quirks[i];
15206 if (d->device == q->device &&
15207 (d->subsystem_vendor == q->subsystem_vendor ||
15208 q->subsystem_vendor == PCI_ANY_ID) &&
15209 (d->subsystem_device == q->subsystem_device ||
15210 q->subsystem_device == PCI_ANY_ID))
15213 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15214 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15215 intel_dmi_quirks[i].hook(dev);
15219 /* Disable the VGA plane that we never use */
15220 static void i915_disable_vga(struct drm_device *dev)
15222 struct drm_i915_private *dev_priv = dev->dev_private;
15224 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15226 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15227 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15228 outb(SR01, VGA_SR_INDEX);
15229 sr1 = inb(VGA_SR_DATA);
15230 outb(sr1 | 1<<5, VGA_SR_DATA);
15231 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15234 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15235 POSTING_READ(vga_reg);
15238 void intel_modeset_init_hw(struct drm_device *dev)
15240 intel_update_cdclk(dev);
15241 intel_prepare_ddi(dev);
15242 intel_init_clock_gating(dev);
15243 intel_enable_gt_powersave(dev);
15246 void intel_modeset_init(struct drm_device *dev)
15248 struct drm_i915_private *dev_priv = dev->dev_private;
15251 struct intel_crtc *crtc;
15253 drm_mode_config_init(dev);
15255 dev->mode_config.min_width = 0;
15256 dev->mode_config.min_height = 0;
15258 dev->mode_config.preferred_depth = 24;
15259 dev->mode_config.prefer_shadow = 1;
15261 dev->mode_config.allow_fb_modifiers = true;
15263 dev->mode_config.funcs = &intel_mode_funcs;
15265 intel_init_quirks(dev);
15267 intel_init_pm(dev);
15269 if (INTEL_INFO(dev)->num_pipes == 0)
15273 * There may be no VBT; and if the BIOS enabled SSC we can
15274 * just keep using it to avoid unnecessary flicker. Whereas if the
15275 * BIOS isn't using it, don't assume it will work even if the VBT
15276 * indicates as much.
15278 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15279 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15282 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15283 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15284 bios_lvds_use_ssc ? "en" : "dis",
15285 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15286 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15290 intel_init_display(dev);
15291 intel_init_audio(dev);
15293 if (IS_GEN2(dev)) {
15294 dev->mode_config.max_width = 2048;
15295 dev->mode_config.max_height = 2048;
15296 } else if (IS_GEN3(dev)) {
15297 dev->mode_config.max_width = 4096;
15298 dev->mode_config.max_height = 4096;
15300 dev->mode_config.max_width = 8192;
15301 dev->mode_config.max_height = 8192;
15304 if (IS_845G(dev) || IS_I865G(dev)) {
15305 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15306 dev->mode_config.cursor_height = 1023;
15307 } else if (IS_GEN2(dev)) {
15308 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15309 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15311 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15312 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15315 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15317 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15318 INTEL_INFO(dev)->num_pipes,
15319 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15321 for_each_pipe(dev_priv, pipe) {
15322 intel_crtc_init(dev, pipe);
15323 for_each_sprite(dev_priv, pipe, sprite) {
15324 ret = intel_plane_init(dev, pipe, sprite);
15326 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15327 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15331 intel_update_czclk(dev_priv);
15332 intel_update_cdclk(dev);
15334 intel_shared_dpll_init(dev);
15336 /* Just disable it once at startup */
15337 i915_disable_vga(dev);
15338 intel_setup_outputs(dev);
15340 drm_modeset_lock_all(dev);
15341 intel_modeset_setup_hw_state(dev);
15342 drm_modeset_unlock_all(dev);
15344 for_each_intel_crtc(dev, crtc) {
15345 struct intel_initial_plane_config plane_config = {};
15351 * Note that reserving the BIOS fb up front prevents us
15352 * from stuffing other stolen allocations like the ring
15353 * on top. This prevents some ugliness at boot time, and
15354 * can even allow for smooth boot transitions if the BIOS
15355 * fb is large enough for the active pipe configuration.
15357 dev_priv->display.get_initial_plane_config(crtc,
15361 * If the fb is shared between multiple heads, we'll
15362 * just get the first one.
15364 intel_find_initial_plane_obj(crtc, &plane_config);
15368 static void intel_enable_pipe_a(struct drm_device *dev)
15370 struct intel_connector *connector;
15371 struct drm_connector *crt = NULL;
15372 struct intel_load_detect_pipe load_detect_temp;
15373 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15375 /* We can't just switch on the pipe A, we need to set things up with a
15376 * proper mode and output configuration. As a gross hack, enable pipe A
15377 * by enabling the load detect pipe once. */
15378 for_each_intel_connector(dev, connector) {
15379 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15380 crt = &connector->base;
15388 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15389 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15393 intel_check_plane_mapping(struct intel_crtc *crtc)
15395 struct drm_device *dev = crtc->base.dev;
15396 struct drm_i915_private *dev_priv = dev->dev_private;
15399 if (INTEL_INFO(dev)->num_pipes == 1)
15402 val = I915_READ(DSPCNTR(!crtc->plane));
15404 if ((val & DISPLAY_PLANE_ENABLE) &&
15405 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15411 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15413 struct drm_device *dev = crtc->base.dev;
15414 struct intel_encoder *encoder;
15416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15422 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15424 struct drm_device *dev = crtc->base.dev;
15425 struct drm_i915_private *dev_priv = dev->dev_private;
15426 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15428 /* Clear any frame start delays used for debugging left by the BIOS */
15429 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15431 /* restore vblank interrupts to correct state */
15432 drm_crtc_vblank_reset(&crtc->base);
15433 if (crtc->active) {
15434 struct intel_plane *plane;
15436 drm_crtc_vblank_on(&crtc->base);
15438 /* Disable everything but the primary plane */
15439 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15440 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15443 plane->disable_plane(&plane->base, &crtc->base);
15447 /* We need to sanitize the plane -> pipe mapping first because this will
15448 * disable the crtc (and hence change the state) if it is wrong. Note
15449 * that gen4+ has a fixed plane -> pipe mapping. */
15450 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15453 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15454 crtc->base.base.id);
15456 /* Pipe has the wrong plane attached and the plane is active.
15457 * Temporarily change the plane mapping and disable everything
15459 plane = crtc->plane;
15460 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15461 crtc->plane = !plane;
15462 intel_crtc_disable_noatomic(&crtc->base);
15463 crtc->plane = plane;
15466 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15467 crtc->pipe == PIPE_A && !crtc->active) {
15468 /* BIOS forgot to enable pipe A, this mostly happens after
15469 * resume. Force-enable the pipe to fix this, the update_dpms
15470 * call below we restore the pipe to the right state, but leave
15471 * the required bits on. */
15472 intel_enable_pipe_a(dev);
15475 /* Adjust the state of the output pipe according to whether we
15476 * have active connectors/encoders. */
15477 if (!intel_crtc_has_encoders(crtc))
15478 intel_crtc_disable_noatomic(&crtc->base);
15480 if (crtc->active != crtc->base.state->active) {
15481 struct intel_encoder *encoder;
15483 /* This can happen either due to bugs in the get_hw_state
15484 * functions or because of calls to intel_crtc_disable_noatomic,
15485 * or because the pipe is force-enabled due to the
15487 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15488 crtc->base.base.id,
15489 crtc->base.state->enable ? "enabled" : "disabled",
15490 crtc->active ? "enabled" : "disabled");
15492 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15493 crtc->base.state->active = crtc->active;
15494 crtc->base.enabled = crtc->active;
15495 crtc->base.state->connector_mask = 0;
15497 /* Because we only establish the connector -> encoder ->
15498 * crtc links if something is active, this means the
15499 * crtc is now deactivated. Break the links. connector
15500 * -> encoder links are only establish when things are
15501 * actually up, hence no need to break them. */
15502 WARN_ON(crtc->active);
15504 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15505 encoder->base.crtc = NULL;
15508 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15510 * We start out with underrun reporting disabled to avoid races.
15511 * For correct bookkeeping mark this on active crtcs.
15513 * Also on gmch platforms we dont have any hardware bits to
15514 * disable the underrun reporting. Which means we need to start
15515 * out with underrun reporting disabled also on inactive pipes,
15516 * since otherwise we'll complain about the garbage we read when
15517 * e.g. coming up after runtime pm.
15519 * No protection against concurrent access is required - at
15520 * worst a fifo underrun happens which also sets this to false.
15522 crtc->cpu_fifo_underrun_disabled = true;
15523 crtc->pch_fifo_underrun_disabled = true;
15527 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15529 struct intel_connector *connector;
15530 struct drm_device *dev = encoder->base.dev;
15531 bool active = false;
15533 /* We need to check both for a crtc link (meaning that the
15534 * encoder is active and trying to read from a pipe) and the
15535 * pipe itself being active. */
15536 bool has_active_crtc = encoder->base.crtc &&
15537 to_intel_crtc(encoder->base.crtc)->active;
15539 for_each_intel_connector(dev, connector) {
15540 if (connector->base.encoder != &encoder->base)
15547 if (active && !has_active_crtc) {
15548 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15549 encoder->base.base.id,
15550 encoder->base.name);
15552 /* Connector is active, but has no active pipe. This is
15553 * fallout from our resume register restoring. Disable
15554 * the encoder manually again. */
15555 if (encoder->base.crtc) {
15556 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15557 encoder->base.base.id,
15558 encoder->base.name);
15559 encoder->disable(encoder);
15560 if (encoder->post_disable)
15561 encoder->post_disable(encoder);
15563 encoder->base.crtc = NULL;
15565 /* Inconsistent output/port/pipe state happens presumably due to
15566 * a bug in one of the get_hw_state functions. Or someplace else
15567 * in our code, like the register restore mess on resume. Clamp
15568 * things to off as a safer default. */
15569 for_each_intel_connector(dev, connector) {
15570 if (connector->encoder != encoder)
15572 connector->base.dpms = DRM_MODE_DPMS_OFF;
15573 connector->base.encoder = NULL;
15576 /* Enabled encoders without active connectors will be fixed in
15577 * the crtc fixup. */
15580 void i915_redisable_vga_power_on(struct drm_device *dev)
15582 struct drm_i915_private *dev_priv = dev->dev_private;
15583 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15585 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15586 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15587 i915_disable_vga(dev);
15591 void i915_redisable_vga(struct drm_device *dev)
15593 struct drm_i915_private *dev_priv = dev->dev_private;
15595 /* This function can be called both from intel_modeset_setup_hw_state or
15596 * at a very early point in our resume sequence, where the power well
15597 * structures are not yet restored. Since this function is at a very
15598 * paranoid "someone might have enabled VGA while we were not looking"
15599 * level, just check if the power well is enabled instead of trying to
15600 * follow the "don't touch the power well if we don't need it" policy
15601 * the rest of the driver uses. */
15602 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15605 i915_redisable_vga_power_on(dev);
15607 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15610 static bool primary_get_hw_state(struct intel_plane *plane)
15612 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15614 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15617 /* FIXME read out full plane state for all planes */
15618 static void readout_plane_state(struct intel_crtc *crtc)
15620 struct drm_plane *primary = crtc->base.primary;
15621 struct intel_plane_state *plane_state =
15622 to_intel_plane_state(primary->state);
15624 plane_state->visible = crtc->active &&
15625 primary_get_hw_state(to_intel_plane(primary));
15627 if (plane_state->visible)
15628 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15631 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15633 struct drm_i915_private *dev_priv = dev->dev_private;
15635 struct intel_crtc *crtc;
15636 struct intel_encoder *encoder;
15637 struct intel_connector *connector;
15640 for_each_intel_crtc(dev, crtc) {
15641 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15642 memset(crtc->config, 0, sizeof(*crtc->config));
15643 crtc->config->base.crtc = &crtc->base;
15645 crtc->active = dev_priv->display.get_pipe_config(crtc,
15648 crtc->base.state->active = crtc->active;
15649 crtc->base.enabled = crtc->active;
15651 readout_plane_state(crtc);
15653 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15654 crtc->base.base.id,
15655 crtc->active ? "enabled" : "disabled");
15658 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15659 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15661 pll->on = pll->get_hw_state(dev_priv, pll,
15662 &pll->config.hw_state);
15664 pll->config.crtc_mask = 0;
15665 for_each_intel_crtc(dev, crtc) {
15666 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15668 pll->config.crtc_mask |= 1 << crtc->pipe;
15672 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15673 pll->name, pll->config.crtc_mask, pll->on);
15675 if (pll->config.crtc_mask)
15676 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15679 for_each_intel_encoder(dev, encoder) {
15682 if (encoder->get_hw_state(encoder, &pipe)) {
15683 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15684 encoder->base.crtc = &crtc->base;
15685 encoder->get_config(encoder, crtc->config);
15687 encoder->base.crtc = NULL;
15690 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15691 encoder->base.base.id,
15692 encoder->base.name,
15693 encoder->base.crtc ? "enabled" : "disabled",
15697 for_each_intel_connector(dev, connector) {
15698 if (connector->get_hw_state(connector)) {
15699 connector->base.dpms = DRM_MODE_DPMS_ON;
15701 encoder = connector->encoder;
15702 connector->base.encoder = &encoder->base;
15704 if (encoder->base.crtc &&
15705 encoder->base.crtc->state->active) {
15707 * This has to be done during hardware readout
15708 * because anything calling .crtc_disable may
15709 * rely on the connector_mask being accurate.
15711 encoder->base.crtc->state->connector_mask |=
15712 1 << drm_connector_index(&connector->base);
15716 connector->base.dpms = DRM_MODE_DPMS_OFF;
15717 connector->base.encoder = NULL;
15719 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15720 connector->base.base.id,
15721 connector->base.name,
15722 connector->base.encoder ? "enabled" : "disabled");
15725 for_each_intel_crtc(dev, crtc) {
15726 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15728 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15729 if (crtc->base.state->active) {
15730 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15731 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15732 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15735 * The initial mode needs to be set in order to keep
15736 * the atomic core happy. It wants a valid mode if the
15737 * crtc's enabled, so we do the above call.
15739 * At this point some state updated by the connectors
15740 * in their ->detect() callback has not run yet, so
15741 * no recalculation can be done yet.
15743 * Even if we could do a recalculation and modeset
15744 * right now it would cause a double modeset if
15745 * fbdev or userspace chooses a different initial mode.
15747 * If that happens, someone indicated they wanted a
15748 * mode change, which means it's safe to do a full
15751 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15753 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15754 update_scanline_offset(crtc);
15759 /* Scan out the current hw modeset state,
15760 * and sanitizes it to the current state
15763 intel_modeset_setup_hw_state(struct drm_device *dev)
15765 struct drm_i915_private *dev_priv = dev->dev_private;
15767 struct intel_crtc *crtc;
15768 struct intel_encoder *encoder;
15771 intel_modeset_readout_hw_state(dev);
15773 /* HW state is read out, now we need to sanitize this mess. */
15774 for_each_intel_encoder(dev, encoder) {
15775 intel_sanitize_encoder(encoder);
15778 for_each_pipe(dev_priv, pipe) {
15779 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15780 intel_sanitize_crtc(crtc);
15781 intel_dump_pipe_config(crtc, crtc->config,
15782 "[setup_hw_state]");
15785 intel_modeset_update_connector_atomic_state(dev);
15787 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15788 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15790 if (!pll->on || pll->active)
15793 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15795 pll->disable(dev_priv, pll);
15799 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15800 vlv_wm_get_hw_state(dev);
15801 else if (IS_GEN9(dev))
15802 skl_wm_get_hw_state(dev);
15803 else if (HAS_PCH_SPLIT(dev))
15804 ilk_wm_get_hw_state(dev);
15806 for_each_intel_crtc(dev, crtc) {
15807 unsigned long put_domains;
15809 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15810 if (WARN_ON(put_domains))
15811 modeset_put_power_domains(dev_priv, put_domains);
15813 intel_display_set_init_power(dev_priv, false);
15816 void intel_display_resume(struct drm_device *dev)
15818 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15819 struct intel_connector *conn;
15820 struct intel_plane *plane;
15821 struct drm_crtc *crtc;
15827 state->acquire_ctx = dev->mode_config.acquire_ctx;
15829 /* preserve complete old state, including dpll */
15830 intel_atomic_get_shared_dpll_state(state);
15832 for_each_crtc(dev, crtc) {
15833 struct drm_crtc_state *crtc_state =
15834 drm_atomic_get_crtc_state(state, crtc);
15836 ret = PTR_ERR_OR_ZERO(crtc_state);
15840 /* force a restore */
15841 crtc_state->mode_changed = true;
15844 for_each_intel_plane(dev, plane) {
15845 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15850 for_each_intel_connector(dev, conn) {
15851 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15856 intel_modeset_setup_hw_state(dev);
15858 i915_redisable_vga(dev);
15859 ret = drm_atomic_commit(state);
15864 DRM_ERROR("Restoring old state failed with %i\n", ret);
15865 drm_atomic_state_free(state);
15868 void intel_modeset_gem_init(struct drm_device *dev)
15870 struct drm_crtc *c;
15871 struct drm_i915_gem_object *obj;
15874 mutex_lock(&dev->struct_mutex);
15875 intel_init_gt_powersave(dev);
15876 mutex_unlock(&dev->struct_mutex);
15878 intel_modeset_init_hw(dev);
15880 intel_setup_overlay(dev);
15883 * Make sure any fbs we allocated at startup are properly
15884 * pinned & fenced. When we do the allocation it's too early
15887 for_each_crtc(dev, c) {
15888 obj = intel_fb_obj(c->primary->fb);
15892 mutex_lock(&dev->struct_mutex);
15893 ret = intel_pin_and_fence_fb_obj(c->primary,
15895 c->primary->state);
15896 mutex_unlock(&dev->struct_mutex);
15898 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15899 to_intel_crtc(c)->pipe);
15900 drm_framebuffer_unreference(c->primary->fb);
15901 c->primary->fb = NULL;
15902 c->primary->crtc = c->primary->state->crtc = NULL;
15903 update_state_fb(c->primary);
15904 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15908 intel_backlight_register(dev);
15911 void intel_connector_unregister(struct intel_connector *intel_connector)
15913 struct drm_connector *connector = &intel_connector->base;
15915 intel_panel_destroy_backlight(connector);
15916 drm_connector_unregister(connector);
15919 void intel_modeset_cleanup(struct drm_device *dev)
15921 struct drm_i915_private *dev_priv = dev->dev_private;
15922 struct intel_connector *connector;
15924 intel_disable_gt_powersave(dev);
15926 intel_backlight_unregister(dev);
15929 * Interrupts and polling as the first thing to avoid creating havoc.
15930 * Too much stuff here (turning of connectors, ...) would
15931 * experience fancy races otherwise.
15933 intel_irq_uninstall(dev_priv);
15936 * Due to the hpd irq storm handling the hotplug work can re-arm the
15937 * poll handlers. Hence disable polling after hpd handling is shut down.
15939 drm_kms_helper_poll_fini(dev);
15941 intel_unregister_dsm_handler();
15943 intel_fbc_disable(dev_priv);
15945 /* flush any delayed tasks or pending work */
15946 flush_scheduled_work();
15948 /* destroy the backlight and sysfs files before encoders/connectors */
15949 for_each_intel_connector(dev, connector)
15950 connector->unregister(connector);
15952 drm_mode_config_cleanup(dev);
15954 intel_cleanup_overlay(dev);
15956 mutex_lock(&dev->struct_mutex);
15957 intel_cleanup_gt_powersave(dev);
15958 mutex_unlock(&dev->struct_mutex);
15960 intel_teardown_gmbus(dev);
15964 * Return which encoder is currently attached for connector.
15966 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15968 return &intel_attached_encoder(connector)->base;
15971 void intel_connector_attach_encoder(struct intel_connector *connector,
15972 struct intel_encoder *encoder)
15974 connector->encoder = encoder;
15975 drm_mode_connector_attach_encoder(&connector->base,
15980 * set vga decode state - true == enable VGA decode
15982 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15984 struct drm_i915_private *dev_priv = dev->dev_private;
15985 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15988 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15989 DRM_ERROR("failed to read control word\n");
15993 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15997 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15999 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16001 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16002 DRM_ERROR("failed to write control word\n");
16009 struct intel_display_error_state {
16011 u32 power_well_driver;
16013 int num_transcoders;
16015 struct intel_cursor_error_state {
16020 } cursor[I915_MAX_PIPES];
16022 struct intel_pipe_error_state {
16023 bool power_domain_on;
16026 } pipe[I915_MAX_PIPES];
16028 struct intel_plane_error_state {
16036 } plane[I915_MAX_PIPES];
16038 struct intel_transcoder_error_state {
16039 bool power_domain_on;
16040 enum transcoder cpu_transcoder;
16053 struct intel_display_error_state *
16054 intel_display_capture_error_state(struct drm_device *dev)
16056 struct drm_i915_private *dev_priv = dev->dev_private;
16057 struct intel_display_error_state *error;
16058 int transcoders[] = {
16066 if (INTEL_INFO(dev)->num_pipes == 0)
16069 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16073 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16074 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16076 for_each_pipe(dev_priv, i) {
16077 error->pipe[i].power_domain_on =
16078 __intel_display_power_is_enabled(dev_priv,
16079 POWER_DOMAIN_PIPE(i));
16080 if (!error->pipe[i].power_domain_on)
16083 error->cursor[i].control = I915_READ(CURCNTR(i));
16084 error->cursor[i].position = I915_READ(CURPOS(i));
16085 error->cursor[i].base = I915_READ(CURBASE(i));
16087 error->plane[i].control = I915_READ(DSPCNTR(i));
16088 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16089 if (INTEL_INFO(dev)->gen <= 3) {
16090 error->plane[i].size = I915_READ(DSPSIZE(i));
16091 error->plane[i].pos = I915_READ(DSPPOS(i));
16093 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16094 error->plane[i].addr = I915_READ(DSPADDR(i));
16095 if (INTEL_INFO(dev)->gen >= 4) {
16096 error->plane[i].surface = I915_READ(DSPSURF(i));
16097 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16100 error->pipe[i].source = I915_READ(PIPESRC(i));
16102 if (HAS_GMCH_DISPLAY(dev))
16103 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16106 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16107 if (HAS_DDI(dev_priv->dev))
16108 error->num_transcoders++; /* Account for eDP. */
16110 for (i = 0; i < error->num_transcoders; i++) {
16111 enum transcoder cpu_transcoder = transcoders[i];
16113 error->transcoder[i].power_domain_on =
16114 __intel_display_power_is_enabled(dev_priv,
16115 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16116 if (!error->transcoder[i].power_domain_on)
16119 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16121 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16122 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16123 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16124 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16125 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16126 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16127 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16133 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16136 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16137 struct drm_device *dev,
16138 struct intel_display_error_state *error)
16140 struct drm_i915_private *dev_priv = dev->dev_private;
16146 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16147 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16148 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16149 error->power_well_driver);
16150 for_each_pipe(dev_priv, i) {
16151 err_printf(m, "Pipe [%d]:\n", i);
16152 err_printf(m, " Power: %s\n",
16153 error->pipe[i].power_domain_on ? "on" : "off");
16154 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16155 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16157 err_printf(m, "Plane [%d]:\n", i);
16158 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16159 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16160 if (INTEL_INFO(dev)->gen <= 3) {
16161 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16162 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16164 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16165 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16166 if (INTEL_INFO(dev)->gen >= 4) {
16167 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16168 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16171 err_printf(m, "Cursor [%d]:\n", i);
16172 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16173 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16174 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16177 for (i = 0; i < error->num_transcoders; i++) {
16178 err_printf(m, "CPU transcoder: %c\n",
16179 transcoder_name(error->transcoder[i].cpu_transcoder));
16180 err_printf(m, " Power: %s\n",
16181 error->transcoder[i].power_domain_on ? "on" : "off");
16182 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16183 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16184 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16185 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16186 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16187 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16188 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16192 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16194 struct intel_crtc *crtc;
16196 for_each_intel_crtc(dev, crtc) {
16197 struct intel_unpin_work *work;
16199 spin_lock_irq(&dev->event_lock);
16201 work = crtc->unpin_work;
16203 if (work && work->event &&
16204 work->event->base.file_priv == file) {
16205 kfree(work->event);
16206 work->event = NULL;
16209 spin_unlock_irq(&dev->event_lock);