drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         i915_reg_t reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         i915_reg_t pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1484                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1485                         return false;
1486         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1488                         return false;
1489         } else {
1490                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1491                         return false;
1492         }
1493         return true;
1494 }
1495
1496 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1497                               enum pipe pipe, u32 val)
1498 {
1499         if ((val & SDVO_ENABLE) == 0)
1500                 return false;
1501
1502         if (HAS_PCH_CPT(dev_priv->dev)) {
1503                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1504                         return false;
1505         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1506                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1507                         return false;
1508         } else {
1509                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1510                         return false;
1511         }
1512         return true;
1513 }
1514
1515 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1516                               enum pipe pipe, u32 val)
1517 {
1518         if ((val & LVDS_PORT_EN) == 0)
1519                 return false;
1520
1521         if (HAS_PCH_CPT(dev_priv->dev)) {
1522                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1523                         return false;
1524         } else {
1525                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1526                         return false;
1527         }
1528         return true;
1529 }
1530
1531 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1532                               enum pipe pipe, u32 val)
1533 {
1534         if ((val & ADPA_DAC_ENABLE) == 0)
1535                 return false;
1536         if (HAS_PCH_CPT(dev_priv->dev)) {
1537                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1538                         return false;
1539         } else {
1540                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1541                         return false;
1542         }
1543         return true;
1544 }
1545
1546 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1547                                    enum pipe pipe, i915_reg_t reg,
1548                                    u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              i915_mmio_reg_offset(reg), pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, i915_reg_t reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              i915_mmio_reg_offset(reg), pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         i915_reg_t reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         i915_reg_t reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /*
1717          * Apparently we need to have VGA mode enabled prior to changing
1718          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719          * dividers, even though the register value does change.
1720          */
1721         I915_WRITE(reg, 0);
1722
1723         I915_WRITE(reg, dpll);
1724
1725         /* Wait for the clocks to stabilize. */
1726         POSTING_READ(reg);
1727         udelay(150);
1728
1729         if (INTEL_INFO(dev)->gen >= 4) {
1730                 I915_WRITE(DPLL_MD(crtc->pipe),
1731                            crtc->config->dpll_hw_state.dpll_md);
1732         } else {
1733                 /* The pixel multiplier can only be updated once the
1734                  * DPLL is enabled and the clocks are stable.
1735                  *
1736                  * So write it again.
1737                  */
1738                 I915_WRITE(reg, dpll);
1739         }
1740
1741         /* We do this three times for luck */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748         I915_WRITE(reg, dpll);
1749         POSTING_READ(reg);
1750         udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754  * i9xx_disable_pll - disable a PLL
1755  * @dev_priv: i915 private structure
1756  * @pipe: pipe PLL to disable
1757  *
1758  * Disable the PLL for @pipe, making sure the pipe is off first.
1759  *
1760  * Note!  This is for pre-ILK only.
1761  */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->base.dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         enum pipe pipe = crtc->pipe;
1767
1768         /* Disable DVO 2x clock on both PLLs if necessary */
1769         if (IS_I830(dev) &&
1770             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771             !intel_num_dvo_pipes(dev)) {
1772                 I915_WRITE(DPLL(PIPE_B),
1773                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774                 I915_WRITE(DPLL(PIPE_A),
1775                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776         }
1777
1778         /* Don't disable pipe or pipe PLLs if needed */
1779         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781                 return;
1782
1783         /* Make sure the pipe isn't still relying on us */
1784         assert_pipe_disabled(dev_priv, pipe);
1785
1786         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787         POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792         u32 val;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         /*
1798          * Leave integrated clock source and reference clock enabled for pipe B.
1799          * The latter is needed for VGA hotplug / manual detection.
1800          */
1801         val = DPLL_VGA_MODE_DIS;
1802         if (pipe == PIPE_B)
1803                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804         I915_WRITE(DPLL(pipe), val);
1805         POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812         u32 val;
1813
1814         /* Make sure the pipe isn't still relying on us */
1815         assert_pipe_disabled(dev_priv, pipe);
1816
1817         /* Set PLL en = 0 */
1818         val = DPLL_SSC_REF_CLK_CHV |
1819                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820         if (pipe != PIPE_A)
1821                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822         I915_WRITE(DPLL(pipe), val);
1823         POSTING_READ(DPLL(pipe));
1824
1825         mutex_lock(&dev_priv->sb_lock);
1826
1827         /* Disable 10bit clock to display controller */
1828         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829         val &= ~DPIO_DCLKP_EN;
1830         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         i915_reg_t dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         if (INTEL_INFO(dev)->gen < 5)
1930                 return;
1931
1932         if (pll == NULL)
1933                 return;
1934
1935         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936                 return;
1937
1938         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939                       pll->name, pll->active, pll->on,
1940                       crtc->base.base.id);
1941
1942         if (WARN_ON(pll->active == 0)) {
1943                 assert_shared_dpll_disabled(dev_priv, pll);
1944                 return;
1945         }
1946
1947         assert_shared_dpll_enabled(dev_priv, pll);
1948         WARN_ON(!pll->on);
1949         if (--pll->active)
1950                 return;
1951
1952         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953         pll->disable(dev_priv, pll);
1954         pll->on = false;
1955
1956         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960                                            enum pipe pipe)
1961 {
1962         struct drm_device *dev = dev_priv->dev;
1963         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965         i915_reg_t reg;
1966         uint32_t val, pipeconf_val;
1967
1968         /* PCH only available on ILK+ */
1969         BUG_ON(!HAS_PCH_SPLIT(dev));
1970
1971         /* Make sure PCH DPLL is enabled */
1972         assert_shared_dpll_enabled(dev_priv,
1973                                    intel_crtc_to_shared_dpll(intel_crtc));
1974
1975         /* FDI must be feeding us bits for PCH ports */
1976         assert_fdi_tx_enabled(dev_priv, pipe);
1977         assert_fdi_rx_enabled(dev_priv, pipe);
1978
1979         if (HAS_PCH_CPT(dev)) {
1980                 /* Workaround: Set the timing override bit before enabling the
1981                  * pch transcoder. */
1982                 reg = TRANS_CHICKEN2(pipe);
1983                 val = I915_READ(reg);
1984                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1985                 I915_WRITE(reg, val);
1986         }
1987
1988         reg = PCH_TRANSCONF(pipe);
1989         val = I915_READ(reg);
1990         pipeconf_val = I915_READ(PIPECONF(pipe));
1991
1992         if (HAS_PCH_IBX(dev_priv->dev)) {
1993                 /*
1994                  * Make the BPC in transcoder be consistent with
1995                  * that in pipeconf reg. For HDMI we must use 8bpc
1996                  * here for both 8bpc and 12bpc.
1997                  */
1998                 val &= ~PIPECONF_BPC_MASK;
1999                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2000                         val |= PIPECONF_8BPC;
2001                 else
2002                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2003         }
2004
2005         val &= ~TRANS_INTERLACE_MASK;
2006         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2007                 if (HAS_PCH_IBX(dev_priv->dev) &&
2008                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2009                         val |= TRANS_LEGACY_INTERLACED_ILK;
2010                 else
2011                         val |= TRANS_INTERLACED;
2012         else
2013                 val |= TRANS_PROGRESSIVE;
2014
2015         I915_WRITE(reg, val | TRANS_ENABLE);
2016         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2017                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2018 }
2019
2020 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2021                                       enum transcoder cpu_transcoder)
2022 {
2023         u32 val, pipeconf_val;
2024
2025         /* PCH only available on ILK+ */
2026         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2027
2028         /* FDI must be feeding us bits for PCH ports */
2029         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2030         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2031
2032         /* Workaround: set timing override bit. */
2033         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2034         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2035         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2036
2037         val = TRANS_ENABLE;
2038         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2039
2040         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2041             PIPECONF_INTERLACED_ILK)
2042                 val |= TRANS_INTERLACED;
2043         else
2044                 val |= TRANS_PROGRESSIVE;
2045
2046         I915_WRITE(LPT_TRANSCONF, val);
2047         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2048                 DRM_ERROR("Failed to enable PCH transcoder\n");
2049 }
2050
2051 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2052                                             enum pipe pipe)
2053 {
2054         struct drm_device *dev = dev_priv->dev;
2055         i915_reg_t reg;
2056         uint32_t val;
2057
2058         /* FDI relies on the transcoder */
2059         assert_fdi_tx_disabled(dev_priv, pipe);
2060         assert_fdi_rx_disabled(dev_priv, pipe);
2061
2062         /* Ports must be off as well */
2063         assert_pch_ports_disabled(dev_priv, pipe);
2064
2065         reg = PCH_TRANSCONF(pipe);
2066         val = I915_READ(reg);
2067         val &= ~TRANS_ENABLE;
2068         I915_WRITE(reg, val);
2069         /* wait for PCH transcoder off, transcoder state */
2070         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2071                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2072
2073         if (HAS_PCH_CPT(dev)) {
2074                 /* Workaround: Clear the timing override chicken bit again. */
2075                 reg = TRANS_CHICKEN2(pipe);
2076                 val = I915_READ(reg);
2077                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2078                 I915_WRITE(reg, val);
2079         }
2080 }
2081
2082 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2083 {
2084         u32 val;
2085
2086         val = I915_READ(LPT_TRANSCONF);
2087         val &= ~TRANS_ENABLE;
2088         I915_WRITE(LPT_TRANSCONF, val);
2089         /* wait for PCH transcoder off, transcoder state */
2090         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2091                 DRM_ERROR("Failed to disable PCH transcoder\n");
2092
2093         /* Workaround: clear timing override bit. */
2094         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2095         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2096         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2097 }
2098
2099 /**
2100  * intel_enable_pipe - enable a pipe, asserting requirements
2101  * @crtc: crtc responsible for the pipe
2102  *
2103  * Enable @crtc's pipe, making sure that various hardware specific requirements
2104  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2105  */
2106 static void intel_enable_pipe(struct intel_crtc *crtc)
2107 {
2108         struct drm_device *dev = crtc->base.dev;
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         enum pipe pipe = crtc->pipe;
2111         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2112         enum pipe pch_transcoder;
2113         i915_reg_t reg;
2114         u32 val;
2115
2116         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2117
2118         assert_planes_disabled(dev_priv, pipe);
2119         assert_cursor_disabled(dev_priv, pipe);
2120         assert_sprites_disabled(dev_priv, pipe);
2121
2122         if (HAS_PCH_LPT(dev_priv->dev))
2123                 pch_transcoder = TRANSCODER_A;
2124         else
2125                 pch_transcoder = pipe;
2126
2127         /*
2128          * A pipe without a PLL won't actually be able to drive bits from
2129          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2130          * need the check.
2131          */
2132         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2133                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2134                         assert_dsi_pll_enabled(dev_priv);
2135                 else
2136                         assert_pll_enabled(dev_priv, pipe);
2137         else {
2138                 if (crtc->config->has_pch_encoder) {
2139                         /* if driving the PCH, we need FDI enabled */
2140                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2141                         assert_fdi_tx_pll_enabled(dev_priv,
2142                                                   (enum pipe) cpu_transcoder);
2143                 }
2144                 /* FIXME: assert CPU port conditions for SNB+ */
2145         }
2146
2147         reg = PIPECONF(cpu_transcoder);
2148         val = I915_READ(reg);
2149         if (val & PIPECONF_ENABLE) {
2150                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2151                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2152                 return;
2153         }
2154
2155         I915_WRITE(reg, val | PIPECONF_ENABLE);
2156         POSTING_READ(reg);
2157 }
2158
2159 /**
2160  * intel_disable_pipe - disable a pipe, asserting requirements
2161  * @crtc: crtc whose pipes is to be disabled
2162  *
2163  * Disable the pipe of @crtc, making sure that various hardware
2164  * specific requirements are met, if applicable, e.g. plane
2165  * disabled, panel fitter off, etc.
2166  *
2167  * Will wait until the pipe has shut down before returning.
2168  */
2169 static void intel_disable_pipe(struct intel_crtc *crtc)
2170 {
2171         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2172         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2173         enum pipe pipe = crtc->pipe;
2174         i915_reg_t reg;
2175         u32 val;
2176
2177         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2178
2179         /*
2180          * Make sure planes won't keep trying to pump pixels to us,
2181          * or we might hang the display.
2182          */
2183         assert_planes_disabled(dev_priv, pipe);
2184         assert_cursor_disabled(dev_priv, pipe);
2185         assert_sprites_disabled(dev_priv, pipe);
2186
2187         reg = PIPECONF(cpu_transcoder);
2188         val = I915_READ(reg);
2189         if ((val & PIPECONF_ENABLE) == 0)
2190                 return;
2191
2192         /*
2193          * Double wide has implications for planes
2194          * so best keep it disabled when not needed.
2195          */
2196         if (crtc->config->double_wide)
2197                 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199         /* Don't disable pipe or pipe PLLs if needed */
2200         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202                 val &= ~PIPECONF_ENABLE;
2203
2204         I915_WRITE(reg, val);
2205         if ((val & PIPECONF_ENABLE) == 0)
2206                 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 static bool need_vtd_wa(struct drm_device *dev)
2210 {
2211 #ifdef CONFIG_INTEL_IOMMU
2212         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2213                 return true;
2214 #endif
2215         return false;
2216 }
2217
2218 unsigned int
2219 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2220                   uint64_t fb_format_modifier, unsigned int plane)
2221 {
2222         unsigned int tile_height;
2223         uint32_t pixel_bytes;
2224
2225         switch (fb_format_modifier) {
2226         case DRM_FORMAT_MOD_NONE:
2227                 tile_height = 1;
2228                 break;
2229         case I915_FORMAT_MOD_X_TILED:
2230                 tile_height = IS_GEN2(dev) ? 16 : 8;
2231                 break;
2232         case I915_FORMAT_MOD_Y_TILED:
2233                 tile_height = 32;
2234                 break;
2235         case I915_FORMAT_MOD_Yf_TILED:
2236                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2237                 switch (pixel_bytes) {
2238                 default:
2239                 case 1:
2240                         tile_height = 64;
2241                         break;
2242                 case 2:
2243                 case 4:
2244                         tile_height = 32;
2245                         break;
2246                 case 8:
2247                         tile_height = 16;
2248                         break;
2249                 case 16:
2250                         WARN_ONCE(1,
2251                                   "128-bit pixels are not supported for display!");
2252                         tile_height = 16;
2253                         break;
2254                 }
2255                 break;
2256         default:
2257                 MISSING_CASE(fb_format_modifier);
2258                 tile_height = 1;
2259                 break;
2260         }
2261
2262         return tile_height;
2263 }
2264
2265 unsigned int
2266 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2267                       uint32_t pixel_format, uint64_t fb_format_modifier)
2268 {
2269         return ALIGN(height, intel_tile_height(dev, pixel_format,
2270                                                fb_format_modifier, 0));
2271 }
2272
2273 static void
2274 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2275                         const struct drm_plane_state *plane_state)
2276 {
2277         struct intel_rotation_info *info = &view->params.rotation_info;
2278         unsigned int tile_height, tile_pitch;
2279
2280         *view = i915_ggtt_view_normal;
2281
2282         if (!plane_state)
2283                 return;
2284
2285         if (!intel_rotation_90_or_270(plane_state->rotation))
2286                 return;
2287
2288         *view = i915_ggtt_view_rotated;
2289
2290         info->height = fb->height;
2291         info->pixel_format = fb->pixel_format;
2292         info->pitch = fb->pitches[0];
2293         info->uv_offset = fb->offsets[1];
2294         info->fb_modifier = fb->modifier[0];
2295
2296         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2297                                         fb->modifier[0], 0);
2298         tile_pitch = PAGE_SIZE / tile_height;
2299         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2300         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2301         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2302
2303         if (info->pixel_format == DRM_FORMAT_NV12) {
2304                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305                                                 fb->modifier[0], 1);
2306                 tile_pitch = PAGE_SIZE / tile_height;
2307                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2309                                                      tile_height);
2310                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2311                                 PAGE_SIZE;
2312         }
2313 }
2314
2315 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2316 {
2317         if (INTEL_INFO(dev_priv)->gen >= 9)
2318                 return 256 * 1024;
2319         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2320                  IS_VALLEYVIEW(dev_priv))
2321                 return 128 * 1024;
2322         else if (INTEL_INFO(dev_priv)->gen >= 4)
2323                 return 4 * 1024;
2324         else
2325                 return 0;
2326 }
2327
2328 int
2329 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2330                            struct drm_framebuffer *fb,
2331                            const struct drm_plane_state *plane_state)
2332 {
2333         struct drm_device *dev = fb->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2336         struct i915_ggtt_view view;
2337         u32 alignment;
2338         int ret;
2339
2340         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341
2342         switch (fb->modifier[0]) {
2343         case DRM_FORMAT_MOD_NONE:
2344                 alignment = intel_linear_alignment(dev_priv);
2345                 break;
2346         case I915_FORMAT_MOD_X_TILED:
2347                 if (INTEL_INFO(dev)->gen >= 9)
2348                         alignment = 256 * 1024;
2349                 else {
2350                         /* pin() will align the object as required by fence */
2351                         alignment = 0;
2352                 }
2353                 break;
2354         case I915_FORMAT_MOD_Y_TILED:
2355         case I915_FORMAT_MOD_Yf_TILED:
2356                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2357                           "Y tiling bo slipped through, driver bug!\n"))
2358                         return -EINVAL;
2359                 alignment = 1 * 1024 * 1024;
2360                 break;
2361         default:
2362                 MISSING_CASE(fb->modifier[0]);
2363                 return -EINVAL;
2364         }
2365
2366         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2367
2368         /* Note that the w/a also requires 64 PTE of padding following the
2369          * bo. We currently fill all unused PTE with the shadow page and so
2370          * we should always have valid PTE following the scanout preventing
2371          * the VT-d warning.
2372          */
2373         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2374                 alignment = 256 * 1024;
2375
2376         /*
2377          * Global gtt pte registers are special registers which actually forward
2378          * writes to a chunk of system memory. Which means that there is no risk
2379          * that the register values disappear as soon as we call
2380          * intel_runtime_pm_put(), so it is correct to wrap only the
2381          * pin/unpin/fence and not more.
2382          */
2383         intel_runtime_pm_get(dev_priv);
2384
2385         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2386                                                    &view);
2387         if (ret)
2388                 goto err_pm;
2389
2390         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2391          * fence, whereas 965+ only requires a fence if using
2392          * framebuffer compression.  For simplicity, we always install
2393          * a fence as the cost is not that onerous.
2394          */
2395         if (view.type == I915_GGTT_VIEW_NORMAL) {
2396                 ret = i915_gem_object_get_fence(obj);
2397                 if (ret == -EDEADLK) {
2398                         /*
2399                          * -EDEADLK means there are no free fences
2400                          * no pending flips.
2401                          *
2402                          * This is propagated to atomic, but it uses
2403                          * -EDEADLK to force a locking recovery, so
2404                          * change the returned error to -EBUSY.
2405                          */
2406                         ret = -EBUSY;
2407                         goto err_unpin;
2408                 } else if (ret)
2409                         goto err_unpin;
2410
2411                 i915_gem_object_pin_fence(obj);
2412         }
2413
2414         intel_runtime_pm_put(dev_priv);
2415         return 0;
2416
2417 err_unpin:
2418         i915_gem_object_unpin_from_display_plane(obj, &view);
2419 err_pm:
2420         intel_runtime_pm_put(dev_priv);
2421         return ret;
2422 }
2423
2424 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425                                const struct drm_plane_state *plane_state)
2426 {
2427         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428         struct i915_ggtt_view view;
2429
2430         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
2432         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433
2434         if (view.type == I915_GGTT_VIEW_NORMAL)
2435                 i915_gem_object_unpin_fence(obj);
2436
2437         i915_gem_object_unpin_from_display_plane(obj, &view);
2438 }
2439
2440 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441  * is assumed to be a power-of-two. */
2442 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2443                                              int *x, int *y,
2444                                              unsigned int tiling_mode,
2445                                              unsigned int cpp,
2446                                              unsigned int pitch)
2447 {
2448         if (tiling_mode != I915_TILING_NONE) {
2449                 unsigned int tile_rows, tiles;
2450
2451                 tile_rows = *y / 8;
2452                 *y %= 8;
2453
2454                 tiles = *x / (512/cpp);
2455                 *x %= 512/cpp;
2456
2457                 return tile_rows * pitch * 8 + tiles * 4096;
2458         } else {
2459                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2460                 unsigned int offset;
2461
2462                 offset = *y * pitch + *x * cpp;
2463                 *y = (offset & alignment) / pitch;
2464                 *x = ((offset & alignment) - *y * pitch) / cpp;
2465                 return offset & ~alignment;
2466         }
2467 }
2468
2469 static int i9xx_format_to_fourcc(int format)
2470 {
2471         switch (format) {
2472         case DISPPLANE_8BPP:
2473                 return DRM_FORMAT_C8;
2474         case DISPPLANE_BGRX555:
2475                 return DRM_FORMAT_XRGB1555;
2476         case DISPPLANE_BGRX565:
2477                 return DRM_FORMAT_RGB565;
2478         default:
2479         case DISPPLANE_BGRX888:
2480                 return DRM_FORMAT_XRGB8888;
2481         case DISPPLANE_RGBX888:
2482                 return DRM_FORMAT_XBGR8888;
2483         case DISPPLANE_BGRX101010:
2484                 return DRM_FORMAT_XRGB2101010;
2485         case DISPPLANE_RGBX101010:
2486                 return DRM_FORMAT_XBGR2101010;
2487         }
2488 }
2489
2490 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2491 {
2492         switch (format) {
2493         case PLANE_CTL_FORMAT_RGB_565:
2494                 return DRM_FORMAT_RGB565;
2495         default:
2496         case PLANE_CTL_FORMAT_XRGB_8888:
2497                 if (rgb_order) {
2498                         if (alpha)
2499                                 return DRM_FORMAT_ABGR8888;
2500                         else
2501                                 return DRM_FORMAT_XBGR8888;
2502                 } else {
2503                         if (alpha)
2504                                 return DRM_FORMAT_ARGB8888;
2505                         else
2506                                 return DRM_FORMAT_XRGB8888;
2507                 }
2508         case PLANE_CTL_FORMAT_XRGB_2101010:
2509                 if (rgb_order)
2510                         return DRM_FORMAT_XBGR2101010;
2511                 else
2512                         return DRM_FORMAT_XRGB2101010;
2513         }
2514 }
2515
2516 static bool
2517 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2518                               struct intel_initial_plane_config *plane_config)
2519 {
2520         struct drm_device *dev = crtc->base.dev;
2521         struct drm_i915_private *dev_priv = to_i915(dev);
2522         struct drm_i915_gem_object *obj = NULL;
2523         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2524         struct drm_framebuffer *fb = &plane_config->fb->base;
2525         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2526         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2527                                     PAGE_SIZE);
2528
2529         size_aligned -= base_aligned;
2530
2531         if (plane_config->size == 0)
2532                 return false;
2533
2534         /* If the FB is too big, just don't use it since fbdev is not very
2535          * important and we should probably use that space with FBC or other
2536          * features. */
2537         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2538                 return false;
2539
2540         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541                                                              base_aligned,
2542                                                              base_aligned,
2543                                                              size_aligned);
2544         if (!obj)
2545                 return false;
2546
2547         obj->tiling_mode = plane_config->tiling;
2548         if (obj->tiling_mode == I915_TILING_X)
2549                 obj->stride = fb->pitches[0];
2550
2551         mode_cmd.pixel_format = fb->pixel_format;
2552         mode_cmd.width = fb->width;
2553         mode_cmd.height = fb->height;
2554         mode_cmd.pitches[0] = fb->pitches[0];
2555         mode_cmd.modifier[0] = fb->modifier[0];
2556         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558         mutex_lock(&dev->struct_mutex);
2559         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560                                    &mode_cmd, obj)) {
2561                 DRM_DEBUG_KMS("intel fb init failed\n");
2562                 goto out_unref_obj;
2563         }
2564         mutex_unlock(&dev->struct_mutex);
2565
2566         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567         return true;
2568
2569 out_unref_obj:
2570         drm_gem_object_unreference(&obj->base);
2571         mutex_unlock(&dev->struct_mutex);
2572         return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579         if (plane->fb == plane->state->fb)
2580                 return;
2581
2582         if (plane->state->fb)
2583                 drm_framebuffer_unreference(plane->state->fb);
2584         plane->state->fb = plane->fb;
2585         if (plane->state->fb)
2586                 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591                              struct intel_initial_plane_config *plane_config)
2592 {
2593         struct drm_device *dev = intel_crtc->base.dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct drm_crtc *c;
2596         struct intel_crtc *i;
2597         struct drm_i915_gem_object *obj;
2598         struct drm_plane *primary = intel_crtc->base.primary;
2599         struct drm_plane_state *plane_state = primary->state;
2600         struct drm_framebuffer *fb;
2601
2602         if (!plane_config->fb)
2603                 return;
2604
2605         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2606                 fb = &plane_config->fb->base;
2607                 goto valid_fb;
2608         }
2609
2610         kfree(plane_config->fb);
2611
2612         /*
2613          * Failed to alloc the obj, check to see if we should share
2614          * an fb with another CRTC instead
2615          */
2616         for_each_crtc(dev, c) {
2617                 i = to_intel_crtc(c);
2618
2619                 if (c == &intel_crtc->base)
2620                         continue;
2621
2622                 if (!i->active)
2623                         continue;
2624
2625                 fb = c->primary->fb;
2626                 if (!fb)
2627                         continue;
2628
2629                 obj = intel_fb_obj(fb);
2630                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2631                         drm_framebuffer_reference(fb);
2632                         goto valid_fb;
2633                 }
2634         }
2635
2636         return;
2637
2638 valid_fb:
2639         plane_state->src_x = 0;
2640         plane_state->src_y = 0;
2641         plane_state->src_w = fb->width << 16;
2642         plane_state->src_h = fb->height << 16;
2643
2644         plane_state->crtc_x = 0;
2645         plane_state->crtc_y = 0;
2646         plane_state->crtc_w = fb->width;
2647         plane_state->crtc_h = fb->height;
2648
2649         obj = intel_fb_obj(fb);
2650         if (obj->tiling_mode != I915_TILING_NONE)
2651                 dev_priv->preserve_bios_swizzle = true;
2652
2653         drm_framebuffer_reference(fb);
2654         primary->fb = primary->state->fb = fb;
2655         primary->crtc = primary->state->crtc = &intel_crtc->base;
2656         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2657         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658 }
2659
2660 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2661                                       struct drm_framebuffer *fb,
2662                                       int x, int y)
2663 {
2664         struct drm_device *dev = crtc->dev;
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667         struct drm_plane *primary = crtc->primary;
2668         bool visible = to_intel_plane_state(primary->state)->visible;
2669         struct drm_i915_gem_object *obj;
2670         int plane = intel_crtc->plane;
2671         unsigned long linear_offset;
2672         u32 dspcntr;
2673         i915_reg_t reg = DSPCNTR(plane);
2674         int pixel_size;
2675
2676         if (!visible || !fb) {
2677                 I915_WRITE(reg, 0);
2678                 if (INTEL_INFO(dev)->gen >= 4)
2679                         I915_WRITE(DSPSURF(plane), 0);
2680                 else
2681                         I915_WRITE(DSPADDR(plane), 0);
2682                 POSTING_READ(reg);
2683                 return;
2684         }
2685
2686         obj = intel_fb_obj(fb);
2687         if (WARN_ON(obj == NULL))
2688                 return;
2689
2690         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2691
2692         dspcntr = DISPPLANE_GAMMA_ENABLE;
2693
2694         dspcntr |= DISPLAY_PLANE_ENABLE;
2695
2696         if (INTEL_INFO(dev)->gen < 4) {
2697                 if (intel_crtc->pipe == PIPE_B)
2698                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2699
2700                 /* pipesrc and dspsize control the size that is scaled from,
2701                  * which should always be the user's requested size.
2702                  */
2703                 I915_WRITE(DSPSIZE(plane),
2704                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705                            (intel_crtc->config->pipe_src_w - 1));
2706                 I915_WRITE(DSPPOS(plane), 0);
2707         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2708                 I915_WRITE(PRIMSIZE(plane),
2709                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2710                            (intel_crtc->config->pipe_src_w - 1));
2711                 I915_WRITE(PRIMPOS(plane), 0);
2712                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2713         }
2714
2715         switch (fb->pixel_format) {
2716         case DRM_FORMAT_C8:
2717                 dspcntr |= DISPPLANE_8BPP;
2718                 break;
2719         case DRM_FORMAT_XRGB1555:
2720                 dspcntr |= DISPPLANE_BGRX555;
2721                 break;
2722         case DRM_FORMAT_RGB565:
2723                 dspcntr |= DISPPLANE_BGRX565;
2724                 break;
2725         case DRM_FORMAT_XRGB8888:
2726                 dspcntr |= DISPPLANE_BGRX888;
2727                 break;
2728         case DRM_FORMAT_XBGR8888:
2729                 dspcntr |= DISPPLANE_RGBX888;
2730                 break;
2731         case DRM_FORMAT_XRGB2101010:
2732                 dspcntr |= DISPPLANE_BGRX101010;
2733                 break;
2734         case DRM_FORMAT_XBGR2101010:
2735                 dspcntr |= DISPPLANE_RGBX101010;
2736                 break;
2737         default:
2738                 BUG();
2739         }
2740
2741         if (INTEL_INFO(dev)->gen >= 4 &&
2742             obj->tiling_mode != I915_TILING_NONE)
2743                 dspcntr |= DISPPLANE_TILED;
2744
2745         if (IS_G4X(dev))
2746                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2747
2748         linear_offset = y * fb->pitches[0] + x * pixel_size;
2749
2750         if (INTEL_INFO(dev)->gen >= 4) {
2751                 intel_crtc->dspaddr_offset =
2752                         intel_gen4_compute_page_offset(dev_priv,
2753                                                        &x, &y, obj->tiling_mode,
2754                                                        pixel_size,
2755                                                        fb->pitches[0]);
2756                 linear_offset -= intel_crtc->dspaddr_offset;
2757         } else {
2758                 intel_crtc->dspaddr_offset = linear_offset;
2759         }
2760
2761         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2762                 dspcntr |= DISPPLANE_ROTATE_180;
2763
2764                 x += (intel_crtc->config->pipe_src_w - 1);
2765                 y += (intel_crtc->config->pipe_src_h - 1);
2766
2767                 /* Finding the last pixel of the last line of the display
2768                 data and adding to linear_offset*/
2769                 linear_offset +=
2770                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2772         }
2773
2774         intel_crtc->adjusted_x = x;
2775         intel_crtc->adjusted_y = y;
2776
2777         I915_WRITE(reg, dspcntr);
2778
2779         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2780         if (INTEL_INFO(dev)->gen >= 4) {
2781                 I915_WRITE(DSPSURF(plane),
2782                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2783                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2784                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2785         } else
2786                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2787         POSTING_READ(reg);
2788 }
2789
2790 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2791                                           struct drm_framebuffer *fb,
2792                                           int x, int y)
2793 {
2794         struct drm_device *dev = crtc->dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797         struct drm_plane *primary = crtc->primary;
2798         bool visible = to_intel_plane_state(primary->state)->visible;
2799         struct drm_i915_gem_object *obj;
2800         int plane = intel_crtc->plane;
2801         unsigned long linear_offset;
2802         u32 dspcntr;
2803         i915_reg_t reg = DSPCNTR(plane);
2804         int pixel_size;
2805
2806         if (!visible || !fb) {
2807                 I915_WRITE(reg, 0);
2808                 I915_WRITE(DSPSURF(plane), 0);
2809                 POSTING_READ(reg);
2810                 return;
2811         }
2812
2813         obj = intel_fb_obj(fb);
2814         if (WARN_ON(obj == NULL))
2815                 return;
2816
2817         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
2819         dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
2821         dspcntr |= DISPLAY_PLANE_ENABLE;
2822
2823         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2825
2826         switch (fb->pixel_format) {
2827         case DRM_FORMAT_C8:
2828                 dspcntr |= DISPPLANE_8BPP;
2829                 break;
2830         case DRM_FORMAT_RGB565:
2831                 dspcntr |= DISPPLANE_BGRX565;
2832                 break;
2833         case DRM_FORMAT_XRGB8888:
2834                 dspcntr |= DISPPLANE_BGRX888;
2835                 break;
2836         case DRM_FORMAT_XBGR8888:
2837                 dspcntr |= DISPPLANE_RGBX888;
2838                 break;
2839         case DRM_FORMAT_XRGB2101010:
2840                 dspcntr |= DISPPLANE_BGRX101010;
2841                 break;
2842         case DRM_FORMAT_XBGR2101010:
2843                 dspcntr |= DISPPLANE_RGBX101010;
2844                 break;
2845         default:
2846                 BUG();
2847         }
2848
2849         if (obj->tiling_mode != I915_TILING_NONE)
2850                 dspcntr |= DISPPLANE_TILED;
2851
2852         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2853                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2854
2855         linear_offset = y * fb->pitches[0] + x * pixel_size;
2856         intel_crtc->dspaddr_offset =
2857                 intel_gen4_compute_page_offset(dev_priv,
2858                                                &x, &y, obj->tiling_mode,
2859                                                pixel_size,
2860                                                fb->pitches[0]);
2861         linear_offset -= intel_crtc->dspaddr_offset;
2862         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2863                 dspcntr |= DISPPLANE_ROTATE_180;
2864
2865                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2866                         x += (intel_crtc->config->pipe_src_w - 1);
2867                         y += (intel_crtc->config->pipe_src_h - 1);
2868
2869                         /* Finding the last pixel of the last line of the display
2870                         data and adding to linear_offset*/
2871                         linear_offset +=
2872                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2873                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2874                 }
2875         }
2876
2877         intel_crtc->adjusted_x = x;
2878         intel_crtc->adjusted_y = y;
2879
2880         I915_WRITE(reg, dspcntr);
2881
2882         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2883         I915_WRITE(DSPSURF(plane),
2884                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2885         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2886                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887         } else {
2888                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890         }
2891         POSTING_READ(reg);
2892 }
2893
2894 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895                               uint32_t pixel_format)
2896 {
2897         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899         /*
2900          * The stride is either expressed as a multiple of 64 bytes
2901          * chunks for linear buffers or in number of tiles for tiled
2902          * buffers.
2903          */
2904         switch (fb_modifier) {
2905         case DRM_FORMAT_MOD_NONE:
2906                 return 64;
2907         case I915_FORMAT_MOD_X_TILED:
2908                 if (INTEL_INFO(dev)->gen == 2)
2909                         return 128;
2910                 return 512;
2911         case I915_FORMAT_MOD_Y_TILED:
2912                 /* No need to check for old gens and Y tiling since this is
2913                  * about the display engine and those will be blocked before
2914                  * we get here.
2915                  */
2916                 return 128;
2917         case I915_FORMAT_MOD_Yf_TILED:
2918                 if (bits_per_pixel == 8)
2919                         return 64;
2920                 else
2921                         return 128;
2922         default:
2923                 MISSING_CASE(fb_modifier);
2924                 return 64;
2925         }
2926 }
2927
2928 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2929                            struct drm_i915_gem_object *obj,
2930                            unsigned int plane)
2931 {
2932         struct i915_ggtt_view view;
2933         struct i915_vma *vma;
2934         u64 offset;
2935
2936         intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2937                                 intel_plane->base.state);
2938
2939         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2940         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2941                 view.type))
2942                 return -1;
2943
2944         offset = vma->node.start;
2945
2946         if (plane == 1) {
2947                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2948                           PAGE_SIZE;
2949         }
2950
2951         WARN_ON(upper_32_bits(offset));
2952
2953         return lower_32_bits(offset);
2954 }
2955
2956 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2957 {
2958         struct drm_device *dev = intel_crtc->base.dev;
2959         struct drm_i915_private *dev_priv = dev->dev_private;
2960
2961         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2962         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2963         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2964 }
2965
2966 /*
2967  * This function detaches (aka. unbinds) unused scalers in hardware
2968  */
2969 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2970 {
2971         struct intel_crtc_scaler_state *scaler_state;
2972         int i;
2973
2974         scaler_state = &intel_crtc->config->scaler_state;
2975
2976         /* loop through and disable scalers that aren't in use */
2977         for (i = 0; i < intel_crtc->num_scalers; i++) {
2978                 if (!scaler_state->scalers[i].in_use)
2979                         skl_detach_scaler(intel_crtc, i);
2980         }
2981 }
2982
2983 u32 skl_plane_ctl_format(uint32_t pixel_format)
2984 {
2985         switch (pixel_format) {
2986         case DRM_FORMAT_C8:
2987                 return PLANE_CTL_FORMAT_INDEXED;
2988         case DRM_FORMAT_RGB565:
2989                 return PLANE_CTL_FORMAT_RGB_565;
2990         case DRM_FORMAT_XBGR8888:
2991                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2992         case DRM_FORMAT_XRGB8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888;
2994         /*
2995          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2996          * to be already pre-multiplied. We need to add a knob (or a different
2997          * DRM_FORMAT) for user-space to configure that.
2998          */
2999         case DRM_FORMAT_ABGR8888:
3000                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3001                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3002         case DRM_FORMAT_ARGB8888:
3003                 return PLANE_CTL_FORMAT_XRGB_8888 |
3004                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3005         case DRM_FORMAT_XRGB2101010:
3006                 return PLANE_CTL_FORMAT_XRGB_2101010;
3007         case DRM_FORMAT_XBGR2101010:
3008                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3009         case DRM_FORMAT_YUYV:
3010                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3011         case DRM_FORMAT_YVYU:
3012                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3013         case DRM_FORMAT_UYVY:
3014                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3015         case DRM_FORMAT_VYUY:
3016                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3017         default:
3018                 MISSING_CASE(pixel_format);
3019         }
3020
3021         return 0;
3022 }
3023
3024 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3025 {
3026         switch (fb_modifier) {
3027         case DRM_FORMAT_MOD_NONE:
3028                 break;
3029         case I915_FORMAT_MOD_X_TILED:
3030                 return PLANE_CTL_TILED_X;
3031         case I915_FORMAT_MOD_Y_TILED:
3032                 return PLANE_CTL_TILED_Y;
3033         case I915_FORMAT_MOD_Yf_TILED:
3034                 return PLANE_CTL_TILED_YF;
3035         default:
3036                 MISSING_CASE(fb_modifier);
3037         }
3038
3039         return 0;
3040 }
3041
3042 u32 skl_plane_ctl_rotation(unsigned int rotation)
3043 {
3044         switch (rotation) {
3045         case BIT(DRM_ROTATE_0):
3046                 break;
3047         /*
3048          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3049          * while i915 HW rotation is clockwise, thats why this swapping.
3050          */
3051         case BIT(DRM_ROTATE_90):
3052                 return PLANE_CTL_ROTATE_270;
3053         case BIT(DRM_ROTATE_180):
3054                 return PLANE_CTL_ROTATE_180;
3055         case BIT(DRM_ROTATE_270):
3056                 return PLANE_CTL_ROTATE_90;
3057         default:
3058                 MISSING_CASE(rotation);
3059         }
3060
3061         return 0;
3062 }
3063
3064 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3065                                          struct drm_framebuffer *fb,
3066                                          int x, int y)
3067 {
3068         struct drm_device *dev = crtc->dev;
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071         struct drm_plane *plane = crtc->primary;
3072         bool visible = to_intel_plane_state(plane->state)->visible;
3073         struct drm_i915_gem_object *obj;
3074         int pipe = intel_crtc->pipe;
3075         u32 plane_ctl, stride_div, stride;
3076         u32 tile_height, plane_offset, plane_size;
3077         unsigned int rotation;
3078         int x_offset, y_offset;
3079         u32 surf_addr;
3080         struct intel_crtc_state *crtc_state = intel_crtc->config;
3081         struct intel_plane_state *plane_state;
3082         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3083         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3084         int scaler_id = -1;
3085
3086         plane_state = to_intel_plane_state(plane->state);
3087
3088         if (!visible || !fb) {
3089                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3090                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3091                 POSTING_READ(PLANE_CTL(pipe, 0));
3092                 return;
3093         }
3094
3095         plane_ctl = PLANE_CTL_ENABLE |
3096                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3097                     PLANE_CTL_PIPE_CSC_ENABLE;
3098
3099         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3100         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3101         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3102
3103         rotation = plane->state->rotation;
3104         plane_ctl |= skl_plane_ctl_rotation(rotation);
3105
3106         obj = intel_fb_obj(fb);
3107         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3108                                                fb->pixel_format);
3109         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3110
3111         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3112
3113         scaler_id = plane_state->scaler_id;
3114         src_x = plane_state->src.x1 >> 16;
3115         src_y = plane_state->src.y1 >> 16;
3116         src_w = drm_rect_width(&plane_state->src) >> 16;
3117         src_h = drm_rect_height(&plane_state->src) >> 16;
3118         dst_x = plane_state->dst.x1;
3119         dst_y = plane_state->dst.y1;
3120         dst_w = drm_rect_width(&plane_state->dst);
3121         dst_h = drm_rect_height(&plane_state->dst);
3122
3123         WARN_ON(x != src_x || y != src_y);
3124
3125         if (intel_rotation_90_or_270(rotation)) {
3126                 /* stride = Surface height in tiles */
3127                 tile_height = intel_tile_height(dev, fb->pixel_format,
3128                                                 fb->modifier[0], 0);
3129                 stride = DIV_ROUND_UP(fb->height, tile_height);
3130                 x_offset = stride * tile_height - y - src_h;
3131                 y_offset = x;
3132                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3133         } else {
3134                 stride = fb->pitches[0] / stride_div;
3135                 x_offset = x;
3136                 y_offset = y;
3137                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3138         }
3139         plane_offset = y_offset << 16 | x_offset;
3140
3141         intel_crtc->adjusted_x = x_offset;
3142         intel_crtc->adjusted_y = y_offset;
3143
3144         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3145         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3146         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3147         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3148
3149         if (scaler_id >= 0) {
3150                 uint32_t ps_ctrl = 0;
3151
3152                 WARN_ON(!dst_w || !dst_h);
3153                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3154                         crtc_state->scaler_state.scalers[scaler_id].mode;
3155                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3156                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3157                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3158                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3159                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3160         } else {
3161                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3162         }
3163
3164         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3165
3166         POSTING_READ(PLANE_SURF(pipe, 0));
3167 }
3168
3169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3170 static int
3171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3172                            int x, int y, enum mode_set_atomic state)
3173 {
3174         struct drm_device *dev = crtc->dev;
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176
3177         if (dev_priv->fbc.disable_fbc)
3178                 dev_priv->fbc.disable_fbc(dev_priv);
3179
3180         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3181
3182         return 0;
3183 }
3184
3185 static void intel_complete_page_flips(struct drm_device *dev)
3186 {
3187         struct drm_crtc *crtc;
3188
3189         for_each_crtc(dev, crtc) {
3190                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3191                 enum plane plane = intel_crtc->plane;
3192
3193                 intel_prepare_page_flip(dev, plane);
3194                 intel_finish_page_flip_plane(dev, plane);
3195         }
3196 }
3197
3198 static void intel_update_primary_planes(struct drm_device *dev)
3199 {
3200         struct drm_crtc *crtc;
3201
3202         for_each_crtc(dev, crtc) {
3203                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3204                 struct intel_plane_state *plane_state;
3205
3206                 drm_modeset_lock_crtc(crtc, &plane->base);
3207                 plane_state = to_intel_plane_state(plane->base.state);
3208
3209                 if (crtc->state->active && plane_state->base.fb)
3210                         plane->commit_plane(&plane->base, plane_state);
3211
3212                 drm_modeset_unlock_crtc(crtc);
3213         }
3214 }
3215
3216 void intel_prepare_reset(struct drm_device *dev)
3217 {
3218         /* no reset support for gen2 */
3219         if (IS_GEN2(dev))
3220                 return;
3221
3222         /* reset doesn't touch the display */
3223         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3224                 return;
3225
3226         drm_modeset_lock_all(dev);
3227         /*
3228          * Disabling the crtcs gracefully seems nicer. Also the
3229          * g33 docs say we should at least disable all the planes.
3230          */
3231         intel_display_suspend(dev);
3232 }
3233
3234 void intel_finish_reset(struct drm_device *dev)
3235 {
3236         struct drm_i915_private *dev_priv = to_i915(dev);
3237
3238         /*
3239          * Flips in the rings will be nuked by the reset,
3240          * so complete all pending flips so that user space
3241          * will get its events and not get stuck.
3242          */
3243         intel_complete_page_flips(dev);
3244
3245         /* no reset support for gen2 */
3246         if (IS_GEN2(dev))
3247                 return;
3248
3249         /* reset doesn't touch the display */
3250         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3251                 /*
3252                  * Flips in the rings have been nuked by the reset,
3253                  * so update the base address of all primary
3254                  * planes to the the last fb to make sure we're
3255                  * showing the correct fb after a reset.
3256                  *
3257                  * FIXME: Atomic will make this obsolete since we won't schedule
3258                  * CS-based flips (which might get lost in gpu resets) any more.
3259                  */
3260                 intel_update_primary_planes(dev);
3261                 return;
3262         }
3263
3264         /*
3265          * The display has been reset as well,
3266          * so need a full re-initialization.
3267          */
3268         intel_runtime_pm_disable_interrupts(dev_priv);
3269         intel_runtime_pm_enable_interrupts(dev_priv);
3270
3271         intel_modeset_init_hw(dev);
3272
3273         spin_lock_irq(&dev_priv->irq_lock);
3274         if (dev_priv->display.hpd_irq_setup)
3275                 dev_priv->display.hpd_irq_setup(dev);
3276         spin_unlock_irq(&dev_priv->irq_lock);
3277
3278         intel_display_resume(dev);
3279
3280         intel_hpd_init(dev_priv);
3281
3282         drm_modeset_unlock_all(dev);
3283 }
3284
3285 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3286 {
3287         struct drm_device *dev = crtc->dev;
3288         struct drm_i915_private *dev_priv = dev->dev_private;
3289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290         bool pending;
3291
3292         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3293             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3294                 return false;
3295
3296         spin_lock_irq(&dev->event_lock);
3297         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3298         spin_unlock_irq(&dev->event_lock);
3299
3300         return pending;
3301 }
3302
3303 static void intel_update_pipe_config(struct intel_crtc *crtc,
3304                                      struct intel_crtc_state *old_crtc_state)
3305 {
3306         struct drm_device *dev = crtc->base.dev;
3307         struct drm_i915_private *dev_priv = dev->dev_private;
3308         struct intel_crtc_state *pipe_config =
3309                 to_intel_crtc_state(crtc->base.state);
3310
3311         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3312         crtc->base.mode = crtc->base.state->mode;
3313
3314         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3315                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3316                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3317
3318         if (HAS_DDI(dev))
3319                 intel_set_pipe_csc(&crtc->base);
3320
3321         /*
3322          * Update pipe size and adjust fitter if needed: the reason for this is
3323          * that in compute_mode_changes we check the native mode (not the pfit
3324          * mode) to see if we can flip rather than do a full mode set. In the
3325          * fastboot case, we'll flip, but if we don't update the pipesrc and
3326          * pfit state, we'll end up with a big fb scanned out into the wrong
3327          * sized surface.
3328          */
3329
3330         I915_WRITE(PIPESRC(crtc->pipe),
3331                    ((pipe_config->pipe_src_w - 1) << 16) |
3332                    (pipe_config->pipe_src_h - 1));
3333
3334         /* on skylake this is done by detaching scalers */
3335         if (INTEL_INFO(dev)->gen >= 9) {
3336                 skl_detach_scalers(crtc);
3337
3338                 if (pipe_config->pch_pfit.enabled)
3339                         skylake_pfit_enable(crtc);
3340         } else if (HAS_PCH_SPLIT(dev)) {
3341                 if (pipe_config->pch_pfit.enabled)
3342                         ironlake_pfit_enable(crtc);
3343                 else if (old_crtc_state->pch_pfit.enabled)
3344                         ironlake_pfit_disable(crtc, true);
3345         }
3346 }
3347
3348 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3349 {
3350         struct drm_device *dev = crtc->dev;
3351         struct drm_i915_private *dev_priv = dev->dev_private;
3352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353         int pipe = intel_crtc->pipe;
3354         i915_reg_t reg;
3355         u32 temp;
3356
3357         /* enable normal train */
3358         reg = FDI_TX_CTL(pipe);
3359         temp = I915_READ(reg);
3360         if (IS_IVYBRIDGE(dev)) {
3361                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3362                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3363         } else {
3364                 temp &= ~FDI_LINK_TRAIN_NONE;
3365                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3366         }
3367         I915_WRITE(reg, temp);
3368
3369         reg = FDI_RX_CTL(pipe);
3370         temp = I915_READ(reg);
3371         if (HAS_PCH_CPT(dev)) {
3372                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3373                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3374         } else {
3375                 temp &= ~FDI_LINK_TRAIN_NONE;
3376                 temp |= FDI_LINK_TRAIN_NONE;
3377         }
3378         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3379
3380         /* wait one idle pattern time */
3381         POSTING_READ(reg);
3382         udelay(1000);
3383
3384         /* IVB wants error correction enabled */
3385         if (IS_IVYBRIDGE(dev))
3386                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3387                            FDI_FE_ERRC_ENABLE);
3388 }
3389
3390 /* The FDI link training functions for ILK/Ibexpeak. */
3391 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         int pipe = intel_crtc->pipe;
3397         i915_reg_t reg;
3398         u32 temp, tries;
3399
3400         /* FDI needs bits from pipe first */
3401         assert_pipe_enabled(dev_priv, pipe);
3402
3403         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404            for train result */
3405         reg = FDI_RX_IMR(pipe);
3406         temp = I915_READ(reg);
3407         temp &= ~FDI_RX_SYMBOL_LOCK;
3408         temp &= ~FDI_RX_BIT_LOCK;
3409         I915_WRITE(reg, temp);
3410         I915_READ(reg);
3411         udelay(150);
3412
3413         /* enable CPU FDI TX and PCH FDI RX */
3414         reg = FDI_TX_CTL(pipe);
3415         temp = I915_READ(reg);
3416         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3417         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3418         temp &= ~FDI_LINK_TRAIN_NONE;
3419         temp |= FDI_LINK_TRAIN_PATTERN_1;
3420         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3421
3422         reg = FDI_RX_CTL(pipe);
3423         temp = I915_READ(reg);
3424         temp &= ~FDI_LINK_TRAIN_NONE;
3425         temp |= FDI_LINK_TRAIN_PATTERN_1;
3426         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428         POSTING_READ(reg);
3429         udelay(150);
3430
3431         /* Ironlake workaround, enable clock pointer after FDI enable*/
3432         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434                    FDI_RX_PHASE_SYNC_POINTER_EN);
3435
3436         reg = FDI_RX_IIR(pipe);
3437         for (tries = 0; tries < 5; tries++) {
3438                 temp = I915_READ(reg);
3439                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441                 if ((temp & FDI_RX_BIT_LOCK)) {
3442                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3443                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3444                         break;
3445                 }
3446         }
3447         if (tries == 5)
3448                 DRM_ERROR("FDI train 1 fail!\n");
3449
3450         /* Train 2 */
3451         reg = FDI_TX_CTL(pipe);
3452         temp = I915_READ(reg);
3453         temp &= ~FDI_LINK_TRAIN_NONE;
3454         temp |= FDI_LINK_TRAIN_PATTERN_2;
3455         I915_WRITE(reg, temp);
3456
3457         reg = FDI_RX_CTL(pipe);
3458         temp = I915_READ(reg);
3459         temp &= ~FDI_LINK_TRAIN_NONE;
3460         temp |= FDI_LINK_TRAIN_PATTERN_2;
3461         I915_WRITE(reg, temp);
3462
3463         POSTING_READ(reg);
3464         udelay(150);
3465
3466         reg = FDI_RX_IIR(pipe);
3467         for (tries = 0; tries < 5; tries++) {
3468                 temp = I915_READ(reg);
3469                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471                 if (temp & FDI_RX_SYMBOL_LOCK) {
3472                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3473                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3474                         break;
3475                 }
3476         }
3477         if (tries == 5)
3478                 DRM_ERROR("FDI train 2 fail!\n");
3479
3480         DRM_DEBUG_KMS("FDI train done\n");
3481
3482 }
3483
3484 static const int snb_b_fdi_train_param[] = {
3485         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489 };
3490
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493 {
3494         struct drm_device *dev = crtc->dev;
3495         struct drm_i915_private *dev_priv = dev->dev_private;
3496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497         int pipe = intel_crtc->pipe;
3498         i915_reg_t reg;
3499         u32 temp, i, retry;
3500
3501         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502            for train result */
3503         reg = FDI_RX_IMR(pipe);
3504         temp = I915_READ(reg);
3505         temp &= ~FDI_RX_SYMBOL_LOCK;
3506         temp &= ~FDI_RX_BIT_LOCK;
3507         I915_WRITE(reg, temp);
3508
3509         POSTING_READ(reg);
3510         udelay(150);
3511
3512         /* enable CPU FDI TX and PCH FDI RX */
3513         reg = FDI_TX_CTL(pipe);
3514         temp = I915_READ(reg);
3515         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3516         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3517         temp &= ~FDI_LINK_TRAIN_NONE;
3518         temp |= FDI_LINK_TRAIN_PATTERN_1;
3519         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3520         /* SNB-B */
3521         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3522         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3523
3524         I915_WRITE(FDI_RX_MISC(pipe),
3525                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3526
3527         reg = FDI_RX_CTL(pipe);
3528         temp = I915_READ(reg);
3529         if (HAS_PCH_CPT(dev)) {
3530                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3531                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3532         } else {
3533                 temp &= ~FDI_LINK_TRAIN_NONE;
3534                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3535         }
3536         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3537
3538         POSTING_READ(reg);
3539         udelay(150);
3540
3541         for (i = 0; i < 4; i++) {
3542                 reg = FDI_TX_CTL(pipe);
3543                 temp = I915_READ(reg);
3544                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545                 temp |= snb_b_fdi_train_param[i];
3546                 I915_WRITE(reg, temp);
3547
3548                 POSTING_READ(reg);
3549                 udelay(500);
3550
3551                 for (retry = 0; retry < 5; retry++) {
3552                         reg = FDI_RX_IIR(pipe);
3553                         temp = I915_READ(reg);
3554                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3555                         if (temp & FDI_RX_BIT_LOCK) {
3556                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3557                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3558                                 break;
3559                         }
3560                         udelay(50);
3561                 }
3562                 if (retry < 5)
3563                         break;
3564         }
3565         if (i == 4)
3566                 DRM_ERROR("FDI train 1 fail!\n");
3567
3568         /* Train 2 */
3569         reg = FDI_TX_CTL(pipe);
3570         temp = I915_READ(reg);
3571         temp &= ~FDI_LINK_TRAIN_NONE;
3572         temp |= FDI_LINK_TRAIN_PATTERN_2;
3573         if (IS_GEN6(dev)) {
3574                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575                 /* SNB-B */
3576                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3577         }
3578         I915_WRITE(reg, temp);
3579
3580         reg = FDI_RX_CTL(pipe);
3581         temp = I915_READ(reg);
3582         if (HAS_PCH_CPT(dev)) {
3583                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3585         } else {
3586                 temp &= ~FDI_LINK_TRAIN_NONE;
3587                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3588         }
3589         I915_WRITE(reg, temp);
3590
3591         POSTING_READ(reg);
3592         udelay(150);
3593
3594         for (i = 0; i < 4; i++) {
3595                 reg = FDI_TX_CTL(pipe);
3596                 temp = I915_READ(reg);
3597                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598                 temp |= snb_b_fdi_train_param[i];
3599                 I915_WRITE(reg, temp);
3600
3601                 POSTING_READ(reg);
3602                 udelay(500);
3603
3604                 for (retry = 0; retry < 5; retry++) {
3605                         reg = FDI_RX_IIR(pipe);
3606                         temp = I915_READ(reg);
3607                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3608                         if (temp & FDI_RX_SYMBOL_LOCK) {
3609                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3610                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3611                                 break;
3612                         }
3613                         udelay(50);
3614                 }
3615                 if (retry < 5)
3616                         break;
3617         }
3618         if (i == 4)
3619                 DRM_ERROR("FDI train 2 fail!\n");
3620
3621         DRM_DEBUG_KMS("FDI train done.\n");
3622 }
3623
3624 /* Manual link training for Ivy Bridge A0 parts */
3625 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3626 {
3627         struct drm_device *dev = crtc->dev;
3628         struct drm_i915_private *dev_priv = dev->dev_private;
3629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630         int pipe = intel_crtc->pipe;
3631         i915_reg_t reg;
3632         u32 temp, i, j;
3633
3634         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635            for train result */
3636         reg = FDI_RX_IMR(pipe);
3637         temp = I915_READ(reg);
3638         temp &= ~FDI_RX_SYMBOL_LOCK;
3639         temp &= ~FDI_RX_BIT_LOCK;
3640         I915_WRITE(reg, temp);
3641
3642         POSTING_READ(reg);
3643         udelay(150);
3644
3645         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646                       I915_READ(FDI_RX_IIR(pipe)));
3647
3648         /* Try each vswing and preemphasis setting twice before moving on */
3649         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650                 /* disable first in case we need to retry */
3651                 reg = FDI_TX_CTL(pipe);
3652                 temp = I915_READ(reg);
3653                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654                 temp &= ~FDI_TX_ENABLE;
3655                 I915_WRITE(reg, temp);
3656
3657                 reg = FDI_RX_CTL(pipe);
3658                 temp = I915_READ(reg);
3659                 temp &= ~FDI_LINK_TRAIN_AUTO;
3660                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661                 temp &= ~FDI_RX_ENABLE;
3662                 I915_WRITE(reg, temp);
3663
3664                 /* enable CPU FDI TX and PCH FDI RX */
3665                 reg = FDI_TX_CTL(pipe);
3666                 temp = I915_READ(reg);
3667                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671                 temp |= snb_b_fdi_train_param[j/2];
3672                 temp |= FDI_COMPOSITE_SYNC;
3673                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675                 I915_WRITE(FDI_RX_MISC(pipe),
3676                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678                 reg = FDI_RX_CTL(pipe);
3679                 temp = I915_READ(reg);
3680                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681                 temp |= FDI_COMPOSITE_SYNC;
3682                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684                 POSTING_READ(reg);
3685                 udelay(1); /* should be 0.5us */
3686
3687                 for (i = 0; i < 4; i++) {
3688                         reg = FDI_RX_IIR(pipe);
3689                         temp = I915_READ(reg);
3690                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692                         if (temp & FDI_RX_BIT_LOCK ||
3693                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696                                               i);
3697                                 break;
3698                         }
3699                         udelay(1); /* should be 0.5us */
3700                 }
3701                 if (i == 4) {
3702                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703                         continue;
3704                 }
3705
3706                 /* Train 2 */
3707                 reg = FDI_TX_CTL(pipe);
3708                 temp = I915_READ(reg);
3709                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711                 I915_WRITE(reg, temp);
3712
3713                 reg = FDI_RX_CTL(pipe);
3714                 temp = I915_READ(reg);
3715                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717                 I915_WRITE(reg, temp);
3718
3719                 POSTING_READ(reg);
3720                 udelay(2); /* should be 1.5us */
3721
3722                 for (i = 0; i < 4; i++) {
3723                         reg = FDI_RX_IIR(pipe);
3724                         temp = I915_READ(reg);
3725                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727                         if (temp & FDI_RX_SYMBOL_LOCK ||
3728                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731                                               i);
3732                                 goto train_done;
3733                         }
3734                         udelay(2); /* should be 1.5us */
3735                 }
3736                 if (i == 4)
3737                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738         }
3739
3740 train_done:
3741         DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746         struct drm_device *dev = intel_crtc->base.dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         int pipe = intel_crtc->pipe;
3749         i915_reg_t reg;
3750         u32 temp;
3751
3752         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760         POSTING_READ(reg);
3761         udelay(200);
3762
3763         /* Switch from Rawclk to PCDclk */
3764         temp = I915_READ(reg);
3765         I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767         POSTING_READ(reg);
3768         udelay(200);
3769
3770         /* Enable CPU FDI TX PLL, always on for Ironlake */
3771         reg = FDI_TX_CTL(pipe);
3772         temp = I915_READ(reg);
3773         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776                 POSTING_READ(reg);
3777                 udelay(100);
3778         }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783         struct drm_device *dev = intel_crtc->base.dev;
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785         int pipe = intel_crtc->pipe;
3786         i915_reg_t reg;
3787         u32 temp;
3788
3789         /* Switch from PCDclk to Rawclk */
3790         reg = FDI_RX_CTL(pipe);
3791         temp = I915_READ(reg);
3792         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3793
3794         /* Disable CPU FDI TX PLL */
3795         reg = FDI_TX_CTL(pipe);
3796         temp = I915_READ(reg);
3797         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3798
3799         POSTING_READ(reg);
3800         udelay(100);
3801
3802         reg = FDI_RX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3805
3806         /* Wait for the clocks to turn off. */
3807         POSTING_READ(reg);
3808         udelay(100);
3809 }
3810
3811 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3812 {
3813         struct drm_device *dev = crtc->dev;
3814         struct drm_i915_private *dev_priv = dev->dev_private;
3815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3816         int pipe = intel_crtc->pipe;
3817         i915_reg_t reg;
3818         u32 temp;
3819
3820         /* disable CPU FDI tx and PCH FDI rx */
3821         reg = FDI_TX_CTL(pipe);
3822         temp = I915_READ(reg);
3823         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3824         POSTING_READ(reg);
3825
3826         reg = FDI_RX_CTL(pipe);
3827         temp = I915_READ(reg);
3828         temp &= ~(0x7 << 16);
3829         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3830         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3831
3832         POSTING_READ(reg);
3833         udelay(100);
3834
3835         /* Ironlake workaround, disable clock pointer after downing FDI */
3836         if (HAS_PCH_IBX(dev))
3837                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3838
3839         /* still set train pattern 1 */
3840         reg = FDI_TX_CTL(pipe);
3841         temp = I915_READ(reg);
3842         temp &= ~FDI_LINK_TRAIN_NONE;
3843         temp |= FDI_LINK_TRAIN_PATTERN_1;
3844         I915_WRITE(reg, temp);
3845
3846         reg = FDI_RX_CTL(pipe);
3847         temp = I915_READ(reg);
3848         if (HAS_PCH_CPT(dev)) {
3849                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3850                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3851         } else {
3852                 temp &= ~FDI_LINK_TRAIN_NONE;
3853                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854         }
3855         /* BPC in FDI rx is consistent with that in PIPECONF */
3856         temp &= ~(0x07 << 16);
3857         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3858         I915_WRITE(reg, temp);
3859
3860         POSTING_READ(reg);
3861         udelay(100);
3862 }
3863
3864 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3865 {
3866         struct intel_crtc *crtc;
3867
3868         /* Note that we don't need to be called with mode_config.lock here
3869          * as our list of CRTC objects is static for the lifetime of the
3870          * device and so cannot disappear as we iterate. Similarly, we can
3871          * happily treat the predicates as racy, atomic checks as userspace
3872          * cannot claim and pin a new fb without at least acquring the
3873          * struct_mutex and so serialising with us.
3874          */
3875         for_each_intel_crtc(dev, crtc) {
3876                 if (atomic_read(&crtc->unpin_work_count) == 0)
3877                         continue;
3878
3879                 if (crtc->unpin_work)
3880                         intel_wait_for_vblank(dev, crtc->pipe);
3881
3882                 return true;
3883         }
3884
3885         return false;
3886 }
3887
3888 static void page_flip_completed(struct intel_crtc *intel_crtc)
3889 {
3890         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3891         struct intel_unpin_work *work = intel_crtc->unpin_work;
3892
3893         /* ensure that the unpin work is consistent wrt ->pending. */
3894         smp_rmb();
3895         intel_crtc->unpin_work = NULL;
3896
3897         if (work->event)
3898                 drm_send_vblank_event(intel_crtc->base.dev,
3899                                       intel_crtc->pipe,
3900                                       work->event);
3901
3902         drm_crtc_vblank_put(&intel_crtc->base);
3903
3904         wake_up_all(&dev_priv->pending_flip_queue);
3905         queue_work(dev_priv->wq, &work->work);
3906
3907         trace_i915_flip_complete(intel_crtc->plane,
3908                                  work->pending_flip_obj);
3909 }
3910
3911 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3912 {
3913         struct drm_device *dev = crtc->dev;
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915         long ret;
3916
3917         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3918
3919         ret = wait_event_interruptible_timeout(
3920                                         dev_priv->pending_flip_queue,
3921                                         !intel_crtc_has_pending_flip(crtc),
3922                                         60*HZ);
3923
3924         if (ret < 0)
3925                 return ret;
3926
3927         if (ret == 0) {
3928                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929
3930                 spin_lock_irq(&dev->event_lock);
3931                 if (intel_crtc->unpin_work) {
3932                         WARN_ONCE(1, "Removing stuck page flip\n");
3933                         page_flip_completed(intel_crtc);
3934                 }
3935                 spin_unlock_irq(&dev->event_lock);
3936         }
3937
3938         return 0;
3939 }
3940
3941 /* Program iCLKIP clock to the desired frequency */
3942 static void lpt_program_iclkip(struct drm_crtc *crtc)
3943 {
3944         struct drm_device *dev = crtc->dev;
3945         struct drm_i915_private *dev_priv = dev->dev_private;
3946         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3947         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3948         u32 temp;
3949
3950         mutex_lock(&dev_priv->sb_lock);
3951
3952         /* It is necessary to ungate the pixclk gate prior to programming
3953          * the divisors, and gate it back when it is done.
3954          */
3955         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3956
3957         /* Disable SSCCTL */
3958         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3959                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3960                                 SBI_SSCCTL_DISABLE,
3961                         SBI_ICLK);
3962
3963         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3964         if (clock == 20000) {
3965                 auxdiv = 1;
3966                 divsel = 0x41;
3967                 phaseinc = 0x20;
3968         } else {
3969                 /* The iCLK virtual clock root frequency is in MHz,
3970                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3971                  * divisors, it is necessary to divide one by another, so we
3972                  * convert the virtual clock precision to KHz here for higher
3973                  * precision.
3974                  */
3975                 u32 iclk_virtual_root_freq = 172800 * 1000;
3976                 u32 iclk_pi_range = 64;
3977                 u32 desired_divisor, msb_divisor_value, pi_value;
3978
3979                 desired_divisor = (iclk_virtual_root_freq / clock);
3980                 msb_divisor_value = desired_divisor / iclk_pi_range;
3981                 pi_value = desired_divisor % iclk_pi_range;
3982
3983                 auxdiv = 0;
3984                 divsel = msb_divisor_value - 2;
3985                 phaseinc = pi_value;
3986         }
3987
3988         /* This should not happen with any sane values */
3989         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3990                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3991         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3992                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3993
3994         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3995                         clock,
3996                         auxdiv,
3997                         divsel,
3998                         phasedir,
3999                         phaseinc);
4000
4001         /* Program SSCDIVINTPHASE6 */
4002         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4003         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4004         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4005         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4006         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4007         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4008         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4009         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4010
4011         /* Program SSCAUXDIV */
4012         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4013         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4014         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4015         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4016
4017         /* Enable modulator and associated divider */
4018         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4019         temp &= ~SBI_SSCCTL_DISABLE;
4020         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4021
4022         /* Wait for initialization time */
4023         udelay(24);
4024
4025         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4026
4027         mutex_unlock(&dev_priv->sb_lock);
4028 }
4029
4030 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4031                                                 enum pipe pch_transcoder)
4032 {
4033         struct drm_device *dev = crtc->base.dev;
4034         struct drm_i915_private *dev_priv = dev->dev_private;
4035         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4036
4037         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4038                    I915_READ(HTOTAL(cpu_transcoder)));
4039         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4040                    I915_READ(HBLANK(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4042                    I915_READ(HSYNC(cpu_transcoder)));
4043
4044         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4045                    I915_READ(VTOTAL(cpu_transcoder)));
4046         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4047                    I915_READ(VBLANK(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4049                    I915_READ(VSYNC(cpu_transcoder)));
4050         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4051                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4052 }
4053
4054 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4055 {
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         uint32_t temp;
4058
4059         temp = I915_READ(SOUTH_CHICKEN1);
4060         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4061                 return;
4062
4063         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4064         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4065
4066         temp &= ~FDI_BC_BIFURCATION_SELECT;
4067         if (enable)
4068                 temp |= FDI_BC_BIFURCATION_SELECT;
4069
4070         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4071         I915_WRITE(SOUTH_CHICKEN1, temp);
4072         POSTING_READ(SOUTH_CHICKEN1);
4073 }
4074
4075 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4076 {
4077         struct drm_device *dev = intel_crtc->base.dev;
4078
4079         switch (intel_crtc->pipe) {
4080         case PIPE_A:
4081                 break;
4082         case PIPE_B:
4083                 if (intel_crtc->config->fdi_lanes > 2)
4084                         cpt_set_fdi_bc_bifurcation(dev, false);
4085                 else
4086                         cpt_set_fdi_bc_bifurcation(dev, true);
4087
4088                 break;
4089         case PIPE_C:
4090                 cpt_set_fdi_bc_bifurcation(dev, true);
4091
4092                 break;
4093         default:
4094                 BUG();
4095         }
4096 }
4097
4098 /* Return which DP Port should be selected for Transcoder DP control */
4099 static enum port
4100 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->dev;
4103         struct intel_encoder *encoder;
4104
4105         for_each_encoder_on_crtc(dev, crtc, encoder) {
4106                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4107                     encoder->type == INTEL_OUTPUT_EDP)
4108                         return enc_to_dig_port(&encoder->base)->port;
4109         }
4110
4111         return -1;
4112 }
4113
4114 /*
4115  * Enable PCH resources required for PCH ports:
4116  *   - PCH PLLs
4117  *   - FDI training & RX/TX
4118  *   - update transcoder timings
4119  *   - DP transcoding bits
4120  *   - transcoder
4121  */
4122 static void ironlake_pch_enable(struct drm_crtc *crtc)
4123 {
4124         struct drm_device *dev = crtc->dev;
4125         struct drm_i915_private *dev_priv = dev->dev_private;
4126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4127         int pipe = intel_crtc->pipe;
4128         u32 temp;
4129
4130         assert_pch_transcoder_disabled(dev_priv, pipe);
4131
4132         if (IS_IVYBRIDGE(dev))
4133                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4134
4135         /* Write the TU size bits before fdi link training, so that error
4136          * detection works. */
4137         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4138                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4139
4140         /*
4141          * Sometimes spurious CPU pipe underruns happen during FDI
4142          * training, at least with VGA+HDMI cloning. Suppress them.
4143          */
4144         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4145
4146         /* For PCH output, training FDI link */
4147         dev_priv->display.fdi_link_train(crtc);
4148
4149         /* We need to program the right clock selection before writing the pixel
4150          * mutliplier into the DPLL. */
4151         if (HAS_PCH_CPT(dev)) {
4152                 u32 sel;
4153
4154                 temp = I915_READ(PCH_DPLL_SEL);
4155                 temp |= TRANS_DPLL_ENABLE(pipe);
4156                 sel = TRANS_DPLLB_SEL(pipe);
4157                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4158                         temp |= sel;
4159                 else
4160                         temp &= ~sel;
4161                 I915_WRITE(PCH_DPLL_SEL, temp);
4162         }
4163
4164         /* XXX: pch pll's can be enabled any time before we enable the PCH
4165          * transcoder, and we actually should do this to not upset any PCH
4166          * transcoder that already use the clock when we share it.
4167          *
4168          * Note that enable_shared_dpll tries to do the right thing, but
4169          * get_shared_dpll unconditionally resets the pll - we need that to have
4170          * the right LVDS enable sequence. */
4171         intel_enable_shared_dpll(intel_crtc);
4172
4173         /* set transcoder timing, panel must allow it */
4174         assert_panel_unlocked(dev_priv, pipe);
4175         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4176
4177         intel_fdi_normal_train(crtc);
4178
4179         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4180
4181         /* For PCH DP, enable TRANS_DP_CTL */
4182         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4183                 const struct drm_display_mode *adjusted_mode =
4184                         &intel_crtc->config->base.adjusted_mode;
4185                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4186                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4187                 temp = I915_READ(reg);
4188                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4189                           TRANS_DP_SYNC_MASK |
4190                           TRANS_DP_BPC_MASK);
4191                 temp |= TRANS_DP_OUTPUT_ENABLE;
4192                 temp |= bpc << 9; /* same format but at 11:9 */
4193
4194                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4195                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4196                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4197                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4198
4199                 switch (intel_trans_dp_port_sel(crtc)) {
4200                 case PORT_B:
4201                         temp |= TRANS_DP_PORT_SEL_B;
4202                         break;
4203                 case PORT_C:
4204                         temp |= TRANS_DP_PORT_SEL_C;
4205                         break;
4206                 case PORT_D:
4207                         temp |= TRANS_DP_PORT_SEL_D;
4208                         break;
4209                 default:
4210                         BUG();
4211                 }
4212
4213                 I915_WRITE(reg, temp);
4214         }
4215
4216         ironlake_enable_pch_transcoder(dev_priv, pipe);
4217 }
4218
4219 static void lpt_pch_enable(struct drm_crtc *crtc)
4220 {
4221         struct drm_device *dev = crtc->dev;
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4225
4226         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4227
4228         lpt_program_iclkip(crtc);
4229
4230         /* Set transcoder timing. */
4231         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4232
4233         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4234 }
4235
4236 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4237                                                 struct intel_crtc_state *crtc_state)
4238 {
4239         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4240         struct intel_shared_dpll *pll;
4241         struct intel_shared_dpll_config *shared_dpll;
4242         enum intel_dpll_id i;
4243         int max = dev_priv->num_shared_dpll;
4244
4245         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4246
4247         if (HAS_PCH_IBX(dev_priv->dev)) {
4248                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4249                 i = (enum intel_dpll_id) crtc->pipe;
4250                 pll = &dev_priv->shared_dplls[i];
4251
4252                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4253                               crtc->base.base.id, pll->name);
4254
4255                 WARN_ON(shared_dpll[i].crtc_mask);
4256
4257                 goto found;
4258         }
4259
4260         if (IS_BROXTON(dev_priv->dev)) {
4261                 /* PLL is attached to port in bxt */
4262                 struct intel_encoder *encoder;
4263                 struct intel_digital_port *intel_dig_port;
4264
4265                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4266                 if (WARN_ON(!encoder))
4267                         return NULL;
4268
4269                 intel_dig_port = enc_to_dig_port(&encoder->base);
4270                 /* 1:1 mapping between ports and PLLs */
4271                 i = (enum intel_dpll_id)intel_dig_port->port;
4272                 pll = &dev_priv->shared_dplls[i];
4273                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4274                         crtc->base.base.id, pll->name);
4275                 WARN_ON(shared_dpll[i].crtc_mask);
4276
4277                 goto found;
4278         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4279                 /* Do not consider SPLL */
4280                 max = 2;
4281
4282         for (i = 0; i < max; i++) {
4283                 pll = &dev_priv->shared_dplls[i];
4284
4285                 /* Only want to check enabled timings first */
4286                 if (shared_dpll[i].crtc_mask == 0)
4287                         continue;
4288
4289                 if (memcmp(&crtc_state->dpll_hw_state,
4290                            &shared_dpll[i].hw_state,
4291                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4292                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4293                                       crtc->base.base.id, pll->name,
4294                                       shared_dpll[i].crtc_mask,
4295                                       pll->active);
4296                         goto found;
4297                 }
4298         }
4299
4300         /* Ok no matching timings, maybe there's a free one? */
4301         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4302                 pll = &dev_priv->shared_dplls[i];
4303                 if (shared_dpll[i].crtc_mask == 0) {
4304                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4305                                       crtc->base.base.id, pll->name);
4306                         goto found;
4307                 }
4308         }
4309
4310         return NULL;
4311
4312 found:
4313         if (shared_dpll[i].crtc_mask == 0)
4314                 shared_dpll[i].hw_state =
4315                         crtc_state->dpll_hw_state;
4316
4317         crtc_state->shared_dpll = i;
4318         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4319                          pipe_name(crtc->pipe));
4320
4321         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4322
4323         return pll;
4324 }
4325
4326 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4327 {
4328         struct drm_i915_private *dev_priv = to_i915(state->dev);
4329         struct intel_shared_dpll_config *shared_dpll;
4330         struct intel_shared_dpll *pll;
4331         enum intel_dpll_id i;
4332
4333         if (!to_intel_atomic_state(state)->dpll_set)
4334                 return;
4335
4336         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4337         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4338                 pll = &dev_priv->shared_dplls[i];
4339                 pll->config = shared_dpll[i];
4340         }
4341 }
4342
4343 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4344 {
4345         struct drm_i915_private *dev_priv = dev->dev_private;
4346         i915_reg_t dslreg = PIPEDSL(pipe);
4347         u32 temp;
4348
4349         temp = I915_READ(dslreg);
4350         udelay(500);
4351         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4352                 if (wait_for(I915_READ(dslreg) != temp, 5))
4353                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4354         }
4355 }
4356
4357 static int
4358 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4359                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4360                   int src_w, int src_h, int dst_w, int dst_h)
4361 {
4362         struct intel_crtc_scaler_state *scaler_state =
4363                 &crtc_state->scaler_state;
4364         struct intel_crtc *intel_crtc =
4365                 to_intel_crtc(crtc_state->base.crtc);
4366         int need_scaling;
4367
4368         need_scaling = intel_rotation_90_or_270(rotation) ?
4369                 (src_h != dst_w || src_w != dst_h):
4370                 (src_w != dst_w || src_h != dst_h);
4371
4372         /*
4373          * if plane is being disabled or scaler is no more required or force detach
4374          *  - free scaler binded to this plane/crtc
4375          *  - in order to do this, update crtc->scaler_usage
4376          *
4377          * Here scaler state in crtc_state is set free so that
4378          * scaler can be assigned to other user. Actual register
4379          * update to free the scaler is done in plane/panel-fit programming.
4380          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4381          */
4382         if (force_detach || !need_scaling) {
4383                 if (*scaler_id >= 0) {
4384                         scaler_state->scaler_users &= ~(1 << scaler_user);
4385                         scaler_state->scalers[*scaler_id].in_use = 0;
4386
4387                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4388                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4389                                 intel_crtc->pipe, scaler_user, *scaler_id,
4390                                 scaler_state->scaler_users);
4391                         *scaler_id = -1;
4392                 }
4393                 return 0;
4394         }
4395
4396         /* range checks */
4397         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4398                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4399
4400                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4401                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4402                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4403                         "size is out of scaler range\n",
4404                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4405                 return -EINVAL;
4406         }
4407
4408         /* mark this plane as a scaler user in crtc_state */
4409         scaler_state->scaler_users |= (1 << scaler_user);
4410         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4411                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4412                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4413                 scaler_state->scaler_users);
4414
4415         return 0;
4416 }
4417
4418 /**
4419  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4420  *
4421  * @state: crtc's scaler state
4422  *
4423  * Return
4424  *     0 - scaler_usage updated successfully
4425  *    error - requested scaling cannot be supported or other error condition
4426  */
4427 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4428 {
4429         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4430         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4431
4432         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4433                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4434
4435         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4436                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4437                 state->pipe_src_w, state->pipe_src_h,
4438                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4439 }
4440
4441 /**
4442  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4443  *
4444  * @state: crtc's scaler state
4445  * @plane_state: atomic plane state to update
4446  *
4447  * Return
4448  *     0 - scaler_usage updated successfully
4449  *    error - requested scaling cannot be supported or other error condition
4450  */
4451 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4452                                    struct intel_plane_state *plane_state)
4453 {
4454
4455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4456         struct intel_plane *intel_plane =
4457                 to_intel_plane(plane_state->base.plane);
4458         struct drm_framebuffer *fb = plane_state->base.fb;
4459         int ret;
4460
4461         bool force_detach = !fb || !plane_state->visible;
4462
4463         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4464                       intel_plane->base.base.id, intel_crtc->pipe,
4465                       drm_plane_index(&intel_plane->base));
4466
4467         ret = skl_update_scaler(crtc_state, force_detach,
4468                                 drm_plane_index(&intel_plane->base),
4469                                 &plane_state->scaler_id,
4470                                 plane_state->base.rotation,
4471                                 drm_rect_width(&plane_state->src) >> 16,
4472                                 drm_rect_height(&plane_state->src) >> 16,
4473                                 drm_rect_width(&plane_state->dst),
4474                                 drm_rect_height(&plane_state->dst));
4475
4476         if (ret || plane_state->scaler_id < 0)
4477                 return ret;
4478
4479         /* check colorkey */
4480         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4481                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4482                               intel_plane->base.base.id);
4483                 return -EINVAL;
4484         }
4485
4486         /* Check src format */
4487         switch (fb->pixel_format) {
4488         case DRM_FORMAT_RGB565:
4489         case DRM_FORMAT_XBGR8888:
4490         case DRM_FORMAT_XRGB8888:
4491         case DRM_FORMAT_ABGR8888:
4492         case DRM_FORMAT_ARGB8888:
4493         case DRM_FORMAT_XRGB2101010:
4494         case DRM_FORMAT_XBGR2101010:
4495         case DRM_FORMAT_YUYV:
4496         case DRM_FORMAT_YVYU:
4497         case DRM_FORMAT_UYVY:
4498         case DRM_FORMAT_VYUY:
4499                 break;
4500         default:
4501                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4502                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4503                 return -EINVAL;
4504         }
4505
4506         return 0;
4507 }
4508
4509 static void skylake_scaler_disable(struct intel_crtc *crtc)
4510 {
4511         int i;
4512
4513         for (i = 0; i < crtc->num_scalers; i++)
4514                 skl_detach_scaler(crtc, i);
4515 }
4516
4517 static void skylake_pfit_enable(struct intel_crtc *crtc)
4518 {
4519         struct drm_device *dev = crtc->base.dev;
4520         struct drm_i915_private *dev_priv = dev->dev_private;
4521         int pipe = crtc->pipe;
4522         struct intel_crtc_scaler_state *scaler_state =
4523                 &crtc->config->scaler_state;
4524
4525         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4526
4527         if (crtc->config->pch_pfit.enabled) {
4528                 int id;
4529
4530                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4531                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4532                         return;
4533                 }
4534
4535                 id = scaler_state->scaler_id;
4536                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4537                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4538                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4539                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4540
4541                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4542         }
4543 }
4544
4545 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4546 {
4547         struct drm_device *dev = crtc->base.dev;
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549         int pipe = crtc->pipe;
4550
4551         if (crtc->config->pch_pfit.enabled) {
4552                 /* Force use of hard-coded filter coefficients
4553                  * as some pre-programmed values are broken,
4554                  * e.g. x201.
4555                  */
4556                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4557                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4558                                                  PF_PIPE_SEL_IVB(pipe));
4559                 else
4560                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4561                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4562                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4563         }
4564 }
4565
4566 void hsw_enable_ips(struct intel_crtc *crtc)
4567 {
4568         struct drm_device *dev = crtc->base.dev;
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570
4571         if (!crtc->config->ips_enabled)
4572                 return;
4573
4574         /* We can only enable IPS after we enable a plane and wait for a vblank */
4575         intel_wait_for_vblank(dev, crtc->pipe);
4576
4577         assert_plane_enabled(dev_priv, crtc->plane);
4578         if (IS_BROADWELL(dev)) {
4579                 mutex_lock(&dev_priv->rps.hw_lock);
4580                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4581                 mutex_unlock(&dev_priv->rps.hw_lock);
4582                 /* Quoting Art Runyan: "its not safe to expect any particular
4583                  * value in IPS_CTL bit 31 after enabling IPS through the
4584                  * mailbox." Moreover, the mailbox may return a bogus state,
4585                  * so we need to just enable it and continue on.
4586                  */
4587         } else {
4588                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4589                 /* The bit only becomes 1 in the next vblank, so this wait here
4590                  * is essentially intel_wait_for_vblank. If we don't have this
4591                  * and don't wait for vblanks until the end of crtc_enable, then
4592                  * the HW state readout code will complain that the expected
4593                  * IPS_CTL value is not the one we read. */
4594                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4595                         DRM_ERROR("Timed out waiting for IPS enable\n");
4596         }
4597 }
4598
4599 void hsw_disable_ips(struct intel_crtc *crtc)
4600 {
4601         struct drm_device *dev = crtc->base.dev;
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603
4604         if (!crtc->config->ips_enabled)
4605                 return;
4606
4607         assert_plane_enabled(dev_priv, crtc->plane);
4608         if (IS_BROADWELL(dev)) {
4609                 mutex_lock(&dev_priv->rps.hw_lock);
4610                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4611                 mutex_unlock(&dev_priv->rps.hw_lock);
4612                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4613                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4614                         DRM_ERROR("Timed out waiting for IPS disable\n");
4615         } else {
4616                 I915_WRITE(IPS_CTL, 0);
4617                 POSTING_READ(IPS_CTL);
4618         }
4619
4620         /* We need to wait for a vblank before we can disable the plane. */
4621         intel_wait_for_vblank(dev, crtc->pipe);
4622 }
4623
4624 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4625 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4626 {
4627         struct drm_device *dev = crtc->dev;
4628         struct drm_i915_private *dev_priv = dev->dev_private;
4629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4630         enum pipe pipe = intel_crtc->pipe;
4631         int i;
4632         bool reenable_ips = false;
4633
4634         /* The clocks have to be on to load the palette. */
4635         if (!crtc->state->active)
4636                 return;
4637
4638         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4639                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4640                         assert_dsi_pll_enabled(dev_priv);
4641                 else
4642                         assert_pll_enabled(dev_priv, pipe);
4643         }
4644
4645         /* Workaround : Do not read or write the pipe palette/gamma data while
4646          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4647          */
4648         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4649             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4650              GAMMA_MODE_MODE_SPLIT)) {
4651                 hsw_disable_ips(intel_crtc);
4652                 reenable_ips = true;
4653         }
4654
4655         for (i = 0; i < 256; i++) {
4656                 i915_reg_t palreg;
4657
4658                 if (HAS_GMCH_DISPLAY(dev))
4659                         palreg = PALETTE(pipe, i);
4660                 else
4661                         palreg = LGC_PALETTE(pipe, i);
4662
4663                 I915_WRITE(palreg,
4664                            (intel_crtc->lut_r[i] << 16) |
4665                            (intel_crtc->lut_g[i] << 8) |
4666                            intel_crtc->lut_b[i]);
4667         }
4668
4669         if (reenable_ips)
4670                 hsw_enable_ips(intel_crtc);
4671 }
4672
4673 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4674 {
4675         if (intel_crtc->overlay) {
4676                 struct drm_device *dev = intel_crtc->base.dev;
4677                 struct drm_i915_private *dev_priv = dev->dev_private;
4678
4679                 mutex_lock(&dev->struct_mutex);
4680                 dev_priv->mm.interruptible = false;
4681                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4682                 dev_priv->mm.interruptible = true;
4683                 mutex_unlock(&dev->struct_mutex);
4684         }
4685
4686         /* Let userspace switch the overlay on again. In most cases userspace
4687          * has to recompute where to put it anyway.
4688          */
4689 }
4690
4691 /**
4692  * intel_post_enable_primary - Perform operations after enabling primary plane
4693  * @crtc: the CRTC whose primary plane was just enabled
4694  *
4695  * Performs potentially sleeping operations that must be done after the primary
4696  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4697  * called due to an explicit primary plane update, or due to an implicit
4698  * re-enable that is caused when a sprite plane is updated to no longer
4699  * completely hide the primary plane.
4700  */
4701 static void
4702 intel_post_enable_primary(struct drm_crtc *crtc)
4703 {
4704         struct drm_device *dev = crtc->dev;
4705         struct drm_i915_private *dev_priv = dev->dev_private;
4706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707         int pipe = intel_crtc->pipe;
4708
4709         /*
4710          * BDW signals flip done immediately if the plane
4711          * is disabled, even if the plane enable is already
4712          * armed to occur at the next vblank :(
4713          */
4714         if (IS_BROADWELL(dev))
4715                 intel_wait_for_vblank(dev, pipe);
4716
4717         /*
4718          * FIXME IPS should be fine as long as one plane is
4719          * enabled, but in practice it seems to have problems
4720          * when going from primary only to sprite only and vice
4721          * versa.
4722          */
4723         hsw_enable_ips(intel_crtc);
4724
4725         /*
4726          * Gen2 reports pipe underruns whenever all planes are disabled.
4727          * So don't enable underrun reporting before at least some planes
4728          * are enabled.
4729          * FIXME: Need to fix the logic to work when we turn off all planes
4730          * but leave the pipe running.
4731          */
4732         if (IS_GEN2(dev))
4733                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4734
4735         /* Underruns don't always raise interrupts, so check manually. */
4736         intel_check_cpu_fifo_underruns(dev_priv);
4737         intel_check_pch_fifo_underruns(dev_priv);
4738 }
4739
4740 /**
4741  * intel_pre_disable_primary - Perform operations before disabling primary plane
4742  * @crtc: the CRTC whose primary plane is to be disabled
4743  *
4744  * Performs potentially sleeping operations that must be done before the
4745  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4746  * be called due to an explicit primary plane update, or due to an implicit
4747  * disable that is caused when a sprite plane completely hides the primary
4748  * plane.
4749  */
4750 static void
4751 intel_pre_disable_primary(struct drm_crtc *crtc)
4752 {
4753         struct drm_device *dev = crtc->dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4756         int pipe = intel_crtc->pipe;
4757
4758         /*
4759          * Gen2 reports pipe underruns whenever all planes are disabled.
4760          * So diasble underrun reporting before all the planes get disabled.
4761          * FIXME: Need to fix the logic to work when we turn off all planes
4762          * but leave the pipe running.
4763          */
4764         if (IS_GEN2(dev))
4765                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4766
4767         /*
4768          * Vblank time updates from the shadow to live plane control register
4769          * are blocked if the memory self-refresh mode is active at that
4770          * moment. So to make sure the plane gets truly disabled, disable
4771          * first the self-refresh mode. The self-refresh enable bit in turn
4772          * will be checked/applied by the HW only at the next frame start
4773          * event which is after the vblank start event, so we need to have a
4774          * wait-for-vblank between disabling the plane and the pipe.
4775          */
4776         if (HAS_GMCH_DISPLAY(dev)) {
4777                 intel_set_memory_cxsr(dev_priv, false);
4778                 dev_priv->wm.vlv.cxsr = false;
4779                 intel_wait_for_vblank(dev, pipe);
4780         }
4781
4782         /*
4783          * FIXME IPS should be fine as long as one plane is
4784          * enabled, but in practice it seems to have problems
4785          * when going from primary only to sprite only and vice
4786          * versa.
4787          */
4788         hsw_disable_ips(intel_crtc);
4789 }
4790
4791 static void intel_post_plane_update(struct intel_crtc *crtc)
4792 {
4793         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4794         struct drm_device *dev = crtc->base.dev;
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796
4797         if (atomic->wait_vblank)
4798                 intel_wait_for_vblank(dev, crtc->pipe);
4799
4800         intel_frontbuffer_flip(dev, atomic->fb_bits);
4801
4802         if (atomic->disable_cxsr)
4803                 crtc->wm.cxsr_allowed = true;
4804
4805         if (crtc->atomic.update_wm_post)
4806                 intel_update_watermarks(&crtc->base);
4807
4808         if (atomic->update_fbc)
4809                 intel_fbc_update(dev_priv);
4810
4811         if (atomic->post_enable_primary)
4812                 intel_post_enable_primary(&crtc->base);
4813
4814         memset(atomic, 0, sizeof(*atomic));
4815 }
4816
4817 static void intel_pre_plane_update(struct intel_crtc *crtc)
4818 {
4819         struct drm_device *dev = crtc->base.dev;
4820         struct drm_i915_private *dev_priv = dev->dev_private;
4821         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4822
4823         if (atomic->disable_fbc)
4824                 intel_fbc_disable_crtc(crtc);
4825
4826         if (crtc->atomic.disable_ips)
4827                 hsw_disable_ips(crtc);
4828
4829         if (atomic->pre_disable_primary)
4830                 intel_pre_disable_primary(&crtc->base);
4831
4832         if (atomic->disable_cxsr) {
4833                 crtc->wm.cxsr_allowed = false;
4834                 intel_set_memory_cxsr(dev_priv, false);
4835         }
4836 }
4837
4838 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4839 {
4840         struct drm_device *dev = crtc->dev;
4841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842         struct drm_plane *p;
4843         int pipe = intel_crtc->pipe;
4844
4845         intel_crtc_dpms_overlay_disable(intel_crtc);
4846
4847         drm_for_each_plane_mask(p, dev, plane_mask)
4848                 to_intel_plane(p)->disable_plane(p, crtc);
4849
4850         /*
4851          * FIXME: Once we grow proper nuclear flip support out of this we need
4852          * to compute the mask of flip planes precisely. For the time being
4853          * consider this a flip to a NULL plane.
4854          */
4855         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4856 }
4857
4858 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4859 {
4860         struct drm_device *dev = crtc->dev;
4861         struct drm_i915_private *dev_priv = dev->dev_private;
4862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4863         struct intel_encoder *encoder;
4864         int pipe = intel_crtc->pipe;
4865
4866         if (WARN_ON(intel_crtc->active))
4867                 return;
4868
4869         if (intel_crtc->config->has_pch_encoder)
4870                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4871
4872         if (intel_crtc->config->has_pch_encoder)
4873                 intel_prepare_shared_dpll(intel_crtc);
4874
4875         if (intel_crtc->config->has_dp_encoder)
4876                 intel_dp_set_m_n(intel_crtc, M1_N1);
4877
4878         intel_set_pipe_timings(intel_crtc);
4879
4880         if (intel_crtc->config->has_pch_encoder) {
4881                 intel_cpu_transcoder_set_m_n(intel_crtc,
4882                                      &intel_crtc->config->fdi_m_n, NULL);
4883         }
4884
4885         ironlake_set_pipeconf(crtc);
4886
4887         intel_crtc->active = true;
4888
4889         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4890
4891         for_each_encoder_on_crtc(dev, crtc, encoder)
4892                 if (encoder->pre_enable)
4893                         encoder->pre_enable(encoder);
4894
4895         if (intel_crtc->config->has_pch_encoder) {
4896                 /* Note: FDI PLL enabling _must_ be done before we enable the
4897                  * cpu pipes, hence this is separate from all the other fdi/pch
4898                  * enabling. */
4899                 ironlake_fdi_pll_enable(intel_crtc);
4900         } else {
4901                 assert_fdi_tx_disabled(dev_priv, pipe);
4902                 assert_fdi_rx_disabled(dev_priv, pipe);
4903         }
4904
4905         ironlake_pfit_enable(intel_crtc);
4906
4907         /*
4908          * On ILK+ LUT must be loaded before the pipe is running but with
4909          * clocks enabled
4910          */
4911         intel_crtc_load_lut(crtc);
4912
4913         intel_update_watermarks(crtc);
4914         intel_enable_pipe(intel_crtc);
4915
4916         if (intel_crtc->config->has_pch_encoder)
4917                 ironlake_pch_enable(crtc);
4918
4919         assert_vblank_disabled(crtc);
4920         drm_crtc_vblank_on(crtc);
4921
4922         for_each_encoder_on_crtc(dev, crtc, encoder)
4923                 encoder->enable(encoder);
4924
4925         if (HAS_PCH_CPT(dev))
4926                 cpt_verify_modeset(dev, intel_crtc->pipe);
4927
4928         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4929         if (intel_crtc->config->has_pch_encoder)
4930                 intel_wait_for_vblank(dev, pipe);
4931         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4932 }
4933
4934 /* IPS only exists on ULT machines and is tied to pipe A. */
4935 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4936 {
4937         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4938 }
4939
4940 static void haswell_crtc_enable(struct drm_crtc *crtc)
4941 {
4942         struct drm_device *dev = crtc->dev;
4943         struct drm_i915_private *dev_priv = dev->dev_private;
4944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945         struct intel_encoder *encoder;
4946         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4947         struct intel_crtc_state *pipe_config =
4948                 to_intel_crtc_state(crtc->state);
4949         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4950
4951         if (WARN_ON(intel_crtc->active))
4952                 return;
4953
4954         if (intel_crtc->config->has_pch_encoder)
4955                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4956                                                       false);
4957
4958         if (intel_crtc_to_shared_dpll(intel_crtc))
4959                 intel_enable_shared_dpll(intel_crtc);
4960
4961         if (intel_crtc->config->has_dp_encoder)
4962                 intel_dp_set_m_n(intel_crtc, M1_N1);
4963
4964         intel_set_pipe_timings(intel_crtc);
4965
4966         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4967                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4968                            intel_crtc->config->pixel_multiplier - 1);
4969         }
4970
4971         if (intel_crtc->config->has_pch_encoder) {
4972                 intel_cpu_transcoder_set_m_n(intel_crtc,
4973                                      &intel_crtc->config->fdi_m_n, NULL);
4974         }
4975
4976         haswell_set_pipeconf(crtc);
4977
4978         intel_set_pipe_csc(crtc);
4979
4980         intel_crtc->active = true;
4981
4982         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4983         for_each_encoder_on_crtc(dev, crtc, encoder) {
4984                 if (encoder->pre_pll_enable)
4985                         encoder->pre_pll_enable(encoder);
4986                 if (encoder->pre_enable)
4987                         encoder->pre_enable(encoder);
4988         }
4989
4990         if (intel_crtc->config->has_pch_encoder)
4991                 dev_priv->display.fdi_link_train(crtc);
4992
4993         if (!is_dsi)
4994                 intel_ddi_enable_pipe_clock(intel_crtc);
4995
4996         if (INTEL_INFO(dev)->gen >= 9)
4997                 skylake_pfit_enable(intel_crtc);
4998         else
4999                 ironlake_pfit_enable(intel_crtc);
5000
5001         /*
5002          * On ILK+ LUT must be loaded before the pipe is running but with
5003          * clocks enabled
5004          */
5005         intel_crtc_load_lut(crtc);
5006
5007         intel_ddi_set_pipe_settings(crtc);
5008         if (!is_dsi)
5009                 intel_ddi_enable_transcoder_func(crtc);
5010
5011         intel_update_watermarks(crtc);
5012         intel_enable_pipe(intel_crtc);
5013
5014         if (intel_crtc->config->has_pch_encoder)
5015                 lpt_pch_enable(crtc);
5016
5017         if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5018                 intel_ddi_set_vc_payload_alloc(crtc, true);
5019
5020         assert_vblank_disabled(crtc);
5021         drm_crtc_vblank_on(crtc);
5022
5023         for_each_encoder_on_crtc(dev, crtc, encoder) {
5024                 encoder->enable(encoder);
5025                 intel_opregion_notify_encoder(encoder, true);
5026         }
5027
5028         if (intel_crtc->config->has_pch_encoder)
5029                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5030                                                       true);
5031
5032         /* If we change the relative order between pipe/planes enabling, we need
5033          * to change the workaround. */
5034         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5035         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5036                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5037                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5038         }
5039 }
5040
5041 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5042 {
5043         struct drm_device *dev = crtc->base.dev;
5044         struct drm_i915_private *dev_priv = dev->dev_private;
5045         int pipe = crtc->pipe;
5046
5047         /* To avoid upsetting the power well on haswell only disable the pfit if
5048          * it's in use. The hw state code will make sure we get this right. */
5049         if (force || crtc->config->pch_pfit.enabled) {
5050                 I915_WRITE(PF_CTL(pipe), 0);
5051                 I915_WRITE(PF_WIN_POS(pipe), 0);
5052                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5053         }
5054 }
5055
5056 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5057 {
5058         struct drm_device *dev = crtc->dev;
5059         struct drm_i915_private *dev_priv = dev->dev_private;
5060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5061         struct intel_encoder *encoder;
5062         int pipe = intel_crtc->pipe;
5063
5064         if (intel_crtc->config->has_pch_encoder)
5065                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5066
5067         for_each_encoder_on_crtc(dev, crtc, encoder)
5068                 encoder->disable(encoder);
5069
5070         drm_crtc_vblank_off(crtc);
5071         assert_vblank_disabled(crtc);
5072
5073         /*
5074          * Sometimes spurious CPU pipe underruns happen when the
5075          * pipe is already disabled, but FDI RX/TX is still enabled.
5076          * Happens at least with VGA+HDMI cloning. Suppress them.
5077          */
5078         if (intel_crtc->config->has_pch_encoder)
5079                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5080
5081         intel_disable_pipe(intel_crtc);
5082
5083         ironlake_pfit_disable(intel_crtc, false);
5084
5085         if (intel_crtc->config->has_pch_encoder) {
5086                 ironlake_fdi_disable(crtc);
5087                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5088         }
5089
5090         for_each_encoder_on_crtc(dev, crtc, encoder)
5091                 if (encoder->post_disable)
5092                         encoder->post_disable(encoder);
5093
5094         if (intel_crtc->config->has_pch_encoder) {
5095                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5096
5097                 if (HAS_PCH_CPT(dev)) {
5098                         i915_reg_t reg;
5099                         u32 temp;
5100
5101                         /* disable TRANS_DP_CTL */
5102                         reg = TRANS_DP_CTL(pipe);
5103                         temp = I915_READ(reg);
5104                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5105                                   TRANS_DP_PORT_SEL_MASK);
5106                         temp |= TRANS_DP_PORT_SEL_NONE;
5107                         I915_WRITE(reg, temp);
5108
5109                         /* disable DPLL_SEL */
5110                         temp = I915_READ(PCH_DPLL_SEL);
5111                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5112                         I915_WRITE(PCH_DPLL_SEL, temp);
5113                 }
5114
5115                 ironlake_fdi_pll_disable(intel_crtc);
5116         }
5117
5118         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5119 }
5120
5121 static void haswell_crtc_disable(struct drm_crtc *crtc)
5122 {
5123         struct drm_device *dev = crtc->dev;
5124         struct drm_i915_private *dev_priv = dev->dev_private;
5125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5126         struct intel_encoder *encoder;
5127         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5128         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5129
5130         if (intel_crtc->config->has_pch_encoder)
5131                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5132                                                       false);
5133
5134         for_each_encoder_on_crtc(dev, crtc, encoder) {
5135                 intel_opregion_notify_encoder(encoder, false);
5136                 encoder->disable(encoder);
5137         }
5138
5139         drm_crtc_vblank_off(crtc);
5140         assert_vblank_disabled(crtc);
5141
5142         intel_disable_pipe(intel_crtc);
5143
5144         if (intel_crtc->config->dp_encoder_is_mst)
5145                 intel_ddi_set_vc_payload_alloc(crtc, false);
5146
5147         if (!is_dsi)
5148                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5149
5150         if (INTEL_INFO(dev)->gen >= 9)
5151                 skylake_scaler_disable(intel_crtc);
5152         else
5153                 ironlake_pfit_disable(intel_crtc, false);
5154
5155         if (!is_dsi)
5156                 intel_ddi_disable_pipe_clock(intel_crtc);
5157
5158         if (intel_crtc->config->has_pch_encoder) {
5159                 lpt_disable_pch_transcoder(dev_priv);
5160                 intel_ddi_fdi_disable(crtc);
5161         }
5162
5163         for_each_encoder_on_crtc(dev, crtc, encoder)
5164                 if (encoder->post_disable)
5165                         encoder->post_disable(encoder);
5166
5167         if (intel_crtc->config->has_pch_encoder)
5168                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5169                                                       true);
5170 }
5171
5172 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5173 {
5174         struct drm_device *dev = crtc->base.dev;
5175         struct drm_i915_private *dev_priv = dev->dev_private;
5176         struct intel_crtc_state *pipe_config = crtc->config;
5177
5178         if (!pipe_config->gmch_pfit.control)
5179                 return;
5180
5181         /*
5182          * The panel fitter should only be adjusted whilst the pipe is disabled,
5183          * according to register description and PRM.
5184          */
5185         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5186         assert_pipe_disabled(dev_priv, crtc->pipe);
5187
5188         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5189         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5190
5191         /* Border color in case we don't scale up to the full screen. Black by
5192          * default, change to something else for debugging. */
5193         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5194 }
5195
5196 static enum intel_display_power_domain port_to_power_domain(enum port port)
5197 {
5198         switch (port) {
5199         case PORT_A:
5200                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5201         case PORT_B:
5202                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5203         case PORT_C:
5204                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5205         case PORT_D:
5206                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5207         case PORT_E:
5208                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5209         default:
5210                 MISSING_CASE(port);
5211                 return POWER_DOMAIN_PORT_OTHER;
5212         }
5213 }
5214
5215 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5216 {
5217         switch (port) {
5218         case PORT_A:
5219                 return POWER_DOMAIN_AUX_A;
5220         case PORT_B:
5221                 return POWER_DOMAIN_AUX_B;
5222         case PORT_C:
5223                 return POWER_DOMAIN_AUX_C;
5224         case PORT_D:
5225                 return POWER_DOMAIN_AUX_D;
5226         case PORT_E:
5227                 /* FIXME: Check VBT for actual wiring of PORT E */
5228                 return POWER_DOMAIN_AUX_D;
5229         default:
5230                 MISSING_CASE(port);
5231                 return POWER_DOMAIN_AUX_A;
5232         }
5233 }
5234
5235 enum intel_display_power_domain
5236 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5237 {
5238         struct drm_device *dev = intel_encoder->base.dev;
5239         struct intel_digital_port *intel_dig_port;
5240
5241         switch (intel_encoder->type) {
5242         case INTEL_OUTPUT_UNKNOWN:
5243                 /* Only DDI platforms should ever use this output type */
5244                 WARN_ON_ONCE(!HAS_DDI(dev));
5245         case INTEL_OUTPUT_DISPLAYPORT:
5246         case INTEL_OUTPUT_HDMI:
5247         case INTEL_OUTPUT_EDP:
5248                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5249                 return port_to_power_domain(intel_dig_port->port);
5250         case INTEL_OUTPUT_DP_MST:
5251                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5252                 return port_to_power_domain(intel_dig_port->port);
5253         case INTEL_OUTPUT_ANALOG:
5254                 return POWER_DOMAIN_PORT_CRT;
5255         case INTEL_OUTPUT_DSI:
5256                 return POWER_DOMAIN_PORT_DSI;
5257         default:
5258                 return POWER_DOMAIN_PORT_OTHER;
5259         }
5260 }
5261
5262 enum intel_display_power_domain
5263 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5264 {
5265         struct drm_device *dev = intel_encoder->base.dev;
5266         struct intel_digital_port *intel_dig_port;
5267
5268         switch (intel_encoder->type) {
5269         case INTEL_OUTPUT_UNKNOWN:
5270         case INTEL_OUTPUT_HDMI:
5271                 /*
5272                  * Only DDI platforms should ever use these output types.
5273                  * We can get here after the HDMI detect code has already set
5274                  * the type of the shared encoder. Since we can't be sure
5275                  * what's the status of the given connectors, play safe and
5276                  * run the DP detection too.
5277                  */
5278                 WARN_ON_ONCE(!HAS_DDI(dev));
5279         case INTEL_OUTPUT_DISPLAYPORT:
5280         case INTEL_OUTPUT_EDP:
5281                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5282                 return port_to_aux_power_domain(intel_dig_port->port);
5283         case INTEL_OUTPUT_DP_MST:
5284                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5285                 return port_to_aux_power_domain(intel_dig_port->port);
5286         default:
5287                 MISSING_CASE(intel_encoder->type);
5288                 return POWER_DOMAIN_AUX_A;
5289         }
5290 }
5291
5292 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5293 {
5294         struct drm_device *dev = crtc->dev;
5295         struct intel_encoder *intel_encoder;
5296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5297         enum pipe pipe = intel_crtc->pipe;
5298         unsigned long mask;
5299         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5300
5301         if (!crtc->state->active)
5302                 return 0;
5303
5304         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5305         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5306         if (intel_crtc->config->pch_pfit.enabled ||
5307             intel_crtc->config->pch_pfit.force_thru)
5308                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5309
5310         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5311                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5312
5313         return mask;
5314 }
5315
5316 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5317 {
5318         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5320         enum intel_display_power_domain domain;
5321         unsigned long domains, new_domains, old_domains;
5322
5323         old_domains = intel_crtc->enabled_power_domains;
5324         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5325
5326         domains = new_domains & ~old_domains;
5327
5328         for_each_power_domain(domain, domains)
5329                 intel_display_power_get(dev_priv, domain);
5330
5331         return old_domains & ~new_domains;
5332 }
5333
5334 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5335                                       unsigned long domains)
5336 {
5337         enum intel_display_power_domain domain;
5338
5339         for_each_power_domain(domain, domains)
5340                 intel_display_power_put(dev_priv, domain);
5341 }
5342
5343 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5344 {
5345         struct drm_device *dev = state->dev;
5346         struct drm_i915_private *dev_priv = dev->dev_private;
5347         unsigned long put_domains[I915_MAX_PIPES] = {};
5348         struct drm_crtc_state *crtc_state;
5349         struct drm_crtc *crtc;
5350         int i;
5351
5352         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5353                 if (needs_modeset(crtc->state))
5354                         put_domains[to_intel_crtc(crtc)->pipe] =
5355                                 modeset_get_crtc_power_domains(crtc);
5356         }
5357
5358         if (dev_priv->display.modeset_commit_cdclk) {
5359                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5360
5361                 if (cdclk != dev_priv->cdclk_freq &&
5362                     !WARN_ON(!state->allow_modeset))
5363                         dev_priv->display.modeset_commit_cdclk(state);
5364         }
5365
5366         for (i = 0; i < I915_MAX_PIPES; i++)
5367                 if (put_domains[i])
5368                         modeset_put_power_domains(dev_priv, put_domains[i]);
5369 }
5370
5371 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5372 {
5373         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5374
5375         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5376             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5377                 return max_cdclk_freq;
5378         else if (IS_CHERRYVIEW(dev_priv))
5379                 return max_cdclk_freq*95/100;
5380         else if (INTEL_INFO(dev_priv)->gen < 4)
5381                 return 2*max_cdclk_freq*90/100;
5382         else
5383                 return max_cdclk_freq*90/100;
5384 }
5385
5386 static void intel_update_max_cdclk(struct drm_device *dev)
5387 {
5388         struct drm_i915_private *dev_priv = dev->dev_private;
5389
5390         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5391                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5392
5393                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5394                         dev_priv->max_cdclk_freq = 675000;
5395                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5396                         dev_priv->max_cdclk_freq = 540000;
5397                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5398                         dev_priv->max_cdclk_freq = 450000;
5399                 else
5400                         dev_priv->max_cdclk_freq = 337500;
5401         } else if (IS_BROADWELL(dev))  {
5402                 /*
5403                  * FIXME with extra cooling we can allow
5404                  * 540 MHz for ULX and 675 Mhz for ULT.
5405                  * How can we know if extra cooling is
5406                  * available? PCI ID, VTB, something else?
5407                  */
5408                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5409                         dev_priv->max_cdclk_freq = 450000;
5410                 else if (IS_BDW_ULX(dev))
5411                         dev_priv->max_cdclk_freq = 450000;
5412                 else if (IS_BDW_ULT(dev))
5413                         dev_priv->max_cdclk_freq = 540000;
5414                 else
5415                         dev_priv->max_cdclk_freq = 675000;
5416         } else if (IS_CHERRYVIEW(dev)) {
5417                 dev_priv->max_cdclk_freq = 320000;
5418         } else if (IS_VALLEYVIEW(dev)) {
5419                 dev_priv->max_cdclk_freq = 400000;
5420         } else {
5421                 /* otherwise assume cdclk is fixed */
5422                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5423         }
5424
5425         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5426
5427         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5428                          dev_priv->max_cdclk_freq);
5429
5430         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5431                          dev_priv->max_dotclk_freq);
5432 }
5433
5434 static void intel_update_cdclk(struct drm_device *dev)
5435 {
5436         struct drm_i915_private *dev_priv = dev->dev_private;
5437
5438         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5439         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5440                          dev_priv->cdclk_freq);
5441
5442         /*
5443          * Program the gmbus_freq based on the cdclk frequency.
5444          * BSpec erroneously claims we should aim for 4MHz, but
5445          * in fact 1MHz is the correct frequency.
5446          */
5447         if (IS_VALLEYVIEW(dev)) {
5448                 /*
5449                  * Program the gmbus_freq based on the cdclk frequency.
5450                  * BSpec erroneously claims we should aim for 4MHz, but
5451                  * in fact 1MHz is the correct frequency.
5452                  */
5453                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5454         }
5455
5456         if (dev_priv->max_cdclk_freq == 0)
5457                 intel_update_max_cdclk(dev);
5458 }
5459
5460 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5461 {
5462         struct drm_i915_private *dev_priv = dev->dev_private;
5463         uint32_t divider;
5464         uint32_t ratio;
5465         uint32_t current_freq;
5466         int ret;
5467
5468         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5469         switch (frequency) {
5470         case 144000:
5471                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5472                 ratio = BXT_DE_PLL_RATIO(60);
5473                 break;
5474         case 288000:
5475                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5476                 ratio = BXT_DE_PLL_RATIO(60);
5477                 break;
5478         case 384000:
5479                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5480                 ratio = BXT_DE_PLL_RATIO(60);
5481                 break;
5482         case 576000:
5483                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5484                 ratio = BXT_DE_PLL_RATIO(60);
5485                 break;
5486         case 624000:
5487                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5488                 ratio = BXT_DE_PLL_RATIO(65);
5489                 break;
5490         case 19200:
5491                 /*
5492                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5493                  * to suppress GCC warning.
5494                  */
5495                 ratio = 0;
5496                 divider = 0;
5497                 break;
5498         default:
5499                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5500
5501                 return;
5502         }
5503
5504         mutex_lock(&dev_priv->rps.hw_lock);
5505         /* Inform power controller of upcoming frequency change */
5506         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5507                                       0x80000000);
5508         mutex_unlock(&dev_priv->rps.hw_lock);
5509
5510         if (ret) {
5511                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5512                           ret, frequency);
5513                 return;
5514         }
5515
5516         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5517         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5518         current_freq = current_freq * 500 + 1000;
5519
5520         /*
5521          * DE PLL has to be disabled when
5522          * - setting to 19.2MHz (bypass, PLL isn't used)
5523          * - before setting to 624MHz (PLL needs toggling)
5524          * - before setting to any frequency from 624MHz (PLL needs toggling)
5525          */
5526         if (frequency == 19200 || frequency == 624000 ||
5527             current_freq == 624000) {
5528                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5529                 /* Timeout 200us */
5530                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5531                              1))
5532                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5533         }
5534
5535         if (frequency != 19200) {
5536                 uint32_t val;
5537
5538                 val = I915_READ(BXT_DE_PLL_CTL);
5539                 val &= ~BXT_DE_PLL_RATIO_MASK;
5540                 val |= ratio;
5541                 I915_WRITE(BXT_DE_PLL_CTL, val);
5542
5543                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5544                 /* Timeout 200us */
5545                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5546                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5547
5548                 val = I915_READ(CDCLK_CTL);
5549                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5550                 val |= divider;
5551                 /*
5552                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5553                  * enable otherwise.
5554                  */
5555                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5556                 if (frequency >= 500000)
5557                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5558
5559                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5560                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5561                 val |= (frequency - 1000) / 500;
5562                 I915_WRITE(CDCLK_CTL, val);
5563         }
5564
5565         mutex_lock(&dev_priv->rps.hw_lock);
5566         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5567                                       DIV_ROUND_UP(frequency, 25000));
5568         mutex_unlock(&dev_priv->rps.hw_lock);
5569
5570         if (ret) {
5571                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5572                           ret, frequency);
5573                 return;
5574         }
5575
5576         intel_update_cdclk(dev);
5577 }
5578
5579 void broxton_init_cdclk(struct drm_device *dev)
5580 {
5581         struct drm_i915_private *dev_priv = dev->dev_private;
5582         uint32_t val;
5583
5584         /*
5585          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5586          * or else the reset will hang because there is no PCH to respond.
5587          * Move the handshake programming to initialization sequence.
5588          * Previously was left up to BIOS.
5589          */
5590         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5591         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5592         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5593
5594         /* Enable PG1 for cdclk */
5595         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5596
5597         /* check if cd clock is enabled */
5598         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5599                 DRM_DEBUG_KMS("Display already initialized\n");
5600                 return;
5601         }
5602
5603         /*
5604          * FIXME:
5605          * - The initial CDCLK needs to be read from VBT.
5606          *   Need to make this change after VBT has changes for BXT.
5607          * - check if setting the max (or any) cdclk freq is really necessary
5608          *   here, it belongs to modeset time
5609          */
5610         broxton_set_cdclk(dev, 624000);
5611
5612         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5613         POSTING_READ(DBUF_CTL);
5614
5615         udelay(10);
5616
5617         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5618                 DRM_ERROR("DBuf power enable timeout!\n");
5619 }
5620
5621 void broxton_uninit_cdclk(struct drm_device *dev)
5622 {
5623         struct drm_i915_private *dev_priv = dev->dev_private;
5624
5625         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5626         POSTING_READ(DBUF_CTL);
5627
5628         udelay(10);
5629
5630         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5631                 DRM_ERROR("DBuf power disable timeout!\n");
5632
5633         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5634         broxton_set_cdclk(dev, 19200);
5635
5636         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5637 }
5638
5639 static const struct skl_cdclk_entry {
5640         unsigned int freq;
5641         unsigned int vco;
5642 } skl_cdclk_frequencies[] = {
5643         { .freq = 308570, .vco = 8640 },
5644         { .freq = 337500, .vco = 8100 },
5645         { .freq = 432000, .vco = 8640 },
5646         { .freq = 450000, .vco = 8100 },
5647         { .freq = 540000, .vco = 8100 },
5648         { .freq = 617140, .vco = 8640 },
5649         { .freq = 675000, .vco = 8100 },
5650 };
5651
5652 static unsigned int skl_cdclk_decimal(unsigned int freq)
5653 {
5654         return (freq - 1000) / 500;
5655 }
5656
5657 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5658 {
5659         unsigned int i;
5660
5661         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5662                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5663
5664                 if (e->freq == freq)
5665                         return e->vco;
5666         }
5667
5668         return 8100;
5669 }
5670
5671 static void
5672 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5673 {
5674         unsigned int min_freq;
5675         u32 val;
5676
5677         /* select the minimum CDCLK before enabling DPLL 0 */
5678         val = I915_READ(CDCLK_CTL);
5679         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5680         val |= CDCLK_FREQ_337_308;
5681
5682         if (required_vco == 8640)
5683                 min_freq = 308570;
5684         else
5685                 min_freq = 337500;
5686
5687         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5688
5689         I915_WRITE(CDCLK_CTL, val);
5690         POSTING_READ(CDCLK_CTL);
5691
5692         /*
5693          * We always enable DPLL0 with the lowest link rate possible, but still
5694          * taking into account the VCO required to operate the eDP panel at the
5695          * desired frequency. The usual DP link rates operate with a VCO of
5696          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5697          * The modeset code is responsible for the selection of the exact link
5698          * rate later on, with the constraint of choosing a frequency that
5699          * works with required_vco.
5700          */
5701         val = I915_READ(DPLL_CTRL1);
5702
5703         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5704                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5705         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5706         if (required_vco == 8640)
5707                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5708                                             SKL_DPLL0);
5709         else
5710                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5711                                             SKL_DPLL0);
5712
5713         I915_WRITE(DPLL_CTRL1, val);
5714         POSTING_READ(DPLL_CTRL1);
5715
5716         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5717
5718         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5719                 DRM_ERROR("DPLL0 not locked\n");
5720 }
5721
5722 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5723 {
5724         int ret;
5725         u32 val;
5726
5727         /* inform PCU we want to change CDCLK */
5728         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5729         mutex_lock(&dev_priv->rps.hw_lock);
5730         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5731         mutex_unlock(&dev_priv->rps.hw_lock);
5732
5733         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5734 }
5735
5736 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5737 {
5738         unsigned int i;
5739
5740         for (i = 0; i < 15; i++) {
5741                 if (skl_cdclk_pcu_ready(dev_priv))
5742                         return true;
5743                 udelay(10);
5744         }
5745
5746         return false;
5747 }
5748
5749 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5750 {
5751         struct drm_device *dev = dev_priv->dev;
5752         u32 freq_select, pcu_ack;
5753
5754         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5755
5756         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5757                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5758                 return;
5759         }
5760
5761         /* set CDCLK_CTL */
5762         switch(freq) {
5763         case 450000:
5764         case 432000:
5765                 freq_select = CDCLK_FREQ_450_432;
5766                 pcu_ack = 1;
5767                 break;
5768         case 540000:
5769                 freq_select = CDCLK_FREQ_540;
5770                 pcu_ack = 2;
5771                 break;
5772         case 308570:
5773         case 337500:
5774         default:
5775                 freq_select = CDCLK_FREQ_337_308;
5776                 pcu_ack = 0;
5777                 break;
5778         case 617140:
5779         case 675000:
5780                 freq_select = CDCLK_FREQ_675_617;
5781                 pcu_ack = 3;
5782                 break;
5783         }
5784
5785         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5786         POSTING_READ(CDCLK_CTL);
5787
5788         /* inform PCU of the change */
5789         mutex_lock(&dev_priv->rps.hw_lock);
5790         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5791         mutex_unlock(&dev_priv->rps.hw_lock);
5792
5793         intel_update_cdclk(dev);
5794 }
5795
5796 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5797 {
5798         /* disable DBUF power */
5799         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5800         POSTING_READ(DBUF_CTL);
5801
5802         udelay(10);
5803
5804         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5805                 DRM_ERROR("DBuf power disable timeout\n");
5806
5807         /* disable DPLL0 */
5808         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5809         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5810                 DRM_ERROR("Couldn't disable DPLL0\n");
5811 }
5812
5813 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5814 {
5815         unsigned int required_vco;
5816
5817         /* DPLL0 not enabled (happens on early BIOS versions) */
5818         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5819                 /* enable DPLL0 */
5820                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5821                 skl_dpll0_enable(dev_priv, required_vco);
5822         }
5823
5824         /* set CDCLK to the frequency the BIOS chose */
5825         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5826
5827         /* enable DBUF power */
5828         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5829         POSTING_READ(DBUF_CTL);
5830
5831         udelay(10);
5832
5833         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5834                 DRM_ERROR("DBuf power enable timeout\n");
5835 }
5836
5837 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5838 {
5839         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5840         uint32_t cdctl = I915_READ(CDCLK_CTL);
5841         int freq = dev_priv->skl_boot_cdclk;
5842
5843         /*
5844          * check if the pre-os intialized the display
5845          * There is SWF18 scratchpad register defined which is set by the
5846          * pre-os which can be used by the OS drivers to check the status
5847          */
5848         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5849                 goto sanitize;
5850
5851         /* Is PLL enabled and locked ? */
5852         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5853                 goto sanitize;
5854
5855         /* DPLL okay; verify the cdclock
5856          *
5857          * Noticed in some instances that the freq selection is correct but
5858          * decimal part is programmed wrong from BIOS where pre-os does not
5859          * enable display. Verify the same as well.
5860          */
5861         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5862                 /* All well; nothing to sanitize */
5863                 return false;
5864 sanitize:
5865         /*
5866          * As of now initialize with max cdclk till
5867          * we get dynamic cdclk support
5868          * */
5869         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5870         skl_init_cdclk(dev_priv);
5871
5872         /* we did have to sanitize */
5873         return true;
5874 }
5875
5876 /* Adjust CDclk dividers to allow high res or save power if possible */
5877 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5878 {
5879         struct drm_i915_private *dev_priv = dev->dev_private;
5880         u32 val, cmd;
5881
5882         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5883                                         != dev_priv->cdclk_freq);
5884
5885         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5886                 cmd = 2;
5887         else if (cdclk == 266667)
5888                 cmd = 1;
5889         else
5890                 cmd = 0;
5891
5892         mutex_lock(&dev_priv->rps.hw_lock);
5893         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5894         val &= ~DSPFREQGUAR_MASK;
5895         val |= (cmd << DSPFREQGUAR_SHIFT);
5896         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5897         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5898                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5899                      50)) {
5900                 DRM_ERROR("timed out waiting for CDclk change\n");
5901         }
5902         mutex_unlock(&dev_priv->rps.hw_lock);
5903
5904         mutex_lock(&dev_priv->sb_lock);
5905
5906         if (cdclk == 400000) {
5907                 u32 divider;
5908
5909                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5910
5911                 /* adjust cdclk divider */
5912                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5913                 val &= ~CCK_FREQUENCY_VALUES;
5914                 val |= divider;
5915                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5916
5917                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5918                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5919                              50))
5920                         DRM_ERROR("timed out waiting for CDclk change\n");
5921         }
5922
5923         /* adjust self-refresh exit latency value */
5924         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5925         val &= ~0x7f;
5926
5927         /*
5928          * For high bandwidth configs, we set a higher latency in the bunit
5929          * so that the core display fetch happens in time to avoid underruns.
5930          */
5931         if (cdclk == 400000)
5932                 val |= 4500 / 250; /* 4.5 usec */
5933         else
5934                 val |= 3000 / 250; /* 3.0 usec */
5935         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5936
5937         mutex_unlock(&dev_priv->sb_lock);
5938
5939         intel_update_cdclk(dev);
5940 }
5941
5942 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5943 {
5944         struct drm_i915_private *dev_priv = dev->dev_private;
5945         u32 val, cmd;
5946
5947         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5948                                                 != dev_priv->cdclk_freq);
5949
5950         switch (cdclk) {
5951         case 333333:
5952         case 320000:
5953         case 266667:
5954         case 200000:
5955                 break;
5956         default:
5957                 MISSING_CASE(cdclk);
5958                 return;
5959         }
5960
5961         /*
5962          * Specs are full of misinformation, but testing on actual
5963          * hardware has shown that we just need to write the desired
5964          * CCK divider into the Punit register.
5965          */
5966         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5967
5968         mutex_lock(&dev_priv->rps.hw_lock);
5969         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5970         val &= ~DSPFREQGUAR_MASK_CHV;
5971         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5972         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5973         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5974                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5975                      50)) {
5976                 DRM_ERROR("timed out waiting for CDclk change\n");
5977         }
5978         mutex_unlock(&dev_priv->rps.hw_lock);
5979
5980         intel_update_cdclk(dev);
5981 }
5982
5983 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5984                                  int max_pixclk)
5985 {
5986         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5987         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5988
5989         /*
5990          * Really only a few cases to deal with, as only 4 CDclks are supported:
5991          *   200MHz
5992          *   267MHz
5993          *   320/333MHz (depends on HPLL freq)
5994          *   400MHz (VLV only)
5995          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5996          * of the lower bin and adjust if needed.
5997          *
5998          * We seem to get an unstable or solid color picture at 200MHz.
5999          * Not sure what's wrong. For now use 200MHz only when all pipes
6000          * are off.
6001          */
6002         if (!IS_CHERRYVIEW(dev_priv) &&
6003             max_pixclk > freq_320*limit/100)
6004                 return 400000;
6005         else if (max_pixclk > 266667*limit/100)
6006                 return freq_320;
6007         else if (max_pixclk > 0)
6008                 return 266667;
6009         else
6010                 return 200000;
6011 }
6012
6013 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6014                               int max_pixclk)
6015 {
6016         /*
6017          * FIXME:
6018          * - remove the guardband, it's not needed on BXT
6019          * - set 19.2MHz bypass frequency if there are no active pipes
6020          */
6021         if (max_pixclk > 576000*9/10)
6022                 return 624000;
6023         else if (max_pixclk > 384000*9/10)
6024                 return 576000;
6025         else if (max_pixclk > 288000*9/10)
6026                 return 384000;
6027         else if (max_pixclk > 144000*9/10)
6028                 return 288000;
6029         else
6030                 return 144000;
6031 }
6032
6033 /* Compute the max pixel clock for new configuration. Uses atomic state if
6034  * that's non-NULL, look at current state otherwise. */
6035 static int intel_mode_max_pixclk(struct drm_device *dev,
6036                                  struct drm_atomic_state *state)
6037 {
6038         struct intel_crtc *intel_crtc;
6039         struct intel_crtc_state *crtc_state;
6040         int max_pixclk = 0;
6041
6042         for_each_intel_crtc(dev, intel_crtc) {
6043                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6044                 if (IS_ERR(crtc_state))
6045                         return PTR_ERR(crtc_state);
6046
6047                 if (!crtc_state->base.enable)
6048                         continue;
6049
6050                 max_pixclk = max(max_pixclk,
6051                                  crtc_state->base.adjusted_mode.crtc_clock);
6052         }
6053
6054         return max_pixclk;
6055 }
6056
6057 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6058 {
6059         struct drm_device *dev = state->dev;
6060         struct drm_i915_private *dev_priv = dev->dev_private;
6061         int max_pixclk = intel_mode_max_pixclk(dev, state);
6062
6063         if (max_pixclk < 0)
6064                 return max_pixclk;
6065
6066         to_intel_atomic_state(state)->cdclk =
6067                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6068
6069         return 0;
6070 }
6071
6072 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6073 {
6074         struct drm_device *dev = state->dev;
6075         struct drm_i915_private *dev_priv = dev->dev_private;
6076         int max_pixclk = intel_mode_max_pixclk(dev, state);
6077
6078         if (max_pixclk < 0)
6079                 return max_pixclk;
6080
6081         to_intel_atomic_state(state)->cdclk =
6082                 broxton_calc_cdclk(dev_priv, max_pixclk);
6083
6084         return 0;
6085 }
6086
6087 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6088 {
6089         unsigned int credits, default_credits;
6090
6091         if (IS_CHERRYVIEW(dev_priv))
6092                 default_credits = PFI_CREDIT(12);
6093         else
6094                 default_credits = PFI_CREDIT(8);
6095
6096         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6097                 /* CHV suggested value is 31 or 63 */
6098                 if (IS_CHERRYVIEW(dev_priv))
6099                         credits = PFI_CREDIT_63;
6100                 else
6101                         credits = PFI_CREDIT(15);
6102         } else {
6103                 credits = default_credits;
6104         }
6105
6106         /*
6107          * WA - write default credits before re-programming
6108          * FIXME: should we also set the resend bit here?
6109          */
6110         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6111                    default_credits);
6112
6113         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6114                    credits | PFI_CREDIT_RESEND);
6115
6116         /*
6117          * FIXME is this guaranteed to clear
6118          * immediately or should we poll for it?
6119          */
6120         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6121 }
6122
6123 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6124 {
6125         struct drm_device *dev = old_state->dev;
6126         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128
6129         /*
6130          * FIXME: We can end up here with all power domains off, yet
6131          * with a CDCLK frequency other than the minimum. To account
6132          * for this take the PIPE-A power domain, which covers the HW
6133          * blocks needed for the following programming. This can be
6134          * removed once it's guaranteed that we get here either with
6135          * the minimum CDCLK set, or the required power domains
6136          * enabled.
6137          */
6138         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6139
6140         if (IS_CHERRYVIEW(dev))
6141                 cherryview_set_cdclk(dev, req_cdclk);
6142         else
6143                 valleyview_set_cdclk(dev, req_cdclk);
6144
6145         vlv_program_pfi_credits(dev_priv);
6146
6147         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6148 }
6149
6150 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6151 {
6152         struct drm_device *dev = crtc->dev;
6153         struct drm_i915_private *dev_priv = to_i915(dev);
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         struct intel_encoder *encoder;
6156         int pipe = intel_crtc->pipe;
6157         bool is_dsi;
6158
6159         if (WARN_ON(intel_crtc->active))
6160                 return;
6161
6162         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6163
6164         if (intel_crtc->config->has_dp_encoder)
6165                 intel_dp_set_m_n(intel_crtc, M1_N1);
6166
6167         intel_set_pipe_timings(intel_crtc);
6168
6169         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6170                 struct drm_i915_private *dev_priv = dev->dev_private;
6171
6172                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6173                 I915_WRITE(CHV_CANVAS(pipe), 0);
6174         }
6175
6176         i9xx_set_pipeconf(intel_crtc);
6177
6178         intel_crtc->active = true;
6179
6180         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6181
6182         for_each_encoder_on_crtc(dev, crtc, encoder)
6183                 if (encoder->pre_pll_enable)
6184                         encoder->pre_pll_enable(encoder);
6185
6186         if (!is_dsi) {
6187                 if (IS_CHERRYVIEW(dev)) {
6188                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6189                         chv_enable_pll(intel_crtc, intel_crtc->config);
6190                 } else {
6191                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6192                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6193                 }
6194         }
6195
6196         for_each_encoder_on_crtc(dev, crtc, encoder)
6197                 if (encoder->pre_enable)
6198                         encoder->pre_enable(encoder);
6199
6200         i9xx_pfit_enable(intel_crtc);
6201
6202         intel_crtc_load_lut(crtc);
6203
6204         intel_enable_pipe(intel_crtc);
6205
6206         assert_vblank_disabled(crtc);
6207         drm_crtc_vblank_on(crtc);
6208
6209         for_each_encoder_on_crtc(dev, crtc, encoder)
6210                 encoder->enable(encoder);
6211 }
6212
6213 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6214 {
6215         struct drm_device *dev = crtc->base.dev;
6216         struct drm_i915_private *dev_priv = dev->dev_private;
6217
6218         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6219         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6220 }
6221
6222 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6223 {
6224         struct drm_device *dev = crtc->dev;
6225         struct drm_i915_private *dev_priv = to_i915(dev);
6226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6227         struct intel_encoder *encoder;
6228         int pipe = intel_crtc->pipe;
6229
6230         if (WARN_ON(intel_crtc->active))
6231                 return;
6232
6233         i9xx_set_pll_dividers(intel_crtc);
6234
6235         if (intel_crtc->config->has_dp_encoder)
6236                 intel_dp_set_m_n(intel_crtc, M1_N1);
6237
6238         intel_set_pipe_timings(intel_crtc);
6239
6240         i9xx_set_pipeconf(intel_crtc);
6241
6242         intel_crtc->active = true;
6243
6244         if (!IS_GEN2(dev))
6245                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6246
6247         for_each_encoder_on_crtc(dev, crtc, encoder)
6248                 if (encoder->pre_enable)
6249                         encoder->pre_enable(encoder);
6250
6251         i9xx_enable_pll(intel_crtc);
6252
6253         i9xx_pfit_enable(intel_crtc);
6254
6255         intel_crtc_load_lut(crtc);
6256
6257         intel_update_watermarks(crtc);
6258         intel_enable_pipe(intel_crtc);
6259
6260         assert_vblank_disabled(crtc);
6261         drm_crtc_vblank_on(crtc);
6262
6263         for_each_encoder_on_crtc(dev, crtc, encoder)
6264                 encoder->enable(encoder);
6265 }
6266
6267 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6268 {
6269         struct drm_device *dev = crtc->base.dev;
6270         struct drm_i915_private *dev_priv = dev->dev_private;
6271
6272         if (!crtc->config->gmch_pfit.control)
6273                 return;
6274
6275         assert_pipe_disabled(dev_priv, crtc->pipe);
6276
6277         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6278                          I915_READ(PFIT_CONTROL));
6279         I915_WRITE(PFIT_CONTROL, 0);
6280 }
6281
6282 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6283 {
6284         struct drm_device *dev = crtc->dev;
6285         struct drm_i915_private *dev_priv = dev->dev_private;
6286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6287         struct intel_encoder *encoder;
6288         int pipe = intel_crtc->pipe;
6289
6290         /*
6291          * On gen2 planes are double buffered but the pipe isn't, so we must
6292          * wait for planes to fully turn off before disabling the pipe.
6293          * We also need to wait on all gmch platforms because of the
6294          * self-refresh mode constraint explained above.
6295          */
6296         intel_wait_for_vblank(dev, pipe);
6297
6298         for_each_encoder_on_crtc(dev, crtc, encoder)
6299                 encoder->disable(encoder);
6300
6301         drm_crtc_vblank_off(crtc);
6302         assert_vblank_disabled(crtc);
6303
6304         intel_disable_pipe(intel_crtc);
6305
6306         i9xx_pfit_disable(intel_crtc);
6307
6308         for_each_encoder_on_crtc(dev, crtc, encoder)
6309                 if (encoder->post_disable)
6310                         encoder->post_disable(encoder);
6311
6312         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6313                 if (IS_CHERRYVIEW(dev))
6314                         chv_disable_pll(dev_priv, pipe);
6315                 else if (IS_VALLEYVIEW(dev))
6316                         vlv_disable_pll(dev_priv, pipe);
6317                 else
6318                         i9xx_disable_pll(intel_crtc);
6319         }
6320
6321         for_each_encoder_on_crtc(dev, crtc, encoder)
6322                 if (encoder->post_pll_disable)
6323                         encoder->post_pll_disable(encoder);
6324
6325         if (!IS_GEN2(dev))
6326                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6327 }
6328
6329 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6330 {
6331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6332         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6333         enum intel_display_power_domain domain;
6334         unsigned long domains;
6335
6336         if (!intel_crtc->active)
6337                 return;
6338
6339         if (to_intel_plane_state(crtc->primary->state)->visible) {
6340                 WARN_ON(intel_crtc->unpin_work);
6341
6342                 intel_pre_disable_primary(crtc);
6343         }
6344
6345         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6346         dev_priv->display.crtc_disable(crtc);
6347         intel_crtc->active = false;
6348         intel_update_watermarks(crtc);
6349         intel_disable_shared_dpll(intel_crtc);
6350
6351         domains = intel_crtc->enabled_power_domains;
6352         for_each_power_domain(domain, domains)
6353                 intel_display_power_put(dev_priv, domain);
6354         intel_crtc->enabled_power_domains = 0;
6355 }
6356
6357 /*
6358  * turn all crtc's off, but do not adjust state
6359  * This has to be paired with a call to intel_modeset_setup_hw_state.
6360  */
6361 int intel_display_suspend(struct drm_device *dev)
6362 {
6363         struct drm_mode_config *config = &dev->mode_config;
6364         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6365         struct drm_atomic_state *state;
6366         struct drm_crtc *crtc;
6367         unsigned crtc_mask = 0;
6368         int ret = 0;
6369
6370         if (WARN_ON(!ctx))
6371                 return 0;
6372
6373         lockdep_assert_held(&ctx->ww_ctx);
6374         state = drm_atomic_state_alloc(dev);
6375         if (WARN_ON(!state))
6376                 return -ENOMEM;
6377
6378         state->acquire_ctx = ctx;
6379         state->allow_modeset = true;
6380
6381         for_each_crtc(dev, crtc) {
6382                 struct drm_crtc_state *crtc_state =
6383                         drm_atomic_get_crtc_state(state, crtc);
6384
6385                 ret = PTR_ERR_OR_ZERO(crtc_state);
6386                 if (ret)
6387                         goto free;
6388
6389                 if (!crtc_state->active)
6390                         continue;
6391
6392                 crtc_state->active = false;
6393                 crtc_mask |= 1 << drm_crtc_index(crtc);
6394         }
6395
6396         if (crtc_mask) {
6397                 ret = drm_atomic_commit(state);
6398
6399                 if (!ret) {
6400                         for_each_crtc(dev, crtc)
6401                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6402                                         crtc->state->active = true;
6403
6404                         return ret;
6405                 }
6406         }
6407
6408 free:
6409         if (ret)
6410                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6411         drm_atomic_state_free(state);
6412         return ret;
6413 }
6414
6415 void intel_encoder_destroy(struct drm_encoder *encoder)
6416 {
6417         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6418
6419         drm_encoder_cleanup(encoder);
6420         kfree(intel_encoder);
6421 }
6422
6423 /* Cross check the actual hw state with our own modeset state tracking (and it's
6424  * internal consistency). */
6425 static void intel_connector_check_state(struct intel_connector *connector)
6426 {
6427         struct drm_crtc *crtc = connector->base.state->crtc;
6428
6429         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6430                       connector->base.base.id,
6431                       connector->base.name);
6432
6433         if (connector->get_hw_state(connector)) {
6434                 struct intel_encoder *encoder = connector->encoder;
6435                 struct drm_connector_state *conn_state = connector->base.state;
6436
6437                 I915_STATE_WARN(!crtc,
6438                          "connector enabled without attached crtc\n");
6439
6440                 if (!crtc)
6441                         return;
6442
6443                 I915_STATE_WARN(!crtc->state->active,
6444                       "connector is active, but attached crtc isn't\n");
6445
6446                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6447                         return;
6448
6449                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6450                         "atomic encoder doesn't match attached encoder\n");
6451
6452                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6453                         "attached encoder crtc differs from connector crtc\n");
6454         } else {
6455                 I915_STATE_WARN(crtc && crtc->state->active,
6456                         "attached crtc is active, but connector isn't\n");
6457                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6458                         "best encoder set without crtc!\n");
6459         }
6460 }
6461
6462 int intel_connector_init(struct intel_connector *connector)
6463 {
6464         struct drm_connector_state *connector_state;
6465
6466         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6467         if (!connector_state)
6468                 return -ENOMEM;
6469
6470         connector->base.state = connector_state;
6471         return 0;
6472 }
6473
6474 struct intel_connector *intel_connector_alloc(void)
6475 {
6476         struct intel_connector *connector;
6477
6478         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6479         if (!connector)
6480                 return NULL;
6481
6482         if (intel_connector_init(connector) < 0) {
6483                 kfree(connector);
6484                 return NULL;
6485         }
6486
6487         return connector;
6488 }
6489
6490 /* Simple connector->get_hw_state implementation for encoders that support only
6491  * one connector and no cloning and hence the encoder state determines the state
6492  * of the connector. */
6493 bool intel_connector_get_hw_state(struct intel_connector *connector)
6494 {
6495         enum pipe pipe = 0;
6496         struct intel_encoder *encoder = connector->encoder;
6497
6498         return encoder->get_hw_state(encoder, &pipe);
6499 }
6500
6501 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6502 {
6503         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6504                 return crtc_state->fdi_lanes;
6505
6506         return 0;
6507 }
6508
6509 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6510                                      struct intel_crtc_state *pipe_config)
6511 {
6512         struct drm_atomic_state *state = pipe_config->base.state;
6513         struct intel_crtc *other_crtc;
6514         struct intel_crtc_state *other_crtc_state;
6515
6516         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6517                       pipe_name(pipe), pipe_config->fdi_lanes);
6518         if (pipe_config->fdi_lanes > 4) {
6519                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6520                               pipe_name(pipe), pipe_config->fdi_lanes);
6521                 return -EINVAL;
6522         }
6523
6524         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6525                 if (pipe_config->fdi_lanes > 2) {
6526                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6527                                       pipe_config->fdi_lanes);
6528                         return -EINVAL;
6529                 } else {
6530                         return 0;
6531                 }
6532         }
6533
6534         if (INTEL_INFO(dev)->num_pipes == 2)
6535                 return 0;
6536
6537         /* Ivybridge 3 pipe is really complicated */
6538         switch (pipe) {
6539         case PIPE_A:
6540                 return 0;
6541         case PIPE_B:
6542                 if (pipe_config->fdi_lanes <= 2)
6543                         return 0;
6544
6545                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6546                 other_crtc_state =
6547                         intel_atomic_get_crtc_state(state, other_crtc);
6548                 if (IS_ERR(other_crtc_state))
6549                         return PTR_ERR(other_crtc_state);
6550
6551                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6552                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6553                                       pipe_name(pipe), pipe_config->fdi_lanes);
6554                         return -EINVAL;
6555                 }
6556                 return 0;
6557         case PIPE_C:
6558                 if (pipe_config->fdi_lanes > 2) {
6559                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6560                                       pipe_name(pipe), pipe_config->fdi_lanes);
6561                         return -EINVAL;
6562                 }
6563
6564                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6565                 other_crtc_state =
6566                         intel_atomic_get_crtc_state(state, other_crtc);
6567                 if (IS_ERR(other_crtc_state))
6568                         return PTR_ERR(other_crtc_state);
6569
6570                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6571                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6572                         return -EINVAL;
6573                 }
6574                 return 0;
6575         default:
6576                 BUG();
6577         }
6578 }
6579
6580 #define RETRY 1
6581 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6582                                        struct intel_crtc_state *pipe_config)
6583 {
6584         struct drm_device *dev = intel_crtc->base.dev;
6585         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6586         int lane, link_bw, fdi_dotclock, ret;
6587         bool needs_recompute = false;
6588
6589 retry:
6590         /* FDI is a binary signal running at ~2.7GHz, encoding
6591          * each output octet as 10 bits. The actual frequency
6592          * is stored as a divider into a 100MHz clock, and the
6593          * mode pixel clock is stored in units of 1KHz.
6594          * Hence the bw of each lane in terms of the mode signal
6595          * is:
6596          */
6597         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6598
6599         fdi_dotclock = adjusted_mode->crtc_clock;
6600
6601         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6602                                            pipe_config->pipe_bpp);
6603
6604         pipe_config->fdi_lanes = lane;
6605
6606         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6607                                link_bw, &pipe_config->fdi_m_n);
6608
6609         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6610                                        intel_crtc->pipe, pipe_config);
6611         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6612                 pipe_config->pipe_bpp -= 2*3;
6613                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6614                               pipe_config->pipe_bpp);
6615                 needs_recompute = true;
6616                 pipe_config->bw_constrained = true;
6617
6618                 goto retry;
6619         }
6620
6621         if (needs_recompute)
6622                 return RETRY;
6623
6624         return ret;
6625 }
6626
6627 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6628                                      struct intel_crtc_state *pipe_config)
6629 {
6630         if (pipe_config->pipe_bpp > 24)
6631                 return false;
6632
6633         /* HSW can handle pixel rate up to cdclk? */
6634         if (IS_HASWELL(dev_priv->dev))
6635                 return true;
6636
6637         /*
6638          * We compare against max which means we must take
6639          * the increased cdclk requirement into account when
6640          * calculating the new cdclk.
6641          *
6642          * Should measure whether using a lower cdclk w/o IPS
6643          */
6644         return ilk_pipe_pixel_rate(pipe_config) <=
6645                 dev_priv->max_cdclk_freq * 95 / 100;
6646 }
6647
6648 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6649                                    struct intel_crtc_state *pipe_config)
6650 {
6651         struct drm_device *dev = crtc->base.dev;
6652         struct drm_i915_private *dev_priv = dev->dev_private;
6653
6654         pipe_config->ips_enabled = i915.enable_ips &&
6655                 hsw_crtc_supports_ips(crtc) &&
6656                 pipe_config_supports_ips(dev_priv, pipe_config);
6657 }
6658
6659 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6660 {
6661         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6662
6663         /* GDG double wide on either pipe, otherwise pipe A only */
6664         return INTEL_INFO(dev_priv)->gen < 4 &&
6665                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6666 }
6667
6668 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6669                                      struct intel_crtc_state *pipe_config)
6670 {
6671         struct drm_device *dev = crtc->base.dev;
6672         struct drm_i915_private *dev_priv = dev->dev_private;
6673         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6674
6675         /* FIXME should check pixel clock limits on all platforms */
6676         if (INTEL_INFO(dev)->gen < 4) {
6677                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6678
6679                 /*
6680                  * Enable double wide mode when the dot clock
6681                  * is > 90% of the (display) core speed.
6682                  */
6683                 if (intel_crtc_supports_double_wide(crtc) &&
6684                     adjusted_mode->crtc_clock > clock_limit) {
6685                         clock_limit *= 2;
6686                         pipe_config->double_wide = true;
6687                 }
6688
6689                 if (adjusted_mode->crtc_clock > clock_limit) {
6690                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6691                                       adjusted_mode->crtc_clock, clock_limit,
6692                                       yesno(pipe_config->double_wide));
6693                         return -EINVAL;
6694                 }
6695         }
6696
6697         /*
6698          * Pipe horizontal size must be even in:
6699          * - DVO ganged mode
6700          * - LVDS dual channel mode
6701          * - Double wide pipe
6702          */
6703         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6704              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6705                 pipe_config->pipe_src_w &= ~1;
6706
6707         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6708          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6709          */
6710         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6711                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6712                 return -EINVAL;
6713
6714         if (HAS_IPS(dev))
6715                 hsw_compute_ips_config(crtc, pipe_config);
6716
6717         if (pipe_config->has_pch_encoder)
6718                 return ironlake_fdi_compute_config(crtc, pipe_config);
6719
6720         return 0;
6721 }
6722
6723 static int skylake_get_display_clock_speed(struct drm_device *dev)
6724 {
6725         struct drm_i915_private *dev_priv = to_i915(dev);
6726         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6727         uint32_t cdctl = I915_READ(CDCLK_CTL);
6728         uint32_t linkrate;
6729
6730         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6731                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6732
6733         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6734                 return 540000;
6735
6736         linkrate = (I915_READ(DPLL_CTRL1) &
6737                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6738
6739         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6740             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6741                 /* vco 8640 */
6742                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6743                 case CDCLK_FREQ_450_432:
6744                         return 432000;
6745                 case CDCLK_FREQ_337_308:
6746                         return 308570;
6747                 case CDCLK_FREQ_675_617:
6748                         return 617140;
6749                 default:
6750                         WARN(1, "Unknown cd freq selection\n");
6751                 }
6752         } else {
6753                 /* vco 8100 */
6754                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6755                 case CDCLK_FREQ_450_432:
6756                         return 450000;
6757                 case CDCLK_FREQ_337_308:
6758                         return 337500;
6759                 case CDCLK_FREQ_675_617:
6760                         return 675000;
6761                 default:
6762                         WARN(1, "Unknown cd freq selection\n");
6763                 }
6764         }
6765
6766         /* error case, do as if DPLL0 isn't enabled */
6767         return 24000;
6768 }
6769
6770 static int broxton_get_display_clock_speed(struct drm_device *dev)
6771 {
6772         struct drm_i915_private *dev_priv = to_i915(dev);
6773         uint32_t cdctl = I915_READ(CDCLK_CTL);
6774         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6775         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6776         int cdclk;
6777
6778         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6779                 return 19200;
6780
6781         cdclk = 19200 * pll_ratio / 2;
6782
6783         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6784         case BXT_CDCLK_CD2X_DIV_SEL_1:
6785                 return cdclk;  /* 576MHz or 624MHz */
6786         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6787                 return cdclk * 2 / 3; /* 384MHz */
6788         case BXT_CDCLK_CD2X_DIV_SEL_2:
6789                 return cdclk / 2; /* 288MHz */
6790         case BXT_CDCLK_CD2X_DIV_SEL_4:
6791                 return cdclk / 4; /* 144MHz */
6792         }
6793
6794         /* error case, do as if DE PLL isn't enabled */
6795         return 19200;
6796 }
6797
6798 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6799 {
6800         struct drm_i915_private *dev_priv = dev->dev_private;
6801         uint32_t lcpll = I915_READ(LCPLL_CTL);
6802         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6803
6804         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6805                 return 800000;
6806         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6807                 return 450000;
6808         else if (freq == LCPLL_CLK_FREQ_450)
6809                 return 450000;
6810         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6811                 return 540000;
6812         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6813                 return 337500;
6814         else
6815                 return 675000;
6816 }
6817
6818 static int haswell_get_display_clock_speed(struct drm_device *dev)
6819 {
6820         struct drm_i915_private *dev_priv = dev->dev_private;
6821         uint32_t lcpll = I915_READ(LCPLL_CTL);
6822         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6823
6824         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6825                 return 800000;
6826         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6827                 return 450000;
6828         else if (freq == LCPLL_CLK_FREQ_450)
6829                 return 450000;
6830         else if (IS_HSW_ULT(dev))
6831                 return 337500;
6832         else
6833                 return 540000;
6834 }
6835
6836 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6837 {
6838         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6839                                       CCK_DISPLAY_CLOCK_CONTROL);
6840 }
6841
6842 static int ilk_get_display_clock_speed(struct drm_device *dev)
6843 {
6844         return 450000;
6845 }
6846
6847 static int i945_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         return 400000;
6850 }
6851
6852 static int i915_get_display_clock_speed(struct drm_device *dev)
6853 {
6854         return 333333;
6855 }
6856
6857 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6858 {
6859         return 200000;
6860 }
6861
6862 static int pnv_get_display_clock_speed(struct drm_device *dev)
6863 {
6864         u16 gcfgc = 0;
6865
6866         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6867
6868         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6869         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6870                 return 266667;
6871         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6872                 return 333333;
6873         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6874                 return 444444;
6875         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6876                 return 200000;
6877         default:
6878                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6879         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6880                 return 133333;
6881         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6882                 return 166667;
6883         }
6884 }
6885
6886 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6887 {
6888         u16 gcfgc = 0;
6889
6890         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6891
6892         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6893                 return 133333;
6894         else {
6895                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6896                 case GC_DISPLAY_CLOCK_333_MHZ:
6897                         return 333333;
6898                 default:
6899                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6900                         return 190000;
6901                 }
6902         }
6903 }
6904
6905 static int i865_get_display_clock_speed(struct drm_device *dev)
6906 {
6907         return 266667;
6908 }
6909
6910 static int i85x_get_display_clock_speed(struct drm_device *dev)
6911 {
6912         u16 hpllcc = 0;
6913
6914         /*
6915          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6916          * encoding is different :(
6917          * FIXME is this the right way to detect 852GM/852GMV?
6918          */
6919         if (dev->pdev->revision == 0x1)
6920                 return 133333;
6921
6922         pci_bus_read_config_word(dev->pdev->bus,
6923                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6924
6925         /* Assume that the hardware is in the high speed state.  This
6926          * should be the default.
6927          */
6928         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6929         case GC_CLOCK_133_200:
6930         case GC_CLOCK_133_200_2:
6931         case GC_CLOCK_100_200:
6932                 return 200000;
6933         case GC_CLOCK_166_250:
6934                 return 250000;
6935         case GC_CLOCK_100_133:
6936                 return 133333;
6937         case GC_CLOCK_133_266:
6938         case GC_CLOCK_133_266_2:
6939         case GC_CLOCK_166_266:
6940                 return 266667;
6941         }
6942
6943         /* Shouldn't happen */
6944         return 0;
6945 }
6946
6947 static int i830_get_display_clock_speed(struct drm_device *dev)
6948 {
6949         return 133333;
6950 }
6951
6952 static unsigned int intel_hpll_vco(struct drm_device *dev)
6953 {
6954         struct drm_i915_private *dev_priv = dev->dev_private;
6955         static const unsigned int blb_vco[8] = {
6956                 [0] = 3200000,
6957                 [1] = 4000000,
6958                 [2] = 5333333,
6959                 [3] = 4800000,
6960                 [4] = 6400000,
6961         };
6962         static const unsigned int pnv_vco[8] = {
6963                 [0] = 3200000,
6964                 [1] = 4000000,
6965                 [2] = 5333333,
6966                 [3] = 4800000,
6967                 [4] = 2666667,
6968         };
6969         static const unsigned int cl_vco[8] = {
6970                 [0] = 3200000,
6971                 [1] = 4000000,
6972                 [2] = 5333333,
6973                 [3] = 6400000,
6974                 [4] = 3333333,
6975                 [5] = 3566667,
6976                 [6] = 4266667,
6977         };
6978         static const unsigned int elk_vco[8] = {
6979                 [0] = 3200000,
6980                 [1] = 4000000,
6981                 [2] = 5333333,
6982                 [3] = 4800000,
6983         };
6984         static const unsigned int ctg_vco[8] = {
6985                 [0] = 3200000,
6986                 [1] = 4000000,
6987                 [2] = 5333333,
6988                 [3] = 6400000,
6989                 [4] = 2666667,
6990                 [5] = 4266667,
6991         };
6992         const unsigned int *vco_table;
6993         unsigned int vco;
6994         uint8_t tmp = 0;
6995
6996         /* FIXME other chipsets? */
6997         if (IS_GM45(dev))
6998                 vco_table = ctg_vco;
6999         else if (IS_G4X(dev))
7000                 vco_table = elk_vco;
7001         else if (IS_CRESTLINE(dev))
7002                 vco_table = cl_vco;
7003         else if (IS_PINEVIEW(dev))
7004                 vco_table = pnv_vco;
7005         else if (IS_G33(dev))
7006                 vco_table = blb_vco;
7007         else
7008                 return 0;
7009
7010         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7011
7012         vco = vco_table[tmp & 0x7];
7013         if (vco == 0)
7014                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7015         else
7016                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7017
7018         return vco;
7019 }
7020
7021 static int gm45_get_display_clock_speed(struct drm_device *dev)
7022 {
7023         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7024         uint16_t tmp = 0;
7025
7026         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7027
7028         cdclk_sel = (tmp >> 12) & 0x1;
7029
7030         switch (vco) {
7031         case 2666667:
7032         case 4000000:
7033         case 5333333:
7034                 return cdclk_sel ? 333333 : 222222;
7035         case 3200000:
7036                 return cdclk_sel ? 320000 : 228571;
7037         default:
7038                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7039                 return 222222;
7040         }
7041 }
7042
7043 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7044 {
7045         static const uint8_t div_3200[] = { 16, 10,  8 };
7046         static const uint8_t div_4000[] = { 20, 12, 10 };
7047         static const uint8_t div_5333[] = { 24, 16, 14 };
7048         const uint8_t *div_table;
7049         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7050         uint16_t tmp = 0;
7051
7052         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7053
7054         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7055
7056         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7057                 goto fail;
7058
7059         switch (vco) {
7060         case 3200000:
7061                 div_table = div_3200;
7062                 break;
7063         case 4000000:
7064                 div_table = div_4000;
7065                 break;
7066         case 5333333:
7067                 div_table = div_5333;
7068                 break;
7069         default:
7070                 goto fail;
7071         }
7072
7073         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7074
7075 fail:
7076         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7077         return 200000;
7078 }
7079
7080 static int g33_get_display_clock_speed(struct drm_device *dev)
7081 {
7082         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7083         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7084         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7085         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7086         const uint8_t *div_table;
7087         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7088         uint16_t tmp = 0;
7089
7090         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7091
7092         cdclk_sel = (tmp >> 4) & 0x7;
7093
7094         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7095                 goto fail;
7096
7097         switch (vco) {
7098         case 3200000:
7099                 div_table = div_3200;
7100                 break;
7101         case 4000000:
7102                 div_table = div_4000;
7103                 break;
7104         case 4800000:
7105                 div_table = div_4800;
7106                 break;
7107         case 5333333:
7108                 div_table = div_5333;
7109                 break;
7110         default:
7111                 goto fail;
7112         }
7113
7114         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7115
7116 fail:
7117         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7118         return 190476;
7119 }
7120
7121 static void
7122 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7123 {
7124         while (*num > DATA_LINK_M_N_MASK ||
7125                *den > DATA_LINK_M_N_MASK) {
7126                 *num >>= 1;
7127                 *den >>= 1;
7128         }
7129 }
7130
7131 static void compute_m_n(unsigned int m, unsigned int n,
7132                         uint32_t *ret_m, uint32_t *ret_n)
7133 {
7134         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7135         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7136         intel_reduce_m_n_ratio(ret_m, ret_n);
7137 }
7138
7139 void
7140 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7141                        int pixel_clock, int link_clock,
7142                        struct intel_link_m_n *m_n)
7143 {
7144         m_n->tu = 64;
7145
7146         compute_m_n(bits_per_pixel * pixel_clock,
7147                     link_clock * nlanes * 8,
7148                     &m_n->gmch_m, &m_n->gmch_n);
7149
7150         compute_m_n(pixel_clock, link_clock,
7151                     &m_n->link_m, &m_n->link_n);
7152 }
7153
7154 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7155 {
7156         if (i915.panel_use_ssc >= 0)
7157                 return i915.panel_use_ssc != 0;
7158         return dev_priv->vbt.lvds_use_ssc
7159                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7160 }
7161
7162 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7163                            int num_connectors)
7164 {
7165         struct drm_device *dev = crtc_state->base.crtc->dev;
7166         struct drm_i915_private *dev_priv = dev->dev_private;
7167         int refclk;
7168
7169         WARN_ON(!crtc_state->base.state);
7170
7171         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7172                 refclk = 100000;
7173         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7174             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7175                 refclk = dev_priv->vbt.lvds_ssc_freq;
7176                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7177         } else if (!IS_GEN2(dev)) {
7178                 refclk = 96000;
7179         } else {
7180                 refclk = 48000;
7181         }
7182
7183         return refclk;
7184 }
7185
7186 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7187 {
7188         return (1 << dpll->n) << 16 | dpll->m2;
7189 }
7190
7191 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7192 {
7193         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7194 }
7195
7196 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7197                                      struct intel_crtc_state *crtc_state,
7198                                      intel_clock_t *reduced_clock)
7199 {
7200         struct drm_device *dev = crtc->base.dev;
7201         u32 fp, fp2 = 0;
7202
7203         if (IS_PINEVIEW(dev)) {
7204                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7205                 if (reduced_clock)
7206                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7207         } else {
7208                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7209                 if (reduced_clock)
7210                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7211         }
7212
7213         crtc_state->dpll_hw_state.fp0 = fp;
7214
7215         crtc->lowfreq_avail = false;
7216         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7217             reduced_clock) {
7218                 crtc_state->dpll_hw_state.fp1 = fp2;
7219                 crtc->lowfreq_avail = true;
7220         } else {
7221                 crtc_state->dpll_hw_state.fp1 = fp;
7222         }
7223 }
7224
7225 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7226                 pipe)
7227 {
7228         u32 reg_val;
7229
7230         /*
7231          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7232          * and set it to a reasonable value instead.
7233          */
7234         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7235         reg_val &= 0xffffff00;
7236         reg_val |= 0x00000030;
7237         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7238
7239         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7240         reg_val &= 0x8cffffff;
7241         reg_val = 0x8c000000;
7242         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7243
7244         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7245         reg_val &= 0xffffff00;
7246         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7247
7248         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7249         reg_val &= 0x00ffffff;
7250         reg_val |= 0xb0000000;
7251         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7252 }
7253
7254 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7255                                          struct intel_link_m_n *m_n)
7256 {
7257         struct drm_device *dev = crtc->base.dev;
7258         struct drm_i915_private *dev_priv = dev->dev_private;
7259         int pipe = crtc->pipe;
7260
7261         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7262         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7263         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7264         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7265 }
7266
7267 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7268                                          struct intel_link_m_n *m_n,
7269                                          struct intel_link_m_n *m2_n2)
7270 {
7271         struct drm_device *dev = crtc->base.dev;
7272         struct drm_i915_private *dev_priv = dev->dev_private;
7273         int pipe = crtc->pipe;
7274         enum transcoder transcoder = crtc->config->cpu_transcoder;
7275
7276         if (INTEL_INFO(dev)->gen >= 5) {
7277                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7278                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7279                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7280                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7281                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7282                  * for gen < 8) and if DRRS is supported (to make sure the
7283                  * registers are not unnecessarily accessed).
7284                  */
7285                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7286                         crtc->config->has_drrs) {
7287                         I915_WRITE(PIPE_DATA_M2(transcoder),
7288                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7289                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7290                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7291                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7292                 }
7293         } else {
7294                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7295                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7296                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7297                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7298         }
7299 }
7300
7301 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7302 {
7303         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7304
7305         if (m_n == M1_N1) {
7306                 dp_m_n = &crtc->config->dp_m_n;
7307                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7308         } else if (m_n == M2_N2) {
7309
7310                 /*
7311                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7312                  * needs to be programmed into M1_N1.
7313                  */
7314                 dp_m_n = &crtc->config->dp_m2_n2;
7315         } else {
7316                 DRM_ERROR("Unsupported divider value\n");
7317                 return;
7318         }
7319
7320         if (crtc->config->has_pch_encoder)
7321                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7322         else
7323                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7324 }
7325
7326 static void vlv_compute_dpll(struct intel_crtc *crtc,
7327                              struct intel_crtc_state *pipe_config)
7328 {
7329         u32 dpll, dpll_md;
7330
7331         /*
7332          * Enable DPIO clock input. We should never disable the reference
7333          * clock for pipe B, since VGA hotplug / manual detection depends
7334          * on it.
7335          */
7336         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7337                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7338         /* We should never disable this, set it here for state tracking */
7339         if (crtc->pipe == PIPE_B)
7340                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7341         dpll |= DPLL_VCO_ENABLE;
7342         pipe_config->dpll_hw_state.dpll = dpll;
7343
7344         dpll_md = (pipe_config->pixel_multiplier - 1)
7345                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7346         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7347 }
7348
7349 static void vlv_prepare_pll(struct intel_crtc *crtc,
7350                             const struct intel_crtc_state *pipe_config)
7351 {
7352         struct drm_device *dev = crtc->base.dev;
7353         struct drm_i915_private *dev_priv = dev->dev_private;
7354         int pipe = crtc->pipe;
7355         u32 mdiv;
7356         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7357         u32 coreclk, reg_val;
7358
7359         mutex_lock(&dev_priv->sb_lock);
7360
7361         bestn = pipe_config->dpll.n;
7362         bestm1 = pipe_config->dpll.m1;
7363         bestm2 = pipe_config->dpll.m2;
7364         bestp1 = pipe_config->dpll.p1;
7365         bestp2 = pipe_config->dpll.p2;
7366
7367         /* See eDP HDMI DPIO driver vbios notes doc */
7368
7369         /* PLL B needs special handling */
7370         if (pipe == PIPE_B)
7371                 vlv_pllb_recal_opamp(dev_priv, pipe);
7372
7373         /* Set up Tx target for periodic Rcomp update */
7374         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7375
7376         /* Disable target IRef on PLL */
7377         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7378         reg_val &= 0x00ffffff;
7379         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7380
7381         /* Disable fast lock */
7382         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7383
7384         /* Set idtafcrecal before PLL is enabled */
7385         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7386         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7387         mdiv |= ((bestn << DPIO_N_SHIFT));
7388         mdiv |= (1 << DPIO_K_SHIFT);
7389
7390         /*
7391          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7392          * but we don't support that).
7393          * Note: don't use the DAC post divider as it seems unstable.
7394          */
7395         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7396         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7397
7398         mdiv |= DPIO_ENABLE_CALIBRATION;
7399         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7400
7401         /* Set HBR and RBR LPF coefficients */
7402         if (pipe_config->port_clock == 162000 ||
7403             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7404             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7405                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7406                                  0x009f0003);
7407         else
7408                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7409                                  0x00d0000f);
7410
7411         if (pipe_config->has_dp_encoder) {
7412                 /* Use SSC source */
7413                 if (pipe == PIPE_A)
7414                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7415                                          0x0df40000);
7416                 else
7417                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7418                                          0x0df70000);
7419         } else { /* HDMI or VGA */
7420                 /* Use bend source */
7421                 if (pipe == PIPE_A)
7422                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7423                                          0x0df70000);
7424                 else
7425                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7426                                          0x0df40000);
7427         }
7428
7429         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7430         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7431         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7432             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7433                 coreclk |= 0x01000000;
7434         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7435
7436         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7437         mutex_unlock(&dev_priv->sb_lock);
7438 }
7439
7440 static void chv_compute_dpll(struct intel_crtc *crtc,
7441                              struct intel_crtc_state *pipe_config)
7442 {
7443         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7444                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7445                 DPLL_VCO_ENABLE;
7446         if (crtc->pipe != PIPE_A)
7447                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7448
7449         pipe_config->dpll_hw_state.dpll_md =
7450                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7451 }
7452
7453 static void chv_prepare_pll(struct intel_crtc *crtc,
7454                             const struct intel_crtc_state *pipe_config)
7455 {
7456         struct drm_device *dev = crtc->base.dev;
7457         struct drm_i915_private *dev_priv = dev->dev_private;
7458         int pipe = crtc->pipe;
7459         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7460         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7461         u32 loopfilter, tribuf_calcntr;
7462         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7463         u32 dpio_val;
7464         int vco;
7465
7466         bestn = pipe_config->dpll.n;
7467         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7468         bestm1 = pipe_config->dpll.m1;
7469         bestm2 = pipe_config->dpll.m2 >> 22;
7470         bestp1 = pipe_config->dpll.p1;
7471         bestp2 = pipe_config->dpll.p2;
7472         vco = pipe_config->dpll.vco;
7473         dpio_val = 0;
7474         loopfilter = 0;
7475
7476         /*
7477          * Enable Refclk and SSC
7478          */
7479         I915_WRITE(dpll_reg,
7480                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7481
7482         mutex_lock(&dev_priv->sb_lock);
7483
7484         /* p1 and p2 divider */
7485         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7486                         5 << DPIO_CHV_S1_DIV_SHIFT |
7487                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7488                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7489                         1 << DPIO_CHV_K_DIV_SHIFT);
7490
7491         /* Feedback post-divider - m2 */
7492         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7493
7494         /* Feedback refclk divider - n and m1 */
7495         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7496                         DPIO_CHV_M1_DIV_BY_2 |
7497                         1 << DPIO_CHV_N_DIV_SHIFT);
7498
7499         /* M2 fraction division */
7500         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7501
7502         /* M2 fraction division enable */
7503         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7504         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7505         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7506         if (bestm2_frac)
7507                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7508         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7509
7510         /* Program digital lock detect threshold */
7511         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7512         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7513                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7514         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7515         if (!bestm2_frac)
7516                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7517         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7518
7519         /* Loop filter */
7520         if (vco == 5400000) {
7521                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7522                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7523                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7524                 tribuf_calcntr = 0x9;
7525         } else if (vco <= 6200000) {
7526                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7527                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7528                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7529                 tribuf_calcntr = 0x9;
7530         } else if (vco <= 6480000) {
7531                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7532                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7533                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7534                 tribuf_calcntr = 0x8;
7535         } else {
7536                 /* Not supported. Apply the same limits as in the max case */
7537                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7538                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7539                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7540                 tribuf_calcntr = 0;
7541         }
7542         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7543
7544         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7545         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7546         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7547         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7548
7549         /* AFC Recal */
7550         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7551                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7552                         DPIO_AFC_RECAL);
7553
7554         mutex_unlock(&dev_priv->sb_lock);
7555 }
7556
7557 /**
7558  * vlv_force_pll_on - forcibly enable just the PLL
7559  * @dev_priv: i915 private structure
7560  * @pipe: pipe PLL to enable
7561  * @dpll: PLL configuration
7562  *
7563  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7564  * in cases where we need the PLL enabled even when @pipe is not going to
7565  * be enabled.
7566  */
7567 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7568                       const struct dpll *dpll)
7569 {
7570         struct intel_crtc *crtc =
7571                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7572         struct intel_crtc_state pipe_config = {
7573                 .base.crtc = &crtc->base,
7574                 .pixel_multiplier = 1,
7575                 .dpll = *dpll,
7576         };
7577
7578         if (IS_CHERRYVIEW(dev)) {
7579                 chv_compute_dpll(crtc, &pipe_config);
7580                 chv_prepare_pll(crtc, &pipe_config);
7581                 chv_enable_pll(crtc, &pipe_config);
7582         } else {
7583                 vlv_compute_dpll(crtc, &pipe_config);
7584                 vlv_prepare_pll(crtc, &pipe_config);
7585                 vlv_enable_pll(crtc, &pipe_config);
7586         }
7587 }
7588
7589 /**
7590  * vlv_force_pll_off - forcibly disable just the PLL
7591  * @dev_priv: i915 private structure
7592  * @pipe: pipe PLL to disable
7593  *
7594  * Disable the PLL for @pipe. To be used in cases where we need
7595  * the PLL enabled even when @pipe is not going to be enabled.
7596  */
7597 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7598 {
7599         if (IS_CHERRYVIEW(dev))
7600                 chv_disable_pll(to_i915(dev), pipe);
7601         else
7602                 vlv_disable_pll(to_i915(dev), pipe);
7603 }
7604
7605 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7606                               struct intel_crtc_state *crtc_state,
7607                               intel_clock_t *reduced_clock,
7608                               int num_connectors)
7609 {
7610         struct drm_device *dev = crtc->base.dev;
7611         struct drm_i915_private *dev_priv = dev->dev_private;
7612         u32 dpll;
7613         bool is_sdvo;
7614         struct dpll *clock = &crtc_state->dpll;
7615
7616         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7617
7618         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7619                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7620
7621         dpll = DPLL_VGA_MODE_DIS;
7622
7623         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7624                 dpll |= DPLLB_MODE_LVDS;
7625         else
7626                 dpll |= DPLLB_MODE_DAC_SERIAL;
7627
7628         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7629                 dpll |= (crtc_state->pixel_multiplier - 1)
7630                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7631         }
7632
7633         if (is_sdvo)
7634                 dpll |= DPLL_SDVO_HIGH_SPEED;
7635
7636         if (crtc_state->has_dp_encoder)
7637                 dpll |= DPLL_SDVO_HIGH_SPEED;
7638
7639         /* compute bitmask from p1 value */
7640         if (IS_PINEVIEW(dev))
7641                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7642         else {
7643                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7644                 if (IS_G4X(dev) && reduced_clock)
7645                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7646         }
7647         switch (clock->p2) {
7648         case 5:
7649                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7650                 break;
7651         case 7:
7652                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7653                 break;
7654         case 10:
7655                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7656                 break;
7657         case 14:
7658                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7659                 break;
7660         }
7661         if (INTEL_INFO(dev)->gen >= 4)
7662                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7663
7664         if (crtc_state->sdvo_tv_clock)
7665                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7666         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7667                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7668                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7669         else
7670                 dpll |= PLL_REF_INPUT_DREFCLK;
7671
7672         dpll |= DPLL_VCO_ENABLE;
7673         crtc_state->dpll_hw_state.dpll = dpll;
7674
7675         if (INTEL_INFO(dev)->gen >= 4) {
7676                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7677                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7678                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7679         }
7680 }
7681
7682 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7683                               struct intel_crtc_state *crtc_state,
7684                               intel_clock_t *reduced_clock,
7685                               int num_connectors)
7686 {
7687         struct drm_device *dev = crtc->base.dev;
7688         struct drm_i915_private *dev_priv = dev->dev_private;
7689         u32 dpll;
7690         struct dpll *clock = &crtc_state->dpll;
7691
7692         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7693
7694         dpll = DPLL_VGA_MODE_DIS;
7695
7696         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7697                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7698         } else {
7699                 if (clock->p1 == 2)
7700                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7701                 else
7702                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7703                 if (clock->p2 == 4)
7704                         dpll |= PLL_P2_DIVIDE_BY_4;
7705         }
7706
7707         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7708                 dpll |= DPLL_DVO_2X_MODE;
7709
7710         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7711                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7712                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7713         else
7714                 dpll |= PLL_REF_INPUT_DREFCLK;
7715
7716         dpll |= DPLL_VCO_ENABLE;
7717         crtc_state->dpll_hw_state.dpll = dpll;
7718 }
7719
7720 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7721 {
7722         struct drm_device *dev = intel_crtc->base.dev;
7723         struct drm_i915_private *dev_priv = dev->dev_private;
7724         enum pipe pipe = intel_crtc->pipe;
7725         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7726         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7727         uint32_t crtc_vtotal, crtc_vblank_end;
7728         int vsyncshift = 0;
7729
7730         /* We need to be careful not to changed the adjusted mode, for otherwise
7731          * the hw state checker will get angry at the mismatch. */
7732         crtc_vtotal = adjusted_mode->crtc_vtotal;
7733         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7734
7735         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7736                 /* the chip adds 2 halflines automatically */
7737                 crtc_vtotal -= 1;
7738                 crtc_vblank_end -= 1;
7739
7740                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7741                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7742                 else
7743                         vsyncshift = adjusted_mode->crtc_hsync_start -
7744                                 adjusted_mode->crtc_htotal / 2;
7745                 if (vsyncshift < 0)
7746                         vsyncshift += adjusted_mode->crtc_htotal;
7747         }
7748
7749         if (INTEL_INFO(dev)->gen > 3)
7750                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7751
7752         I915_WRITE(HTOTAL(cpu_transcoder),
7753                    (adjusted_mode->crtc_hdisplay - 1) |
7754                    ((adjusted_mode->crtc_htotal - 1) << 16));
7755         I915_WRITE(HBLANK(cpu_transcoder),
7756                    (adjusted_mode->crtc_hblank_start - 1) |
7757                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7758         I915_WRITE(HSYNC(cpu_transcoder),
7759                    (adjusted_mode->crtc_hsync_start - 1) |
7760                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7761
7762         I915_WRITE(VTOTAL(cpu_transcoder),
7763                    (adjusted_mode->crtc_vdisplay - 1) |
7764                    ((crtc_vtotal - 1) << 16));
7765         I915_WRITE(VBLANK(cpu_transcoder),
7766                    (adjusted_mode->crtc_vblank_start - 1) |
7767                    ((crtc_vblank_end - 1) << 16));
7768         I915_WRITE(VSYNC(cpu_transcoder),
7769                    (adjusted_mode->crtc_vsync_start - 1) |
7770                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7771
7772         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7773          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7774          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7775          * bits. */
7776         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7777             (pipe == PIPE_B || pipe == PIPE_C))
7778                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7779
7780         /* pipesrc controls the size that is scaled from, which should
7781          * always be the user's requested size.
7782          */
7783         I915_WRITE(PIPESRC(pipe),
7784                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7785                    (intel_crtc->config->pipe_src_h - 1));
7786 }
7787
7788 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7789                                    struct intel_crtc_state *pipe_config)
7790 {
7791         struct drm_device *dev = crtc->base.dev;
7792         struct drm_i915_private *dev_priv = dev->dev_private;
7793         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7794         uint32_t tmp;
7795
7796         tmp = I915_READ(HTOTAL(cpu_transcoder));
7797         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7798         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7799         tmp = I915_READ(HBLANK(cpu_transcoder));
7800         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7801         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7802         tmp = I915_READ(HSYNC(cpu_transcoder));
7803         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7804         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7805
7806         tmp = I915_READ(VTOTAL(cpu_transcoder));
7807         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7808         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7809         tmp = I915_READ(VBLANK(cpu_transcoder));
7810         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7811         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7812         tmp = I915_READ(VSYNC(cpu_transcoder));
7813         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7814         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7815
7816         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7817                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7818                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7819                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7820         }
7821
7822         tmp = I915_READ(PIPESRC(crtc->pipe));
7823         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7824         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7825
7826         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7827         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7828 }
7829
7830 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7831                                  struct intel_crtc_state *pipe_config)
7832 {
7833         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7834         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7835         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7836         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7837
7838         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7839         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7840         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7841         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7842
7843         mode->flags = pipe_config->base.adjusted_mode.flags;
7844         mode->type = DRM_MODE_TYPE_DRIVER;
7845
7846         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7847         mode->flags |= pipe_config->base.adjusted_mode.flags;
7848
7849         mode->hsync = drm_mode_hsync(mode);
7850         mode->vrefresh = drm_mode_vrefresh(mode);
7851         drm_mode_set_name(mode);
7852 }
7853
7854 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7855 {
7856         struct drm_device *dev = intel_crtc->base.dev;
7857         struct drm_i915_private *dev_priv = dev->dev_private;
7858         uint32_t pipeconf;
7859
7860         pipeconf = 0;
7861
7862         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7863             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7864                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7865
7866         if (intel_crtc->config->double_wide)
7867                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7868
7869         /* only g4x and later have fancy bpc/dither controls */
7870         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7871                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7872                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7873                         pipeconf |= PIPECONF_DITHER_EN |
7874                                     PIPECONF_DITHER_TYPE_SP;
7875
7876                 switch (intel_crtc->config->pipe_bpp) {
7877                 case 18:
7878                         pipeconf |= PIPECONF_6BPC;
7879                         break;
7880                 case 24:
7881                         pipeconf |= PIPECONF_8BPC;
7882                         break;
7883                 case 30:
7884                         pipeconf |= PIPECONF_10BPC;
7885                         break;
7886                 default:
7887                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7888                         BUG();
7889                 }
7890         }
7891
7892         if (HAS_PIPE_CXSR(dev)) {
7893                 if (intel_crtc->lowfreq_avail) {
7894                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7895                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7896                 } else {
7897                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7898                 }
7899         }
7900
7901         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7902                 if (INTEL_INFO(dev)->gen < 4 ||
7903                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7904                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7905                 else
7906                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7907         } else
7908                 pipeconf |= PIPECONF_PROGRESSIVE;
7909
7910         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7911                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7912
7913         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7914         POSTING_READ(PIPECONF(intel_crtc->pipe));
7915 }
7916
7917 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7918                                    struct intel_crtc_state *crtc_state)
7919 {
7920         struct drm_device *dev = crtc->base.dev;
7921         struct drm_i915_private *dev_priv = dev->dev_private;
7922         int refclk, num_connectors = 0;
7923         intel_clock_t clock;
7924         bool ok;
7925         bool is_dsi = false;
7926         struct intel_encoder *encoder;
7927         const intel_limit_t *limit;
7928         struct drm_atomic_state *state = crtc_state->base.state;
7929         struct drm_connector *connector;
7930         struct drm_connector_state *connector_state;
7931         int i;
7932
7933         memset(&crtc_state->dpll_hw_state, 0,
7934                sizeof(crtc_state->dpll_hw_state));
7935
7936         for_each_connector_in_state(state, connector, connector_state, i) {
7937                 if (connector_state->crtc != &crtc->base)
7938                         continue;
7939
7940                 encoder = to_intel_encoder(connector_state->best_encoder);
7941
7942                 switch (encoder->type) {
7943                 case INTEL_OUTPUT_DSI:
7944                         is_dsi = true;
7945                         break;
7946                 default:
7947                         break;
7948                 }
7949
7950                 num_connectors++;
7951         }
7952
7953         if (is_dsi)
7954                 return 0;
7955
7956         if (!crtc_state->clock_set) {
7957                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7958
7959                 /*
7960                  * Returns a set of divisors for the desired target clock with
7961                  * the given refclk, or FALSE.  The returned values represent
7962                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7963                  * 2) / p1 / p2.
7964                  */
7965                 limit = intel_limit(crtc_state, refclk);
7966                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7967                                                  crtc_state->port_clock,
7968                                                  refclk, NULL, &clock);
7969                 if (!ok) {
7970                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7971                         return -EINVAL;
7972                 }
7973
7974                 /* Compat-code for transition, will disappear. */
7975                 crtc_state->dpll.n = clock.n;
7976                 crtc_state->dpll.m1 = clock.m1;
7977                 crtc_state->dpll.m2 = clock.m2;
7978                 crtc_state->dpll.p1 = clock.p1;
7979                 crtc_state->dpll.p2 = clock.p2;
7980         }
7981
7982         if (IS_GEN2(dev)) {
7983                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7984                                   num_connectors);
7985         } else if (IS_CHERRYVIEW(dev)) {
7986                 chv_compute_dpll(crtc, crtc_state);
7987         } else if (IS_VALLEYVIEW(dev)) {
7988                 vlv_compute_dpll(crtc, crtc_state);
7989         } else {
7990                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7991                                   num_connectors);
7992         }
7993
7994         return 0;
7995 }
7996
7997 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7998                                  struct intel_crtc_state *pipe_config)
7999 {
8000         struct drm_device *dev = crtc->base.dev;
8001         struct drm_i915_private *dev_priv = dev->dev_private;
8002         uint32_t tmp;
8003
8004         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8005                 return;
8006
8007         tmp = I915_READ(PFIT_CONTROL);
8008         if (!(tmp & PFIT_ENABLE))
8009                 return;
8010
8011         /* Check whether the pfit is attached to our pipe. */
8012         if (INTEL_INFO(dev)->gen < 4) {
8013                 if (crtc->pipe != PIPE_B)
8014                         return;
8015         } else {
8016                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8017                         return;
8018         }
8019
8020         pipe_config->gmch_pfit.control = tmp;
8021         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8022         if (INTEL_INFO(dev)->gen < 5)
8023                 pipe_config->gmch_pfit.lvds_border_bits =
8024                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8025 }
8026
8027 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8028                                struct intel_crtc_state *pipe_config)
8029 {
8030         struct drm_device *dev = crtc->base.dev;
8031         struct drm_i915_private *dev_priv = dev->dev_private;
8032         int pipe = pipe_config->cpu_transcoder;
8033         intel_clock_t clock;
8034         u32 mdiv;
8035         int refclk = 100000;
8036
8037         /* In case of MIPI DPLL will not even be used */
8038         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8039                 return;
8040
8041         mutex_lock(&dev_priv->sb_lock);
8042         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8043         mutex_unlock(&dev_priv->sb_lock);
8044
8045         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8046         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8047         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8048         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8049         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8050
8051         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8052 }
8053
8054 static void
8055 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8056                               struct intel_initial_plane_config *plane_config)
8057 {
8058         struct drm_device *dev = crtc->base.dev;
8059         struct drm_i915_private *dev_priv = dev->dev_private;
8060         u32 val, base, offset;
8061         int pipe = crtc->pipe, plane = crtc->plane;
8062         int fourcc, pixel_format;
8063         unsigned int aligned_height;
8064         struct drm_framebuffer *fb;
8065         struct intel_framebuffer *intel_fb;
8066
8067         val = I915_READ(DSPCNTR(plane));
8068         if (!(val & DISPLAY_PLANE_ENABLE))
8069                 return;
8070
8071         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8072         if (!intel_fb) {
8073                 DRM_DEBUG_KMS("failed to alloc fb\n");
8074                 return;
8075         }
8076
8077         fb = &intel_fb->base;
8078
8079         if (INTEL_INFO(dev)->gen >= 4) {
8080                 if (val & DISPPLANE_TILED) {
8081                         plane_config->tiling = I915_TILING_X;
8082                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8083                 }
8084         }
8085
8086         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8087         fourcc = i9xx_format_to_fourcc(pixel_format);
8088         fb->pixel_format = fourcc;
8089         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8090
8091         if (INTEL_INFO(dev)->gen >= 4) {
8092                 if (plane_config->tiling)
8093                         offset = I915_READ(DSPTILEOFF(plane));
8094                 else
8095                         offset = I915_READ(DSPLINOFF(plane));
8096                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8097         } else {
8098                 base = I915_READ(DSPADDR(plane));
8099         }
8100         plane_config->base = base;
8101
8102         val = I915_READ(PIPESRC(pipe));
8103         fb->width = ((val >> 16) & 0xfff) + 1;
8104         fb->height = ((val >> 0) & 0xfff) + 1;
8105
8106         val = I915_READ(DSPSTRIDE(pipe));
8107         fb->pitches[0] = val & 0xffffffc0;
8108
8109         aligned_height = intel_fb_align_height(dev, fb->height,
8110                                                fb->pixel_format,
8111                                                fb->modifier[0]);
8112
8113         plane_config->size = fb->pitches[0] * aligned_height;
8114
8115         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8116                       pipe_name(pipe), plane, fb->width, fb->height,
8117                       fb->bits_per_pixel, base, fb->pitches[0],
8118                       plane_config->size);
8119
8120         plane_config->fb = intel_fb;
8121 }
8122
8123 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8124                                struct intel_crtc_state *pipe_config)
8125 {
8126         struct drm_device *dev = crtc->base.dev;
8127         struct drm_i915_private *dev_priv = dev->dev_private;
8128         int pipe = pipe_config->cpu_transcoder;
8129         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8130         intel_clock_t clock;
8131         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8132         int refclk = 100000;
8133
8134         mutex_lock(&dev_priv->sb_lock);
8135         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8136         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8137         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8138         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8139         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8140         mutex_unlock(&dev_priv->sb_lock);
8141
8142         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8143         clock.m2 = (pll_dw0 & 0xff) << 22;
8144         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8145                 clock.m2 |= pll_dw2 & 0x3fffff;
8146         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8147         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8148         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8149
8150         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8151 }
8152
8153 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8154                                  struct intel_crtc_state *pipe_config)
8155 {
8156         struct drm_device *dev = crtc->base.dev;
8157         struct drm_i915_private *dev_priv = dev->dev_private;
8158         uint32_t tmp;
8159
8160         if (!intel_display_power_is_enabled(dev_priv,
8161                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8162                 return false;
8163
8164         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8165         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8166
8167         tmp = I915_READ(PIPECONF(crtc->pipe));
8168         if (!(tmp & PIPECONF_ENABLE))
8169                 return false;
8170
8171         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8172                 switch (tmp & PIPECONF_BPC_MASK) {
8173                 case PIPECONF_6BPC:
8174                         pipe_config->pipe_bpp = 18;
8175                         break;
8176                 case PIPECONF_8BPC:
8177                         pipe_config->pipe_bpp = 24;
8178                         break;
8179                 case PIPECONF_10BPC:
8180                         pipe_config->pipe_bpp = 30;
8181                         break;
8182                 default:
8183                         break;
8184                 }
8185         }
8186
8187         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8188                 pipe_config->limited_color_range = true;
8189
8190         if (INTEL_INFO(dev)->gen < 4)
8191                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8192
8193         intel_get_pipe_timings(crtc, pipe_config);
8194
8195         i9xx_get_pfit_config(crtc, pipe_config);
8196
8197         if (INTEL_INFO(dev)->gen >= 4) {
8198                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8199                 pipe_config->pixel_multiplier =
8200                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8201                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8202                 pipe_config->dpll_hw_state.dpll_md = tmp;
8203         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8204                 tmp = I915_READ(DPLL(crtc->pipe));
8205                 pipe_config->pixel_multiplier =
8206                         ((tmp & SDVO_MULTIPLIER_MASK)
8207                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8208         } else {
8209                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8210                  * port and will be fixed up in the encoder->get_config
8211                  * function. */
8212                 pipe_config->pixel_multiplier = 1;
8213         }
8214         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8215         if (!IS_VALLEYVIEW(dev)) {
8216                 /*
8217                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8218                  * on 830. Filter it out here so that we don't
8219                  * report errors due to that.
8220                  */
8221                 if (IS_I830(dev))
8222                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8223
8224                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8225                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8226         } else {
8227                 /* Mask out read-only status bits. */
8228                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8229                                                      DPLL_PORTC_READY_MASK |
8230                                                      DPLL_PORTB_READY_MASK);
8231         }
8232
8233         if (IS_CHERRYVIEW(dev))
8234                 chv_crtc_clock_get(crtc, pipe_config);
8235         else if (IS_VALLEYVIEW(dev))
8236                 vlv_crtc_clock_get(crtc, pipe_config);
8237         else
8238                 i9xx_crtc_clock_get(crtc, pipe_config);
8239
8240         /*
8241          * Normally the dotclock is filled in by the encoder .get_config()
8242          * but in case the pipe is enabled w/o any ports we need a sane
8243          * default.
8244          */
8245         pipe_config->base.adjusted_mode.crtc_clock =
8246                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8247
8248         return true;
8249 }
8250
8251 static void ironlake_init_pch_refclk(struct drm_device *dev)
8252 {
8253         struct drm_i915_private *dev_priv = dev->dev_private;
8254         struct intel_encoder *encoder;
8255         u32 val, final;
8256         bool has_lvds = false;
8257         bool has_cpu_edp = false;
8258         bool has_panel = false;
8259         bool has_ck505 = false;
8260         bool can_ssc = false;
8261
8262         /* We need to take the global config into account */
8263         for_each_intel_encoder(dev, encoder) {
8264                 switch (encoder->type) {
8265                 case INTEL_OUTPUT_LVDS:
8266                         has_panel = true;
8267                         has_lvds = true;
8268                         break;
8269                 case INTEL_OUTPUT_EDP:
8270                         has_panel = true;
8271                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8272                                 has_cpu_edp = true;
8273                         break;
8274                 default:
8275                         break;
8276                 }
8277         }
8278
8279         if (HAS_PCH_IBX(dev)) {
8280                 has_ck505 = dev_priv->vbt.display_clock_mode;
8281                 can_ssc = has_ck505;
8282         } else {
8283                 has_ck505 = false;
8284                 can_ssc = true;
8285         }
8286
8287         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8288                       has_panel, has_lvds, has_ck505);
8289
8290         /* Ironlake: try to setup display ref clock before DPLL
8291          * enabling. This is only under driver's control after
8292          * PCH B stepping, previous chipset stepping should be
8293          * ignoring this setting.
8294          */
8295         val = I915_READ(PCH_DREF_CONTROL);
8296
8297         /* As we must carefully and slowly disable/enable each source in turn,
8298          * compute the final state we want first and check if we need to
8299          * make any changes at all.
8300          */
8301         final = val;
8302         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8303         if (has_ck505)
8304                 final |= DREF_NONSPREAD_CK505_ENABLE;
8305         else
8306                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8307
8308         final &= ~DREF_SSC_SOURCE_MASK;
8309         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8310         final &= ~DREF_SSC1_ENABLE;
8311
8312         if (has_panel) {
8313                 final |= DREF_SSC_SOURCE_ENABLE;
8314
8315                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8316                         final |= DREF_SSC1_ENABLE;
8317
8318                 if (has_cpu_edp) {
8319                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8320                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8321                         else
8322                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8323                 } else
8324                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8325         } else {
8326                 final |= DREF_SSC_SOURCE_DISABLE;
8327                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8328         }
8329
8330         if (final == val)
8331                 return;
8332
8333         /* Always enable nonspread source */
8334         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8335
8336         if (has_ck505)
8337                 val |= DREF_NONSPREAD_CK505_ENABLE;
8338         else
8339                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8340
8341         if (has_panel) {
8342                 val &= ~DREF_SSC_SOURCE_MASK;
8343                 val |= DREF_SSC_SOURCE_ENABLE;
8344
8345                 /* SSC must be turned on before enabling the CPU output  */
8346                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8347                         DRM_DEBUG_KMS("Using SSC on panel\n");
8348                         val |= DREF_SSC1_ENABLE;
8349                 } else
8350                         val &= ~DREF_SSC1_ENABLE;
8351
8352                 /* Get SSC going before enabling the outputs */
8353                 I915_WRITE(PCH_DREF_CONTROL, val);
8354                 POSTING_READ(PCH_DREF_CONTROL);
8355                 udelay(200);
8356
8357                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8358
8359                 /* Enable CPU source on CPU attached eDP */
8360                 if (has_cpu_edp) {
8361                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8362                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8363                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8364                         } else
8365                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8366                 } else
8367                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8368
8369                 I915_WRITE(PCH_DREF_CONTROL, val);
8370                 POSTING_READ(PCH_DREF_CONTROL);
8371                 udelay(200);
8372         } else {
8373                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8374
8375                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8376
8377                 /* Turn off CPU output */
8378                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8379
8380                 I915_WRITE(PCH_DREF_CONTROL, val);
8381                 POSTING_READ(PCH_DREF_CONTROL);
8382                 udelay(200);
8383
8384                 /* Turn off the SSC source */
8385                 val &= ~DREF_SSC_SOURCE_MASK;
8386                 val |= DREF_SSC_SOURCE_DISABLE;
8387
8388                 /* Turn off SSC1 */
8389                 val &= ~DREF_SSC1_ENABLE;
8390
8391                 I915_WRITE(PCH_DREF_CONTROL, val);
8392                 POSTING_READ(PCH_DREF_CONTROL);
8393                 udelay(200);
8394         }
8395
8396         BUG_ON(val != final);
8397 }
8398
8399 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8400 {
8401         uint32_t tmp;
8402
8403         tmp = I915_READ(SOUTH_CHICKEN2);
8404         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8405         I915_WRITE(SOUTH_CHICKEN2, tmp);
8406
8407         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8408                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8409                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8410
8411         tmp = I915_READ(SOUTH_CHICKEN2);
8412         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8413         I915_WRITE(SOUTH_CHICKEN2, tmp);
8414
8415         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8416                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8417                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8418 }
8419
8420 /* WaMPhyProgramming:hsw */
8421 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8422 {
8423         uint32_t tmp;
8424
8425         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8426         tmp &= ~(0xFF << 24);
8427         tmp |= (0x12 << 24);
8428         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8429
8430         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8431         tmp |= (1 << 11);
8432         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8433
8434         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8435         tmp |= (1 << 11);
8436         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8439         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8440         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8441
8442         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8443         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8444         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8445
8446         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8447         tmp &= ~(7 << 13);
8448         tmp |= (5 << 13);
8449         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8450
8451         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8452         tmp &= ~(7 << 13);
8453         tmp |= (5 << 13);
8454         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8455
8456         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8457         tmp &= ~0xFF;
8458         tmp |= 0x1C;
8459         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8460
8461         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8462         tmp &= ~0xFF;
8463         tmp |= 0x1C;
8464         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8465
8466         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8467         tmp &= ~(0xFF << 16);
8468         tmp |= (0x1C << 16);
8469         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8470
8471         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8472         tmp &= ~(0xFF << 16);
8473         tmp |= (0x1C << 16);
8474         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8475
8476         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8477         tmp |= (1 << 27);
8478         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8479
8480         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8481         tmp |= (1 << 27);
8482         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8483
8484         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8485         tmp &= ~(0xF << 28);
8486         tmp |= (4 << 28);
8487         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8488
8489         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8490         tmp &= ~(0xF << 28);
8491         tmp |= (4 << 28);
8492         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8493 }
8494
8495 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8496  * Programming" based on the parameters passed:
8497  * - Sequence to enable CLKOUT_DP
8498  * - Sequence to enable CLKOUT_DP without spread
8499  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8500  */
8501 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8502                                  bool with_fdi)
8503 {
8504         struct drm_i915_private *dev_priv = dev->dev_private;
8505         uint32_t reg, tmp;
8506
8507         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8508                 with_spread = true;
8509         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8510                 with_fdi = false;
8511
8512         mutex_lock(&dev_priv->sb_lock);
8513
8514         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8515         tmp &= ~SBI_SSCCTL_DISABLE;
8516         tmp |= SBI_SSCCTL_PATHALT;
8517         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8518
8519         udelay(24);
8520
8521         if (with_spread) {
8522                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8523                 tmp &= ~SBI_SSCCTL_PATHALT;
8524                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8525
8526                 if (with_fdi) {
8527                         lpt_reset_fdi_mphy(dev_priv);
8528                         lpt_program_fdi_mphy(dev_priv);
8529                 }
8530         }
8531
8532         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8533         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8534         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8535         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8536
8537         mutex_unlock(&dev_priv->sb_lock);
8538 }
8539
8540 /* Sequence to disable CLKOUT_DP */
8541 static void lpt_disable_clkout_dp(struct drm_device *dev)
8542 {
8543         struct drm_i915_private *dev_priv = dev->dev_private;
8544         uint32_t reg, tmp;
8545
8546         mutex_lock(&dev_priv->sb_lock);
8547
8548         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8549         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8550         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8551         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8552
8553         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8554         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8555                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8556                         tmp |= SBI_SSCCTL_PATHALT;
8557                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8558                         udelay(32);
8559                 }
8560                 tmp |= SBI_SSCCTL_DISABLE;
8561                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8562         }
8563
8564         mutex_unlock(&dev_priv->sb_lock);
8565 }
8566
8567 static void lpt_init_pch_refclk(struct drm_device *dev)
8568 {
8569         struct intel_encoder *encoder;
8570         bool has_vga = false;
8571
8572         for_each_intel_encoder(dev, encoder) {
8573                 switch (encoder->type) {
8574                 case INTEL_OUTPUT_ANALOG:
8575                         has_vga = true;
8576                         break;
8577                 default:
8578                         break;
8579                 }
8580         }
8581
8582         if (has_vga)
8583                 lpt_enable_clkout_dp(dev, true, true);
8584         else
8585                 lpt_disable_clkout_dp(dev);
8586 }
8587
8588 /*
8589  * Initialize reference clocks when the driver loads
8590  */
8591 void intel_init_pch_refclk(struct drm_device *dev)
8592 {
8593         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8594                 ironlake_init_pch_refclk(dev);
8595         else if (HAS_PCH_LPT(dev))
8596                 lpt_init_pch_refclk(dev);
8597 }
8598
8599 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8600 {
8601         struct drm_device *dev = crtc_state->base.crtc->dev;
8602         struct drm_i915_private *dev_priv = dev->dev_private;
8603         struct drm_atomic_state *state = crtc_state->base.state;
8604         struct drm_connector *connector;
8605         struct drm_connector_state *connector_state;
8606         struct intel_encoder *encoder;
8607         int num_connectors = 0, i;
8608         bool is_lvds = false;
8609
8610         for_each_connector_in_state(state, connector, connector_state, i) {
8611                 if (connector_state->crtc != crtc_state->base.crtc)
8612                         continue;
8613
8614                 encoder = to_intel_encoder(connector_state->best_encoder);
8615
8616                 switch (encoder->type) {
8617                 case INTEL_OUTPUT_LVDS:
8618                         is_lvds = true;
8619                         break;
8620                 default:
8621                         break;
8622                 }
8623                 num_connectors++;
8624         }
8625
8626         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8627                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8628                               dev_priv->vbt.lvds_ssc_freq);
8629                 return dev_priv->vbt.lvds_ssc_freq;
8630         }
8631
8632         return 120000;
8633 }
8634
8635 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8636 {
8637         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8639         int pipe = intel_crtc->pipe;
8640         uint32_t val;
8641
8642         val = 0;
8643
8644         switch (intel_crtc->config->pipe_bpp) {
8645         case 18:
8646                 val |= PIPECONF_6BPC;
8647                 break;
8648         case 24:
8649                 val |= PIPECONF_8BPC;
8650                 break;
8651         case 30:
8652                 val |= PIPECONF_10BPC;
8653                 break;
8654         case 36:
8655                 val |= PIPECONF_12BPC;
8656                 break;
8657         default:
8658                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8659                 BUG();
8660         }
8661
8662         if (intel_crtc->config->dither)
8663                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8664
8665         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8666                 val |= PIPECONF_INTERLACED_ILK;
8667         else
8668                 val |= PIPECONF_PROGRESSIVE;
8669
8670         if (intel_crtc->config->limited_color_range)
8671                 val |= PIPECONF_COLOR_RANGE_SELECT;
8672
8673         I915_WRITE(PIPECONF(pipe), val);
8674         POSTING_READ(PIPECONF(pipe));
8675 }
8676
8677 /*
8678  * Set up the pipe CSC unit.
8679  *
8680  * Currently only full range RGB to limited range RGB conversion
8681  * is supported, but eventually this should handle various
8682  * RGB<->YCbCr scenarios as well.
8683  */
8684 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8685 {
8686         struct drm_device *dev = crtc->dev;
8687         struct drm_i915_private *dev_priv = dev->dev_private;
8688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8689         int pipe = intel_crtc->pipe;
8690         uint16_t coeff = 0x7800; /* 1.0 */
8691
8692         /*
8693          * TODO: Check what kind of values actually come out of the pipe
8694          * with these coeff/postoff values and adjust to get the best
8695          * accuracy. Perhaps we even need to take the bpc value into
8696          * consideration.
8697          */
8698
8699         if (intel_crtc->config->limited_color_range)
8700                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8701
8702         /*
8703          * GY/GU and RY/RU should be the other way around according
8704          * to BSpec, but reality doesn't agree. Just set them up in
8705          * a way that results in the correct picture.
8706          */
8707         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8708         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8709
8710         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8711         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8712
8713         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8714         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8715
8716         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8717         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8718         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8719
8720         if (INTEL_INFO(dev)->gen > 6) {
8721                 uint16_t postoff = 0;
8722
8723                 if (intel_crtc->config->limited_color_range)
8724                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8725
8726                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8727                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8728                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8729
8730                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8731         } else {
8732                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8733
8734                 if (intel_crtc->config->limited_color_range)
8735                         mode |= CSC_BLACK_SCREEN_OFFSET;
8736
8737                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8738         }
8739 }
8740
8741 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8742 {
8743         struct drm_device *dev = crtc->dev;
8744         struct drm_i915_private *dev_priv = dev->dev_private;
8745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8746         enum pipe pipe = intel_crtc->pipe;
8747         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8748         uint32_t val;
8749
8750         val = 0;
8751
8752         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8753                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8754
8755         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8756                 val |= PIPECONF_INTERLACED_ILK;
8757         else
8758                 val |= PIPECONF_PROGRESSIVE;
8759
8760         I915_WRITE(PIPECONF(cpu_transcoder), val);
8761         POSTING_READ(PIPECONF(cpu_transcoder));
8762
8763         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8764         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8765
8766         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8767                 val = 0;
8768
8769                 switch (intel_crtc->config->pipe_bpp) {
8770                 case 18:
8771                         val |= PIPEMISC_DITHER_6_BPC;
8772                         break;
8773                 case 24:
8774                         val |= PIPEMISC_DITHER_8_BPC;
8775                         break;
8776                 case 30:
8777                         val |= PIPEMISC_DITHER_10_BPC;
8778                         break;
8779                 case 36:
8780                         val |= PIPEMISC_DITHER_12_BPC;
8781                         break;
8782                 default:
8783                         /* Case prevented by pipe_config_set_bpp. */
8784                         BUG();
8785                 }
8786
8787                 if (intel_crtc->config->dither)
8788                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8789
8790                 I915_WRITE(PIPEMISC(pipe), val);
8791         }
8792 }
8793
8794 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8795                                     struct intel_crtc_state *crtc_state,
8796                                     intel_clock_t *clock,
8797                                     bool *has_reduced_clock,
8798                                     intel_clock_t *reduced_clock)
8799 {
8800         struct drm_device *dev = crtc->dev;
8801         struct drm_i915_private *dev_priv = dev->dev_private;
8802         int refclk;
8803         const intel_limit_t *limit;
8804         bool ret;
8805
8806         refclk = ironlake_get_refclk(crtc_state);
8807
8808         /*
8809          * Returns a set of divisors for the desired target clock with the given
8810          * refclk, or FALSE.  The returned values represent the clock equation:
8811          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8812          */
8813         limit = intel_limit(crtc_state, refclk);
8814         ret = dev_priv->display.find_dpll(limit, crtc_state,
8815                                           crtc_state->port_clock,
8816                                           refclk, NULL, clock);
8817         if (!ret)
8818                 return false;
8819
8820         return true;
8821 }
8822
8823 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8824 {
8825         /*
8826          * Account for spread spectrum to avoid
8827          * oversubscribing the link. Max center spread
8828          * is 2.5%; use 5% for safety's sake.
8829          */
8830         u32 bps = target_clock * bpp * 21 / 20;
8831         return DIV_ROUND_UP(bps, link_bw * 8);
8832 }
8833
8834 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8835 {
8836         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8837 }
8838
8839 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8840                                       struct intel_crtc_state *crtc_state,
8841                                       u32 *fp,
8842                                       intel_clock_t *reduced_clock, u32 *fp2)
8843 {
8844         struct drm_crtc *crtc = &intel_crtc->base;
8845         struct drm_device *dev = crtc->dev;
8846         struct drm_i915_private *dev_priv = dev->dev_private;
8847         struct drm_atomic_state *state = crtc_state->base.state;
8848         struct drm_connector *connector;
8849         struct drm_connector_state *connector_state;
8850         struct intel_encoder *encoder;
8851         uint32_t dpll;
8852         int factor, num_connectors = 0, i;
8853         bool is_lvds = false, is_sdvo = false;
8854
8855         for_each_connector_in_state(state, connector, connector_state, i) {
8856                 if (connector_state->crtc != crtc_state->base.crtc)
8857                         continue;
8858
8859                 encoder = to_intel_encoder(connector_state->best_encoder);
8860
8861                 switch (encoder->type) {
8862                 case INTEL_OUTPUT_LVDS:
8863                         is_lvds = true;
8864                         break;
8865                 case INTEL_OUTPUT_SDVO:
8866                 case INTEL_OUTPUT_HDMI:
8867                         is_sdvo = true;
8868                         break;
8869                 default:
8870                         break;
8871                 }
8872
8873                 num_connectors++;
8874         }
8875
8876         /* Enable autotuning of the PLL clock (if permissible) */
8877         factor = 21;
8878         if (is_lvds) {
8879                 if ((intel_panel_use_ssc(dev_priv) &&
8880                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8881                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8882                         factor = 25;
8883         } else if (crtc_state->sdvo_tv_clock)
8884                 factor = 20;
8885
8886         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8887                 *fp |= FP_CB_TUNE;
8888
8889         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8890                 *fp2 |= FP_CB_TUNE;
8891
8892         dpll = 0;
8893
8894         if (is_lvds)
8895                 dpll |= DPLLB_MODE_LVDS;
8896         else
8897                 dpll |= DPLLB_MODE_DAC_SERIAL;
8898
8899         dpll |= (crtc_state->pixel_multiplier - 1)
8900                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8901
8902         if (is_sdvo)
8903                 dpll |= DPLL_SDVO_HIGH_SPEED;
8904         if (crtc_state->has_dp_encoder)
8905                 dpll |= DPLL_SDVO_HIGH_SPEED;
8906
8907         /* compute bitmask from p1 value */
8908         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8909         /* also FPA1 */
8910         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8911
8912         switch (crtc_state->dpll.p2) {
8913         case 5:
8914                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8915                 break;
8916         case 7:
8917                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8918                 break;
8919         case 10:
8920                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8921                 break;
8922         case 14:
8923                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8924                 break;
8925         }
8926
8927         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8928                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8929         else
8930                 dpll |= PLL_REF_INPUT_DREFCLK;
8931
8932         return dpll | DPLL_VCO_ENABLE;
8933 }
8934
8935 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8936                                        struct intel_crtc_state *crtc_state)
8937 {
8938         struct drm_device *dev = crtc->base.dev;
8939         intel_clock_t clock, reduced_clock;
8940         u32 dpll = 0, fp = 0, fp2 = 0;
8941         bool ok, has_reduced_clock = false;
8942         bool is_lvds = false;
8943         struct intel_shared_dpll *pll;
8944
8945         memset(&crtc_state->dpll_hw_state, 0,
8946                sizeof(crtc_state->dpll_hw_state));
8947
8948         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8949
8950         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8951              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8952
8953         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8954                                      &has_reduced_clock, &reduced_clock);
8955         if (!ok && !crtc_state->clock_set) {
8956                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8957                 return -EINVAL;
8958         }
8959         /* Compat-code for transition, will disappear. */
8960         if (!crtc_state->clock_set) {
8961                 crtc_state->dpll.n = clock.n;
8962                 crtc_state->dpll.m1 = clock.m1;
8963                 crtc_state->dpll.m2 = clock.m2;
8964                 crtc_state->dpll.p1 = clock.p1;
8965                 crtc_state->dpll.p2 = clock.p2;
8966         }
8967
8968         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8969         if (crtc_state->has_pch_encoder) {
8970                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8971                 if (has_reduced_clock)
8972                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8973
8974                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8975                                              &fp, &reduced_clock,
8976                                              has_reduced_clock ? &fp2 : NULL);
8977
8978                 crtc_state->dpll_hw_state.dpll = dpll;
8979                 crtc_state->dpll_hw_state.fp0 = fp;
8980                 if (has_reduced_clock)
8981                         crtc_state->dpll_hw_state.fp1 = fp2;
8982                 else
8983                         crtc_state->dpll_hw_state.fp1 = fp;
8984
8985                 pll = intel_get_shared_dpll(crtc, crtc_state);
8986                 if (pll == NULL) {
8987                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8988                                          pipe_name(crtc->pipe));
8989                         return -EINVAL;
8990                 }
8991         }
8992
8993         if (is_lvds && has_reduced_clock)
8994                 crtc->lowfreq_avail = true;
8995         else
8996                 crtc->lowfreq_avail = false;
8997
8998         return 0;
8999 }
9000
9001 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9002                                          struct intel_link_m_n *m_n)
9003 {
9004         struct drm_device *dev = crtc->base.dev;
9005         struct drm_i915_private *dev_priv = dev->dev_private;
9006         enum pipe pipe = crtc->pipe;
9007
9008         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9009         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9010         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9011                 & ~TU_SIZE_MASK;
9012         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9013         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9014                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9015 }
9016
9017 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9018                                          enum transcoder transcoder,
9019                                          struct intel_link_m_n *m_n,
9020                                          struct intel_link_m_n *m2_n2)
9021 {
9022         struct drm_device *dev = crtc->base.dev;
9023         struct drm_i915_private *dev_priv = dev->dev_private;
9024         enum pipe pipe = crtc->pipe;
9025
9026         if (INTEL_INFO(dev)->gen >= 5) {
9027                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9028                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9029                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9030                         & ~TU_SIZE_MASK;
9031                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9032                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9033                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9034                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9035                  * gen < 8) and if DRRS is supported (to make sure the
9036                  * registers are not unnecessarily read).
9037                  */
9038                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9039                         crtc->config->has_drrs) {
9040                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9041                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9042                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9043                                         & ~TU_SIZE_MASK;
9044                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9045                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9046                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9047                 }
9048         } else {
9049                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9050                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9051                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9052                         & ~TU_SIZE_MASK;
9053                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9054                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9055                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9056         }
9057 }
9058
9059 void intel_dp_get_m_n(struct intel_crtc *crtc,
9060                       struct intel_crtc_state *pipe_config)
9061 {
9062         if (pipe_config->has_pch_encoder)
9063                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9064         else
9065                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9066                                              &pipe_config->dp_m_n,
9067                                              &pipe_config->dp_m2_n2);
9068 }
9069
9070 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9071                                         struct intel_crtc_state *pipe_config)
9072 {
9073         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9074                                      &pipe_config->fdi_m_n, NULL);
9075 }
9076
9077 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9078                                     struct intel_crtc_state *pipe_config)
9079 {
9080         struct drm_device *dev = crtc->base.dev;
9081         struct drm_i915_private *dev_priv = dev->dev_private;
9082         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9083         uint32_t ps_ctrl = 0;
9084         int id = -1;
9085         int i;
9086
9087         /* find scaler attached to this pipe */
9088         for (i = 0; i < crtc->num_scalers; i++) {
9089                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9090                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9091                         id = i;
9092                         pipe_config->pch_pfit.enabled = true;
9093                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9094                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9095                         break;
9096                 }
9097         }
9098
9099         scaler_state->scaler_id = id;
9100         if (id >= 0) {
9101                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9102         } else {
9103                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9104         }
9105 }
9106
9107 static void
9108 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9109                                  struct intel_initial_plane_config *plane_config)
9110 {
9111         struct drm_device *dev = crtc->base.dev;
9112         struct drm_i915_private *dev_priv = dev->dev_private;
9113         u32 val, base, offset, stride_mult, tiling;
9114         int pipe = crtc->pipe;
9115         int fourcc, pixel_format;
9116         unsigned int aligned_height;
9117         struct drm_framebuffer *fb;
9118         struct intel_framebuffer *intel_fb;
9119
9120         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9121         if (!intel_fb) {
9122                 DRM_DEBUG_KMS("failed to alloc fb\n");
9123                 return;
9124         }
9125
9126         fb = &intel_fb->base;
9127
9128         val = I915_READ(PLANE_CTL(pipe, 0));
9129         if (!(val & PLANE_CTL_ENABLE))
9130                 goto error;
9131
9132         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9133         fourcc = skl_format_to_fourcc(pixel_format,
9134                                       val & PLANE_CTL_ORDER_RGBX,
9135                                       val & PLANE_CTL_ALPHA_MASK);
9136         fb->pixel_format = fourcc;
9137         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9138
9139         tiling = val & PLANE_CTL_TILED_MASK;
9140         switch (tiling) {
9141         case PLANE_CTL_TILED_LINEAR:
9142                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9143                 break;
9144         case PLANE_CTL_TILED_X:
9145                 plane_config->tiling = I915_TILING_X;
9146                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9147                 break;
9148         case PLANE_CTL_TILED_Y:
9149                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9150                 break;
9151         case PLANE_CTL_TILED_YF:
9152                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9153                 break;
9154         default:
9155                 MISSING_CASE(tiling);
9156                 goto error;
9157         }
9158
9159         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9160         plane_config->base = base;
9161
9162         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9163
9164         val = I915_READ(PLANE_SIZE(pipe, 0));
9165         fb->height = ((val >> 16) & 0xfff) + 1;
9166         fb->width = ((val >> 0) & 0x1fff) + 1;
9167
9168         val = I915_READ(PLANE_STRIDE(pipe, 0));
9169         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9170                                                 fb->pixel_format);
9171         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9172
9173         aligned_height = intel_fb_align_height(dev, fb->height,
9174                                                fb->pixel_format,
9175                                                fb->modifier[0]);
9176
9177         plane_config->size = fb->pitches[0] * aligned_height;
9178
9179         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9180                       pipe_name(pipe), fb->width, fb->height,
9181                       fb->bits_per_pixel, base, fb->pitches[0],
9182                       plane_config->size);
9183
9184         plane_config->fb = intel_fb;
9185         return;
9186
9187 error:
9188         kfree(fb);
9189 }
9190
9191 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9192                                      struct intel_crtc_state *pipe_config)
9193 {
9194         struct drm_device *dev = crtc->base.dev;
9195         struct drm_i915_private *dev_priv = dev->dev_private;
9196         uint32_t tmp;
9197
9198         tmp = I915_READ(PF_CTL(crtc->pipe));
9199
9200         if (tmp & PF_ENABLE) {
9201                 pipe_config->pch_pfit.enabled = true;
9202                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9203                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9204
9205                 /* We currently do not free assignements of panel fitters on
9206                  * ivb/hsw (since we don't use the higher upscaling modes which
9207                  * differentiates them) so just WARN about this case for now. */
9208                 if (IS_GEN7(dev)) {
9209                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9210                                 PF_PIPE_SEL_IVB(crtc->pipe));
9211                 }
9212         }
9213 }
9214
9215 static void
9216 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9217                                   struct intel_initial_plane_config *plane_config)
9218 {
9219         struct drm_device *dev = crtc->base.dev;
9220         struct drm_i915_private *dev_priv = dev->dev_private;
9221         u32 val, base, offset;
9222         int pipe = crtc->pipe;
9223         int fourcc, pixel_format;
9224         unsigned int aligned_height;
9225         struct drm_framebuffer *fb;
9226         struct intel_framebuffer *intel_fb;
9227
9228         val = I915_READ(DSPCNTR(pipe));
9229         if (!(val & DISPLAY_PLANE_ENABLE))
9230                 return;
9231
9232         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9233         if (!intel_fb) {
9234                 DRM_DEBUG_KMS("failed to alloc fb\n");
9235                 return;
9236         }
9237
9238         fb = &intel_fb->base;
9239
9240         if (INTEL_INFO(dev)->gen >= 4) {
9241                 if (val & DISPPLANE_TILED) {
9242                         plane_config->tiling = I915_TILING_X;
9243                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9244                 }
9245         }
9246
9247         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9248         fourcc = i9xx_format_to_fourcc(pixel_format);
9249         fb->pixel_format = fourcc;
9250         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9251
9252         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9253         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9254                 offset = I915_READ(DSPOFFSET(pipe));
9255         } else {
9256                 if (plane_config->tiling)
9257                         offset = I915_READ(DSPTILEOFF(pipe));
9258                 else
9259                         offset = I915_READ(DSPLINOFF(pipe));
9260         }
9261         plane_config->base = base;
9262
9263         val = I915_READ(PIPESRC(pipe));
9264         fb->width = ((val >> 16) & 0xfff) + 1;
9265         fb->height = ((val >> 0) & 0xfff) + 1;
9266
9267         val = I915_READ(DSPSTRIDE(pipe));
9268         fb->pitches[0] = val & 0xffffffc0;
9269
9270         aligned_height = intel_fb_align_height(dev, fb->height,
9271                                                fb->pixel_format,
9272                                                fb->modifier[0]);
9273
9274         plane_config->size = fb->pitches[0] * aligned_height;
9275
9276         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9277                       pipe_name(pipe), fb->width, fb->height,
9278                       fb->bits_per_pixel, base, fb->pitches[0],
9279                       plane_config->size);
9280
9281         plane_config->fb = intel_fb;
9282 }
9283
9284 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9285                                      struct intel_crtc_state *pipe_config)
9286 {
9287         struct drm_device *dev = crtc->base.dev;
9288         struct drm_i915_private *dev_priv = dev->dev_private;
9289         uint32_t tmp;
9290
9291         if (!intel_display_power_is_enabled(dev_priv,
9292                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9293                 return false;
9294
9295         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9296         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9297
9298         tmp = I915_READ(PIPECONF(crtc->pipe));
9299         if (!(tmp & PIPECONF_ENABLE))
9300                 return false;
9301
9302         switch (tmp & PIPECONF_BPC_MASK) {
9303         case PIPECONF_6BPC:
9304                 pipe_config->pipe_bpp = 18;
9305                 break;
9306         case PIPECONF_8BPC:
9307                 pipe_config->pipe_bpp = 24;
9308                 break;
9309         case PIPECONF_10BPC:
9310                 pipe_config->pipe_bpp = 30;
9311                 break;
9312         case PIPECONF_12BPC:
9313                 pipe_config->pipe_bpp = 36;
9314                 break;
9315         default:
9316                 break;
9317         }
9318
9319         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9320                 pipe_config->limited_color_range = true;
9321
9322         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9323                 struct intel_shared_dpll *pll;
9324
9325                 pipe_config->has_pch_encoder = true;
9326
9327                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9328                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9329                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9330
9331                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9332
9333                 if (HAS_PCH_IBX(dev_priv->dev)) {
9334                         pipe_config->shared_dpll =
9335                                 (enum intel_dpll_id) crtc->pipe;
9336                 } else {
9337                         tmp = I915_READ(PCH_DPLL_SEL);
9338                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9339                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9340                         else
9341                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9342                 }
9343
9344                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9345
9346                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9347                                            &pipe_config->dpll_hw_state));
9348
9349                 tmp = pipe_config->dpll_hw_state.dpll;
9350                 pipe_config->pixel_multiplier =
9351                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9352                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9353
9354                 ironlake_pch_clock_get(crtc, pipe_config);
9355         } else {
9356                 pipe_config->pixel_multiplier = 1;
9357         }
9358
9359         intel_get_pipe_timings(crtc, pipe_config);
9360
9361         ironlake_get_pfit_config(crtc, pipe_config);
9362
9363         return true;
9364 }
9365
9366 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9367 {
9368         struct drm_device *dev = dev_priv->dev;
9369         struct intel_crtc *crtc;
9370
9371         for_each_intel_crtc(dev, crtc)
9372                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9373                      pipe_name(crtc->pipe));
9374
9375         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9376         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9377         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9378         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9379         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9380         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9381              "CPU PWM1 enabled\n");
9382         if (IS_HASWELL(dev))
9383                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9384                      "CPU PWM2 enabled\n");
9385         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9386              "PCH PWM1 enabled\n");
9387         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9388              "Utility pin enabled\n");
9389         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9390
9391         /*
9392          * In theory we can still leave IRQs enabled, as long as only the HPD
9393          * interrupts remain enabled. We used to check for that, but since it's
9394          * gen-specific and since we only disable LCPLL after we fully disable
9395          * the interrupts, the check below should be enough.
9396          */
9397         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9398 }
9399
9400 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9401 {
9402         struct drm_device *dev = dev_priv->dev;
9403
9404         if (IS_HASWELL(dev))
9405                 return I915_READ(D_COMP_HSW);
9406         else
9407                 return I915_READ(D_COMP_BDW);
9408 }
9409
9410 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9411 {
9412         struct drm_device *dev = dev_priv->dev;
9413
9414         if (IS_HASWELL(dev)) {
9415                 mutex_lock(&dev_priv->rps.hw_lock);
9416                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9417                                             val))
9418                         DRM_ERROR("Failed to write to D_COMP\n");
9419                 mutex_unlock(&dev_priv->rps.hw_lock);
9420         } else {
9421                 I915_WRITE(D_COMP_BDW, val);
9422                 POSTING_READ(D_COMP_BDW);
9423         }
9424 }
9425
9426 /*
9427  * This function implements pieces of two sequences from BSpec:
9428  * - Sequence for display software to disable LCPLL
9429  * - Sequence for display software to allow package C8+
9430  * The steps implemented here are just the steps that actually touch the LCPLL
9431  * register. Callers should take care of disabling all the display engine
9432  * functions, doing the mode unset, fixing interrupts, etc.
9433  */
9434 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9435                               bool switch_to_fclk, bool allow_power_down)
9436 {
9437         uint32_t val;
9438
9439         assert_can_disable_lcpll(dev_priv);
9440
9441         val = I915_READ(LCPLL_CTL);
9442
9443         if (switch_to_fclk) {
9444                 val |= LCPLL_CD_SOURCE_FCLK;
9445                 I915_WRITE(LCPLL_CTL, val);
9446
9447                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9448                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9449                         DRM_ERROR("Switching to FCLK failed\n");
9450
9451                 val = I915_READ(LCPLL_CTL);
9452         }
9453
9454         val |= LCPLL_PLL_DISABLE;
9455         I915_WRITE(LCPLL_CTL, val);
9456         POSTING_READ(LCPLL_CTL);
9457
9458         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9459                 DRM_ERROR("LCPLL still locked\n");
9460
9461         val = hsw_read_dcomp(dev_priv);
9462         val |= D_COMP_COMP_DISABLE;
9463         hsw_write_dcomp(dev_priv, val);
9464         ndelay(100);
9465
9466         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9467                      1))
9468                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9469
9470         if (allow_power_down) {
9471                 val = I915_READ(LCPLL_CTL);
9472                 val |= LCPLL_POWER_DOWN_ALLOW;
9473                 I915_WRITE(LCPLL_CTL, val);
9474                 POSTING_READ(LCPLL_CTL);
9475         }
9476 }
9477
9478 /*
9479  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9480  * source.
9481  */
9482 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9483 {
9484         uint32_t val;
9485
9486         val = I915_READ(LCPLL_CTL);
9487
9488         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9489                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9490                 return;
9491
9492         /*
9493          * Make sure we're not on PC8 state before disabling PC8, otherwise
9494          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9495          */
9496         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9497
9498         if (val & LCPLL_POWER_DOWN_ALLOW) {
9499                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9500                 I915_WRITE(LCPLL_CTL, val);
9501                 POSTING_READ(LCPLL_CTL);
9502         }
9503
9504         val = hsw_read_dcomp(dev_priv);
9505         val |= D_COMP_COMP_FORCE;
9506         val &= ~D_COMP_COMP_DISABLE;
9507         hsw_write_dcomp(dev_priv, val);
9508
9509         val = I915_READ(LCPLL_CTL);
9510         val &= ~LCPLL_PLL_DISABLE;
9511         I915_WRITE(LCPLL_CTL, val);
9512
9513         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9514                 DRM_ERROR("LCPLL not locked yet\n");
9515
9516         if (val & LCPLL_CD_SOURCE_FCLK) {
9517                 val = I915_READ(LCPLL_CTL);
9518                 val &= ~LCPLL_CD_SOURCE_FCLK;
9519                 I915_WRITE(LCPLL_CTL, val);
9520
9521                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9522                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9523                         DRM_ERROR("Switching back to LCPLL failed\n");
9524         }
9525
9526         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9527         intel_update_cdclk(dev_priv->dev);
9528 }
9529
9530 /*
9531  * Package states C8 and deeper are really deep PC states that can only be
9532  * reached when all the devices on the system allow it, so even if the graphics
9533  * device allows PC8+, it doesn't mean the system will actually get to these
9534  * states. Our driver only allows PC8+ when going into runtime PM.
9535  *
9536  * The requirements for PC8+ are that all the outputs are disabled, the power
9537  * well is disabled and most interrupts are disabled, and these are also
9538  * requirements for runtime PM. When these conditions are met, we manually do
9539  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9540  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9541  * hang the machine.
9542  *
9543  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9544  * the state of some registers, so when we come back from PC8+ we need to
9545  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9546  * need to take care of the registers kept by RC6. Notice that this happens even
9547  * if we don't put the device in PCI D3 state (which is what currently happens
9548  * because of the runtime PM support).
9549  *
9550  * For more, read "Display Sequences for Package C8" on the hardware
9551  * documentation.
9552  */
9553 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9554 {
9555         struct drm_device *dev = dev_priv->dev;
9556         uint32_t val;
9557
9558         DRM_DEBUG_KMS("Enabling package C8+\n");
9559
9560         if (HAS_PCH_LPT_LP(dev)) {
9561                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9562                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9563                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9564         }
9565
9566         lpt_disable_clkout_dp(dev);
9567         hsw_disable_lcpll(dev_priv, true, true);
9568 }
9569
9570 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9571 {
9572         struct drm_device *dev = dev_priv->dev;
9573         uint32_t val;
9574
9575         DRM_DEBUG_KMS("Disabling package C8+\n");
9576
9577         hsw_restore_lcpll(dev_priv);
9578         lpt_init_pch_refclk(dev);
9579
9580         if (HAS_PCH_LPT_LP(dev)) {
9581                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9582                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9583                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9584         }
9585
9586         intel_prepare_ddi(dev);
9587 }
9588
9589 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9590 {
9591         struct drm_device *dev = old_state->dev;
9592         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9593
9594         broxton_set_cdclk(dev, req_cdclk);
9595 }
9596
9597 /* compute the max rate for new configuration */
9598 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9599 {
9600         struct intel_crtc *intel_crtc;
9601         struct intel_crtc_state *crtc_state;
9602         int max_pixel_rate = 0;
9603
9604         for_each_intel_crtc(state->dev, intel_crtc) {
9605                 int pixel_rate;
9606
9607                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9608                 if (IS_ERR(crtc_state))
9609                         return PTR_ERR(crtc_state);
9610
9611                 if (!crtc_state->base.enable)
9612                         continue;
9613
9614                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9615
9616                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9617                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9618                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9619
9620                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9621         }
9622
9623         return max_pixel_rate;
9624 }
9625
9626 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9627 {
9628         struct drm_i915_private *dev_priv = dev->dev_private;
9629         uint32_t val, data;
9630         int ret;
9631
9632         if (WARN((I915_READ(LCPLL_CTL) &
9633                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9634                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9635                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9636                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9637                  "trying to change cdclk frequency with cdclk not enabled\n"))
9638                 return;
9639
9640         mutex_lock(&dev_priv->rps.hw_lock);
9641         ret = sandybridge_pcode_write(dev_priv,
9642                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9643         mutex_unlock(&dev_priv->rps.hw_lock);
9644         if (ret) {
9645                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9646                 return;
9647         }
9648
9649         val = I915_READ(LCPLL_CTL);
9650         val |= LCPLL_CD_SOURCE_FCLK;
9651         I915_WRITE(LCPLL_CTL, val);
9652
9653         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9654                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9655                 DRM_ERROR("Switching to FCLK failed\n");
9656
9657         val = I915_READ(LCPLL_CTL);
9658         val &= ~LCPLL_CLK_FREQ_MASK;
9659
9660         switch (cdclk) {
9661         case 450000:
9662                 val |= LCPLL_CLK_FREQ_450;
9663                 data = 0;
9664                 break;
9665         case 540000:
9666                 val |= LCPLL_CLK_FREQ_54O_BDW;
9667                 data = 1;
9668                 break;
9669         case 337500:
9670                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9671                 data = 2;
9672                 break;
9673         case 675000:
9674                 val |= LCPLL_CLK_FREQ_675_BDW;
9675                 data = 3;
9676                 break;
9677         default:
9678                 WARN(1, "invalid cdclk frequency\n");
9679                 return;
9680         }
9681
9682         I915_WRITE(LCPLL_CTL, val);
9683
9684         val = I915_READ(LCPLL_CTL);
9685         val &= ~LCPLL_CD_SOURCE_FCLK;
9686         I915_WRITE(LCPLL_CTL, val);
9687
9688         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9689                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9690                 DRM_ERROR("Switching back to LCPLL failed\n");
9691
9692         mutex_lock(&dev_priv->rps.hw_lock);
9693         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9694         mutex_unlock(&dev_priv->rps.hw_lock);
9695
9696         intel_update_cdclk(dev);
9697
9698         WARN(cdclk != dev_priv->cdclk_freq,
9699              "cdclk requested %d kHz but got %d kHz\n",
9700              cdclk, dev_priv->cdclk_freq);
9701 }
9702
9703 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9704 {
9705         struct drm_i915_private *dev_priv = to_i915(state->dev);
9706         int max_pixclk = ilk_max_pixel_rate(state);
9707         int cdclk;
9708
9709         /*
9710          * FIXME should also account for plane ratio
9711          * once 64bpp pixel formats are supported.
9712          */
9713         if (max_pixclk > 540000)
9714                 cdclk = 675000;
9715         else if (max_pixclk > 450000)
9716                 cdclk = 540000;
9717         else if (max_pixclk > 337500)
9718                 cdclk = 450000;
9719         else
9720                 cdclk = 337500;
9721
9722         /*
9723          * FIXME move the cdclk caclulation to
9724          * compute_config() so we can fail gracegully.
9725          */
9726         if (cdclk > dev_priv->max_cdclk_freq) {
9727                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9728                           cdclk, dev_priv->max_cdclk_freq);
9729                 cdclk = dev_priv->max_cdclk_freq;
9730         }
9731
9732         to_intel_atomic_state(state)->cdclk = cdclk;
9733
9734         return 0;
9735 }
9736
9737 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9738 {
9739         struct drm_device *dev = old_state->dev;
9740         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9741
9742         broadwell_set_cdclk(dev, req_cdclk);
9743 }
9744
9745 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9746                                       struct intel_crtc_state *crtc_state)
9747 {
9748         if (!intel_ddi_pll_select(crtc, crtc_state))
9749                 return -EINVAL;
9750
9751         crtc->lowfreq_avail = false;
9752
9753         return 0;
9754 }
9755
9756 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9757                                 enum port port,
9758                                 struct intel_crtc_state *pipe_config)
9759 {
9760         switch (port) {
9761         case PORT_A:
9762                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9763                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9764                 break;
9765         case PORT_B:
9766                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9767                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9768                 break;
9769         case PORT_C:
9770                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9771                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9772                 break;
9773         default:
9774                 DRM_ERROR("Incorrect port type\n");
9775         }
9776 }
9777
9778 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9779                                 enum port port,
9780                                 struct intel_crtc_state *pipe_config)
9781 {
9782         u32 temp, dpll_ctl1;
9783
9784         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9785         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9786
9787         switch (pipe_config->ddi_pll_sel) {
9788         case SKL_DPLL0:
9789                 /*
9790                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9791                  * of the shared DPLL framework and thus needs to be read out
9792                  * separately
9793                  */
9794                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9795                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9796                 break;
9797         case SKL_DPLL1:
9798                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9799                 break;
9800         case SKL_DPLL2:
9801                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9802                 break;
9803         case SKL_DPLL3:
9804                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9805                 break;
9806         }
9807 }
9808
9809 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9810                                 enum port port,
9811                                 struct intel_crtc_state *pipe_config)
9812 {
9813         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9814
9815         switch (pipe_config->ddi_pll_sel) {
9816         case PORT_CLK_SEL_WRPLL1:
9817                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9818                 break;
9819         case PORT_CLK_SEL_WRPLL2:
9820                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9821                 break;
9822         case PORT_CLK_SEL_SPLL:
9823                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9824         }
9825 }
9826
9827 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9828                                        struct intel_crtc_state *pipe_config)
9829 {
9830         struct drm_device *dev = crtc->base.dev;
9831         struct drm_i915_private *dev_priv = dev->dev_private;
9832         struct intel_shared_dpll *pll;
9833         enum port port;
9834         uint32_t tmp;
9835
9836         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9837
9838         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9839
9840         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9841                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9842         else if (IS_BROXTON(dev))
9843                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9844         else
9845                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9846
9847         if (pipe_config->shared_dpll >= 0) {
9848                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9849
9850                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9851                                            &pipe_config->dpll_hw_state));
9852         }
9853
9854         /*
9855          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9856          * DDI E. So just check whether this pipe is wired to DDI E and whether
9857          * the PCH transcoder is on.
9858          */
9859         if (INTEL_INFO(dev)->gen < 9 &&
9860             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9861                 pipe_config->has_pch_encoder = true;
9862
9863                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9864                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9865                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9866
9867                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9868         }
9869 }
9870
9871 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9872                                     struct intel_crtc_state *pipe_config)
9873 {
9874         struct drm_device *dev = crtc->base.dev;
9875         struct drm_i915_private *dev_priv = dev->dev_private;
9876         enum intel_display_power_domain pfit_domain;
9877         uint32_t tmp;
9878
9879         if (!intel_display_power_is_enabled(dev_priv,
9880                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9881                 return false;
9882
9883         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9884         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9885
9886         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9887         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9888                 enum pipe trans_edp_pipe;
9889                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9890                 default:
9891                         WARN(1, "unknown pipe linked to edp transcoder\n");
9892                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9893                 case TRANS_DDI_EDP_INPUT_A_ON:
9894                         trans_edp_pipe = PIPE_A;
9895                         break;
9896                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9897                         trans_edp_pipe = PIPE_B;
9898                         break;
9899                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9900                         trans_edp_pipe = PIPE_C;
9901                         break;
9902                 }
9903
9904                 if (trans_edp_pipe == crtc->pipe)
9905                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9906         }
9907
9908         if (!intel_display_power_is_enabled(dev_priv,
9909                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9910                 return false;
9911
9912         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9913         if (!(tmp & PIPECONF_ENABLE))
9914                 return false;
9915
9916         haswell_get_ddi_port_state(crtc, pipe_config);
9917
9918         intel_get_pipe_timings(crtc, pipe_config);
9919
9920         if (INTEL_INFO(dev)->gen >= 9) {
9921                 skl_init_scalers(dev, crtc, pipe_config);
9922         }
9923
9924         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9925
9926         if (INTEL_INFO(dev)->gen >= 9) {
9927                 pipe_config->scaler_state.scaler_id = -1;
9928                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9929         }
9930
9931         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9932                 if (INTEL_INFO(dev)->gen >= 9)
9933                         skylake_get_pfit_config(crtc, pipe_config);
9934                 else
9935                         ironlake_get_pfit_config(crtc, pipe_config);
9936         }
9937
9938         if (IS_HASWELL(dev))
9939                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9940                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9941
9942         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9943                 pipe_config->pixel_multiplier =
9944                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9945         } else {
9946                 pipe_config->pixel_multiplier = 1;
9947         }
9948
9949         return true;
9950 }
9951
9952 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9953 {
9954         struct drm_device *dev = crtc->dev;
9955         struct drm_i915_private *dev_priv = dev->dev_private;
9956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9957         uint32_t cntl = 0, size = 0;
9958
9959         if (base) {
9960                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9961                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9962                 unsigned int stride = roundup_pow_of_two(width) * 4;
9963
9964                 switch (stride) {
9965                 default:
9966                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9967                                   width, stride);
9968                         stride = 256;
9969                         /* fallthrough */
9970                 case 256:
9971                 case 512:
9972                 case 1024:
9973                 case 2048:
9974                         break;
9975                 }
9976
9977                 cntl |= CURSOR_ENABLE |
9978                         CURSOR_GAMMA_ENABLE |
9979                         CURSOR_FORMAT_ARGB |
9980                         CURSOR_STRIDE(stride);
9981
9982                 size = (height << 12) | width;
9983         }
9984
9985         if (intel_crtc->cursor_cntl != 0 &&
9986             (intel_crtc->cursor_base != base ||
9987              intel_crtc->cursor_size != size ||
9988              intel_crtc->cursor_cntl != cntl)) {
9989                 /* On these chipsets we can only modify the base/size/stride
9990                  * whilst the cursor is disabled.
9991                  */
9992                 I915_WRITE(CURCNTR(PIPE_A), 0);
9993                 POSTING_READ(CURCNTR(PIPE_A));
9994                 intel_crtc->cursor_cntl = 0;
9995         }
9996
9997         if (intel_crtc->cursor_base != base) {
9998                 I915_WRITE(CURBASE(PIPE_A), base);
9999                 intel_crtc->cursor_base = base;
10000         }
10001
10002         if (intel_crtc->cursor_size != size) {
10003                 I915_WRITE(CURSIZE, size);
10004                 intel_crtc->cursor_size = size;
10005         }
10006
10007         if (intel_crtc->cursor_cntl != cntl) {
10008                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10009                 POSTING_READ(CURCNTR(PIPE_A));
10010                 intel_crtc->cursor_cntl = cntl;
10011         }
10012 }
10013
10014 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10015 {
10016         struct drm_device *dev = crtc->dev;
10017         struct drm_i915_private *dev_priv = dev->dev_private;
10018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10019         int pipe = intel_crtc->pipe;
10020         uint32_t cntl;
10021
10022         cntl = 0;
10023         if (base) {
10024                 cntl = MCURSOR_GAMMA_ENABLE;
10025                 switch (intel_crtc->base.cursor->state->crtc_w) {
10026                         case 64:
10027                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10028                                 break;
10029                         case 128:
10030                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10031                                 break;
10032                         case 256:
10033                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10034                                 break;
10035                         default:
10036                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10037                                 return;
10038                 }
10039                 cntl |= pipe << 28; /* Connect to correct pipe */
10040
10041                 if (HAS_DDI(dev))
10042                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10043         }
10044
10045         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10046                 cntl |= CURSOR_ROTATE_180;
10047
10048         if (intel_crtc->cursor_cntl != cntl) {
10049                 I915_WRITE(CURCNTR(pipe), cntl);
10050                 POSTING_READ(CURCNTR(pipe));
10051                 intel_crtc->cursor_cntl = cntl;
10052         }
10053
10054         /* and commit changes on next vblank */
10055         I915_WRITE(CURBASE(pipe), base);
10056         POSTING_READ(CURBASE(pipe));
10057
10058         intel_crtc->cursor_base = base;
10059 }
10060
10061 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10062 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10063                                      bool on)
10064 {
10065         struct drm_device *dev = crtc->dev;
10066         struct drm_i915_private *dev_priv = dev->dev_private;
10067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10068         int pipe = intel_crtc->pipe;
10069         struct drm_plane_state *cursor_state = crtc->cursor->state;
10070         int x = cursor_state->crtc_x;
10071         int y = cursor_state->crtc_y;
10072         u32 base = 0, pos = 0;
10073
10074         if (on)
10075                 base = intel_crtc->cursor_addr;
10076
10077         if (x >= intel_crtc->config->pipe_src_w)
10078                 base = 0;
10079
10080         if (y >= intel_crtc->config->pipe_src_h)
10081                 base = 0;
10082
10083         if (x < 0) {
10084                 if (x + cursor_state->crtc_w <= 0)
10085                         base = 0;
10086
10087                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10088                 x = -x;
10089         }
10090         pos |= x << CURSOR_X_SHIFT;
10091
10092         if (y < 0) {
10093                 if (y + cursor_state->crtc_h <= 0)
10094                         base = 0;
10095
10096                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10097                 y = -y;
10098         }
10099         pos |= y << CURSOR_Y_SHIFT;
10100
10101         if (base == 0 && intel_crtc->cursor_base == 0)
10102                 return;
10103
10104         I915_WRITE(CURPOS(pipe), pos);
10105
10106         /* ILK+ do this automagically */
10107         if (HAS_GMCH_DISPLAY(dev) &&
10108             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10109                 base += (cursor_state->crtc_h *
10110                          cursor_state->crtc_w - 1) * 4;
10111         }
10112
10113         if (IS_845G(dev) || IS_I865G(dev))
10114                 i845_update_cursor(crtc, base);
10115         else
10116                 i9xx_update_cursor(crtc, base);
10117 }
10118
10119 static bool cursor_size_ok(struct drm_device *dev,
10120                            uint32_t width, uint32_t height)
10121 {
10122         if (width == 0 || height == 0)
10123                 return false;
10124
10125         /*
10126          * 845g/865g are special in that they are only limited by
10127          * the width of their cursors, the height is arbitrary up to
10128          * the precision of the register. Everything else requires
10129          * square cursors, limited to a few power-of-two sizes.
10130          */
10131         if (IS_845G(dev) || IS_I865G(dev)) {
10132                 if ((width & 63) != 0)
10133                         return false;
10134
10135                 if (width > (IS_845G(dev) ? 64 : 512))
10136                         return false;
10137
10138                 if (height > 1023)
10139                         return false;
10140         } else {
10141                 switch (width | height) {
10142                 case 256:
10143                 case 128:
10144                         if (IS_GEN2(dev))
10145                                 return false;
10146                 case 64:
10147                         break;
10148                 default:
10149                         return false;
10150                 }
10151         }
10152
10153         return true;
10154 }
10155
10156 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10157                                  u16 *blue, uint32_t start, uint32_t size)
10158 {
10159         int end = (start + size > 256) ? 256 : start + size, i;
10160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10161
10162         for (i = start; i < end; i++) {
10163                 intel_crtc->lut_r[i] = red[i] >> 8;
10164                 intel_crtc->lut_g[i] = green[i] >> 8;
10165                 intel_crtc->lut_b[i] = blue[i] >> 8;
10166         }
10167
10168         intel_crtc_load_lut(crtc);
10169 }
10170
10171 /* VESA 640x480x72Hz mode to set on the pipe */
10172 static struct drm_display_mode load_detect_mode = {
10173         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10174                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10175 };
10176
10177 struct drm_framebuffer *
10178 __intel_framebuffer_create(struct drm_device *dev,
10179                            struct drm_mode_fb_cmd2 *mode_cmd,
10180                            struct drm_i915_gem_object *obj)
10181 {
10182         struct intel_framebuffer *intel_fb;
10183         int ret;
10184
10185         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10186         if (!intel_fb)
10187                 return ERR_PTR(-ENOMEM);
10188
10189         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10190         if (ret)
10191                 goto err;
10192
10193         return &intel_fb->base;
10194
10195 err:
10196         kfree(intel_fb);
10197         return ERR_PTR(ret);
10198 }
10199
10200 static struct drm_framebuffer *
10201 intel_framebuffer_create(struct drm_device *dev,
10202                          struct drm_mode_fb_cmd2 *mode_cmd,
10203                          struct drm_i915_gem_object *obj)
10204 {
10205         struct drm_framebuffer *fb;
10206         int ret;
10207
10208         ret = i915_mutex_lock_interruptible(dev);
10209         if (ret)
10210                 return ERR_PTR(ret);
10211         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10212         mutex_unlock(&dev->struct_mutex);
10213
10214         return fb;
10215 }
10216
10217 static u32
10218 intel_framebuffer_pitch_for_width(int width, int bpp)
10219 {
10220         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10221         return ALIGN(pitch, 64);
10222 }
10223
10224 static u32
10225 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10226 {
10227         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10228         return PAGE_ALIGN(pitch * mode->vdisplay);
10229 }
10230
10231 static struct drm_framebuffer *
10232 intel_framebuffer_create_for_mode(struct drm_device *dev,
10233                                   struct drm_display_mode *mode,
10234                                   int depth, int bpp)
10235 {
10236         struct drm_framebuffer *fb;
10237         struct drm_i915_gem_object *obj;
10238         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10239
10240         obj = i915_gem_alloc_object(dev,
10241                                     intel_framebuffer_size_for_mode(mode, bpp));
10242         if (obj == NULL)
10243                 return ERR_PTR(-ENOMEM);
10244
10245         mode_cmd.width = mode->hdisplay;
10246         mode_cmd.height = mode->vdisplay;
10247         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10248                                                                 bpp);
10249         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10250
10251         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10252         if (IS_ERR(fb))
10253                 drm_gem_object_unreference_unlocked(&obj->base);
10254
10255         return fb;
10256 }
10257
10258 static struct drm_framebuffer *
10259 mode_fits_in_fbdev(struct drm_device *dev,
10260                    struct drm_display_mode *mode)
10261 {
10262 #ifdef CONFIG_DRM_FBDEV_EMULATION
10263         struct drm_i915_private *dev_priv = dev->dev_private;
10264         struct drm_i915_gem_object *obj;
10265         struct drm_framebuffer *fb;
10266
10267         if (!dev_priv->fbdev)
10268                 return NULL;
10269
10270         if (!dev_priv->fbdev->fb)
10271                 return NULL;
10272
10273         obj = dev_priv->fbdev->fb->obj;
10274         BUG_ON(!obj);
10275
10276         fb = &dev_priv->fbdev->fb->base;
10277         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10278                                                                fb->bits_per_pixel))
10279                 return NULL;
10280
10281         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10282                 return NULL;
10283
10284         return fb;
10285 #else
10286         return NULL;
10287 #endif
10288 }
10289
10290 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10291                                            struct drm_crtc *crtc,
10292                                            struct drm_display_mode *mode,
10293                                            struct drm_framebuffer *fb,
10294                                            int x, int y)
10295 {
10296         struct drm_plane_state *plane_state;
10297         int hdisplay, vdisplay;
10298         int ret;
10299
10300         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10301         if (IS_ERR(plane_state))
10302                 return PTR_ERR(plane_state);
10303
10304         if (mode)
10305                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10306         else
10307                 hdisplay = vdisplay = 0;
10308
10309         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10310         if (ret)
10311                 return ret;
10312         drm_atomic_set_fb_for_plane(plane_state, fb);
10313         plane_state->crtc_x = 0;
10314         plane_state->crtc_y = 0;
10315         plane_state->crtc_w = hdisplay;
10316         plane_state->crtc_h = vdisplay;
10317         plane_state->src_x = x << 16;
10318         plane_state->src_y = y << 16;
10319         plane_state->src_w = hdisplay << 16;
10320         plane_state->src_h = vdisplay << 16;
10321
10322         return 0;
10323 }
10324
10325 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10326                                 struct drm_display_mode *mode,
10327                                 struct intel_load_detect_pipe *old,
10328                                 struct drm_modeset_acquire_ctx *ctx)
10329 {
10330         struct intel_crtc *intel_crtc;
10331         struct intel_encoder *intel_encoder =
10332                 intel_attached_encoder(connector);
10333         struct drm_crtc *possible_crtc;
10334         struct drm_encoder *encoder = &intel_encoder->base;
10335         struct drm_crtc *crtc = NULL;
10336         struct drm_device *dev = encoder->dev;
10337         struct drm_framebuffer *fb;
10338         struct drm_mode_config *config = &dev->mode_config;
10339         struct drm_atomic_state *state = NULL;
10340         struct drm_connector_state *connector_state;
10341         struct intel_crtc_state *crtc_state;
10342         int ret, i = -1;
10343
10344         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10345                       connector->base.id, connector->name,
10346                       encoder->base.id, encoder->name);
10347
10348 retry:
10349         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10350         if (ret)
10351                 goto fail;
10352
10353         /*
10354          * Algorithm gets a little messy:
10355          *
10356          *   - if the connector already has an assigned crtc, use it (but make
10357          *     sure it's on first)
10358          *
10359          *   - try to find the first unused crtc that can drive this connector,
10360          *     and use that if we find one
10361          */
10362
10363         /* See if we already have a CRTC for this connector */
10364         if (encoder->crtc) {
10365                 crtc = encoder->crtc;
10366
10367                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10368                 if (ret)
10369                         goto fail;
10370                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10371                 if (ret)
10372                         goto fail;
10373
10374                 old->dpms_mode = connector->dpms;
10375                 old->load_detect_temp = false;
10376
10377                 /* Make sure the crtc and connector are running */
10378                 if (connector->dpms != DRM_MODE_DPMS_ON)
10379                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10380
10381                 return true;
10382         }
10383
10384         /* Find an unused one (if possible) */
10385         for_each_crtc(dev, possible_crtc) {
10386                 i++;
10387                 if (!(encoder->possible_crtcs & (1 << i)))
10388                         continue;
10389                 if (possible_crtc->state->enable)
10390                         continue;
10391
10392                 crtc = possible_crtc;
10393                 break;
10394         }
10395
10396         /*
10397          * If we didn't find an unused CRTC, don't use any.
10398          */
10399         if (!crtc) {
10400                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10401                 goto fail;
10402         }
10403
10404         ret = drm_modeset_lock(&crtc->mutex, ctx);
10405         if (ret)
10406                 goto fail;
10407         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10408         if (ret)
10409                 goto fail;
10410
10411         intel_crtc = to_intel_crtc(crtc);
10412         old->dpms_mode = connector->dpms;
10413         old->load_detect_temp = true;
10414         old->release_fb = NULL;
10415
10416         state = drm_atomic_state_alloc(dev);
10417         if (!state)
10418                 return false;
10419
10420         state->acquire_ctx = ctx;
10421
10422         connector_state = drm_atomic_get_connector_state(state, connector);
10423         if (IS_ERR(connector_state)) {
10424                 ret = PTR_ERR(connector_state);
10425                 goto fail;
10426         }
10427
10428         connector_state->crtc = crtc;
10429         connector_state->best_encoder = &intel_encoder->base;
10430
10431         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10432         if (IS_ERR(crtc_state)) {
10433                 ret = PTR_ERR(crtc_state);
10434                 goto fail;
10435         }
10436
10437         crtc_state->base.active = crtc_state->base.enable = true;
10438
10439         if (!mode)
10440                 mode = &load_detect_mode;
10441
10442         /* We need a framebuffer large enough to accommodate all accesses
10443          * that the plane may generate whilst we perform load detection.
10444          * We can not rely on the fbcon either being present (we get called
10445          * during its initialisation to detect all boot displays, or it may
10446          * not even exist) or that it is large enough to satisfy the
10447          * requested mode.
10448          */
10449         fb = mode_fits_in_fbdev(dev, mode);
10450         if (fb == NULL) {
10451                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10452                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10453                 old->release_fb = fb;
10454         } else
10455                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10456         if (IS_ERR(fb)) {
10457                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10458                 goto fail;
10459         }
10460
10461         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10462         if (ret)
10463                 goto fail;
10464
10465         drm_mode_copy(&crtc_state->base.mode, mode);
10466
10467         if (drm_atomic_commit(state)) {
10468                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10469                 if (old->release_fb)
10470                         old->release_fb->funcs->destroy(old->release_fb);
10471                 goto fail;
10472         }
10473         crtc->primary->crtc = crtc;
10474
10475         /* let the connector get through one full cycle before testing */
10476         intel_wait_for_vblank(dev, intel_crtc->pipe);
10477         return true;
10478
10479 fail:
10480         drm_atomic_state_free(state);
10481         state = NULL;
10482
10483         if (ret == -EDEADLK) {
10484                 drm_modeset_backoff(ctx);
10485                 goto retry;
10486         }
10487
10488         return false;
10489 }
10490
10491 void intel_release_load_detect_pipe(struct drm_connector *connector,
10492                                     struct intel_load_detect_pipe *old,
10493                                     struct drm_modeset_acquire_ctx *ctx)
10494 {
10495         struct drm_device *dev = connector->dev;
10496         struct intel_encoder *intel_encoder =
10497                 intel_attached_encoder(connector);
10498         struct drm_encoder *encoder = &intel_encoder->base;
10499         struct drm_crtc *crtc = encoder->crtc;
10500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10501         struct drm_atomic_state *state;
10502         struct drm_connector_state *connector_state;
10503         struct intel_crtc_state *crtc_state;
10504         int ret;
10505
10506         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10507                       connector->base.id, connector->name,
10508                       encoder->base.id, encoder->name);
10509
10510         if (old->load_detect_temp) {
10511                 state = drm_atomic_state_alloc(dev);
10512                 if (!state)
10513                         goto fail;
10514
10515                 state->acquire_ctx = ctx;
10516
10517                 connector_state = drm_atomic_get_connector_state(state, connector);
10518                 if (IS_ERR(connector_state))
10519                         goto fail;
10520
10521                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10522                 if (IS_ERR(crtc_state))
10523                         goto fail;
10524
10525                 connector_state->best_encoder = NULL;
10526                 connector_state->crtc = NULL;
10527
10528                 crtc_state->base.enable = crtc_state->base.active = false;
10529
10530                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10531                                                       0, 0);
10532                 if (ret)
10533                         goto fail;
10534
10535                 ret = drm_atomic_commit(state);
10536                 if (ret)
10537                         goto fail;
10538
10539                 if (old->release_fb) {
10540                         drm_framebuffer_unregister_private(old->release_fb);
10541                         drm_framebuffer_unreference(old->release_fb);
10542                 }
10543
10544                 return;
10545         }
10546
10547         /* Switch crtc and encoder back off if necessary */
10548         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10549                 connector->funcs->dpms(connector, old->dpms_mode);
10550
10551         return;
10552 fail:
10553         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10554         drm_atomic_state_free(state);
10555 }
10556
10557 static int i9xx_pll_refclk(struct drm_device *dev,
10558                            const struct intel_crtc_state *pipe_config)
10559 {
10560         struct drm_i915_private *dev_priv = dev->dev_private;
10561         u32 dpll = pipe_config->dpll_hw_state.dpll;
10562
10563         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10564                 return dev_priv->vbt.lvds_ssc_freq;
10565         else if (HAS_PCH_SPLIT(dev))
10566                 return 120000;
10567         else if (!IS_GEN2(dev))
10568                 return 96000;
10569         else
10570                 return 48000;
10571 }
10572
10573 /* Returns the clock of the currently programmed mode of the given pipe. */
10574 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10575                                 struct intel_crtc_state *pipe_config)
10576 {
10577         struct drm_device *dev = crtc->base.dev;
10578         struct drm_i915_private *dev_priv = dev->dev_private;
10579         int pipe = pipe_config->cpu_transcoder;
10580         u32 dpll = pipe_config->dpll_hw_state.dpll;
10581         u32 fp;
10582         intel_clock_t clock;
10583         int port_clock;
10584         int refclk = i9xx_pll_refclk(dev, pipe_config);
10585
10586         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10587                 fp = pipe_config->dpll_hw_state.fp0;
10588         else
10589                 fp = pipe_config->dpll_hw_state.fp1;
10590
10591         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10592         if (IS_PINEVIEW(dev)) {
10593                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10594                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10595         } else {
10596                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10597                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10598         }
10599
10600         if (!IS_GEN2(dev)) {
10601                 if (IS_PINEVIEW(dev))
10602                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10603                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10604                 else
10605                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10606                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10607
10608                 switch (dpll & DPLL_MODE_MASK) {
10609                 case DPLLB_MODE_DAC_SERIAL:
10610                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10611                                 5 : 10;
10612                         break;
10613                 case DPLLB_MODE_LVDS:
10614                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10615                                 7 : 14;
10616                         break;
10617                 default:
10618                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10619                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10620                         return;
10621                 }
10622
10623                 if (IS_PINEVIEW(dev))
10624                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10625                 else
10626                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10627         } else {
10628                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10629                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10630
10631                 if (is_lvds) {
10632                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10633                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10634
10635                         if (lvds & LVDS_CLKB_POWER_UP)
10636                                 clock.p2 = 7;
10637                         else
10638                                 clock.p2 = 14;
10639                 } else {
10640                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10641                                 clock.p1 = 2;
10642                         else {
10643                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10644                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10645                         }
10646                         if (dpll & PLL_P2_DIVIDE_BY_4)
10647                                 clock.p2 = 4;
10648                         else
10649                                 clock.p2 = 2;
10650                 }
10651
10652                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10653         }
10654
10655         /*
10656          * This value includes pixel_multiplier. We will use
10657          * port_clock to compute adjusted_mode.crtc_clock in the
10658          * encoder's get_config() function.
10659          */
10660         pipe_config->port_clock = port_clock;
10661 }
10662
10663 int intel_dotclock_calculate(int link_freq,
10664                              const struct intel_link_m_n *m_n)
10665 {
10666         /*
10667          * The calculation for the data clock is:
10668          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10669          * But we want to avoid losing precison if possible, so:
10670          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10671          *
10672          * and the link clock is simpler:
10673          * link_clock = (m * link_clock) / n
10674          */
10675
10676         if (!m_n->link_n)
10677                 return 0;
10678
10679         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10680 }
10681
10682 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10683                                    struct intel_crtc_state *pipe_config)
10684 {
10685         struct drm_device *dev = crtc->base.dev;
10686
10687         /* read out port_clock from the DPLL */
10688         i9xx_crtc_clock_get(crtc, pipe_config);
10689
10690         /*
10691          * This value does not include pixel_multiplier.
10692          * We will check that port_clock and adjusted_mode.crtc_clock
10693          * agree once we know their relationship in the encoder's
10694          * get_config() function.
10695          */
10696         pipe_config->base.adjusted_mode.crtc_clock =
10697                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10698                                          &pipe_config->fdi_m_n);
10699 }
10700
10701 /** Returns the currently programmed mode of the given pipe. */
10702 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10703                                              struct drm_crtc *crtc)
10704 {
10705         struct drm_i915_private *dev_priv = dev->dev_private;
10706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10707         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10708         struct drm_display_mode *mode;
10709         struct intel_crtc_state pipe_config;
10710         int htot = I915_READ(HTOTAL(cpu_transcoder));
10711         int hsync = I915_READ(HSYNC(cpu_transcoder));
10712         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10713         int vsync = I915_READ(VSYNC(cpu_transcoder));
10714         enum pipe pipe = intel_crtc->pipe;
10715
10716         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10717         if (!mode)
10718                 return NULL;
10719
10720         /*
10721          * Construct a pipe_config sufficient for getting the clock info
10722          * back out of crtc_clock_get.
10723          *
10724          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10725          * to use a real value here instead.
10726          */
10727         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10728         pipe_config.pixel_multiplier = 1;
10729         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10730         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10731         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10732         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10733
10734         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10735         mode->hdisplay = (htot & 0xffff) + 1;
10736         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10737         mode->hsync_start = (hsync & 0xffff) + 1;
10738         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10739         mode->vdisplay = (vtot & 0xffff) + 1;
10740         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10741         mode->vsync_start = (vsync & 0xffff) + 1;
10742         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10743
10744         drm_mode_set_name(mode);
10745
10746         return mode;
10747 }
10748
10749 void intel_mark_busy(struct drm_device *dev)
10750 {
10751         struct drm_i915_private *dev_priv = dev->dev_private;
10752
10753         if (dev_priv->mm.busy)
10754                 return;
10755
10756         intel_runtime_pm_get(dev_priv);
10757         i915_update_gfx_val(dev_priv);
10758         if (INTEL_INFO(dev)->gen >= 6)
10759                 gen6_rps_busy(dev_priv);
10760         dev_priv->mm.busy = true;
10761 }
10762
10763 void intel_mark_idle(struct drm_device *dev)
10764 {
10765         struct drm_i915_private *dev_priv = dev->dev_private;
10766
10767         if (!dev_priv->mm.busy)
10768                 return;
10769
10770         dev_priv->mm.busy = false;
10771
10772         if (INTEL_INFO(dev)->gen >= 6)
10773                 gen6_rps_idle(dev->dev_private);
10774
10775         intel_runtime_pm_put(dev_priv);
10776 }
10777
10778 static void intel_crtc_destroy(struct drm_crtc *crtc)
10779 {
10780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10781         struct drm_device *dev = crtc->dev;
10782         struct intel_unpin_work *work;
10783
10784         spin_lock_irq(&dev->event_lock);
10785         work = intel_crtc->unpin_work;
10786         intel_crtc->unpin_work = NULL;
10787         spin_unlock_irq(&dev->event_lock);
10788
10789         if (work) {
10790                 cancel_work_sync(&work->work);
10791                 kfree(work);
10792         }
10793
10794         drm_crtc_cleanup(crtc);
10795
10796         kfree(intel_crtc);
10797 }
10798
10799 static void intel_unpin_work_fn(struct work_struct *__work)
10800 {
10801         struct intel_unpin_work *work =
10802                 container_of(__work, struct intel_unpin_work, work);
10803         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10804         struct drm_device *dev = crtc->base.dev;
10805         struct drm_plane *primary = crtc->base.primary;
10806
10807         mutex_lock(&dev->struct_mutex);
10808         intel_unpin_fb_obj(work->old_fb, primary->state);
10809         drm_gem_object_unreference(&work->pending_flip_obj->base);
10810
10811         if (work->flip_queued_req)
10812                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10813         mutex_unlock(&dev->struct_mutex);
10814
10815         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10816         drm_framebuffer_unreference(work->old_fb);
10817
10818         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10819         atomic_dec(&crtc->unpin_work_count);
10820
10821         kfree(work);
10822 }
10823
10824 static void do_intel_finish_page_flip(struct drm_device *dev,
10825                                       struct drm_crtc *crtc)
10826 {
10827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10828         struct intel_unpin_work *work;
10829         unsigned long flags;
10830
10831         /* Ignore early vblank irqs */
10832         if (intel_crtc == NULL)
10833                 return;
10834
10835         /*
10836          * This is called both by irq handlers and the reset code (to complete
10837          * lost pageflips) so needs the full irqsave spinlocks.
10838          */
10839         spin_lock_irqsave(&dev->event_lock, flags);
10840         work = intel_crtc->unpin_work;
10841
10842         /* Ensure we don't miss a work->pending update ... */
10843         smp_rmb();
10844
10845         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10846                 spin_unlock_irqrestore(&dev->event_lock, flags);
10847                 return;
10848         }
10849
10850         page_flip_completed(intel_crtc);
10851
10852         spin_unlock_irqrestore(&dev->event_lock, flags);
10853 }
10854
10855 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10856 {
10857         struct drm_i915_private *dev_priv = dev->dev_private;
10858         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10859
10860         do_intel_finish_page_flip(dev, crtc);
10861 }
10862
10863 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10864 {
10865         struct drm_i915_private *dev_priv = dev->dev_private;
10866         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10867
10868         do_intel_finish_page_flip(dev, crtc);
10869 }
10870
10871 /* Is 'a' after or equal to 'b'? */
10872 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10873 {
10874         return !((a - b) & 0x80000000);
10875 }
10876
10877 static bool page_flip_finished(struct intel_crtc *crtc)
10878 {
10879         struct drm_device *dev = crtc->base.dev;
10880         struct drm_i915_private *dev_priv = dev->dev_private;
10881
10882         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10883             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10884                 return true;
10885
10886         /*
10887          * The relevant registers doen't exist on pre-ctg.
10888          * As the flip done interrupt doesn't trigger for mmio
10889          * flips on gmch platforms, a flip count check isn't
10890          * really needed there. But since ctg has the registers,
10891          * include it in the check anyway.
10892          */
10893         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10894                 return true;
10895
10896         /*
10897          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10898          * used the same base address. In that case the mmio flip might
10899          * have completed, but the CS hasn't even executed the flip yet.
10900          *
10901          * A flip count check isn't enough as the CS might have updated
10902          * the base address just after start of vblank, but before we
10903          * managed to process the interrupt. This means we'd complete the
10904          * CS flip too soon.
10905          *
10906          * Combining both checks should get us a good enough result. It may
10907          * still happen that the CS flip has been executed, but has not
10908          * yet actually completed. But in case the base address is the same
10909          * anyway, we don't really care.
10910          */
10911         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10912                 crtc->unpin_work->gtt_offset &&
10913                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10914                                     crtc->unpin_work->flip_count);
10915 }
10916
10917 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10918 {
10919         struct drm_i915_private *dev_priv = dev->dev_private;
10920         struct intel_crtc *intel_crtc =
10921                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10922         unsigned long flags;
10923
10924
10925         /*
10926          * This is called both by irq handlers and the reset code (to complete
10927          * lost pageflips) so needs the full irqsave spinlocks.
10928          *
10929          * NB: An MMIO update of the plane base pointer will also
10930          * generate a page-flip completion irq, i.e. every modeset
10931          * is also accompanied by a spurious intel_prepare_page_flip().
10932          */
10933         spin_lock_irqsave(&dev->event_lock, flags);
10934         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10935                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10936         spin_unlock_irqrestore(&dev->event_lock, flags);
10937 }
10938
10939 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10940 {
10941         /* Ensure that the work item is consistent when activating it ... */
10942         smp_wmb();
10943         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10944         /* and that it is marked active as soon as the irq could fire. */
10945         smp_wmb();
10946 }
10947
10948 static int intel_gen2_queue_flip(struct drm_device *dev,
10949                                  struct drm_crtc *crtc,
10950                                  struct drm_framebuffer *fb,
10951                                  struct drm_i915_gem_object *obj,
10952                                  struct drm_i915_gem_request *req,
10953                                  uint32_t flags)
10954 {
10955         struct intel_engine_cs *ring = req->ring;
10956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10957         u32 flip_mask;
10958         int ret;
10959
10960         ret = intel_ring_begin(req, 6);
10961         if (ret)
10962                 return ret;
10963
10964         /* Can't queue multiple flips, so wait for the previous
10965          * one to finish before executing the next.
10966          */
10967         if (intel_crtc->plane)
10968                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10969         else
10970                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10971         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10972         intel_ring_emit(ring, MI_NOOP);
10973         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10974                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10975         intel_ring_emit(ring, fb->pitches[0]);
10976         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10977         intel_ring_emit(ring, 0); /* aux display base address, unused */
10978
10979         intel_mark_page_flip_active(intel_crtc->unpin_work);
10980         return 0;
10981 }
10982
10983 static int intel_gen3_queue_flip(struct drm_device *dev,
10984                                  struct drm_crtc *crtc,
10985                                  struct drm_framebuffer *fb,
10986                                  struct drm_i915_gem_object *obj,
10987                                  struct drm_i915_gem_request *req,
10988                                  uint32_t flags)
10989 {
10990         struct intel_engine_cs *ring = req->ring;
10991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10992         u32 flip_mask;
10993         int ret;
10994
10995         ret = intel_ring_begin(req, 6);
10996         if (ret)
10997                 return ret;
10998
10999         if (intel_crtc->plane)
11000                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11001         else
11002                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11003         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11004         intel_ring_emit(ring, MI_NOOP);
11005         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11006                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11007         intel_ring_emit(ring, fb->pitches[0]);
11008         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11009         intel_ring_emit(ring, MI_NOOP);
11010
11011         intel_mark_page_flip_active(intel_crtc->unpin_work);
11012         return 0;
11013 }
11014
11015 static int intel_gen4_queue_flip(struct drm_device *dev,
11016                                  struct drm_crtc *crtc,
11017                                  struct drm_framebuffer *fb,
11018                                  struct drm_i915_gem_object *obj,
11019                                  struct drm_i915_gem_request *req,
11020                                  uint32_t flags)
11021 {
11022         struct intel_engine_cs *ring = req->ring;
11023         struct drm_i915_private *dev_priv = dev->dev_private;
11024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11025         uint32_t pf, pipesrc;
11026         int ret;
11027
11028         ret = intel_ring_begin(req, 4);
11029         if (ret)
11030                 return ret;
11031
11032         /* i965+ uses the linear or tiled offsets from the
11033          * Display Registers (which do not change across a page-flip)
11034          * so we need only reprogram the base address.
11035          */
11036         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11037                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11038         intel_ring_emit(ring, fb->pitches[0]);
11039         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11040                         obj->tiling_mode);
11041
11042         /* XXX Enabling the panel-fitter across page-flip is so far
11043          * untested on non-native modes, so ignore it for now.
11044          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11045          */
11046         pf = 0;
11047         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11048         intel_ring_emit(ring, pf | pipesrc);
11049
11050         intel_mark_page_flip_active(intel_crtc->unpin_work);
11051         return 0;
11052 }
11053
11054 static int intel_gen6_queue_flip(struct drm_device *dev,
11055                                  struct drm_crtc *crtc,
11056                                  struct drm_framebuffer *fb,
11057                                  struct drm_i915_gem_object *obj,
11058                                  struct drm_i915_gem_request *req,
11059                                  uint32_t flags)
11060 {
11061         struct intel_engine_cs *ring = req->ring;
11062         struct drm_i915_private *dev_priv = dev->dev_private;
11063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11064         uint32_t pf, pipesrc;
11065         int ret;
11066
11067         ret = intel_ring_begin(req, 4);
11068         if (ret)
11069                 return ret;
11070
11071         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11072                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11073         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11074         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11075
11076         /* Contrary to the suggestions in the documentation,
11077          * "Enable Panel Fitter" does not seem to be required when page
11078          * flipping with a non-native mode, and worse causes a normal
11079          * modeset to fail.
11080          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11081          */
11082         pf = 0;
11083         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11084         intel_ring_emit(ring, pf | pipesrc);
11085
11086         intel_mark_page_flip_active(intel_crtc->unpin_work);
11087         return 0;
11088 }
11089
11090 static int intel_gen7_queue_flip(struct drm_device *dev,
11091                                  struct drm_crtc *crtc,
11092                                  struct drm_framebuffer *fb,
11093                                  struct drm_i915_gem_object *obj,
11094                                  struct drm_i915_gem_request *req,
11095                                  uint32_t flags)
11096 {
11097         struct intel_engine_cs *ring = req->ring;
11098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11099         uint32_t plane_bit = 0;
11100         int len, ret;
11101
11102         switch (intel_crtc->plane) {
11103         case PLANE_A:
11104                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11105                 break;
11106         case PLANE_B:
11107                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11108                 break;
11109         case PLANE_C:
11110                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11111                 break;
11112         default:
11113                 WARN_ONCE(1, "unknown plane in flip command\n");
11114                 return -ENODEV;
11115         }
11116
11117         len = 4;
11118         if (ring->id == RCS) {
11119                 len += 6;
11120                 /*
11121                  * On Gen 8, SRM is now taking an extra dword to accommodate
11122                  * 48bits addresses, and we need a NOOP for the batch size to
11123                  * stay even.
11124                  */
11125                 if (IS_GEN8(dev))
11126                         len += 2;
11127         }
11128
11129         /*
11130          * BSpec MI_DISPLAY_FLIP for IVB:
11131          * "The full packet must be contained within the same cache line."
11132          *
11133          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11134          * cacheline, if we ever start emitting more commands before
11135          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11136          * then do the cacheline alignment, and finally emit the
11137          * MI_DISPLAY_FLIP.
11138          */
11139         ret = intel_ring_cacheline_align(req);
11140         if (ret)
11141                 return ret;
11142
11143         ret = intel_ring_begin(req, len);
11144         if (ret)
11145                 return ret;
11146
11147         /* Unmask the flip-done completion message. Note that the bspec says that
11148          * we should do this for both the BCS and RCS, and that we must not unmask
11149          * more than one flip event at any time (or ensure that one flip message
11150          * can be sent by waiting for flip-done prior to queueing new flips).
11151          * Experimentation says that BCS works despite DERRMR masking all
11152          * flip-done completion events and that unmasking all planes at once
11153          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11154          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11155          */
11156         if (ring->id == RCS) {
11157                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11158                 intel_ring_emit_reg(ring, DERRMR);
11159                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11160                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11161                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11162                 if (IS_GEN8(dev))
11163                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11164                                               MI_SRM_LRM_GLOBAL_GTT);
11165                 else
11166                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11167                                               MI_SRM_LRM_GLOBAL_GTT);
11168                 intel_ring_emit_reg(ring, DERRMR);
11169                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11170                 if (IS_GEN8(dev)) {
11171                         intel_ring_emit(ring, 0);
11172                         intel_ring_emit(ring, MI_NOOP);
11173                 }
11174         }
11175
11176         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11177         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11178         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11179         intel_ring_emit(ring, (MI_NOOP));
11180
11181         intel_mark_page_flip_active(intel_crtc->unpin_work);
11182         return 0;
11183 }
11184
11185 static bool use_mmio_flip(struct intel_engine_cs *ring,
11186                           struct drm_i915_gem_object *obj)
11187 {
11188         /*
11189          * This is not being used for older platforms, because
11190          * non-availability of flip done interrupt forces us to use
11191          * CS flips. Older platforms derive flip done using some clever
11192          * tricks involving the flip_pending status bits and vblank irqs.
11193          * So using MMIO flips there would disrupt this mechanism.
11194          */
11195
11196         if (ring == NULL)
11197                 return true;
11198
11199         if (INTEL_INFO(ring->dev)->gen < 5)
11200                 return false;
11201
11202         if (i915.use_mmio_flip < 0)
11203                 return false;
11204         else if (i915.use_mmio_flip > 0)
11205                 return true;
11206         else if (i915.enable_execlists)
11207                 return true;
11208         else
11209                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11210 }
11211
11212 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11213                              unsigned int rotation,
11214                              struct intel_unpin_work *work)
11215 {
11216         struct drm_device *dev = intel_crtc->base.dev;
11217         struct drm_i915_private *dev_priv = dev->dev_private;
11218         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11219         const enum pipe pipe = intel_crtc->pipe;
11220         u32 ctl, stride, tile_height;
11221
11222         ctl = I915_READ(PLANE_CTL(pipe, 0));
11223         ctl &= ~PLANE_CTL_TILED_MASK;
11224         switch (fb->modifier[0]) {
11225         case DRM_FORMAT_MOD_NONE:
11226                 break;
11227         case I915_FORMAT_MOD_X_TILED:
11228                 ctl |= PLANE_CTL_TILED_X;
11229                 break;
11230         case I915_FORMAT_MOD_Y_TILED:
11231                 ctl |= PLANE_CTL_TILED_Y;
11232                 break;
11233         case I915_FORMAT_MOD_Yf_TILED:
11234                 ctl |= PLANE_CTL_TILED_YF;
11235                 break;
11236         default:
11237                 MISSING_CASE(fb->modifier[0]);
11238         }
11239
11240         /*
11241          * The stride is either expressed as a multiple of 64 bytes chunks for
11242          * linear buffers or in number of tiles for tiled buffers.
11243          */
11244         if (intel_rotation_90_or_270(rotation)) {
11245                 /* stride = Surface height in tiles */
11246                 tile_height = intel_tile_height(dev, fb->pixel_format,
11247                                                 fb->modifier[0], 0);
11248                 stride = DIV_ROUND_UP(fb->height, tile_height);
11249         } else {
11250                 stride = fb->pitches[0] /
11251                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11252                                                           fb->pixel_format);
11253         }
11254
11255         /*
11256          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11257          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11258          */
11259         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11260         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11261
11262         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11263         POSTING_READ(PLANE_SURF(pipe, 0));
11264 }
11265
11266 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11267                              struct intel_unpin_work *work)
11268 {
11269         struct drm_device *dev = intel_crtc->base.dev;
11270         struct drm_i915_private *dev_priv = dev->dev_private;
11271         struct intel_framebuffer *intel_fb =
11272                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11273         struct drm_i915_gem_object *obj = intel_fb->obj;
11274         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11275         u32 dspcntr;
11276
11277         dspcntr = I915_READ(reg);
11278
11279         if (obj->tiling_mode != I915_TILING_NONE)
11280                 dspcntr |= DISPPLANE_TILED;
11281         else
11282                 dspcntr &= ~DISPPLANE_TILED;
11283
11284         I915_WRITE(reg, dspcntr);
11285
11286         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11287         POSTING_READ(DSPSURF(intel_crtc->plane));
11288 }
11289
11290 /*
11291  * XXX: This is the temporary way to update the plane registers until we get
11292  * around to using the usual plane update functions for MMIO flips
11293  */
11294 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11295 {
11296         struct intel_crtc *crtc = mmio_flip->crtc;
11297         struct intel_unpin_work *work;
11298
11299         spin_lock_irq(&crtc->base.dev->event_lock);
11300         work = crtc->unpin_work;
11301         spin_unlock_irq(&crtc->base.dev->event_lock);
11302         if (work == NULL)
11303                 return;
11304
11305         intel_mark_page_flip_active(work);
11306
11307         intel_pipe_update_start(crtc);
11308
11309         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11310                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11311         else
11312                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11313                 ilk_do_mmio_flip(crtc, work);
11314
11315         intel_pipe_update_end(crtc);
11316 }
11317
11318 static void intel_mmio_flip_work_func(struct work_struct *work)
11319 {
11320         struct intel_mmio_flip *mmio_flip =
11321                 container_of(work, struct intel_mmio_flip, work);
11322
11323         if (mmio_flip->req) {
11324                 WARN_ON(__i915_wait_request(mmio_flip->req,
11325                                             mmio_flip->crtc->reset_counter,
11326                                             false, NULL,
11327                                             &mmio_flip->i915->rps.mmioflips));
11328                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11329         }
11330
11331         intel_do_mmio_flip(mmio_flip);
11332         kfree(mmio_flip);
11333 }
11334
11335 static int intel_queue_mmio_flip(struct drm_device *dev,
11336                                  struct drm_crtc *crtc,
11337                                  struct drm_i915_gem_object *obj)
11338 {
11339         struct intel_mmio_flip *mmio_flip;
11340
11341         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11342         if (mmio_flip == NULL)
11343                 return -ENOMEM;
11344
11345         mmio_flip->i915 = to_i915(dev);
11346         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11347         mmio_flip->crtc = to_intel_crtc(crtc);
11348         mmio_flip->rotation = crtc->primary->state->rotation;
11349
11350         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11351         schedule_work(&mmio_flip->work);
11352
11353         return 0;
11354 }
11355
11356 static int intel_default_queue_flip(struct drm_device *dev,
11357                                     struct drm_crtc *crtc,
11358                                     struct drm_framebuffer *fb,
11359                                     struct drm_i915_gem_object *obj,
11360                                     struct drm_i915_gem_request *req,
11361                                     uint32_t flags)
11362 {
11363         return -ENODEV;
11364 }
11365
11366 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11367                                          struct drm_crtc *crtc)
11368 {
11369         struct drm_i915_private *dev_priv = dev->dev_private;
11370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11371         struct intel_unpin_work *work = intel_crtc->unpin_work;
11372         u32 addr;
11373
11374         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11375                 return true;
11376
11377         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11378                 return false;
11379
11380         if (!work->enable_stall_check)
11381                 return false;
11382
11383         if (work->flip_ready_vblank == 0) {
11384                 if (work->flip_queued_req &&
11385                     !i915_gem_request_completed(work->flip_queued_req, true))
11386                         return false;
11387
11388                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11389         }
11390
11391         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11392                 return false;
11393
11394         /* Potential stall - if we see that the flip has happened,
11395          * assume a missed interrupt. */
11396         if (INTEL_INFO(dev)->gen >= 4)
11397                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11398         else
11399                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11400
11401         /* There is a potential issue here with a false positive after a flip
11402          * to the same address. We could address this by checking for a
11403          * non-incrementing frame counter.
11404          */
11405         return addr == work->gtt_offset;
11406 }
11407
11408 void intel_check_page_flip(struct drm_device *dev, int pipe)
11409 {
11410         struct drm_i915_private *dev_priv = dev->dev_private;
11411         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11413         struct intel_unpin_work *work;
11414
11415         WARN_ON(!in_interrupt());
11416
11417         if (crtc == NULL)
11418                 return;
11419
11420         spin_lock(&dev->event_lock);
11421         work = intel_crtc->unpin_work;
11422         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11423                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11424                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11425                 page_flip_completed(intel_crtc);
11426                 work = NULL;
11427         }
11428         if (work != NULL &&
11429             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11430                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11431         spin_unlock(&dev->event_lock);
11432 }
11433
11434 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11435                                 struct drm_framebuffer *fb,
11436                                 struct drm_pending_vblank_event *event,
11437                                 uint32_t page_flip_flags)
11438 {
11439         struct drm_device *dev = crtc->dev;
11440         struct drm_i915_private *dev_priv = dev->dev_private;
11441         struct drm_framebuffer *old_fb = crtc->primary->fb;
11442         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11444         struct drm_plane *primary = crtc->primary;
11445         enum pipe pipe = intel_crtc->pipe;
11446         struct intel_unpin_work *work;
11447         struct intel_engine_cs *ring;
11448         bool mmio_flip;
11449         struct drm_i915_gem_request *request = NULL;
11450         int ret;
11451
11452         /*
11453          * drm_mode_page_flip_ioctl() should already catch this, but double
11454          * check to be safe.  In the future we may enable pageflipping from
11455          * a disabled primary plane.
11456          */
11457         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11458                 return -EBUSY;
11459
11460         /* Can't change pixel format via MI display flips. */
11461         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11462                 return -EINVAL;
11463
11464         /*
11465          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11466          * Note that pitch changes could also affect these register.
11467          */
11468         if (INTEL_INFO(dev)->gen > 3 &&
11469             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11470              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11471                 return -EINVAL;
11472
11473         if (i915_terminally_wedged(&dev_priv->gpu_error))
11474                 goto out_hang;
11475
11476         work = kzalloc(sizeof(*work), GFP_KERNEL);
11477         if (work == NULL)
11478                 return -ENOMEM;
11479
11480         work->event = event;
11481         work->crtc = crtc;
11482         work->old_fb = old_fb;
11483         INIT_WORK(&work->work, intel_unpin_work_fn);
11484
11485         ret = drm_crtc_vblank_get(crtc);
11486         if (ret)
11487                 goto free_work;
11488
11489         /* We borrow the event spin lock for protecting unpin_work */
11490         spin_lock_irq(&dev->event_lock);
11491         if (intel_crtc->unpin_work) {
11492                 /* Before declaring the flip queue wedged, check if
11493                  * the hardware completed the operation behind our backs.
11494                  */
11495                 if (__intel_pageflip_stall_check(dev, crtc)) {
11496                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11497                         page_flip_completed(intel_crtc);
11498                 } else {
11499                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11500                         spin_unlock_irq(&dev->event_lock);
11501
11502                         drm_crtc_vblank_put(crtc);
11503                         kfree(work);
11504                         return -EBUSY;
11505                 }
11506         }
11507         intel_crtc->unpin_work = work;
11508         spin_unlock_irq(&dev->event_lock);
11509
11510         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11511                 flush_workqueue(dev_priv->wq);
11512
11513         /* Reference the objects for the scheduled work. */
11514         drm_framebuffer_reference(work->old_fb);
11515         drm_gem_object_reference(&obj->base);
11516
11517         crtc->primary->fb = fb;
11518         update_state_fb(crtc->primary);
11519
11520         work->pending_flip_obj = obj;
11521
11522         ret = i915_mutex_lock_interruptible(dev);
11523         if (ret)
11524                 goto cleanup;
11525
11526         atomic_inc(&intel_crtc->unpin_work_count);
11527         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11528
11529         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11530                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11531
11532         if (IS_VALLEYVIEW(dev)) {
11533                 ring = &dev_priv->ring[BCS];
11534                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11535                         /* vlv: DISPLAY_FLIP fails to change tiling */
11536                         ring = NULL;
11537         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11538                 ring = &dev_priv->ring[BCS];
11539         } else if (INTEL_INFO(dev)->gen >= 7) {
11540                 ring = i915_gem_request_get_ring(obj->last_write_req);
11541                 if (ring == NULL || ring->id != RCS)
11542                         ring = &dev_priv->ring[BCS];
11543         } else {
11544                 ring = &dev_priv->ring[RCS];
11545         }
11546
11547         mmio_flip = use_mmio_flip(ring, obj);
11548
11549         /* When using CS flips, we want to emit semaphores between rings.
11550          * However, when using mmio flips we will create a task to do the
11551          * synchronisation, so all we want here is to pin the framebuffer
11552          * into the display plane and skip any waits.
11553          */
11554         if (!mmio_flip) {
11555                 ret = i915_gem_object_sync(obj, ring, &request);
11556                 if (ret)
11557                         goto cleanup_pending;
11558         }
11559
11560         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11561                                          crtc->primary->state);
11562         if (ret)
11563                 goto cleanup_pending;
11564
11565         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11566                                                   obj, 0);
11567         work->gtt_offset += intel_crtc->dspaddr_offset;
11568
11569         if (mmio_flip) {
11570                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11571                 if (ret)
11572                         goto cleanup_unpin;
11573
11574                 i915_gem_request_assign(&work->flip_queued_req,
11575                                         obj->last_write_req);
11576         } else {
11577                 if (!request) {
11578                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11579                         if (ret)
11580                                 goto cleanup_unpin;
11581                 }
11582
11583                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11584                                                    page_flip_flags);
11585                 if (ret)
11586                         goto cleanup_unpin;
11587
11588                 i915_gem_request_assign(&work->flip_queued_req, request);
11589         }
11590
11591         if (request)
11592                 i915_add_request_no_flush(request);
11593
11594         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11595         work->enable_stall_check = true;
11596
11597         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11598                           to_intel_plane(primary)->frontbuffer_bit);
11599         mutex_unlock(&dev->struct_mutex);
11600
11601         intel_fbc_disable_crtc(intel_crtc);
11602         intel_frontbuffer_flip_prepare(dev,
11603                                        to_intel_plane(primary)->frontbuffer_bit);
11604
11605         trace_i915_flip_request(intel_crtc->plane, obj);
11606
11607         return 0;
11608
11609 cleanup_unpin:
11610         intel_unpin_fb_obj(fb, crtc->primary->state);
11611 cleanup_pending:
11612         if (request)
11613                 i915_gem_request_cancel(request);
11614         atomic_dec(&intel_crtc->unpin_work_count);
11615         mutex_unlock(&dev->struct_mutex);
11616 cleanup:
11617         crtc->primary->fb = old_fb;
11618         update_state_fb(crtc->primary);
11619
11620         drm_gem_object_unreference_unlocked(&obj->base);
11621         drm_framebuffer_unreference(work->old_fb);
11622
11623         spin_lock_irq(&dev->event_lock);
11624         intel_crtc->unpin_work = NULL;
11625         spin_unlock_irq(&dev->event_lock);
11626
11627         drm_crtc_vblank_put(crtc);
11628 free_work:
11629         kfree(work);
11630
11631         if (ret == -EIO) {
11632                 struct drm_atomic_state *state;
11633                 struct drm_plane_state *plane_state;
11634
11635 out_hang:
11636                 state = drm_atomic_state_alloc(dev);
11637                 if (!state)
11638                         return -ENOMEM;
11639                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11640
11641 retry:
11642                 plane_state = drm_atomic_get_plane_state(state, primary);
11643                 ret = PTR_ERR_OR_ZERO(plane_state);
11644                 if (!ret) {
11645                         drm_atomic_set_fb_for_plane(plane_state, fb);
11646
11647                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11648                         if (!ret)
11649                                 ret = drm_atomic_commit(state);
11650                 }
11651
11652                 if (ret == -EDEADLK) {
11653                         drm_modeset_backoff(state->acquire_ctx);
11654                         drm_atomic_state_clear(state);
11655                         goto retry;
11656                 }
11657
11658                 if (ret)
11659                         drm_atomic_state_free(state);
11660
11661                 if (ret == 0 && event) {
11662                         spin_lock_irq(&dev->event_lock);
11663                         drm_send_vblank_event(dev, pipe, event);
11664                         spin_unlock_irq(&dev->event_lock);
11665                 }
11666         }
11667         return ret;
11668 }
11669
11670
11671 /**
11672  * intel_wm_need_update - Check whether watermarks need updating
11673  * @plane: drm plane
11674  * @state: new plane state
11675  *
11676  * Check current plane state versus the new one to determine whether
11677  * watermarks need to be recalculated.
11678  *
11679  * Returns true or false.
11680  */
11681 static bool intel_wm_need_update(struct drm_plane *plane,
11682                                  struct drm_plane_state *state)
11683 {
11684         struct intel_plane_state *new = to_intel_plane_state(state);
11685         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11686
11687         /* Update watermarks on tiling or size changes. */
11688         if (!plane->state->fb || !state->fb ||
11689             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11690             plane->state->rotation != state->rotation ||
11691             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11692             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11693             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11694             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11695                 return true;
11696
11697         return false;
11698 }
11699
11700 static bool needs_scaling(struct intel_plane_state *state)
11701 {
11702         int src_w = drm_rect_width(&state->src) >> 16;
11703         int src_h = drm_rect_height(&state->src) >> 16;
11704         int dst_w = drm_rect_width(&state->dst);
11705         int dst_h = drm_rect_height(&state->dst);
11706
11707         return (src_w != dst_w || src_h != dst_h);
11708 }
11709
11710 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11711                                     struct drm_plane_state *plane_state)
11712 {
11713         struct drm_crtc *crtc = crtc_state->crtc;
11714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11715         struct drm_plane *plane = plane_state->plane;
11716         struct drm_device *dev = crtc->dev;
11717         struct drm_i915_private *dev_priv = dev->dev_private;
11718         struct intel_plane_state *old_plane_state =
11719                 to_intel_plane_state(plane->state);
11720         int idx = intel_crtc->base.base.id, ret;
11721         int i = drm_plane_index(plane);
11722         bool mode_changed = needs_modeset(crtc_state);
11723         bool was_crtc_enabled = crtc->state->active;
11724         bool is_crtc_enabled = crtc_state->active;
11725         bool turn_off, turn_on, visible, was_visible;
11726         struct drm_framebuffer *fb = plane_state->fb;
11727
11728         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11729             plane->type != DRM_PLANE_TYPE_CURSOR) {
11730                 ret = skl_update_scaler_plane(
11731                         to_intel_crtc_state(crtc_state),
11732                         to_intel_plane_state(plane_state));
11733                 if (ret)
11734                         return ret;
11735         }
11736
11737         was_visible = old_plane_state->visible;
11738         visible = to_intel_plane_state(plane_state)->visible;
11739
11740         if (!was_crtc_enabled && WARN_ON(was_visible))
11741                 was_visible = false;
11742
11743         if (!is_crtc_enabled && WARN_ON(visible))
11744                 visible = false;
11745
11746         if (!was_visible && !visible)
11747                 return 0;
11748
11749         turn_off = was_visible && (!visible || mode_changed);
11750         turn_on = visible && (!was_visible || mode_changed);
11751
11752         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11753                          plane->base.id, fb ? fb->base.id : -1);
11754
11755         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11756                          plane->base.id, was_visible, visible,
11757                          turn_off, turn_on, mode_changed);
11758
11759         if (turn_on) {
11760                 intel_crtc->atomic.update_wm_pre = true;
11761                 /* must disable cxsr around plane enable/disable */
11762                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11763                         intel_crtc->atomic.disable_cxsr = true;
11764                         /* to potentially re-enable cxsr */
11765                         intel_crtc->atomic.wait_vblank = true;
11766                         intel_crtc->atomic.update_wm_post = true;
11767                 }
11768         } else if (turn_off) {
11769                 intel_crtc->atomic.update_wm_post = true;
11770                 /* must disable cxsr around plane enable/disable */
11771                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11772                         if (is_crtc_enabled)
11773                                 intel_crtc->atomic.wait_vblank = true;
11774                         intel_crtc->atomic.disable_cxsr = true;
11775                 }
11776         } else if (intel_wm_need_update(plane, plane_state)) {
11777                 intel_crtc->atomic.update_wm_pre = true;
11778         }
11779
11780         if (visible || was_visible)
11781                 intel_crtc->atomic.fb_bits |=
11782                         to_intel_plane(plane)->frontbuffer_bit;
11783
11784         switch (plane->type) {
11785         case DRM_PLANE_TYPE_PRIMARY:
11786                 intel_crtc->atomic.pre_disable_primary = turn_off;
11787                 intel_crtc->atomic.post_enable_primary = turn_on;
11788
11789                 if (turn_off) {
11790                         /*
11791                          * FIXME: Actually if we will still have any other
11792                          * plane enabled on the pipe we could let IPS enabled
11793                          * still, but for now lets consider that when we make
11794                          * primary invisible by setting DSPCNTR to 0 on
11795                          * update_primary_plane function IPS needs to be
11796                          * disable.
11797                          */
11798                         intel_crtc->atomic.disable_ips = true;
11799
11800                         intel_crtc->atomic.disable_fbc = true;
11801                 }
11802
11803                 /*
11804                  * FBC does not work on some platforms for rotated
11805                  * planes, so disable it when rotation is not 0 and
11806                  * update it when rotation is set back to 0.
11807                  *
11808                  * FIXME: This is redundant with the fbc update done in
11809                  * the primary plane enable function except that that
11810                  * one is done too late. We eventually need to unify
11811                  * this.
11812                  */
11813
11814                 if (visible &&
11815                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11816                     dev_priv->fbc.crtc == intel_crtc &&
11817                     plane_state->rotation != BIT(DRM_ROTATE_0))
11818                         intel_crtc->atomic.disable_fbc = true;
11819
11820                 /*
11821                  * BDW signals flip done immediately if the plane
11822                  * is disabled, even if the plane enable is already
11823                  * armed to occur at the next vblank :(
11824                  */
11825                 if (turn_on && IS_BROADWELL(dev))
11826                         intel_crtc->atomic.wait_vblank = true;
11827
11828                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11829                 break;
11830         case DRM_PLANE_TYPE_CURSOR:
11831                 break;
11832         case DRM_PLANE_TYPE_OVERLAY:
11833                 /*
11834                  * WaCxSRDisabledForSpriteScaling:ivb
11835                  *
11836                  * cstate->update_wm was already set above, so this flag will
11837                  * take effect when we commit and program watermarks.
11838                  */
11839                 if (IS_IVYBRIDGE(dev) &&
11840                     needs_scaling(to_intel_plane_state(plane_state)) &&
11841                     !needs_scaling(old_plane_state)) {
11842                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11843                 } else if (turn_off && !mode_changed) {
11844                         intel_crtc->atomic.wait_vblank = true;
11845                         intel_crtc->atomic.update_sprite_watermarks |=
11846                                 1 << i;
11847                 }
11848
11849                 break;
11850         }
11851         return 0;
11852 }
11853
11854 static bool encoders_cloneable(const struct intel_encoder *a,
11855                                const struct intel_encoder *b)
11856 {
11857         /* masks could be asymmetric, so check both ways */
11858         return a == b || (a->cloneable & (1 << b->type) &&
11859                           b->cloneable & (1 << a->type));
11860 }
11861
11862 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11863                                          struct intel_crtc *crtc,
11864                                          struct intel_encoder *encoder)
11865 {
11866         struct intel_encoder *source_encoder;
11867         struct drm_connector *connector;
11868         struct drm_connector_state *connector_state;
11869         int i;
11870
11871         for_each_connector_in_state(state, connector, connector_state, i) {
11872                 if (connector_state->crtc != &crtc->base)
11873                         continue;
11874
11875                 source_encoder =
11876                         to_intel_encoder(connector_state->best_encoder);
11877                 if (!encoders_cloneable(encoder, source_encoder))
11878                         return false;
11879         }
11880
11881         return true;
11882 }
11883
11884 static bool check_encoder_cloning(struct drm_atomic_state *state,
11885                                   struct intel_crtc *crtc)
11886 {
11887         struct intel_encoder *encoder;
11888         struct drm_connector *connector;
11889         struct drm_connector_state *connector_state;
11890         int i;
11891
11892         for_each_connector_in_state(state, connector, connector_state, i) {
11893                 if (connector_state->crtc != &crtc->base)
11894                         continue;
11895
11896                 encoder = to_intel_encoder(connector_state->best_encoder);
11897                 if (!check_single_encoder_cloning(state, crtc, encoder))
11898                         return false;
11899         }
11900
11901         return true;
11902 }
11903
11904 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11905                                    struct drm_crtc_state *crtc_state)
11906 {
11907         struct drm_device *dev = crtc->dev;
11908         struct drm_i915_private *dev_priv = dev->dev_private;
11909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11910         struct intel_crtc_state *pipe_config =
11911                 to_intel_crtc_state(crtc_state);
11912         struct drm_atomic_state *state = crtc_state->state;
11913         int ret;
11914         bool mode_changed = needs_modeset(crtc_state);
11915
11916         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11917                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11918                 return -EINVAL;
11919         }
11920
11921         if (mode_changed && !crtc_state->active)
11922                 intel_crtc->atomic.update_wm_post = true;
11923
11924         if (mode_changed && crtc_state->enable &&
11925             dev_priv->display.crtc_compute_clock &&
11926             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11927                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11928                                                            pipe_config);
11929                 if (ret)
11930                         return ret;
11931         }
11932
11933         ret = 0;
11934         if (dev_priv->display.compute_pipe_wm) {
11935                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11936                 if (ret)
11937                         return ret;
11938         }
11939
11940         if (INTEL_INFO(dev)->gen >= 9) {
11941                 if (mode_changed)
11942                         ret = skl_update_scaler_crtc(pipe_config);
11943
11944                 if (!ret)
11945                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11946                                                          pipe_config);
11947         }
11948
11949         return ret;
11950 }
11951
11952 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11953         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11954         .load_lut = intel_crtc_load_lut,
11955         .atomic_begin = intel_begin_crtc_commit,
11956         .atomic_flush = intel_finish_crtc_commit,
11957         .atomic_check = intel_crtc_atomic_check,
11958 };
11959
11960 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11961 {
11962         struct intel_connector *connector;
11963
11964         for_each_intel_connector(dev, connector) {
11965                 if (connector->base.encoder) {
11966                         connector->base.state->best_encoder =
11967                                 connector->base.encoder;
11968                         connector->base.state->crtc =
11969                                 connector->base.encoder->crtc;
11970                 } else {
11971                         connector->base.state->best_encoder = NULL;
11972                         connector->base.state->crtc = NULL;
11973                 }
11974         }
11975 }
11976
11977 static void
11978 connected_sink_compute_bpp(struct intel_connector *connector,
11979                            struct intel_crtc_state *pipe_config)
11980 {
11981         int bpp = pipe_config->pipe_bpp;
11982
11983         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11984                 connector->base.base.id,
11985                 connector->base.name);
11986
11987         /* Don't use an invalid EDID bpc value */
11988         if (connector->base.display_info.bpc &&
11989             connector->base.display_info.bpc * 3 < bpp) {
11990                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11991                               bpp, connector->base.display_info.bpc*3);
11992                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11993         }
11994
11995         /* Clamp bpp to 8 on screens without EDID 1.4 */
11996         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11997                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11998                               bpp);
11999                 pipe_config->pipe_bpp = 24;
12000         }
12001 }
12002
12003 static int
12004 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12005                           struct intel_crtc_state *pipe_config)
12006 {
12007         struct drm_device *dev = crtc->base.dev;
12008         struct drm_atomic_state *state;
12009         struct drm_connector *connector;
12010         struct drm_connector_state *connector_state;
12011         int bpp, i;
12012
12013         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12014                 bpp = 10*3;
12015         else if (INTEL_INFO(dev)->gen >= 5)
12016                 bpp = 12*3;
12017         else
12018                 bpp = 8*3;
12019
12020
12021         pipe_config->pipe_bpp = bpp;
12022
12023         state = pipe_config->base.state;
12024
12025         /* Clamp display bpp to EDID value */
12026         for_each_connector_in_state(state, connector, connector_state, i) {
12027                 if (connector_state->crtc != &crtc->base)
12028                         continue;
12029
12030                 connected_sink_compute_bpp(to_intel_connector(connector),
12031                                            pipe_config);
12032         }
12033
12034         return bpp;
12035 }
12036
12037 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12038 {
12039         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12040                         "type: 0x%x flags: 0x%x\n",
12041                 mode->crtc_clock,
12042                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12043                 mode->crtc_hsync_end, mode->crtc_htotal,
12044                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12045                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12046 }
12047
12048 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12049                                    struct intel_crtc_state *pipe_config,
12050                                    const char *context)
12051 {
12052         struct drm_device *dev = crtc->base.dev;
12053         struct drm_plane *plane;
12054         struct intel_plane *intel_plane;
12055         struct intel_plane_state *state;
12056         struct drm_framebuffer *fb;
12057
12058         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12059                       context, pipe_config, pipe_name(crtc->pipe));
12060
12061         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12062         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12063                       pipe_config->pipe_bpp, pipe_config->dither);
12064         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12065                       pipe_config->has_pch_encoder,
12066                       pipe_config->fdi_lanes,
12067                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12068                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12069                       pipe_config->fdi_m_n.tu);
12070         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12071                       pipe_config->has_dp_encoder,
12072                       pipe_config->lane_count,
12073                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12074                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12075                       pipe_config->dp_m_n.tu);
12076
12077         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12078                       pipe_config->has_dp_encoder,
12079                       pipe_config->lane_count,
12080                       pipe_config->dp_m2_n2.gmch_m,
12081                       pipe_config->dp_m2_n2.gmch_n,
12082                       pipe_config->dp_m2_n2.link_m,
12083                       pipe_config->dp_m2_n2.link_n,
12084                       pipe_config->dp_m2_n2.tu);
12085
12086         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12087                       pipe_config->has_audio,
12088                       pipe_config->has_infoframe);
12089
12090         DRM_DEBUG_KMS("requested mode:\n");
12091         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12092         DRM_DEBUG_KMS("adjusted mode:\n");
12093         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12094         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12095         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12096         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12097                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12098         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12099                       crtc->num_scalers,
12100                       pipe_config->scaler_state.scaler_users,
12101                       pipe_config->scaler_state.scaler_id);
12102         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12103                       pipe_config->gmch_pfit.control,
12104                       pipe_config->gmch_pfit.pgm_ratios,
12105                       pipe_config->gmch_pfit.lvds_border_bits);
12106         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12107                       pipe_config->pch_pfit.pos,
12108                       pipe_config->pch_pfit.size,
12109                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12110         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12111         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12112
12113         if (IS_BROXTON(dev)) {
12114                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12115                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12116                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12117                               pipe_config->ddi_pll_sel,
12118                               pipe_config->dpll_hw_state.ebb0,
12119                               pipe_config->dpll_hw_state.ebb4,
12120                               pipe_config->dpll_hw_state.pll0,
12121                               pipe_config->dpll_hw_state.pll1,
12122                               pipe_config->dpll_hw_state.pll2,
12123                               pipe_config->dpll_hw_state.pll3,
12124                               pipe_config->dpll_hw_state.pll6,
12125                               pipe_config->dpll_hw_state.pll8,
12126                               pipe_config->dpll_hw_state.pll9,
12127                               pipe_config->dpll_hw_state.pll10,
12128                               pipe_config->dpll_hw_state.pcsdw12);
12129         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12130                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12131                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12132                               pipe_config->ddi_pll_sel,
12133                               pipe_config->dpll_hw_state.ctrl1,
12134                               pipe_config->dpll_hw_state.cfgcr1,
12135                               pipe_config->dpll_hw_state.cfgcr2);
12136         } else if (HAS_DDI(dev)) {
12137                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12138                               pipe_config->ddi_pll_sel,
12139                               pipe_config->dpll_hw_state.wrpll,
12140                               pipe_config->dpll_hw_state.spll);
12141         } else {
12142                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12143                               "fp0: 0x%x, fp1: 0x%x\n",
12144                               pipe_config->dpll_hw_state.dpll,
12145                               pipe_config->dpll_hw_state.dpll_md,
12146                               pipe_config->dpll_hw_state.fp0,
12147                               pipe_config->dpll_hw_state.fp1);
12148         }
12149
12150         DRM_DEBUG_KMS("planes on this crtc\n");
12151         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12152                 intel_plane = to_intel_plane(plane);
12153                 if (intel_plane->pipe != crtc->pipe)
12154                         continue;
12155
12156                 state = to_intel_plane_state(plane->state);
12157                 fb = state->base.fb;
12158                 if (!fb) {
12159                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12160                                 "disabled, scaler_id = %d\n",
12161                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12162                                 plane->base.id, intel_plane->pipe,
12163                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12164                                 drm_plane_index(plane), state->scaler_id);
12165                         continue;
12166                 }
12167
12168                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12169                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12170                         plane->base.id, intel_plane->pipe,
12171                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12172                         drm_plane_index(plane));
12173                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12174                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12175                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12176                         state->scaler_id,
12177                         state->src.x1 >> 16, state->src.y1 >> 16,
12178                         drm_rect_width(&state->src) >> 16,
12179                         drm_rect_height(&state->src) >> 16,
12180                         state->dst.x1, state->dst.y1,
12181                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12182         }
12183 }
12184
12185 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12186 {
12187         struct drm_device *dev = state->dev;
12188         struct intel_encoder *encoder;
12189         struct drm_connector *connector;
12190         struct drm_connector_state *connector_state;
12191         unsigned int used_ports = 0;
12192         int i;
12193
12194         /*
12195          * Walk the connector list instead of the encoder
12196          * list to detect the problem on ddi platforms
12197          * where there's just one encoder per digital port.
12198          */
12199         for_each_connector_in_state(state, connector, connector_state, i) {
12200                 if (!connector_state->best_encoder)
12201                         continue;
12202
12203                 encoder = to_intel_encoder(connector_state->best_encoder);
12204
12205                 WARN_ON(!connector_state->crtc);
12206
12207                 switch (encoder->type) {
12208                         unsigned int port_mask;
12209                 case INTEL_OUTPUT_UNKNOWN:
12210                         if (WARN_ON(!HAS_DDI(dev)))
12211                                 break;
12212                 case INTEL_OUTPUT_DISPLAYPORT:
12213                 case INTEL_OUTPUT_HDMI:
12214                 case INTEL_OUTPUT_EDP:
12215                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12216
12217                         /* the same port mustn't appear more than once */
12218                         if (used_ports & port_mask)
12219                                 return false;
12220
12221                         used_ports |= port_mask;
12222                 default:
12223                         break;
12224                 }
12225         }
12226
12227         return true;
12228 }
12229
12230 static void
12231 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12232 {
12233         struct drm_crtc_state tmp_state;
12234         struct intel_crtc_scaler_state scaler_state;
12235         struct intel_dpll_hw_state dpll_hw_state;
12236         enum intel_dpll_id shared_dpll;
12237         uint32_t ddi_pll_sel;
12238         bool force_thru;
12239
12240         /* FIXME: before the switch to atomic started, a new pipe_config was
12241          * kzalloc'd. Code that depends on any field being zero should be
12242          * fixed, so that the crtc_state can be safely duplicated. For now,
12243          * only fields that are know to not cause problems are preserved. */
12244
12245         tmp_state = crtc_state->base;
12246         scaler_state = crtc_state->scaler_state;
12247         shared_dpll = crtc_state->shared_dpll;
12248         dpll_hw_state = crtc_state->dpll_hw_state;
12249         ddi_pll_sel = crtc_state->ddi_pll_sel;
12250         force_thru = crtc_state->pch_pfit.force_thru;
12251
12252         memset(crtc_state, 0, sizeof *crtc_state);
12253
12254         crtc_state->base = tmp_state;
12255         crtc_state->scaler_state = scaler_state;
12256         crtc_state->shared_dpll = shared_dpll;
12257         crtc_state->dpll_hw_state = dpll_hw_state;
12258         crtc_state->ddi_pll_sel = ddi_pll_sel;
12259         crtc_state->pch_pfit.force_thru = force_thru;
12260 }
12261
12262 static int
12263 intel_modeset_pipe_config(struct drm_crtc *crtc,
12264                           struct intel_crtc_state *pipe_config)
12265 {
12266         struct drm_atomic_state *state = pipe_config->base.state;
12267         struct intel_encoder *encoder;
12268         struct drm_connector *connector;
12269         struct drm_connector_state *connector_state;
12270         int base_bpp, ret = -EINVAL;
12271         int i;
12272         bool retry = true;
12273
12274         clear_intel_crtc_state(pipe_config);
12275
12276         pipe_config->cpu_transcoder =
12277                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12278
12279         /*
12280          * Sanitize sync polarity flags based on requested ones. If neither
12281          * positive or negative polarity is requested, treat this as meaning
12282          * negative polarity.
12283          */
12284         if (!(pipe_config->base.adjusted_mode.flags &
12285               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12286                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12287
12288         if (!(pipe_config->base.adjusted_mode.flags &
12289               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12290                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12291
12292         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12293                                              pipe_config);
12294         if (base_bpp < 0)
12295                 goto fail;
12296
12297         /*
12298          * Determine the real pipe dimensions. Note that stereo modes can
12299          * increase the actual pipe size due to the frame doubling and
12300          * insertion of additional space for blanks between the frame. This
12301          * is stored in the crtc timings. We use the requested mode to do this
12302          * computation to clearly distinguish it from the adjusted mode, which
12303          * can be changed by the connectors in the below retry loop.
12304          */
12305         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12306                                &pipe_config->pipe_src_w,
12307                                &pipe_config->pipe_src_h);
12308
12309 encoder_retry:
12310         /* Ensure the port clock defaults are reset when retrying. */
12311         pipe_config->port_clock = 0;
12312         pipe_config->pixel_multiplier = 1;
12313
12314         /* Fill in default crtc timings, allow encoders to overwrite them. */
12315         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12316                               CRTC_STEREO_DOUBLE);
12317
12318         /* Pass our mode to the connectors and the CRTC to give them a chance to
12319          * adjust it according to limitations or connector properties, and also
12320          * a chance to reject the mode entirely.
12321          */
12322         for_each_connector_in_state(state, connector, connector_state, i) {
12323                 if (connector_state->crtc != crtc)
12324                         continue;
12325
12326                 encoder = to_intel_encoder(connector_state->best_encoder);
12327
12328                 if (!(encoder->compute_config(encoder, pipe_config))) {
12329                         DRM_DEBUG_KMS("Encoder config failure\n");
12330                         goto fail;
12331                 }
12332         }
12333
12334         /* Set default port clock if not overwritten by the encoder. Needs to be
12335          * done afterwards in case the encoder adjusts the mode. */
12336         if (!pipe_config->port_clock)
12337                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12338                         * pipe_config->pixel_multiplier;
12339
12340         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12341         if (ret < 0) {
12342                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12343                 goto fail;
12344         }
12345
12346         if (ret == RETRY) {
12347                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12348                         ret = -EINVAL;
12349                         goto fail;
12350                 }
12351
12352                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12353                 retry = false;
12354                 goto encoder_retry;
12355         }
12356
12357         /* Dithering seems to not pass-through bits correctly when it should, so
12358          * only enable it on 6bpc panels. */
12359         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12360         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12361                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12362
12363 fail:
12364         return ret;
12365 }
12366
12367 static void
12368 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12369 {
12370         struct drm_crtc *crtc;
12371         struct drm_crtc_state *crtc_state;
12372         int i;
12373
12374         /* Double check state. */
12375         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12376                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12377
12378                 /* Update hwmode for vblank functions */
12379                 if (crtc->state->active)
12380                         crtc->hwmode = crtc->state->adjusted_mode;
12381                 else
12382                         crtc->hwmode.crtc_clock = 0;
12383
12384                 /*
12385                  * Update legacy state to satisfy fbc code. This can
12386                  * be removed when fbc uses the atomic state.
12387                  */
12388                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12389                         struct drm_plane_state *plane_state = crtc->primary->state;
12390
12391                         crtc->primary->fb = plane_state->fb;
12392                         crtc->x = plane_state->src_x >> 16;
12393                         crtc->y = plane_state->src_y >> 16;
12394                 }
12395         }
12396 }
12397
12398 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12399 {
12400         int diff;
12401
12402         if (clock1 == clock2)
12403                 return true;
12404
12405         if (!clock1 || !clock2)
12406                 return false;
12407
12408         diff = abs(clock1 - clock2);
12409
12410         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12411                 return true;
12412
12413         return false;
12414 }
12415
12416 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12417         list_for_each_entry((intel_crtc), \
12418                             &(dev)->mode_config.crtc_list, \
12419                             base.head) \
12420                 if (mask & (1 <<(intel_crtc)->pipe))
12421
12422 static bool
12423 intel_compare_m_n(unsigned int m, unsigned int n,
12424                   unsigned int m2, unsigned int n2,
12425                   bool exact)
12426 {
12427         if (m == m2 && n == n2)
12428                 return true;
12429
12430         if (exact || !m || !n || !m2 || !n2)
12431                 return false;
12432
12433         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12434
12435         if (m > m2) {
12436                 while (m > m2) {
12437                         m2 <<= 1;
12438                         n2 <<= 1;
12439                 }
12440         } else if (m < m2) {
12441                 while (m < m2) {
12442                         m <<= 1;
12443                         n <<= 1;
12444                 }
12445         }
12446
12447         return m == m2 && n == n2;
12448 }
12449
12450 static bool
12451 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12452                        struct intel_link_m_n *m2_n2,
12453                        bool adjust)
12454 {
12455         if (m_n->tu == m2_n2->tu &&
12456             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12457                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12458             intel_compare_m_n(m_n->link_m, m_n->link_n,
12459                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12460                 if (adjust)
12461                         *m2_n2 = *m_n;
12462
12463                 return true;
12464         }
12465
12466         return false;
12467 }
12468
12469 static bool
12470 intel_pipe_config_compare(struct drm_device *dev,
12471                           struct intel_crtc_state *current_config,
12472                           struct intel_crtc_state *pipe_config,
12473                           bool adjust)
12474 {
12475         bool ret = true;
12476
12477 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12478         do { \
12479                 if (!adjust) \
12480                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12481                 else \
12482                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12483         } while (0)
12484
12485 #define PIPE_CONF_CHECK_X(name) \
12486         if (current_config->name != pipe_config->name) { \
12487                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12488                           "(expected 0x%08x, found 0x%08x)\n", \
12489                           current_config->name, \
12490                           pipe_config->name); \
12491                 ret = false; \
12492         }
12493
12494 #define PIPE_CONF_CHECK_I(name) \
12495         if (current_config->name != pipe_config->name) { \
12496                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12497                           "(expected %i, found %i)\n", \
12498                           current_config->name, \
12499                           pipe_config->name); \
12500                 ret = false; \
12501         }
12502
12503 #define PIPE_CONF_CHECK_M_N(name) \
12504         if (!intel_compare_link_m_n(&current_config->name, \
12505                                     &pipe_config->name,\
12506                                     adjust)) { \
12507                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12508                           "(expected tu %i gmch %i/%i link %i/%i, " \
12509                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12510                           current_config->name.tu, \
12511                           current_config->name.gmch_m, \
12512                           current_config->name.gmch_n, \
12513                           current_config->name.link_m, \
12514                           current_config->name.link_n, \
12515                           pipe_config->name.tu, \
12516                           pipe_config->name.gmch_m, \
12517                           pipe_config->name.gmch_n, \
12518                           pipe_config->name.link_m, \
12519                           pipe_config->name.link_n); \
12520                 ret = false; \
12521         }
12522
12523 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12524         if (!intel_compare_link_m_n(&current_config->name, \
12525                                     &pipe_config->name, adjust) && \
12526             !intel_compare_link_m_n(&current_config->alt_name, \
12527                                     &pipe_config->name, adjust)) { \
12528                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12529                           "(expected tu %i gmch %i/%i link %i/%i, " \
12530                           "or tu %i gmch %i/%i link %i/%i, " \
12531                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12532                           current_config->name.tu, \
12533                           current_config->name.gmch_m, \
12534                           current_config->name.gmch_n, \
12535                           current_config->name.link_m, \
12536                           current_config->name.link_n, \
12537                           current_config->alt_name.tu, \
12538                           current_config->alt_name.gmch_m, \
12539                           current_config->alt_name.gmch_n, \
12540                           current_config->alt_name.link_m, \
12541                           current_config->alt_name.link_n, \
12542                           pipe_config->name.tu, \
12543                           pipe_config->name.gmch_m, \
12544                           pipe_config->name.gmch_n, \
12545                           pipe_config->name.link_m, \
12546                           pipe_config->name.link_n); \
12547                 ret = false; \
12548         }
12549
12550 /* This is required for BDW+ where there is only one set of registers for
12551  * switching between high and low RR.
12552  * This macro can be used whenever a comparison has to be made between one
12553  * hw state and multiple sw state variables.
12554  */
12555 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12556         if ((current_config->name != pipe_config->name) && \
12557                 (current_config->alt_name != pipe_config->name)) { \
12558                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12559                                   "(expected %i or %i, found %i)\n", \
12560                                   current_config->name, \
12561                                   current_config->alt_name, \
12562                                   pipe_config->name); \
12563                         ret = false; \
12564         }
12565
12566 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12567         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12568                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12569                           "(expected %i, found %i)\n", \
12570                           current_config->name & (mask), \
12571                           pipe_config->name & (mask)); \
12572                 ret = false; \
12573         }
12574
12575 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12576         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12577                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12578                           "(expected %i, found %i)\n", \
12579                           current_config->name, \
12580                           pipe_config->name); \
12581                 ret = false; \
12582         }
12583
12584 #define PIPE_CONF_QUIRK(quirk)  \
12585         ((current_config->quirks | pipe_config->quirks) & (quirk))
12586
12587         PIPE_CONF_CHECK_I(cpu_transcoder);
12588
12589         PIPE_CONF_CHECK_I(has_pch_encoder);
12590         PIPE_CONF_CHECK_I(fdi_lanes);
12591         PIPE_CONF_CHECK_M_N(fdi_m_n);
12592
12593         PIPE_CONF_CHECK_I(has_dp_encoder);
12594         PIPE_CONF_CHECK_I(lane_count);
12595
12596         if (INTEL_INFO(dev)->gen < 8) {
12597                 PIPE_CONF_CHECK_M_N(dp_m_n);
12598
12599                 PIPE_CONF_CHECK_I(has_drrs);
12600                 if (current_config->has_drrs)
12601                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12602         } else
12603                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12604
12605         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12606         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12607         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12608         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12609         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12610         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12611
12612         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12613         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12614         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12615         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12616         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12617         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12618
12619         PIPE_CONF_CHECK_I(pixel_multiplier);
12620         PIPE_CONF_CHECK_I(has_hdmi_sink);
12621         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12622             IS_VALLEYVIEW(dev))
12623                 PIPE_CONF_CHECK_I(limited_color_range);
12624         PIPE_CONF_CHECK_I(has_infoframe);
12625
12626         PIPE_CONF_CHECK_I(has_audio);
12627
12628         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12629                               DRM_MODE_FLAG_INTERLACE);
12630
12631         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12632                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12633                                       DRM_MODE_FLAG_PHSYNC);
12634                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12635                                       DRM_MODE_FLAG_NHSYNC);
12636                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12637                                       DRM_MODE_FLAG_PVSYNC);
12638                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12639                                       DRM_MODE_FLAG_NVSYNC);
12640         }
12641
12642         PIPE_CONF_CHECK_X(gmch_pfit.control);
12643         /* pfit ratios are autocomputed by the hw on gen4+ */
12644         if (INTEL_INFO(dev)->gen < 4)
12645                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12646         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12647
12648         if (!adjust) {
12649                 PIPE_CONF_CHECK_I(pipe_src_w);
12650                 PIPE_CONF_CHECK_I(pipe_src_h);
12651
12652                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12653                 if (current_config->pch_pfit.enabled) {
12654                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12655                         PIPE_CONF_CHECK_X(pch_pfit.size);
12656                 }
12657
12658                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12659         }
12660
12661         /* BDW+ don't expose a synchronous way to read the state */
12662         if (IS_HASWELL(dev))
12663                 PIPE_CONF_CHECK_I(ips_enabled);
12664
12665         PIPE_CONF_CHECK_I(double_wide);
12666
12667         PIPE_CONF_CHECK_X(ddi_pll_sel);
12668
12669         PIPE_CONF_CHECK_I(shared_dpll);
12670         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12671         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12672         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12673         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12674         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12675         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12676         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12677         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12678         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12679
12680         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12681                 PIPE_CONF_CHECK_I(pipe_bpp);
12682
12683         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12684         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12685
12686 #undef PIPE_CONF_CHECK_X
12687 #undef PIPE_CONF_CHECK_I
12688 #undef PIPE_CONF_CHECK_I_ALT
12689 #undef PIPE_CONF_CHECK_FLAGS
12690 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12691 #undef PIPE_CONF_QUIRK
12692 #undef INTEL_ERR_OR_DBG_KMS
12693
12694         return ret;
12695 }
12696
12697 static void check_wm_state(struct drm_device *dev)
12698 {
12699         struct drm_i915_private *dev_priv = dev->dev_private;
12700         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12701         struct intel_crtc *intel_crtc;
12702         int plane;
12703
12704         if (INTEL_INFO(dev)->gen < 9)
12705                 return;
12706
12707         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12708         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12709
12710         for_each_intel_crtc(dev, intel_crtc) {
12711                 struct skl_ddb_entry *hw_entry, *sw_entry;
12712                 const enum pipe pipe = intel_crtc->pipe;
12713
12714                 if (!intel_crtc->active)
12715                         continue;
12716
12717                 /* planes */
12718                 for_each_plane(dev_priv, pipe, plane) {
12719                         hw_entry = &hw_ddb.plane[pipe][plane];
12720                         sw_entry = &sw_ddb->plane[pipe][plane];
12721
12722                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12723                                 continue;
12724
12725                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12726                                   "(expected (%u,%u), found (%u,%u))\n",
12727                                   pipe_name(pipe), plane + 1,
12728                                   sw_entry->start, sw_entry->end,
12729                                   hw_entry->start, hw_entry->end);
12730                 }
12731
12732                 /* cursor */
12733                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12734                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12735
12736                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12737                         continue;
12738
12739                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12740                           "(expected (%u,%u), found (%u,%u))\n",
12741                           pipe_name(pipe),
12742                           sw_entry->start, sw_entry->end,
12743                           hw_entry->start, hw_entry->end);
12744         }
12745 }
12746
12747 static void
12748 check_connector_state(struct drm_device *dev,
12749                       struct drm_atomic_state *old_state)
12750 {
12751         struct drm_connector_state *old_conn_state;
12752         struct drm_connector *connector;
12753         int i;
12754
12755         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12756                 struct drm_encoder *encoder = connector->encoder;
12757                 struct drm_connector_state *state = connector->state;
12758
12759                 /* This also checks the encoder/connector hw state with the
12760                  * ->get_hw_state callbacks. */
12761                 intel_connector_check_state(to_intel_connector(connector));
12762
12763                 I915_STATE_WARN(state->best_encoder != encoder,
12764                      "connector's atomic encoder doesn't match legacy encoder\n");
12765         }
12766 }
12767
12768 static void
12769 check_encoder_state(struct drm_device *dev)
12770 {
12771         struct intel_encoder *encoder;
12772         struct intel_connector *connector;
12773
12774         for_each_intel_encoder(dev, encoder) {
12775                 bool enabled = false;
12776                 enum pipe pipe;
12777
12778                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12779                               encoder->base.base.id,
12780                               encoder->base.name);
12781
12782                 for_each_intel_connector(dev, connector) {
12783                         if (connector->base.state->best_encoder != &encoder->base)
12784                                 continue;
12785                         enabled = true;
12786
12787                         I915_STATE_WARN(connector->base.state->crtc !=
12788                                         encoder->base.crtc,
12789                              "connector's crtc doesn't match encoder crtc\n");
12790                 }
12791
12792                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12793                      "encoder's enabled state mismatch "
12794                      "(expected %i, found %i)\n",
12795                      !!encoder->base.crtc, enabled);
12796
12797                 if (!encoder->base.crtc) {
12798                         bool active;
12799
12800                         active = encoder->get_hw_state(encoder, &pipe);
12801                         I915_STATE_WARN(active,
12802                              "encoder detached but still enabled on pipe %c.\n",
12803                              pipe_name(pipe));
12804                 }
12805         }
12806 }
12807
12808 static void
12809 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12810 {
12811         struct drm_i915_private *dev_priv = dev->dev_private;
12812         struct intel_encoder *encoder;
12813         struct drm_crtc_state *old_crtc_state;
12814         struct drm_crtc *crtc;
12815         int i;
12816
12817         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12818                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12819                 struct intel_crtc_state *pipe_config, *sw_config;
12820                 bool active;
12821
12822                 if (!needs_modeset(crtc->state) &&
12823                     !to_intel_crtc_state(crtc->state)->update_pipe)
12824                         continue;
12825
12826                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12827                 pipe_config = to_intel_crtc_state(old_crtc_state);
12828                 memset(pipe_config, 0, sizeof(*pipe_config));
12829                 pipe_config->base.crtc = crtc;
12830                 pipe_config->base.state = old_state;
12831
12832                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12833                               crtc->base.id);
12834
12835                 active = dev_priv->display.get_pipe_config(intel_crtc,
12836                                                            pipe_config);
12837
12838                 /* hw state is inconsistent with the pipe quirk */
12839                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12840                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12841                         active = crtc->state->active;
12842
12843                 I915_STATE_WARN(crtc->state->active != active,
12844                      "crtc active state doesn't match with hw state "
12845                      "(expected %i, found %i)\n", crtc->state->active, active);
12846
12847                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12848                      "transitional active state does not match atomic hw state "
12849                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12850
12851                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12852                         enum pipe pipe;
12853
12854                         active = encoder->get_hw_state(encoder, &pipe);
12855                         I915_STATE_WARN(active != crtc->state->active,
12856                                 "[ENCODER:%i] active %i with crtc active %i\n",
12857                                 encoder->base.base.id, active, crtc->state->active);
12858
12859                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12860                                         "Encoder connected to wrong pipe %c\n",
12861                                         pipe_name(pipe));
12862
12863                         if (active)
12864                                 encoder->get_config(encoder, pipe_config);
12865                 }
12866
12867                 if (!crtc->state->active)
12868                         continue;
12869
12870                 sw_config = to_intel_crtc_state(crtc->state);
12871                 if (!intel_pipe_config_compare(dev, sw_config,
12872                                                pipe_config, false)) {
12873                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12874                         intel_dump_pipe_config(intel_crtc, pipe_config,
12875                                                "[hw state]");
12876                         intel_dump_pipe_config(intel_crtc, sw_config,
12877                                                "[sw state]");
12878                 }
12879         }
12880 }
12881
12882 static void
12883 check_shared_dpll_state(struct drm_device *dev)
12884 {
12885         struct drm_i915_private *dev_priv = dev->dev_private;
12886         struct intel_crtc *crtc;
12887         struct intel_dpll_hw_state dpll_hw_state;
12888         int i;
12889
12890         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12891                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12892                 int enabled_crtcs = 0, active_crtcs = 0;
12893                 bool active;
12894
12895                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12896
12897                 DRM_DEBUG_KMS("%s\n", pll->name);
12898
12899                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12900
12901                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12902                      "more active pll users than references: %i vs %i\n",
12903                      pll->active, hweight32(pll->config.crtc_mask));
12904                 I915_STATE_WARN(pll->active && !pll->on,
12905                      "pll in active use but not on in sw tracking\n");
12906                 I915_STATE_WARN(pll->on && !pll->active,
12907                      "pll in on but not on in use in sw tracking\n");
12908                 I915_STATE_WARN(pll->on != active,
12909                      "pll on state mismatch (expected %i, found %i)\n",
12910                      pll->on, active);
12911
12912                 for_each_intel_crtc(dev, crtc) {
12913                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12914                                 enabled_crtcs++;
12915                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12916                                 active_crtcs++;
12917                 }
12918                 I915_STATE_WARN(pll->active != active_crtcs,
12919                      "pll active crtcs mismatch (expected %i, found %i)\n",
12920                      pll->active, active_crtcs);
12921                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12922                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12923                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12924
12925                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12926                                        sizeof(dpll_hw_state)),
12927                      "pll hw state mismatch\n");
12928         }
12929 }
12930
12931 static void
12932 intel_modeset_check_state(struct drm_device *dev,
12933                           struct drm_atomic_state *old_state)
12934 {
12935         check_wm_state(dev);
12936         check_connector_state(dev, old_state);
12937         check_encoder_state(dev);
12938         check_crtc_state(dev, old_state);
12939         check_shared_dpll_state(dev);
12940 }
12941
12942 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12943                                      int dotclock)
12944 {
12945         /*
12946          * FDI already provided one idea for the dotclock.
12947          * Yell if the encoder disagrees.
12948          */
12949         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12950              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12951              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12952 }
12953
12954 static void update_scanline_offset(struct intel_crtc *crtc)
12955 {
12956         struct drm_device *dev = crtc->base.dev;
12957
12958         /*
12959          * The scanline counter increments at the leading edge of hsync.
12960          *
12961          * On most platforms it starts counting from vtotal-1 on the
12962          * first active line. That means the scanline counter value is
12963          * always one less than what we would expect. Ie. just after
12964          * start of vblank, which also occurs at start of hsync (on the
12965          * last active line), the scanline counter will read vblank_start-1.
12966          *
12967          * On gen2 the scanline counter starts counting from 1 instead
12968          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12969          * to keep the value positive), instead of adding one.
12970          *
12971          * On HSW+ the behaviour of the scanline counter depends on the output
12972          * type. For DP ports it behaves like most other platforms, but on HDMI
12973          * there's an extra 1 line difference. So we need to add two instead of
12974          * one to the value.
12975          */
12976         if (IS_GEN2(dev)) {
12977                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12978                 int vtotal;
12979
12980                 vtotal = adjusted_mode->crtc_vtotal;
12981                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12982                         vtotal /= 2;
12983
12984                 crtc->scanline_offset = vtotal - 1;
12985         } else if (HAS_DDI(dev) &&
12986                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12987                 crtc->scanline_offset = 2;
12988         } else
12989                 crtc->scanline_offset = 1;
12990 }
12991
12992 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12993 {
12994         struct drm_device *dev = state->dev;
12995         struct drm_i915_private *dev_priv = to_i915(dev);
12996         struct intel_shared_dpll_config *shared_dpll = NULL;
12997         struct intel_crtc *intel_crtc;
12998         struct intel_crtc_state *intel_crtc_state;
12999         struct drm_crtc *crtc;
13000         struct drm_crtc_state *crtc_state;
13001         int i;
13002
13003         if (!dev_priv->display.crtc_compute_clock)
13004                 return;
13005
13006         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13007                 int dpll;
13008
13009                 intel_crtc = to_intel_crtc(crtc);
13010                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13011                 dpll = intel_crtc_state->shared_dpll;
13012
13013                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13014                         continue;
13015
13016                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13017
13018                 if (!shared_dpll)
13019                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13020
13021                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13022         }
13023 }
13024
13025 /*
13026  * This implements the workaround described in the "notes" section of the mode
13027  * set sequence documentation. When going from no pipes or single pipe to
13028  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13029  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13030  */
13031 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13032 {
13033         struct drm_crtc_state *crtc_state;
13034         struct intel_crtc *intel_crtc;
13035         struct drm_crtc *crtc;
13036         struct intel_crtc_state *first_crtc_state = NULL;
13037         struct intel_crtc_state *other_crtc_state = NULL;
13038         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13039         int i;
13040
13041         /* look at all crtc's that are going to be enabled in during modeset */
13042         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13043                 intel_crtc = to_intel_crtc(crtc);
13044
13045                 if (!crtc_state->active || !needs_modeset(crtc_state))
13046                         continue;
13047
13048                 if (first_crtc_state) {
13049                         other_crtc_state = to_intel_crtc_state(crtc_state);
13050                         break;
13051                 } else {
13052                         first_crtc_state = to_intel_crtc_state(crtc_state);
13053                         first_pipe = intel_crtc->pipe;
13054                 }
13055         }
13056
13057         /* No workaround needed? */
13058         if (!first_crtc_state)
13059                 return 0;
13060
13061         /* w/a possibly needed, check how many crtc's are already enabled. */
13062         for_each_intel_crtc(state->dev, intel_crtc) {
13063                 struct intel_crtc_state *pipe_config;
13064
13065                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13066                 if (IS_ERR(pipe_config))
13067                         return PTR_ERR(pipe_config);
13068
13069                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13070
13071                 if (!pipe_config->base.active ||
13072                     needs_modeset(&pipe_config->base))
13073                         continue;
13074
13075                 /* 2 or more enabled crtcs means no need for w/a */
13076                 if (enabled_pipe != INVALID_PIPE)
13077                         return 0;
13078
13079                 enabled_pipe = intel_crtc->pipe;
13080         }
13081
13082         if (enabled_pipe != INVALID_PIPE)
13083                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13084         else if (other_crtc_state)
13085                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13086
13087         return 0;
13088 }
13089
13090 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13091 {
13092         struct drm_crtc *crtc;
13093         struct drm_crtc_state *crtc_state;
13094         int ret = 0;
13095
13096         /* add all active pipes to the state */
13097         for_each_crtc(state->dev, crtc) {
13098                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13099                 if (IS_ERR(crtc_state))
13100                         return PTR_ERR(crtc_state);
13101
13102                 if (!crtc_state->active || needs_modeset(crtc_state))
13103                         continue;
13104
13105                 crtc_state->mode_changed = true;
13106
13107                 ret = drm_atomic_add_affected_connectors(state, crtc);
13108                 if (ret)
13109                         break;
13110
13111                 ret = drm_atomic_add_affected_planes(state, crtc);
13112                 if (ret)
13113                         break;
13114         }
13115
13116         return ret;
13117 }
13118
13119 static int intel_modeset_checks(struct drm_atomic_state *state)
13120 {
13121         struct drm_device *dev = state->dev;
13122         struct drm_i915_private *dev_priv = dev->dev_private;
13123         int ret;
13124
13125         if (!check_digital_port_conflicts(state)) {
13126                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13127                 return -EINVAL;
13128         }
13129
13130         /*
13131          * See if the config requires any additional preparation, e.g.
13132          * to adjust global state with pipes off.  We need to do this
13133          * here so we can get the modeset_pipe updated config for the new
13134          * mode set on this crtc.  For other crtcs we need to use the
13135          * adjusted_mode bits in the crtc directly.
13136          */
13137         if (dev_priv->display.modeset_calc_cdclk) {
13138                 unsigned int cdclk;
13139
13140                 ret = dev_priv->display.modeset_calc_cdclk(state);
13141
13142                 cdclk = to_intel_atomic_state(state)->cdclk;
13143                 if (!ret && cdclk != dev_priv->cdclk_freq)
13144                         ret = intel_modeset_all_pipes(state);
13145
13146                 if (ret < 0)
13147                         return ret;
13148         } else
13149                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13150
13151         intel_modeset_clear_plls(state);
13152
13153         if (IS_HASWELL(dev))
13154                 return haswell_mode_set_planes_workaround(state);
13155
13156         return 0;
13157 }
13158
13159 /*
13160  * Handle calculation of various watermark data at the end of the atomic check
13161  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13162  * handlers to ensure that all derived state has been updated.
13163  */
13164 static void calc_watermark_data(struct drm_atomic_state *state)
13165 {
13166         struct drm_device *dev = state->dev;
13167         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13168         struct drm_crtc *crtc;
13169         struct drm_crtc_state *cstate;
13170         struct drm_plane *plane;
13171         struct drm_plane_state *pstate;
13172
13173         /*
13174          * Calculate watermark configuration details now that derived
13175          * plane/crtc state is all properly updated.
13176          */
13177         drm_for_each_crtc(crtc, dev) {
13178                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13179                         crtc->state;
13180
13181                 if (cstate->active)
13182                         intel_state->wm_config.num_pipes_active++;
13183         }
13184         drm_for_each_legacy_plane(plane, dev) {
13185                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13186                         plane->state;
13187
13188                 if (!to_intel_plane_state(pstate)->visible)
13189                         continue;
13190
13191                 intel_state->wm_config.sprites_enabled = true;
13192                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13193                     pstate->crtc_h != pstate->src_h >> 16)
13194                         intel_state->wm_config.sprites_scaled = true;
13195         }
13196 }
13197
13198 /**
13199  * intel_atomic_check - validate state object
13200  * @dev: drm device
13201  * @state: state to validate
13202  */
13203 static int intel_atomic_check(struct drm_device *dev,
13204                               struct drm_atomic_state *state)
13205 {
13206         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13207         struct drm_crtc *crtc;
13208         struct drm_crtc_state *crtc_state;
13209         int ret, i;
13210         bool any_ms = false;
13211
13212         ret = drm_atomic_helper_check_modeset(dev, state);
13213         if (ret)
13214                 return ret;
13215
13216         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13217                 struct intel_crtc_state *pipe_config =
13218                         to_intel_crtc_state(crtc_state);
13219
13220                 memset(&to_intel_crtc(crtc)->atomic, 0,
13221                        sizeof(struct intel_crtc_atomic_commit));
13222
13223                 /* Catch I915_MODE_FLAG_INHERITED */
13224                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13225                         crtc_state->mode_changed = true;
13226
13227                 if (!crtc_state->enable) {
13228                         if (needs_modeset(crtc_state))
13229                                 any_ms = true;
13230                         continue;
13231                 }
13232
13233                 if (!needs_modeset(crtc_state))
13234                         continue;
13235
13236                 /* FIXME: For only active_changed we shouldn't need to do any
13237                  * state recomputation at all. */
13238
13239                 ret = drm_atomic_add_affected_connectors(state, crtc);
13240                 if (ret)
13241                         return ret;
13242
13243                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13244                 if (ret)
13245                         return ret;
13246
13247                 if (i915.fastboot &&
13248                     intel_pipe_config_compare(state->dev,
13249                                         to_intel_crtc_state(crtc->state),
13250                                         pipe_config, true)) {
13251                         crtc_state->mode_changed = false;
13252                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13253                 }
13254
13255                 if (needs_modeset(crtc_state)) {
13256                         any_ms = true;
13257
13258                         ret = drm_atomic_add_affected_planes(state, crtc);
13259                         if (ret)
13260                                 return ret;
13261                 }
13262
13263                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13264                                        needs_modeset(crtc_state) ?
13265                                        "[modeset]" : "[fastset]");
13266         }
13267
13268         if (any_ms) {
13269                 ret = intel_modeset_checks(state);
13270
13271                 if (ret)
13272                         return ret;
13273         } else
13274                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13275
13276         ret = drm_atomic_helper_check_planes(state->dev, state);
13277         if (ret)
13278                 return ret;
13279
13280         calc_watermark_data(state);
13281
13282         return 0;
13283 }
13284
13285 static int intel_atomic_prepare_commit(struct drm_device *dev,
13286                                        struct drm_atomic_state *state,
13287                                        bool async)
13288 {
13289         struct drm_i915_private *dev_priv = dev->dev_private;
13290         struct drm_plane_state *plane_state;
13291         struct drm_crtc_state *crtc_state;
13292         struct drm_plane *plane;
13293         struct drm_crtc *crtc;
13294         int i, ret;
13295
13296         if (async) {
13297                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13298                 return -EINVAL;
13299         }
13300
13301         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13302                 ret = intel_crtc_wait_for_pending_flips(crtc);
13303                 if (ret)
13304                         return ret;
13305
13306                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13307                         flush_workqueue(dev_priv->wq);
13308         }
13309
13310         ret = mutex_lock_interruptible(&dev->struct_mutex);
13311         if (ret)
13312                 return ret;
13313
13314         ret = drm_atomic_helper_prepare_planes(dev, state);
13315         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13316                 u32 reset_counter;
13317
13318                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13319                 mutex_unlock(&dev->struct_mutex);
13320
13321                 for_each_plane_in_state(state, plane, plane_state, i) {
13322                         struct intel_plane_state *intel_plane_state =
13323                                 to_intel_plane_state(plane_state);
13324
13325                         if (!intel_plane_state->wait_req)
13326                                 continue;
13327
13328                         ret = __i915_wait_request(intel_plane_state->wait_req,
13329                                                   reset_counter, true,
13330                                                   NULL, NULL);
13331
13332                         /* Swallow -EIO errors to allow updates during hw lockup. */
13333                         if (ret == -EIO)
13334                                 ret = 0;
13335
13336                         if (ret)
13337                                 break;
13338                 }
13339
13340                 if (!ret)
13341                         return 0;
13342
13343                 mutex_lock(&dev->struct_mutex);
13344                 drm_atomic_helper_cleanup_planes(dev, state);
13345         }
13346
13347         mutex_unlock(&dev->struct_mutex);
13348         return ret;
13349 }
13350
13351 /**
13352  * intel_atomic_commit - commit validated state object
13353  * @dev: DRM device
13354  * @state: the top-level driver state object
13355  * @async: asynchronous commit
13356  *
13357  * This function commits a top-level state object that has been validated
13358  * with drm_atomic_helper_check().
13359  *
13360  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13361  * we can only handle plane-related operations and do not yet support
13362  * asynchronous commit.
13363  *
13364  * RETURNS
13365  * Zero for success or -errno.
13366  */
13367 static int intel_atomic_commit(struct drm_device *dev,
13368                                struct drm_atomic_state *state,
13369                                bool async)
13370 {
13371         struct drm_i915_private *dev_priv = dev->dev_private;
13372         struct drm_crtc_state *crtc_state;
13373         struct drm_crtc *crtc;
13374         int ret = 0;
13375         int i;
13376         bool any_ms = false;
13377
13378         ret = intel_atomic_prepare_commit(dev, state, async);
13379         if (ret) {
13380                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13381                 return ret;
13382         }
13383
13384         drm_atomic_helper_swap_state(dev, state);
13385         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13386
13387         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13388                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13389
13390                 if (!needs_modeset(crtc->state))
13391                         continue;
13392
13393                 any_ms = true;
13394                 intel_pre_plane_update(intel_crtc);
13395
13396                 if (crtc_state->active) {
13397                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13398                         dev_priv->display.crtc_disable(crtc);
13399                         intel_crtc->active = false;
13400                         intel_disable_shared_dpll(intel_crtc);
13401
13402                         /*
13403                          * Underruns don't always raise
13404                          * interrupts, so check manually.
13405                          */
13406                         intel_check_cpu_fifo_underruns(dev_priv);
13407                         intel_check_pch_fifo_underruns(dev_priv);
13408                 }
13409         }
13410
13411         /* Only after disabling all output pipelines that will be changed can we
13412          * update the the output configuration. */
13413         intel_modeset_update_crtc_state(state);
13414
13415         if (any_ms) {
13416                 intel_shared_dpll_commit(state);
13417
13418                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13419                 modeset_update_crtc_power_domains(state);
13420         }
13421
13422         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13423         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13424                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13425                 bool modeset = needs_modeset(crtc->state);
13426                 bool update_pipe = !modeset &&
13427                         to_intel_crtc_state(crtc->state)->update_pipe;
13428                 unsigned long put_domains = 0;
13429
13430                 if (modeset)
13431                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13432
13433                 if (modeset && crtc->state->active) {
13434                         update_scanline_offset(to_intel_crtc(crtc));
13435                         dev_priv->display.crtc_enable(crtc);
13436                 }
13437
13438                 if (update_pipe) {
13439                         put_domains = modeset_get_crtc_power_domains(crtc);
13440
13441                         /* make sure intel_modeset_check_state runs */
13442                         any_ms = true;
13443                 }
13444
13445                 if (!modeset)
13446                         intel_pre_plane_update(intel_crtc);
13447
13448                 if (crtc->state->active &&
13449                     (crtc->state->planes_changed || update_pipe))
13450                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13451
13452                 if (put_domains)
13453                         modeset_put_power_domains(dev_priv, put_domains);
13454
13455                 intel_post_plane_update(intel_crtc);
13456
13457                 if (modeset)
13458                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13459         }
13460
13461         /* FIXME: add subpixel order */
13462
13463         drm_atomic_helper_wait_for_vblanks(dev, state);
13464
13465         mutex_lock(&dev->struct_mutex);
13466         drm_atomic_helper_cleanup_planes(dev, state);
13467         mutex_unlock(&dev->struct_mutex);
13468
13469         if (any_ms)
13470                 intel_modeset_check_state(dev, state);
13471
13472         drm_atomic_state_free(state);
13473
13474         return 0;
13475 }
13476
13477 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13478 {
13479         struct drm_device *dev = crtc->dev;
13480         struct drm_atomic_state *state;
13481         struct drm_crtc_state *crtc_state;
13482         int ret;
13483
13484         state = drm_atomic_state_alloc(dev);
13485         if (!state) {
13486                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13487                               crtc->base.id);
13488                 return;
13489         }
13490
13491         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13492
13493 retry:
13494         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13495         ret = PTR_ERR_OR_ZERO(crtc_state);
13496         if (!ret) {
13497                 if (!crtc_state->active)
13498                         goto out;
13499
13500                 crtc_state->mode_changed = true;
13501                 ret = drm_atomic_commit(state);
13502         }
13503
13504         if (ret == -EDEADLK) {
13505                 drm_atomic_state_clear(state);
13506                 drm_modeset_backoff(state->acquire_ctx);
13507                 goto retry;
13508         }
13509
13510         if (ret)
13511 out:
13512                 drm_atomic_state_free(state);
13513 }
13514
13515 #undef for_each_intel_crtc_masked
13516
13517 static const struct drm_crtc_funcs intel_crtc_funcs = {
13518         .gamma_set = intel_crtc_gamma_set,
13519         .set_config = drm_atomic_helper_set_config,
13520         .destroy = intel_crtc_destroy,
13521         .page_flip = intel_crtc_page_flip,
13522         .atomic_duplicate_state = intel_crtc_duplicate_state,
13523         .atomic_destroy_state = intel_crtc_destroy_state,
13524 };
13525
13526 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13527                                       struct intel_shared_dpll *pll,
13528                                       struct intel_dpll_hw_state *hw_state)
13529 {
13530         uint32_t val;
13531
13532         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13533                 return false;
13534
13535         val = I915_READ(PCH_DPLL(pll->id));
13536         hw_state->dpll = val;
13537         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13538         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13539
13540         return val & DPLL_VCO_ENABLE;
13541 }
13542
13543 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13544                                   struct intel_shared_dpll *pll)
13545 {
13546         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13547         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13548 }
13549
13550 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13551                                 struct intel_shared_dpll *pll)
13552 {
13553         /* PCH refclock must be enabled first */
13554         ibx_assert_pch_refclk_enabled(dev_priv);
13555
13556         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13557
13558         /* Wait for the clocks to stabilize. */
13559         POSTING_READ(PCH_DPLL(pll->id));
13560         udelay(150);
13561
13562         /* The pixel multiplier can only be updated once the
13563          * DPLL is enabled and the clocks are stable.
13564          *
13565          * So write it again.
13566          */
13567         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13568         POSTING_READ(PCH_DPLL(pll->id));
13569         udelay(200);
13570 }
13571
13572 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13573                                  struct intel_shared_dpll *pll)
13574 {
13575         struct drm_device *dev = dev_priv->dev;
13576         struct intel_crtc *crtc;
13577
13578         /* Make sure no transcoder isn't still depending on us. */
13579         for_each_intel_crtc(dev, crtc) {
13580                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13581                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13582         }
13583
13584         I915_WRITE(PCH_DPLL(pll->id), 0);
13585         POSTING_READ(PCH_DPLL(pll->id));
13586         udelay(200);
13587 }
13588
13589 static char *ibx_pch_dpll_names[] = {
13590         "PCH DPLL A",
13591         "PCH DPLL B",
13592 };
13593
13594 static void ibx_pch_dpll_init(struct drm_device *dev)
13595 {
13596         struct drm_i915_private *dev_priv = dev->dev_private;
13597         int i;
13598
13599         dev_priv->num_shared_dpll = 2;
13600
13601         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13602                 dev_priv->shared_dplls[i].id = i;
13603                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13604                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13605                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13606                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13607                 dev_priv->shared_dplls[i].get_hw_state =
13608                         ibx_pch_dpll_get_hw_state;
13609         }
13610 }
13611
13612 static void intel_shared_dpll_init(struct drm_device *dev)
13613 {
13614         struct drm_i915_private *dev_priv = dev->dev_private;
13615
13616         if (HAS_DDI(dev))
13617                 intel_ddi_pll_init(dev);
13618         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13619                 ibx_pch_dpll_init(dev);
13620         else
13621                 dev_priv->num_shared_dpll = 0;
13622
13623         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13624 }
13625
13626 /**
13627  * intel_prepare_plane_fb - Prepare fb for usage on plane
13628  * @plane: drm plane to prepare for
13629  * @fb: framebuffer to prepare for presentation
13630  *
13631  * Prepares a framebuffer for usage on a display plane.  Generally this
13632  * involves pinning the underlying object and updating the frontbuffer tracking
13633  * bits.  Some older platforms need special physical address handling for
13634  * cursor planes.
13635  *
13636  * Must be called with struct_mutex held.
13637  *
13638  * Returns 0 on success, negative error code on failure.
13639  */
13640 int
13641 intel_prepare_plane_fb(struct drm_plane *plane,
13642                        const struct drm_plane_state *new_state)
13643 {
13644         struct drm_device *dev = plane->dev;
13645         struct drm_framebuffer *fb = new_state->fb;
13646         struct intel_plane *intel_plane = to_intel_plane(plane);
13647         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13648         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13649         int ret = 0;
13650
13651         if (!obj && !old_obj)
13652                 return 0;
13653
13654         if (old_obj) {
13655                 struct drm_crtc_state *crtc_state =
13656                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13657
13658                 /* Big Hammer, we also need to ensure that any pending
13659                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13660                  * current scanout is retired before unpinning the old
13661                  * framebuffer. Note that we rely on userspace rendering
13662                  * into the buffer attached to the pipe they are waiting
13663                  * on. If not, userspace generates a GPU hang with IPEHR
13664                  * point to the MI_WAIT_FOR_EVENT.
13665                  *
13666                  * This should only fail upon a hung GPU, in which case we
13667                  * can safely continue.
13668                  */
13669                 if (needs_modeset(crtc_state))
13670                         ret = i915_gem_object_wait_rendering(old_obj, true);
13671
13672                 /* Swallow -EIO errors to allow updates during hw lockup. */
13673                 if (ret && ret != -EIO)
13674                         return ret;
13675         }
13676
13677         if (!obj) {
13678                 ret = 0;
13679         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13680             INTEL_INFO(dev)->cursor_needs_physical) {
13681                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13682                 ret = i915_gem_object_attach_phys(obj, align);
13683                 if (ret)
13684                         DRM_DEBUG_KMS("failed to attach phys object\n");
13685         } else {
13686                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13687         }
13688
13689         if (ret == 0) {
13690                 if (obj) {
13691                         struct intel_plane_state *plane_state =
13692                                 to_intel_plane_state(new_state);
13693
13694                         i915_gem_request_assign(&plane_state->wait_req,
13695                                                 obj->last_write_req);
13696                 }
13697
13698                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13699         }
13700
13701         return ret;
13702 }
13703
13704 /**
13705  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13706  * @plane: drm plane to clean up for
13707  * @fb: old framebuffer that was on plane
13708  *
13709  * Cleans up a framebuffer that has just been removed from a plane.
13710  *
13711  * Must be called with struct_mutex held.
13712  */
13713 void
13714 intel_cleanup_plane_fb(struct drm_plane *plane,
13715                        const struct drm_plane_state *old_state)
13716 {
13717         struct drm_device *dev = plane->dev;
13718         struct intel_plane *intel_plane = to_intel_plane(plane);
13719         struct intel_plane_state *old_intel_state;
13720         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13721         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13722
13723         old_intel_state = to_intel_plane_state(old_state);
13724
13725         if (!obj && !old_obj)
13726                 return;
13727
13728         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13729             !INTEL_INFO(dev)->cursor_needs_physical))
13730                 intel_unpin_fb_obj(old_state->fb, old_state);
13731
13732         /* prepare_fb aborted? */
13733         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13734             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13735                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13736
13737         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13738
13739 }
13740
13741 int
13742 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13743 {
13744         int max_scale;
13745         struct drm_device *dev;
13746         struct drm_i915_private *dev_priv;
13747         int crtc_clock, cdclk;
13748
13749         if (!intel_crtc || !crtc_state)
13750                 return DRM_PLANE_HELPER_NO_SCALING;
13751
13752         dev = intel_crtc->base.dev;
13753         dev_priv = dev->dev_private;
13754         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13755         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13756
13757         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13758                 return DRM_PLANE_HELPER_NO_SCALING;
13759
13760         /*
13761          * skl max scale is lower of:
13762          *    close to 3 but not 3, -1 is for that purpose
13763          *            or
13764          *    cdclk/crtc_clock
13765          */
13766         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13767
13768         return max_scale;
13769 }
13770
13771 static int
13772 intel_check_primary_plane(struct drm_plane *plane,
13773                           struct intel_crtc_state *crtc_state,
13774                           struct intel_plane_state *state)
13775 {
13776         struct drm_crtc *crtc = state->base.crtc;
13777         struct drm_framebuffer *fb = state->base.fb;
13778         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13779         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13780         bool can_position = false;
13781
13782         /* use scaler when colorkey is not required */
13783         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13784             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13785                 min_scale = 1;
13786                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13787                 can_position = true;
13788         }
13789
13790         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13791                                              &state->dst, &state->clip,
13792                                              min_scale, max_scale,
13793                                              can_position, true,
13794                                              &state->visible);
13795 }
13796
13797 static void
13798 intel_commit_primary_plane(struct drm_plane *plane,
13799                            struct intel_plane_state *state)
13800 {
13801         struct drm_crtc *crtc = state->base.crtc;
13802         struct drm_framebuffer *fb = state->base.fb;
13803         struct drm_device *dev = plane->dev;
13804         struct drm_i915_private *dev_priv = dev->dev_private;
13805
13806         crtc = crtc ? crtc : plane->crtc;
13807
13808         dev_priv->display.update_primary_plane(crtc, fb,
13809                                                state->src.x1 >> 16,
13810                                                state->src.y1 >> 16);
13811 }
13812
13813 static void
13814 intel_disable_primary_plane(struct drm_plane *plane,
13815                             struct drm_crtc *crtc)
13816 {
13817         struct drm_device *dev = plane->dev;
13818         struct drm_i915_private *dev_priv = dev->dev_private;
13819
13820         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13821 }
13822
13823 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13824                                     struct drm_crtc_state *old_crtc_state)
13825 {
13826         struct drm_device *dev = crtc->dev;
13827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13828         struct intel_crtc_state *old_intel_state =
13829                 to_intel_crtc_state(old_crtc_state);
13830         bool modeset = needs_modeset(crtc->state);
13831
13832         if (intel_crtc->atomic.update_wm_pre)
13833                 intel_update_watermarks(crtc);
13834
13835         /* Perform vblank evasion around commit operation */
13836         intel_pipe_update_start(intel_crtc);
13837
13838         if (modeset)
13839                 return;
13840
13841         if (to_intel_crtc_state(crtc->state)->update_pipe)
13842                 intel_update_pipe_config(intel_crtc, old_intel_state);
13843         else if (INTEL_INFO(dev)->gen >= 9)
13844                 skl_detach_scalers(intel_crtc);
13845 }
13846
13847 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13848                                      struct drm_crtc_state *old_crtc_state)
13849 {
13850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13851
13852         intel_pipe_update_end(intel_crtc);
13853 }
13854
13855 /**
13856  * intel_plane_destroy - destroy a plane
13857  * @plane: plane to destroy
13858  *
13859  * Common destruction function for all types of planes (primary, cursor,
13860  * sprite).
13861  */
13862 void intel_plane_destroy(struct drm_plane *plane)
13863 {
13864         struct intel_plane *intel_plane = to_intel_plane(plane);
13865         drm_plane_cleanup(plane);
13866         kfree(intel_plane);
13867 }
13868
13869 const struct drm_plane_funcs intel_plane_funcs = {
13870         .update_plane = drm_atomic_helper_update_plane,
13871         .disable_plane = drm_atomic_helper_disable_plane,
13872         .destroy = intel_plane_destroy,
13873         .set_property = drm_atomic_helper_plane_set_property,
13874         .atomic_get_property = intel_plane_atomic_get_property,
13875         .atomic_set_property = intel_plane_atomic_set_property,
13876         .atomic_duplicate_state = intel_plane_duplicate_state,
13877         .atomic_destroy_state = intel_plane_destroy_state,
13878
13879 };
13880
13881 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13882                                                     int pipe)
13883 {
13884         struct intel_plane *primary;
13885         struct intel_plane_state *state;
13886         const uint32_t *intel_primary_formats;
13887         unsigned int num_formats;
13888
13889         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13890         if (primary == NULL)
13891                 return NULL;
13892
13893         state = intel_create_plane_state(&primary->base);
13894         if (!state) {
13895                 kfree(primary);
13896                 return NULL;
13897         }
13898         primary->base.state = &state->base;
13899
13900         primary->can_scale = false;
13901         primary->max_downscale = 1;
13902         if (INTEL_INFO(dev)->gen >= 9) {
13903                 primary->can_scale = true;
13904                 state->scaler_id = -1;
13905         }
13906         primary->pipe = pipe;
13907         primary->plane = pipe;
13908         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13909         primary->check_plane = intel_check_primary_plane;
13910         primary->commit_plane = intel_commit_primary_plane;
13911         primary->disable_plane = intel_disable_primary_plane;
13912         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13913                 primary->plane = !pipe;
13914
13915         if (INTEL_INFO(dev)->gen >= 9) {
13916                 intel_primary_formats = skl_primary_formats;
13917                 num_formats = ARRAY_SIZE(skl_primary_formats);
13918         } else if (INTEL_INFO(dev)->gen >= 4) {
13919                 intel_primary_formats = i965_primary_formats;
13920                 num_formats = ARRAY_SIZE(i965_primary_formats);
13921         } else {
13922                 intel_primary_formats = i8xx_primary_formats;
13923                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13924         }
13925
13926         drm_universal_plane_init(dev, &primary->base, 0,
13927                                  &intel_plane_funcs,
13928                                  intel_primary_formats, num_formats,
13929                                  DRM_PLANE_TYPE_PRIMARY);
13930
13931         if (INTEL_INFO(dev)->gen >= 4)
13932                 intel_create_rotation_property(dev, primary);
13933
13934         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13935
13936         return &primary->base;
13937 }
13938
13939 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13940 {
13941         if (!dev->mode_config.rotation_property) {
13942                 unsigned long flags = BIT(DRM_ROTATE_0) |
13943                         BIT(DRM_ROTATE_180);
13944
13945                 if (INTEL_INFO(dev)->gen >= 9)
13946                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13947
13948                 dev->mode_config.rotation_property =
13949                         drm_mode_create_rotation_property(dev, flags);
13950         }
13951         if (dev->mode_config.rotation_property)
13952                 drm_object_attach_property(&plane->base.base,
13953                                 dev->mode_config.rotation_property,
13954                                 plane->base.state->rotation);
13955 }
13956
13957 static int
13958 intel_check_cursor_plane(struct drm_plane *plane,
13959                          struct intel_crtc_state *crtc_state,
13960                          struct intel_plane_state *state)
13961 {
13962         struct drm_crtc *crtc = crtc_state->base.crtc;
13963         struct drm_framebuffer *fb = state->base.fb;
13964         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13965         unsigned stride;
13966         int ret;
13967
13968         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13969                                             &state->dst, &state->clip,
13970                                             DRM_PLANE_HELPER_NO_SCALING,
13971                                             DRM_PLANE_HELPER_NO_SCALING,
13972                                             true, true, &state->visible);
13973         if (ret)
13974                 return ret;
13975
13976         /* if we want to turn off the cursor ignore width and height */
13977         if (!obj)
13978                 return 0;
13979
13980         /* Check for which cursor types we support */
13981         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13982                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13983                           state->base.crtc_w, state->base.crtc_h);
13984                 return -EINVAL;
13985         }
13986
13987         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13988         if (obj->base.size < stride * state->base.crtc_h) {
13989                 DRM_DEBUG_KMS("buffer is too small\n");
13990                 return -ENOMEM;
13991         }
13992
13993         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13994                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13995                 return -EINVAL;
13996         }
13997
13998         return 0;
13999 }
14000
14001 static void
14002 intel_disable_cursor_plane(struct drm_plane *plane,
14003                            struct drm_crtc *crtc)
14004 {
14005         intel_crtc_update_cursor(crtc, false);
14006 }
14007
14008 static void
14009 intel_commit_cursor_plane(struct drm_plane *plane,
14010                           struct intel_plane_state *state)
14011 {
14012         struct drm_crtc *crtc = state->base.crtc;
14013         struct drm_device *dev = plane->dev;
14014         struct intel_crtc *intel_crtc;
14015         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14016         uint32_t addr;
14017
14018         crtc = crtc ? crtc : plane->crtc;
14019         intel_crtc = to_intel_crtc(crtc);
14020
14021         if (intel_crtc->cursor_bo == obj)
14022                 goto update;
14023
14024         if (!obj)
14025                 addr = 0;
14026         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14027                 addr = i915_gem_obj_ggtt_offset(obj);
14028         else
14029                 addr = obj->phys_handle->busaddr;
14030
14031         intel_crtc->cursor_addr = addr;
14032         intel_crtc->cursor_bo = obj;
14033
14034 update:
14035         intel_crtc_update_cursor(crtc, state->visible);
14036 }
14037
14038 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14039                                                    int pipe)
14040 {
14041         struct intel_plane *cursor;
14042         struct intel_plane_state *state;
14043
14044         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14045         if (cursor == NULL)
14046                 return NULL;
14047
14048         state = intel_create_plane_state(&cursor->base);
14049         if (!state) {
14050                 kfree(cursor);
14051                 return NULL;
14052         }
14053         cursor->base.state = &state->base;
14054
14055         cursor->can_scale = false;
14056         cursor->max_downscale = 1;
14057         cursor->pipe = pipe;
14058         cursor->plane = pipe;
14059         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14060         cursor->check_plane = intel_check_cursor_plane;
14061         cursor->commit_plane = intel_commit_cursor_plane;
14062         cursor->disable_plane = intel_disable_cursor_plane;
14063
14064         drm_universal_plane_init(dev, &cursor->base, 0,
14065                                  &intel_plane_funcs,
14066                                  intel_cursor_formats,
14067                                  ARRAY_SIZE(intel_cursor_formats),
14068                                  DRM_PLANE_TYPE_CURSOR);
14069
14070         if (INTEL_INFO(dev)->gen >= 4) {
14071                 if (!dev->mode_config.rotation_property)
14072                         dev->mode_config.rotation_property =
14073                                 drm_mode_create_rotation_property(dev,
14074                                                         BIT(DRM_ROTATE_0) |
14075                                                         BIT(DRM_ROTATE_180));
14076                 if (dev->mode_config.rotation_property)
14077                         drm_object_attach_property(&cursor->base.base,
14078                                 dev->mode_config.rotation_property,
14079                                 state->base.rotation);
14080         }
14081
14082         if (INTEL_INFO(dev)->gen >=9)
14083                 state->scaler_id = -1;
14084
14085         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14086
14087         return &cursor->base;
14088 }
14089
14090 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14091         struct intel_crtc_state *crtc_state)
14092 {
14093         int i;
14094         struct intel_scaler *intel_scaler;
14095         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14096
14097         for (i = 0; i < intel_crtc->num_scalers; i++) {
14098                 intel_scaler = &scaler_state->scalers[i];
14099                 intel_scaler->in_use = 0;
14100                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14101         }
14102
14103         scaler_state->scaler_id = -1;
14104 }
14105
14106 static void intel_crtc_init(struct drm_device *dev, int pipe)
14107 {
14108         struct drm_i915_private *dev_priv = dev->dev_private;
14109         struct intel_crtc *intel_crtc;
14110         struct intel_crtc_state *crtc_state = NULL;
14111         struct drm_plane *primary = NULL;
14112         struct drm_plane *cursor = NULL;
14113         int i, ret;
14114
14115         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14116         if (intel_crtc == NULL)
14117                 return;
14118
14119         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14120         if (!crtc_state)
14121                 goto fail;
14122         intel_crtc->config = crtc_state;
14123         intel_crtc->base.state = &crtc_state->base;
14124         crtc_state->base.crtc = &intel_crtc->base;
14125
14126         /* initialize shared scalers */
14127         if (INTEL_INFO(dev)->gen >= 9) {
14128                 if (pipe == PIPE_C)
14129                         intel_crtc->num_scalers = 1;
14130                 else
14131                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14132
14133                 skl_init_scalers(dev, intel_crtc, crtc_state);
14134         }
14135
14136         primary = intel_primary_plane_create(dev, pipe);
14137         if (!primary)
14138                 goto fail;
14139
14140         cursor = intel_cursor_plane_create(dev, pipe);
14141         if (!cursor)
14142                 goto fail;
14143
14144         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14145                                         cursor, &intel_crtc_funcs);
14146         if (ret)
14147                 goto fail;
14148
14149         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14150         for (i = 0; i < 256; i++) {
14151                 intel_crtc->lut_r[i] = i;
14152                 intel_crtc->lut_g[i] = i;
14153                 intel_crtc->lut_b[i] = i;
14154         }
14155
14156         /*
14157          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14158          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14159          */
14160         intel_crtc->pipe = pipe;
14161         intel_crtc->plane = pipe;
14162         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14163                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14164                 intel_crtc->plane = !pipe;
14165         }
14166
14167         intel_crtc->cursor_base = ~0;
14168         intel_crtc->cursor_cntl = ~0;
14169         intel_crtc->cursor_size = ~0;
14170
14171         intel_crtc->wm.cxsr_allowed = true;
14172
14173         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14174                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14175         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14176         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14177
14178         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14179
14180         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14181         return;
14182
14183 fail:
14184         if (primary)
14185                 drm_plane_cleanup(primary);
14186         if (cursor)
14187                 drm_plane_cleanup(cursor);
14188         kfree(crtc_state);
14189         kfree(intel_crtc);
14190 }
14191
14192 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14193 {
14194         struct drm_encoder *encoder = connector->base.encoder;
14195         struct drm_device *dev = connector->base.dev;
14196
14197         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14198
14199         if (!encoder || WARN_ON(!encoder->crtc))
14200                 return INVALID_PIPE;
14201
14202         return to_intel_crtc(encoder->crtc)->pipe;
14203 }
14204
14205 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14206                                 struct drm_file *file)
14207 {
14208         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14209         struct drm_crtc *drmmode_crtc;
14210         struct intel_crtc *crtc;
14211
14212         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14213
14214         if (!drmmode_crtc) {
14215                 DRM_ERROR("no such CRTC id\n");
14216                 return -ENOENT;
14217         }
14218
14219         crtc = to_intel_crtc(drmmode_crtc);
14220         pipe_from_crtc_id->pipe = crtc->pipe;
14221
14222         return 0;
14223 }
14224
14225 static int intel_encoder_clones(struct intel_encoder *encoder)
14226 {
14227         struct drm_device *dev = encoder->base.dev;
14228         struct intel_encoder *source_encoder;
14229         int index_mask = 0;
14230         int entry = 0;
14231
14232         for_each_intel_encoder(dev, source_encoder) {
14233                 if (encoders_cloneable(encoder, source_encoder))
14234                         index_mask |= (1 << entry);
14235
14236                 entry++;
14237         }
14238
14239         return index_mask;
14240 }
14241
14242 static bool has_edp_a(struct drm_device *dev)
14243 {
14244         struct drm_i915_private *dev_priv = dev->dev_private;
14245
14246         if (!IS_MOBILE(dev))
14247                 return false;
14248
14249         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14250                 return false;
14251
14252         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14253                 return false;
14254
14255         return true;
14256 }
14257
14258 static bool intel_crt_present(struct drm_device *dev)
14259 {
14260         struct drm_i915_private *dev_priv = dev->dev_private;
14261
14262         if (INTEL_INFO(dev)->gen >= 9)
14263                 return false;
14264
14265         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14266                 return false;
14267
14268         if (IS_CHERRYVIEW(dev))
14269                 return false;
14270
14271         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14272                 return false;
14273
14274         return true;
14275 }
14276
14277 static void intel_setup_outputs(struct drm_device *dev)
14278 {
14279         struct drm_i915_private *dev_priv = dev->dev_private;
14280         struct intel_encoder *encoder;
14281         bool dpd_is_edp = false;
14282
14283         intel_lvds_init(dev);
14284
14285         if (intel_crt_present(dev))
14286                 intel_crt_init(dev);
14287
14288         if (IS_BROXTON(dev)) {
14289                 /*
14290                  * FIXME: Broxton doesn't support port detection via the
14291                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14292                  * detect the ports.
14293                  */
14294                 intel_ddi_init(dev, PORT_A);
14295                 intel_ddi_init(dev, PORT_B);
14296                 intel_ddi_init(dev, PORT_C);
14297         } else if (HAS_DDI(dev)) {
14298                 int found;
14299
14300                 /*
14301                  * Haswell uses DDI functions to detect digital outputs.
14302                  * On SKL pre-D0 the strap isn't connected, so we assume
14303                  * it's there.
14304                  */
14305                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14306                 /* WaIgnoreDDIAStrap: skl */
14307                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14308                         intel_ddi_init(dev, PORT_A);
14309
14310                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14311                  * register */
14312                 found = I915_READ(SFUSE_STRAP);
14313
14314                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14315                         intel_ddi_init(dev, PORT_B);
14316                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14317                         intel_ddi_init(dev, PORT_C);
14318                 if (found & SFUSE_STRAP_DDID_DETECTED)
14319                         intel_ddi_init(dev, PORT_D);
14320                 /*
14321                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14322                  */
14323                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14324                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14325                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14326                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14327                         intel_ddi_init(dev, PORT_E);
14328
14329         } else if (HAS_PCH_SPLIT(dev)) {
14330                 int found;
14331                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14332
14333                 if (has_edp_a(dev))
14334                         intel_dp_init(dev, DP_A, PORT_A);
14335
14336                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14337                         /* PCH SDVOB multiplex with HDMIB */
14338                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14339                         if (!found)
14340                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14341                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14342                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14343                 }
14344
14345                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14346                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14347
14348                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14349                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14350
14351                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14352                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14353
14354                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14355                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14356         } else if (IS_VALLEYVIEW(dev)) {
14357                 /*
14358                  * The DP_DETECTED bit is the latched state of the DDC
14359                  * SDA pin at boot. However since eDP doesn't require DDC
14360                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14361                  * eDP ports may have been muxed to an alternate function.
14362                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14363                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14364                  * detect eDP ports.
14365                  */
14366                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14367                     !intel_dp_is_edp(dev, PORT_B))
14368                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14369                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14370                     intel_dp_is_edp(dev, PORT_B))
14371                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14372
14373                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14374                     !intel_dp_is_edp(dev, PORT_C))
14375                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14376                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14377                     intel_dp_is_edp(dev, PORT_C))
14378                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14379
14380                 if (IS_CHERRYVIEW(dev)) {
14381                         /* eDP not supported on port D, so don't check VBT */
14382                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14383                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14384                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14385                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14386                 }
14387
14388                 intel_dsi_init(dev);
14389         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14390                 bool found = false;
14391
14392                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14393                         DRM_DEBUG_KMS("probing SDVOB\n");
14394                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14395                         if (!found && IS_G4X(dev)) {
14396                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14397                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14398                         }
14399
14400                         if (!found && IS_G4X(dev))
14401                                 intel_dp_init(dev, DP_B, PORT_B);
14402                 }
14403
14404                 /* Before G4X SDVOC doesn't have its own detect register */
14405
14406                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14407                         DRM_DEBUG_KMS("probing SDVOC\n");
14408                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14409                 }
14410
14411                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14412
14413                         if (IS_G4X(dev)) {
14414                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14415                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14416                         }
14417                         if (IS_G4X(dev))
14418                                 intel_dp_init(dev, DP_C, PORT_C);
14419                 }
14420
14421                 if (IS_G4X(dev) &&
14422                     (I915_READ(DP_D) & DP_DETECTED))
14423                         intel_dp_init(dev, DP_D, PORT_D);
14424         } else if (IS_GEN2(dev))
14425                 intel_dvo_init(dev);
14426
14427         if (SUPPORTS_TV(dev))
14428                 intel_tv_init(dev);
14429
14430         intel_psr_init(dev);
14431
14432         for_each_intel_encoder(dev, encoder) {
14433                 encoder->base.possible_crtcs = encoder->crtc_mask;
14434                 encoder->base.possible_clones =
14435                         intel_encoder_clones(encoder);
14436         }
14437
14438         intel_init_pch_refclk(dev);
14439
14440         drm_helper_move_panel_connectors_to_head(dev);
14441 }
14442
14443 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14444 {
14445         struct drm_device *dev = fb->dev;
14446         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14447
14448         drm_framebuffer_cleanup(fb);
14449         mutex_lock(&dev->struct_mutex);
14450         WARN_ON(!intel_fb->obj->framebuffer_references--);
14451         drm_gem_object_unreference(&intel_fb->obj->base);
14452         mutex_unlock(&dev->struct_mutex);
14453         kfree(intel_fb);
14454 }
14455
14456 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14457                                                 struct drm_file *file,
14458                                                 unsigned int *handle)
14459 {
14460         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14461         struct drm_i915_gem_object *obj = intel_fb->obj;
14462
14463         if (obj->userptr.mm) {
14464                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14465                 return -EINVAL;
14466         }
14467
14468         return drm_gem_handle_create(file, &obj->base, handle);
14469 }
14470
14471 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14472                                         struct drm_file *file,
14473                                         unsigned flags, unsigned color,
14474                                         struct drm_clip_rect *clips,
14475                                         unsigned num_clips)
14476 {
14477         struct drm_device *dev = fb->dev;
14478         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14479         struct drm_i915_gem_object *obj = intel_fb->obj;
14480
14481         mutex_lock(&dev->struct_mutex);
14482         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14483         mutex_unlock(&dev->struct_mutex);
14484
14485         return 0;
14486 }
14487
14488 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14489         .destroy = intel_user_framebuffer_destroy,
14490         .create_handle = intel_user_framebuffer_create_handle,
14491         .dirty = intel_user_framebuffer_dirty,
14492 };
14493
14494 static
14495 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14496                          uint32_t pixel_format)
14497 {
14498         u32 gen = INTEL_INFO(dev)->gen;
14499
14500         if (gen >= 9) {
14501                 /* "The stride in bytes must not exceed the of the size of 8K
14502                  *  pixels and 32K bytes."
14503                  */
14504                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14505         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14506                 return 32*1024;
14507         } else if (gen >= 4) {
14508                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14509                         return 16*1024;
14510                 else
14511                         return 32*1024;
14512         } else if (gen >= 3) {
14513                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14514                         return 8*1024;
14515                 else
14516                         return 16*1024;
14517         } else {
14518                 /* XXX DSPC is limited to 4k tiled */
14519                 return 8*1024;
14520         }
14521 }
14522
14523 static int intel_framebuffer_init(struct drm_device *dev,
14524                                   struct intel_framebuffer *intel_fb,
14525                                   struct drm_mode_fb_cmd2 *mode_cmd,
14526                                   struct drm_i915_gem_object *obj)
14527 {
14528         unsigned int aligned_height;
14529         int ret;
14530         u32 pitch_limit, stride_alignment;
14531
14532         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14533
14534         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14535                 /* Enforce that fb modifier and tiling mode match, but only for
14536                  * X-tiled. This is needed for FBC. */
14537                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14538                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14539                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14540                         return -EINVAL;
14541                 }
14542         } else {
14543                 if (obj->tiling_mode == I915_TILING_X)
14544                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14545                 else if (obj->tiling_mode == I915_TILING_Y) {
14546                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14547                         return -EINVAL;
14548                 }
14549         }
14550
14551         /* Passed in modifier sanity checking. */
14552         switch (mode_cmd->modifier[0]) {
14553         case I915_FORMAT_MOD_Y_TILED:
14554         case I915_FORMAT_MOD_Yf_TILED:
14555                 if (INTEL_INFO(dev)->gen < 9) {
14556                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14557                                   mode_cmd->modifier[0]);
14558                         return -EINVAL;
14559                 }
14560         case DRM_FORMAT_MOD_NONE:
14561         case I915_FORMAT_MOD_X_TILED:
14562                 break;
14563         default:
14564                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14565                           mode_cmd->modifier[0]);
14566                 return -EINVAL;
14567         }
14568
14569         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14570                                                      mode_cmd->pixel_format);
14571         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14572                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14573                           mode_cmd->pitches[0], stride_alignment);
14574                 return -EINVAL;
14575         }
14576
14577         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14578                                            mode_cmd->pixel_format);
14579         if (mode_cmd->pitches[0] > pitch_limit) {
14580                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14581                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14582                           "tiled" : "linear",
14583                           mode_cmd->pitches[0], pitch_limit);
14584                 return -EINVAL;
14585         }
14586
14587         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14588             mode_cmd->pitches[0] != obj->stride) {
14589                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14590                           mode_cmd->pitches[0], obj->stride);
14591                 return -EINVAL;
14592         }
14593
14594         /* Reject formats not supported by any plane early. */
14595         switch (mode_cmd->pixel_format) {
14596         case DRM_FORMAT_C8:
14597         case DRM_FORMAT_RGB565:
14598         case DRM_FORMAT_XRGB8888:
14599         case DRM_FORMAT_ARGB8888:
14600                 break;
14601         case DRM_FORMAT_XRGB1555:
14602                 if (INTEL_INFO(dev)->gen > 3) {
14603                         DRM_DEBUG("unsupported pixel format: %s\n",
14604                                   drm_get_format_name(mode_cmd->pixel_format));
14605                         return -EINVAL;
14606                 }
14607                 break;
14608         case DRM_FORMAT_ABGR8888:
14609                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14610                         DRM_DEBUG("unsupported pixel format: %s\n",
14611                                   drm_get_format_name(mode_cmd->pixel_format));
14612                         return -EINVAL;
14613                 }
14614                 break;
14615         case DRM_FORMAT_XBGR8888:
14616         case DRM_FORMAT_XRGB2101010:
14617         case DRM_FORMAT_XBGR2101010:
14618                 if (INTEL_INFO(dev)->gen < 4) {
14619                         DRM_DEBUG("unsupported pixel format: %s\n",
14620                                   drm_get_format_name(mode_cmd->pixel_format));
14621                         return -EINVAL;
14622                 }
14623                 break;
14624         case DRM_FORMAT_ABGR2101010:
14625                 if (!IS_VALLEYVIEW(dev)) {
14626                         DRM_DEBUG("unsupported pixel format: %s\n",
14627                                   drm_get_format_name(mode_cmd->pixel_format));
14628                         return -EINVAL;
14629                 }
14630                 break;
14631         case DRM_FORMAT_YUYV:
14632         case DRM_FORMAT_UYVY:
14633         case DRM_FORMAT_YVYU:
14634         case DRM_FORMAT_VYUY:
14635                 if (INTEL_INFO(dev)->gen < 5) {
14636                         DRM_DEBUG("unsupported pixel format: %s\n",
14637                                   drm_get_format_name(mode_cmd->pixel_format));
14638                         return -EINVAL;
14639                 }
14640                 break;
14641         default:
14642                 DRM_DEBUG("unsupported pixel format: %s\n",
14643                           drm_get_format_name(mode_cmd->pixel_format));
14644                 return -EINVAL;
14645         }
14646
14647         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14648         if (mode_cmd->offsets[0] != 0)
14649                 return -EINVAL;
14650
14651         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14652                                                mode_cmd->pixel_format,
14653                                                mode_cmd->modifier[0]);
14654         /* FIXME drm helper for size checks (especially planar formats)? */
14655         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14656                 return -EINVAL;
14657
14658         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14659         intel_fb->obj = obj;
14660         intel_fb->obj->framebuffer_references++;
14661
14662         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14663         if (ret) {
14664                 DRM_ERROR("framebuffer init failed %d\n", ret);
14665                 return ret;
14666         }
14667
14668         return 0;
14669 }
14670
14671 static struct drm_framebuffer *
14672 intel_user_framebuffer_create(struct drm_device *dev,
14673                               struct drm_file *filp,
14674                               struct drm_mode_fb_cmd2 *user_mode_cmd)
14675 {
14676         struct drm_framebuffer *fb;
14677         struct drm_i915_gem_object *obj;
14678         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14679
14680         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14681                                                 mode_cmd.handles[0]));
14682         if (&obj->base == NULL)
14683                 return ERR_PTR(-ENOENT);
14684
14685         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14686         if (IS_ERR(fb))
14687                 drm_gem_object_unreference_unlocked(&obj->base);
14688
14689         return fb;
14690 }
14691
14692 #ifndef CONFIG_DRM_FBDEV_EMULATION
14693 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14694 {
14695 }
14696 #endif
14697
14698 static const struct drm_mode_config_funcs intel_mode_funcs = {
14699         .fb_create = intel_user_framebuffer_create,
14700         .output_poll_changed = intel_fbdev_output_poll_changed,
14701         .atomic_check = intel_atomic_check,
14702         .atomic_commit = intel_atomic_commit,
14703         .atomic_state_alloc = intel_atomic_state_alloc,
14704         .atomic_state_clear = intel_atomic_state_clear,
14705 };
14706
14707 /* Set up chip specific display functions */
14708 static void intel_init_display(struct drm_device *dev)
14709 {
14710         struct drm_i915_private *dev_priv = dev->dev_private;
14711
14712         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14713                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14714         else if (IS_CHERRYVIEW(dev))
14715                 dev_priv->display.find_dpll = chv_find_best_dpll;
14716         else if (IS_VALLEYVIEW(dev))
14717                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14718         else if (IS_PINEVIEW(dev))
14719                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14720         else
14721                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14722
14723         if (INTEL_INFO(dev)->gen >= 9) {
14724                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14725                 dev_priv->display.get_initial_plane_config =
14726                         skylake_get_initial_plane_config;
14727                 dev_priv->display.crtc_compute_clock =
14728                         haswell_crtc_compute_clock;
14729                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14730                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14731                 dev_priv->display.update_primary_plane =
14732                         skylake_update_primary_plane;
14733         } else if (HAS_DDI(dev)) {
14734                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14735                 dev_priv->display.get_initial_plane_config =
14736                         ironlake_get_initial_plane_config;
14737                 dev_priv->display.crtc_compute_clock =
14738                         haswell_crtc_compute_clock;
14739                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14740                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14741                 dev_priv->display.update_primary_plane =
14742                         ironlake_update_primary_plane;
14743         } else if (HAS_PCH_SPLIT(dev)) {
14744                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14745                 dev_priv->display.get_initial_plane_config =
14746                         ironlake_get_initial_plane_config;
14747                 dev_priv->display.crtc_compute_clock =
14748                         ironlake_crtc_compute_clock;
14749                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14750                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14751                 dev_priv->display.update_primary_plane =
14752                         ironlake_update_primary_plane;
14753         } else if (IS_VALLEYVIEW(dev)) {
14754                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14755                 dev_priv->display.get_initial_plane_config =
14756                         i9xx_get_initial_plane_config;
14757                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14758                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14759                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14760                 dev_priv->display.update_primary_plane =
14761                         i9xx_update_primary_plane;
14762         } else {
14763                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14764                 dev_priv->display.get_initial_plane_config =
14765                         i9xx_get_initial_plane_config;
14766                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14767                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14768                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14769                 dev_priv->display.update_primary_plane =
14770                         i9xx_update_primary_plane;
14771         }
14772
14773         /* Returns the core display clock speed */
14774         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14775                 dev_priv->display.get_display_clock_speed =
14776                         skylake_get_display_clock_speed;
14777         else if (IS_BROXTON(dev))
14778                 dev_priv->display.get_display_clock_speed =
14779                         broxton_get_display_clock_speed;
14780         else if (IS_BROADWELL(dev))
14781                 dev_priv->display.get_display_clock_speed =
14782                         broadwell_get_display_clock_speed;
14783         else if (IS_HASWELL(dev))
14784                 dev_priv->display.get_display_clock_speed =
14785                         haswell_get_display_clock_speed;
14786         else if (IS_VALLEYVIEW(dev))
14787                 dev_priv->display.get_display_clock_speed =
14788                         valleyview_get_display_clock_speed;
14789         else if (IS_GEN5(dev))
14790                 dev_priv->display.get_display_clock_speed =
14791                         ilk_get_display_clock_speed;
14792         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14793                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14794                 dev_priv->display.get_display_clock_speed =
14795                         i945_get_display_clock_speed;
14796         else if (IS_GM45(dev))
14797                 dev_priv->display.get_display_clock_speed =
14798                         gm45_get_display_clock_speed;
14799         else if (IS_CRESTLINE(dev))
14800                 dev_priv->display.get_display_clock_speed =
14801                         i965gm_get_display_clock_speed;
14802         else if (IS_PINEVIEW(dev))
14803                 dev_priv->display.get_display_clock_speed =
14804                         pnv_get_display_clock_speed;
14805         else if (IS_G33(dev) || IS_G4X(dev))
14806                 dev_priv->display.get_display_clock_speed =
14807                         g33_get_display_clock_speed;
14808         else if (IS_I915G(dev))
14809                 dev_priv->display.get_display_clock_speed =
14810                         i915_get_display_clock_speed;
14811         else if (IS_I945GM(dev) || IS_845G(dev))
14812                 dev_priv->display.get_display_clock_speed =
14813                         i9xx_misc_get_display_clock_speed;
14814         else if (IS_PINEVIEW(dev))
14815                 dev_priv->display.get_display_clock_speed =
14816                         pnv_get_display_clock_speed;
14817         else if (IS_I915GM(dev))
14818                 dev_priv->display.get_display_clock_speed =
14819                         i915gm_get_display_clock_speed;
14820         else if (IS_I865G(dev))
14821                 dev_priv->display.get_display_clock_speed =
14822                         i865_get_display_clock_speed;
14823         else if (IS_I85X(dev))
14824                 dev_priv->display.get_display_clock_speed =
14825                         i85x_get_display_clock_speed;
14826         else { /* 830 */
14827                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14828                 dev_priv->display.get_display_clock_speed =
14829                         i830_get_display_clock_speed;
14830         }
14831
14832         if (IS_GEN5(dev)) {
14833                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14834         } else if (IS_GEN6(dev)) {
14835                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14836         } else if (IS_IVYBRIDGE(dev)) {
14837                 /* FIXME: detect B0+ stepping and use auto training */
14838                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14839         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14840                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14841                 if (IS_BROADWELL(dev)) {
14842                         dev_priv->display.modeset_commit_cdclk =
14843                                 broadwell_modeset_commit_cdclk;
14844                         dev_priv->display.modeset_calc_cdclk =
14845                                 broadwell_modeset_calc_cdclk;
14846                 }
14847         } else if (IS_VALLEYVIEW(dev)) {
14848                 dev_priv->display.modeset_commit_cdclk =
14849                         valleyview_modeset_commit_cdclk;
14850                 dev_priv->display.modeset_calc_cdclk =
14851                         valleyview_modeset_calc_cdclk;
14852         } else if (IS_BROXTON(dev)) {
14853                 dev_priv->display.modeset_commit_cdclk =
14854                         broxton_modeset_commit_cdclk;
14855                 dev_priv->display.modeset_calc_cdclk =
14856                         broxton_modeset_calc_cdclk;
14857         }
14858
14859         switch (INTEL_INFO(dev)->gen) {
14860         case 2:
14861                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14862                 break;
14863
14864         case 3:
14865                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14866                 break;
14867
14868         case 4:
14869         case 5:
14870                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14871                 break;
14872
14873         case 6:
14874                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14875                 break;
14876         case 7:
14877         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14878                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14879                 break;
14880         case 9:
14881                 /* Drop through - unsupported since execlist only. */
14882         default:
14883                 /* Default just returns -ENODEV to indicate unsupported */
14884                 dev_priv->display.queue_flip = intel_default_queue_flip;
14885         }
14886
14887         mutex_init(&dev_priv->pps_mutex);
14888 }
14889
14890 /*
14891  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14892  * resume, or other times.  This quirk makes sure that's the case for
14893  * affected systems.
14894  */
14895 static void quirk_pipea_force(struct drm_device *dev)
14896 {
14897         struct drm_i915_private *dev_priv = dev->dev_private;
14898
14899         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14900         DRM_INFO("applying pipe a force quirk\n");
14901 }
14902
14903 static void quirk_pipeb_force(struct drm_device *dev)
14904 {
14905         struct drm_i915_private *dev_priv = dev->dev_private;
14906
14907         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14908         DRM_INFO("applying pipe b force quirk\n");
14909 }
14910
14911 /*
14912  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14913  */
14914 static void quirk_ssc_force_disable(struct drm_device *dev)
14915 {
14916         struct drm_i915_private *dev_priv = dev->dev_private;
14917         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14918         DRM_INFO("applying lvds SSC disable quirk\n");
14919 }
14920
14921 /*
14922  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14923  * brightness value
14924  */
14925 static void quirk_invert_brightness(struct drm_device *dev)
14926 {
14927         struct drm_i915_private *dev_priv = dev->dev_private;
14928         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14929         DRM_INFO("applying inverted panel brightness quirk\n");
14930 }
14931
14932 /* Some VBT's incorrectly indicate no backlight is present */
14933 static void quirk_backlight_present(struct drm_device *dev)
14934 {
14935         struct drm_i915_private *dev_priv = dev->dev_private;
14936         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14937         DRM_INFO("applying backlight present quirk\n");
14938 }
14939
14940 struct intel_quirk {
14941         int device;
14942         int subsystem_vendor;
14943         int subsystem_device;
14944         void (*hook)(struct drm_device *dev);
14945 };
14946
14947 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14948 struct intel_dmi_quirk {
14949         void (*hook)(struct drm_device *dev);
14950         const struct dmi_system_id (*dmi_id_list)[];
14951 };
14952
14953 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14954 {
14955         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14956         return 1;
14957 }
14958
14959 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14960         {
14961                 .dmi_id_list = &(const struct dmi_system_id[]) {
14962                         {
14963                                 .callback = intel_dmi_reverse_brightness,
14964                                 .ident = "NCR Corporation",
14965                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14966                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14967                                 },
14968                         },
14969                         { }  /* terminating entry */
14970                 },
14971                 .hook = quirk_invert_brightness,
14972         },
14973 };
14974
14975 static struct intel_quirk intel_quirks[] = {
14976         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14977         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14978
14979         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14980         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14981
14982         /* 830 needs to leave pipe A & dpll A up */
14983         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14984
14985         /* 830 needs to leave pipe B & dpll B up */
14986         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14987
14988         /* Lenovo U160 cannot use SSC on LVDS */
14989         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14990
14991         /* Sony Vaio Y cannot use SSC on LVDS */
14992         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14993
14994         /* Acer Aspire 5734Z must invert backlight brightness */
14995         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14996
14997         /* Acer/eMachines G725 */
14998         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14999
15000         /* Acer/eMachines e725 */
15001         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15002
15003         /* Acer/Packard Bell NCL20 */
15004         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15005
15006         /* Acer Aspire 4736Z */
15007         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15008
15009         /* Acer Aspire 5336 */
15010         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15011
15012         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15013         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15014
15015         /* Acer C720 Chromebook (Core i3 4005U) */
15016         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15017
15018         /* Apple Macbook 2,1 (Core 2 T7400) */
15019         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15020
15021         /* Apple Macbook 4,1 */
15022         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15023
15024         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15025         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15026
15027         /* HP Chromebook 14 (Celeron 2955U) */
15028         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15029
15030         /* Dell Chromebook 11 */
15031         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15032
15033         /* Dell Chromebook 11 (2015 version) */
15034         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15035 };
15036
15037 static void intel_init_quirks(struct drm_device *dev)
15038 {
15039         struct pci_dev *d = dev->pdev;
15040         int i;
15041
15042         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15043                 struct intel_quirk *q = &intel_quirks[i];
15044
15045                 if (d->device == q->device &&
15046                     (d->subsystem_vendor == q->subsystem_vendor ||
15047                      q->subsystem_vendor == PCI_ANY_ID) &&
15048                     (d->subsystem_device == q->subsystem_device ||
15049                      q->subsystem_device == PCI_ANY_ID))
15050                         q->hook(dev);
15051         }
15052         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15053                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15054                         intel_dmi_quirks[i].hook(dev);
15055         }
15056 }
15057
15058 /* Disable the VGA plane that we never use */
15059 static void i915_disable_vga(struct drm_device *dev)
15060 {
15061         struct drm_i915_private *dev_priv = dev->dev_private;
15062         u8 sr1;
15063         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15064
15065         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15066         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15067         outb(SR01, VGA_SR_INDEX);
15068         sr1 = inb(VGA_SR_DATA);
15069         outb(sr1 | 1<<5, VGA_SR_DATA);
15070         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15071         udelay(300);
15072
15073         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15074         POSTING_READ(vga_reg);
15075 }
15076
15077 void intel_modeset_init_hw(struct drm_device *dev)
15078 {
15079         intel_update_cdclk(dev);
15080         intel_prepare_ddi(dev);
15081         intel_init_clock_gating(dev);
15082         intel_enable_gt_powersave(dev);
15083 }
15084
15085 void intel_modeset_init(struct drm_device *dev)
15086 {
15087         struct drm_i915_private *dev_priv = dev->dev_private;
15088         int sprite, ret;
15089         enum pipe pipe;
15090         struct intel_crtc *crtc;
15091
15092         drm_mode_config_init(dev);
15093
15094         dev->mode_config.min_width = 0;
15095         dev->mode_config.min_height = 0;
15096
15097         dev->mode_config.preferred_depth = 24;
15098         dev->mode_config.prefer_shadow = 1;
15099
15100         dev->mode_config.allow_fb_modifiers = true;
15101
15102         dev->mode_config.funcs = &intel_mode_funcs;
15103
15104         intel_init_quirks(dev);
15105
15106         intel_init_pm(dev);
15107
15108         if (INTEL_INFO(dev)->num_pipes == 0)
15109                 return;
15110
15111         /*
15112          * There may be no VBT; and if the BIOS enabled SSC we can
15113          * just keep using it to avoid unnecessary flicker.  Whereas if the
15114          * BIOS isn't using it, don't assume it will work even if the VBT
15115          * indicates as much.
15116          */
15117         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15118                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15119                                             DREF_SSC1_ENABLE);
15120
15121                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15122                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15123                                      bios_lvds_use_ssc ? "en" : "dis",
15124                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15125                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15126                 }
15127         }
15128
15129         intel_init_display(dev);
15130         intel_init_audio(dev);
15131
15132         if (IS_GEN2(dev)) {
15133                 dev->mode_config.max_width = 2048;
15134                 dev->mode_config.max_height = 2048;
15135         } else if (IS_GEN3(dev)) {
15136                 dev->mode_config.max_width = 4096;
15137                 dev->mode_config.max_height = 4096;
15138         } else {
15139                 dev->mode_config.max_width = 8192;
15140                 dev->mode_config.max_height = 8192;
15141         }
15142
15143         if (IS_845G(dev) || IS_I865G(dev)) {
15144                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15145                 dev->mode_config.cursor_height = 1023;
15146         } else if (IS_GEN2(dev)) {
15147                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15148                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15149         } else {
15150                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15151                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15152         }
15153
15154         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15155
15156         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15157                       INTEL_INFO(dev)->num_pipes,
15158                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15159
15160         for_each_pipe(dev_priv, pipe) {
15161                 intel_crtc_init(dev, pipe);
15162                 for_each_sprite(dev_priv, pipe, sprite) {
15163                         ret = intel_plane_init(dev, pipe, sprite);
15164                         if (ret)
15165                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15166                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15167                 }
15168         }
15169
15170         intel_update_czclk(dev_priv);
15171         intel_update_cdclk(dev);
15172
15173         intel_shared_dpll_init(dev);
15174
15175         /* Just disable it once at startup */
15176         i915_disable_vga(dev);
15177         intel_setup_outputs(dev);
15178
15179         drm_modeset_lock_all(dev);
15180         intel_modeset_setup_hw_state(dev);
15181         drm_modeset_unlock_all(dev);
15182
15183         for_each_intel_crtc(dev, crtc) {
15184                 struct intel_initial_plane_config plane_config = {};
15185
15186                 if (!crtc->active)
15187                         continue;
15188
15189                 /*
15190                  * Note that reserving the BIOS fb up front prevents us
15191                  * from stuffing other stolen allocations like the ring
15192                  * on top.  This prevents some ugliness at boot time, and
15193                  * can even allow for smooth boot transitions if the BIOS
15194                  * fb is large enough for the active pipe configuration.
15195                  */
15196                 dev_priv->display.get_initial_plane_config(crtc,
15197                                                            &plane_config);
15198
15199                 /*
15200                  * If the fb is shared between multiple heads, we'll
15201                  * just get the first one.
15202                  */
15203                 intel_find_initial_plane_obj(crtc, &plane_config);
15204         }
15205 }
15206
15207 static void intel_enable_pipe_a(struct drm_device *dev)
15208 {
15209         struct intel_connector *connector;
15210         struct drm_connector *crt = NULL;
15211         struct intel_load_detect_pipe load_detect_temp;
15212         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15213
15214         /* We can't just switch on the pipe A, we need to set things up with a
15215          * proper mode and output configuration. As a gross hack, enable pipe A
15216          * by enabling the load detect pipe once. */
15217         for_each_intel_connector(dev, connector) {
15218                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15219                         crt = &connector->base;
15220                         break;
15221                 }
15222         }
15223
15224         if (!crt)
15225                 return;
15226
15227         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15228                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15229 }
15230
15231 static bool
15232 intel_check_plane_mapping(struct intel_crtc *crtc)
15233 {
15234         struct drm_device *dev = crtc->base.dev;
15235         struct drm_i915_private *dev_priv = dev->dev_private;
15236         u32 val;
15237
15238         if (INTEL_INFO(dev)->num_pipes == 1)
15239                 return true;
15240
15241         val = I915_READ(DSPCNTR(!crtc->plane));
15242
15243         if ((val & DISPLAY_PLANE_ENABLE) &&
15244             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15245                 return false;
15246
15247         return true;
15248 }
15249
15250 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15251 {
15252         struct drm_device *dev = crtc->base.dev;
15253         struct intel_encoder *encoder;
15254
15255         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15256                 return true;
15257
15258         return false;
15259 }
15260
15261 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15262 {
15263         struct drm_device *dev = crtc->base.dev;
15264         struct drm_i915_private *dev_priv = dev->dev_private;
15265         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15266
15267         /* Clear any frame start delays used for debugging left by the BIOS */
15268         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15269
15270         /* restore vblank interrupts to correct state */
15271         drm_crtc_vblank_reset(&crtc->base);
15272         if (crtc->active) {
15273                 struct intel_plane *plane;
15274
15275                 drm_crtc_vblank_on(&crtc->base);
15276
15277                 /* Disable everything but the primary plane */
15278                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15279                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15280                                 continue;
15281
15282                         plane->disable_plane(&plane->base, &crtc->base);
15283                 }
15284         }
15285
15286         /* We need to sanitize the plane -> pipe mapping first because this will
15287          * disable the crtc (and hence change the state) if it is wrong. Note
15288          * that gen4+ has a fixed plane -> pipe mapping.  */
15289         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15290                 bool plane;
15291
15292                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15293                               crtc->base.base.id);
15294
15295                 /* Pipe has the wrong plane attached and the plane is active.
15296                  * Temporarily change the plane mapping and disable everything
15297                  * ...  */
15298                 plane = crtc->plane;
15299                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15300                 crtc->plane = !plane;
15301                 intel_crtc_disable_noatomic(&crtc->base);
15302                 crtc->plane = plane;
15303         }
15304
15305         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15306             crtc->pipe == PIPE_A && !crtc->active) {
15307                 /* BIOS forgot to enable pipe A, this mostly happens after
15308                  * resume. Force-enable the pipe to fix this, the update_dpms
15309                  * call below we restore the pipe to the right state, but leave
15310                  * the required bits on. */
15311                 intel_enable_pipe_a(dev);
15312         }
15313
15314         /* Adjust the state of the output pipe according to whether we
15315          * have active connectors/encoders. */
15316         if (!intel_crtc_has_encoders(crtc))
15317                 intel_crtc_disable_noatomic(&crtc->base);
15318
15319         if (crtc->active != crtc->base.state->active) {
15320                 struct intel_encoder *encoder;
15321
15322                 /* This can happen either due to bugs in the get_hw_state
15323                  * functions or because of calls to intel_crtc_disable_noatomic,
15324                  * or because the pipe is force-enabled due to the
15325                  * pipe A quirk. */
15326                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15327                               crtc->base.base.id,
15328                               crtc->base.state->enable ? "enabled" : "disabled",
15329                               crtc->active ? "enabled" : "disabled");
15330
15331                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15332                 crtc->base.state->active = crtc->active;
15333                 crtc->base.enabled = crtc->active;
15334
15335                 /* Because we only establish the connector -> encoder ->
15336                  * crtc links if something is active, this means the
15337                  * crtc is now deactivated. Break the links. connector
15338                  * -> encoder links are only establish when things are
15339                  *  actually up, hence no need to break them. */
15340                 WARN_ON(crtc->active);
15341
15342                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15343                         encoder->base.crtc = NULL;
15344         }
15345
15346         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15347                 /*
15348                  * We start out with underrun reporting disabled to avoid races.
15349                  * For correct bookkeeping mark this on active crtcs.
15350                  *
15351                  * Also on gmch platforms we dont have any hardware bits to
15352                  * disable the underrun reporting. Which means we need to start
15353                  * out with underrun reporting disabled also on inactive pipes,
15354                  * since otherwise we'll complain about the garbage we read when
15355                  * e.g. coming up after runtime pm.
15356                  *
15357                  * No protection against concurrent access is required - at
15358                  * worst a fifo underrun happens which also sets this to false.
15359                  */
15360                 crtc->cpu_fifo_underrun_disabled = true;
15361                 crtc->pch_fifo_underrun_disabled = true;
15362         }
15363 }
15364
15365 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15366 {
15367         struct intel_connector *connector;
15368         struct drm_device *dev = encoder->base.dev;
15369         bool active = false;
15370
15371         /* We need to check both for a crtc link (meaning that the
15372          * encoder is active and trying to read from a pipe) and the
15373          * pipe itself being active. */
15374         bool has_active_crtc = encoder->base.crtc &&
15375                 to_intel_crtc(encoder->base.crtc)->active;
15376
15377         for_each_intel_connector(dev, connector) {
15378                 if (connector->base.encoder != &encoder->base)
15379                         continue;
15380
15381                 active = true;
15382                 break;
15383         }
15384
15385         if (active && !has_active_crtc) {
15386                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15387                               encoder->base.base.id,
15388                               encoder->base.name);
15389
15390                 /* Connector is active, but has no active pipe. This is
15391                  * fallout from our resume register restoring. Disable
15392                  * the encoder manually again. */
15393                 if (encoder->base.crtc) {
15394                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15395                                       encoder->base.base.id,
15396                                       encoder->base.name);
15397                         encoder->disable(encoder);
15398                         if (encoder->post_disable)
15399                                 encoder->post_disable(encoder);
15400                 }
15401                 encoder->base.crtc = NULL;
15402
15403                 /* Inconsistent output/port/pipe state happens presumably due to
15404                  * a bug in one of the get_hw_state functions. Or someplace else
15405                  * in our code, like the register restore mess on resume. Clamp
15406                  * things to off as a safer default. */
15407                 for_each_intel_connector(dev, connector) {
15408                         if (connector->encoder != encoder)
15409                                 continue;
15410                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15411                         connector->base.encoder = NULL;
15412                 }
15413         }
15414         /* Enabled encoders without active connectors will be fixed in
15415          * the crtc fixup. */
15416 }
15417
15418 void i915_redisable_vga_power_on(struct drm_device *dev)
15419 {
15420         struct drm_i915_private *dev_priv = dev->dev_private;
15421         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15422
15423         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15424                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15425                 i915_disable_vga(dev);
15426         }
15427 }
15428
15429 void i915_redisable_vga(struct drm_device *dev)
15430 {
15431         struct drm_i915_private *dev_priv = dev->dev_private;
15432
15433         /* This function can be called both from intel_modeset_setup_hw_state or
15434          * at a very early point in our resume sequence, where the power well
15435          * structures are not yet restored. Since this function is at a very
15436          * paranoid "someone might have enabled VGA while we were not looking"
15437          * level, just check if the power well is enabled instead of trying to
15438          * follow the "don't touch the power well if we don't need it" policy
15439          * the rest of the driver uses. */
15440         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15441                 return;
15442
15443         i915_redisable_vga_power_on(dev);
15444 }
15445
15446 static bool primary_get_hw_state(struct intel_plane *plane)
15447 {
15448         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15449
15450         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15451 }
15452
15453 /* FIXME read out full plane state for all planes */
15454 static void readout_plane_state(struct intel_crtc *crtc)
15455 {
15456         struct drm_plane *primary = crtc->base.primary;
15457         struct intel_plane_state *plane_state =
15458                 to_intel_plane_state(primary->state);
15459
15460         plane_state->visible = crtc->active &&
15461                 primary_get_hw_state(to_intel_plane(primary));
15462
15463         if (plane_state->visible)
15464                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15465 }
15466
15467 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15468 {
15469         struct drm_i915_private *dev_priv = dev->dev_private;
15470         enum pipe pipe;
15471         struct intel_crtc *crtc;
15472         struct intel_encoder *encoder;
15473         struct intel_connector *connector;
15474         int i;
15475
15476         for_each_intel_crtc(dev, crtc) {
15477                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15478                 memset(crtc->config, 0, sizeof(*crtc->config));
15479                 crtc->config->base.crtc = &crtc->base;
15480
15481                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15482                                                                  crtc->config);
15483
15484                 crtc->base.state->active = crtc->active;
15485                 crtc->base.enabled = crtc->active;
15486
15487                 readout_plane_state(crtc);
15488
15489                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15490                               crtc->base.base.id,
15491                               crtc->active ? "enabled" : "disabled");
15492         }
15493
15494         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15495                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15496
15497                 pll->on = pll->get_hw_state(dev_priv, pll,
15498                                             &pll->config.hw_state);
15499                 pll->active = 0;
15500                 pll->config.crtc_mask = 0;
15501                 for_each_intel_crtc(dev, crtc) {
15502                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15503                                 pll->active++;
15504                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15505                         }
15506                 }
15507
15508                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15509                               pll->name, pll->config.crtc_mask, pll->on);
15510
15511                 if (pll->config.crtc_mask)
15512                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15513         }
15514
15515         for_each_intel_encoder(dev, encoder) {
15516                 pipe = 0;
15517
15518                 if (encoder->get_hw_state(encoder, &pipe)) {
15519                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15520                         encoder->base.crtc = &crtc->base;
15521                         encoder->get_config(encoder, crtc->config);
15522                 } else {
15523                         encoder->base.crtc = NULL;
15524                 }
15525
15526                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15527                               encoder->base.base.id,
15528                               encoder->base.name,
15529                               encoder->base.crtc ? "enabled" : "disabled",
15530                               pipe_name(pipe));
15531         }
15532
15533         for_each_intel_connector(dev, connector) {
15534                 if (connector->get_hw_state(connector)) {
15535                         connector->base.dpms = DRM_MODE_DPMS_ON;
15536                         connector->base.encoder = &connector->encoder->base;
15537                 } else {
15538                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15539                         connector->base.encoder = NULL;
15540                 }
15541                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15542                               connector->base.base.id,
15543                               connector->base.name,
15544                               connector->base.encoder ? "enabled" : "disabled");
15545         }
15546
15547         for_each_intel_crtc(dev, crtc) {
15548                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15549
15550                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15551                 if (crtc->base.state->active) {
15552                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15553                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15554                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15555
15556                         /*
15557                          * The initial mode needs to be set in order to keep
15558                          * the atomic core happy. It wants a valid mode if the
15559                          * crtc's enabled, so we do the above call.
15560                          *
15561                          * At this point some state updated by the connectors
15562                          * in their ->detect() callback has not run yet, so
15563                          * no recalculation can be done yet.
15564                          *
15565                          * Even if we could do a recalculation and modeset
15566                          * right now it would cause a double modeset if
15567                          * fbdev or userspace chooses a different initial mode.
15568                          *
15569                          * If that happens, someone indicated they wanted a
15570                          * mode change, which means it's safe to do a full
15571                          * recalculation.
15572                          */
15573                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15574
15575                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15576                         update_scanline_offset(crtc);
15577                 }
15578         }
15579 }
15580
15581 /* Scan out the current hw modeset state,
15582  * and sanitizes it to the current state
15583  */
15584 static void
15585 intel_modeset_setup_hw_state(struct drm_device *dev)
15586 {
15587         struct drm_i915_private *dev_priv = dev->dev_private;
15588         enum pipe pipe;
15589         struct intel_crtc *crtc;
15590         struct intel_encoder *encoder;
15591         int i;
15592
15593         intel_modeset_readout_hw_state(dev);
15594
15595         /* HW state is read out, now we need to sanitize this mess. */
15596         for_each_intel_encoder(dev, encoder) {
15597                 intel_sanitize_encoder(encoder);
15598         }
15599
15600         for_each_pipe(dev_priv, pipe) {
15601                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15602                 intel_sanitize_crtc(crtc);
15603                 intel_dump_pipe_config(crtc, crtc->config,
15604                                        "[setup_hw_state]");
15605         }
15606
15607         intel_modeset_update_connector_atomic_state(dev);
15608
15609         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15610                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15611
15612                 if (!pll->on || pll->active)
15613                         continue;
15614
15615                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15616
15617                 pll->disable(dev_priv, pll);
15618                 pll->on = false;
15619         }
15620
15621         if (IS_VALLEYVIEW(dev))
15622                 vlv_wm_get_hw_state(dev);
15623         else if (IS_GEN9(dev))
15624                 skl_wm_get_hw_state(dev);
15625         else if (HAS_PCH_SPLIT(dev))
15626                 ilk_wm_get_hw_state(dev);
15627
15628         for_each_intel_crtc(dev, crtc) {
15629                 unsigned long put_domains;
15630
15631                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15632                 if (WARN_ON(put_domains))
15633                         modeset_put_power_domains(dev_priv, put_domains);
15634         }
15635         intel_display_set_init_power(dev_priv, false);
15636 }
15637
15638 void intel_display_resume(struct drm_device *dev)
15639 {
15640         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15641         struct intel_connector *conn;
15642         struct intel_plane *plane;
15643         struct drm_crtc *crtc;
15644         int ret;
15645
15646         if (!state)
15647                 return;
15648
15649         state->acquire_ctx = dev->mode_config.acquire_ctx;
15650
15651         /* preserve complete old state, including dpll */
15652         intel_atomic_get_shared_dpll_state(state);
15653
15654         for_each_crtc(dev, crtc) {
15655                 struct drm_crtc_state *crtc_state =
15656                         drm_atomic_get_crtc_state(state, crtc);
15657
15658                 ret = PTR_ERR_OR_ZERO(crtc_state);
15659                 if (ret)
15660                         goto err;
15661
15662                 /* force a restore */
15663                 crtc_state->mode_changed = true;
15664         }
15665
15666         for_each_intel_plane(dev, plane) {
15667                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15668                 if (ret)
15669                         goto err;
15670         }
15671
15672         for_each_intel_connector(dev, conn) {
15673                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15674                 if (ret)
15675                         goto err;
15676         }
15677
15678         intel_modeset_setup_hw_state(dev);
15679
15680         i915_redisable_vga(dev);
15681         ret = drm_atomic_commit(state);
15682         if (!ret)
15683                 return;
15684
15685 err:
15686         DRM_ERROR("Restoring old state failed with %i\n", ret);
15687         drm_atomic_state_free(state);
15688 }
15689
15690 void intel_modeset_gem_init(struct drm_device *dev)
15691 {
15692         struct drm_crtc *c;
15693         struct drm_i915_gem_object *obj;
15694         int ret;
15695
15696         mutex_lock(&dev->struct_mutex);
15697         intel_init_gt_powersave(dev);
15698         mutex_unlock(&dev->struct_mutex);
15699
15700         intel_modeset_init_hw(dev);
15701
15702         intel_setup_overlay(dev);
15703
15704         /*
15705          * Make sure any fbs we allocated at startup are properly
15706          * pinned & fenced.  When we do the allocation it's too early
15707          * for this.
15708          */
15709         for_each_crtc(dev, c) {
15710                 obj = intel_fb_obj(c->primary->fb);
15711                 if (obj == NULL)
15712                         continue;
15713
15714                 mutex_lock(&dev->struct_mutex);
15715                 ret = intel_pin_and_fence_fb_obj(c->primary,
15716                                                  c->primary->fb,
15717                                                  c->primary->state);
15718                 mutex_unlock(&dev->struct_mutex);
15719                 if (ret) {
15720                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15721                                   to_intel_crtc(c)->pipe);
15722                         drm_framebuffer_unreference(c->primary->fb);
15723                         c->primary->fb = NULL;
15724                         c->primary->crtc = c->primary->state->crtc = NULL;
15725                         update_state_fb(c->primary);
15726                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15727                 }
15728         }
15729
15730         intel_backlight_register(dev);
15731 }
15732
15733 void intel_connector_unregister(struct intel_connector *intel_connector)
15734 {
15735         struct drm_connector *connector = &intel_connector->base;
15736
15737         intel_panel_destroy_backlight(connector);
15738         drm_connector_unregister(connector);
15739 }
15740
15741 void intel_modeset_cleanup(struct drm_device *dev)
15742 {
15743         struct drm_i915_private *dev_priv = dev->dev_private;
15744         struct drm_connector *connector;
15745
15746         intel_disable_gt_powersave(dev);
15747
15748         intel_backlight_unregister(dev);
15749
15750         /*
15751          * Interrupts and polling as the first thing to avoid creating havoc.
15752          * Too much stuff here (turning of connectors, ...) would
15753          * experience fancy races otherwise.
15754          */
15755         intel_irq_uninstall(dev_priv);
15756
15757         /*
15758          * Due to the hpd irq storm handling the hotplug work can re-arm the
15759          * poll handlers. Hence disable polling after hpd handling is shut down.
15760          */
15761         drm_kms_helper_poll_fini(dev);
15762
15763         intel_unregister_dsm_handler();
15764
15765         intel_fbc_disable(dev_priv);
15766
15767         /* flush any delayed tasks or pending work */
15768         flush_scheduled_work();
15769
15770         /* destroy the backlight and sysfs files before encoders/connectors */
15771         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15772                 struct intel_connector *intel_connector;
15773
15774                 intel_connector = to_intel_connector(connector);
15775                 intel_connector->unregister(intel_connector);
15776         }
15777
15778         drm_mode_config_cleanup(dev);
15779
15780         intel_cleanup_overlay(dev);
15781
15782         mutex_lock(&dev->struct_mutex);
15783         intel_cleanup_gt_powersave(dev);
15784         mutex_unlock(&dev->struct_mutex);
15785 }
15786
15787 /*
15788  * Return which encoder is currently attached for connector.
15789  */
15790 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15791 {
15792         return &intel_attached_encoder(connector)->base;
15793 }
15794
15795 void intel_connector_attach_encoder(struct intel_connector *connector,
15796                                     struct intel_encoder *encoder)
15797 {
15798         connector->encoder = encoder;
15799         drm_mode_connector_attach_encoder(&connector->base,
15800                                           &encoder->base);
15801 }
15802
15803 /*
15804  * set vga decode state - true == enable VGA decode
15805  */
15806 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15807 {
15808         struct drm_i915_private *dev_priv = dev->dev_private;
15809         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15810         u16 gmch_ctrl;
15811
15812         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15813                 DRM_ERROR("failed to read control word\n");
15814                 return -EIO;
15815         }
15816
15817         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15818                 return 0;
15819
15820         if (state)
15821                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15822         else
15823                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15824
15825         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15826                 DRM_ERROR("failed to write control word\n");
15827                 return -EIO;
15828         }
15829
15830         return 0;
15831 }
15832
15833 struct intel_display_error_state {
15834
15835         u32 power_well_driver;
15836
15837         int num_transcoders;
15838
15839         struct intel_cursor_error_state {
15840                 u32 control;
15841                 u32 position;
15842                 u32 base;
15843                 u32 size;
15844         } cursor[I915_MAX_PIPES];
15845
15846         struct intel_pipe_error_state {
15847                 bool power_domain_on;
15848                 u32 source;
15849                 u32 stat;
15850         } pipe[I915_MAX_PIPES];
15851
15852         struct intel_plane_error_state {
15853                 u32 control;
15854                 u32 stride;
15855                 u32 size;
15856                 u32 pos;
15857                 u32 addr;
15858                 u32 surface;
15859                 u32 tile_offset;
15860         } plane[I915_MAX_PIPES];
15861
15862         struct intel_transcoder_error_state {
15863                 bool power_domain_on;
15864                 enum transcoder cpu_transcoder;
15865
15866                 u32 conf;
15867
15868                 u32 htotal;
15869                 u32 hblank;
15870                 u32 hsync;
15871                 u32 vtotal;
15872                 u32 vblank;
15873                 u32 vsync;
15874         } transcoder[4];
15875 };
15876
15877 struct intel_display_error_state *
15878 intel_display_capture_error_state(struct drm_device *dev)
15879 {
15880         struct drm_i915_private *dev_priv = dev->dev_private;
15881         struct intel_display_error_state *error;
15882         int transcoders[] = {
15883                 TRANSCODER_A,
15884                 TRANSCODER_B,
15885                 TRANSCODER_C,
15886                 TRANSCODER_EDP,
15887         };
15888         int i;
15889
15890         if (INTEL_INFO(dev)->num_pipes == 0)
15891                 return NULL;
15892
15893         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15894         if (error == NULL)
15895                 return NULL;
15896
15897         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15898                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15899
15900         for_each_pipe(dev_priv, i) {
15901                 error->pipe[i].power_domain_on =
15902                         __intel_display_power_is_enabled(dev_priv,
15903                                                          POWER_DOMAIN_PIPE(i));
15904                 if (!error->pipe[i].power_domain_on)
15905                         continue;
15906
15907                 error->cursor[i].control = I915_READ(CURCNTR(i));
15908                 error->cursor[i].position = I915_READ(CURPOS(i));
15909                 error->cursor[i].base = I915_READ(CURBASE(i));
15910
15911                 error->plane[i].control = I915_READ(DSPCNTR(i));
15912                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15913                 if (INTEL_INFO(dev)->gen <= 3) {
15914                         error->plane[i].size = I915_READ(DSPSIZE(i));
15915                         error->plane[i].pos = I915_READ(DSPPOS(i));
15916                 }
15917                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15918                         error->plane[i].addr = I915_READ(DSPADDR(i));
15919                 if (INTEL_INFO(dev)->gen >= 4) {
15920                         error->plane[i].surface = I915_READ(DSPSURF(i));
15921                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15922                 }
15923
15924                 error->pipe[i].source = I915_READ(PIPESRC(i));
15925
15926                 if (HAS_GMCH_DISPLAY(dev))
15927                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15928         }
15929
15930         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15931         if (HAS_DDI(dev_priv->dev))
15932                 error->num_transcoders++; /* Account for eDP. */
15933
15934         for (i = 0; i < error->num_transcoders; i++) {
15935                 enum transcoder cpu_transcoder = transcoders[i];
15936
15937                 error->transcoder[i].power_domain_on =
15938                         __intel_display_power_is_enabled(dev_priv,
15939                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15940                 if (!error->transcoder[i].power_domain_on)
15941                         continue;
15942
15943                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15944
15945                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15946                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15947                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15948                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15949                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15950                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15951                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15952         }
15953
15954         return error;
15955 }
15956
15957 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15958
15959 void
15960 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15961                                 struct drm_device *dev,
15962                                 struct intel_display_error_state *error)
15963 {
15964         struct drm_i915_private *dev_priv = dev->dev_private;
15965         int i;
15966
15967         if (!error)
15968                 return;
15969
15970         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15971         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15972                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15973                            error->power_well_driver);
15974         for_each_pipe(dev_priv, i) {
15975                 err_printf(m, "Pipe [%d]:\n", i);
15976                 err_printf(m, "  Power: %s\n",
15977                            error->pipe[i].power_domain_on ? "on" : "off");
15978                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15979                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15980
15981                 err_printf(m, "Plane [%d]:\n", i);
15982                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15983                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15984                 if (INTEL_INFO(dev)->gen <= 3) {
15985                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15986                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15987                 }
15988                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15989                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15990                 if (INTEL_INFO(dev)->gen >= 4) {
15991                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15992                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15993                 }
15994
15995                 err_printf(m, "Cursor [%d]:\n", i);
15996                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15997                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15998                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15999         }
16000
16001         for (i = 0; i < error->num_transcoders; i++) {
16002                 err_printf(m, "CPU transcoder: %c\n",
16003                            transcoder_name(error->transcoder[i].cpu_transcoder));
16004                 err_printf(m, "  Power: %s\n",
16005                            error->transcoder[i].power_domain_on ? "on" : "off");
16006                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16007                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16008                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16009                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16010                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16011                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16012                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16013         }
16014 }
16015
16016 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16017 {
16018         struct intel_crtc *crtc;
16019
16020         for_each_intel_crtc(dev, crtc) {
16021                 struct intel_unpin_work *work;
16022
16023                 spin_lock_irq(&dev->event_lock);
16024
16025                 work = crtc->unpin_work;
16026
16027                 if (work && work->event &&
16028                     work->event->base.file_priv == file) {
16029                         kfree(work->event);
16030                         work->event = NULL;
16031                 }
16032
16033                 spin_unlock_irq(&dev->event_lock);
16034         }
16035 }