drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include "drmP.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "drm_dp_helper.h"
  40
  41 #include "drm_crtc_helper.h"
  42
  43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  44
  45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  46 static void intel_update_watermarks(struct drm_device *dev);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51     /* given values */
  52     int n;
  53     int m1, m2;
  54     int p1, p2;
  55     /* derived values */
  56     int dot;
  57     int vco;
  58     int m;
  59     int p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63     int min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67     int dot_limit;
  68     int p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75     intel_p2_t      p2;
  76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                       int, int, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *best_clock);
  86 static bool
  87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  88                         int target, int refclk, intel_clock_t *best_clock);
  89
  90 static bool
  91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  92                       int target, int refclk, intel_clock_t *best_clock);
  93 static bool
  94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                            int target, int refclk, intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2,.max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2,.max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 359                                                 int refclk)
 360 {
 361         struct drm_device *dev = crtc->dev;
 362         struct drm_i915_private *dev_priv = dev->dev_private;
 363         const intel_limit_t *limit;
 364
 365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 367                     LVDS_CLKB_POWER_UP) {
 368                         /* LVDS dual channel */
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_dual_lvds;
 373                 } else {
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_single_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_single_lvds;
 378                 }
 379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 380                         HAS_eDP)
 381                 limit = &intel_limits_ironlake_display_port;
 382         else
 383                 limit = &intel_limits_ironlake_dac;
 384
 385         return limit;
 386 }
 387
 388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 389 {
 390         struct drm_device *dev = crtc->dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         const intel_limit_t *limit;
 393
 394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 396                     LVDS_CLKB_POWER_UP)
 397                         /* LVDS with dual channel */
 398                         limit = &intel_limits_g4x_dual_channel_lvds;
 399                 else
 400                         /* LVDS with dual channel */
 401                         limit = &intel_limits_g4x_single_channel_lvds;
 402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 404                 limit = &intel_limits_g4x_hdmi;
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 406                 limit = &intel_limits_g4x_sdvo;
 407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 408                 limit = &intel_limits_g4x_display_port;
 409         } else /* The option is for other outputs */
 410                 limit = &intel_limits_i9xx_sdvo;
 411
 412         return limit;
 413 }
 414
 415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 416 {
 417         struct drm_device *dev = crtc->dev;
 418         const intel_limit_t *limit;
 419
 420         if (HAS_PCH_SPLIT(dev))
 421                 limit = intel_ironlake_limit(crtc, refclk);
 422         else if (IS_G4X(dev)) {
 423                 limit = intel_g4x_limit(crtc);
 424         } else if (IS_PINEVIEW(dev)) {
 425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 426                         limit = &intel_limits_pineview_lvds;
 427                 else
 428                         limit = &intel_limits_pineview_sdvo;
 429         } else if (!IS_GEN2(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_i9xx_lvds;
 432                 else
 433                         limit = &intel_limits_i9xx_sdvo;
 434         } else {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i8xx_lvds;
 437                 else
 438                         limit = &intel_limits_i8xx_dvo;
 439         }
 440         return limit;
 441 }
 442
 443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 444 static void pineview_clock(int refclk, intel_clock_t *clock)
 445 {
 446         clock->m = clock->m2 + 2;
 447         clock->p = clock->p1 * clock->p2;
 448         clock->vco = refclk * clock->m / clock->n;
 449         clock->dot = clock->vco / clock->p;
 450 }
 451
 452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 453 {
 454         if (IS_PINEVIEW(dev)) {
 455                 pineview_clock(refclk, clock);
 456                 return;
 457         }
 458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 459         clock->p = clock->p1 * clock->p2;
 460         clock->vco = refclk * clock->m / (clock->n + 2);
 461         clock->dot = clock->vco / clock->p;
 462 }
 463
 464 /**
 465  * Returns whether any output on the specified pipe is of the specified type
 466  */
 467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_mode_config *mode_config = &dev->mode_config;
 471         struct intel_encoder *encoder;
 472
 473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 474                 if (encoder->base.crtc == crtc && encoder->type == type)
 475                         return true;
 476
 477         return false;
 478 }
 479
 480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 481 /**
 482  * Returns whether the given set of divisors are valid for a given refclk with
 483  * the given connectors.
 484  */
 485
 486 static bool intel_PLL_is_valid(struct drm_device *dev,
 487                                const intel_limit_t *limit,
 488                                const intel_clock_t *clock)
 489 {
 490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 491                 INTELPllInvalid ("p1 out of range\n");
 492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 493                 INTELPllInvalid ("p out of range\n");
 494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 495                 INTELPllInvalid ("m2 out of range\n");
 496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 497                 INTELPllInvalid ("m1 out of range\n");
 498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 499                 INTELPllInvalid ("m1 <= m2\n");
 500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 501                 INTELPllInvalid ("m out of range\n");
 502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 503                 INTELPllInvalid ("n out of range\n");
 504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 505                 INTELPllInvalid ("vco out of range\n");
 506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 507          * connector, etc., rather than just a single range.
 508          */
 509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 510                 INTELPllInvalid ("dot out of range\n");
 511
 512         return true;
 513 }
 514
 515 static bool
 516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 517                     int target, int refclk, intel_clock_t *best_clock)
 518
 519 {
 520         struct drm_device *dev = crtc->dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         intel_clock_t clock;
 523         int err = target;
 524
 525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 526             (I915_READ(LVDS)) != 0) {
 527                 /*
 528                  * For LVDS, if the panel is on, just rely on its current
 529                  * settings for dual-channel.  We haven't figured out how to
 530                  * reliably set up different single/dual channel state, if we
 531                  * even can.
 532                  */
 533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 534                     LVDS_CLKB_POWER_UP)
 535                         clock.p2 = limit->p2.p2_fast;
 536                 else
 537                         clock.p2 = limit->p2.p2_slow;
 538         } else {
 539                 if (target < limit->p2.dot_limit)
 540                         clock.p2 = limit->p2.p2_slow;
 541                 else
 542                         clock.p2 = limit->p2.p2_fast;
 543         }
 544
 545         memset (best_clock, 0, sizeof (*best_clock));
 546
 547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 548              clock.m1++) {
 549                 for (clock.m2 = limit->m2.min;
 550                      clock.m2 <= limit->m2.max; clock.m2++) {
 551                         /* m1 is always 0 in Pineview */
 552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 553                                 break;
 554                         for (clock.n = limit->n.min;
 555                              clock.n <= limit->n.max; clock.n++) {
 556                                 for (clock.p1 = limit->p1.min;
 557                                         clock.p1 <= limit->p1.max; clock.p1++) {
 558                                         int this_err;
 559
 560                                         intel_clock(dev, refclk, &clock);
 561                                         if (!intel_PLL_is_valid(dev, limit,
 562                                                                 &clock))
 563                                                 continue;
 564
 565                                         this_err = abs(clock.dot - target);
 566                                         if (this_err < err) {
 567                                                 *best_clock = clock;
 568                                                 err = this_err;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573         }
 574
 575         return (err != target);
 576 }
 577
 578 static bool
 579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                         int target, int refclk, intel_clock_t *best_clock)
 581 {
 582         struct drm_device *dev = crtc->dev;
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         intel_clock_t clock;
 585         int max_n;
 586         bool found;
 587         /* approximately equals target * 0.00585 */
 588         int err_most = (target >> 8) + (target >> 9);
 589         found = false;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 int lvds_reg;
 593
 594                 if (HAS_PCH_SPLIT(dev))
 595                         lvds_reg = PCH_LVDS;
 596                 else
 597                         lvds_reg = LVDS;
 598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 599                     LVDS_CLKB_POWER_UP)
 600                         clock.p2 = limit->p2.p2_fast;
 601                 else
 602                         clock.p2 = limit->p2.p2_slow;
 603         } else {
 604                 if (target < limit->p2.dot_limit)
 605                         clock.p2 = limit->p2.p2_slow;
 606                 else
 607                         clock.p2 = limit->p2.p2_fast;
 608         }
 609
 610         memset(best_clock, 0, sizeof(*best_clock));
 611         max_n = limit->n.max;
 612         /* based on hardware requirement, prefer smaller n to precision */
 613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 614                 /* based on hardware requirement, prefere larger m1,m2 */
 615                 for (clock.m1 = limit->m1.max;
 616                      clock.m1 >= limit->m1.min; clock.m1--) {
 617                         for (clock.m2 = limit->m2.max;
 618                              clock.m2 >= limit->m2.min; clock.m2--) {
 619                                 for (clock.p1 = limit->p1.max;
 620                                      clock.p1 >= limit->p1.min; clock.p1--) {
 621                                         int this_err;
 622
 623                                         intel_clock(dev, refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err_most) {
 630                                                 *best_clock = clock;
 631                                                 err_most = this_err;
 632                                                 max_n = clock.n;
 633                                                 found = true;
 634                                         }
 635                                 }
 636                         }
 637                 }
 638         }
 639         return found;
 640 }
 641
 642 static bool
 643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 644                            int target, int refclk, intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         intel_clock_t clock;
 648
 649         if (target < 200000) {
 650                 clock.n = 1;
 651                 clock.p1 = 2;
 652                 clock.p2 = 10;
 653                 clock.m1 = 12;
 654                 clock.m2 = 9;
 655         } else {
 656                 clock.n = 2;
 657                 clock.p1 = 1;
 658                 clock.p2 = 10;
 659                 clock.m1 = 14;
 660                 clock.m2 = 8;
 661         }
 662         intel_clock(dev, refclk, &clock);
 663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 664         return true;
 665 }
 666
 667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 668 static bool
 669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                       int target, int refclk, intel_clock_t *best_clock)
 671 {
 672         intel_clock_t clock;
 673         if (target < 200000) {
 674                 clock.p1 = 2;
 675                 clock.p2 = 10;
 676                 clock.n = 2;
 677                 clock.m1 = 23;
 678                 clock.m2 = 8;
 679         } else {
 680                 clock.p1 = 1;
 681                 clock.p2 = 10;
 682                 clock.n = 1;
 683                 clock.m1 = 14;
 684                 clock.m2 = 2;
 685         }
 686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 687         clock.p = (clock.p1 * clock.p2);
 688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 689         clock.vco = 0;
 690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 691         return true;
 692 }
 693
 694 /**
 695  * intel_wait_for_vblank - wait for vblank on a given pipe
 696  * @dev: drm device
 697  * @pipe: pipe to wait for
 698  *
 699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 700  * mode setting code.
 701  */
 702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 703 {
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         int pipestat_reg = PIPESTAT(pipe);
 706
 707         /* Clear existing vblank status. Note this will clear any other
 708          * sticky status fields as well.
 709          *
 710          * This races with i915_driver_irq_handler() with the result
 711          * that either function could miss a vblank event.  Here it is not
 712          * fatal, as we will either wait upon the next vblank interrupt or
 713          * timeout.  Generally speaking intel_wait_for_vblank() is only
 714          * called during modeset at which time the GPU should be idle and
 715          * should *not* be performing page flips and thus not waiting on
 716          * vblanks...
 717          * Currently, the result of us stealing a vblank from the irq
 718          * handler is that a single frame will be skipped during swapbuffers.
 719          */
 720         I915_WRITE(pipestat_reg,
 721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 722
 723         /* Wait for vblank interrupt bit to set */
 724         if (wait_for(I915_READ(pipestat_reg) &
 725                      PIPE_VBLANK_INTERRUPT_STATUS,
 726                      50))
 727                 DRM_DEBUG_KMS("vblank wait timed out\n");
 728 }
 729
 730 /*
 731  * intel_wait_for_pipe_off - wait for pipe to turn off
 732  * @dev: drm device
 733  * @pipe: pipe to wait for
 734  *
 735  * After disabling a pipe, we can't wait for vblank in the usual way,
 736  * spinning on the vblank interrupt status bit, since we won't actually
 737  * see an interrupt when the pipe is disabled.
 738  *
 739  * On Gen4 and above:
 740  *   wait for the pipe register state bit to turn off
 741  *
 742  * Otherwise:
 743  *   wait for the display line value to settle (it usually
 744  *   ends up stopping at the start of the next frame).
 745  *
 746  */
 747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750
 751         if (INTEL_INFO(dev)->gen >= 4) {
 752                 int reg = PIPECONF(pipe);
 753
 754                 /* Wait for the Pipe State to go off */
 755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 756                              100))
 757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 758         } else {
 759                 u32 last_line;
 760                 int reg = PIPEDSL(pipe);
 761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 762
 763                 /* Wait for the display line to settle */
 764                 do {
 765                         last_line = I915_READ(reg) & DSL_LINEMASK;
 766                         mdelay(5);
 767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 768                          time_after(timeout, jiffies));
 769                 if (time_after(jiffies, timeout))
 770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 771         }
 772 }
 773
 774 static const char *state_string(bool enabled)
 775 {
 776         return enabled ? "on" : "off";
 777 }
 778
 779 /* Only for pre-ILK configs */
 780 static void assert_pll(struct drm_i915_private *dev_priv,
 781                        enum pipe pipe, bool state)
 782 {
 783         int reg;
 784         u32 val;
 785         bool cur_state;
 786
 787         reg = DPLL(pipe);
 788         val = I915_READ(reg);
 789         cur_state = !!(val & DPLL_VCO_ENABLE);
 790         WARN(cur_state != state,
 791              "PLL state assertion failure (expected %s, current %s)\n",
 792              state_string(state), state_string(cur_state));
 793 }
 794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 796
 797 /* For ILK+ */
 798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 799                            enum pipe pipe, bool state)
 800 {
 801         int reg;
 802         u32 val;
 803         bool cur_state;
 804
 805         reg = PCH_DPLL(pipe);
 806         val = I915_READ(reg);
 807         cur_state = !!(val & DPLL_VCO_ENABLE);
 808         WARN(cur_state != state,
 809              "PCH PLL state assertion failure (expected %s, current %s)\n",
 810              state_string(state), state_string(cur_state));
 811 }
 812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 814
 815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 816                           enum pipe pipe, bool state)
 817 {
 818         int reg;
 819         u32 val;
 820         bool cur_state;
 821
 822         reg = FDI_TX_CTL(pipe);
 823         val = I915_READ(reg);
 824         cur_state = !!(val & FDI_TX_ENABLE);
 825         WARN(cur_state != state,
 826              "FDI TX state assertion failure (expected %s, current %s)\n",
 827              state_string(state), state_string(cur_state));
 828 }
 829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 831
 832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 833                           enum pipe pipe, bool state)
 834 {
 835         int reg;
 836         u32 val;
 837         bool cur_state;
 838
 839         reg = FDI_RX_CTL(pipe);
 840         val = I915_READ(reg);
 841         cur_state = !!(val & FDI_RX_ENABLE);
 842         WARN(cur_state != state,
 843              "FDI RX state assertion failure (expected %s, current %s)\n",
 844              state_string(state), state_string(cur_state));
 845 }
 846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 848
 849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 850                                       enum pipe pipe)
 851 {
 852         int reg;
 853         u32 val;
 854
 855         /* ILK FDI PLL is always enabled */
 856         if (dev_priv->info->gen == 5)
 857                 return;
 858
 859         reg = FDI_TX_CTL(pipe);
 860         val = I915_READ(reg);
 861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 862 }
 863
 864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 865                                       enum pipe pipe)
 866 {
 867         int reg;
 868         u32 val;
 869
 870         reg = FDI_RX_CTL(pipe);
 871         val = I915_READ(reg);
 872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 873 }
 874
 875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 876                                   enum pipe pipe)
 877 {
 878         int pp_reg, lvds_reg;
 879         u32 val;
 880         enum pipe panel_pipe = PIPE_A;
 881         bool locked = locked;
 882
 883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 884                 pp_reg = PCH_PP_CONTROL;
 885                 lvds_reg = PCH_LVDS;
 886         } else {
 887                 pp_reg = PP_CONTROL;
 888                 lvds_reg = LVDS;
 889         }
 890
 891         val = I915_READ(pp_reg);
 892         if (!(val & PANEL_POWER_ON) ||
 893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 894                 locked = false;
 895
 896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 897                 panel_pipe = PIPE_B;
 898
 899         WARN(panel_pipe == pipe && locked,
 900              "panel assertion failure, pipe %c regs locked\n",
 901              pipe_name(pipe));
 902 }
 903
 904 static void assert_pipe(struct drm_i915_private *dev_priv,
 905                         enum pipe pipe, bool state)
 906 {
 907         int reg;
 908         u32 val;
 909         bool cur_state;
 910
 911         reg = PIPECONF(pipe);
 912         val = I915_READ(reg);
 913         cur_state = !!(val & PIPECONF_ENABLE);
 914         WARN(cur_state != state,
 915              "pipe %c assertion failure (expected %s, current %s)\n",
 916              pipe_name(pipe), state_string(state), state_string(cur_state));
 917 }
 918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 920
 921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 922                                  enum plane plane)
 923 {
 924         int reg;
 925         u32 val;
 926
 927         reg = DSPCNTR(plane);
 928         val = I915_READ(reg);
 929         WARN(!(val & DISPLAY_PLANE_ENABLE),
 930              "plane %c assertion failure, should be active but is disabled\n",
 931              plane_name(plane));
 932 }
 933
 934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 935                                    enum pipe pipe)
 936 {
 937         int reg, i;
 938         u32 val;
 939         int cur_pipe;
 940
 941         /* Planes are fixed to pipes on ILK+ */
 942         if (HAS_PCH_SPLIT(dev_priv->dev))
 943                 return;
 944
 945         /* Need to check both planes against the pipe */
 946         for (i = 0; i < 2; i++) {
 947                 reg = DSPCNTR(i);
 948                 val = I915_READ(reg);
 949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 950                         DISPPLANE_SEL_PIPE_SHIFT;
 951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 953                      plane_name(i), pipe_name(pipe));
 954         }
 955 }
 956
 957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 958 {
 959         u32 val;
 960         bool enabled;
 961
 962         val = I915_READ(PCH_DREF_CONTROL);
 963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 964                             DREF_SUPERSPREAD_SOURCE_MASK));
 965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 966 }
 967
 968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 969                                        enum pipe pipe)
 970 {
 971         int reg;
 972         u32 val;
 973         bool enabled;
 974
 975         reg = TRANSCONF(pipe);
 976         val = I915_READ(reg);
 977         enabled = !!(val & TRANS_ENABLE);
 978         WARN(enabled,
 979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 980              pipe_name(pipe));
 981 }
 982
 983 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 984                                    enum pipe pipe, int reg)
 985 {
 986         u32 val = I915_READ(reg);
 987         WARN(DP_PIPE_ENABLED(val, pipe),
 988              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 989              reg, pipe_name(pipe));
 990 }
 991
 992 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 993                                      enum pipe pipe, int reg)
 994 {
 995         u32 val = I915_READ(reg);
 996         WARN(HDMI_PIPE_ENABLED(val, pipe),
 997              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 998              reg, pipe_name(pipe));
 999 }
1000
1001 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011         reg = PCH_ADPA;
1012         val = I915_READ(reg);
1013         WARN(ADPA_PIPE_ENABLED(val, pipe),
1014              "PCH VGA enabled on transcoder %c, should be disabled\n",
1015              pipe_name(pipe));
1016
1017         reg = PCH_LVDS;
1018         val = I915_READ(reg);
1019         WARN(LVDS_PIPE_ENABLED(val, pipe),
1020              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1021              pipe_name(pipe));
1022
1023         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026 }
1027
1028 /**
1029  * intel_enable_pll - enable a PLL
1030  * @dev_priv: i915 private structure
1031  * @pipe: pipe PLL to enable
1032  *
1033  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1034  * make sure the PLL reg is writable first though, since the panel write
1035  * protect mechanism may be enabled.
1036  *
1037  * Note!  This is for pre-ILK only.
1038  */
1039 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040 {
1041         int reg;
1042         u32 val;
1043
1044         /* No really, not for ILK+ */
1045         BUG_ON(dev_priv->info->gen >= 5);
1046
1047         /* PLL is protected by panel, make sure we can write it */
1048         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049                 assert_panel_unlocked(dev_priv, pipe);
1050
1051         reg = DPLL(pipe);
1052         val = I915_READ(reg);
1053         val |= DPLL_VCO_ENABLE;
1054
1055         /* We do this three times for luck */
1056         I915_WRITE(reg, val);
1057         POSTING_READ(reg);
1058         udelay(150); /* wait for warmup */
1059         I915_WRITE(reg, val);
1060         POSTING_READ(reg);
1061         udelay(150); /* wait for warmup */
1062         I915_WRITE(reg, val);
1063         POSTING_READ(reg);
1064         udelay(150); /* wait for warmup */
1065 }
1066
1067 /**
1068  * intel_disable_pll - disable a PLL
1069  * @dev_priv: i915 private structure
1070  * @pipe: pipe PLL to disable
1071  *
1072  * Disable the PLL for @pipe, making sure the pipe is off first.
1073  *
1074  * Note!  This is for pre-ILK only.
1075  */
1076 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077 {
1078         int reg;
1079         u32 val;
1080
1081         /* Don't disable pipe A or pipe A PLLs if needed */
1082         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083                 return;
1084
1085         /* Make sure the pipe isn't still relying on us */
1086         assert_pipe_disabled(dev_priv, pipe);
1087
1088         reg = DPLL(pipe);
1089         val = I915_READ(reg);
1090         val &= ~DPLL_VCO_ENABLE;
1091         I915_WRITE(reg, val);
1092         POSTING_READ(reg);
1093 }
1094
1095 /**
1096  * intel_enable_pch_pll - enable PCH PLL
1097  * @dev_priv: i915 private structure
1098  * @pipe: pipe PLL to enable
1099  *
1100  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101  * drives the transcoder clock.
1102  */
1103 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104                                  enum pipe pipe)
1105 {
1106         int reg;
1107         u32 val;
1108
1109         /* PCH only available on ILK+ */
1110         BUG_ON(dev_priv->info->gen < 5);
1111
1112         /* PCH refclock must be enabled first */
1113         assert_pch_refclk_enabled(dev_priv);
1114
1115         reg = PCH_DPLL(pipe);
1116         val = I915_READ(reg);
1117         val |= DPLL_VCO_ENABLE;
1118         I915_WRITE(reg, val);
1119         POSTING_READ(reg);
1120         udelay(200);
1121 }
1122
1123 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124                                   enum pipe pipe)
1125 {
1126         int reg;
1127         u32 val;
1128
1129         /* PCH only available on ILK+ */
1130         BUG_ON(dev_priv->info->gen < 5);
1131
1132         /* Make sure transcoder isn't still depending on us */
1133         assert_transcoder_disabled(dev_priv, pipe);
1134
1135         reg = PCH_DPLL(pipe);
1136         val = I915_READ(reg);
1137         val &= ~DPLL_VCO_ENABLE;
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(200);
1141 }
1142
1143 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144                                     enum pipe pipe)
1145 {
1146         int reg;
1147         u32 val;
1148
1149         /* PCH only available on ILK+ */
1150         BUG_ON(dev_priv->info->gen < 5);
1151
1152         /* Make sure PCH DPLL is enabled */
1153         assert_pch_pll_enabled(dev_priv, pipe);
1154
1155         /* FDI must be feeding us bits for PCH ports */
1156         assert_fdi_tx_enabled(dev_priv, pipe);
1157         assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159         reg = TRANSCONF(pipe);
1160         val = I915_READ(reg);
1161         /*
1162          * make the BPC in transcoder be consistent with
1163          * that in pipeconf reg.
1164          */
1165         val &= ~PIPE_BPC_MASK;
1166         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1167         I915_WRITE(reg, val | TRANS_ENABLE);
1168         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1169                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1170 }
1171
1172 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1173                                      enum pipe pipe)
1174 {
1175         int reg;
1176         u32 val;
1177
1178         /* FDI relies on the transcoder */
1179         assert_fdi_tx_disabled(dev_priv, pipe);
1180         assert_fdi_rx_disabled(dev_priv, pipe);
1181
1182         /* Ports must be off as well */
1183         assert_pch_ports_disabled(dev_priv, pipe);
1184
1185         reg = TRANSCONF(pipe);
1186         val = I915_READ(reg);
1187         val &= ~TRANS_ENABLE;
1188         I915_WRITE(reg, val);
1189         /* wait for PCH transcoder off, transcoder state */
1190         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1191                 DRM_ERROR("failed to disable transcoder\n");
1192 }
1193
1194 /**
1195  * intel_enable_pipe - enable a pipe, asserting requirements
1196  * @dev_priv: i915 private structure
1197  * @pipe: pipe to enable
1198  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1199  *
1200  * Enable @pipe, making sure that various hardware specific requirements
1201  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1202  *
1203  * @pipe should be %PIPE_A or %PIPE_B.
1204  *
1205  * Will wait until the pipe is actually running (i.e. first vblank) before
1206  * returning.
1207  */
1208 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1209                               bool pch_port)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         /*
1215          * A pipe without a PLL won't actually be able to drive bits from
1216          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1217          * need the check.
1218          */
1219         if (!HAS_PCH_SPLIT(dev_priv->dev))
1220                 assert_pll_enabled(dev_priv, pipe);
1221         else {
1222                 if (pch_port) {
1223                         /* if driving the PCH, we need FDI enabled */
1224                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1225                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1226                 }
1227                 /* FIXME: assert CPU port conditions for SNB+ */
1228         }
1229
1230         reg = PIPECONF(pipe);
1231         val = I915_READ(reg);
1232         if (val & PIPECONF_ENABLE)
1233                 return;
1234
1235         I915_WRITE(reg, val | PIPECONF_ENABLE);
1236         intel_wait_for_vblank(dev_priv->dev, pipe);
1237 }
1238
1239 /**
1240  * intel_disable_pipe - disable a pipe, asserting requirements
1241  * @dev_priv: i915 private structure
1242  * @pipe: pipe to disable
1243  *
1244  * Disable @pipe, making sure that various hardware specific requirements
1245  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1246  *
1247  * @pipe should be %PIPE_A or %PIPE_B.
1248  *
1249  * Will wait until the pipe has shut down before returning.
1250  */
1251 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1252                                enum pipe pipe)
1253 {
1254         int reg;
1255         u32 val;
1256
1257         /*
1258          * Make sure planes won't keep trying to pump pixels to us,
1259          * or we might hang the display.
1260          */
1261         assert_planes_disabled(dev_priv, pipe);
1262
1263         /* Don't disable pipe A or pipe A PLLs if needed */
1264         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1265                 return;
1266
1267         reg = PIPECONF(pipe);
1268         val = I915_READ(reg);
1269         if ((val & PIPECONF_ENABLE) == 0)
1270                 return;
1271
1272         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1273         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1274 }
1275
1276 /**
1277  * intel_enable_plane - enable a display plane on a given pipe
1278  * @dev_priv: i915 private structure
1279  * @plane: plane to enable
1280  * @pipe: pipe being fed
1281  *
1282  * Enable @plane on @pipe, making sure that @pipe is running first.
1283  */
1284 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1285                                enum plane plane, enum pipe pipe)
1286 {
1287         int reg;
1288         u32 val;
1289
1290         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1291         assert_pipe_enabled(dev_priv, pipe);
1292
1293         reg = DSPCNTR(plane);
1294         val = I915_READ(reg);
1295         if (val & DISPLAY_PLANE_ENABLE)
1296                 return;
1297
1298         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1299         intel_wait_for_vblank(dev_priv->dev, pipe);
1300 }
1301
1302 /*
1303  * Plane regs are double buffered, going from enabled->disabled needs a
1304  * trigger in order to latch.  The display address reg provides this.
1305  */
1306 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1307                                       enum plane plane)
1308 {
1309         u32 reg = DSPADDR(plane);
1310         I915_WRITE(reg, I915_READ(reg));
1311 }
1312
1313 /**
1314  * intel_disable_plane - disable a display plane
1315  * @dev_priv: i915 private structure
1316  * @plane: plane to disable
1317  * @pipe: pipe consuming the data
1318  *
1319  * Disable @plane; should be an independent operation.
1320  */
1321 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1322                                 enum plane plane, enum pipe pipe)
1323 {
1324         int reg;
1325         u32 val;
1326
1327         reg = DSPCNTR(plane);
1328         val = I915_READ(reg);
1329         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1330                 return;
1331
1332         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1333         intel_flush_display_plane(dev_priv, plane);
1334         intel_wait_for_vblank(dev_priv->dev, pipe);
1335 }
1336
1337 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1338                            enum pipe pipe, int reg)
1339 {
1340         u32 val = I915_READ(reg);
1341         if (DP_PIPE_ENABLED(val, pipe))
1342                 I915_WRITE(reg, val & ~DP_PORT_EN);
1343 }
1344
1345 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1346                              enum pipe pipe, int reg)
1347 {
1348         u32 val = I915_READ(reg);
1349         if (HDMI_PIPE_ENABLED(val, pipe))
1350                 I915_WRITE(reg, val & ~PORT_ENABLE);
1351 }
1352
1353 /* Disable any ports connected to this transcoder */
1354 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1355                                     enum pipe pipe)
1356 {
1357         u32 reg, val;
1358
1359         val = I915_READ(PCH_PP_CONTROL);
1360         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1361
1362         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1363         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1364         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1365
1366         reg = PCH_ADPA;
1367         val = I915_READ(reg);
1368         if (ADPA_PIPE_ENABLED(val, pipe))
1369                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1370
1371         reg = PCH_LVDS;
1372         val = I915_READ(reg);
1373         if (LVDS_PIPE_ENABLED(val, pipe)) {
1374                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1375                 POSTING_READ(reg);
1376                 udelay(100);
1377         }
1378
1379         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1380         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1381         disable_pch_hdmi(dev_priv, pipe, HDMID);
1382 }
1383
1384 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1385 {
1386         struct drm_device *dev = crtc->dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         struct drm_framebuffer *fb = crtc->fb;
1389         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1390         struct drm_i915_gem_object *obj = intel_fb->obj;
1391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1392         int plane, i;
1393         u32 fbc_ctl, fbc_ctl2;
1394
1395         if (fb->pitch == dev_priv->cfb_pitch &&
1396             obj->fence_reg == dev_priv->cfb_fence &&
1397             intel_crtc->plane == dev_priv->cfb_plane &&
1398             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1399                 return;
1400
1401         i8xx_disable_fbc(dev);
1402
1403         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1404
1405         if (fb->pitch < dev_priv->cfb_pitch)
1406                 dev_priv->cfb_pitch = fb->pitch;
1407
1408         /* FBC_CTL wants 64B units */
1409         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1410         dev_priv->cfb_fence = obj->fence_reg;
1411         dev_priv->cfb_plane = intel_crtc->plane;
1412         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1413
1414         /* Clear old tags */
1415         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1416                 I915_WRITE(FBC_TAG + (i * 4), 0);
1417
1418         /* Set it up... */
1419         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1420         if (obj->tiling_mode != I915_TILING_NONE)
1421                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1422         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1423         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1424
1425         /* enable it... */
1426         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1427         if (IS_I945GM(dev))
1428                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1429         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1430         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1431         if (obj->tiling_mode != I915_TILING_NONE)
1432                 fbc_ctl |= dev_priv->cfb_fence;
1433         I915_WRITE(FBC_CONTROL, fbc_ctl);
1434
1435         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1436                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1437 }
1438
1439 void i8xx_disable_fbc(struct drm_device *dev)
1440 {
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         u32 fbc_ctl;
1443
1444         /* Disable compression */
1445         fbc_ctl = I915_READ(FBC_CONTROL);
1446         if ((fbc_ctl & FBC_CTL_EN) == 0)
1447                 return;
1448
1449         fbc_ctl &= ~FBC_CTL_EN;
1450         I915_WRITE(FBC_CONTROL, fbc_ctl);
1451
1452         /* Wait for compressing bit to clear */
1453         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1454                 DRM_DEBUG_KMS("FBC idle timed out\n");
1455                 return;
1456         }
1457
1458         DRM_DEBUG_KMS("disabled FBC\n");
1459 }
1460
1461 static bool i8xx_fbc_enabled(struct drm_device *dev)
1462 {
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464
1465         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1466 }
1467
1468 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1469 {
1470         struct drm_device *dev = crtc->dev;
1471         struct drm_i915_private *dev_priv = dev->dev_private;
1472         struct drm_framebuffer *fb = crtc->fb;
1473         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1474         struct drm_i915_gem_object *obj = intel_fb->obj;
1475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1476         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1477         unsigned long stall_watermark = 200;
1478         u32 dpfc_ctl;
1479
1480         dpfc_ctl = I915_READ(DPFC_CONTROL);
1481         if (dpfc_ctl & DPFC_CTL_EN) {
1482                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1483                     dev_priv->cfb_fence == obj->fence_reg &&
1484                     dev_priv->cfb_plane == intel_crtc->plane &&
1485                     dev_priv->cfb_y == crtc->y)
1486                         return;
1487
1488                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1489                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1490         }
1491
1492         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1493         dev_priv->cfb_fence = obj->fence_reg;
1494         dev_priv->cfb_plane = intel_crtc->plane;
1495         dev_priv->cfb_y = crtc->y;
1496
1497         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1498         if (obj->tiling_mode != I915_TILING_NONE) {
1499                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1500                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1501         } else {
1502                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1503         }
1504
1505         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1506                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1507                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1508         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1509
1510         /* enable it... */
1511         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1512
1513         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1514 }
1515
1516 void g4x_disable_fbc(struct drm_device *dev)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         u32 dpfc_ctl;
1520
1521         /* Disable compression */
1522         dpfc_ctl = I915_READ(DPFC_CONTROL);
1523         if (dpfc_ctl & DPFC_CTL_EN) {
1524                 dpfc_ctl &= ~DPFC_CTL_EN;
1525                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1526
1527                 DRM_DEBUG_KMS("disabled FBC\n");
1528         }
1529 }
1530
1531 static bool g4x_fbc_enabled(struct drm_device *dev)
1532 {
1533         struct drm_i915_private *dev_priv = dev->dev_private;
1534
1535         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1536 }
1537
1538 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1539 {
1540         struct drm_i915_private *dev_priv = dev->dev_private;
1541         u32 blt_ecoskpd;
1542
1543         /* Make sure blitter notifies FBC of writes */
1544         gen6_gt_force_wake_get(dev_priv);
1545         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1546         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1547                 GEN6_BLITTER_LOCK_SHIFT;
1548         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1549         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1550         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1551         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1552                          GEN6_BLITTER_LOCK_SHIFT);
1553         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1554         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1555         gen6_gt_force_wake_put(dev_priv);
1556 }
1557
1558 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1559 {
1560         struct drm_device *dev = crtc->dev;
1561         struct drm_i915_private *dev_priv = dev->dev_private;
1562         struct drm_framebuffer *fb = crtc->fb;
1563         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1564         struct drm_i915_gem_object *obj = intel_fb->obj;
1565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1566         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1567         unsigned long stall_watermark = 200;
1568         u32 dpfc_ctl;
1569
1570         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1571         if (dpfc_ctl & DPFC_CTL_EN) {
1572                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1573                     dev_priv->cfb_fence == obj->fence_reg &&
1574                     dev_priv->cfb_plane == intel_crtc->plane &&
1575                     dev_priv->cfb_offset == obj->gtt_offset &&
1576                     dev_priv->cfb_y == crtc->y)
1577                         return;
1578
1579                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1580                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1581         }
1582
1583         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1584         dev_priv->cfb_fence = obj->fence_reg;
1585         dev_priv->cfb_plane = intel_crtc->plane;
1586         dev_priv->cfb_offset = obj->gtt_offset;
1587         dev_priv->cfb_y = crtc->y;
1588
1589         dpfc_ctl &= DPFC_RESERVED;
1590         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1591         if (obj->tiling_mode != I915_TILING_NONE) {
1592                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1593                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1594         } else {
1595                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1596         }
1597
1598         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1599                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1600                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1601         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1602         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1603         /* enable it... */
1604         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1605
1606         if (IS_GEN6(dev)) {
1607                 I915_WRITE(SNB_DPFC_CTL_SA,
1608                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1609                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1610                 sandybridge_blit_fbc_update(dev);
1611         }
1612
1613         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1614 }
1615
1616 void ironlake_disable_fbc(struct drm_device *dev)
1617 {
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619         u32 dpfc_ctl;
1620
1621         /* Disable compression */
1622         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1623         if (dpfc_ctl & DPFC_CTL_EN) {
1624                 dpfc_ctl &= ~DPFC_CTL_EN;
1625                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1626
1627                 DRM_DEBUG_KMS("disabled FBC\n");
1628         }
1629 }
1630
1631 static bool ironlake_fbc_enabled(struct drm_device *dev)
1632 {
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634
1635         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1636 }
1637
1638 bool intel_fbc_enabled(struct drm_device *dev)
1639 {
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641
1642         if (!dev_priv->display.fbc_enabled)
1643                 return false;
1644
1645         return dev_priv->display.fbc_enabled(dev);
1646 }
1647
1648 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1649 {
1650         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1651
1652         if (!dev_priv->display.enable_fbc)
1653                 return;
1654
1655         dev_priv->display.enable_fbc(crtc, interval);
1656 }
1657
1658 void intel_disable_fbc(struct drm_device *dev)
1659 {
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661
1662         if (!dev_priv->display.disable_fbc)
1663                 return;
1664
1665         dev_priv->display.disable_fbc(dev);
1666 }
1667
1668 /**
1669  * intel_update_fbc - enable/disable FBC as needed
1670  * @dev: the drm_device
1671  *
1672  * Set up the framebuffer compression hardware at mode set time.  We
1673  * enable it if possible:
1674  *   - plane A only (on pre-965)
1675  *   - no pixel mulitply/line duplication
1676  *   - no alpha buffer discard
1677  *   - no dual wide
1678  *   - framebuffer <= 2048 in width, 1536 in height
1679  *
1680  * We can't assume that any compression will take place (worst case),
1681  * so the compressed buffer has to be the same size as the uncompressed
1682  * one.  It also must reside (along with the line length buffer) in
1683  * stolen memory.
1684  *
1685  * We need to enable/disable FBC on a global basis.
1686  */
1687 static void intel_update_fbc(struct drm_device *dev)
1688 {
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         struct drm_crtc *crtc = NULL, *tmp_crtc;
1691         struct intel_crtc *intel_crtc;
1692         struct drm_framebuffer *fb;
1693         struct intel_framebuffer *intel_fb;
1694         struct drm_i915_gem_object *obj;
1695
1696         DRM_DEBUG_KMS("\n");
1697
1698         if (!i915_powersave)
1699                 return;
1700
1701         if (!I915_HAS_FBC(dev))
1702                 return;
1703
1704         /*
1705          * If FBC is already on, we just have to verify that we can
1706          * keep it that way...
1707          * Need to disable if:
1708          *   - more than one pipe is active
1709          *   - changing FBC params (stride, fence, mode)
1710          *   - new fb is too large to fit in compressed buffer
1711          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1712          */
1713         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1714                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1715                         if (crtc) {
1716                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1717                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1718                                 goto out_disable;
1719                         }
1720                         crtc = tmp_crtc;
1721                 }
1722         }
1723
1724         if (!crtc || crtc->fb == NULL) {
1725                 DRM_DEBUG_KMS("no output, disabling\n");
1726                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1727                 goto out_disable;
1728         }
1729
1730         intel_crtc = to_intel_crtc(crtc);
1731         fb = crtc->fb;
1732         intel_fb = to_intel_framebuffer(fb);
1733         obj = intel_fb->obj;
1734
1735         if (!i915_enable_fbc) {
1736                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1737                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1738                 goto out_disable;
1739         }
1740         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1741                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1742                               "compression\n");
1743                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1744                 goto out_disable;
1745         }
1746         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1747             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1748                 DRM_DEBUG_KMS("mode incompatible with compression, "
1749                               "disabling\n");
1750                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1751                 goto out_disable;
1752         }
1753         if ((crtc->mode.hdisplay > 2048) ||
1754             (crtc->mode.vdisplay > 1536)) {
1755                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1756                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1757                 goto out_disable;
1758         }
1759         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1760                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1761                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1762                 goto out_disable;
1763         }
1764         if (obj->tiling_mode != I915_TILING_X) {
1765                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1766                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1767                 goto out_disable;
1768         }
1769
1770         /* If the kernel debugger is active, always disable compression */
1771         if (in_dbg_master())
1772                 goto out_disable;
1773
1774         intel_enable_fbc(crtc, 500);
1775         return;
1776
1777 out_disable:
1778         /* Multiple disables should be harmless */
1779         if (intel_fbc_enabled(dev)) {
1780                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1781                 intel_disable_fbc(dev);
1782         }
1783 }
1784
1785 int
1786 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1787                            struct drm_i915_gem_object *obj,
1788                            struct intel_ring_buffer *pipelined)
1789 {
1790         struct drm_i915_private *dev_priv = dev->dev_private;
1791         u32 alignment;
1792         int ret;
1793
1794         switch (obj->tiling_mode) {
1795         case I915_TILING_NONE:
1796                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1797                         alignment = 128 * 1024;
1798                 else if (INTEL_INFO(dev)->gen >= 4)
1799                         alignment = 4 * 1024;
1800                 else
1801                         alignment = 64 * 1024;
1802                 break;
1803         case I915_TILING_X:
1804                 /* pin() will align the object as required by fence */
1805                 alignment = 0;
1806                 break;
1807         case I915_TILING_Y:
1808                 /* FIXME: Is this true? */
1809                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1810                 return -EINVAL;
1811         default:
1812                 BUG();
1813         }
1814
1815         dev_priv->mm.interruptible = false;
1816         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1817         if (ret)
1818                 goto err_interruptible;
1819
1820         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1821          * fence, whereas 965+ only requires a fence if using
1822          * framebuffer compression.  For simplicity, we always install
1823          * a fence as the cost is not that onerous.
1824          */
1825         if (obj->tiling_mode != I915_TILING_NONE) {
1826                 ret = i915_gem_object_get_fence(obj, pipelined);
1827                 if (ret)
1828                         goto err_unpin;
1829         }
1830
1831         dev_priv->mm.interruptible = true;
1832         return 0;
1833
1834 err_unpin:
1835         i915_gem_object_unpin(obj);
1836 err_interruptible:
1837         dev_priv->mm.interruptible = true;
1838         return ret;
1839 }
1840
1841 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1842 static int
1843 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1844                            int x, int y, enum mode_set_atomic state)
1845 {
1846         struct drm_device *dev = crtc->dev;
1847         struct drm_i915_private *dev_priv = dev->dev_private;
1848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1849         struct intel_framebuffer *intel_fb;
1850         struct drm_i915_gem_object *obj;
1851         int plane = intel_crtc->plane;
1852         unsigned long Start, Offset;
1853         u32 dspcntr;
1854         u32 reg;
1855
1856         switch (plane) {
1857         case 0:
1858         case 1:
1859                 break;
1860         default:
1861                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1862                 return -EINVAL;
1863         }
1864
1865         intel_fb = to_intel_framebuffer(fb);
1866         obj = intel_fb->obj;
1867
1868         reg = DSPCNTR(plane);
1869         dspcntr = I915_READ(reg);
1870         /* Mask out pixel format bits in case we change it */
1871         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1872         switch (fb->bits_per_pixel) {
1873         case 8:
1874                 dspcntr |= DISPPLANE_8BPP;
1875                 break;
1876         case 16:
1877                 if (fb->depth == 15)
1878                         dspcntr |= DISPPLANE_15_16BPP;
1879                 else
1880                         dspcntr |= DISPPLANE_16BPP;
1881                 break;
1882         case 24:
1883         case 32:
1884                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1885                 break;
1886         default:
1887                 DRM_ERROR("Unknown color depth\n");
1888                 return -EINVAL;
1889         }
1890         if (INTEL_INFO(dev)->gen >= 4) {
1891                 if (obj->tiling_mode != I915_TILING_NONE)
1892                         dspcntr |= DISPPLANE_TILED;
1893                 else
1894                         dspcntr &= ~DISPPLANE_TILED;
1895         }
1896
1897         if (HAS_PCH_SPLIT(dev))
1898                 /* must disable */
1899                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1900
1901         I915_WRITE(reg, dspcntr);
1902
1903         Start = obj->gtt_offset;
1904         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1905
1906         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1907                       Start, Offset, x, y, fb->pitch);
1908         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1909         if (INTEL_INFO(dev)->gen >= 4) {
1910                 I915_WRITE(DSPSURF(plane), Start);
1911                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1912                 I915_WRITE(DSPADDR(plane), Offset);
1913         } else
1914                 I915_WRITE(DSPADDR(plane), Start + Offset);
1915         POSTING_READ(reg);
1916
1917         intel_update_fbc(dev);
1918         intel_increase_pllclock(crtc);
1919
1920         return 0;
1921 }
1922
1923 static int
1924 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1925                     struct drm_framebuffer *old_fb)
1926 {
1927         struct drm_device *dev = crtc->dev;
1928         struct drm_i915_master_private *master_priv;
1929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1930         int ret;
1931
1932         /* no fb bound */
1933         if (!crtc->fb) {
1934                 DRM_DEBUG_KMS("No FB bound\n");
1935                 return 0;
1936         }
1937
1938         switch (intel_crtc->plane) {
1939         case 0:
1940         case 1:
1941                 break;
1942         default:
1943                 return -EINVAL;
1944         }
1945
1946         mutex_lock(&dev->struct_mutex);
1947         ret = intel_pin_and_fence_fb_obj(dev,
1948                                          to_intel_framebuffer(crtc->fb)->obj,
1949                                          NULL);
1950         if (ret != 0) {
1951                 mutex_unlock(&dev->struct_mutex);
1952                 return ret;
1953         }
1954
1955         if (old_fb) {
1956                 struct drm_i915_private *dev_priv = dev->dev_private;
1957                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1958
1959                 wait_event(dev_priv->pending_flip_queue,
1960                            atomic_read(&dev_priv->mm.wedged) ||
1961                            atomic_read(&obj->pending_flip) == 0);
1962
1963                 /* Big Hammer, we also need to ensure that any pending
1964                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1965                  * current scanout is retired before unpinning the old
1966                  * framebuffer.
1967                  *
1968                  * This should only fail upon a hung GPU, in which case we
1969                  * can safely continue.
1970                  */
1971                 ret = i915_gem_object_finish_gpu(obj);
1972                 (void) ret;
1973         }
1974
1975         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1976                                          LEAVE_ATOMIC_MODE_SET);
1977         if (ret) {
1978                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1979                 mutex_unlock(&dev->struct_mutex);
1980                 return ret;
1981         }
1982
1983         if (old_fb) {
1984                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1985                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1986         }
1987
1988         mutex_unlock(&dev->struct_mutex);
1989
1990         if (!dev->primary->master)
1991                 return 0;
1992
1993         master_priv = dev->primary->master->driver_priv;
1994         if (!master_priv->sarea_priv)
1995                 return 0;
1996
1997         if (intel_crtc->pipe) {
1998                 master_priv->sarea_priv->pipeB_x = x;
1999                 master_priv->sarea_priv->pipeB_y = y;
2000         } else {
2001                 master_priv->sarea_priv->pipeA_x = x;
2002                 master_priv->sarea_priv->pipeA_y = y;
2003         }
2004
2005         return 0;
2006 }
2007
2008 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2009 {
2010         struct drm_device *dev = crtc->dev;
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         u32 dpa_ctl;
2013
2014         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2015         dpa_ctl = I915_READ(DP_A);
2016         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2017
2018         if (clock < 200000) {
2019                 u32 temp;
2020                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2021                 /* workaround for 160Mhz:
2022                    1) program 0x4600c bits 15:0 = 0x8124
2023                    2) program 0x46010 bit 0 = 1
2024                    3) program 0x46034 bit 24 = 1
2025                    4) program 0x64000 bit 14 = 1
2026                    */
2027                 temp = I915_READ(0x4600c);
2028                 temp &= 0xffff0000;
2029                 I915_WRITE(0x4600c, temp | 0x8124);
2030
2031                 temp = I915_READ(0x46010);
2032                 I915_WRITE(0x46010, temp | 1);
2033
2034                 temp = I915_READ(0x46034);
2035                 I915_WRITE(0x46034, temp | (1 << 24));
2036         } else {
2037                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2038         }
2039         I915_WRITE(DP_A, dpa_ctl);
2040
2041         POSTING_READ(DP_A);
2042         udelay(500);
2043 }
2044
2045 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2046 {
2047         struct drm_device *dev = crtc->dev;
2048         struct drm_i915_private *dev_priv = dev->dev_private;
2049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2050         int pipe = intel_crtc->pipe;
2051         u32 reg, temp;
2052
2053         /* enable normal train */
2054         reg = FDI_TX_CTL(pipe);
2055         temp = I915_READ(reg);
2056         if (IS_IVYBRIDGE(dev)) {
2057                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2058                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2059         } else {
2060                 temp &= ~FDI_LINK_TRAIN_NONE;
2061                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2062         }
2063         I915_WRITE(reg, temp);
2064
2065         reg = FDI_RX_CTL(pipe);
2066         temp = I915_READ(reg);
2067         if (HAS_PCH_CPT(dev)) {
2068                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2069                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2070         } else {
2071                 temp &= ~FDI_LINK_TRAIN_NONE;
2072                 temp |= FDI_LINK_TRAIN_NONE;
2073         }
2074         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2075
2076         /* wait one idle pattern time */
2077         POSTING_READ(reg);
2078         udelay(1000);
2079
2080         /* IVB wants error correction enabled */
2081         if (IS_IVYBRIDGE(dev))
2082                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2083                            FDI_FE_ERRC_ENABLE);
2084 }
2085
2086 /* The FDI link training functions for ILK/Ibexpeak. */
2087 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2088 {
2089         struct drm_device *dev = crtc->dev;
2090         struct drm_i915_private *dev_priv = dev->dev_private;
2091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2092         int pipe = intel_crtc->pipe;
2093         int plane = intel_crtc->plane;
2094         u32 reg, temp, tries;
2095
2096         /* FDI needs bits from pipe & plane first */
2097         assert_pipe_enabled(dev_priv, pipe);
2098         assert_plane_enabled(dev_priv, plane);
2099
2100         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2101            for train result */
2102         reg = FDI_RX_IMR(pipe);
2103         temp = I915_READ(reg);
2104         temp &= ~FDI_RX_SYMBOL_LOCK;
2105         temp &= ~FDI_RX_BIT_LOCK;
2106         I915_WRITE(reg, temp);
2107         I915_READ(reg);
2108         udelay(150);
2109
2110         /* enable CPU FDI TX and PCH FDI RX */
2111         reg = FDI_TX_CTL(pipe);
2112         temp = I915_READ(reg);
2113         temp &= ~(7 << 19);
2114         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2115         temp &= ~FDI_LINK_TRAIN_NONE;
2116         temp |= FDI_LINK_TRAIN_PATTERN_1;
2117         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2118
2119         reg = FDI_RX_CTL(pipe);
2120         temp = I915_READ(reg);
2121         temp &= ~FDI_LINK_TRAIN_NONE;
2122         temp |= FDI_LINK_TRAIN_PATTERN_1;
2123         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2124
2125         POSTING_READ(reg);
2126         udelay(150);
2127
2128         /* Ironlake workaround, enable clock pointer after FDI enable*/
2129         if (HAS_PCH_IBX(dev)) {
2130                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2131                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2132                            FDI_RX_PHASE_SYNC_POINTER_EN);
2133         }
2134
2135         reg = FDI_RX_IIR(pipe);
2136         for (tries = 0; tries < 5; tries++) {
2137                 temp = I915_READ(reg);
2138                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2139
2140                 if ((temp & FDI_RX_BIT_LOCK)) {
2141                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2142                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2143                         break;
2144                 }
2145         }
2146         if (tries == 5)
2147                 DRM_ERROR("FDI train 1 fail!\n");
2148
2149         /* Train 2 */
2150         reg = FDI_TX_CTL(pipe);
2151         temp = I915_READ(reg);
2152         temp &= ~FDI_LINK_TRAIN_NONE;
2153         temp |= FDI_LINK_TRAIN_PATTERN_2;
2154         I915_WRITE(reg, temp);
2155
2156         reg = FDI_RX_CTL(pipe);
2157         temp = I915_READ(reg);
2158         temp &= ~FDI_LINK_TRAIN_NONE;
2159         temp |= FDI_LINK_TRAIN_PATTERN_2;
2160         I915_WRITE(reg, temp);
2161
2162         POSTING_READ(reg);
2163         udelay(150);
2164
2165         reg = FDI_RX_IIR(pipe);
2166         for (tries = 0; tries < 5; tries++) {
2167                 temp = I915_READ(reg);
2168                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2169
2170                 if (temp & FDI_RX_SYMBOL_LOCK) {
2171                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2172                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2173                         break;
2174                 }
2175         }
2176         if (tries == 5)
2177                 DRM_ERROR("FDI train 2 fail!\n");
2178
2179         DRM_DEBUG_KMS("FDI train done\n");
2180
2181 }
2182
2183 static const int snb_b_fdi_train_param [] = {
2184         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2185         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2186         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2187         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2188 };
2189
2190 /* The FDI link training functions for SNB/Cougarpoint. */
2191 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2192 {
2193         struct drm_device *dev = crtc->dev;
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2196         int pipe = intel_crtc->pipe;
2197         u32 reg, temp, i;
2198
2199         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2200            for train result */
2201         reg = FDI_RX_IMR(pipe);
2202         temp = I915_READ(reg);
2203         temp &= ~FDI_RX_SYMBOL_LOCK;
2204         temp &= ~FDI_RX_BIT_LOCK;
2205         I915_WRITE(reg, temp);
2206
2207         POSTING_READ(reg);
2208         udelay(150);
2209
2210         /* enable CPU FDI TX and PCH FDI RX */
2211         reg = FDI_TX_CTL(pipe);
2212         temp = I915_READ(reg);
2213         temp &= ~(7 << 19);
2214         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2215         temp &= ~FDI_LINK_TRAIN_NONE;
2216         temp |= FDI_LINK_TRAIN_PATTERN_1;
2217         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2218         /* SNB-B */
2219         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2220         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2221
2222         reg = FDI_RX_CTL(pipe);
2223         temp = I915_READ(reg);
2224         if (HAS_PCH_CPT(dev)) {
2225                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2226                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2227         } else {
2228                 temp &= ~FDI_LINK_TRAIN_NONE;
2229                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2230         }
2231         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2232
2233         POSTING_READ(reg);
2234         udelay(150);
2235
2236         for (i = 0; i < 4; i++ ) {
2237                 reg = FDI_TX_CTL(pipe);
2238                 temp = I915_READ(reg);
2239                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2240                 temp |= snb_b_fdi_train_param[i];
2241                 I915_WRITE(reg, temp);
2242
2243                 POSTING_READ(reg);
2244                 udelay(500);
2245
2246                 reg = FDI_RX_IIR(pipe);
2247                 temp = I915_READ(reg);
2248                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2249
2250                 if (temp & FDI_RX_BIT_LOCK) {
2251                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2252                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2253                         break;
2254                 }
2255         }
2256         if (i == 4)
2257                 DRM_ERROR("FDI train 1 fail!\n");
2258
2259         /* Train 2 */
2260         reg = FDI_TX_CTL(pipe);
2261         temp = I915_READ(reg);
2262         temp &= ~FDI_LINK_TRAIN_NONE;
2263         temp |= FDI_LINK_TRAIN_PATTERN_2;
2264         if (IS_GEN6(dev)) {
2265                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2266                 /* SNB-B */
2267                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2268         }
2269         I915_WRITE(reg, temp);
2270
2271         reg = FDI_RX_CTL(pipe);
2272         temp = I915_READ(reg);
2273         if (HAS_PCH_CPT(dev)) {
2274                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2275                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2276         } else {
2277                 temp &= ~FDI_LINK_TRAIN_NONE;
2278                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2279         }
2280         I915_WRITE(reg, temp);
2281
2282         POSTING_READ(reg);
2283         udelay(150);
2284
2285         for (i = 0; i < 4; i++ ) {
2286                 reg = FDI_TX_CTL(pipe);
2287                 temp = I915_READ(reg);
2288                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2289                 temp |= snb_b_fdi_train_param[i];
2290                 I915_WRITE(reg, temp);
2291
2292                 POSTING_READ(reg);
2293                 udelay(500);
2294
2295                 reg = FDI_RX_IIR(pipe);
2296                 temp = I915_READ(reg);
2297                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2298
2299                 if (temp & FDI_RX_SYMBOL_LOCK) {
2300                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2301                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2302                         break;
2303                 }
2304         }
2305         if (i == 4)
2306                 DRM_ERROR("FDI train 2 fail!\n");
2307
2308         DRM_DEBUG_KMS("FDI train done.\n");
2309 }
2310
2311 /* Manual link training for Ivy Bridge A0 parts */
2312 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2313 {
2314         struct drm_device *dev = crtc->dev;
2315         struct drm_i915_private *dev_priv = dev->dev_private;
2316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2317         int pipe = intel_crtc->pipe;
2318         u32 reg, temp, i;
2319
2320         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2321            for train result */
2322         reg = FDI_RX_IMR(pipe);
2323         temp = I915_READ(reg);
2324         temp &= ~FDI_RX_SYMBOL_LOCK;
2325         temp &= ~FDI_RX_BIT_LOCK;
2326         I915_WRITE(reg, temp);
2327
2328         POSTING_READ(reg);
2329         udelay(150);
2330
2331         /* enable CPU FDI TX and PCH FDI RX */
2332         reg = FDI_TX_CTL(pipe);
2333         temp = I915_READ(reg);
2334         temp &= ~(7 << 19);
2335         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2336         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2337         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2338         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2339         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2340         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2341
2342         reg = FDI_RX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         temp &= ~FDI_LINK_TRAIN_AUTO;
2345         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2346         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2347         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2348
2349         POSTING_READ(reg);
2350         udelay(150);
2351
2352         for (i = 0; i < 4; i++ ) {
2353                 reg = FDI_TX_CTL(pipe);
2354                 temp = I915_READ(reg);
2355                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2356                 temp |= snb_b_fdi_train_param[i];
2357                 I915_WRITE(reg, temp);
2358
2359                 POSTING_READ(reg);
2360                 udelay(500);
2361
2362                 reg = FDI_RX_IIR(pipe);
2363                 temp = I915_READ(reg);
2364                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2365
2366                 if (temp & FDI_RX_BIT_LOCK ||
2367                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2368                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2369                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2370                         break;
2371                 }
2372         }
2373         if (i == 4)
2374                 DRM_ERROR("FDI train 1 fail!\n");
2375
2376         /* Train 2 */
2377         reg = FDI_TX_CTL(pipe);
2378         temp = I915_READ(reg);
2379         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2380         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2381         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2382         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2383         I915_WRITE(reg, temp);
2384
2385         reg = FDI_RX_CTL(pipe);
2386         temp = I915_READ(reg);
2387         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2388         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2389         I915_WRITE(reg, temp);
2390
2391         POSTING_READ(reg);
2392         udelay(150);
2393
2394         for (i = 0; i < 4; i++ ) {
2395                 reg = FDI_TX_CTL(pipe);
2396                 temp = I915_READ(reg);
2397                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2398                 temp |= snb_b_fdi_train_param[i];
2399                 I915_WRITE(reg, temp);
2400
2401                 POSTING_READ(reg);
2402                 udelay(500);
2403
2404                 reg = FDI_RX_IIR(pipe);
2405                 temp = I915_READ(reg);
2406                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2407
2408                 if (temp & FDI_RX_SYMBOL_LOCK) {
2409                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2410                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2411                         break;
2412                 }
2413         }
2414         if (i == 4)
2415                 DRM_ERROR("FDI train 2 fail!\n");
2416
2417         DRM_DEBUG_KMS("FDI train done.\n");
2418 }
2419
2420 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2421 {
2422         struct drm_device *dev = crtc->dev;
2423         struct drm_i915_private *dev_priv = dev->dev_private;
2424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2425         int pipe = intel_crtc->pipe;
2426         u32 reg, temp;
2427
2428         /* Write the TU size bits so error detection works */
2429         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2430                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2431
2432         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2433         reg = FDI_RX_CTL(pipe);
2434         temp = I915_READ(reg);
2435         temp &= ~((0x7 << 19) | (0x7 << 16));
2436         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2437         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2438         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2439
2440         POSTING_READ(reg);
2441         udelay(200);
2442
2443         /* Switch from Rawclk to PCDclk */
2444         temp = I915_READ(reg);
2445         I915_WRITE(reg, temp | FDI_PCDCLK);
2446
2447         POSTING_READ(reg);
2448         udelay(200);
2449
2450         /* Enable CPU FDI TX PLL, always on for Ironlake */
2451         reg = FDI_TX_CTL(pipe);
2452         temp = I915_READ(reg);
2453         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2454                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2455
2456                 POSTING_READ(reg);
2457                 udelay(100);
2458         }
2459 }
2460
2461 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2462 {
2463         struct drm_device *dev = crtc->dev;
2464         struct drm_i915_private *dev_priv = dev->dev_private;
2465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2466         int pipe = intel_crtc->pipe;
2467         u32 reg, temp;
2468
2469         /* disable CPU FDI tx and PCH FDI rx */
2470         reg = FDI_TX_CTL(pipe);
2471         temp = I915_READ(reg);
2472         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2473         POSTING_READ(reg);
2474
2475         reg = FDI_RX_CTL(pipe);
2476         temp = I915_READ(reg);
2477         temp &= ~(0x7 << 16);
2478         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2479         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2480
2481         POSTING_READ(reg);
2482         udelay(100);
2483
2484         /* Ironlake workaround, disable clock pointer after downing FDI */
2485         if (HAS_PCH_IBX(dev)) {
2486                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2487                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2488                            I915_READ(FDI_RX_CHICKEN(pipe) &
2489                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2490         }
2491
2492         /* still set train pattern 1 */
2493         reg = FDI_TX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         temp &= ~FDI_LINK_TRAIN_NONE;
2496         temp |= FDI_LINK_TRAIN_PATTERN_1;
2497         I915_WRITE(reg, temp);
2498
2499         reg = FDI_RX_CTL(pipe);
2500         temp = I915_READ(reg);
2501         if (HAS_PCH_CPT(dev)) {
2502                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2503                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2504         } else {
2505                 temp &= ~FDI_LINK_TRAIN_NONE;
2506                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2507         }
2508         /* BPC in FDI rx is consistent with that in PIPECONF */
2509         temp &= ~(0x07 << 16);
2510         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2511         I915_WRITE(reg, temp);
2512
2513         POSTING_READ(reg);
2514         udelay(100);
2515 }
2516
2517 /*
2518  * When we disable a pipe, we need to clear any pending scanline wait events
2519  * to avoid hanging the ring, which we assume we are waiting on.
2520  */
2521 static void intel_clear_scanline_wait(struct drm_device *dev)
2522 {
2523         struct drm_i915_private *dev_priv = dev->dev_private;
2524         struct intel_ring_buffer *ring;
2525         u32 tmp;
2526
2527         if (IS_GEN2(dev))
2528                 /* Can't break the hang on i8xx */
2529                 return;
2530
2531         ring = LP_RING(dev_priv);
2532         tmp = I915_READ_CTL(ring);
2533         if (tmp & RING_WAIT)
2534                 I915_WRITE_CTL(ring, tmp);
2535 }
2536
2537 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2538 {
2539         struct drm_i915_gem_object *obj;
2540         struct drm_i915_private *dev_priv;
2541
2542         if (crtc->fb == NULL)
2543                 return;
2544
2545         obj = to_intel_framebuffer(crtc->fb)->obj;
2546         dev_priv = crtc->dev->dev_private;
2547         wait_event(dev_priv->pending_flip_queue,
2548                    atomic_read(&obj->pending_flip) == 0);
2549 }
2550
2551 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2552 {
2553         struct drm_device *dev = crtc->dev;
2554         struct drm_mode_config *mode_config = &dev->mode_config;
2555         struct intel_encoder *encoder;
2556
2557         /*
2558          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2559          * must be driven by its own crtc; no sharing is possible.
2560          */
2561         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2562                 if (encoder->base.crtc != crtc)
2563                         continue;
2564
2565                 switch (encoder->type) {
2566                 case INTEL_OUTPUT_EDP:
2567                         if (!intel_encoder_is_pch_edp(&encoder->base))
2568                                 return false;
2569                         continue;
2570                 }
2571         }
2572
2573         return true;
2574 }
2575
2576 /*
2577  * Enable PCH resources required for PCH ports:
2578  *   - PCH PLLs
2579  *   - FDI training & RX/TX
2580  *   - update transcoder timings
2581  *   - DP transcoding bits
2582  *   - transcoder
2583  */
2584 static void ironlake_pch_enable(struct drm_crtc *crtc)
2585 {
2586         struct drm_device *dev = crtc->dev;
2587         struct drm_i915_private *dev_priv = dev->dev_private;
2588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2589         int pipe = intel_crtc->pipe;
2590         u32 reg, temp;
2591
2592         /* For PCH output, training FDI link */
2593         dev_priv->display.fdi_link_train(crtc);
2594
2595         intel_enable_pch_pll(dev_priv, pipe);
2596
2597         if (HAS_PCH_CPT(dev)) {
2598                 /* Be sure PCH DPLL SEL is set */
2599                 temp = I915_READ(PCH_DPLL_SEL);
2600                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2601                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2602                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2603                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2604                 I915_WRITE(PCH_DPLL_SEL, temp);
2605         }
2606
2607         /* set transcoder timing, panel must allow it */
2608         assert_panel_unlocked(dev_priv, pipe);
2609         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2610         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2611         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2612
2613         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2614         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2615         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2616
2617         intel_fdi_normal_train(crtc);
2618
2619         /* For PCH DP, enable TRANS_DP_CTL */
2620         if (HAS_PCH_CPT(dev) &&
2621             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2622                 reg = TRANS_DP_CTL(pipe);
2623                 temp = I915_READ(reg);
2624                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2625                           TRANS_DP_SYNC_MASK |
2626                           TRANS_DP_BPC_MASK);
2627                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2628                          TRANS_DP_ENH_FRAMING);
2629                 temp |= TRANS_DP_8BPC;
2630
2631                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2632                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2633                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2634                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2635
2636                 switch (intel_trans_dp_port_sel(crtc)) {
2637                 case PCH_DP_B:
2638                         temp |= TRANS_DP_PORT_SEL_B;
2639                         break;
2640                 case PCH_DP_C:
2641                         temp |= TRANS_DP_PORT_SEL_C;
2642                         break;
2643                 case PCH_DP_D:
2644                         temp |= TRANS_DP_PORT_SEL_D;
2645                         break;
2646                 default:
2647                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2648                         temp |= TRANS_DP_PORT_SEL_B;
2649                         break;
2650                 }
2651
2652                 I915_WRITE(reg, temp);
2653         }
2654
2655         intel_enable_transcoder(dev_priv, pipe);
2656 }
2657
2658 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2659 {
2660         struct drm_device *dev = crtc->dev;
2661         struct drm_i915_private *dev_priv = dev->dev_private;
2662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2663         int pipe = intel_crtc->pipe;
2664         int plane = intel_crtc->plane;
2665         u32 temp;
2666         bool is_pch_port;
2667
2668         if (intel_crtc->active)
2669                 return;
2670
2671         intel_crtc->active = true;
2672         intel_update_watermarks(dev);
2673
2674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2675                 temp = I915_READ(PCH_LVDS);
2676                 if ((temp & LVDS_PORT_EN) == 0)
2677                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2678         }
2679
2680         is_pch_port = intel_crtc_driving_pch(crtc);
2681
2682         if (is_pch_port)
2683                 ironlake_fdi_pll_enable(crtc);
2684         else
2685                 ironlake_fdi_disable(crtc);
2686
2687         /* Enable panel fitting for LVDS */
2688         if (dev_priv->pch_pf_size &&
2689             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2690                 /* Force use of hard-coded filter coefficients
2691                  * as some pre-programmed values are broken,
2692                  * e.g. x201.
2693                  */
2694                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2695                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2696                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2697         }
2698
2699         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2700         intel_enable_plane(dev_priv, plane, pipe);
2701
2702         if (is_pch_port)
2703                 ironlake_pch_enable(crtc);
2704
2705         intel_crtc_load_lut(crtc);
2706
2707         mutex_lock(&dev->struct_mutex);
2708         intel_update_fbc(dev);
2709         mutex_unlock(&dev->struct_mutex);
2710
2711         intel_crtc_update_cursor(crtc, true);
2712 }
2713
2714 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2715 {
2716         struct drm_device *dev = crtc->dev;
2717         struct drm_i915_private *dev_priv = dev->dev_private;
2718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2719         int pipe = intel_crtc->pipe;
2720         int plane = intel_crtc->plane;
2721         u32 reg, temp;
2722
2723         if (!intel_crtc->active)
2724                 return;
2725
2726         intel_crtc_wait_for_pending_flips(crtc);
2727         drm_vblank_off(dev, pipe);
2728         intel_crtc_update_cursor(crtc, false);
2729
2730         intel_disable_plane(dev_priv, plane, pipe);
2731
2732         if (dev_priv->cfb_plane == plane &&
2733             dev_priv->display.disable_fbc)
2734                 dev_priv->display.disable_fbc(dev);
2735
2736         intel_disable_pipe(dev_priv, pipe);
2737
2738         /* Disable PF */
2739         I915_WRITE(PF_CTL(pipe), 0);
2740         I915_WRITE(PF_WIN_SZ(pipe), 0);
2741
2742         ironlake_fdi_disable(crtc);
2743
2744         /* This is a horrible layering violation; we should be doing this in
2745          * the connector/encoder ->prepare instead, but we don't always have
2746          * enough information there about the config to know whether it will
2747          * actually be necessary or just cause undesired flicker.
2748          */
2749         intel_disable_pch_ports(dev_priv, pipe);
2750
2751         intel_disable_transcoder(dev_priv, pipe);
2752
2753         if (HAS_PCH_CPT(dev)) {
2754                 /* disable TRANS_DP_CTL */
2755                 reg = TRANS_DP_CTL(pipe);
2756                 temp = I915_READ(reg);
2757                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2758                 temp |= TRANS_DP_PORT_SEL_NONE;
2759                 I915_WRITE(reg, temp);
2760
2761                 /* disable DPLL_SEL */
2762                 temp = I915_READ(PCH_DPLL_SEL);
2763                 switch (pipe) {
2764                 case 0:
2765                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2766                         break;
2767                 case 1:
2768                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2769                         break;
2770                 case 2:
2771                         /* FIXME: manage transcoder PLLs? */
2772                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2773                         break;
2774                 default:
2775                         BUG(); /* wtf */
2776                 }
2777                 I915_WRITE(PCH_DPLL_SEL, temp);
2778         }
2779
2780         /* disable PCH DPLL */
2781         intel_disable_pch_pll(dev_priv, pipe);
2782
2783         /* Switch from PCDclk to Rawclk */
2784         reg = FDI_RX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2787
2788         /* Disable CPU FDI TX PLL */
2789         reg = FDI_TX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         reg = FDI_RX_CTL(pipe);
2797         temp = I915_READ(reg);
2798         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2799
2800         /* Wait for the clocks to turn off. */
2801         POSTING_READ(reg);
2802         udelay(100);
2803
2804         intel_crtc->active = false;
2805         intel_update_watermarks(dev);
2806
2807         mutex_lock(&dev->struct_mutex);
2808         intel_update_fbc(dev);
2809         intel_clear_scanline_wait(dev);
2810         mutex_unlock(&dev->struct_mutex);
2811 }
2812
2813 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2814 {
2815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2816         int pipe = intel_crtc->pipe;
2817         int plane = intel_crtc->plane;
2818
2819         /* XXX: When our outputs are all unaware of DPMS modes other than off
2820          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2821          */
2822         switch (mode) {
2823         case DRM_MODE_DPMS_ON:
2824         case DRM_MODE_DPMS_STANDBY:
2825         case DRM_MODE_DPMS_SUSPEND:
2826                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2827                 ironlake_crtc_enable(crtc);
2828                 break;
2829
2830         case DRM_MODE_DPMS_OFF:
2831                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2832                 ironlake_crtc_disable(crtc);
2833                 break;
2834         }
2835 }
2836
2837 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2838 {
2839         if (!enable && intel_crtc->overlay) {
2840                 struct drm_device *dev = intel_crtc->base.dev;
2841                 struct drm_i915_private *dev_priv = dev->dev_private;
2842
2843                 mutex_lock(&dev->struct_mutex);
2844                 dev_priv->mm.interruptible = false;
2845                 (void) intel_overlay_switch_off(intel_crtc->overlay);
2846                 dev_priv->mm.interruptible = true;
2847                 mutex_unlock(&dev->struct_mutex);
2848         }
2849
2850         /* Let userspace switch the overlay on again. In most cases userspace
2851          * has to recompute where to put it anyway.
2852          */
2853 }
2854
2855 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2856 {
2857         struct drm_device *dev = crtc->dev;
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2860         int pipe = intel_crtc->pipe;
2861         int plane = intel_crtc->plane;
2862
2863         if (intel_crtc->active)
2864                 return;
2865
2866         intel_crtc->active = true;
2867         intel_update_watermarks(dev);
2868
2869         intel_enable_pll(dev_priv, pipe);
2870         intel_enable_pipe(dev_priv, pipe, false);
2871         intel_enable_plane(dev_priv, plane, pipe);
2872
2873         intel_crtc_load_lut(crtc);
2874         intel_update_fbc(dev);
2875
2876         /* Give the overlay scaler a chance to enable if it's on this pipe */
2877         intel_crtc_dpms_overlay(intel_crtc, true);
2878         intel_crtc_update_cursor(crtc, true);
2879 }
2880
2881 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2882 {
2883         struct drm_device *dev = crtc->dev;
2884         struct drm_i915_private *dev_priv = dev->dev_private;
2885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2886         int pipe = intel_crtc->pipe;
2887         int plane = intel_crtc->plane;
2888
2889         if (!intel_crtc->active)
2890                 return;
2891
2892         /* Give the overlay scaler a chance to disable if it's on this pipe */
2893         intel_crtc_wait_for_pending_flips(crtc);
2894         drm_vblank_off(dev, pipe);
2895         intel_crtc_dpms_overlay(intel_crtc, false);
2896         intel_crtc_update_cursor(crtc, false);
2897
2898         if (dev_priv->cfb_plane == plane &&
2899             dev_priv->display.disable_fbc)
2900                 dev_priv->display.disable_fbc(dev);
2901
2902         intel_disable_plane(dev_priv, plane, pipe);
2903         intel_disable_pipe(dev_priv, pipe);
2904         intel_disable_pll(dev_priv, pipe);
2905
2906         intel_crtc->active = false;
2907         intel_update_fbc(dev);
2908         intel_update_watermarks(dev);
2909         intel_clear_scanline_wait(dev);
2910 }
2911
2912 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2913 {
2914         /* XXX: When our outputs are all unaware of DPMS modes other than off
2915          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2916          */
2917         switch (mode) {
2918         case DRM_MODE_DPMS_ON:
2919         case DRM_MODE_DPMS_STANDBY:
2920         case DRM_MODE_DPMS_SUSPEND:
2921                 i9xx_crtc_enable(crtc);
2922                 break;
2923         case DRM_MODE_DPMS_OFF:
2924                 i9xx_crtc_disable(crtc);
2925                 break;
2926         }
2927 }
2928
2929 /**
2930  * Sets the power management mode of the pipe and plane.
2931  */
2932 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2933 {
2934         struct drm_device *dev = crtc->dev;
2935         struct drm_i915_private *dev_priv = dev->dev_private;
2936         struct drm_i915_master_private *master_priv;
2937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2938         int pipe = intel_crtc->pipe;
2939         bool enabled;
2940
2941         if (intel_crtc->dpms_mode == mode)
2942                 return;
2943
2944         intel_crtc->dpms_mode = mode;
2945
2946         dev_priv->display.dpms(crtc, mode);
2947
2948         if (!dev->primary->master)
2949                 return;
2950
2951         master_priv = dev->primary->master->driver_priv;
2952         if (!master_priv->sarea_priv)
2953                 return;
2954
2955         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2956
2957         switch (pipe) {
2958         case 0:
2959                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2960                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2961                 break;
2962         case 1:
2963                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2964                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2965                 break;
2966         default:
2967                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2968                 break;
2969         }
2970 }
2971
2972 static void intel_crtc_disable(struct drm_crtc *crtc)
2973 {
2974         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2975         struct drm_device *dev = crtc->dev;
2976
2977         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2978
2979         if (crtc->fb) {
2980                 mutex_lock(&dev->struct_mutex);
2981                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2982                 mutex_unlock(&dev->struct_mutex);
2983         }
2984 }
2985
2986 /* Prepare for a mode set.
2987  *
2988  * Note we could be a lot smarter here.  We need to figure out which outputs
2989  * will be enabled, which disabled (in short, how the config will changes)
2990  * and perform the minimum necessary steps to accomplish that, e.g. updating
2991  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2992  * panel fitting is in the proper state, etc.
2993  */
2994 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2995 {
2996         i9xx_crtc_disable(crtc);
2997 }
2998
2999 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3000 {
3001         i9xx_crtc_enable(crtc);
3002 }
3003
3004 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3005 {
3006         ironlake_crtc_disable(crtc);
3007 }
3008
3009 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3010 {
3011         ironlake_crtc_enable(crtc);
3012 }
3013
3014 void intel_encoder_prepare (struct drm_encoder *encoder)
3015 {
3016         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3017         /* lvds has its own version of prepare see intel_lvds_prepare */
3018         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3019 }
3020
3021 void intel_encoder_commit (struct drm_encoder *encoder)
3022 {
3023         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3024         /* lvds has its own version of commit see intel_lvds_commit */
3025         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3026 }
3027
3028 void intel_encoder_destroy(struct drm_encoder *encoder)
3029 {
3030         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3031
3032         drm_encoder_cleanup(encoder);
3033         kfree(intel_encoder);
3034 }
3035
3036 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3037                                   struct drm_display_mode *mode,
3038                                   struct drm_display_mode *adjusted_mode)
3039 {
3040         struct drm_device *dev = crtc->dev;
3041
3042         if (HAS_PCH_SPLIT(dev)) {
3043                 /* FDI link clock is fixed at 2.7G */
3044                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3045                         return false;
3046         }
3047
3048         /* XXX some encoders set the crtcinfo, others don't.
3049          * Obviously we need some form of conflict resolution here...
3050          */
3051         if (adjusted_mode->crtc_htotal == 0)
3052                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3053
3054         return true;
3055 }
3056
3057 static int i945_get_display_clock_speed(struct drm_device *dev)
3058 {
3059         return 400000;
3060 }
3061
3062 static int i915_get_display_clock_speed(struct drm_device *dev)
3063 {
3064         return 333000;
3065 }
3066
3067 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3068 {
3069         return 200000;
3070 }
3071
3072 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3073 {
3074         u16 gcfgc = 0;
3075
3076         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3077
3078         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3079                 return 133000;
3080         else {
3081                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3082                 case GC_DISPLAY_CLOCK_333_MHZ:
3083                         return 333000;
3084                 default:
3085                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3086                         return 190000;
3087                 }
3088         }
3089 }
3090
3091 static int i865_get_display_clock_speed(struct drm_device *dev)
3092 {
3093         return 266000;
3094 }
3095
3096 static int i855_get_display_clock_speed(struct drm_device *dev)
3097 {
3098         u16 hpllcc = 0;
3099         /* Assume that the hardware is in the high speed state.  This
3100          * should be the default.
3101          */
3102         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3103         case GC_CLOCK_133_200:
3104         case GC_CLOCK_100_200:
3105                 return 200000;
3106         case GC_CLOCK_166_250:
3107                 return 250000;
3108         case GC_CLOCK_100_133:
3109                 return 133000;
3110         }
3111
3112         /* Shouldn't happen */
3113         return 0;
3114 }
3115
3116 static int i830_get_display_clock_speed(struct drm_device *dev)
3117 {
3118         return 133000;
3119 }
3120
3121 struct fdi_m_n {
3122         u32        tu;
3123         u32        gmch_m;
3124         u32        gmch_n;
3125         u32        link_m;
3126         u32        link_n;
3127 };
3128
3129 static void
3130 fdi_reduce_ratio(u32 *num, u32 *den)
3131 {
3132         while (*num > 0xffffff || *den > 0xffffff) {
3133                 *num >>= 1;
3134                 *den >>= 1;
3135         }
3136 }
3137
3138 static void
3139 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3140                      int link_clock, struct fdi_m_n *m_n)
3141 {
3142         m_n->tu = 64; /* default size */
3143
3144         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3145         m_n->gmch_m = bits_per_pixel * pixel_clock;
3146         m_n->gmch_n = link_clock * nlanes * 8;
3147         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3148
3149         m_n->link_m = pixel_clock;
3150         m_n->link_n = link_clock;
3151         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3152 }
3153
3154
3155 struct intel_watermark_params {
3156         unsigned long fifo_size;
3157         unsigned long max_wm;
3158         unsigned long default_wm;
3159         unsigned long guard_size;
3160         unsigned long cacheline_size;
3161 };
3162
3163 /* Pineview has different values for various configs */
3164 static const struct intel_watermark_params pineview_display_wm = {
3165         PINEVIEW_DISPLAY_FIFO,
3166         PINEVIEW_MAX_WM,
3167         PINEVIEW_DFT_WM,
3168         PINEVIEW_GUARD_WM,
3169         PINEVIEW_FIFO_LINE_SIZE
3170 };
3171 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3172         PINEVIEW_DISPLAY_FIFO,
3173         PINEVIEW_MAX_WM,
3174         PINEVIEW_DFT_HPLLOFF_WM,
3175         PINEVIEW_GUARD_WM,
3176         PINEVIEW_FIFO_LINE_SIZE
3177 };
3178 static const struct intel_watermark_params pineview_cursor_wm = {
3179         PINEVIEW_CURSOR_FIFO,
3180         PINEVIEW_CURSOR_MAX_WM,
3181         PINEVIEW_CURSOR_DFT_WM,
3182         PINEVIEW_CURSOR_GUARD_WM,
3183         PINEVIEW_FIFO_LINE_SIZE,
3184 };
3185 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3186         PINEVIEW_CURSOR_FIFO,
3187         PINEVIEW_CURSOR_MAX_WM,
3188         PINEVIEW_CURSOR_DFT_WM,
3189         PINEVIEW_CURSOR_GUARD_WM,
3190         PINEVIEW_FIFO_LINE_SIZE
3191 };
3192 static const struct intel_watermark_params g4x_wm_info = {
3193         G4X_FIFO_SIZE,
3194         G4X_MAX_WM,
3195         G4X_MAX_WM,
3196         2,
3197         G4X_FIFO_LINE_SIZE,
3198 };
3199 static const struct intel_watermark_params g4x_cursor_wm_info = {
3200         I965_CURSOR_FIFO,
3201         I965_CURSOR_MAX_WM,
3202         I965_CURSOR_DFT_WM,
3203         2,
3204         G4X_FIFO_LINE_SIZE,
3205 };
3206 static const struct intel_watermark_params i965_cursor_wm_info = {
3207         I965_CURSOR_FIFO,
3208         I965_CURSOR_MAX_WM,
3209         I965_CURSOR_DFT_WM,
3210         2,
3211         I915_FIFO_LINE_SIZE,
3212 };
3213 static const struct intel_watermark_params i945_wm_info = {
3214         I945_FIFO_SIZE,
3215         I915_MAX_WM,
3216         1,
3217         2,
3218         I915_FIFO_LINE_SIZE
3219 };
3220 static const struct intel_watermark_params i915_wm_info = {
3221         I915_FIFO_SIZE,
3222         I915_MAX_WM,
3223         1,
3224         2,
3225         I915_FIFO_LINE_SIZE
3226 };
3227 static const struct intel_watermark_params i855_wm_info = {
3228         I855GM_FIFO_SIZE,
3229         I915_MAX_WM,
3230         1,
3231         2,
3232         I830_FIFO_LINE_SIZE
3233 };
3234 static const struct intel_watermark_params i830_wm_info = {
3235         I830_FIFO_SIZE,
3236         I915_MAX_WM,
3237         1,
3238         2,
3239         I830_FIFO_LINE_SIZE
3240 };
3241
3242 static const struct intel_watermark_params ironlake_display_wm_info = {
3243         ILK_DISPLAY_FIFO,
3244         ILK_DISPLAY_MAXWM,
3245         ILK_DISPLAY_DFTWM,
3246         2,
3247         ILK_FIFO_LINE_SIZE
3248 };
3249 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3250         ILK_CURSOR_FIFO,
3251         ILK_CURSOR_MAXWM,
3252         ILK_CURSOR_DFTWM,
3253         2,
3254         ILK_FIFO_LINE_SIZE
3255 };
3256 static const struct intel_watermark_params ironlake_display_srwm_info = {
3257         ILK_DISPLAY_SR_FIFO,
3258         ILK_DISPLAY_MAX_SRWM,
3259         ILK_DISPLAY_DFT_SRWM,
3260         2,
3261         ILK_FIFO_LINE_SIZE
3262 };
3263 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3264         ILK_CURSOR_SR_FIFO,
3265         ILK_CURSOR_MAX_SRWM,
3266         ILK_CURSOR_DFT_SRWM,
3267         2,
3268         ILK_FIFO_LINE_SIZE
3269 };
3270
3271 static const struct intel_watermark_params sandybridge_display_wm_info = {
3272         SNB_DISPLAY_FIFO,
3273         SNB_DISPLAY_MAXWM,
3274         SNB_DISPLAY_DFTWM,
3275         2,
3276         SNB_FIFO_LINE_SIZE
3277 };
3278 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3279         SNB_CURSOR_FIFO,
3280         SNB_CURSOR_MAXWM,
3281         SNB_CURSOR_DFTWM,
3282         2,
3283         SNB_FIFO_LINE_SIZE
3284 };
3285 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3286         SNB_DISPLAY_SR_FIFO,
3287         SNB_DISPLAY_MAX_SRWM,
3288         SNB_DISPLAY_DFT_SRWM,
3289         2,
3290         SNB_FIFO_LINE_SIZE
3291 };
3292 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3293         SNB_CURSOR_SR_FIFO,
3294         SNB_CURSOR_MAX_SRWM,
3295         SNB_CURSOR_DFT_SRWM,
3296         2,
3297         SNB_FIFO_LINE_SIZE
3298 };
3299
3300
3301 /**
3302  * intel_calculate_wm - calculate watermark level
3303  * @clock_in_khz: pixel clock
3304  * @wm: chip FIFO params
3305  * @pixel_size: display pixel size
3306  * @latency_ns: memory latency for the platform
3307  *
3308  * Calculate the watermark level (the level at which the display plane will
3309  * start fetching from memory again).  Each chip has a different display
3310  * FIFO size and allocation, so the caller needs to figure that out and pass
3311  * in the correct intel_watermark_params structure.
3312  *
3313  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3314  * on the pixel size.  When it reaches the watermark level, it'll start
3315  * fetching FIFO line sized based chunks from memory until the FIFO fills
3316  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3317  * will occur, and a display engine hang could result.
3318  */
3319 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3320                                         const struct intel_watermark_params *wm,
3321                                         int fifo_size,
3322                                         int pixel_size,
3323                                         unsigned long latency_ns)
3324 {
3325         long entries_required, wm_size;
3326
3327         /*
3328          * Note: we need to make sure we don't overflow for various clock &
3329          * latency values.
3330          * clocks go from a few thousand to several hundred thousand.
3331          * latency is usually a few thousand
3332          */
3333         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3334                 1000;
3335         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3336
3337         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3338
3339         wm_size = fifo_size - (entries_required + wm->guard_size);
3340
3341         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3342
3343         /* Don't promote wm_size to unsigned... */
3344         if (wm_size > (long)wm->max_wm)
3345                 wm_size = wm->max_wm;
3346         if (wm_size <= 0)
3347                 wm_size = wm->default_wm;
3348         return wm_size;
3349 }
3350
3351 struct cxsr_latency {
3352         int is_desktop;
3353         int is_ddr3;
3354         unsigned long fsb_freq;
3355         unsigned long mem_freq;
3356         unsigned long display_sr;
3357         unsigned long display_hpll_disable;
3358         unsigned long cursor_sr;
3359         unsigned long cursor_hpll_disable;
3360 };
3361
3362 static const struct cxsr_latency cxsr_latency_table[] = {
3363         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3364         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3365         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3366         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3367         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3368
3369         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3370         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3371         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3372         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3373         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3374
3375         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3376         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3377         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3378         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3379         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3380
3381         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3382         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3383         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3384         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3385         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3386
3387         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3388         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3389         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3390         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3391         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3392
3393         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3394         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3395         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3396         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3397         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3398 };
3399
3400 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3401                                                          int is_ddr3,
3402                                                          int fsb,
3403                                                          int mem)
3404 {
3405         const struct cxsr_latency *latency;
3406         int i;
3407
3408         if (fsb == 0 || mem == 0)
3409                 return NULL;
3410
3411         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3412                 latency = &cxsr_latency_table[i];
3413                 if (is_desktop == latency->is_desktop &&
3414                     is_ddr3 == latency->is_ddr3 &&
3415                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3416                         return latency;
3417         }
3418
3419         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3420
3421         return NULL;
3422 }
3423
3424 static void pineview_disable_cxsr(struct drm_device *dev)
3425 {
3426         struct drm_i915_private *dev_priv = dev->dev_private;
3427
3428         /* deactivate cxsr */
3429         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3430 }
3431
3432 /*
3433  * Latency for FIFO fetches is dependent on several factors:
3434  *   - memory configuration (speed, channels)
3435  *   - chipset
3436  *   - current MCH state
3437  * It can be fairly high in some situations, so here we assume a fairly
3438  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3439  * set this value too high, the FIFO will fetch frequently to stay full)
3440  * and power consumption (set it too low to save power and we might see
3441  * FIFO underruns and display "flicker").
3442  *
3443  * A value of 5us seems to be a good balance; safe for very low end
3444  * platforms but not overly aggressive on lower latency configs.
3445  */
3446 static const int latency_ns = 5000;
3447
3448 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3449 {
3450         struct drm_i915_private *dev_priv = dev->dev_private;
3451         uint32_t dsparb = I915_READ(DSPARB);
3452         int size;
3453
3454         size = dsparb & 0x7f;
3455         if (plane)
3456                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3457
3458         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3459                       plane ? "B" : "A", size);
3460
3461         return size;
3462 }
3463
3464 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3465 {
3466         struct drm_i915_private *dev_priv = dev->dev_private;
3467         uint32_t dsparb = I915_READ(DSPARB);
3468         int size;
3469
3470         size = dsparb & 0x1ff;
3471         if (plane)
3472                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3473         size >>= 1; /* Convert to cachelines */
3474
3475         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3476                       plane ? "B" : "A", size);
3477
3478         return size;
3479 }
3480
3481 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3482 {
3483         struct drm_i915_private *dev_priv = dev->dev_private;
3484         uint32_t dsparb = I915_READ(DSPARB);
3485         int size;
3486
3487         size = dsparb & 0x7f;
3488         size >>= 2; /* Convert to cachelines */
3489
3490         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3491                       plane ? "B" : "A",
3492                       size);
3493
3494         return size;
3495 }
3496
3497 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3498 {
3499         struct drm_i915_private *dev_priv = dev->dev_private;
3500         uint32_t dsparb = I915_READ(DSPARB);
3501         int size;
3502
3503         size = dsparb & 0x7f;
3504         size >>= 1; /* Convert to cachelines */
3505
3506         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3507                       plane ? "B" : "A", size);
3508
3509         return size;
3510 }
3511
3512 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3513 {
3514         struct drm_crtc *crtc, *enabled = NULL;
3515
3516         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3517                 if (crtc->enabled && crtc->fb) {
3518                         if (enabled)
3519                                 return NULL;
3520                         enabled = crtc;
3521                 }
3522         }
3523
3524         return enabled;
3525 }
3526
3527 static void pineview_update_wm(struct drm_device *dev)
3528 {
3529         struct drm_i915_private *dev_priv = dev->dev_private;
3530         struct drm_crtc *crtc;
3531         const struct cxsr_latency *latency;
3532         u32 reg;
3533         unsigned long wm;
3534
3535         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3536                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3537         if (!latency) {
3538                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3539                 pineview_disable_cxsr(dev);
3540                 return;
3541         }
3542
3543         crtc = single_enabled_crtc(dev);
3544         if (crtc) {
3545                 int clock = crtc->mode.clock;
3546                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3547
3548                 /* Display SR */
3549                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3550                                         pineview_display_wm.fifo_size,
3551                                         pixel_size, latency->display_sr);
3552                 reg = I915_READ(DSPFW1);
3553                 reg &= ~DSPFW_SR_MASK;
3554                 reg |= wm << DSPFW_SR_SHIFT;
3555                 I915_WRITE(DSPFW1, reg);
3556                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3557
3558                 /* cursor SR */
3559                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3560                                         pineview_display_wm.fifo_size,
3561                                         pixel_size, latency->cursor_sr);
3562                 reg = I915_READ(DSPFW3);
3563                 reg &= ~DSPFW_CURSOR_SR_MASK;
3564                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3565                 I915_WRITE(DSPFW3, reg);
3566
3567                 /* Display HPLL off SR */
3568                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3569                                         pineview_display_hplloff_wm.fifo_size,
3570                                         pixel_size, latency->display_hpll_disable);
3571                 reg = I915_READ(DSPFW3);
3572                 reg &= ~DSPFW_HPLL_SR_MASK;
3573                 reg |= wm & DSPFW_HPLL_SR_MASK;
3574                 I915_WRITE(DSPFW3, reg);
3575
3576                 /* cursor HPLL off SR */
3577                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3578                                         pineview_display_hplloff_wm.fifo_size,
3579                                         pixel_size, latency->cursor_hpll_disable);
3580                 reg = I915_READ(DSPFW3);
3581                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3582                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3583                 I915_WRITE(DSPFW3, reg);
3584                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3585
3586                 /* activate cxsr */
3587                 I915_WRITE(DSPFW3,
3588                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3589                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3590         } else {
3591                 pineview_disable_cxsr(dev);
3592                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3593         }
3594 }
3595
3596 static bool g4x_compute_wm0(struct drm_device *dev,
3597                             int plane,
3598                             const struct intel_watermark_params *display,
3599                             int display_latency_ns,
3600                             const struct intel_watermark_params *cursor,
3601                             int cursor_latency_ns,
3602                             int *plane_wm,
3603                             int *cursor_wm)
3604 {
3605         struct drm_crtc *crtc;
3606         int htotal, hdisplay, clock, pixel_size;
3607         int line_time_us, line_count;
3608         int entries, tlb_miss;
3609
3610         crtc = intel_get_crtc_for_plane(dev, plane);
3611         if (crtc->fb == NULL || !crtc->enabled) {
3612                 *cursor_wm = cursor->guard_size;
3613                 *plane_wm = display->guard_size;
3614                 return false;
3615         }
3616
3617         htotal = crtc->mode.htotal;
3618         hdisplay = crtc->mode.hdisplay;
3619         clock = crtc->mode.clock;
3620         pixel_size = crtc->fb->bits_per_pixel / 8;
3621
3622         /* Use the small buffer method to calculate plane watermark */
3623         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3624         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3625         if (tlb_miss > 0)
3626                 entries += tlb_miss;
3627         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3628         *plane_wm = entries + display->guard_size;
3629         if (*plane_wm > (int)display->max_wm)
3630                 *plane_wm = display->max_wm;
3631
3632         /* Use the large buffer method to calculate cursor watermark */
3633         line_time_us = ((htotal * 1000) / clock);
3634         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3635         entries = line_count * 64 * pixel_size;
3636         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3637         if (tlb_miss > 0)
3638                 entries += tlb_miss;
3639         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3640         *cursor_wm = entries + cursor->guard_size;
3641         if (*cursor_wm > (int)cursor->max_wm)
3642                 *cursor_wm = (int)cursor->max_wm;
3643
3644         return true;
3645 }
3646
3647 /*
3648  * Check the wm result.
3649  *
3650  * If any calculated watermark values is larger than the maximum value that
3651  * can be programmed into the associated watermark register, that watermark
3652  * must be disabled.
3653  */
3654 static bool g4x_check_srwm(struct drm_device *dev,
3655                            int display_wm, int cursor_wm,
3656                            const struct intel_watermark_params *display,
3657                            const struct intel_watermark_params *cursor)
3658 {
3659         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3660                       display_wm, cursor_wm);
3661
3662         if (display_wm > display->max_wm) {
3663                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3664                               display_wm, display->max_wm);
3665                 return false;
3666         }
3667
3668         if (cursor_wm > cursor->max_wm) {
3669                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3670                               cursor_wm, cursor->max_wm);
3671                 return false;
3672         }
3673
3674         if (!(display_wm || cursor_wm)) {
3675                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3676                 return false;
3677         }
3678
3679         return true;
3680 }
3681
3682 static bool g4x_compute_srwm(struct drm_device *dev,
3683                              int plane,
3684                              int latency_ns,
3685                              const struct intel_watermark_params *display,
3686                              const struct intel_watermark_params *cursor,
3687                              int *display_wm, int *cursor_wm)
3688 {
3689         struct drm_crtc *crtc;
3690         int hdisplay, htotal, pixel_size, clock;
3691         unsigned long line_time_us;
3692         int line_count, line_size;
3693         int small, large;
3694         int entries;
3695
3696         if (!latency_ns) {
3697                 *display_wm = *cursor_wm = 0;
3698                 return false;
3699         }
3700
3701         crtc = intel_get_crtc_for_plane(dev, plane);
3702         hdisplay = crtc->mode.hdisplay;
3703         htotal = crtc->mode.htotal;
3704         clock = crtc->mode.clock;
3705         pixel_size = crtc->fb->bits_per_pixel / 8;
3706
3707         line_time_us = (htotal * 1000) / clock;
3708         line_count = (latency_ns / line_time_us + 1000) / 1000;
3709         line_size = hdisplay * pixel_size;
3710
3711         /* Use the minimum of the small and large buffer method for primary */
3712         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3713         large = line_count * line_size;
3714
3715         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3716         *display_wm = entries + display->guard_size;
3717
3718         /* calculate the self-refresh watermark for display cursor */
3719         entries = line_count * pixel_size * 64;
3720         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3721         *cursor_wm = entries + cursor->guard_size;
3722
3723         return g4x_check_srwm(dev,
3724                               *display_wm, *cursor_wm,
3725                               display, cursor);
3726 }
3727
3728 #define single_plane_enabled(mask) is_power_of_2(mask)
3729
3730 static void g4x_update_wm(struct drm_device *dev)
3731 {
3732         static const int sr_latency_ns = 12000;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3735         int plane_sr, cursor_sr;
3736         unsigned int enabled = 0;
3737
3738         if (g4x_compute_wm0(dev, 0,
3739                             &g4x_wm_info, latency_ns,
3740                             &g4x_cursor_wm_info, latency_ns,
3741                             &planea_wm, &cursora_wm))
3742                 enabled |= 1;
3743
3744         if (g4x_compute_wm0(dev, 1,
3745                             &g4x_wm_info, latency_ns,
3746                             &g4x_cursor_wm_info, latency_ns,
3747                             &planeb_wm, &cursorb_wm))
3748                 enabled |= 2;
3749
3750         plane_sr = cursor_sr = 0;
3751         if (single_plane_enabled(enabled) &&
3752             g4x_compute_srwm(dev, ffs(enabled) - 1,
3753                              sr_latency_ns,
3754                              &g4x_wm_info,
3755                              &g4x_cursor_wm_info,
3756                              &plane_sr, &cursor_sr))
3757                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3758         else
3759                 I915_WRITE(FW_BLC_SELF,
3760                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3761
3762         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3763                       planea_wm, cursora_wm,
3764                       planeb_wm, cursorb_wm,
3765                       plane_sr, cursor_sr);
3766
3767         I915_WRITE(DSPFW1,
3768                    (plane_sr << DSPFW_SR_SHIFT) |
3769                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3770                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3771                    planea_wm);
3772         I915_WRITE(DSPFW2,
3773                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3774                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3775         /* HPLL off in SR has some issues on G4x... disable it */
3776         I915_WRITE(DSPFW3,
3777                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3778                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3779 }
3780
3781 static void i965_update_wm(struct drm_device *dev)
3782 {
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784         struct drm_crtc *crtc;
3785         int srwm = 1;
3786         int cursor_sr = 16;
3787
3788         /* Calc sr entries for one plane configs */
3789         crtc = single_enabled_crtc(dev);
3790         if (crtc) {
3791                 /* self-refresh has much higher latency */
3792                 static const int sr_latency_ns = 12000;
3793                 int clock = crtc->mode.clock;
3794                 int htotal = crtc->mode.htotal;
3795                 int hdisplay = crtc->mode.hdisplay;
3796                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3797                 unsigned long line_time_us;
3798                 int entries;
3799
3800                 line_time_us = ((htotal * 1000) / clock);
3801
3802                 /* Use ns/us then divide to preserve precision */
3803                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3804                         pixel_size * hdisplay;
3805                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3806                 srwm = I965_FIFO_SIZE - entries;
3807                 if (srwm < 0)
3808                         srwm = 1;
3809                 srwm &= 0x1ff;
3810                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3811                               entries, srwm);
3812
3813                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3814                         pixel_size * 64;
3815                 entries = DIV_ROUND_UP(entries,
3816                                           i965_cursor_wm_info.cacheline_size);
3817                 cursor_sr = i965_cursor_wm_info.fifo_size -
3818                         (entries + i965_cursor_wm_info.guard_size);
3819
3820                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3821                         cursor_sr = i965_cursor_wm_info.max_wm;
3822
3823                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3824                               "cursor %d\n", srwm, cursor_sr);
3825
3826                 if (IS_CRESTLINE(dev))
3827                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3828         } else {
3829                 /* Turn off self refresh if both pipes are enabled */
3830                 if (IS_CRESTLINE(dev))
3831                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3832                                    & ~FW_BLC_SELF_EN);
3833         }
3834
3835         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3836                       srwm);
3837
3838         /* 965 has limitations... */
3839         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3840                    (8 << 16) | (8 << 8) | (8 << 0));
3841         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3842         /* update cursor SR watermark */
3843         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3844 }
3845
3846 static void i9xx_update_wm(struct drm_device *dev)
3847 {
3848         struct drm_i915_private *dev_priv = dev->dev_private;
3849         const struct intel_watermark_params *wm_info;
3850         uint32_t fwater_lo;
3851         uint32_t fwater_hi;
3852         int cwm, srwm = 1;
3853         int fifo_size;
3854         int planea_wm, planeb_wm;
3855         struct drm_crtc *crtc, *enabled = NULL;
3856
3857         if (IS_I945GM(dev))
3858                 wm_info = &i945_wm_info;
3859         else if (!IS_GEN2(dev))
3860                 wm_info = &i915_wm_info;
3861         else
3862                 wm_info = &i855_wm_info;
3863
3864         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3865         crtc = intel_get_crtc_for_plane(dev, 0);
3866         if (crtc->enabled && crtc->fb) {
3867                 planea_wm = intel_calculate_wm(crtc->mode.clock,
3868                                                wm_info, fifo_size,
3869                                                crtc->fb->bits_per_pixel / 8,
3870                                                latency_ns);
3871                 enabled = crtc;
3872         } else
3873                 planea_wm = fifo_size - wm_info->guard_size;
3874
3875         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3876         crtc = intel_get_crtc_for_plane(dev, 1);
3877         if (crtc->enabled && crtc->fb) {
3878                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3879                                                wm_info, fifo_size,
3880                                                crtc->fb->bits_per_pixel / 8,
3881                                                latency_ns);
3882                 if (enabled == NULL)
3883                         enabled = crtc;
3884                 else
3885                         enabled = NULL;
3886         } else
3887                 planeb_wm = fifo_size - wm_info->guard_size;
3888
3889         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3890
3891         /*
3892          * Overlay gets an aggressive default since video jitter is bad.
3893          */
3894         cwm = 2;
3895
3896         /* Play safe and disable self-refresh before adjusting watermarks. */
3897         if (IS_I945G(dev) || IS_I945GM(dev))
3898                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3899         else if (IS_I915GM(dev))
3900                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3901
3902         /* Calc sr entries for one plane configs */
3903         if (HAS_FW_BLC(dev) && enabled) {
3904                 /* self-refresh has much higher latency */
3905                 static const int sr_latency_ns = 6000;
3906                 int clock = enabled->mode.clock;
3907                 int htotal = enabled->mode.htotal;
3908                 int hdisplay = enabled->mode.hdisplay;
3909                 int pixel_size = enabled->fb->bits_per_pixel / 8;
3910                 unsigned long line_time_us;
3911                 int entries;
3912
3913                 line_time_us = (htotal * 1000) / clock;
3914
3915                 /* Use ns/us then divide to preserve precision */
3916                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3917                         pixel_size * hdisplay;
3918                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3919                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3920                 srwm = wm_info->fifo_size - entries;
3921                 if (srwm < 0)
3922                         srwm = 1;
3923
3924                 if (IS_I945G(dev) || IS_I945GM(dev))
3925                         I915_WRITE(FW_BLC_SELF,
3926                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3927                 else if (IS_I915GM(dev))
3928                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3929         }
3930
3931         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3932                       planea_wm, planeb_wm, cwm, srwm);
3933
3934         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3935         fwater_hi = (cwm & 0x1f);
3936
3937         /* Set request length to 8 cachelines per fetch */
3938         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3939         fwater_hi = fwater_hi | (1 << 8);
3940
3941         I915_WRITE(FW_BLC, fwater_lo);
3942         I915_WRITE(FW_BLC2, fwater_hi);
3943
3944         if (HAS_FW_BLC(dev)) {
3945                 if (enabled) {
3946                         if (IS_I945G(dev) || IS_I945GM(dev))
3947                                 I915_WRITE(FW_BLC_SELF,
3948                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3949                         else if (IS_I915GM(dev))
3950                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3951                         DRM_DEBUG_KMS("memory self refresh enabled\n");
3952                 } else
3953                         DRM_DEBUG_KMS("memory self refresh disabled\n");
3954         }
3955 }
3956
3957 static void i830_update_wm(struct drm_device *dev)
3958 {
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         struct drm_crtc *crtc;
3961         uint32_t fwater_lo;
3962         int planea_wm;
3963
3964         crtc = single_enabled_crtc(dev);
3965         if (crtc == NULL)
3966                 return;
3967
3968         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3969                                        dev_priv->display.get_fifo_size(dev, 0),
3970                                        crtc->fb->bits_per_pixel / 8,
3971                                        latency_ns);
3972         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3973         fwater_lo |= (3<<8) | planea_wm;
3974
3975         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3976
3977         I915_WRITE(FW_BLC, fwater_lo);
3978 }
3979
3980 #define ILK_LP0_PLANE_LATENCY           700
3981 #define ILK_LP0_CURSOR_LATENCY          1300
3982
3983 /*
3984  * Check the wm result.
3985  *
3986  * If any calculated watermark values is larger than the maximum value that
3987  * can be programmed into the associated watermark register, that watermark
3988  * must be disabled.
3989  */
3990 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3991                                 int fbc_wm, int display_wm, int cursor_wm,
3992                                 const struct intel_watermark_params *display,
3993                                 const struct intel_watermark_params *cursor)
3994 {
3995         struct drm_i915_private *dev_priv = dev->dev_private;
3996
3997         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3998                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3999
4000         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4001                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4002                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4003
4004                 /* fbc has it's own way to disable FBC WM */
4005                 I915_WRITE(DISP_ARB_CTL,
4006                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4007                 return false;
4008         }
4009
4010         if (display_wm > display->max_wm) {
4011                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4012                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4013                 return false;
4014         }
4015
4016         if (cursor_wm > cursor->max_wm) {
4017                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4018                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4019                 return false;
4020         }
4021
4022         if (!(fbc_wm || display_wm || cursor_wm)) {
4023                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4024                 return false;
4025         }
4026
4027         return true;
4028 }
4029
4030 /*
4031  * Compute watermark values of WM[1-3],
4032  */
4033 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4034                                   int latency_ns,
4035                                   const struct intel_watermark_params *display,
4036                                   const struct intel_watermark_params *cursor,
4037                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4038 {
4039         struct drm_crtc *crtc;
4040         unsigned long line_time_us;
4041         int hdisplay, htotal, pixel_size, clock;
4042         int line_count, line_size;
4043         int small, large;
4044         int entries;
4045
4046         if (!latency_ns) {
4047                 *fbc_wm = *display_wm = *cursor_wm = 0;
4048                 return false;
4049         }
4050
4051         crtc = intel_get_crtc_for_plane(dev, plane);
4052         hdisplay = crtc->mode.hdisplay;
4053         htotal = crtc->mode.htotal;
4054         clock = crtc->mode.clock;
4055         pixel_size = crtc->fb->bits_per_pixel / 8;
4056
4057         line_time_us = (htotal * 1000) / clock;
4058         line_count = (latency_ns / line_time_us + 1000) / 1000;
4059         line_size = hdisplay * pixel_size;
4060
4061         /* Use the minimum of the small and large buffer method for primary */
4062         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4063         large = line_count * line_size;
4064
4065         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4066         *display_wm = entries + display->guard_size;
4067
4068         /*
4069          * Spec says:
4070          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4071          */
4072         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4073
4074         /* calculate the self-refresh watermark for display cursor */
4075         entries = line_count * pixel_size * 64;
4076         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4077         *cursor_wm = entries + cursor->guard_size;
4078
4079         return ironlake_check_srwm(dev, level,
4080                                    *fbc_wm, *display_wm, *cursor_wm,
4081                                    display, cursor);
4082 }
4083
4084 static void ironlake_update_wm(struct drm_device *dev)
4085 {
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         int fbc_wm, plane_wm, cursor_wm;
4088         unsigned int enabled;
4089
4090         enabled = 0;
4091         if (g4x_compute_wm0(dev, 0,
4092                             &ironlake_display_wm_info,
4093                             ILK_LP0_PLANE_LATENCY,
4094                             &ironlake_cursor_wm_info,
4095                             ILK_LP0_CURSOR_LATENCY,
4096                             &plane_wm, &cursor_wm)) {
4097                 I915_WRITE(WM0_PIPEA_ILK,
4098                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4099                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4100                               " plane %d, " "cursor: %d\n",
4101                               plane_wm, cursor_wm);
4102                 enabled |= 1;
4103         }
4104
4105         if (g4x_compute_wm0(dev, 1,
4106                             &ironlake_display_wm_info,
4107                             ILK_LP0_PLANE_LATENCY,
4108                             &ironlake_cursor_wm_info,
4109                             ILK_LP0_CURSOR_LATENCY,
4110                             &plane_wm, &cursor_wm)) {
4111                 I915_WRITE(WM0_PIPEB_ILK,
4112                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4113                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4114                               " plane %d, cursor: %d\n",
4115                               plane_wm, cursor_wm);
4116                 enabled |= 2;
4117         }
4118
4119         /*
4120          * Calculate and update the self-refresh watermark only when one
4121          * display plane is used.
4122          */
4123         I915_WRITE(WM3_LP_ILK, 0);
4124         I915_WRITE(WM2_LP_ILK, 0);
4125         I915_WRITE(WM1_LP_ILK, 0);
4126
4127         if (!single_plane_enabled(enabled))
4128                 return;
4129         enabled = ffs(enabled) - 1;
4130
4131         /* WM1 */
4132         if (!ironlake_compute_srwm(dev, 1, enabled,
4133                                    ILK_READ_WM1_LATENCY() * 500,
4134                                    &ironlake_display_srwm_info,
4135                                    &ironlake_cursor_srwm_info,
4136                                    &fbc_wm, &plane_wm, &cursor_wm))
4137                 return;
4138
4139         I915_WRITE(WM1_LP_ILK,
4140                    WM1_LP_SR_EN |
4141                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4142                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4143                    (plane_wm << WM1_LP_SR_SHIFT) |
4144                    cursor_wm);
4145
4146         /* WM2 */
4147         if (!ironlake_compute_srwm(dev, 2, enabled,
4148                                    ILK_READ_WM2_LATENCY() * 500,
4149                                    &ironlake_display_srwm_info,
4150                                    &ironlake_cursor_srwm_info,
4151                                    &fbc_wm, &plane_wm, &cursor_wm))
4152                 return;
4153
4154         I915_WRITE(WM2_LP_ILK,
4155                    WM2_LP_EN |
4156                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4157                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4158                    (plane_wm << WM1_LP_SR_SHIFT) |
4159                    cursor_wm);
4160
4161         /*
4162          * WM3 is unsupported on ILK, probably because we don't have latency
4163          * data for that power state
4164          */
4165 }
4166
4167 static void sandybridge_update_wm(struct drm_device *dev)
4168 {
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4171         int fbc_wm, plane_wm, cursor_wm;
4172         unsigned int enabled;
4173
4174         enabled = 0;
4175         if (g4x_compute_wm0(dev, 0,
4176                             &sandybridge_display_wm_info, latency,
4177                             &sandybridge_cursor_wm_info, latency,
4178                             &plane_wm, &cursor_wm)) {
4179                 I915_WRITE(WM0_PIPEA_ILK,
4180                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4181                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4182                               " plane %d, " "cursor: %d\n",
4183                               plane_wm, cursor_wm);
4184                 enabled |= 1;
4185         }
4186
4187         if (g4x_compute_wm0(dev, 1,
4188                             &sandybridge_display_wm_info, latency,
4189                             &sandybridge_cursor_wm_info, latency,
4190                             &plane_wm, &cursor_wm)) {
4191                 I915_WRITE(WM0_PIPEB_ILK,
4192                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4193                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4194                               " plane %d, cursor: %d\n",
4195                               plane_wm, cursor_wm);
4196                 enabled |= 2;
4197         }
4198
4199         /*
4200          * Calculate and update the self-refresh watermark only when one
4201          * display plane is used.
4202          *
4203          * SNB support 3 levels of watermark.
4204          *
4205          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4206          * and disabled in the descending order
4207          *
4208          */
4209         I915_WRITE(WM3_LP_ILK, 0);
4210         I915_WRITE(WM2_LP_ILK, 0);
4211         I915_WRITE(WM1_LP_ILK, 0);
4212
4213         if (!single_plane_enabled(enabled))
4214                 return;
4215         enabled = ffs(enabled) - 1;
4216
4217         /* WM1 */
4218         if (!ironlake_compute_srwm(dev, 1, enabled,
4219                                    SNB_READ_WM1_LATENCY() * 500,
4220                                    &sandybridge_display_srwm_info,
4221                                    &sandybridge_cursor_srwm_info,
4222                                    &fbc_wm, &plane_wm, &cursor_wm))
4223                 return;
4224
4225         I915_WRITE(WM1_LP_ILK,
4226                    WM1_LP_SR_EN |
4227                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4228                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4229                    (plane_wm << WM1_LP_SR_SHIFT) |
4230                    cursor_wm);
4231
4232         /* WM2 */
4233         if (!ironlake_compute_srwm(dev, 2, enabled,
4234                                    SNB_READ_WM2_LATENCY() * 500,
4235                                    &sandybridge_display_srwm_info,
4236                                    &sandybridge_cursor_srwm_info,
4237                                    &fbc_wm, &plane_wm, &cursor_wm))
4238                 return;
4239
4240         I915_WRITE(WM2_LP_ILK,
4241                    WM2_LP_EN |
4242                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4243                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4244                    (plane_wm << WM1_LP_SR_SHIFT) |
4245                    cursor_wm);
4246
4247         /* WM3 */
4248         if (!ironlake_compute_srwm(dev, 3, enabled,
4249                                    SNB_READ_WM3_LATENCY() * 500,
4250                                    &sandybridge_display_srwm_info,
4251                                    &sandybridge_cursor_srwm_info,
4252                                    &fbc_wm, &plane_wm, &cursor_wm))
4253                 return;
4254
4255         I915_WRITE(WM3_LP_ILK,
4256                    WM3_LP_EN |
4257                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4258                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4259                    (plane_wm << WM1_LP_SR_SHIFT) |
4260                    cursor_wm);
4261 }
4262
4263 /**
4264  * intel_update_watermarks - update FIFO watermark values based on current modes
4265  *
4266  * Calculate watermark values for the various WM regs based on current mode
4267  * and plane configuration.
4268  *
4269  * There are several cases to deal with here:
4270  *   - normal (i.e. non-self-refresh)
4271  *   - self-refresh (SR) mode
4272  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4273  *   - lines are small relative to FIFO size (buffer can hold more than 2
4274  *     lines), so need to account for TLB latency
4275  *
4276  *   The normal calculation is:
4277  *     watermark = dotclock * bytes per pixel * latency
4278  *   where latency is platform & configuration dependent (we assume pessimal
4279  *   values here).
4280  *
4281  *   The SR calculation is:
4282  *     watermark = (trunc(latency/line time)+1) * surface width *
4283  *       bytes per pixel
4284  *   where
4285  *     line time = htotal / dotclock
4286  *     surface width = hdisplay for normal plane and 64 for cursor
4287  *   and latency is assumed to be high, as above.
4288  *
4289  * The final value programmed to the register should always be rounded up,
4290  * and include an extra 2 entries to account for clock crossings.
4291  *
4292  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4293  * to set the non-SR watermarks to 8.
4294  */
4295 static void intel_update_watermarks(struct drm_device *dev)
4296 {
4297         struct drm_i915_private *dev_priv = dev->dev_private;
4298
4299         if (dev_priv->display.update_wm)
4300                 dev_priv->display.update_wm(dev);
4301 }
4302
4303 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4304 {
4305         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4306 }
4307
4308 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4309                               struct drm_display_mode *mode,
4310                               struct drm_display_mode *adjusted_mode,
4311                               int x, int y,
4312                               struct drm_framebuffer *old_fb)
4313 {
4314         struct drm_device *dev = crtc->dev;
4315         struct drm_i915_private *dev_priv = dev->dev_private;
4316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317         int pipe = intel_crtc->pipe;
4318         int plane = intel_crtc->plane;
4319         int refclk, num_connectors = 0;
4320         intel_clock_t clock, reduced_clock;
4321         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4322         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4323         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4324         struct drm_mode_config *mode_config = &dev->mode_config;
4325         struct intel_encoder *encoder;
4326         const intel_limit_t *limit;
4327         int ret;
4328         u32 temp;
4329         u32 lvds_sync = 0;
4330
4331         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4332                 if (encoder->base.crtc != crtc)
4333                         continue;
4334
4335                 switch (encoder->type) {
4336                 case INTEL_OUTPUT_LVDS:
4337                         is_lvds = true;
4338                         break;
4339                 case INTEL_OUTPUT_SDVO:
4340                 case INTEL_OUTPUT_HDMI:
4341                         is_sdvo = true;
4342                         if (encoder->needs_tv_clock)
4343                                 is_tv = true;
4344                         break;
4345                 case INTEL_OUTPUT_DVO:
4346                         is_dvo = true;
4347                         break;
4348                 case INTEL_OUTPUT_TVOUT:
4349                         is_tv = true;
4350                         break;
4351                 case INTEL_OUTPUT_ANALOG:
4352                         is_crt = true;
4353                         break;
4354                 case INTEL_OUTPUT_DISPLAYPORT:
4355                         is_dp = true;
4356                         break;
4357                 }
4358
4359                 num_connectors++;
4360         }
4361
4362         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4363                 refclk = dev_priv->lvds_ssc_freq * 1000;
4364                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4365                               refclk / 1000);
4366         } else if (!IS_GEN2(dev)) {
4367                 refclk = 96000;
4368         } else {
4369                 refclk = 48000;
4370         }
4371
4372         /*
4373          * Returns a set of divisors for the desired target clock with the given
4374          * refclk, or FALSE.  The returned values represent the clock equation:
4375          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4376          */
4377         limit = intel_limit(crtc, refclk);
4378         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4379         if (!ok) {
4380                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4381                 return -EINVAL;
4382         }
4383
4384         /* Ensure that the cursor is valid for the new mode before changing... */
4385         intel_crtc_update_cursor(crtc, true);
4386
4387         if (is_lvds && dev_priv->lvds_downclock_avail) {
4388                 has_reduced_clock = limit->find_pll(limit, crtc,
4389                                                     dev_priv->lvds_downclock,
4390                                                     refclk,
4391                                                     &reduced_clock);
4392                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4393                         /*
4394                          * If the different P is found, it means that we can't
4395                          * switch the display clock by using the FP0/FP1.
4396                          * In such case we will disable the LVDS downclock
4397                          * feature.
4398                          */
4399                         DRM_DEBUG_KMS("Different P is found for "
4400                                       "LVDS clock/downclock\n");
4401                         has_reduced_clock = 0;
4402                 }
4403         }
4404         /* SDVO TV has fixed PLL values depend on its clock range,
4405            this mirrors vbios setting. */
4406         if (is_sdvo && is_tv) {
4407                 if (adjusted_mode->clock >= 100000
4408                     && adjusted_mode->clock < 140500) {
4409                         clock.p1 = 2;
4410                         clock.p2 = 10;
4411                         clock.n = 3;
4412                         clock.m1 = 16;
4413                         clock.m2 = 8;
4414                 } else if (adjusted_mode->clock >= 140500
4415                            && adjusted_mode->clock <= 200000) {
4416                         clock.p1 = 1;
4417                         clock.p2 = 10;
4418                         clock.n = 6;
4419                         clock.m1 = 12;
4420                         clock.m2 = 8;
4421                 }
4422         }
4423
4424         if (IS_PINEVIEW(dev)) {
4425                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4426                 if (has_reduced_clock)
4427                         fp2 = (1 << reduced_clock.n) << 16 |
4428                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4429         } else {
4430                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4431                 if (has_reduced_clock)
4432                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4433                                 reduced_clock.m2;
4434         }
4435
4436         dpll = DPLL_VGA_MODE_DIS;
4437
4438         if (!IS_GEN2(dev)) {
4439                 if (is_lvds)
4440                         dpll |= DPLLB_MODE_LVDS;
4441                 else
4442                         dpll |= DPLLB_MODE_DAC_SERIAL;
4443                 if (is_sdvo) {
4444                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4445                         if (pixel_multiplier > 1) {
4446                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4447                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4448                         }
4449                         dpll |= DPLL_DVO_HIGH_SPEED;
4450                 }
4451                 if (is_dp)
4452                         dpll |= DPLL_DVO_HIGH_SPEED;
4453
4454                 /* compute bitmask from p1 value */
4455                 if (IS_PINEVIEW(dev))
4456                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4457                 else {
4458                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4459                         if (IS_G4X(dev) && has_reduced_clock)
4460                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4461                 }
4462                 switch (clock.p2) {
4463                 case 5:
4464                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4465                         break;
4466                 case 7:
4467                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4468                         break;
4469                 case 10:
4470                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4471                         break;
4472                 case 14:
4473                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4474                         break;
4475                 }
4476                 if (INTEL_INFO(dev)->gen >= 4)
4477                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4478         } else {
4479                 if (is_lvds) {
4480                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4481                 } else {
4482                         if (clock.p1 == 2)
4483                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4484                         else
4485                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4486                         if (clock.p2 == 4)
4487                                 dpll |= PLL_P2_DIVIDE_BY_4;
4488                 }
4489         }
4490
4491         if (is_sdvo && is_tv)
4492                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4493         else if (is_tv)
4494                 /* XXX: just matching BIOS for now */
4495                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4496                 dpll |= 3;
4497         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4498                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4499         else
4500                 dpll |= PLL_REF_INPUT_DREFCLK;
4501
4502         /* setup pipeconf */
4503         pipeconf = I915_READ(PIPECONF(pipe));
4504
4505         /* Set up the display plane register */
4506         dspcntr = DISPPLANE_GAMMA_ENABLE;
4507
4508         /* Ironlake's plane is forced to pipe, bit 24 is to
4509            enable color space conversion */
4510         if (pipe == 0)
4511                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4512         else
4513                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4514
4515         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4516                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4517                  * core speed.
4518                  *
4519                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4520                  * pipe == 0 check?
4521                  */
4522                 if (mode->clock >
4523                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4524                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4525                 else
4526                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4527         }
4528
4529         dpll |= DPLL_VCO_ENABLE;
4530
4531         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4532         drm_mode_debug_printmodeline(mode);
4533
4534         I915_WRITE(FP0(pipe), fp);
4535         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4536
4537         POSTING_READ(DPLL(pipe));
4538         udelay(150);
4539
4540         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4541          * This is an exception to the general rule that mode_set doesn't turn
4542          * things on.
4543          */
4544         if (is_lvds) {
4545                 temp = I915_READ(LVDS);
4546                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4547                 if (pipe == 1) {
4548                         temp |= LVDS_PIPEB_SELECT;
4549                 } else {
4550                         temp &= ~LVDS_PIPEB_SELECT;
4551                 }
4552                 /* set the corresponsding LVDS_BORDER bit */
4553                 temp |= dev_priv->lvds_border_bits;
4554                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4555                  * set the DPLLs for dual-channel mode or not.
4556                  */
4557                 if (clock.p2 == 7)
4558                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4559                 else
4560                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4561
4562                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4563                  * appropriately here, but we need to look more thoroughly into how
4564                  * panels behave in the two modes.
4565                  */
4566                 /* set the dithering flag on LVDS as needed */
4567                 if (INTEL_INFO(dev)->gen >= 4) {
4568                         if (dev_priv->lvds_dither)
4569                                 temp |= LVDS_ENABLE_DITHER;
4570                         else
4571                                 temp &= ~LVDS_ENABLE_DITHER;
4572                 }
4573                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4574                         lvds_sync |= LVDS_HSYNC_POLARITY;
4575                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4576                         lvds_sync |= LVDS_VSYNC_POLARITY;
4577                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4578                     != lvds_sync) {
4579                         char flags[2] = "-+";
4580                         DRM_INFO("Changing LVDS panel from "
4581                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4582                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4583                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4584                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4585                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4586                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4587                         temp |= lvds_sync;
4588                 }
4589                 I915_WRITE(LVDS, temp);
4590         }
4591
4592         if (is_dp) {
4593                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4594         }
4595
4596         I915_WRITE(DPLL(pipe), dpll);
4597
4598         /* Wait for the clocks to stabilize. */
4599         POSTING_READ(DPLL(pipe));
4600         udelay(150);
4601
4602         if (INTEL_INFO(dev)->gen >= 4) {
4603                 temp = 0;
4604                 if (is_sdvo) {
4605                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4606                         if (temp > 1)
4607                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4608                         else
4609                                 temp = 0;
4610                 }
4611                 I915_WRITE(DPLL_MD(pipe), temp);
4612         } else {
4613                 /* The pixel multiplier can only be updated once the
4614                  * DPLL is enabled and the clocks are stable.
4615                  *
4616                  * So write it again.
4617                  */
4618                 I915_WRITE(DPLL(pipe), dpll);
4619         }
4620
4621         intel_crtc->lowfreq_avail = false;
4622         if (is_lvds && has_reduced_clock && i915_powersave) {
4623                 I915_WRITE(FP1(pipe), fp2);
4624                 intel_crtc->lowfreq_avail = true;
4625                 if (HAS_PIPE_CXSR(dev)) {
4626                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4627                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4628                 }
4629         } else {
4630                 I915_WRITE(FP1(pipe), fp);
4631                 if (HAS_PIPE_CXSR(dev)) {
4632                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4633                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4634                 }
4635         }
4636
4637         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4638                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4639                 /* the chip adds 2 halflines automatically */
4640                 adjusted_mode->crtc_vdisplay -= 1;
4641                 adjusted_mode->crtc_vtotal -= 1;
4642                 adjusted_mode->crtc_vblank_start -= 1;
4643                 adjusted_mode->crtc_vblank_end -= 1;
4644                 adjusted_mode->crtc_vsync_end -= 1;
4645                 adjusted_mode->crtc_vsync_start -= 1;
4646         } else
4647                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4648
4649         I915_WRITE(HTOTAL(pipe),
4650                    (adjusted_mode->crtc_hdisplay - 1) |
4651                    ((adjusted_mode->crtc_htotal - 1) << 16));
4652         I915_WRITE(HBLANK(pipe),
4653                    (adjusted_mode->crtc_hblank_start - 1) |
4654                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4655         I915_WRITE(HSYNC(pipe),
4656                    (adjusted_mode->crtc_hsync_start - 1) |
4657                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4658
4659         I915_WRITE(VTOTAL(pipe),
4660                    (adjusted_mode->crtc_vdisplay - 1) |
4661                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4662         I915_WRITE(VBLANK(pipe),
4663                    (adjusted_mode->crtc_vblank_start - 1) |
4664                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4665         I915_WRITE(VSYNC(pipe),
4666                    (adjusted_mode->crtc_vsync_start - 1) |
4667                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4668
4669         /* pipesrc and dspsize control the size that is scaled from,
4670          * which should always be the user's requested size.
4671          */
4672         I915_WRITE(DSPSIZE(plane),
4673                    ((mode->vdisplay - 1) << 16) |
4674                    (mode->hdisplay - 1));
4675         I915_WRITE(DSPPOS(plane), 0);
4676         I915_WRITE(PIPESRC(pipe),
4677                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4678
4679         I915_WRITE(PIPECONF(pipe), pipeconf);
4680         POSTING_READ(PIPECONF(pipe));
4681         intel_enable_pipe(dev_priv, pipe, false);
4682
4683         intel_wait_for_vblank(dev, pipe);
4684
4685         I915_WRITE(DSPCNTR(plane), dspcntr);
4686         POSTING_READ(DSPCNTR(plane));
4687         intel_enable_plane(dev_priv, plane, pipe);
4688
4689         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4690
4691         intel_update_watermarks(dev);
4692
4693         return ret;
4694 }
4695
4696 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4697                                   struct drm_display_mode *mode,
4698                                   struct drm_display_mode *adjusted_mode,
4699                                   int x, int y,
4700                                   struct drm_framebuffer *old_fb)
4701 {
4702         struct drm_device *dev = crtc->dev;
4703         struct drm_i915_private *dev_priv = dev->dev_private;
4704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4705         int pipe = intel_crtc->pipe;
4706         int plane = intel_crtc->plane;
4707         int refclk, num_connectors = 0;
4708         intel_clock_t clock, reduced_clock;
4709         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4710         bool ok, has_reduced_clock = false, is_sdvo = false;
4711         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4712         struct intel_encoder *has_edp_encoder = NULL;
4713         struct drm_mode_config *mode_config = &dev->mode_config;
4714         struct intel_encoder *encoder;
4715         const intel_limit_t *limit;
4716         int ret;
4717         struct fdi_m_n m_n = {0};
4718         u32 temp;
4719         u32 lvds_sync = 0;
4720         int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
4721
4722         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4723                 if (encoder->base.crtc != crtc)
4724                         continue;
4725
4726                 switch (encoder->type) {
4727                 case INTEL_OUTPUT_LVDS:
4728                         is_lvds = true;
4729                         break;
4730                 case INTEL_OUTPUT_SDVO:
4731                 case INTEL_OUTPUT_HDMI:
4732                         is_sdvo = true;
4733                         if (encoder->needs_tv_clock)
4734                                 is_tv = true;
4735                         break;
4736                 case INTEL_OUTPUT_TVOUT:
4737                         is_tv = true;
4738                         break;
4739                 case INTEL_OUTPUT_ANALOG:
4740                         is_crt = true;
4741                         break;
4742                 case INTEL_OUTPUT_DISPLAYPORT:
4743                         is_dp = true;
4744                         break;
4745                 case INTEL_OUTPUT_EDP:
4746                         has_edp_encoder = encoder;
4747                         break;
4748                 }
4749
4750                 num_connectors++;
4751         }
4752
4753         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4754                 refclk = dev_priv->lvds_ssc_freq * 1000;
4755                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4756                               refclk / 1000);
4757         } else {
4758                 refclk = 96000;
4759                 if (!has_edp_encoder ||
4760                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
4761                         refclk = 120000; /* 120Mhz refclk */
4762         }
4763
4764         /*
4765          * Returns a set of divisors for the desired target clock with the given
4766          * refclk, or FALSE.  The returned values represent the clock equation:
4767          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4768          */
4769         limit = intel_limit(crtc, refclk);
4770         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4771         if (!ok) {
4772                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4773                 return -EINVAL;
4774         }
4775
4776         /* Ensure that the cursor is valid for the new mode before changing... */
4777         intel_crtc_update_cursor(crtc, true);
4778
4779         if (is_lvds && dev_priv->lvds_downclock_avail) {
4780                 has_reduced_clock = limit->find_pll(limit, crtc,
4781                                                     dev_priv->lvds_downclock,
4782                                                     refclk,
4783                                                     &reduced_clock);
4784                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4785                         /*
4786                          * If the different P is found, it means that we can't
4787                          * switch the display clock by using the FP0/FP1.
4788                          * In such case we will disable the LVDS downclock
4789                          * feature.
4790                          */
4791                         DRM_DEBUG_KMS("Different P is found for "
4792                                       "LVDS clock/downclock\n");
4793                         has_reduced_clock = 0;
4794                 }
4795         }
4796         /* SDVO TV has fixed PLL values depend on its clock range,
4797            this mirrors vbios setting. */
4798         if (is_sdvo && is_tv) {
4799                 if (adjusted_mode->clock >= 100000
4800                     && adjusted_mode->clock < 140500) {
4801                         clock.p1 = 2;
4802                         clock.p2 = 10;
4803                         clock.n = 3;
4804                         clock.m1 = 16;
4805                         clock.m2 = 8;
4806                 } else if (adjusted_mode->clock >= 140500
4807                            && adjusted_mode->clock <= 200000) {
4808                         clock.p1 = 1;
4809                         clock.p2 = 10;
4810                         clock.n = 6;
4811                         clock.m1 = 12;
4812                         clock.m2 = 8;
4813                 }
4814         }
4815
4816         /* FDI link */
4817         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4818         lane = 0;
4819         /* CPU eDP doesn't require FDI link, so just set DP M/N
4820            according to current link config */
4821         if (has_edp_encoder &&
4822             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4823                 target_clock = mode->clock;
4824                 intel_edp_link_config(has_edp_encoder,
4825                                       &lane, &link_bw);
4826         } else {
4827                 /* [e]DP over FDI requires target mode clock
4828                    instead of link clock */
4829                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4830                         target_clock = mode->clock;
4831                 else
4832                         target_clock = adjusted_mode->clock;
4833
4834                 /* FDI is a binary signal running at ~2.7GHz, encoding
4835                  * each output octet as 10 bits. The actual frequency
4836                  * is stored as a divider into a 100MHz clock, and the
4837                  * mode pixel clock is stored in units of 1KHz.
4838                  * Hence the bw of each lane in terms of the mode signal
4839                  * is:
4840                  */
4841                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4842         }
4843
4844         /* determine panel color depth */
4845         temp = I915_READ(PIPECONF(pipe));
4846         temp &= ~PIPE_BPC_MASK;
4847         if (is_lvds) {
4848                 /* the BPC will be 6 if it is 18-bit LVDS panel */
4849                 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4850                         temp |= PIPE_8BPC;
4851                 else
4852                         temp |= PIPE_6BPC;
4853         } else if (has_edp_encoder) {
4854                 switch (dev_priv->edp.bpp/3) {
4855                 case 8:
4856                         temp |= PIPE_8BPC;
4857                         break;
4858                 case 10:
4859                         temp |= PIPE_10BPC;
4860                         break;
4861                 case 6:
4862                         temp |= PIPE_6BPC;
4863                         break;
4864                 case 12:
4865                         temp |= PIPE_12BPC;
4866                         break;
4867                 }
4868         } else
4869                 temp |= PIPE_8BPC;
4870         I915_WRITE(PIPECONF(pipe), temp);
4871
4872         switch (temp & PIPE_BPC_MASK) {
4873         case PIPE_8BPC:
4874                 bpp = 24;
4875                 break;
4876         case PIPE_10BPC:
4877                 bpp = 30;
4878                 break;
4879         case PIPE_6BPC:
4880                 bpp = 18;
4881                 break;
4882         case PIPE_12BPC:
4883                 bpp = 36;
4884                 break;
4885         default:
4886                 DRM_ERROR("unknown pipe bpc value\n");
4887                 bpp = 24;
4888         }
4889
4890         if (!lane) {
4891                 /*
4892                  * Account for spread spectrum to avoid
4893                  * oversubscribing the link. Max center spread
4894                  * is 2.5%; use 5% for safety's sake.
4895                  */
4896                 u32 bps = target_clock * bpp * 21 / 20;
4897                 lane = bps / (link_bw * 8) + 1;
4898         }
4899
4900         intel_crtc->fdi_lanes = lane;
4901
4902         if (pixel_multiplier > 1)
4903                 link_bw *= pixel_multiplier;
4904         ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4905
4906         /* Ironlake: try to setup display ref clock before DPLL
4907          * enabling. This is only under driver's control after
4908          * PCH B stepping, previous chipset stepping should be
4909          * ignoring this setting.
4910          */
4911         temp = I915_READ(PCH_DREF_CONTROL);
4912         /* Always enable nonspread source */
4913         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4914         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4915         temp &= ~DREF_SSC_SOURCE_MASK;
4916         temp |= DREF_SSC_SOURCE_ENABLE;
4917         I915_WRITE(PCH_DREF_CONTROL, temp);
4918
4919         POSTING_READ(PCH_DREF_CONTROL);
4920         udelay(200);
4921
4922         if (has_edp_encoder) {
4923                 if (intel_panel_use_ssc(dev_priv)) {
4924                         temp |= DREF_SSC1_ENABLE;
4925                         I915_WRITE(PCH_DREF_CONTROL, temp);
4926
4927                         POSTING_READ(PCH_DREF_CONTROL);
4928                         udelay(200);
4929                 }
4930                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4931
4932                 /* Enable CPU source on CPU attached eDP */
4933                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4934                         if (intel_panel_use_ssc(dev_priv))
4935                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4936                         else
4937                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4938                 } else {
4939                         /* Enable SSC on PCH eDP if needed */
4940                         if (intel_panel_use_ssc(dev_priv)) {
4941                                 DRM_ERROR("enabling SSC on PCH\n");
4942                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4943                         }
4944                 }
4945                 I915_WRITE(PCH_DREF_CONTROL, temp);
4946                 POSTING_READ(PCH_DREF_CONTROL);
4947                 udelay(200);
4948         }
4949
4950         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4951         if (has_reduced_clock)
4952                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4953                         reduced_clock.m2;
4954
4955         /* Enable autotuning of the PLL clock (if permissible) */
4956         factor = 21;
4957         if (is_lvds) {
4958                 if ((intel_panel_use_ssc(dev_priv) &&
4959                      dev_priv->lvds_ssc_freq == 100) ||
4960                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4961                         factor = 25;
4962         } else if (is_sdvo && is_tv)
4963                 factor = 20;
4964
4965         if (clock.m1 < factor * clock.n)
4966                 fp |= FP_CB_TUNE;
4967
4968         dpll = 0;
4969
4970         if (is_lvds)
4971                 dpll |= DPLLB_MODE_LVDS;
4972         else
4973                 dpll |= DPLLB_MODE_DAC_SERIAL;
4974         if (is_sdvo) {
4975                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4976                 if (pixel_multiplier > 1) {
4977                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4978                 }
4979                 dpll |= DPLL_DVO_HIGH_SPEED;
4980         }
4981         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4982                 dpll |= DPLL_DVO_HIGH_SPEED;
4983
4984         /* compute bitmask from p1 value */
4985         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4986         /* also FPA1 */
4987         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4988
4989         switch (clock.p2) {
4990         case 5:
4991                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4992                 break;
4993         case 7:
4994                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4995                 break;
4996         case 10:
4997                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4998                 break;
4999         case 14:
5000                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5001                 break;
5002         }
5003
5004         if (is_sdvo && is_tv)
5005                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5006         else if (is_tv)
5007                 /* XXX: just matching BIOS for now */
5008                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5009                 dpll |= 3;
5010         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5011                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5012         else
5013                 dpll |= PLL_REF_INPUT_DREFCLK;
5014
5015         /* setup pipeconf */
5016         pipeconf = I915_READ(PIPECONF(pipe));
5017
5018         /* Set up the display plane register */
5019         dspcntr = DISPPLANE_GAMMA_ENABLE;
5020
5021         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5022         drm_mode_debug_printmodeline(mode);
5023
5024         /* PCH eDP needs FDI, but CPU eDP does not */
5025         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5026                 I915_WRITE(PCH_FP0(pipe), fp);
5027                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5028
5029                 POSTING_READ(PCH_DPLL(pipe));
5030                 udelay(150);
5031         }
5032
5033         /* enable transcoder DPLL */
5034         if (HAS_PCH_CPT(dev)) {
5035                 temp = I915_READ(PCH_DPLL_SEL);
5036                 switch (pipe) {
5037                 case 0:
5038                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5039                         break;
5040                 case 1:
5041                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5042                         break;
5043                 case 2:
5044                         /* FIXME: manage transcoder PLLs? */
5045                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5046                         break;
5047                 default:
5048                         BUG();
5049                 }
5050                 I915_WRITE(PCH_DPLL_SEL, temp);
5051
5052                 POSTING_READ(PCH_DPLL_SEL);
5053                 udelay(150);
5054         }
5055
5056         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5057          * This is an exception to the general rule that mode_set doesn't turn
5058          * things on.
5059          */
5060         if (is_lvds) {
5061                 temp = I915_READ(PCH_LVDS);
5062                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5063                 if (pipe == 1) {
5064                         if (HAS_PCH_CPT(dev))
5065                                 temp |= PORT_TRANS_B_SEL_CPT;
5066                         else
5067                                 temp |= LVDS_PIPEB_SELECT;
5068                 } else {
5069                         if (HAS_PCH_CPT(dev))
5070                                 temp &= ~PORT_TRANS_SEL_MASK;
5071                         else
5072                                 temp &= ~LVDS_PIPEB_SELECT;
5073                 }
5074                 /* set the corresponsding LVDS_BORDER bit */
5075                 temp |= dev_priv->lvds_border_bits;
5076                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5077                  * set the DPLLs for dual-channel mode or not.
5078                  */
5079                 if (clock.p2 == 7)
5080                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5081                 else
5082                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5083
5084                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5085                  * appropriately here, but we need to look more thoroughly into how
5086                  * panels behave in the two modes.
5087                  */
5088                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5089                         lvds_sync |= LVDS_HSYNC_POLARITY;
5090                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5091                         lvds_sync |= LVDS_VSYNC_POLARITY;
5092                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5093                     != lvds_sync) {
5094                         char flags[2] = "-+";
5095                         DRM_INFO("Changing LVDS panel from "
5096                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5097                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5098                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5099                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5100                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5101                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5102                         temp |= lvds_sync;
5103                 }
5104                 I915_WRITE(PCH_LVDS, temp);
5105         }
5106
5107         /* set the dithering flag and clear for anything other than a panel. */
5108         pipeconf &= ~PIPECONF_DITHER_EN;
5109         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5110         if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5111                 pipeconf |= PIPECONF_DITHER_EN;
5112                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5113         }
5114
5115         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5116                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5117         } else {
5118                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5119                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5120                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5121                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5122                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5123         }
5124
5125         if (!has_edp_encoder ||
5126             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5127                 I915_WRITE(PCH_DPLL(pipe), dpll);
5128
5129                 /* Wait for the clocks to stabilize. */
5130                 POSTING_READ(PCH_DPLL(pipe));
5131                 udelay(150);
5132
5133                 /* The pixel multiplier can only be updated once the
5134                  * DPLL is enabled and the clocks are stable.
5135                  *
5136                  * So write it again.
5137                  */
5138                 I915_WRITE(PCH_DPLL(pipe), dpll);
5139         }
5140
5141         intel_crtc->lowfreq_avail = false;
5142         if (is_lvds && has_reduced_clock && i915_powersave) {
5143                 I915_WRITE(PCH_FP1(pipe), fp2);
5144                 intel_crtc->lowfreq_avail = true;
5145                 if (HAS_PIPE_CXSR(dev)) {
5146                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5147                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5148                 }
5149         } else {
5150                 I915_WRITE(PCH_FP1(pipe), fp);
5151                 if (HAS_PIPE_CXSR(dev)) {
5152                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5153                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5154                 }
5155         }
5156
5157         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5158                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5159                 /* the chip adds 2 halflines automatically */
5160                 adjusted_mode->crtc_vdisplay -= 1;
5161                 adjusted_mode->crtc_vtotal -= 1;
5162                 adjusted_mode->crtc_vblank_start -= 1;
5163                 adjusted_mode->crtc_vblank_end -= 1;
5164                 adjusted_mode->crtc_vsync_end -= 1;
5165                 adjusted_mode->crtc_vsync_start -= 1;
5166         } else
5167                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5168
5169         I915_WRITE(HTOTAL(pipe),
5170                    (adjusted_mode->crtc_hdisplay - 1) |
5171                    ((adjusted_mode->crtc_htotal - 1) << 16));
5172         I915_WRITE(HBLANK(pipe),
5173                    (adjusted_mode->crtc_hblank_start - 1) |
5174                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5175         I915_WRITE(HSYNC(pipe),
5176                    (adjusted_mode->crtc_hsync_start - 1) |
5177                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5178
5179         I915_WRITE(VTOTAL(pipe),
5180                    (adjusted_mode->crtc_vdisplay - 1) |
5181                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5182         I915_WRITE(VBLANK(pipe),
5183                    (adjusted_mode->crtc_vblank_start - 1) |
5184                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5185         I915_WRITE(VSYNC(pipe),
5186                    (adjusted_mode->crtc_vsync_start - 1) |
5187                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5188
5189         /* pipesrc controls the size that is scaled from, which should
5190          * always be the user's requested size.
5191          */
5192         I915_WRITE(PIPESRC(pipe),
5193                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5194
5195         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5196         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5197         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5198         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5199
5200         if (has_edp_encoder &&
5201             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5202                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5203         }
5204
5205         I915_WRITE(PIPECONF(pipe), pipeconf);
5206         POSTING_READ(PIPECONF(pipe));
5207
5208         intel_wait_for_vblank(dev, pipe);
5209
5210         if (IS_GEN5(dev)) {
5211                 /* enable address swizzle for tiling buffer */
5212                 temp = I915_READ(DISP_ARB_CTL);
5213                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5214         }
5215
5216         I915_WRITE(DSPCNTR(plane), dspcntr);
5217         POSTING_READ(DSPCNTR(plane));
5218
5219         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5220
5221         intel_update_watermarks(dev);
5222
5223         return ret;
5224 }
5225
5226 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5227                                struct drm_display_mode *mode,
5228                                struct drm_display_mode *adjusted_mode,
5229                                int x, int y,
5230                                struct drm_framebuffer *old_fb)
5231 {
5232         struct drm_device *dev = crtc->dev;
5233         struct drm_i915_private *dev_priv = dev->dev_private;
5234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5235         int pipe = intel_crtc->pipe;
5236         int ret;
5237
5238         drm_vblank_pre_modeset(dev, pipe);
5239
5240         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5241                                               x, y, old_fb);
5242
5243         drm_vblank_post_modeset(dev, pipe);
5244
5245         return ret;
5246 }
5247
5248 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5249 void intel_crtc_load_lut(struct drm_crtc *crtc)
5250 {
5251         struct drm_device *dev = crtc->dev;
5252         struct drm_i915_private *dev_priv = dev->dev_private;
5253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254         int palreg = PALETTE(intel_crtc->pipe);
5255         int i;
5256
5257         /* The clocks have to be on to load the palette. */
5258         if (!crtc->enabled)
5259                 return;
5260
5261         /* use legacy palette for Ironlake */
5262         if (HAS_PCH_SPLIT(dev))
5263                 palreg = LGC_PALETTE(intel_crtc->pipe);
5264
5265         for (i = 0; i < 256; i++) {
5266                 I915_WRITE(palreg + 4 * i,
5267                            (intel_crtc->lut_r[i] << 16) |
5268                            (intel_crtc->lut_g[i] << 8) |
5269                            intel_crtc->lut_b[i]);
5270         }
5271 }
5272
5273 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5274 {
5275         struct drm_device *dev = crtc->dev;
5276         struct drm_i915_private *dev_priv = dev->dev_private;
5277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5278         bool visible = base != 0;
5279         u32 cntl;
5280
5281         if (intel_crtc->cursor_visible == visible)
5282                 return;
5283
5284         cntl = I915_READ(_CURACNTR);
5285         if (visible) {
5286                 /* On these chipsets we can only modify the base whilst
5287                  * the cursor is disabled.
5288                  */
5289                 I915_WRITE(_CURABASE, base);
5290
5291                 cntl &= ~(CURSOR_FORMAT_MASK);
5292                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5293                 cntl |= CURSOR_ENABLE |
5294                         CURSOR_GAMMA_ENABLE |
5295                         CURSOR_FORMAT_ARGB;
5296         } else
5297                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5298         I915_WRITE(_CURACNTR, cntl);
5299
5300         intel_crtc->cursor_visible = visible;
5301 }
5302
5303 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5304 {
5305         struct drm_device *dev = crtc->dev;
5306         struct drm_i915_private *dev_priv = dev->dev_private;
5307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5308         int pipe = intel_crtc->pipe;
5309         bool visible = base != 0;
5310
5311         if (intel_crtc->cursor_visible != visible) {
5312                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5313                 if (base) {
5314                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5315                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5316                         cntl |= pipe << 28; /* Connect to correct pipe */
5317                 } else {
5318                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5319                         cntl |= CURSOR_MODE_DISABLE;
5320                 }
5321                 I915_WRITE(CURCNTR(pipe), cntl);
5322
5323                 intel_crtc->cursor_visible = visible;
5324         }
5325         /* and commit changes on next vblank */
5326         I915_WRITE(CURBASE(pipe), base);
5327 }
5328
5329 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5330 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5331                                      bool on)
5332 {
5333         struct drm_device *dev = crtc->dev;
5334         struct drm_i915_private *dev_priv = dev->dev_private;
5335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5336         int pipe = intel_crtc->pipe;
5337         int x = intel_crtc->cursor_x;
5338         int y = intel_crtc->cursor_y;
5339         u32 base, pos;
5340         bool visible;
5341
5342         pos = 0;
5343
5344         if (on && crtc->enabled && crtc->fb) {
5345                 base = intel_crtc->cursor_addr;
5346                 if (x > (int) crtc->fb->width)
5347                         base = 0;
5348
5349                 if (y > (int) crtc->fb->height)
5350                         base = 0;
5351         } else
5352                 base = 0;
5353
5354         if (x < 0) {
5355                 if (x + intel_crtc->cursor_width < 0)
5356                         base = 0;
5357
5358                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5359                 x = -x;
5360         }
5361         pos |= x << CURSOR_X_SHIFT;
5362
5363         if (y < 0) {
5364                 if (y + intel_crtc->cursor_height < 0)
5365                         base = 0;
5366
5367                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5368                 y = -y;
5369         }
5370         pos |= y << CURSOR_Y_SHIFT;
5371
5372         visible = base != 0;
5373         if (!visible && !intel_crtc->cursor_visible)
5374                 return;
5375
5376         I915_WRITE(CURPOS(pipe), pos);
5377         if (IS_845G(dev) || IS_I865G(dev))
5378                 i845_update_cursor(crtc, base);
5379         else
5380                 i9xx_update_cursor(crtc, base);
5381
5382         if (visible)
5383                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5384 }
5385
5386 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5387                                  struct drm_file *file,
5388                                  uint32_t handle,
5389                                  uint32_t width, uint32_t height)
5390 {
5391         struct drm_device *dev = crtc->dev;
5392         struct drm_i915_private *dev_priv = dev->dev_private;
5393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5394         struct drm_i915_gem_object *obj;
5395         uint32_t addr;
5396         int ret;
5397
5398         DRM_DEBUG_KMS("\n");
5399
5400         /* if we want to turn off the cursor ignore width and height */
5401         if (!handle) {
5402                 DRM_DEBUG_KMS("cursor off\n");
5403                 addr = 0;
5404                 obj = NULL;
5405                 mutex_lock(&dev->struct_mutex);
5406                 goto finish;
5407         }
5408
5409         /* Currently we only support 64x64 cursors */
5410         if (width != 64 || height != 64) {
5411                 DRM_ERROR("we currently only support 64x64 cursors\n");
5412                 return -EINVAL;
5413         }
5414
5415         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5416         if (&obj->base == NULL)
5417                 return -ENOENT;
5418
5419         if (obj->base.size < width * height * 4) {
5420                 DRM_ERROR("buffer is to small\n");
5421                 ret = -ENOMEM;
5422                 goto fail;
5423         }
5424
5425         /* we only need to pin inside GTT if cursor is non-phy */
5426         mutex_lock(&dev->struct_mutex);
5427         if (!dev_priv->info->cursor_needs_physical) {
5428                 if (obj->tiling_mode) {
5429                         DRM_ERROR("cursor cannot be tiled\n");
5430                         ret = -EINVAL;
5431                         goto fail_locked;
5432                 }
5433
5434                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5435                 if (ret) {
5436                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5437                         goto fail_locked;
5438                 }
5439
5440                 ret = i915_gem_object_put_fence(obj);
5441                 if (ret) {
5442                         DRM_ERROR("failed to release fence for cursor");
5443                         goto fail_unpin;
5444                 }
5445
5446                 addr = obj->gtt_offset;
5447         } else {
5448                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5449                 ret = i915_gem_attach_phys_object(dev, obj,
5450                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5451                                                   align);
5452                 if (ret) {
5453                         DRM_ERROR("failed to attach phys object\n");
5454                         goto fail_locked;
5455                 }
5456                 addr = obj->phys_obj->handle->busaddr;
5457         }
5458
5459         if (IS_GEN2(dev))
5460                 I915_WRITE(CURSIZE, (height << 12) | width);
5461
5462  finish:
5463         if (intel_crtc->cursor_bo) {
5464                 if (dev_priv->info->cursor_needs_physical) {
5465                         if (intel_crtc->cursor_bo != obj)
5466                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5467                 } else
5468                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5469                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5470         }
5471
5472         mutex_unlock(&dev->struct_mutex);
5473
5474         intel_crtc->cursor_addr = addr;
5475         intel_crtc->cursor_bo = obj;
5476         intel_crtc->cursor_width = width;
5477         intel_crtc->cursor_height = height;
5478
5479         intel_crtc_update_cursor(crtc, true);
5480
5481         return 0;
5482 fail_unpin:
5483         i915_gem_object_unpin(obj);
5484 fail_locked:
5485         mutex_unlock(&dev->struct_mutex);
5486 fail:
5487         drm_gem_object_unreference_unlocked(&obj->base);
5488         return ret;
5489 }
5490
5491 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5492 {
5493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5494
5495         intel_crtc->cursor_x = x;
5496         intel_crtc->cursor_y = y;
5497
5498         intel_crtc_update_cursor(crtc, true);
5499
5500         return 0;
5501 }
5502
5503 /** Sets the color ramps on behalf of RandR */
5504 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5505                                  u16 blue, int regno)
5506 {
5507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508
5509         intel_crtc->lut_r[regno] = red >> 8;
5510         intel_crtc->lut_g[regno] = green >> 8;
5511         intel_crtc->lut_b[regno] = blue >> 8;
5512 }
5513
5514 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5515                              u16 *blue, int regno)
5516 {
5517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5518
5519         *red = intel_crtc->lut_r[regno] << 8;
5520         *green = intel_crtc->lut_g[regno] << 8;
5521         *blue = intel_crtc->lut_b[regno] << 8;
5522 }
5523
5524 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5525                                  u16 *blue, uint32_t start, uint32_t size)
5526 {
5527         int end = (start + size > 256) ? 256 : start + size, i;
5528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5529
5530         for (i = start; i < end; i++) {
5531                 intel_crtc->lut_r[i] = red[i] >> 8;
5532                 intel_crtc->lut_g[i] = green[i] >> 8;
5533                 intel_crtc->lut_b[i] = blue[i] >> 8;
5534         }
5535
5536         intel_crtc_load_lut(crtc);
5537 }
5538
5539 /**
5540  * Get a pipe with a simple mode set on it for doing load-based monitor
5541  * detection.
5542  *
5543  * It will be up to the load-detect code to adjust the pipe as appropriate for
5544  * its requirements.  The pipe will be connected to no other encoders.
5545  *
5546  * Currently this code will only succeed if there is a pipe with no encoders
5547  * configured for it.  In the future, it could choose to temporarily disable
5548  * some outputs to free up a pipe for its use.
5549  *
5550  * \return crtc, or NULL if no pipes are available.
5551  */
5552
5553 /* VESA 640x480x72Hz mode to set on the pipe */
5554 static struct drm_display_mode load_detect_mode = {
5555         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5556                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5557 };
5558
5559 static struct drm_framebuffer *
5560 intel_framebuffer_create(struct drm_device *dev,
5561                          struct drm_mode_fb_cmd *mode_cmd,
5562                          struct drm_i915_gem_object *obj)
5563 {
5564         struct intel_framebuffer *intel_fb;
5565         int ret;
5566
5567         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5568         if (!intel_fb) {
5569                 drm_gem_object_unreference_unlocked(&obj->base);
5570                 return ERR_PTR(-ENOMEM);
5571         }
5572
5573         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5574         if (ret) {
5575                 drm_gem_object_unreference_unlocked(&obj->base);
5576                 kfree(intel_fb);
5577                 return ERR_PTR(ret);
5578         }
5579
5580         return &intel_fb->base;
5581 }
5582
5583 static u32
5584 intel_framebuffer_pitch_for_width(int width, int bpp)
5585 {
5586         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5587         return ALIGN(pitch, 64);
5588 }
5589
5590 static u32
5591 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5592 {
5593         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5594         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5595 }
5596
5597 static struct drm_framebuffer *
5598 intel_framebuffer_create_for_mode(struct drm_device *dev,
5599                                   struct drm_display_mode *mode,
5600                                   int depth, int bpp)
5601 {
5602         struct drm_i915_gem_object *obj;
5603         struct drm_mode_fb_cmd mode_cmd;
5604
5605         obj = i915_gem_alloc_object(dev,
5606                                     intel_framebuffer_size_for_mode(mode, bpp));
5607         if (obj == NULL)
5608                 return ERR_PTR(-ENOMEM);
5609
5610         mode_cmd.width = mode->hdisplay;
5611         mode_cmd.height = mode->vdisplay;
5612         mode_cmd.depth = depth;
5613         mode_cmd.bpp = bpp;
5614         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5615
5616         return intel_framebuffer_create(dev, &mode_cmd, obj);
5617 }
5618
5619 static struct drm_framebuffer *
5620 mode_fits_in_fbdev(struct drm_device *dev,
5621                    struct drm_display_mode *mode)
5622 {
5623         struct drm_i915_private *dev_priv = dev->dev_private;
5624         struct drm_i915_gem_object *obj;
5625         struct drm_framebuffer *fb;
5626
5627         if (dev_priv->fbdev == NULL)
5628                 return NULL;
5629
5630         obj = dev_priv->fbdev->ifb.obj;
5631         if (obj == NULL)
5632                 return NULL;
5633
5634         fb = &dev_priv->fbdev->ifb.base;
5635         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5636                                                           fb->bits_per_pixel))
5637                 return NULL;
5638
5639         if (obj->base.size < mode->vdisplay * fb->pitch)
5640                 return NULL;
5641
5642         return fb;
5643 }
5644
5645 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5646                                 struct drm_connector *connector,
5647                                 struct drm_display_mode *mode,
5648                                 struct intel_load_detect_pipe *old)
5649 {
5650         struct intel_crtc *intel_crtc;
5651         struct drm_crtc *possible_crtc;
5652         struct drm_encoder *encoder = &intel_encoder->base;
5653         struct drm_crtc *crtc = NULL;
5654         struct drm_device *dev = encoder->dev;
5655         struct drm_framebuffer *old_fb;
5656         int i = -1;
5657
5658         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5659                       connector->base.id, drm_get_connector_name(connector),
5660                       encoder->base.id, drm_get_encoder_name(encoder));
5661
5662         /*
5663          * Algorithm gets a little messy:
5664          *
5665          *   - if the connector already has an assigned crtc, use it (but make
5666          *     sure it's on first)
5667          *
5668          *   - try to find the first unused crtc that can drive this connector,
5669          *     and use that if we find one
5670          */
5671
5672         /* See if we already have a CRTC for this connector */
5673         if (encoder->crtc) {
5674                 crtc = encoder->crtc;
5675
5676                 intel_crtc = to_intel_crtc(crtc);
5677                 old->dpms_mode = intel_crtc->dpms_mode;
5678                 old->load_detect_temp = false;
5679
5680                 /* Make sure the crtc and connector are running */
5681                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5682                         struct drm_encoder_helper_funcs *encoder_funcs;
5683                         struct drm_crtc_helper_funcs *crtc_funcs;
5684
5685                         crtc_funcs = crtc->helper_private;
5686                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5687
5688                         encoder_funcs = encoder->helper_private;
5689                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5690                 }
5691
5692                 return true;
5693         }
5694
5695         /* Find an unused one (if possible) */
5696         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5697                 i++;
5698                 if (!(encoder->possible_crtcs & (1 << i)))
5699                         continue;
5700                 if (!possible_crtc->enabled) {
5701                         crtc = possible_crtc;
5702                         break;
5703                 }
5704         }
5705
5706         /*
5707          * If we didn't find an unused CRTC, don't use any.
5708          */
5709         if (!crtc) {
5710                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5711                 return false;
5712         }
5713
5714         encoder->crtc = crtc;
5715         connector->encoder = encoder;
5716
5717         intel_crtc = to_intel_crtc(crtc);
5718         old->dpms_mode = intel_crtc->dpms_mode;
5719         old->load_detect_temp = true;
5720         old->release_fb = NULL;
5721
5722         if (!mode)
5723                 mode = &load_detect_mode;
5724
5725         old_fb = crtc->fb;
5726
5727         /* We need a framebuffer large enough to accommodate all accesses
5728          * that the plane may generate whilst we perform load detection.
5729          * We can not rely on the fbcon either being present (we get called
5730          * during its initialisation to detect all boot displays, or it may
5731          * not even exist) or that it is large enough to satisfy the
5732          * requested mode.
5733          */
5734         crtc->fb = mode_fits_in_fbdev(dev, mode);
5735         if (crtc->fb == NULL) {
5736                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5737                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5738                 old->release_fb = crtc->fb;
5739         } else
5740                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5741         if (IS_ERR(crtc->fb)) {
5742                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5743                 crtc->fb = old_fb;
5744                 return false;
5745         }
5746
5747         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5748                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5749                 if (old->release_fb)
5750                         old->release_fb->funcs->destroy(old->release_fb);
5751                 crtc->fb = old_fb;
5752                 return false;
5753         }
5754
5755         /* let the connector get through one full cycle before testing */
5756         intel_wait_for_vblank(dev, intel_crtc->pipe);
5757
5758         return true;
5759 }
5760
5761 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5762                                     struct drm_connector *connector,
5763                                     struct intel_load_detect_pipe *old)
5764 {
5765         struct drm_encoder *encoder = &intel_encoder->base;
5766         struct drm_device *dev = encoder->dev;
5767         struct drm_crtc *crtc = encoder->crtc;
5768         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5769         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5770
5771         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5772                       connector->base.id, drm_get_connector_name(connector),
5773                       encoder->base.id, drm_get_encoder_name(encoder));
5774
5775         if (old->load_detect_temp) {
5776                 connector->encoder = NULL;
5777                 drm_helper_disable_unused_functions(dev);
5778
5779                 if (old->release_fb)
5780                         old->release_fb->funcs->destroy(old->release_fb);
5781
5782                 return;
5783         }
5784
5785         /* Switch crtc and encoder back off if necessary */
5786         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5787                 encoder_funcs->dpms(encoder, old->dpms_mode);
5788                 crtc_funcs->dpms(crtc, old->dpms_mode);
5789         }
5790 }
5791
5792 /* Returns the clock of the currently programmed mode of the given pipe. */
5793 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5794 {
5795         struct drm_i915_private *dev_priv = dev->dev_private;
5796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5797         int pipe = intel_crtc->pipe;
5798         u32 dpll = I915_READ(DPLL(pipe));
5799         u32 fp;
5800         intel_clock_t clock;
5801
5802         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5803                 fp = I915_READ(FP0(pipe));
5804         else
5805                 fp = I915_READ(FP1(pipe));
5806
5807         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5808         if (IS_PINEVIEW(dev)) {
5809                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5810                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5811         } else {
5812                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5813                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5814         }
5815
5816         if (!IS_GEN2(dev)) {
5817                 if (IS_PINEVIEW(dev))
5818                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5819                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5820                 else
5821                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5822                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5823
5824                 switch (dpll & DPLL_MODE_MASK) {
5825                 case DPLLB_MODE_DAC_SERIAL:
5826                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5827                                 5 : 10;
5828                         break;
5829                 case DPLLB_MODE_LVDS:
5830                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5831                                 7 : 14;
5832                         break;
5833                 default:
5834                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5835                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5836                         return 0;
5837                 }
5838
5839                 /* XXX: Handle the 100Mhz refclk */
5840                 intel_clock(dev, 96000, &clock);
5841         } else {
5842                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5843
5844                 if (is_lvds) {
5845                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5846                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5847                         clock.p2 = 14;
5848
5849                         if ((dpll & PLL_REF_INPUT_MASK) ==
5850                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5851                                 /* XXX: might not be 66MHz */
5852                                 intel_clock(dev, 66000, &clock);
5853                         } else
5854                                 intel_clock(dev, 48000, &clock);
5855                 } else {
5856                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5857                                 clock.p1 = 2;
5858                         else {
5859                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5860                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5861                         }
5862                         if (dpll & PLL_P2_DIVIDE_BY_4)
5863                                 clock.p2 = 4;
5864                         else
5865                                 clock.p2 = 2;
5866
5867                         intel_clock(dev, 48000, &clock);
5868                 }
5869         }
5870
5871         /* XXX: It would be nice to validate the clocks, but we can't reuse
5872          * i830PllIsValid() because it relies on the xf86_config connector
5873          * configuration being accurate, which it isn't necessarily.
5874          */
5875
5876         return clock.dot;
5877 }
5878
5879 /** Returns the currently programmed mode of the given pipe. */
5880 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5881                                              struct drm_crtc *crtc)
5882 {
5883         struct drm_i915_private *dev_priv = dev->dev_private;
5884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5885         int pipe = intel_crtc->pipe;
5886         struct drm_display_mode *mode;
5887         int htot = I915_READ(HTOTAL(pipe));
5888         int hsync = I915_READ(HSYNC(pipe));
5889         int vtot = I915_READ(VTOTAL(pipe));
5890         int vsync = I915_READ(VSYNC(pipe));
5891
5892         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5893         if (!mode)
5894                 return NULL;
5895
5896         mode->clock = intel_crtc_clock_get(dev, crtc);
5897         mode->hdisplay = (htot & 0xffff) + 1;
5898         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5899         mode->hsync_start = (hsync & 0xffff) + 1;
5900         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5901         mode->vdisplay = (vtot & 0xffff) + 1;
5902         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5903         mode->vsync_start = (vsync & 0xffff) + 1;
5904         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5905
5906         drm_mode_set_name(mode);
5907         drm_mode_set_crtcinfo(mode, 0);
5908
5909         return mode;
5910 }
5911
5912 #define GPU_IDLE_TIMEOUT 500 /* ms */
5913
5914 /* When this timer fires, we've been idle for awhile */
5915 static void intel_gpu_idle_timer(unsigned long arg)
5916 {
5917         struct drm_device *dev = (struct drm_device *)arg;
5918         drm_i915_private_t *dev_priv = dev->dev_private;
5919
5920         if (!list_empty(&dev_priv->mm.active_list)) {
5921                 /* Still processing requests, so just re-arm the timer. */
5922                 mod_timer(&dev_priv->idle_timer, jiffies +
5923                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5924                 return;
5925         }
5926
5927         dev_priv->busy = false;
5928         queue_work(dev_priv->wq, &dev_priv->idle_work);
5929 }
5930
5931 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5932
5933 static void intel_crtc_idle_timer(unsigned long arg)
5934 {
5935         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5936         struct drm_crtc *crtc = &intel_crtc->base;
5937         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5938         struct intel_framebuffer *intel_fb;
5939
5940         intel_fb = to_intel_framebuffer(crtc->fb);
5941         if (intel_fb && intel_fb->obj->active) {
5942                 /* The framebuffer is still being accessed by the GPU. */
5943                 mod_timer(&intel_crtc->idle_timer, jiffies +
5944                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5945                 return;
5946         }
5947
5948         intel_crtc->busy = false;
5949         queue_work(dev_priv->wq, &dev_priv->idle_work);
5950 }
5951
5952 static void intel_increase_pllclock(struct drm_crtc *crtc)
5953 {
5954         struct drm_device *dev = crtc->dev;
5955         drm_i915_private_t *dev_priv = dev->dev_private;
5956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957         int pipe = intel_crtc->pipe;
5958         int dpll_reg = DPLL(pipe);
5959         int dpll;
5960
5961         if (HAS_PCH_SPLIT(dev))
5962                 return;
5963
5964         if (!dev_priv->lvds_downclock_avail)
5965                 return;
5966
5967         dpll = I915_READ(dpll_reg);
5968         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5969                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5970
5971                 /* Unlock panel regs */
5972                 I915_WRITE(PP_CONTROL,
5973                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5974
5975                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5976                 I915_WRITE(dpll_reg, dpll);
5977                 intel_wait_for_vblank(dev, pipe);
5978
5979                 dpll = I915_READ(dpll_reg);
5980                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5981                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5982
5983                 /* ...and lock them again */
5984                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5985         }
5986
5987         /* Schedule downclock */
5988         mod_timer(&intel_crtc->idle_timer, jiffies +
5989                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5990 }
5991
5992 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5993 {
5994         struct drm_device *dev = crtc->dev;
5995         drm_i915_private_t *dev_priv = dev->dev_private;
5996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5997         int pipe = intel_crtc->pipe;
5998         int dpll_reg = DPLL(pipe);
5999         int dpll = I915_READ(dpll_reg);
6000
6001         if (HAS_PCH_SPLIT(dev))
6002                 return;
6003
6004         if (!dev_priv->lvds_downclock_avail)
6005                 return;
6006
6007         /*
6008          * Since this is called by a timer, we should never get here in
6009          * the manual case.
6010          */
6011         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6012                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6013
6014                 /* Unlock panel regs */
6015                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6016                            PANEL_UNLOCK_REGS);
6017
6018                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6019                 I915_WRITE(dpll_reg, dpll);
6020                 intel_wait_for_vblank(dev, pipe);
6021                 dpll = I915_READ(dpll_reg);
6022                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6023                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6024
6025                 /* ...and lock them again */
6026                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6027         }
6028
6029 }
6030
6031 /**
6032  * intel_idle_update - adjust clocks for idleness
6033  * @work: work struct
6034  *
6035  * Either the GPU or display (or both) went idle.  Check the busy status
6036  * here and adjust the CRTC and GPU clocks as necessary.
6037  */
6038 static void intel_idle_update(struct work_struct *work)
6039 {
6040         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6041                                                     idle_work);
6042         struct drm_device *dev = dev_priv->dev;
6043         struct drm_crtc *crtc;
6044         struct intel_crtc *intel_crtc;
6045
6046         if (!i915_powersave)
6047                 return;
6048
6049         mutex_lock(&dev->struct_mutex);
6050
6051         i915_update_gfx_val(dev_priv);
6052
6053         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6054                 /* Skip inactive CRTCs */
6055                 if (!crtc->fb)
6056                         continue;
6057
6058                 intel_crtc = to_intel_crtc(crtc);
6059                 if (!intel_crtc->busy)
6060                         intel_decrease_pllclock(crtc);
6061         }
6062
6063
6064         mutex_unlock(&dev->struct_mutex);
6065 }
6066
6067 /**
6068  * intel_mark_busy - mark the GPU and possibly the display busy
6069  * @dev: drm device
6070  * @obj: object we're operating on
6071  *
6072  * Callers can use this function to indicate that the GPU is busy processing
6073  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6074  * buffer), we'll also mark the display as busy, so we know to increase its
6075  * clock frequency.
6076  */
6077 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6078 {
6079         drm_i915_private_t *dev_priv = dev->dev_private;
6080         struct drm_crtc *crtc = NULL;
6081         struct intel_framebuffer *intel_fb;
6082         struct intel_crtc *intel_crtc;
6083
6084         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6085                 return;
6086
6087         if (!dev_priv->busy)
6088                 dev_priv->busy = true;
6089         else
6090                 mod_timer(&dev_priv->idle_timer, jiffies +
6091                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6092
6093         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6094                 if (!crtc->fb)
6095                         continue;
6096
6097                 intel_crtc = to_intel_crtc(crtc);
6098                 intel_fb = to_intel_framebuffer(crtc->fb);
6099                 if (intel_fb->obj == obj) {
6100                         if (!intel_crtc->busy) {
6101                                 /* Non-busy -> busy, upclock */
6102                                 intel_increase_pllclock(crtc);
6103                                 intel_crtc->busy = true;
6104                         } else {
6105                                 /* Busy -> busy, put off timer */
6106                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6107                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6108                         }
6109                 }
6110         }
6111 }
6112
6113 static void intel_crtc_destroy(struct drm_crtc *crtc)
6114 {
6115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6116         struct drm_device *dev = crtc->dev;
6117         struct intel_unpin_work *work;
6118         unsigned long flags;
6119
6120         spin_lock_irqsave(&dev->event_lock, flags);
6121         work = intel_crtc->unpin_work;
6122         intel_crtc->unpin_work = NULL;
6123         spin_unlock_irqrestore(&dev->event_lock, flags);
6124
6125         if (work) {
6126                 cancel_work_sync(&work->work);
6127                 kfree(work);
6128         }
6129
6130         drm_crtc_cleanup(crtc);
6131
6132         kfree(intel_crtc);
6133 }
6134
6135 static void intel_unpin_work_fn(struct work_struct *__work)
6136 {
6137         struct intel_unpin_work *work =
6138                 container_of(__work, struct intel_unpin_work, work);
6139
6140         mutex_lock(&work->dev->struct_mutex);
6141         i915_gem_object_unpin(work->old_fb_obj);
6142         drm_gem_object_unreference(&work->pending_flip_obj->base);
6143         drm_gem_object_unreference(&work->old_fb_obj->base);
6144
6145         mutex_unlock(&work->dev->struct_mutex);
6146         kfree(work);
6147 }
6148
6149 static void do_intel_finish_page_flip(struct drm_device *dev,
6150                                       struct drm_crtc *crtc)
6151 {
6152         drm_i915_private_t *dev_priv = dev->dev_private;
6153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154         struct intel_unpin_work *work;
6155         struct drm_i915_gem_object *obj;
6156         struct drm_pending_vblank_event *e;
6157         struct timeval tnow, tvbl;
6158         unsigned long flags;
6159
6160         /* Ignore early vblank irqs */
6161         if (intel_crtc == NULL)
6162                 return;
6163
6164         do_gettimeofday(&tnow);
6165
6166         spin_lock_irqsave(&dev->event_lock, flags);
6167         work = intel_crtc->unpin_work;
6168         if (work == NULL || !work->pending) {
6169                 spin_unlock_irqrestore(&dev->event_lock, flags);
6170                 return;
6171         }
6172
6173         intel_crtc->unpin_work = NULL;
6174
6175         if (work->event) {
6176                 e = work->event;
6177                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6178
6179                 /* Called before vblank count and timestamps have
6180                  * been updated for the vblank interval of flip
6181                  * completion? Need to increment vblank count and
6182                  * add one videorefresh duration to returned timestamp
6183                  * to account for this. We assume this happened if we
6184                  * get called over 0.9 frame durations after the last
6185                  * timestamped vblank.
6186                  *
6187                  * This calculation can not be used with vrefresh rates
6188                  * below 5Hz (10Hz to be on the safe side) without
6189                  * promoting to 64 integers.
6190                  */
6191                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6192                     9 * crtc->framedur_ns) {
6193                         e->event.sequence++;
6194                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6195                                              crtc->framedur_ns);
6196                 }
6197
6198                 e->event.tv_sec = tvbl.tv_sec;
6199                 e->event.tv_usec = tvbl.tv_usec;
6200
6201                 list_add_tail(&e->base.link,
6202                               &e->base.file_priv->event_list);
6203                 wake_up_interruptible(&e->base.file_priv->event_wait);
6204         }
6205
6206         drm_vblank_put(dev, intel_crtc->pipe);
6207
6208         spin_unlock_irqrestore(&dev->event_lock, flags);
6209
6210         obj = work->old_fb_obj;
6211
6212         atomic_clear_mask(1 << intel_crtc->plane,
6213                           &obj->pending_flip.counter);
6214         if (atomic_read(&obj->pending_flip) == 0)
6215                 wake_up(&dev_priv->pending_flip_queue);
6216
6217         schedule_work(&work->work);
6218
6219         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6220 }
6221
6222 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6223 {
6224         drm_i915_private_t *dev_priv = dev->dev_private;
6225         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6226
6227         do_intel_finish_page_flip(dev, crtc);
6228 }
6229
6230 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6231 {
6232         drm_i915_private_t *dev_priv = dev->dev_private;
6233         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6234
6235         do_intel_finish_page_flip(dev, crtc);
6236 }
6237
6238 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6239 {
6240         drm_i915_private_t *dev_priv = dev->dev_private;
6241         struct intel_crtc *intel_crtc =
6242                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6243         unsigned long flags;
6244
6245         spin_lock_irqsave(&dev->event_lock, flags);
6246         if (intel_crtc->unpin_work) {
6247                 if ((++intel_crtc->unpin_work->pending) > 1)
6248                         DRM_ERROR("Prepared flip multiple times\n");
6249         } else {
6250                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6251         }
6252         spin_unlock_irqrestore(&dev->event_lock, flags);
6253 }
6254
6255 static int intel_gen2_queue_flip(struct drm_device *dev,
6256                                  struct drm_crtc *crtc,
6257                                  struct drm_framebuffer *fb,
6258                                  struct drm_i915_gem_object *obj)
6259 {
6260         struct drm_i915_private *dev_priv = dev->dev_private;
6261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6262         unsigned long offset;
6263         u32 flip_mask;
6264         int ret;
6265
6266         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6267         if (ret)
6268                 goto out;
6269
6270         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6271         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6272
6273         ret = BEGIN_LP_RING(6);
6274         if (ret)
6275                 goto out;
6276
6277         /* Can't queue multiple flips, so wait for the previous
6278          * one to finish before executing the next.
6279          */
6280         if (intel_crtc->plane)
6281                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6282         else
6283                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6284         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6285         OUT_RING(MI_NOOP);
6286         OUT_RING(MI_DISPLAY_FLIP |
6287                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6288         OUT_RING(fb->pitch);
6289         OUT_RING(obj->gtt_offset + offset);
6290         OUT_RING(MI_NOOP);
6291         ADVANCE_LP_RING();
6292 out:
6293         return ret;
6294 }
6295
6296 static int intel_gen3_queue_flip(struct drm_device *dev,
6297                                  struct drm_crtc *crtc,
6298                                  struct drm_framebuffer *fb,
6299                                  struct drm_i915_gem_object *obj)
6300 {
6301         struct drm_i915_private *dev_priv = dev->dev_private;
6302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303         unsigned long offset;
6304         u32 flip_mask;
6305         int ret;
6306
6307         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6308         if (ret)
6309                 goto out;
6310
6311         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6312         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6313
6314         ret = BEGIN_LP_RING(6);
6315         if (ret)
6316                 goto out;
6317
6318         if (intel_crtc->plane)
6319                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6320         else
6321                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6322         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6323         OUT_RING(MI_NOOP);
6324         OUT_RING(MI_DISPLAY_FLIP_I915 |
6325                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6326         OUT_RING(fb->pitch);
6327         OUT_RING(obj->gtt_offset + offset);
6328         OUT_RING(MI_NOOP);
6329
6330         ADVANCE_LP_RING();
6331 out:
6332         return ret;
6333 }
6334
6335 static int intel_gen4_queue_flip(struct drm_device *dev,
6336                                  struct drm_crtc *crtc,
6337                                  struct drm_framebuffer *fb,
6338                                  struct drm_i915_gem_object *obj)
6339 {
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342         uint32_t pf, pipesrc;
6343         int ret;
6344
6345         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6346         if (ret)
6347                 goto out;
6348
6349         ret = BEGIN_LP_RING(4);
6350         if (ret)
6351                 goto out;
6352
6353         /* i965+ uses the linear or tiled offsets from the
6354          * Display Registers (which do not change across a page-flip)
6355          * so we need only reprogram the base address.
6356          */
6357         OUT_RING(MI_DISPLAY_FLIP |
6358                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6359         OUT_RING(fb->pitch);
6360         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6361
6362         /* XXX Enabling the panel-fitter across page-flip is so far
6363          * untested on non-native modes, so ignore it for now.
6364          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6365          */
6366         pf = 0;
6367         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6368         OUT_RING(pf | pipesrc);
6369         ADVANCE_LP_RING();
6370 out:
6371         return ret;
6372 }
6373
6374 static int intel_gen6_queue_flip(struct drm_device *dev,
6375                                  struct drm_crtc *crtc,
6376                                  struct drm_framebuffer *fb,
6377                                  struct drm_i915_gem_object *obj)
6378 {
6379         struct drm_i915_private *dev_priv = dev->dev_private;
6380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381         uint32_t pf, pipesrc;
6382         int ret;
6383
6384         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6385         if (ret)
6386                 goto out;
6387
6388         ret = BEGIN_LP_RING(4);
6389         if (ret)
6390                 goto out;
6391
6392         OUT_RING(MI_DISPLAY_FLIP |
6393                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6394         OUT_RING(fb->pitch | obj->tiling_mode);
6395         OUT_RING(obj->gtt_offset);
6396
6397         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6398         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6399         OUT_RING(pf | pipesrc);
6400         ADVANCE_LP_RING();
6401 out:
6402         return ret;
6403 }
6404
6405 /*
6406  * On gen7 we currently use the blit ring because (in early silicon at least)
6407  * the render ring doesn't give us interrpts for page flip completion, which
6408  * means clients will hang after the first flip is queued.  Fortunately the
6409  * blit ring generates interrupts properly, so use it instead.
6410  */
6411 static int intel_gen7_queue_flip(struct drm_device *dev,
6412                                  struct drm_crtc *crtc,
6413                                  struct drm_framebuffer *fb,
6414                                  struct drm_i915_gem_object *obj)
6415 {
6416         struct drm_i915_private *dev_priv = dev->dev_private;
6417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6419         int ret;
6420
6421         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6422         if (ret)
6423                 goto out;
6424
6425         ret = intel_ring_begin(ring, 4);
6426         if (ret)
6427                 goto out;
6428
6429         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6430         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6431         intel_ring_emit(ring, (obj->gtt_offset));
6432         intel_ring_emit(ring, (MI_NOOP));
6433         intel_ring_advance(ring);
6434 out:
6435         return ret;
6436 }
6437
6438 static int intel_default_queue_flip(struct drm_device *dev,
6439                                     struct drm_crtc *crtc,
6440                                     struct drm_framebuffer *fb,
6441                                     struct drm_i915_gem_object *obj)
6442 {
6443         return -ENODEV;
6444 }
6445
6446 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6447                                 struct drm_framebuffer *fb,
6448                                 struct drm_pending_vblank_event *event)
6449 {
6450         struct drm_device *dev = crtc->dev;
6451         struct drm_i915_private *dev_priv = dev->dev_private;
6452         struct intel_framebuffer *intel_fb;
6453         struct drm_i915_gem_object *obj;
6454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6455         struct intel_unpin_work *work;
6456         unsigned long flags;
6457         int ret;
6458
6459         work = kzalloc(sizeof *work, GFP_KERNEL);
6460         if (work == NULL)
6461                 return -ENOMEM;
6462
6463         work->event = event;
6464         work->dev = crtc->dev;
6465         intel_fb = to_intel_framebuffer(crtc->fb);
6466         work->old_fb_obj = intel_fb->obj;
6467         INIT_WORK(&work->work, intel_unpin_work_fn);
6468
6469         /* We borrow the event spin lock for protecting unpin_work */
6470         spin_lock_irqsave(&dev->event_lock, flags);
6471         if (intel_crtc->unpin_work) {
6472                 spin_unlock_irqrestore(&dev->event_lock, flags);
6473                 kfree(work);
6474
6475                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6476                 return -EBUSY;
6477         }
6478         intel_crtc->unpin_work = work;
6479         spin_unlock_irqrestore(&dev->event_lock, flags);
6480
6481         intel_fb = to_intel_framebuffer(fb);
6482         obj = intel_fb->obj;
6483
6484         mutex_lock(&dev->struct_mutex);
6485
6486         /* Reference the objects for the scheduled work. */
6487         drm_gem_object_reference(&work->old_fb_obj->base);
6488         drm_gem_object_reference(&obj->base);
6489
6490         crtc->fb = fb;
6491
6492         ret = drm_vblank_get(dev, intel_crtc->pipe);
6493         if (ret)
6494                 goto cleanup_objs;
6495
6496         work->pending_flip_obj = obj;
6497
6498         work->enable_stall_check = true;
6499
6500         /* Block clients from rendering to the new back buffer until
6501          * the flip occurs and the object is no longer visible.
6502          */
6503         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6504
6505         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6506         if (ret)
6507                 goto cleanup_pending;
6508
6509         mutex_unlock(&dev->struct_mutex);
6510
6511         trace_i915_flip_request(intel_crtc->plane, obj);
6512
6513         return 0;
6514
6515 cleanup_pending:
6516         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6517 cleanup_objs:
6518         drm_gem_object_unreference(&work->old_fb_obj->base);
6519         drm_gem_object_unreference(&obj->base);
6520         mutex_unlock(&dev->struct_mutex);
6521
6522         spin_lock_irqsave(&dev->event_lock, flags);
6523         intel_crtc->unpin_work = NULL;
6524         spin_unlock_irqrestore(&dev->event_lock, flags);
6525
6526         kfree(work);
6527
6528         return ret;
6529 }
6530
6531 static void intel_sanitize_modesetting(struct drm_device *dev,
6532                                        int pipe, int plane)
6533 {
6534         struct drm_i915_private *dev_priv = dev->dev_private;
6535         u32 reg, val;
6536
6537         if (HAS_PCH_SPLIT(dev))
6538                 return;
6539
6540         /* Who knows what state these registers were left in by the BIOS or
6541          * grub?
6542          *
6543          * If we leave the registers in a conflicting state (e.g. with the
6544          * display plane reading from the other pipe than the one we intend
6545          * to use) then when we attempt to teardown the active mode, we will
6546          * not disable the pipes and planes in the correct order -- leaving
6547          * a plane reading from a disabled pipe and possibly leading to
6548          * undefined behaviour.
6549          */
6550
6551         reg = DSPCNTR(plane);
6552         val = I915_READ(reg);
6553
6554         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6555                 return;
6556         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6557                 return;
6558
6559         /* This display plane is active and attached to the other CPU pipe. */
6560         pipe = !pipe;
6561
6562         /* Disable the plane and wait for it to stop reading from the pipe. */
6563         intel_disable_plane(dev_priv, plane, pipe);
6564         intel_disable_pipe(dev_priv, pipe);
6565 }
6566
6567 static void intel_crtc_reset(struct drm_crtc *crtc)
6568 {
6569         struct drm_device *dev = crtc->dev;
6570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6571
6572         /* Reset flags back to the 'unknown' status so that they
6573          * will be correctly set on the initial modeset.
6574          */
6575         intel_crtc->dpms_mode = -1;
6576
6577         /* We need to fix up any BIOS configuration that conflicts with
6578          * our expectations.
6579          */
6580         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6581 }
6582
6583 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6584         .dpms = intel_crtc_dpms,
6585         .mode_fixup = intel_crtc_mode_fixup,
6586         .mode_set = intel_crtc_mode_set,
6587         .mode_set_base = intel_pipe_set_base,
6588         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6589         .load_lut = intel_crtc_load_lut,
6590         .disable = intel_crtc_disable,
6591 };
6592
6593 static const struct drm_crtc_funcs intel_crtc_funcs = {
6594         .reset = intel_crtc_reset,
6595         .cursor_set = intel_crtc_cursor_set,
6596         .cursor_move = intel_crtc_cursor_move,
6597         .gamma_set = intel_crtc_gamma_set,
6598         .set_config = drm_crtc_helper_set_config,
6599         .destroy = intel_crtc_destroy,
6600         .page_flip = intel_crtc_page_flip,
6601 };
6602
6603 static void intel_crtc_init(struct drm_device *dev, int pipe)
6604 {
6605         drm_i915_private_t *dev_priv = dev->dev_private;
6606         struct intel_crtc *intel_crtc;
6607         int i;
6608
6609         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6610         if (intel_crtc == NULL)
6611                 return;
6612
6613         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6614
6615         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6616         for (i = 0; i < 256; i++) {
6617                 intel_crtc->lut_r[i] = i;
6618                 intel_crtc->lut_g[i] = i;
6619                 intel_crtc->lut_b[i] = i;
6620         }
6621
6622         /* Swap pipes & planes for FBC on pre-965 */
6623         intel_crtc->pipe = pipe;
6624         intel_crtc->plane = pipe;
6625         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6626                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6627                 intel_crtc->plane = !pipe;
6628         }
6629
6630         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6631                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6632         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6633         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6634
6635         intel_crtc_reset(&intel_crtc->base);
6636         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6637
6638         if (HAS_PCH_SPLIT(dev)) {
6639                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6640                 intel_helper_funcs.commit = ironlake_crtc_commit;
6641         } else {
6642                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6643                 intel_helper_funcs.commit = i9xx_crtc_commit;
6644         }
6645
6646         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6647
6648         intel_crtc->busy = false;
6649
6650         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6651                     (unsigned long)intel_crtc);
6652 }
6653
6654 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6655                                 struct drm_file *file)
6656 {
6657         drm_i915_private_t *dev_priv = dev->dev_private;
6658         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6659         struct drm_mode_object *drmmode_obj;
6660         struct intel_crtc *crtc;
6661
6662         if (!dev_priv) {
6663                 DRM_ERROR("called with no initialization\n");
6664                 return -EINVAL;
6665         }
6666
6667         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6668                         DRM_MODE_OBJECT_CRTC);
6669
6670         if (!drmmode_obj) {
6671                 DRM_ERROR("no such CRTC id\n");
6672                 return -EINVAL;
6673         }
6674
6675         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6676         pipe_from_crtc_id->pipe = crtc->pipe;
6677
6678         return 0;
6679 }
6680
6681 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6682 {
6683         struct intel_encoder *encoder;
6684         int index_mask = 0;
6685         int entry = 0;
6686
6687         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6688                 if (type_mask & encoder->clone_mask)
6689                         index_mask |= (1 << entry);
6690                 entry++;
6691         }
6692
6693         return index_mask;
6694 }
6695
6696 static bool has_edp_a(struct drm_device *dev)
6697 {
6698         struct drm_i915_private *dev_priv = dev->dev_private;
6699
6700         if (!IS_MOBILE(dev))
6701                 return false;
6702
6703         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6704                 return false;
6705
6706         if (IS_GEN5(dev) &&
6707             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6708                 return false;
6709
6710         return true;
6711 }
6712
6713 static void intel_setup_outputs(struct drm_device *dev)
6714 {
6715         struct drm_i915_private *dev_priv = dev->dev_private;
6716         struct intel_encoder *encoder;
6717         bool dpd_is_edp = false;
6718         bool has_lvds = false;
6719
6720         if (IS_MOBILE(dev) && !IS_I830(dev))
6721                 has_lvds = intel_lvds_init(dev);
6722         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6723                 /* disable the panel fitter on everything but LVDS */
6724                 I915_WRITE(PFIT_CONTROL, 0);
6725         }
6726
6727         if (HAS_PCH_SPLIT(dev)) {
6728                 dpd_is_edp = intel_dpd_is_edp(dev);
6729
6730                 if (has_edp_a(dev))
6731                         intel_dp_init(dev, DP_A);
6732
6733                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6734                         intel_dp_init(dev, PCH_DP_D);
6735         }
6736
6737         intel_crt_init(dev);
6738
6739         if (HAS_PCH_SPLIT(dev)) {
6740                 int found;
6741
6742                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6743                         /* PCH SDVOB multiplex with HDMIB */
6744                         found = intel_sdvo_init(dev, PCH_SDVOB);
6745                         if (!found)
6746                                 intel_hdmi_init(dev, HDMIB);
6747                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6748                                 intel_dp_init(dev, PCH_DP_B);
6749                 }
6750
6751                 if (I915_READ(HDMIC) & PORT_DETECTED)
6752                         intel_hdmi_init(dev, HDMIC);
6753
6754                 if (I915_READ(HDMID) & PORT_DETECTED)
6755                         intel_hdmi_init(dev, HDMID);
6756
6757                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6758                         intel_dp_init(dev, PCH_DP_C);
6759
6760                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6761                         intel_dp_init(dev, PCH_DP_D);
6762
6763         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6764                 bool found = false;
6765
6766                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6767                         DRM_DEBUG_KMS("probing SDVOB\n");
6768                         found = intel_sdvo_init(dev, SDVOB);
6769                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6770                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6771                                 intel_hdmi_init(dev, SDVOB);
6772                         }
6773
6774                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6775                                 DRM_DEBUG_KMS("probing DP_B\n");
6776                                 intel_dp_init(dev, DP_B);
6777                         }
6778                 }
6779
6780                 /* Before G4X SDVOC doesn't have its own detect register */
6781
6782                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6783                         DRM_DEBUG_KMS("probing SDVOC\n");
6784                         found = intel_sdvo_init(dev, SDVOC);
6785                 }
6786
6787                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6788
6789                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6790                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6791                                 intel_hdmi_init(dev, SDVOC);
6792                         }
6793                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6794                                 DRM_DEBUG_KMS("probing DP_C\n");
6795                                 intel_dp_init(dev, DP_C);
6796                         }
6797                 }
6798
6799                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6800                     (I915_READ(DP_D) & DP_DETECTED)) {
6801                         DRM_DEBUG_KMS("probing DP_D\n");
6802                         intel_dp_init(dev, DP_D);
6803                 }
6804         } else if (IS_GEN2(dev))
6805                 intel_dvo_init(dev);
6806
6807         if (SUPPORTS_TV(dev))
6808                 intel_tv_init(dev);
6809
6810         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6811                 encoder->base.possible_crtcs = encoder->crtc_mask;
6812                 encoder->base.possible_clones =
6813                         intel_encoder_clones(dev, encoder->clone_mask);
6814         }
6815
6816         intel_panel_setup_backlight(dev);
6817
6818         /* disable all the possible outputs/crtcs before entering KMS mode */
6819         drm_helper_disable_unused_functions(dev);
6820 }
6821
6822 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6823 {
6824         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6825
6826         drm_framebuffer_cleanup(fb);
6827         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6828
6829         kfree(intel_fb);
6830 }
6831
6832 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6833                                                 struct drm_file *file,
6834                                                 unsigned int *handle)
6835 {
6836         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6837         struct drm_i915_gem_object *obj = intel_fb->obj;
6838
6839         return drm_gem_handle_create(file, &obj->base, handle);
6840 }
6841
6842 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6843         .destroy = intel_user_framebuffer_destroy,
6844         .create_handle = intel_user_framebuffer_create_handle,
6845 };
6846
6847 int intel_framebuffer_init(struct drm_device *dev,
6848                            struct intel_framebuffer *intel_fb,
6849                            struct drm_mode_fb_cmd *mode_cmd,
6850                            struct drm_i915_gem_object *obj)
6851 {
6852         int ret;
6853
6854         if (obj->tiling_mode == I915_TILING_Y)
6855                 return -EINVAL;
6856
6857         if (mode_cmd->pitch & 63)
6858                 return -EINVAL;
6859
6860         switch (mode_cmd->bpp) {
6861         case 8:
6862         case 16:
6863         case 24:
6864         case 32:
6865                 break;
6866         default:
6867                 return -EINVAL;
6868         }
6869
6870         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6871         if (ret) {
6872                 DRM_ERROR("framebuffer init failed %d\n", ret);
6873                 return ret;
6874         }
6875
6876         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6877         intel_fb->obj = obj;
6878         return 0;
6879 }
6880
6881 static struct drm_framebuffer *
6882 intel_user_framebuffer_create(struct drm_device *dev,
6883                               struct drm_file *filp,
6884                               struct drm_mode_fb_cmd *mode_cmd)
6885 {
6886         struct drm_i915_gem_object *obj;
6887
6888         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6889         if (&obj->base == NULL)
6890                 return ERR_PTR(-ENOENT);
6891
6892         return intel_framebuffer_create(dev, mode_cmd, obj);
6893 }
6894
6895 static const struct drm_mode_config_funcs intel_mode_funcs = {
6896         .fb_create = intel_user_framebuffer_create,
6897         .output_poll_changed = intel_fb_output_poll_changed,
6898 };
6899
6900 static struct drm_i915_gem_object *
6901 intel_alloc_context_page(struct drm_device *dev)
6902 {
6903         struct drm_i915_gem_object *ctx;
6904         int ret;
6905
6906         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6907
6908         ctx = i915_gem_alloc_object(dev, 4096);
6909         if (!ctx) {
6910                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6911                 return NULL;
6912         }
6913
6914         ret = i915_gem_object_pin(ctx, 4096, true);
6915         if (ret) {
6916                 DRM_ERROR("failed to pin power context: %d\n", ret);
6917                 goto err_unref;
6918         }
6919
6920         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6921         if (ret) {
6922                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6923                 goto err_unpin;
6924         }
6925
6926         return ctx;
6927
6928 err_unpin:
6929         i915_gem_object_unpin(ctx);
6930 err_unref:
6931         drm_gem_object_unreference(&ctx->base);
6932         mutex_unlock(&dev->struct_mutex);
6933         return NULL;
6934 }
6935
6936 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6937 {
6938         struct drm_i915_private *dev_priv = dev->dev_private;
6939         u16 rgvswctl;
6940
6941         rgvswctl = I915_READ16(MEMSWCTL);
6942         if (rgvswctl & MEMCTL_CMD_STS) {
6943                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6944                 return false; /* still busy with another command */
6945         }
6946
6947         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6948                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6949         I915_WRITE16(MEMSWCTL, rgvswctl);
6950         POSTING_READ16(MEMSWCTL);
6951
6952         rgvswctl |= MEMCTL_CMD_STS;
6953         I915_WRITE16(MEMSWCTL, rgvswctl);
6954
6955         return true;
6956 }
6957
6958 void ironlake_enable_drps(struct drm_device *dev)
6959 {
6960         struct drm_i915_private *dev_priv = dev->dev_private;
6961         u32 rgvmodectl = I915_READ(MEMMODECTL);
6962         u8 fmax, fmin, fstart, vstart;
6963
6964         /* Enable temp reporting */
6965         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6966         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6967
6968         /* 100ms RC evaluation intervals */
6969         I915_WRITE(RCUPEI, 100000);
6970         I915_WRITE(RCDNEI, 100000);
6971
6972         /* Set max/min thresholds to 90ms and 80ms respectively */
6973         I915_WRITE(RCBMAXAVG, 90000);
6974         I915_WRITE(RCBMINAVG, 80000);
6975
6976         I915_WRITE(MEMIHYST, 1);
6977
6978         /* Set up min, max, and cur for interrupt handling */
6979         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6980         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6981         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6982                 MEMMODE_FSTART_SHIFT;
6983
6984         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6985                 PXVFREQ_PX_SHIFT;
6986
6987         dev_priv->fmax = fmax; /* IPS callback will increase this */
6988         dev_priv->fstart = fstart;
6989
6990         dev_priv->max_delay = fstart;
6991         dev_priv->min_delay = fmin;
6992         dev_priv->cur_delay = fstart;
6993
6994         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6995                          fmax, fmin, fstart);
6996
6997         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6998
6999         /*
7000          * Interrupts will be enabled in ironlake_irq_postinstall
7001          */
7002
7003         I915_WRITE(VIDSTART, vstart);
7004         POSTING_READ(VIDSTART);
7005
7006         rgvmodectl |= MEMMODE_SWMODE_EN;
7007         I915_WRITE(MEMMODECTL, rgvmodectl);
7008
7009         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7010                 DRM_ERROR("stuck trying to change perf mode\n");
7011         msleep(1);
7012
7013         ironlake_set_drps(dev, fstart);
7014
7015         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7016                 I915_READ(0x112e0);
7017         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7018         dev_priv->last_count2 = I915_READ(0x112f4);
7019         getrawmonotonic(&dev_priv->last_time2);
7020 }
7021
7022 void ironlake_disable_drps(struct drm_device *dev)
7023 {
7024         struct drm_i915_private *dev_priv = dev->dev_private;
7025         u16 rgvswctl = I915_READ16(MEMSWCTL);
7026
7027         /* Ack interrupts, disable EFC interrupt */
7028         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7029         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7030         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7031         I915_WRITE(DEIIR, DE_PCU_EVENT);
7032         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7033
7034         /* Go back to the starting frequency */
7035         ironlake_set_drps(dev, dev_priv->fstart);
7036         msleep(1);
7037         rgvswctl |= MEMCTL_CMD_STS;
7038         I915_WRITE(MEMSWCTL, rgvswctl);
7039         msleep(1);
7040
7041 }
7042
7043 void gen6_set_rps(struct drm_device *dev, u8 val)
7044 {
7045         struct drm_i915_private *dev_priv = dev->dev_private;
7046         u32 swreq;
7047
7048         swreq = (val & 0x3ff) << 25;
7049         I915_WRITE(GEN6_RPNSWREQ, swreq);
7050 }
7051
7052 void gen6_disable_rps(struct drm_device *dev)
7053 {
7054         struct drm_i915_private *dev_priv = dev->dev_private;
7055
7056         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7057         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7058         I915_WRITE(GEN6_PMIER, 0);
7059
7060         spin_lock_irq(&dev_priv->rps_lock);
7061         dev_priv->pm_iir = 0;
7062         spin_unlock_irq(&dev_priv->rps_lock);
7063
7064         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7065 }
7066
7067 static unsigned long intel_pxfreq(u32 vidfreq)
7068 {
7069         unsigned long freq;
7070         int div = (vidfreq & 0x3f0000) >> 16;
7071         int post = (vidfreq & 0x3000) >> 12;
7072         int pre = (vidfreq & 0x7);
7073
7074         if (!pre)
7075                 return 0;
7076
7077         freq = ((div * 133333) / ((1<<post) * pre));
7078
7079         return freq;
7080 }
7081
7082 void intel_init_emon(struct drm_device *dev)
7083 {
7084         struct drm_i915_private *dev_priv = dev->dev_private;
7085         u32 lcfuse;
7086         u8 pxw[16];
7087         int i;
7088
7089         /* Disable to program */
7090         I915_WRITE(ECR, 0);
7091         POSTING_READ(ECR);
7092
7093         /* Program energy weights for various events */
7094         I915_WRITE(SDEW, 0x15040d00);
7095         I915_WRITE(CSIEW0, 0x007f0000);
7096         I915_WRITE(CSIEW1, 0x1e220004);
7097         I915_WRITE(CSIEW2, 0x04000004);
7098
7099         for (i = 0; i < 5; i++)
7100                 I915_WRITE(PEW + (i * 4), 0);
7101         for (i = 0; i < 3; i++)
7102                 I915_WRITE(DEW + (i * 4), 0);
7103
7104         /* Program P-state weights to account for frequency power adjustment */
7105         for (i = 0; i < 16; i++) {
7106                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7107                 unsigned long freq = intel_pxfreq(pxvidfreq);
7108                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7109                         PXVFREQ_PX_SHIFT;
7110                 unsigned long val;
7111
7112                 val = vid * vid;
7113                 val *= (freq / 1000);
7114                 val *= 255;
7115                 val /= (127*127*900);
7116                 if (val > 0xff)
7117                         DRM_ERROR("bad pxval: %ld\n", val);
7118                 pxw[i] = val;
7119         }
7120         /* Render standby states get 0 weight */
7121         pxw[14] = 0;
7122         pxw[15] = 0;
7123
7124         for (i = 0; i < 4; i++) {
7125                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7126                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7127                 I915_WRITE(PXW + (i * 4), val);
7128         }
7129
7130         /* Adjust magic regs to magic values (more experimental results) */
7131         I915_WRITE(OGW0, 0);
7132         I915_WRITE(OGW1, 0);
7133         I915_WRITE(EG0, 0x00007f00);
7134         I915_WRITE(EG1, 0x0000000e);
7135         I915_WRITE(EG2, 0x000e0000);
7136         I915_WRITE(EG3, 0x68000300);
7137         I915_WRITE(EG4, 0x42000000);
7138         I915_WRITE(EG5, 0x00140031);
7139         I915_WRITE(EG6, 0);
7140         I915_WRITE(EG7, 0);
7141
7142         for (i = 0; i < 8; i++)
7143                 I915_WRITE(PXWL + (i * 4), 0);
7144
7145         /* Enable PMON + select events */
7146         I915_WRITE(ECR, 0x80000019);
7147
7148         lcfuse = I915_READ(LCFUSE02);
7149
7150         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7151 }
7152
7153 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7154 {
7155         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7156         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7157         u32 pcu_mbox, rc6_mask = 0;
7158         int cur_freq, min_freq, max_freq;
7159         int i;
7160
7161         /* Here begins a magic sequence of register writes to enable
7162          * auto-downclocking.
7163          *
7164          * Perhaps there might be some value in exposing these to
7165          * userspace...
7166          */
7167         I915_WRITE(GEN6_RC_STATE, 0);
7168         mutex_lock(&dev_priv->dev->struct_mutex);
7169         gen6_gt_force_wake_get(dev_priv);
7170
7171         /* disable the counters and set deterministic thresholds */
7172         I915_WRITE(GEN6_RC_CONTROL, 0);
7173
7174         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7175         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7176         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7177         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7178         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7179
7180         for (i = 0; i < I915_NUM_RINGS; i++)
7181                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7182
7183         I915_WRITE(GEN6_RC_SLEEP, 0);
7184         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7185         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7186         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7187         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7188
7189         if (i915_enable_rc6)
7190                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7191                         GEN6_RC_CTL_RC6_ENABLE;
7192
7193         I915_WRITE(GEN6_RC_CONTROL,
7194                    rc6_mask |
7195                    GEN6_RC_CTL_EI_MODE(1) |
7196                    GEN6_RC_CTL_HW_ENABLE);
7197
7198         I915_WRITE(GEN6_RPNSWREQ,
7199                    GEN6_FREQUENCY(10) |
7200                    GEN6_OFFSET(0) |
7201                    GEN6_AGGRESSIVE_TURBO);
7202         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7203                    GEN6_FREQUENCY(12));
7204
7205         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7206         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7207                    18 << 24 |
7208                    6 << 16);
7209         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7210         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7211         I915_WRITE(GEN6_RP_UP_EI, 100000);
7212         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7213         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7214         I915_WRITE(GEN6_RP_CONTROL,
7215                    GEN6_RP_MEDIA_TURBO |
7216                    GEN6_RP_USE_NORMAL_FREQ |
7217                    GEN6_RP_MEDIA_IS_GFX |
7218                    GEN6_RP_ENABLE |
7219                    GEN6_RP_UP_BUSY_AVG |
7220                    GEN6_RP_DOWN_IDLE_CONT);
7221
7222         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7223                      500))
7224                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7225
7226         I915_WRITE(GEN6_PCODE_DATA, 0);
7227         I915_WRITE(GEN6_PCODE_MAILBOX,
7228                    GEN6_PCODE_READY |
7229                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7230         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7231                      500))
7232                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7233
7234         min_freq = (rp_state_cap & 0xff0000) >> 16;
7235         max_freq = rp_state_cap & 0xff;
7236         cur_freq = (gt_perf_status & 0xff00) >> 8;
7237
7238         /* Check for overclock support */
7239         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7240                      500))
7241                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7242         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7243         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7244         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7245                      500))
7246                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7247         if (pcu_mbox & (1<<31)) { /* OC supported */
7248                 max_freq = pcu_mbox & 0xff;
7249                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7250         }
7251
7252         /* In units of 100MHz */
7253         dev_priv->max_delay = max_freq;
7254         dev_priv->min_delay = min_freq;
7255         dev_priv->cur_delay = cur_freq;
7256
7257         /* requires MSI enabled */
7258         I915_WRITE(GEN6_PMIER,
7259                    GEN6_PM_MBOX_EVENT |
7260                    GEN6_PM_THERMAL_EVENT |
7261                    GEN6_PM_RP_DOWN_TIMEOUT |
7262                    GEN6_PM_RP_UP_THRESHOLD |
7263                    GEN6_PM_RP_DOWN_THRESHOLD |
7264                    GEN6_PM_RP_UP_EI_EXPIRED |
7265                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7266         spin_lock_irq(&dev_priv->rps_lock);
7267         WARN_ON(dev_priv->pm_iir != 0);
7268         I915_WRITE(GEN6_PMIMR, 0);
7269         spin_unlock_irq(&dev_priv->rps_lock);
7270         /* enable all PM interrupts */
7271         I915_WRITE(GEN6_PMINTRMSK, 0);
7272
7273         gen6_gt_force_wake_put(dev_priv);
7274         mutex_unlock(&dev_priv->dev->struct_mutex);
7275 }
7276
7277 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7278 {
7279         int min_freq = 15;
7280         int gpu_freq, ia_freq, max_ia_freq;
7281         int scaling_factor = 180;
7282
7283         max_ia_freq = cpufreq_quick_get_max(0);
7284         /*
7285          * Default to measured freq if none found, PCU will ensure we don't go
7286          * over
7287          */
7288         if (!max_ia_freq)
7289                 max_ia_freq = tsc_khz;
7290
7291         /* Convert from kHz to MHz */
7292         max_ia_freq /= 1000;
7293
7294         mutex_lock(&dev_priv->dev->struct_mutex);
7295
7296         /*
7297          * For each potential GPU frequency, load a ring frequency we'd like
7298          * to use for memory access.  We do this by specifying the IA frequency
7299          * the PCU should use as a reference to determine the ring frequency.
7300          */
7301         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7302              gpu_freq--) {
7303                 int diff = dev_priv->max_delay - gpu_freq;
7304
7305                 /*
7306                  * For GPU frequencies less than 750MHz, just use the lowest
7307                  * ring freq.
7308                  */
7309                 if (gpu_freq < min_freq)
7310                         ia_freq = 800;
7311                 else
7312                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7313                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7314
7315                 I915_WRITE(GEN6_PCODE_DATA,
7316                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7317                            gpu_freq);
7318                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7319                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7320                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7321                               GEN6_PCODE_READY) == 0, 10)) {
7322                         DRM_ERROR("pcode write of freq table timed out\n");
7323                         continue;
7324                 }
7325         }
7326
7327         mutex_unlock(&dev_priv->dev->struct_mutex);
7328 }
7329
7330 static void ironlake_init_clock_gating(struct drm_device *dev)
7331 {
7332         struct drm_i915_private *dev_priv = dev->dev_private;
7333         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7334
7335         /* Required for FBC */
7336         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7337                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7338                 DPFDUNIT_CLOCK_GATE_DISABLE;
7339         /* Required for CxSR */
7340         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7341
7342         I915_WRITE(PCH_3DCGDIS0,
7343                    MARIUNIT_CLOCK_GATE_DISABLE |
7344                    SVSMUNIT_CLOCK_GATE_DISABLE);
7345         I915_WRITE(PCH_3DCGDIS1,
7346                    VFMUNIT_CLOCK_GATE_DISABLE);
7347
7348         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7349
7350         /*
7351          * According to the spec the following bits should be set in
7352          * order to enable memory self-refresh
7353          * The bit 22/21 of 0x42004
7354          * The bit 5 of 0x42020
7355          * The bit 15 of 0x45000
7356          */
7357         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7358                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7359                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7360         I915_WRITE(ILK_DSPCLK_GATE,
7361                    (I915_READ(ILK_DSPCLK_GATE) |
7362                     ILK_DPARB_CLK_GATE));
7363         I915_WRITE(DISP_ARB_CTL,
7364                    (I915_READ(DISP_ARB_CTL) |
7365                     DISP_FBC_WM_DIS));
7366         I915_WRITE(WM3_LP_ILK, 0);
7367         I915_WRITE(WM2_LP_ILK, 0);
7368         I915_WRITE(WM1_LP_ILK, 0);
7369
7370         /*
7371          * Based on the document from hardware guys the following bits
7372          * should be set unconditionally in order to enable FBC.
7373          * The bit 22 of 0x42000
7374          * The bit 22 of 0x42004
7375          * The bit 7,8,9 of 0x42020.
7376          */
7377         if (IS_IRONLAKE_M(dev)) {
7378                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7379                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7380                            ILK_FBCQ_DIS);
7381                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7382                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7383                            ILK_DPARB_GATE);
7384                 I915_WRITE(ILK_DSPCLK_GATE,
7385                            I915_READ(ILK_DSPCLK_GATE) |
7386                            ILK_DPFC_DIS1 |
7387                            ILK_DPFC_DIS2 |
7388                            ILK_CLK_FBC);
7389         }
7390
7391         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7392                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7393                    ILK_ELPIN_409_SELECT);
7394         I915_WRITE(_3D_CHICKEN2,
7395                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7396                    _3D_CHICKEN2_WM_READ_PIPELINED);
7397 }
7398
7399 static void gen6_init_clock_gating(struct drm_device *dev)
7400 {
7401         struct drm_i915_private *dev_priv = dev->dev_private;
7402         int pipe;
7403         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7404
7405         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7406
7407         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7408                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7409                    ILK_ELPIN_409_SELECT);
7410
7411         I915_WRITE(WM3_LP_ILK, 0);
7412         I915_WRITE(WM2_LP_ILK, 0);
7413         I915_WRITE(WM1_LP_ILK, 0);
7414
7415         /*
7416          * According to the spec the following bits should be
7417          * set in order to enable memory self-refresh and fbc:
7418          * The bit21 and bit22 of 0x42000
7419          * The bit21 and bit22 of 0x42004
7420          * The bit5 and bit7 of 0x42020
7421          * The bit14 of 0x70180
7422          * The bit14 of 0x71180
7423          */
7424         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7425                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7426                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7427         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7428                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7429                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7430         I915_WRITE(ILK_DSPCLK_GATE,
7431                    I915_READ(ILK_DSPCLK_GATE) |
7432                    ILK_DPARB_CLK_GATE  |
7433                    ILK_DPFD_CLK_GATE);
7434
7435         for_each_pipe(pipe)
7436                 I915_WRITE(DSPCNTR(pipe),
7437                            I915_READ(DSPCNTR(pipe)) |
7438                            DISPPLANE_TRICKLE_FEED_DISABLE);
7439 }
7440
7441 static void ivybridge_init_clock_gating(struct drm_device *dev)
7442 {
7443         struct drm_i915_private *dev_priv = dev->dev_private;
7444         int pipe;
7445         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7446
7447         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7448
7449         I915_WRITE(WM3_LP_ILK, 0);
7450         I915_WRITE(WM2_LP_ILK, 0);
7451         I915_WRITE(WM1_LP_ILK, 0);
7452
7453         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7454
7455         for_each_pipe(pipe)
7456                 I915_WRITE(DSPCNTR(pipe),
7457                            I915_READ(DSPCNTR(pipe)) |
7458                            DISPPLANE_TRICKLE_FEED_DISABLE);
7459 }
7460
7461 static void g4x_init_clock_gating(struct drm_device *dev)
7462 {
7463         struct drm_i915_private *dev_priv = dev->dev_private;
7464         uint32_t dspclk_gate;
7465
7466         I915_WRITE(RENCLK_GATE_D1, 0);
7467         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7468                    GS_UNIT_CLOCK_GATE_DISABLE |
7469                    CL_UNIT_CLOCK_GATE_DISABLE);
7470         I915_WRITE(RAMCLK_GATE_D, 0);
7471         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7472                 OVRUNIT_CLOCK_GATE_DISABLE |
7473                 OVCUNIT_CLOCK_GATE_DISABLE;
7474         if (IS_GM45(dev))
7475                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7476         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7477 }
7478
7479 static void crestline_init_clock_gating(struct drm_device *dev)
7480 {
7481         struct drm_i915_private *dev_priv = dev->dev_private;
7482
7483         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7484         I915_WRITE(RENCLK_GATE_D2, 0);
7485         I915_WRITE(DSPCLK_GATE_D, 0);
7486         I915_WRITE(RAMCLK_GATE_D, 0);
7487         I915_WRITE16(DEUC, 0);
7488 }
7489
7490 static void broadwater_init_clock_gating(struct drm_device *dev)
7491 {
7492         struct drm_i915_private *dev_priv = dev->dev_private;
7493
7494         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7495                    I965_RCC_CLOCK_GATE_DISABLE |
7496                    I965_RCPB_CLOCK_GATE_DISABLE |
7497                    I965_ISC_CLOCK_GATE_DISABLE |
7498                    I965_FBC_CLOCK_GATE_DISABLE);
7499         I915_WRITE(RENCLK_GATE_D2, 0);
7500 }
7501
7502 static void gen3_init_clock_gating(struct drm_device *dev)
7503 {
7504         struct drm_i915_private *dev_priv = dev->dev_private;
7505         u32 dstate = I915_READ(D_STATE);
7506
7507         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7508                 DSTATE_DOT_CLOCK_GATING;
7509         I915_WRITE(D_STATE, dstate);
7510 }
7511
7512 static void i85x_init_clock_gating(struct drm_device *dev)
7513 {
7514         struct drm_i915_private *dev_priv = dev->dev_private;
7515
7516         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7517 }
7518
7519 static void i830_init_clock_gating(struct drm_device *dev)
7520 {
7521         struct drm_i915_private *dev_priv = dev->dev_private;
7522
7523         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7524 }
7525
7526 static void ibx_init_clock_gating(struct drm_device *dev)
7527 {
7528         struct drm_i915_private *dev_priv = dev->dev_private;
7529
7530         /*
7531          * On Ibex Peak and Cougar Point, we need to disable clock
7532          * gating for the panel power sequencer or it will fail to
7533          * start up when no ports are active.
7534          */
7535         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7536 }
7537
7538 static void cpt_init_clock_gating(struct drm_device *dev)
7539 {
7540         struct drm_i915_private *dev_priv = dev->dev_private;
7541
7542         /*
7543          * On Ibex Peak and Cougar Point, we need to disable clock
7544          * gating for the panel power sequencer or it will fail to
7545          * start up when no ports are active.
7546          */
7547         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7548         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7549                    DPLS_EDP_PPS_FIX_DIS);
7550 }
7551
7552 static void ironlake_teardown_rc6(struct drm_device *dev)
7553 {
7554         struct drm_i915_private *dev_priv = dev->dev_private;
7555
7556         if (dev_priv->renderctx) {
7557                 i915_gem_object_unpin(dev_priv->renderctx);
7558                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7559                 dev_priv->renderctx = NULL;
7560         }
7561
7562         if (dev_priv->pwrctx) {
7563                 i915_gem_object_unpin(dev_priv->pwrctx);
7564                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7565                 dev_priv->pwrctx = NULL;
7566         }
7567 }
7568
7569 static void ironlake_disable_rc6(struct drm_device *dev)
7570 {
7571         struct drm_i915_private *dev_priv = dev->dev_private;
7572
7573         if (I915_READ(PWRCTXA)) {
7574                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7575                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7576                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7577                          50);
7578
7579                 I915_WRITE(PWRCTXA, 0);
7580                 POSTING_READ(PWRCTXA);
7581
7582                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7583                 POSTING_READ(RSTDBYCTL);
7584         }
7585
7586         ironlake_teardown_rc6(dev);
7587 }
7588
7589 static int ironlake_setup_rc6(struct drm_device *dev)
7590 {
7591         struct drm_i915_private *dev_priv = dev->dev_private;
7592
7593         if (dev_priv->renderctx == NULL)
7594                 dev_priv->renderctx = intel_alloc_context_page(dev);
7595         if (!dev_priv->renderctx)
7596                 return -ENOMEM;
7597
7598         if (dev_priv->pwrctx == NULL)
7599                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7600         if (!dev_priv->pwrctx) {
7601                 ironlake_teardown_rc6(dev);
7602                 return -ENOMEM;
7603         }
7604
7605         return 0;
7606 }
7607
7608 void ironlake_enable_rc6(struct drm_device *dev)
7609 {
7610         struct drm_i915_private *dev_priv = dev->dev_private;
7611         int ret;
7612
7613         /* rc6 disabled by default due to repeated reports of hanging during
7614          * boot and resume.
7615          */
7616         if (!i915_enable_rc6)
7617                 return;
7618
7619         mutex_lock(&dev->struct_mutex);
7620         ret = ironlake_setup_rc6(dev);
7621         if (ret) {
7622                 mutex_unlock(&dev->struct_mutex);
7623                 return;
7624         }
7625
7626         /*
7627          * GPU can automatically power down the render unit if given a page
7628          * to save state.
7629          */
7630         ret = BEGIN_LP_RING(6);
7631         if (ret) {
7632                 ironlake_teardown_rc6(dev);
7633                 mutex_unlock(&dev->struct_mutex);
7634                 return;
7635         }
7636
7637         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7638         OUT_RING(MI_SET_CONTEXT);
7639         OUT_RING(dev_priv->renderctx->gtt_offset |
7640                  MI_MM_SPACE_GTT |
7641                  MI_SAVE_EXT_STATE_EN |
7642                  MI_RESTORE_EXT_STATE_EN |
7643                  MI_RESTORE_INHIBIT);
7644         OUT_RING(MI_SUSPEND_FLUSH);
7645         OUT_RING(MI_NOOP);
7646         OUT_RING(MI_FLUSH);
7647         ADVANCE_LP_RING();
7648
7649         /*
7650          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7651          * does an implicit flush, combined with MI_FLUSH above, it should be
7652          * safe to assume that renderctx is valid
7653          */
7654         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7655         if (ret) {
7656                 DRM_ERROR("failed to enable ironlake power power savings\n");
7657                 ironlake_teardown_rc6(dev);
7658                 mutex_unlock(&dev->struct_mutex);
7659                 return;
7660         }
7661
7662         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7663         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7664         mutex_unlock(&dev->struct_mutex);
7665 }
7666
7667 void intel_init_clock_gating(struct drm_device *dev)
7668 {
7669         struct drm_i915_private *dev_priv = dev->dev_private;
7670
7671         dev_priv->display.init_clock_gating(dev);
7672
7673         if (dev_priv->display.init_pch_clock_gating)
7674                 dev_priv->display.init_pch_clock_gating(dev);
7675 }
7676
7677 /* Set up chip specific display functions */
7678 static void intel_init_display(struct drm_device *dev)
7679 {
7680         struct drm_i915_private *dev_priv = dev->dev_private;
7681
7682         /* We always want a DPMS function */
7683         if (HAS_PCH_SPLIT(dev)) {
7684                 dev_priv->display.dpms = ironlake_crtc_dpms;
7685                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7686         } else {
7687                 dev_priv->display.dpms = i9xx_crtc_dpms;
7688                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7689         }
7690
7691         if (I915_HAS_FBC(dev)) {
7692                 if (HAS_PCH_SPLIT(dev)) {
7693                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7694                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7695                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7696                 } else if (IS_GM45(dev)) {
7697                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7698                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7699                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7700                 } else if (IS_CRESTLINE(dev)) {
7701                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7702                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7703                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7704                 }
7705                 /* 855GM needs testing */
7706         }
7707
7708         /* Returns the core display clock speed */
7709         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7710                 dev_priv->display.get_display_clock_speed =
7711                         i945_get_display_clock_speed;
7712         else if (IS_I915G(dev))
7713                 dev_priv->display.get_display_clock_speed =
7714                         i915_get_display_clock_speed;
7715         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7716                 dev_priv->display.get_display_clock_speed =
7717                         i9xx_misc_get_display_clock_speed;
7718         else if (IS_I915GM(dev))
7719                 dev_priv->display.get_display_clock_speed =
7720                         i915gm_get_display_clock_speed;
7721         else if (IS_I865G(dev))
7722                 dev_priv->display.get_display_clock_speed =
7723                         i865_get_display_clock_speed;
7724         else if (IS_I85X(dev))
7725                 dev_priv->display.get_display_clock_speed =
7726                         i855_get_display_clock_speed;
7727         else /* 852, 830 */
7728                 dev_priv->display.get_display_clock_speed =
7729                         i830_get_display_clock_speed;
7730
7731         /* For FIFO watermark updates */
7732         if (HAS_PCH_SPLIT(dev)) {
7733                 if (HAS_PCH_IBX(dev))
7734                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7735                 else if (HAS_PCH_CPT(dev))
7736                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7737
7738                 if (IS_GEN5(dev)) {
7739                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7740                                 dev_priv->display.update_wm = ironlake_update_wm;
7741                         else {
7742                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7743                                               "Disable CxSR\n");
7744                                 dev_priv->display.update_wm = NULL;
7745                         }
7746                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7747                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7748                 } else if (IS_GEN6(dev)) {
7749                         if (SNB_READ_WM0_LATENCY()) {
7750                                 dev_priv->display.update_wm = sandybridge_update_wm;
7751                         } else {
7752                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7753                                               "Disable CxSR\n");
7754                                 dev_priv->display.update_wm = NULL;
7755                         }
7756                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7757                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7758                 } else if (IS_IVYBRIDGE(dev)) {
7759                         /* FIXME: detect B0+ stepping and use auto training */
7760                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7761                         if (SNB_READ_WM0_LATENCY()) {
7762                                 dev_priv->display.update_wm = sandybridge_update_wm;
7763                         } else {
7764                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7765                                               "Disable CxSR\n");
7766                                 dev_priv->display.update_wm = NULL;
7767                         }
7768                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7769
7770                 } else
7771                         dev_priv->display.update_wm = NULL;
7772         } else if (IS_PINEVIEW(dev)) {
7773                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7774                                             dev_priv->is_ddr3,
7775                                             dev_priv->fsb_freq,
7776                                             dev_priv->mem_freq)) {
7777                         DRM_INFO("failed to find known CxSR latency "
7778                                  "(found ddr%s fsb freq %d, mem freq %d), "
7779                                  "disabling CxSR\n",
7780                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7781                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7782                         /* Disable CxSR and never update its watermark again */
7783                         pineview_disable_cxsr(dev);
7784                         dev_priv->display.update_wm = NULL;
7785                 } else
7786                         dev_priv->display.update_wm = pineview_update_wm;
7787                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7788         } else if (IS_G4X(dev)) {
7789                 dev_priv->display.update_wm = g4x_update_wm;
7790                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7791         } else if (IS_GEN4(dev)) {
7792                 dev_priv->display.update_wm = i965_update_wm;
7793                 if (IS_CRESTLINE(dev))
7794                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7795                 else if (IS_BROADWATER(dev))
7796                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7797         } else if (IS_GEN3(dev)) {
7798                 dev_priv->display.update_wm = i9xx_update_wm;
7799                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7800                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7801         } else if (IS_I865G(dev)) {
7802                 dev_priv->display.update_wm = i830_update_wm;
7803                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7804                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7805         } else if (IS_I85X(dev)) {
7806                 dev_priv->display.update_wm = i9xx_update_wm;
7807                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7808                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7809         } else {
7810                 dev_priv->display.update_wm = i830_update_wm;
7811                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7812                 if (IS_845G(dev))
7813                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7814                 else
7815                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7816         }
7817
7818         /* Default just returns -ENODEV to indicate unsupported */
7819         dev_priv->display.queue_flip = intel_default_queue_flip;
7820
7821         switch (INTEL_INFO(dev)->gen) {
7822         case 2:
7823                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7824                 break;
7825
7826         case 3:
7827                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7828                 break;
7829
7830         case 4:
7831         case 5:
7832                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7833                 break;
7834
7835         case 6:
7836                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7837                 break;
7838         case 7:
7839                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7840                 break;
7841         }
7842 }
7843
7844 /*
7845  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7846  * resume, or other times.  This quirk makes sure that's the case for
7847  * affected systems.
7848  */
7849 static void quirk_pipea_force (struct drm_device *dev)
7850 {
7851         struct drm_i915_private *dev_priv = dev->dev_private;
7852
7853         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7854         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7855 }
7856
7857 struct intel_quirk {
7858         int device;
7859         int subsystem_vendor;
7860         int subsystem_device;
7861         void (*hook)(struct drm_device *dev);
7862 };
7863
7864 struct intel_quirk intel_quirks[] = {
7865         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7866         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7867         /* HP Mini needs pipe A force quirk (LP: #322104) */
7868         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7869
7870         /* Thinkpad R31 needs pipe A force quirk */
7871         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7872         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7873         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7874
7875         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7876         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7877         /* ThinkPad X40 needs pipe A force quirk */
7878
7879         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7880         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7881
7882         /* 855 & before need to leave pipe A & dpll A up */
7883         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7884         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7885 };
7886
7887 static void intel_init_quirks(struct drm_device *dev)
7888 {
7889         struct pci_dev *d = dev->pdev;
7890         int i;
7891
7892         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7893                 struct intel_quirk *q = &intel_quirks[i];
7894
7895                 if (d->device == q->device &&
7896                     (d->subsystem_vendor == q->subsystem_vendor ||
7897                      q->subsystem_vendor == PCI_ANY_ID) &&
7898                     (d->subsystem_device == q->subsystem_device ||
7899                      q->subsystem_device == PCI_ANY_ID))
7900                         q->hook(dev);
7901         }
7902 }
7903
7904 /* Disable the VGA plane that we never use */
7905 static void i915_disable_vga(struct drm_device *dev)
7906 {
7907         struct drm_i915_private *dev_priv = dev->dev_private;
7908         u8 sr1;
7909         u32 vga_reg;
7910
7911         if (HAS_PCH_SPLIT(dev))
7912                 vga_reg = CPU_VGACNTRL;
7913         else
7914                 vga_reg = VGACNTRL;
7915
7916         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7917         outb(1, VGA_SR_INDEX);
7918         sr1 = inb(VGA_SR_DATA);
7919         outb(sr1 | 1<<5, VGA_SR_DATA);
7920         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7921         udelay(300);
7922
7923         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7924         POSTING_READ(vga_reg);
7925 }
7926
7927 void intel_modeset_init(struct drm_device *dev)
7928 {
7929         struct drm_i915_private *dev_priv = dev->dev_private;
7930         int i;
7931
7932         drm_mode_config_init(dev);
7933
7934         dev->mode_config.min_width = 0;
7935         dev->mode_config.min_height = 0;
7936
7937         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7938
7939         intel_init_quirks(dev);
7940
7941         intel_init_display(dev);
7942
7943         if (IS_GEN2(dev)) {
7944                 dev->mode_config.max_width = 2048;
7945                 dev->mode_config.max_height = 2048;
7946         } else if (IS_GEN3(dev)) {
7947                 dev->mode_config.max_width = 4096;
7948                 dev->mode_config.max_height = 4096;
7949         } else {
7950                 dev->mode_config.max_width = 8192;
7951                 dev->mode_config.max_height = 8192;
7952         }
7953         dev->mode_config.fb_base = dev->agp->base;
7954
7955         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7956                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7957
7958         for (i = 0; i < dev_priv->num_pipe; i++) {
7959                 intel_crtc_init(dev, i);
7960         }
7961
7962         /* Just disable it once at startup */
7963         i915_disable_vga(dev);
7964         intel_setup_outputs(dev);
7965
7966         intel_init_clock_gating(dev);
7967
7968         if (IS_IRONLAKE_M(dev)) {
7969                 ironlake_enable_drps(dev);
7970                 intel_init_emon(dev);
7971         }
7972
7973         if (IS_GEN6(dev) || IS_GEN7(dev)) {
7974                 gen6_enable_rps(dev_priv);
7975                 gen6_update_ring_freq(dev_priv);
7976         }
7977
7978         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7979         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7980                     (unsigned long)dev);
7981 }
7982
7983 void intel_modeset_gem_init(struct drm_device *dev)
7984 {
7985         if (IS_IRONLAKE_M(dev))
7986                 ironlake_enable_rc6(dev);
7987
7988         intel_setup_overlay(dev);
7989 }
7990
7991 void intel_modeset_cleanup(struct drm_device *dev)
7992 {
7993         struct drm_i915_private *dev_priv = dev->dev_private;
7994         struct drm_crtc *crtc;
7995         struct intel_crtc *intel_crtc;
7996
7997         drm_kms_helper_poll_fini(dev);
7998         mutex_lock(&dev->struct_mutex);
7999
8000         intel_unregister_dsm_handler();
8001
8002
8003         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8004                 /* Skip inactive CRTCs */
8005                 if (!crtc->fb)
8006                         continue;
8007
8008                 intel_crtc = to_intel_crtc(crtc);
8009                 intel_increase_pllclock(crtc);
8010         }
8011
8012         if (dev_priv->display.disable_fbc)
8013                 dev_priv->display.disable_fbc(dev);
8014
8015         if (IS_IRONLAKE_M(dev))
8016                 ironlake_disable_drps(dev);
8017         if (IS_GEN6(dev) || IS_GEN7(dev))
8018                 gen6_disable_rps(dev);
8019
8020         if (IS_IRONLAKE_M(dev))
8021                 ironlake_disable_rc6(dev);
8022
8023         mutex_unlock(&dev->struct_mutex);
8024
8025         /* Disable the irq before mode object teardown, for the irq might
8026          * enqueue unpin/hotplug work. */
8027         drm_irq_uninstall(dev);
8028         cancel_work_sync(&dev_priv->hotplug_work);
8029
8030         /* Shut off idle work before the crtcs get freed. */
8031         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8032                 intel_crtc = to_intel_crtc(crtc);
8033                 del_timer_sync(&intel_crtc->idle_timer);
8034         }
8035         del_timer_sync(&dev_priv->idle_timer);
8036         cancel_work_sync(&dev_priv->idle_work);
8037
8038         drm_mode_config_cleanup(dev);
8039 }
8040
8041 /*
8042  * Return which encoder is currently attached for connector.
8043  */
8044 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8045 {
8046         return &intel_attached_encoder(connector)->base;
8047 }
8048
8049 void intel_connector_attach_encoder(struct intel_connector *connector,
8050                                     struct intel_encoder *encoder)
8051 {
8052         connector->encoder = encoder;
8053         drm_mode_connector_attach_encoder(&connector->base,
8054                                           &encoder->base);
8055 }
8056
8057 /*
8058  * set vga decode state - true == enable VGA decode
8059  */
8060 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8061 {
8062         struct drm_i915_private *dev_priv = dev->dev_private;
8063         u16 gmch_ctrl;
8064
8065         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8066         if (state)
8067                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8068         else
8069                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8070         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8071         return 0;
8072 }
8073
8074 #ifdef CONFIG_DEBUG_FS
8075 #include <linux/seq_file.h>
8076
8077 struct intel_display_error_state {
8078         struct intel_cursor_error_state {
8079                 u32 control;
8080                 u32 position;
8081                 u32 base;
8082                 u32 size;
8083         } cursor[2];
8084
8085         struct intel_pipe_error_state {
8086                 u32 conf;
8087                 u32 source;
8088
8089                 u32 htotal;
8090                 u32 hblank;
8091                 u32 hsync;
8092                 u32 vtotal;
8093                 u32 vblank;
8094                 u32 vsync;
8095         } pipe[2];
8096
8097         struct intel_plane_error_state {
8098                 u32 control;
8099                 u32 stride;
8100                 u32 size;
8101                 u32 pos;
8102                 u32 addr;
8103                 u32 surface;
8104                 u32 tile_offset;
8105         } plane[2];
8106 };
8107
8108 struct intel_display_error_state *
8109 intel_display_capture_error_state(struct drm_device *dev)
8110 {
8111         drm_i915_private_t *dev_priv = dev->dev_private;
8112         struct intel_display_error_state *error;
8113         int i;
8114
8115         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8116         if (error == NULL)
8117                 return NULL;
8118
8119         for (i = 0; i < 2; i++) {
8120                 error->cursor[i].control = I915_READ(CURCNTR(i));
8121                 error->cursor[i].position = I915_READ(CURPOS(i));
8122                 error->cursor[i].base = I915_READ(CURBASE(i));
8123
8124                 error->plane[i].control = I915_READ(DSPCNTR(i));
8125                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8126                 error->plane[i].size = I915_READ(DSPSIZE(i));
8127                 error->plane[i].pos= I915_READ(DSPPOS(i));
8128                 error->plane[i].addr = I915_READ(DSPADDR(i));
8129                 if (INTEL_INFO(dev)->gen >= 4) {
8130                         error->plane[i].surface = I915_READ(DSPSURF(i));
8131                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8132                 }
8133
8134                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8135                 error->pipe[i].source = I915_READ(PIPESRC(i));
8136                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8137                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8138                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8139                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8140                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8141                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8142         }
8143
8144         return error;
8145 }
8146
8147 void
8148 intel_display_print_error_state(struct seq_file *m,
8149                                 struct drm_device *dev,
8150                                 struct intel_display_error_state *error)
8151 {
8152         int i;
8153
8154         for (i = 0; i < 2; i++) {
8155                 seq_printf(m, "Pipe [%d]:\n", i);
8156                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8157                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8158                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8159                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8160                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8161                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8162                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8163                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8164
8165                 seq_printf(m, "Plane [%d]:\n", i);
8166                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8167                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8168                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8169                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8170                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8171                 if (INTEL_INFO(dev)->gen >= 4) {
8172                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8173                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8174                 }
8175
8176                 seq_printf(m, "Cursor [%d]:\n", i);
8177                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8178                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8179                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8180         }
8181 }
8182 #endif