2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
78 static const uint32_t intel_cursor_formats[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void chv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 int p2_slow, p2_fast;
122 typedef struct intel_limit intel_limit_t;
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_pch_rawclk(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
133 WARN_ON(!HAS_PCH_SPLIT(dev));
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
369 static const intel_limit_t intel_limits_vlv = {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv = {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
404 .vco = { .min = 4800000, .max = 6700000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
414 needs_modeset(struct drm_crtc_state *state)
416 return drm_atomic_crtc_needs_modeset(state);
420 * Returns whether any output on the specified pipe is of the specified type
422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
424 struct drm_device *dev = crtc->base.dev;
425 struct intel_encoder *encoder;
427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
428 if (encoder->type == type)
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
443 struct drm_atomic_state *state = crtc_state->base.state;
444 struct drm_connector *connector;
445 struct drm_connector_state *connector_state;
446 struct intel_encoder *encoder;
447 int i, num_connectors = 0;
449 for_each_connector_in_state(state, connector, connector_state, i) {
450 if (connector_state->crtc != crtc_state->base.crtc)
455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
460 WARN_ON(num_connectors == 0);
465 static const intel_limit_t *
466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
468 struct drm_device *dev = crtc_state->base.crtc->dev;
469 const intel_limit_t *limit;
471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
472 if (intel_is_dual_link_lvds(dev)) {
473 if (refclk == 100000)
474 limit = &intel_limits_ironlake_dual_lvds_100m;
476 limit = &intel_limits_ironlake_dual_lvds;
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_single_lvds_100m;
481 limit = &intel_limits_ironlake_single_lvds;
484 limit = &intel_limits_ironlake_dac;
489 static const intel_limit_t *
490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
492 struct drm_device *dev = crtc_state->base.crtc->dev;
493 const intel_limit_t *limit;
495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
496 if (intel_is_dual_link_lvds(dev))
497 limit = &intel_limits_g4x_dual_channel_lvds;
499 limit = &intel_limits_g4x_single_channel_lvds;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 limit = &intel_limits_g4x_hdmi;
503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
504 limit = &intel_limits_g4x_sdvo;
505 } else /* The option is for other outputs */
506 limit = &intel_limits_i9xx_sdvo;
511 static const intel_limit_t *
512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
514 struct drm_device *dev = crtc_state->base.crtc->dev;
515 const intel_limit_t *limit;
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
520 limit = intel_ironlake_limit(crtc_state, refclk);
521 else if (IS_G4X(dev)) {
522 limit = intel_g4x_limit(crtc_state);
523 } else if (IS_PINEVIEW(dev)) {
524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
525 limit = &intel_limits_pineview_lvds;
527 limit = &intel_limits_pineview_sdvo;
528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
530 } else if (IS_VALLEYVIEW(dev)) {
531 limit = &intel_limits_vlv;
532 } else if (!IS_GEN2(dev)) {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i9xx_lvds;
536 limit = &intel_limits_i9xx_sdvo;
538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
539 limit = &intel_limits_i8xx_lvds;
540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
541 limit = &intel_limits_i8xx_dvo;
543 limit = &intel_limits_i8xx_dac;
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
561 if (WARN_ON(clock->n == 0 || clock->p == 0))
563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
576 clock->m = i9xx_dpll_compute_m(clock);
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
595 return clock->dot / 5;
598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
608 return clock->dot / 5;
611 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
617 static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
624 INTELPllInvalid("p1 out of range\n");
625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
626 INTELPllInvalid("m2 out of range\n");
627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
628 INTELPllInvalid("m1 out of range\n");
630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
642 INTELPllInvalid("vco out of range\n");
643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
647 INTELPllInvalid("dot out of range\n");
653 i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
657 struct drm_device *dev = crtc_state->base.crtc->dev;
659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
665 if (intel_is_dual_link_lvds(dev))
666 return limit->p2.p2_fast;
668 return limit->p2.p2_slow;
670 if (target < limit->p2.dot_limit)
671 return limit->p2.p2_slow;
673 return limit->p2.p2_fast;
678 i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
683 struct drm_device *dev = crtc_state->base.crtc->dev;
687 memset(best_clock, 0, sizeof(*best_clock));
689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 if (clock.m2 >= clock.m1)
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
703 i9xx_calc_dpll_params(refclk, &clock);
704 if (!intel_PLL_is_valid(dev, limit,
708 clock.p != match_clock->p)
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
721 return (err != target);
725 pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
730 struct drm_device *dev = crtc_state->base.crtc->dev;
734 memset(best_clock, 0, sizeof(*best_clock));
736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
748 pnv_calc_dpll_params(refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
753 clock.p != match_clock->p)
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
766 return (err != target);
770 g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
775 struct drm_device *dev = crtc_state->base.crtc->dev;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
782 memset(best_clock, 0, sizeof(*best_clock));
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
786 max_n = limit->n.max;
787 /* based on hardware requirement, prefer smaller n to precision */
788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 /* based on hardware requirement, prefere larger m1,m2 */
790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
798 i9xx_calc_dpll_params(refclk, &clock);
799 if (!intel_PLL_is_valid(dev, limit,
803 this_err = abs(clock.dot - target);
804 if (this_err < err_most) {
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
831 if (IS_CHERRYVIEW(dev)) {
834 return calculated_clock->p > best_clock->p;
837 if (WARN_ON_ONCE(!target_freq))
840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
854 return *error_ppm + 10 < best_error_ppm;
858 vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
864 struct drm_device *dev = crtc->base.dev;
866 unsigned int bestppm = 1000000;
867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
871 target *= 5; /* fast clock */
873 memset(best_clock, 0, sizeof(*best_clock));
875 /* based on hardware requirement, prefer smaller n to precision */
876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
880 clock.p = clock.p1 * clock.p2;
881 /* based on hardware requirement, prefer bigger m1,m2 values */
882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
888 vlv_calc_dpll_params(refclk, &clock);
890 if (!intel_PLL_is_valid(dev, limit,
894 if (!vlv_PLL_is_optimal(dev, target,
912 chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
918 struct drm_device *dev = crtc->base.dev;
919 unsigned int best_error_ppm;
924 memset(best_clock, 0, sizeof(*best_clock));
925 best_error_ppm = 1000000;
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 unsigned int error_ppm;
941 clock.p = clock.p1 * clock.p2;
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
946 if (m2 > INT_MAX/clock.m1)
951 chv_calc_dpll_params(refclk, &clock);
953 if (!intel_PLL_is_valid(dev, limit, &clock))
956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
961 best_error_ppm = error_ppm;
969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
972 int refclk = i9xx_get_refclk(crtc_state, 0);
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
978 bool intel_crtc_active(struct drm_crtc *crtc)
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
985 * We can ditch the adjusted_mode.crtc_clock check as soon
986 * as Haswell has gained clock readout/fastboot support.
988 * We can ditch the crtc->primary->fb check as soon as we can
989 * properly reconstruct framebuffers.
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
995 return intel_crtc->active && crtc->primary->state->fb &&
996 intel_crtc->config->base.adjusted_mode.crtc_clock;
999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1005 return intel_crtc->config->cpu_transcoder;
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 line1 = I915_READ(reg) & line_mask;
1022 line2 = I915_READ(reg) & line_mask;
1024 return line1 == line2;
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
1029 * @crtc: crtc whose pipe to wait for
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1045 struct drm_device *dev = crtc->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048 enum pipe pipe = crtc->pipe;
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 int reg = PIPECONF(cpu_transcoder);
1053 /* Wait for the Pipe State to go off */
1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1056 WARN(1, "pipe_off wait timed out\n");
1058 /* Wait for the display line to settle */
1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060 WARN(1, "pipe_off wait timed out\n");
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1069 * Returns true if @port is connected, false otherwise.
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1076 if (HAS_PCH_IBX(dev_priv->dev)) {
1077 switch (port->port) {
1079 bit = SDE_PORTB_HOTPLUG;
1082 bit = SDE_PORTC_HOTPLUG;
1085 bit = SDE_PORTD_HOTPLUG;
1091 switch (port->port) {
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1102 bit = SDE_PORTE_HOTPLUG_SPT;
1109 return I915_READ(SDEISR) & bit;
1112 static const char *state_string(bool enabled)
1114 return enabled ? "on" : "off";
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
1128 I915_STATE_WARN(cur_state != state,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139 mutex_lock(&dev_priv->sb_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->sb_lock);
1143 cur_state = val & DSI_PLL_VCO_EN;
1144 I915_STATE_WARN(cur_state != state,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1156 if (crtc->config->shared_dpll < 0)
1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1168 struct intel_dpll_hw_state hw_state;
1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175 I915_STATE_WARN(cur_state != state,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
1216 I915_STATE_WARN(cur_state != state,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv->dev))
1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252 I915_STATE_WARN(cur_state != state,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1260 struct drm_device *dev = dev_priv->dev;
1263 enum pipe panel_pipe = PIPE_A;
1266 if (WARN_ON(HAS_DDI(dev)))
1269 if (HAS_PCH_SPLIT(dev)) {
1272 pp_reg = PCH_PP_CONTROL;
1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1284 pp_reg = PP_CONTROL;
1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1294 I915_STATE_WARN(panel_pipe == pipe && locked,
1295 "panel assertion failure, pipe %c regs locked\n",
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1302 struct drm_device *dev = dev_priv->dev;
1305 if (IS_845G(dev) || IS_I865G(dev))
1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1310 I915_STATE_WARN(cur_state != state,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1331 if (!intel_display_power_is_enabled(dev_priv,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1340 I915_STATE_WARN(cur_state != state,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355 I915_STATE_WARN(cur_state != state,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1366 struct drm_device *dev = dev_priv->dev;
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376 "plane %c assertion failure, should be disabled but not\n",
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv, i) {
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1396 struct drm_device *dev = dev_priv->dev;
1400 if (INTEL_INFO(dev)->gen >= 9) {
1401 for_each_sprite(dev_priv, pipe, sprite) {
1402 val = I915_READ(PLANE_CTL(pipe, sprite));
1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1407 } else if (IS_VALLEYVIEW(dev)) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 reg = SPCNTR(pipe, sprite);
1410 val = I915_READ(reg);
1411 I915_STATE_WARN(val & SP_ENABLE,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe, sprite), pipe_name(pipe));
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
1424 I915_STATE_WARN(val & DVS_ENABLE,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433 drm_crtc_vblank_put(crtc);
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1456 reg = PCH_TRANSCONF(pipe);
1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
1459 I915_STATE_WARN(enabled,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
1467 if ((val & DP_PORT_EN) == 0)
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1488 if ((val & SDVO_ENABLE) == 0)
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1507 if ((val & LVDS_PORT_EN) == 0)
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, int reg, u32 port_sel)
1538 u32 val = I915_READ(reg);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg, pipe_name(pipe));
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544 && (val & DP_PIPEB_SELECT),
1545 "IBX PCH dp port still using transcoder B\n");
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1551 u32 val = I915_READ(reg);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg, pipe_name(pipe));
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557 && (val & SDVO_PIPE_B_SELECT),
1558 "IBX PCH hdmi port still using transcoder B\n");
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1572 val = I915_READ(reg);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1578 val = I915_READ(reg);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1588 static void intel_init_dpio(struct drm_device *dev)
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1592 if (!IS_VALLEYVIEW(dev))
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609 const struct intel_crtc_state *pipe_config)
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv->dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1625 I915_WRITE(reg, dpll);
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(crtc->pipe));
1635 /* We do this three times for luck */
1636 I915_WRITE(reg, dpll);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg, dpll);
1644 udelay(150); /* wait for warmup */
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648 const struct intel_crtc_state *pipe_config)
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1660 mutex_lock(&dev_priv->sb_lock);
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1667 mutex_unlock(&dev_priv->sb_lock);
1670 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1677 /* Check PLL is locked */
1678 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1679 DRM_ERROR("PLL %d failed to lock\n", pipe);
1681 /* not sure when this should be written */
1682 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1683 POSTING_READ(DPLL_MD(pipe));
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1688 struct intel_crtc *crtc;
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->base.state->active &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
1705 assert_pipe_disabled(dev_priv, crtc->pipe);
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1727 /* Wait for the clocks to stabilize. */
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
1733 crtc->config->dpll_hw_state.dpll_md);
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1738 * So write it again.
1740 I915_WRITE(reg, dpll);
1743 /* We do this three times for luck */
1744 I915_WRITE(reg, dpll);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1749 udelay(150); /* wait for warmup */
1750 I915_WRITE(reg, dpll);
1752 udelay(150); /* wait for warmup */
1756 * i9xx_disable_pll - disable a PLL
1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1762 * Note! This is for pre-ILK only.
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773 !intel_num_dvo_pipes(dev)) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1788 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1789 POSTING_READ(DPLL(pipe));
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1803 val = DPLL_VGA_MODE_DIS;
1805 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1806 I915_WRITE(DPLL(pipe), val);
1807 POSTING_READ(DPLL(pipe));
1811 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1813 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1816 /* Make sure the pipe isn't still relying on us */
1817 assert_pipe_disabled(dev_priv, pipe);
1819 /* Set PLL en = 0 */
1820 val = DPLL_SSC_REF_CLK_CHV |
1821 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1823 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824 I915_WRITE(DPLL(pipe), val);
1825 POSTING_READ(DPLL(pipe));
1827 mutex_lock(&dev_priv->sb_lock);
1829 /* Disable 10bit clock to display controller */
1830 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831 val &= ~DPIO_DCLKP_EN;
1832 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1834 /* disable left/right clock distribution */
1835 if (pipe != PIPE_B) {
1836 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1837 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1838 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1840 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1841 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1842 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 mutex_unlock(&dev_priv->sb_lock);
1848 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1849 struct intel_digital_port *dport,
1850 unsigned int expected_mask)
1855 switch (dport->port) {
1857 port_mask = DPLL_PORTB_READY_MASK;
1861 port_mask = DPLL_PORTC_READY_MASK;
1863 expected_mask <<= 4;
1866 port_mask = DPLL_PORTD_READY_MASK;
1867 dpll_reg = DPIO_PHY_STATUS;
1873 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1874 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1875 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1878 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1884 if (WARN_ON(pll == NULL))
1887 WARN_ON(!pll->config.crtc_mask);
1888 if (pll->active == 0) {
1889 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1891 assert_shared_dpll_disabled(dev_priv, pll);
1893 pll->mode_set(dev_priv, pll);
1898 * intel_enable_shared_dpll - enable PCH PLL
1899 * @dev_priv: i915 private structure
1900 * @pipe: pipe PLL to enable
1902 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1903 * drives the transcoder clock.
1905 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1907 struct drm_device *dev = crtc->base.dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
1909 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1911 if (WARN_ON(pll == NULL))
1914 if (WARN_ON(pll->config.crtc_mask == 0))
1917 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1918 pll->name, pll->active, pll->on,
1919 crtc->base.base.id);
1921 if (pll->active++) {
1923 assert_shared_dpll_enabled(dev_priv, pll);
1928 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1930 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1931 pll->enable(dev_priv, pll);
1935 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1937 struct drm_device *dev = crtc->base.dev;
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1941 /* PCH only available on ILK+ */
1942 if (INTEL_INFO(dev)->gen < 5)
1948 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
1953 crtc->base.base.id);
1955 if (WARN_ON(pll->active == 0)) {
1956 assert_shared_dpll_disabled(dev_priv, pll);
1960 assert_shared_dpll_enabled(dev_priv, pll);
1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966 pll->disable(dev_priv, pll);
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1975 struct drm_device *dev = dev_priv->dev;
1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 uint32_t reg, val, pipeconf_val;
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev));
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv,
1985 intel_crtc_to_shared_dpll(intel_crtc));
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
2000 reg = PCH_TRANSCONF(pipe);
2001 val = I915_READ(reg);
2002 pipeconf_val = I915_READ(PIPECONF(pipe));
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2006 * Make the BPC in transcoder be consistent with
2007 * that in pipeconf reg. For HDMI we must use 8bpc
2008 * here for both 8bpc and 12bpc.
2010 val &= ~PIPECONF_BPC_MASK;
2011 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2012 val |= PIPECONF_8BPC;
2014 val |= pipeconf_val & PIPECONF_BPC_MASK;
2017 val &= ~TRANS_INTERLACE_MASK;
2018 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2019 if (HAS_PCH_IBX(dev_priv->dev) &&
2020 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2021 val |= TRANS_LEGACY_INTERLACED_ILK;
2023 val |= TRANS_INTERLACED;
2025 val |= TRANS_PROGRESSIVE;
2027 I915_WRITE(reg, val | TRANS_ENABLE);
2028 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2029 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2032 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2033 enum transcoder cpu_transcoder)
2035 u32 val, pipeconf_val;
2037 /* PCH only available on ILK+ */
2038 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2040 /* FDI must be feeding us bits for PCH ports */
2041 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2042 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2044 /* Workaround: set timing override bit. */
2045 val = I915_READ(_TRANSA_CHICKEN2);
2046 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2047 I915_WRITE(_TRANSA_CHICKEN2, val);
2050 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2052 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2053 PIPECONF_INTERLACED_ILK)
2054 val |= TRANS_INTERLACED;
2056 val |= TRANS_PROGRESSIVE;
2058 I915_WRITE(LPT_TRANSCONF, val);
2059 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2060 DRM_ERROR("Failed to enable PCH transcoder\n");
2063 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2066 struct drm_device *dev = dev_priv->dev;
2069 /* FDI relies on the transcoder */
2070 assert_fdi_tx_disabled(dev_priv, pipe);
2071 assert_fdi_rx_disabled(dev_priv, pipe);
2073 /* Ports must be off as well */
2074 assert_pch_ports_disabled(dev_priv, pipe);
2076 reg = PCH_TRANSCONF(pipe);
2077 val = I915_READ(reg);
2078 val &= ~TRANS_ENABLE;
2079 I915_WRITE(reg, val);
2080 /* wait for PCH transcoder off, transcoder state */
2081 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2082 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2084 if (!HAS_PCH_IBX(dev)) {
2085 /* Workaround: Clear the timing override chicken bit again. */
2086 reg = TRANS_CHICKEN2(pipe);
2087 val = I915_READ(reg);
2088 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2089 I915_WRITE(reg, val);
2093 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2097 val = I915_READ(LPT_TRANSCONF);
2098 val &= ~TRANS_ENABLE;
2099 I915_WRITE(LPT_TRANSCONF, val);
2100 /* wait for PCH transcoder off, transcoder state */
2101 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2102 DRM_ERROR("Failed to disable PCH transcoder\n");
2104 /* Workaround: clear timing override bit. */
2105 val = I915_READ(_TRANSA_CHICKEN2);
2106 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2107 I915_WRITE(_TRANSA_CHICKEN2, val);
2111 * intel_enable_pipe - enable a pipe, asserting requirements
2112 * @crtc: crtc responsible for the pipe
2114 * Enable @crtc's pipe, making sure that various hardware specific requirements
2115 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2117 static void intel_enable_pipe(struct intel_crtc *crtc)
2119 struct drm_device *dev = crtc->base.dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 enum pipe pipe = crtc->pipe;
2122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2124 enum pipe pch_transcoder;
2128 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2130 assert_planes_disabled(dev_priv, pipe);
2131 assert_cursor_disabled(dev_priv, pipe);
2132 assert_sprites_disabled(dev_priv, pipe);
2134 if (HAS_PCH_LPT(dev_priv->dev))
2135 pch_transcoder = TRANSCODER_A;
2137 pch_transcoder = pipe;
2140 * A pipe without a PLL won't actually be able to drive bits from
2141 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2144 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2145 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2146 assert_dsi_pll_enabled(dev_priv);
2148 assert_pll_enabled(dev_priv, pipe);
2150 if (crtc->config->has_pch_encoder) {
2151 /* if driving the PCH, we need FDI enabled */
2152 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2153 assert_fdi_tx_pll_enabled(dev_priv,
2154 (enum pipe) cpu_transcoder);
2156 /* FIXME: assert CPU port conditions for SNB+ */
2159 reg = PIPECONF(cpu_transcoder);
2160 val = I915_READ(reg);
2161 if (val & PIPECONF_ENABLE) {
2162 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2163 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2167 I915_WRITE(reg, val | PIPECONF_ENABLE);
2172 * intel_disable_pipe - disable a pipe, asserting requirements
2173 * @crtc: crtc whose pipes is to be disabled
2175 * Disable the pipe of @crtc, making sure that various hardware
2176 * specific requirements are met, if applicable, e.g. plane
2177 * disabled, panel fitter off, etc.
2179 * Will wait until the pipe has shut down before returning.
2181 static void intel_disable_pipe(struct intel_crtc *crtc)
2183 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2184 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2185 enum pipe pipe = crtc->pipe;
2189 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2192 * Make sure planes won't keep trying to pump pixels to us,
2193 * or we might hang the display.
2195 assert_planes_disabled(dev_priv, pipe);
2196 assert_cursor_disabled(dev_priv, pipe);
2197 assert_sprites_disabled(dev_priv, pipe);
2199 reg = PIPECONF(cpu_transcoder);
2200 val = I915_READ(reg);
2201 if ((val & PIPECONF_ENABLE) == 0)
2205 * Double wide has implications for planes
2206 * so best keep it disabled when not needed.
2208 if (crtc->config->double_wide)
2209 val &= ~PIPECONF_DOUBLE_WIDE;
2211 /* Don't disable pipe or pipe PLLs if needed */
2212 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2213 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2214 val &= ~PIPECONF_ENABLE;
2216 I915_WRITE(reg, val);
2217 if ((val & PIPECONF_ENABLE) == 0)
2218 intel_wait_for_pipe_off(crtc);
2221 static bool need_vtd_wa(struct drm_device *dev)
2223 #ifdef CONFIG_INTEL_IOMMU
2224 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2232 uint64_t fb_format_modifier)
2234 unsigned int tile_height;
2235 uint32_t pixel_bytes;
2237 switch (fb_format_modifier) {
2238 case DRM_FORMAT_MOD_NONE:
2241 case I915_FORMAT_MOD_X_TILED:
2242 tile_height = IS_GEN2(dev) ? 16 : 8;
2244 case I915_FORMAT_MOD_Y_TILED:
2247 case I915_FORMAT_MOD_Yf_TILED:
2248 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2249 switch (pixel_bytes) {
2263 "128-bit pixels are not supported for display!");
2269 MISSING_CASE(fb_format_modifier);
2278 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2279 uint32_t pixel_format, uint64_t fb_format_modifier)
2281 return ALIGN(height, intel_tile_height(dev, pixel_format,
2282 fb_format_modifier));
2286 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2287 const struct drm_plane_state *plane_state)
2289 struct intel_rotation_info *info = &view->rotation_info;
2290 unsigned int tile_height, tile_pitch;
2292 *view = i915_ggtt_view_normal;
2297 if (!intel_rotation_90_or_270(plane_state->rotation))
2300 *view = i915_ggtt_view_rotated;
2302 info->height = fb->height;
2303 info->pixel_format = fb->pixel_format;
2304 info->pitch = fb->pitches[0];
2305 info->fb_modifier = fb->modifier[0];
2307 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2309 tile_pitch = PAGE_SIZE / tile_height;
2310 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2311 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2312 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2317 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2319 if (INTEL_INFO(dev_priv)->gen >= 9)
2321 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322 IS_VALLEYVIEW(dev_priv))
2324 else if (INTEL_INFO(dev_priv)->gen >= 4)
2331 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332 struct drm_framebuffer *fb,
2333 const struct drm_plane_state *plane_state,
2334 struct intel_engine_cs *pipelined,
2335 struct drm_i915_gem_request **pipelined_request)
2337 struct drm_device *dev = fb->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2340 struct i915_ggtt_view view;
2344 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2346 switch (fb->modifier[0]) {
2347 case DRM_FORMAT_MOD_NONE:
2348 alignment = intel_linear_alignment(dev_priv);
2350 case I915_FORMAT_MOD_X_TILED:
2351 if (INTEL_INFO(dev)->gen >= 9)
2352 alignment = 256 * 1024;
2354 /* pin() will align the object as required by fence */
2358 case I915_FORMAT_MOD_Y_TILED:
2359 case I915_FORMAT_MOD_Yf_TILED:
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361 "Y tiling bo slipped through, driver bug!\n"))
2363 alignment = 1 * 1024 * 1024;
2366 MISSING_CASE(fb->modifier[0]);
2370 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2374 /* Note that the w/a also requires 64 PTE of padding following the
2375 * bo. We currently fill all unused PTE with the shadow page and so
2376 * we should always have valid PTE following the scanout preventing
2379 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380 alignment = 256 * 1024;
2383 * Global gtt pte registers are special registers which actually forward
2384 * writes to a chunk of system memory. Which means that there is no risk
2385 * that the register values disappear as soon as we call
2386 * intel_runtime_pm_put(), so it is correct to wrap only the
2387 * pin/unpin/fence and not more.
2389 intel_runtime_pm_get(dev_priv);
2391 dev_priv->mm.interruptible = false;
2392 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2393 pipelined_request, &view);
2395 goto err_interruptible;
2397 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398 * fence, whereas 965+ only requires a fence if using
2399 * framebuffer compression. For simplicity, we always install
2400 * a fence as the cost is not that onerous.
2402 ret = i915_gem_object_get_fence(obj);
2403 if (ret == -EDEADLK) {
2405 * -EDEADLK means there are no free fences
2408 * This is propagated to atomic, but it uses
2409 * -EDEADLK to force a locking recovery, so
2410 * change the returned error to -EBUSY.
2417 i915_gem_object_pin_fence(obj);
2419 dev_priv->mm.interruptible = true;
2420 intel_runtime_pm_put(dev_priv);
2424 i915_gem_object_unpin_from_display_plane(obj, &view);
2426 dev_priv->mm.interruptible = true;
2427 intel_runtime_pm_put(dev_priv);
2431 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2432 const struct drm_plane_state *plane_state)
2434 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2435 struct i915_ggtt_view view;
2438 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2441 WARN_ONCE(ret, "Couldn't get view from plane state!");
2443 i915_gem_object_unpin_fence(obj);
2444 i915_gem_object_unpin_from_display_plane(obj, &view);
2447 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2448 * is assumed to be a power-of-two. */
2449 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2451 unsigned int tiling_mode,
2455 if (tiling_mode != I915_TILING_NONE) {
2456 unsigned int tile_rows, tiles;
2461 tiles = *x / (512/cpp);
2464 return tile_rows * pitch * 8 + tiles * 4096;
2466 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2467 unsigned int offset;
2469 offset = *y * pitch + *x * cpp;
2470 *y = (offset & alignment) / pitch;
2471 *x = ((offset & alignment) - *y * pitch) / cpp;
2472 return offset & ~alignment;
2476 static int i9xx_format_to_fourcc(int format)
2479 case DISPPLANE_8BPP:
2480 return DRM_FORMAT_C8;
2481 case DISPPLANE_BGRX555:
2482 return DRM_FORMAT_XRGB1555;
2483 case DISPPLANE_BGRX565:
2484 return DRM_FORMAT_RGB565;
2486 case DISPPLANE_BGRX888:
2487 return DRM_FORMAT_XRGB8888;
2488 case DISPPLANE_RGBX888:
2489 return DRM_FORMAT_XBGR8888;
2490 case DISPPLANE_BGRX101010:
2491 return DRM_FORMAT_XRGB2101010;
2492 case DISPPLANE_RGBX101010:
2493 return DRM_FORMAT_XBGR2101010;
2497 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2500 case PLANE_CTL_FORMAT_RGB_565:
2501 return DRM_FORMAT_RGB565;
2503 case PLANE_CTL_FORMAT_XRGB_8888:
2506 return DRM_FORMAT_ABGR8888;
2508 return DRM_FORMAT_XBGR8888;
2511 return DRM_FORMAT_ARGB8888;
2513 return DRM_FORMAT_XRGB8888;
2515 case PLANE_CTL_FORMAT_XRGB_2101010:
2517 return DRM_FORMAT_XBGR2101010;
2519 return DRM_FORMAT_XRGB2101010;
2524 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525 struct intel_initial_plane_config *plane_config)
2527 struct drm_device *dev = crtc->base.dev;
2528 struct drm_i915_gem_object *obj = NULL;
2529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2530 struct drm_framebuffer *fb = &plane_config->fb->base;
2531 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2535 size_aligned -= base_aligned;
2537 if (plane_config->size == 0)
2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
2549 obj->stride = fb->pitches[0];
2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2558 mutex_lock(&dev->struct_mutex);
2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2561 DRM_DEBUG_KMS("intel fb init failed\n");
2564 mutex_unlock(&dev->struct_mutex);
2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2577 update_state_fb(struct drm_plane *plane)
2579 if (plane->fb == plane->state->fb)
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
2593 struct drm_device *dev = intel_crtc->base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct intel_crtc *i;
2597 struct drm_i915_gem_object *obj;
2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_plane_state *plane_state = primary->state;
2600 struct drm_framebuffer *fb;
2602 if (!plane_config->fb)
2605 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2606 fb = &plane_config->fb->base;
2610 kfree(plane_config->fb);
2613 * Failed to alloc the obj, check to see if we should share
2614 * an fb with another CRTC instead
2616 for_each_crtc(dev, c) {
2617 i = to_intel_crtc(c);
2619 if (c == &intel_crtc->base)
2625 fb = c->primary->fb;
2629 obj = intel_fb_obj(fb);
2630 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2631 drm_framebuffer_reference(fb);
2639 plane_state->src_x = plane_state->src_y = 0;
2640 plane_state->src_w = fb->width << 16;
2641 plane_state->src_h = fb->height << 16;
2643 plane_state->crtc_x = plane_state->src_y = 0;
2644 plane_state->crtc_w = fb->width;
2645 plane_state->crtc_h = fb->height;
2647 obj = intel_fb_obj(fb);
2648 if (obj->tiling_mode != I915_TILING_NONE)
2649 dev_priv->preserve_bios_swizzle = true;
2651 drm_framebuffer_reference(fb);
2652 primary->fb = primary->state->fb = fb;
2653 primary->crtc = primary->state->crtc = &intel_crtc->base;
2654 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2655 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2659 struct drm_framebuffer *fb,
2662 struct drm_device *dev = crtc->dev;
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2665 struct drm_plane *primary = crtc->primary;
2666 bool visible = to_intel_plane_state(primary->state)->visible;
2667 struct drm_i915_gem_object *obj;
2668 int plane = intel_crtc->plane;
2669 unsigned long linear_offset;
2671 u32 reg = DSPCNTR(plane);
2674 if (!visible || !fb) {
2676 if (INTEL_INFO(dev)->gen >= 4)
2677 I915_WRITE(DSPSURF(plane), 0);
2679 I915_WRITE(DSPADDR(plane), 0);
2684 obj = intel_fb_obj(fb);
2685 if (WARN_ON(obj == NULL))
2688 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2690 dspcntr = DISPPLANE_GAMMA_ENABLE;
2692 dspcntr |= DISPLAY_PLANE_ENABLE;
2694 if (INTEL_INFO(dev)->gen < 4) {
2695 if (intel_crtc->pipe == PIPE_B)
2696 dspcntr |= DISPPLANE_SEL_PIPE_B;
2698 /* pipesrc and dspsize control the size that is scaled from,
2699 * which should always be the user's requested size.
2701 I915_WRITE(DSPSIZE(plane),
2702 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2703 (intel_crtc->config->pipe_src_w - 1));
2704 I915_WRITE(DSPPOS(plane), 0);
2705 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2706 I915_WRITE(PRIMSIZE(plane),
2707 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2708 (intel_crtc->config->pipe_src_w - 1));
2709 I915_WRITE(PRIMPOS(plane), 0);
2710 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2713 switch (fb->pixel_format) {
2715 dspcntr |= DISPPLANE_8BPP;
2717 case DRM_FORMAT_XRGB1555:
2718 dspcntr |= DISPPLANE_BGRX555;
2720 case DRM_FORMAT_RGB565:
2721 dspcntr |= DISPPLANE_BGRX565;
2723 case DRM_FORMAT_XRGB8888:
2724 dspcntr |= DISPPLANE_BGRX888;
2726 case DRM_FORMAT_XBGR8888:
2727 dspcntr |= DISPPLANE_RGBX888;
2729 case DRM_FORMAT_XRGB2101010:
2730 dspcntr |= DISPPLANE_BGRX101010;
2732 case DRM_FORMAT_XBGR2101010:
2733 dspcntr |= DISPPLANE_RGBX101010;
2739 if (INTEL_INFO(dev)->gen >= 4 &&
2740 obj->tiling_mode != I915_TILING_NONE)
2741 dspcntr |= DISPPLANE_TILED;
2744 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2746 linear_offset = y * fb->pitches[0] + x * pixel_size;
2748 if (INTEL_INFO(dev)->gen >= 4) {
2749 intel_crtc->dspaddr_offset =
2750 intel_gen4_compute_page_offset(dev_priv,
2751 &x, &y, obj->tiling_mode,
2754 linear_offset -= intel_crtc->dspaddr_offset;
2756 intel_crtc->dspaddr_offset = linear_offset;
2759 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2760 dspcntr |= DISPPLANE_ROTATE_180;
2762 x += (intel_crtc->config->pipe_src_w - 1);
2763 y += (intel_crtc->config->pipe_src_h - 1);
2765 /* Finding the last pixel of the last line of the display
2766 data and adding to linear_offset*/
2768 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2769 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2772 I915_WRITE(reg, dspcntr);
2774 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2775 if (INTEL_INFO(dev)->gen >= 4) {
2776 I915_WRITE(DSPSURF(plane),
2777 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2778 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2779 I915_WRITE(DSPLINOFF(plane), linear_offset);
2781 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2785 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2786 struct drm_framebuffer *fb,
2789 struct drm_device *dev = crtc->dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2792 struct drm_plane *primary = crtc->primary;
2793 bool visible = to_intel_plane_state(primary->state)->visible;
2794 struct drm_i915_gem_object *obj;
2795 int plane = intel_crtc->plane;
2796 unsigned long linear_offset;
2798 u32 reg = DSPCNTR(plane);
2801 if (!visible || !fb) {
2803 I915_WRITE(DSPSURF(plane), 0);
2808 obj = intel_fb_obj(fb);
2809 if (WARN_ON(obj == NULL))
2812 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2814 dspcntr = DISPPLANE_GAMMA_ENABLE;
2816 dspcntr |= DISPLAY_PLANE_ENABLE;
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2821 switch (fb->pixel_format) {
2823 dspcntr |= DISPPLANE_8BPP;
2825 case DRM_FORMAT_RGB565:
2826 dspcntr |= DISPPLANE_BGRX565;
2828 case DRM_FORMAT_XRGB8888:
2829 dspcntr |= DISPPLANE_BGRX888;
2831 case DRM_FORMAT_XBGR8888:
2832 dspcntr |= DISPPLANE_RGBX888;
2834 case DRM_FORMAT_XRGB2101010:
2835 dspcntr |= DISPPLANE_BGRX101010;
2837 case DRM_FORMAT_XBGR2101010:
2838 dspcntr |= DISPPLANE_RGBX101010;
2844 if (obj->tiling_mode != I915_TILING_NONE)
2845 dspcntr |= DISPPLANE_TILED;
2847 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2848 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2850 linear_offset = y * fb->pitches[0] + x * pixel_size;
2851 intel_crtc->dspaddr_offset =
2852 intel_gen4_compute_page_offset(dev_priv,
2853 &x, &y, obj->tiling_mode,
2856 linear_offset -= intel_crtc->dspaddr_offset;
2857 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2858 dspcntr |= DISPPLANE_ROTATE_180;
2860 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2861 x += (intel_crtc->config->pipe_src_w - 1);
2862 y += (intel_crtc->config->pipe_src_h - 1);
2864 /* Finding the last pixel of the last line of the display
2865 data and adding to linear_offset*/
2867 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2868 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2872 I915_WRITE(reg, dspcntr);
2874 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2875 I915_WRITE(DSPSURF(plane),
2876 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2877 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2878 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2880 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2881 I915_WRITE(DSPLINOFF(plane), linear_offset);
2886 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2887 uint32_t pixel_format)
2889 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2892 * The stride is either expressed as a multiple of 64 bytes
2893 * chunks for linear buffers or in number of tiles for tiled
2896 switch (fb_modifier) {
2897 case DRM_FORMAT_MOD_NONE:
2899 case I915_FORMAT_MOD_X_TILED:
2900 if (INTEL_INFO(dev)->gen == 2)
2903 case I915_FORMAT_MOD_Y_TILED:
2904 /* No need to check for old gens and Y tiling since this is
2905 * about the display engine and those will be blocked before
2909 case I915_FORMAT_MOD_Yf_TILED:
2910 if (bits_per_pixel == 8)
2915 MISSING_CASE(fb_modifier);
2920 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2921 struct drm_i915_gem_object *obj)
2923 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2925 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2926 view = &i915_ggtt_view_rotated;
2928 return i915_gem_obj_ggtt_offset_view(obj, view);
2931 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2933 struct drm_device *dev = intel_crtc->base.dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2936 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2937 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2938 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2939 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2940 intel_crtc->base.base.id, intel_crtc->pipe, id);
2944 * This function detaches (aka. unbinds) unused scalers in hardware
2946 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2948 struct intel_crtc_scaler_state *scaler_state;
2951 scaler_state = &intel_crtc->config->scaler_state;
2953 /* loop through and disable scalers that aren't in use */
2954 for (i = 0; i < intel_crtc->num_scalers; i++) {
2955 if (!scaler_state->scalers[i].in_use)
2956 skl_detach_scaler(intel_crtc, i);
2960 u32 skl_plane_ctl_format(uint32_t pixel_format)
2962 switch (pixel_format) {
2964 return PLANE_CTL_FORMAT_INDEXED;
2965 case DRM_FORMAT_RGB565:
2966 return PLANE_CTL_FORMAT_RGB_565;
2967 case DRM_FORMAT_XBGR8888:
2968 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2969 case DRM_FORMAT_XRGB8888:
2970 return PLANE_CTL_FORMAT_XRGB_8888;
2972 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2973 * to be already pre-multiplied. We need to add a knob (or a different
2974 * DRM_FORMAT) for user-space to configure that.
2976 case DRM_FORMAT_ABGR8888:
2977 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979 case DRM_FORMAT_ARGB8888:
2980 return PLANE_CTL_FORMAT_XRGB_8888 |
2981 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2982 case DRM_FORMAT_XRGB2101010:
2983 return PLANE_CTL_FORMAT_XRGB_2101010;
2984 case DRM_FORMAT_XBGR2101010:
2985 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2986 case DRM_FORMAT_YUYV:
2987 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2988 case DRM_FORMAT_YVYU:
2989 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2990 case DRM_FORMAT_UYVY:
2991 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2992 case DRM_FORMAT_VYUY:
2993 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2995 MISSING_CASE(pixel_format);
3001 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3003 switch (fb_modifier) {
3004 case DRM_FORMAT_MOD_NONE:
3006 case I915_FORMAT_MOD_X_TILED:
3007 return PLANE_CTL_TILED_X;
3008 case I915_FORMAT_MOD_Y_TILED:
3009 return PLANE_CTL_TILED_Y;
3010 case I915_FORMAT_MOD_Yf_TILED:
3011 return PLANE_CTL_TILED_YF;
3013 MISSING_CASE(fb_modifier);
3019 u32 skl_plane_ctl_rotation(unsigned int rotation)
3022 case BIT(DRM_ROTATE_0):
3025 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3026 * while i915 HW rotation is clockwise, thats why this swapping.
3028 case BIT(DRM_ROTATE_90):
3029 return PLANE_CTL_ROTATE_270;
3030 case BIT(DRM_ROTATE_180):
3031 return PLANE_CTL_ROTATE_180;
3032 case BIT(DRM_ROTATE_270):
3033 return PLANE_CTL_ROTATE_90;
3035 MISSING_CASE(rotation);
3041 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3042 struct drm_framebuffer *fb,
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048 struct drm_plane *plane = crtc->primary;
3049 bool visible = to_intel_plane_state(plane->state)->visible;
3050 struct drm_i915_gem_object *obj;
3051 int pipe = intel_crtc->pipe;
3052 u32 plane_ctl, stride_div, stride;
3053 u32 tile_height, plane_offset, plane_size;
3054 unsigned int rotation;
3055 int x_offset, y_offset;
3056 unsigned long surf_addr;
3057 struct intel_crtc_state *crtc_state = intel_crtc->config;
3058 struct intel_plane_state *plane_state;
3059 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3060 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3063 plane_state = to_intel_plane_state(plane->state);
3065 if (!visible || !fb) {
3066 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3067 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3068 POSTING_READ(PLANE_CTL(pipe, 0));
3072 plane_ctl = PLANE_CTL_ENABLE |
3073 PLANE_CTL_PIPE_GAMMA_ENABLE |
3074 PLANE_CTL_PIPE_CSC_ENABLE;
3076 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3077 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3078 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3080 rotation = plane->state->rotation;
3081 plane_ctl |= skl_plane_ctl_rotation(rotation);
3083 obj = intel_fb_obj(fb);
3084 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3086 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3089 * FIXME: intel_plane_state->src, dst aren't set when transitional
3090 * update_plane helpers are called from legacy paths.
3091 * Once full atomic crtc is available, below check can be avoided.
3093 if (drm_rect_width(&plane_state->src)) {
3094 scaler_id = plane_state->scaler_id;
3095 src_x = plane_state->src.x1 >> 16;
3096 src_y = plane_state->src.y1 >> 16;
3097 src_w = drm_rect_width(&plane_state->src) >> 16;
3098 src_h = drm_rect_height(&plane_state->src) >> 16;
3099 dst_x = plane_state->dst.x1;
3100 dst_y = plane_state->dst.y1;
3101 dst_w = drm_rect_width(&plane_state->dst);
3102 dst_h = drm_rect_height(&plane_state->dst);
3104 WARN_ON(x != src_x || y != src_y);
3106 src_w = intel_crtc->config->pipe_src_w;
3107 src_h = intel_crtc->config->pipe_src_h;
3110 if (intel_rotation_90_or_270(rotation)) {
3111 /* stride = Surface height in tiles */
3112 tile_height = intel_tile_height(dev, fb->pixel_format,
3114 stride = DIV_ROUND_UP(fb->height, tile_height);
3115 x_offset = stride * tile_height - y - src_h;
3117 plane_size = (src_w - 1) << 16 | (src_h - 1);
3119 stride = fb->pitches[0] / stride_div;
3122 plane_size = (src_h - 1) << 16 | (src_w - 1);
3124 plane_offset = y_offset << 16 | x_offset;
3126 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3127 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3128 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3129 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3131 if (scaler_id >= 0) {
3132 uint32_t ps_ctrl = 0;
3134 WARN_ON(!dst_w || !dst_h);
3135 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3136 crtc_state->scaler_state.scalers[scaler_id].mode;
3137 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3138 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3139 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3140 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3141 I915_WRITE(PLANE_POS(pipe, 0), 0);
3143 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3146 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3148 POSTING_READ(PLANE_SURF(pipe, 0));
3151 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3153 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3154 int x, int y, enum mode_set_atomic state)
3156 struct drm_device *dev = crtc->dev;
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3159 if (dev_priv->fbc.disable_fbc)
3160 dev_priv->fbc.disable_fbc(dev_priv);
3162 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3167 static void intel_complete_page_flips(struct drm_device *dev)
3169 struct drm_crtc *crtc;
3171 for_each_crtc(dev, crtc) {
3172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173 enum plane plane = intel_crtc->plane;
3175 intel_prepare_page_flip(dev, plane);
3176 intel_finish_page_flip_plane(dev, plane);
3180 static void intel_update_primary_planes(struct drm_device *dev)
3182 struct drm_i915_private *dev_priv = dev->dev_private;
3183 struct drm_crtc *crtc;
3185 for_each_crtc(dev, crtc) {
3186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 drm_modeset_lock(&crtc->mutex, NULL);
3190 * FIXME: Once we have proper support for primary planes (and
3191 * disabling them without disabling the entire crtc) allow again
3192 * a NULL crtc->primary->fb.
3194 if (intel_crtc->active && crtc->primary->fb)
3195 dev_priv->display.update_primary_plane(crtc,
3199 drm_modeset_unlock(&crtc->mutex);
3203 void intel_prepare_reset(struct drm_device *dev)
3205 /* no reset support for gen2 */
3209 /* reset doesn't touch the display */
3210 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3213 drm_modeset_lock_all(dev);
3215 * Disabling the crtcs gracefully seems nicer. Also the
3216 * g33 docs say we should at least disable all the planes.
3218 intel_display_suspend(dev);
3221 void intel_finish_reset(struct drm_device *dev)
3223 struct drm_i915_private *dev_priv = to_i915(dev);
3226 * Flips in the rings will be nuked by the reset,
3227 * so complete all pending flips so that user space
3228 * will get its events and not get stuck.
3230 intel_complete_page_flips(dev);
3232 /* no reset support for gen2 */
3236 /* reset doesn't touch the display */
3237 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3239 * Flips in the rings have been nuked by the reset,
3240 * so update the base address of all primary
3241 * planes to the the last fb to make sure we're
3242 * showing the correct fb after a reset.
3244 intel_update_primary_planes(dev);
3249 * The display has been reset as well,
3250 * so need a full re-initialization.
3252 intel_runtime_pm_disable_interrupts(dev_priv);
3253 intel_runtime_pm_enable_interrupts(dev_priv);
3255 intel_modeset_init_hw(dev);
3257 spin_lock_irq(&dev_priv->irq_lock);
3258 if (dev_priv->display.hpd_irq_setup)
3259 dev_priv->display.hpd_irq_setup(dev);
3260 spin_unlock_irq(&dev_priv->irq_lock);
3262 intel_display_resume(dev);
3264 intel_hpd_init(dev_priv);
3266 drm_modeset_unlock_all(dev);
3270 intel_finish_fb(struct drm_framebuffer *old_fb)
3272 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3273 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3274 bool was_interruptible = dev_priv->mm.interruptible;
3277 /* Big Hammer, we also need to ensure that any pending
3278 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3279 * current scanout is retired before unpinning the old
3280 * framebuffer. Note that we rely on userspace rendering
3281 * into the buffer attached to the pipe they are waiting
3282 * on. If not, userspace generates a GPU hang with IPEHR
3283 * point to the MI_WAIT_FOR_EVENT.
3285 * This should only fail upon a hung GPU, in which case we
3286 * can safely continue.
3288 dev_priv->mm.interruptible = false;
3289 ret = i915_gem_object_wait_rendering(obj, true);
3290 dev_priv->mm.interruptible = was_interruptible;
3295 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3297 struct drm_device *dev = crtc->dev;
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3302 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3303 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3306 spin_lock_irq(&dev->event_lock);
3307 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3308 spin_unlock_irq(&dev->event_lock);
3313 static void intel_update_pipe_size(struct intel_crtc *crtc)
3315 struct drm_device *dev = crtc->base.dev;
3316 struct drm_i915_private *dev_priv = dev->dev_private;
3317 const struct drm_display_mode *adjusted_mode;
3323 * Update pipe size and adjust fitter if needed: the reason for this is
3324 * that in compute_mode_changes we check the native mode (not the pfit
3325 * mode) to see if we can flip rather than do a full mode set. In the
3326 * fastboot case, we'll flip, but if we don't update the pipesrc and
3327 * pfit state, we'll end up with a big fb scanned out into the wrong
3330 * To fix this properly, we need to hoist the checks up into
3331 * compute_mode_changes (or above), check the actual pfit state and
3332 * whether the platform allows pfit disable with pipe active, and only
3333 * then update the pipesrc and pfit state, even on the flip path.
3336 adjusted_mode = &crtc->config->base.adjusted_mode;
3338 I915_WRITE(PIPESRC(crtc->pipe),
3339 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3340 (adjusted_mode->crtc_vdisplay - 1));
3341 if (!crtc->config->pch_pfit.enabled &&
3342 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3343 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3344 I915_WRITE(PF_CTL(crtc->pipe), 0);
3345 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3346 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3348 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3349 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3352 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
3360 /* enable normal train */
3361 reg = FDI_TX_CTL(pipe);
3362 temp = I915_READ(reg);
3363 if (IS_IVYBRIDGE(dev)) {
3364 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3370 I915_WRITE(reg, temp);
3372 reg = FDI_RX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 if (HAS_PCH_CPT(dev)) {
3375 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_NONE;
3381 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3383 /* wait one idle pattern time */
3387 /* IVB wants error correction enabled */
3388 if (IS_IVYBRIDGE(dev))
3389 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390 FDI_FE_ERRC_ENABLE);
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 int pipe = intel_crtc->pipe;
3400 u32 reg, temp, tries;
3402 /* FDI needs bits from pipe first */
3403 assert_pipe_enabled(dev_priv, pipe);
3405 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3407 reg = FDI_RX_IMR(pipe);
3408 temp = I915_READ(reg);
3409 temp &= ~FDI_RX_SYMBOL_LOCK;
3410 temp &= ~FDI_RX_BIT_LOCK;
3411 I915_WRITE(reg, temp);
3415 /* enable CPU FDI TX and PCH FDI RX */
3416 reg = FDI_TX_CTL(pipe);
3417 temp = I915_READ(reg);
3418 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420 temp &= ~FDI_LINK_TRAIN_NONE;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1;
3422 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3424 reg = FDI_RX_CTL(pipe);
3425 temp = I915_READ(reg);
3426 temp &= ~FDI_LINK_TRAIN_NONE;
3427 temp |= FDI_LINK_TRAIN_PATTERN_1;
3428 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3433 /* Ironlake workaround, enable clock pointer after FDI enable*/
3434 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436 FDI_RX_PHASE_SYNC_POINTER_EN);
3438 reg = FDI_RX_IIR(pipe);
3439 for (tries = 0; tries < 5; tries++) {
3440 temp = I915_READ(reg);
3441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3443 if ((temp & FDI_RX_BIT_LOCK)) {
3444 DRM_DEBUG_KMS("FDI train 1 done.\n");
3445 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3450 DRM_ERROR("FDI train 1 fail!\n");
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 I915_WRITE(reg, temp);
3459 reg = FDI_RX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 temp &= ~FDI_LINK_TRAIN_NONE;
3462 temp |= FDI_LINK_TRAIN_PATTERN_2;
3463 I915_WRITE(reg, temp);
3468 reg = FDI_RX_IIR(pipe);
3469 for (tries = 0; tries < 5; tries++) {
3470 temp = I915_READ(reg);
3471 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3473 if (temp & FDI_RX_SYMBOL_LOCK) {
3474 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475 DRM_DEBUG_KMS("FDI train 2 done.\n");
3480 DRM_ERROR("FDI train 2 fail!\n");
3482 DRM_DEBUG_KMS("FDI train done\n");
3486 static const int snb_b_fdi_train_param[] = {
3487 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3496 struct drm_device *dev = crtc->dev;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499 int pipe = intel_crtc->pipe;
3500 u32 reg, temp, i, retry;
3502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3504 reg = FDI_RX_IMR(pipe);
3505 temp = I915_READ(reg);
3506 temp &= ~FDI_RX_SYMBOL_LOCK;
3507 temp &= ~FDI_RX_BIT_LOCK;
3508 I915_WRITE(reg, temp);
3513 /* enable CPU FDI TX and PCH FDI RX */
3514 reg = FDI_TX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3517 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3523 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3525 I915_WRITE(FDI_RX_MISC(pipe),
3526 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3528 reg = FDI_RX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 if (HAS_PCH_CPT(dev)) {
3531 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_1;
3537 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3542 for (i = 0; i < 4; i++) {
3543 reg = FDI_TX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546 temp |= snb_b_fdi_train_param[i];
3547 I915_WRITE(reg, temp);
3552 for (retry = 0; retry < 5; retry++) {
3553 reg = FDI_RX_IIR(pipe);
3554 temp = I915_READ(reg);
3555 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3556 if (temp & FDI_RX_BIT_LOCK) {
3557 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3558 DRM_DEBUG_KMS("FDI train 1 done.\n");
3567 DRM_ERROR("FDI train 1 fail!\n");
3570 reg = FDI_TX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~FDI_LINK_TRAIN_NONE;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2;
3575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3579 I915_WRITE(reg, temp);
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 if (HAS_PCH_CPT(dev)) {
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3587 temp &= ~FDI_LINK_TRAIN_NONE;
3588 temp |= FDI_LINK_TRAIN_PATTERN_2;
3590 I915_WRITE(reg, temp);
3595 for (i = 0; i < 4; i++) {
3596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599 temp |= snb_b_fdi_train_param[i];
3600 I915_WRITE(reg, temp);
3605 for (retry = 0; retry < 5; retry++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609 if (temp & FDI_RX_SYMBOL_LOCK) {
3610 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3611 DRM_DEBUG_KMS("FDI train 2 done.\n");
3620 DRM_ERROR("FDI train 2 fail!\n");
3622 DRM_DEBUG_KMS("FDI train done.\n");
3625 /* Manual link training for Ivy Bridge A0 parts */
3626 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 int pipe = intel_crtc->pipe;
3632 u32 reg, temp, i, j;
3634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3636 reg = FDI_RX_IMR(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_RX_SYMBOL_LOCK;
3639 temp &= ~FDI_RX_BIT_LOCK;
3640 I915_WRITE(reg, temp);
3645 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646 I915_READ(FDI_RX_IIR(pipe)));
3648 /* Try each vswing and preemphasis setting twice before moving on */
3649 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650 /* disable first in case we need to retry */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654 temp &= ~FDI_TX_ENABLE;
3655 I915_WRITE(reg, temp);
3657 reg = FDI_RX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_AUTO;
3660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661 temp &= ~FDI_RX_ENABLE;
3662 I915_WRITE(reg, temp);
3664 /* enable CPU FDI TX and PCH FDI RX */
3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671 temp |= snb_b_fdi_train_param[j/2];
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3675 I915_WRITE(FDI_RX_MISC(pipe),
3676 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3678 reg = FDI_RX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681 temp |= FDI_COMPOSITE_SYNC;
3682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3685 udelay(1); /* should be 0.5us */
3687 for (i = 0; i < 4; i++) {
3688 reg = FDI_RX_IIR(pipe);
3689 temp = I915_READ(reg);
3690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3692 if (temp & FDI_RX_BIT_LOCK ||
3693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3699 udelay(1); /* should be 0.5us */
3702 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3707 reg = FDI_TX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711 I915_WRITE(reg, temp);
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717 I915_WRITE(reg, temp);
3720 udelay(2); /* should be 1.5us */
3722 for (i = 0; i < 4; i++) {
3723 reg = FDI_RX_IIR(pipe);
3724 temp = I915_READ(reg);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3727 if (temp & FDI_RX_SYMBOL_LOCK ||
3728 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3734 udelay(2); /* should be 1.5us */
3737 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3741 DRM_DEBUG_KMS("FDI train done.\n");
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3746 struct drm_device *dev = intel_crtc->base.dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 int pipe = intel_crtc->pipe;
3752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3763 /* Switch from Rawclk to PCDclk */
3764 temp = I915_READ(reg);
3765 I915_WRITE(reg, temp | FDI_PCDCLK);
3770 /* Enable CPU FDI TX PLL, always on for Ironlake */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3783 struct drm_device *dev = intel_crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 int pipe = intel_crtc->pipe;
3788 /* Switch from PCDclk to Rawclk */
3789 reg = FDI_RX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3793 /* Disable CPU FDI TX PLL */
3794 reg = FDI_TX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3805 /* Wait for the clocks to turn off. */
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815 int pipe = intel_crtc->pipe;
3818 /* disable CPU FDI tx and PCH FDI rx */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~(0x7 << 16);
3827 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3833 /* Ironlake workaround, disable clock pointer after downing FDI */
3834 if (HAS_PCH_IBX(dev))
3835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3837 /* still set train pattern 1 */
3838 reg = FDI_TX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 temp &= ~FDI_LINK_TRAIN_NONE;
3841 temp |= FDI_LINK_TRAIN_PATTERN_1;
3842 I915_WRITE(reg, temp);
3844 reg = FDI_RX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 if (HAS_PCH_CPT(dev)) {
3847 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_1;
3853 /* BPC in FDI rx is consistent with that in PIPECONF */
3854 temp &= ~(0x07 << 16);
3855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3856 I915_WRITE(reg, temp);
3862 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3864 struct intel_crtc *crtc;
3866 /* Note that we don't need to be called with mode_config.lock here
3867 * as our list of CRTC objects is static for the lifetime of the
3868 * device and so cannot disappear as we iterate. Similarly, we can
3869 * happily treat the predicates as racy, atomic checks as userspace
3870 * cannot claim and pin a new fb without at least acquring the
3871 * struct_mutex and so serialising with us.
3873 for_each_intel_crtc(dev, crtc) {
3874 if (atomic_read(&crtc->unpin_work_count) == 0)
3877 if (crtc->unpin_work)
3878 intel_wait_for_vblank(dev, crtc->pipe);
3886 static void page_flip_completed(struct intel_crtc *intel_crtc)
3888 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889 struct intel_unpin_work *work = intel_crtc->unpin_work;
3891 /* ensure that the unpin work is consistent wrt ->pending. */
3893 intel_crtc->unpin_work = NULL;
3896 drm_send_vblank_event(intel_crtc->base.dev,
3900 drm_crtc_vblank_put(&intel_crtc->base);
3902 wake_up_all(&dev_priv->pending_flip_queue);
3903 queue_work(dev_priv->wq, &work->work);
3905 trace_i915_flip_complete(intel_crtc->plane,
3906 work->pending_flip_obj);
3909 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3911 struct drm_device *dev = crtc->dev;
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3914 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3915 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3916 !intel_crtc_has_pending_flip(crtc),
3918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3920 spin_lock_irq(&dev->event_lock);
3921 if (intel_crtc->unpin_work) {
3922 WARN_ONCE(1, "Removing stuck page flip\n");
3923 page_flip_completed(intel_crtc);
3925 spin_unlock_irq(&dev->event_lock);
3928 if (crtc->primary->fb) {
3929 mutex_lock(&dev->struct_mutex);
3930 intel_finish_fb(crtc->primary->fb);
3931 mutex_unlock(&dev->struct_mutex);
3935 /* Program iCLKIP clock to the desired frequency */
3936 static void lpt_program_iclkip(struct drm_crtc *crtc)
3938 struct drm_device *dev = crtc->dev;
3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3941 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3944 mutex_lock(&dev_priv->sb_lock);
3946 /* It is necessary to ungate the pixclk gate prior to programming
3947 * the divisors, and gate it back when it is done.
3949 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3951 /* Disable SSCCTL */
3952 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3953 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3957 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3958 if (clock == 20000) {
3963 /* The iCLK virtual clock root frequency is in MHz,
3964 * but the adjusted_mode->crtc_clock in in KHz. To get the
3965 * divisors, it is necessary to divide one by another, so we
3966 * convert the virtual clock precision to KHz here for higher
3969 u32 iclk_virtual_root_freq = 172800 * 1000;
3970 u32 iclk_pi_range = 64;
3971 u32 desired_divisor, msb_divisor_value, pi_value;
3973 desired_divisor = (iclk_virtual_root_freq / clock);
3974 msb_divisor_value = desired_divisor / iclk_pi_range;
3975 pi_value = desired_divisor % iclk_pi_range;
3978 divsel = msb_divisor_value - 2;
3979 phaseinc = pi_value;
3982 /* This should not happen with any sane values */
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3984 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3985 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3986 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3988 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3995 /* Program SSCDIVINTPHASE6 */
3996 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3997 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3999 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4000 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4001 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4002 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4003 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4005 /* Program SSCAUXDIV */
4006 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4007 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4009 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4011 /* Enable modulator and associated divider */
4012 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4013 temp &= ~SBI_SSCCTL_DISABLE;
4014 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4016 /* Wait for initialization time */
4019 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4021 mutex_unlock(&dev_priv->sb_lock);
4024 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4025 enum pipe pch_transcoder)
4027 struct drm_device *dev = crtc->base.dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4031 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4032 I915_READ(HTOTAL(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4034 I915_READ(HBLANK(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4036 I915_READ(HSYNC(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4039 I915_READ(VTOTAL(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4041 I915_READ(VBLANK(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4043 I915_READ(VSYNC(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4045 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4048 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4053 temp = I915_READ(SOUTH_CHICKEN1);
4054 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4058 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4060 temp &= ~FDI_BC_BIFURCATION_SELECT;
4062 temp |= FDI_BC_BIFURCATION_SELECT;
4064 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4065 I915_WRITE(SOUTH_CHICKEN1, temp);
4066 POSTING_READ(SOUTH_CHICKEN1);
4069 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4071 struct drm_device *dev = intel_crtc->base.dev;
4073 switch (intel_crtc->pipe) {
4077 if (intel_crtc->config->fdi_lanes > 2)
4078 cpt_set_fdi_bc_bifurcation(dev, false);
4080 cpt_set_fdi_bc_bifurcation(dev, true);
4084 cpt_set_fdi_bc_bifurcation(dev, true);
4093 * Enable PCH resources required for PCH ports:
4095 * - FDI training & RX/TX
4096 * - update transcoder timings
4097 * - DP transcoding bits
4100 static void ironlake_pch_enable(struct drm_crtc *crtc)
4102 struct drm_device *dev = crtc->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105 int pipe = intel_crtc->pipe;
4108 assert_pch_transcoder_disabled(dev_priv, pipe);
4110 if (IS_IVYBRIDGE(dev))
4111 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4113 /* Write the TU size bits before fdi link training, so that error
4114 * detection works. */
4115 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4116 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4118 /* For PCH output, training FDI link */
4119 dev_priv->display.fdi_link_train(crtc);
4121 /* We need to program the right clock selection before writing the pixel
4122 * mutliplier into the DPLL. */
4123 if (HAS_PCH_CPT(dev)) {
4126 temp = I915_READ(PCH_DPLL_SEL);
4127 temp |= TRANS_DPLL_ENABLE(pipe);
4128 sel = TRANS_DPLLB_SEL(pipe);
4129 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4133 I915_WRITE(PCH_DPLL_SEL, temp);
4136 /* XXX: pch pll's can be enabled any time before we enable the PCH
4137 * transcoder, and we actually should do this to not upset any PCH
4138 * transcoder that already use the clock when we share it.
4140 * Note that enable_shared_dpll tries to do the right thing, but
4141 * get_shared_dpll unconditionally resets the pll - we need that to have
4142 * the right LVDS enable sequence. */
4143 intel_enable_shared_dpll(intel_crtc);
4145 /* set transcoder timing, panel must allow it */
4146 assert_panel_unlocked(dev_priv, pipe);
4147 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4149 intel_fdi_normal_train(crtc);
4151 /* For PCH DP, enable TRANS_DP_CTL */
4152 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4153 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4154 reg = TRANS_DP_CTL(pipe);
4155 temp = I915_READ(reg);
4156 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4157 TRANS_DP_SYNC_MASK |
4159 temp |= TRANS_DP_OUTPUT_ENABLE;
4160 temp |= bpc << 9; /* same format but at 11:9 */
4162 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4163 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4164 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4165 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4167 switch (intel_trans_dp_port_sel(crtc)) {
4169 temp |= TRANS_DP_PORT_SEL_B;
4172 temp |= TRANS_DP_PORT_SEL_C;
4175 temp |= TRANS_DP_PORT_SEL_D;
4181 I915_WRITE(reg, temp);
4184 ironlake_enable_pch_transcoder(dev_priv, pipe);
4187 static void lpt_pch_enable(struct drm_crtc *crtc)
4189 struct drm_device *dev = crtc->dev;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4194 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4196 lpt_program_iclkip(crtc);
4198 /* Set transcoder timing. */
4199 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4201 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4204 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4205 struct intel_crtc_state *crtc_state)
4207 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4208 struct intel_shared_dpll *pll;
4209 struct intel_shared_dpll_config *shared_dpll;
4210 enum intel_dpll_id i;
4212 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4214 if (HAS_PCH_IBX(dev_priv->dev)) {
4215 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4216 i = (enum intel_dpll_id) crtc->pipe;
4217 pll = &dev_priv->shared_dplls[i];
4219 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220 crtc->base.base.id, pll->name);
4222 WARN_ON(shared_dpll[i].crtc_mask);
4227 if (IS_BROXTON(dev_priv->dev)) {
4228 /* PLL is attached to port in bxt */
4229 struct intel_encoder *encoder;
4230 struct intel_digital_port *intel_dig_port;
4232 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4233 if (WARN_ON(!encoder))
4236 intel_dig_port = enc_to_dig_port(&encoder->base);
4237 /* 1:1 mapping between ports and PLLs */
4238 i = (enum intel_dpll_id)intel_dig_port->port;
4239 pll = &dev_priv->shared_dplls[i];
4240 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241 crtc->base.base.id, pll->name);
4242 WARN_ON(shared_dpll[i].crtc_mask);
4247 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4248 pll = &dev_priv->shared_dplls[i];
4250 /* Only want to check enabled timings first */
4251 if (shared_dpll[i].crtc_mask == 0)
4254 if (memcmp(&crtc_state->dpll_hw_state,
4255 &shared_dpll[i].hw_state,
4256 sizeof(crtc_state->dpll_hw_state)) == 0) {
4257 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4258 crtc->base.base.id, pll->name,
4259 shared_dpll[i].crtc_mask,
4265 /* Ok no matching timings, maybe there's a free one? */
4266 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267 pll = &dev_priv->shared_dplls[i];
4268 if (shared_dpll[i].crtc_mask == 0) {
4269 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270 crtc->base.base.id, pll->name);
4278 if (shared_dpll[i].crtc_mask == 0)
4279 shared_dpll[i].hw_state =
4280 crtc_state->dpll_hw_state;
4282 crtc_state->shared_dpll = i;
4283 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4284 pipe_name(crtc->pipe));
4286 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4291 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4293 struct drm_i915_private *dev_priv = to_i915(state->dev);
4294 struct intel_shared_dpll_config *shared_dpll;
4295 struct intel_shared_dpll *pll;
4296 enum intel_dpll_id i;
4298 if (!to_intel_atomic_state(state)->dpll_set)
4301 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303 pll = &dev_priv->shared_dplls[i];
4304 pll->config = shared_dpll[i];
4308 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 int dslreg = PIPEDSL(pipe);
4314 temp = I915_READ(dslreg);
4316 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4317 if (wait_for(I915_READ(dslreg) != temp, 5))
4318 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4323 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4324 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4325 int src_w, int src_h, int dst_w, int dst_h)
4327 struct intel_crtc_scaler_state *scaler_state =
4328 &crtc_state->scaler_state;
4329 struct intel_crtc *intel_crtc =
4330 to_intel_crtc(crtc_state->base.crtc);
4333 need_scaling = intel_rotation_90_or_270(rotation) ?
4334 (src_h != dst_w || src_w != dst_h):
4335 (src_w != dst_w || src_h != dst_h);
4338 * if plane is being disabled or scaler is no more required or force detach
4339 * - free scaler binded to this plane/crtc
4340 * - in order to do this, update crtc->scaler_usage
4342 * Here scaler state in crtc_state is set free so that
4343 * scaler can be assigned to other user. Actual register
4344 * update to free the scaler is done in plane/panel-fit programming.
4345 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4347 if (force_detach || !need_scaling) {
4348 if (*scaler_id >= 0) {
4349 scaler_state->scaler_users &= ~(1 << scaler_user);
4350 scaler_state->scalers[*scaler_id].in_use = 0;
4352 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354 intel_crtc->pipe, scaler_user, *scaler_id,
4355 scaler_state->scaler_users);
4362 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4363 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4365 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4366 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4367 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4368 "size is out of scaler range\n",
4369 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4373 /* mark this plane as a scaler user in crtc_state */
4374 scaler_state->scaler_users |= (1 << scaler_user);
4375 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4378 scaler_state->scaler_users);
4384 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4386 * @state: crtc's scaler state
4389 * 0 - scaler_usage updated successfully
4390 * error - requested scaling cannot be supported or other error condition
4392 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4394 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4395 struct drm_display_mode *adjusted_mode =
4396 &state->base.adjusted_mode;
4398 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4399 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4401 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4402 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4403 state->pipe_src_w, state->pipe_src_h,
4404 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4408 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4410 * @state: crtc's scaler state
4411 * @plane_state: atomic plane state to update
4414 * 0 - scaler_usage updated successfully
4415 * error - requested scaling cannot be supported or other error condition
4417 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4418 struct intel_plane_state *plane_state)
4421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4422 struct intel_plane *intel_plane =
4423 to_intel_plane(plane_state->base.plane);
4424 struct drm_framebuffer *fb = plane_state->base.fb;
4427 bool force_detach = !fb || !plane_state->visible;
4429 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4430 intel_plane->base.base.id, intel_crtc->pipe,
4431 drm_plane_index(&intel_plane->base));
4433 ret = skl_update_scaler(crtc_state, force_detach,
4434 drm_plane_index(&intel_plane->base),
4435 &plane_state->scaler_id,
4436 plane_state->base.rotation,
4437 drm_rect_width(&plane_state->src) >> 16,
4438 drm_rect_height(&plane_state->src) >> 16,
4439 drm_rect_width(&plane_state->dst),
4440 drm_rect_height(&plane_state->dst));
4442 if (ret || plane_state->scaler_id < 0)
4445 /* check colorkey */
4446 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4447 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4448 intel_plane->base.base.id);
4452 /* Check src format */
4453 switch (fb->pixel_format) {
4454 case DRM_FORMAT_RGB565:
4455 case DRM_FORMAT_XBGR8888:
4456 case DRM_FORMAT_XRGB8888:
4457 case DRM_FORMAT_ABGR8888:
4458 case DRM_FORMAT_ARGB8888:
4459 case DRM_FORMAT_XRGB2101010:
4460 case DRM_FORMAT_XBGR2101010:
4461 case DRM_FORMAT_YUYV:
4462 case DRM_FORMAT_YVYU:
4463 case DRM_FORMAT_UYVY:
4464 case DRM_FORMAT_VYUY:
4467 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4468 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4475 static void skylake_scaler_disable(struct intel_crtc *crtc)
4479 for (i = 0; i < crtc->num_scalers; i++)
4480 skl_detach_scaler(crtc, i);
4483 static void skylake_pfit_enable(struct intel_crtc *crtc)
4485 struct drm_device *dev = crtc->base.dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 int pipe = crtc->pipe;
4488 struct intel_crtc_scaler_state *scaler_state =
4489 &crtc->config->scaler_state;
4491 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4493 if (crtc->config->pch_pfit.enabled) {
4496 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4497 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4501 id = scaler_state->scaler_id;
4502 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4503 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4504 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4505 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4507 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4511 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4513 struct drm_device *dev = crtc->base.dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 int pipe = crtc->pipe;
4517 if (crtc->config->pch_pfit.enabled) {
4518 /* Force use of hard-coded filter coefficients
4519 * as some pre-programmed values are broken,
4522 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4523 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4524 PF_PIPE_SEL_IVB(pipe));
4526 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4527 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4528 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4532 void hsw_enable_ips(struct intel_crtc *crtc)
4534 struct drm_device *dev = crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4537 if (!crtc->config->ips_enabled)
4540 /* We can only enable IPS after we enable a plane and wait for a vblank */
4541 intel_wait_for_vblank(dev, crtc->pipe);
4543 assert_plane_enabled(dev_priv, crtc->plane);
4544 if (IS_BROADWELL(dev)) {
4545 mutex_lock(&dev_priv->rps.hw_lock);
4546 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4547 mutex_unlock(&dev_priv->rps.hw_lock);
4548 /* Quoting Art Runyan: "its not safe to expect any particular
4549 * value in IPS_CTL bit 31 after enabling IPS through the
4550 * mailbox." Moreover, the mailbox may return a bogus state,
4551 * so we need to just enable it and continue on.
4554 I915_WRITE(IPS_CTL, IPS_ENABLE);
4555 /* The bit only becomes 1 in the next vblank, so this wait here
4556 * is essentially intel_wait_for_vblank. If we don't have this
4557 * and don't wait for vblanks until the end of crtc_enable, then
4558 * the HW state readout code will complain that the expected
4559 * IPS_CTL value is not the one we read. */
4560 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4561 DRM_ERROR("Timed out waiting for IPS enable\n");
4565 void hsw_disable_ips(struct intel_crtc *crtc)
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4570 if (!crtc->config->ips_enabled)
4573 assert_plane_enabled(dev_priv, crtc->plane);
4574 if (IS_BROADWELL(dev)) {
4575 mutex_lock(&dev_priv->rps.hw_lock);
4576 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4577 mutex_unlock(&dev_priv->rps.hw_lock);
4578 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4579 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4580 DRM_ERROR("Timed out waiting for IPS disable\n");
4582 I915_WRITE(IPS_CTL, 0);
4583 POSTING_READ(IPS_CTL);
4586 /* We need to wait for a vblank before we can disable the plane. */
4587 intel_wait_for_vblank(dev, crtc->pipe);
4590 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4591 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4593 struct drm_device *dev = crtc->dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596 enum pipe pipe = intel_crtc->pipe;
4597 int palreg = PALETTE(pipe);
4599 bool reenable_ips = false;
4601 /* The clocks have to be on to load the palette. */
4602 if (!crtc->state->active)
4605 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4606 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4607 assert_dsi_pll_enabled(dev_priv);
4609 assert_pll_enabled(dev_priv, pipe);
4612 /* use legacy palette for Ironlake */
4613 if (!HAS_GMCH_DISPLAY(dev))
4614 palreg = LGC_PALETTE(pipe);
4616 /* Workaround : Do not read or write the pipe palette/gamma data while
4617 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4619 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4620 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4621 GAMMA_MODE_MODE_SPLIT)) {
4622 hsw_disable_ips(intel_crtc);
4623 reenable_ips = true;
4626 for (i = 0; i < 256; i++) {
4627 I915_WRITE(palreg + 4 * i,
4628 (intel_crtc->lut_r[i] << 16) |
4629 (intel_crtc->lut_g[i] << 8) |
4630 intel_crtc->lut_b[i]);
4634 hsw_enable_ips(intel_crtc);
4637 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4639 if (intel_crtc->overlay) {
4640 struct drm_device *dev = intel_crtc->base.dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4643 mutex_lock(&dev->struct_mutex);
4644 dev_priv->mm.interruptible = false;
4645 (void) intel_overlay_switch_off(intel_crtc->overlay);
4646 dev_priv->mm.interruptible = true;
4647 mutex_unlock(&dev->struct_mutex);
4650 /* Let userspace switch the overlay on again. In most cases userspace
4651 * has to recompute where to put it anyway.
4656 * intel_post_enable_primary - Perform operations after enabling primary plane
4657 * @crtc: the CRTC whose primary plane was just enabled
4659 * Performs potentially sleeping operations that must be done after the primary
4660 * plane is enabled, such as updating FBC and IPS. Note that this may be
4661 * called due to an explicit primary plane update, or due to an implicit
4662 * re-enable that is caused when a sprite plane is updated to no longer
4663 * completely hide the primary plane.
4666 intel_post_enable_primary(struct drm_crtc *crtc)
4668 struct drm_device *dev = crtc->dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4671 int pipe = intel_crtc->pipe;
4674 * BDW signals flip done immediately if the plane
4675 * is disabled, even if the plane enable is already
4676 * armed to occur at the next vblank :(
4678 if (IS_BROADWELL(dev))
4679 intel_wait_for_vblank(dev, pipe);
4682 * FIXME IPS should be fine as long as one plane is
4683 * enabled, but in practice it seems to have problems
4684 * when going from primary only to sprite only and vice
4687 hsw_enable_ips(intel_crtc);
4690 * Gen2 reports pipe underruns whenever all planes are disabled.
4691 * So don't enable underrun reporting before at least some planes
4693 * FIXME: Need to fix the logic to work when we turn off all planes
4694 * but leave the pipe running.
4697 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4699 /* Underruns don't raise interrupts, so check manually. */
4700 if (HAS_GMCH_DISPLAY(dev))
4701 i9xx_check_fifo_underruns(dev_priv);
4705 * intel_pre_disable_primary - Perform operations before disabling primary plane
4706 * @crtc: the CRTC whose primary plane is to be disabled
4708 * Performs potentially sleeping operations that must be done before the
4709 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4710 * be called due to an explicit primary plane update, or due to an implicit
4711 * disable that is caused when a sprite plane completely hides the primary
4715 intel_pre_disable_primary(struct drm_crtc *crtc)
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So diasble underrun reporting before all the planes get disabled.
4725 * FIXME: Need to fix the logic to work when we turn off all planes
4726 * but leave the pipe running.
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4732 * Vblank time updates from the shadow to live plane control register
4733 * are blocked if the memory self-refresh mode is active at that
4734 * moment. So to make sure the plane gets truly disabled, disable
4735 * first the self-refresh mode. The self-refresh enable bit in turn
4736 * will be checked/applied by the HW only at the next frame start
4737 * event which is after the vblank start event, so we need to have a
4738 * wait-for-vblank between disabling the plane and the pipe.
4740 if (HAS_GMCH_DISPLAY(dev)) {
4741 intel_set_memory_cxsr(dev_priv, false);
4742 dev_priv->wm.vlv.cxsr = false;
4743 intel_wait_for_vblank(dev, pipe);
4747 * FIXME IPS should be fine as long as one plane is
4748 * enabled, but in practice it seems to have problems
4749 * when going from primary only to sprite only and vice
4752 hsw_disable_ips(intel_crtc);
4755 static void intel_post_plane_update(struct intel_crtc *crtc)
4757 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4758 struct drm_device *dev = crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 struct drm_plane *plane;
4762 if (atomic->wait_vblank)
4763 intel_wait_for_vblank(dev, crtc->pipe);
4765 intel_frontbuffer_flip(dev, atomic->fb_bits);
4767 if (atomic->disable_cxsr)
4768 crtc->wm.cxsr_allowed = true;
4770 if (crtc->atomic.update_wm_post)
4771 intel_update_watermarks(&crtc->base);
4773 if (atomic->update_fbc)
4774 intel_fbc_update(dev_priv);
4776 if (atomic->post_enable_primary)
4777 intel_post_enable_primary(&crtc->base);
4779 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4780 intel_update_sprite_watermarks(plane, &crtc->base,
4781 0, 0, 0, false, false);
4783 memset(atomic, 0, sizeof(*atomic));
4786 static void intel_pre_plane_update(struct intel_crtc *crtc)
4788 struct drm_device *dev = crtc->base.dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4791 struct drm_plane *p;
4793 /* Track fb's for any planes being disabled */
4794 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4795 struct intel_plane *plane = to_intel_plane(p);
4797 mutex_lock(&dev->struct_mutex);
4798 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4799 plane->frontbuffer_bit);
4800 mutex_unlock(&dev->struct_mutex);
4803 if (atomic->wait_for_flips)
4804 intel_crtc_wait_for_pending_flips(&crtc->base);
4806 if (atomic->disable_fbc)
4807 intel_fbc_disable_crtc(crtc);
4809 if (crtc->atomic.disable_ips)
4810 hsw_disable_ips(crtc);
4812 if (atomic->pre_disable_primary)
4813 intel_pre_disable_primary(&crtc->base);
4815 if (atomic->disable_cxsr) {
4816 crtc->wm.cxsr_allowed = false;
4817 intel_set_memory_cxsr(dev_priv, false);
4821 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4823 struct drm_device *dev = crtc->dev;
4824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4825 struct drm_plane *p;
4826 int pipe = intel_crtc->pipe;
4828 intel_crtc_dpms_overlay_disable(intel_crtc);
4830 drm_for_each_plane_mask(p, dev, plane_mask)
4831 to_intel_plane(p)->disable_plane(p, crtc);
4834 * FIXME: Once we grow proper nuclear flip support out of this we need
4835 * to compute the mask of flip planes precisely. For the time being
4836 * consider this a flip to a NULL plane.
4838 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4841 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4843 struct drm_device *dev = crtc->dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846 struct intel_encoder *encoder;
4847 int pipe = intel_crtc->pipe;
4849 if (WARN_ON(intel_crtc->active))
4852 if (intel_crtc->config->has_pch_encoder)
4853 intel_prepare_shared_dpll(intel_crtc);
4855 if (intel_crtc->config->has_dp_encoder)
4856 intel_dp_set_m_n(intel_crtc, M1_N1);
4858 intel_set_pipe_timings(intel_crtc);
4860 if (intel_crtc->config->has_pch_encoder) {
4861 intel_cpu_transcoder_set_m_n(intel_crtc,
4862 &intel_crtc->config->fdi_m_n, NULL);
4865 ironlake_set_pipeconf(crtc);
4867 intel_crtc->active = true;
4869 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4870 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4872 for_each_encoder_on_crtc(dev, crtc, encoder)
4873 if (encoder->pre_enable)
4874 encoder->pre_enable(encoder);
4876 if (intel_crtc->config->has_pch_encoder) {
4877 /* Note: FDI PLL enabling _must_ be done before we enable the
4878 * cpu pipes, hence this is separate from all the other fdi/pch
4880 ironlake_fdi_pll_enable(intel_crtc);
4882 assert_fdi_tx_disabled(dev_priv, pipe);
4883 assert_fdi_rx_disabled(dev_priv, pipe);
4886 ironlake_pfit_enable(intel_crtc);
4889 * On ILK+ LUT must be loaded before the pipe is running but with
4892 intel_crtc_load_lut(crtc);
4894 intel_update_watermarks(crtc);
4895 intel_enable_pipe(intel_crtc);
4897 if (intel_crtc->config->has_pch_encoder)
4898 ironlake_pch_enable(crtc);
4900 assert_vblank_disabled(crtc);
4901 drm_crtc_vblank_on(crtc);
4903 for_each_encoder_on_crtc(dev, crtc, encoder)
4904 encoder->enable(encoder);
4906 if (HAS_PCH_CPT(dev))
4907 cpt_verify_modeset(dev, intel_crtc->pipe);
4910 /* IPS only exists on ULT machines and is tied to pipe A. */
4911 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4913 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4916 static void haswell_crtc_enable(struct drm_crtc *crtc)
4918 struct drm_device *dev = crtc->dev;
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921 struct intel_encoder *encoder;
4922 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4923 struct intel_crtc_state *pipe_config =
4924 to_intel_crtc_state(crtc->state);
4926 if (WARN_ON(intel_crtc->active))
4929 if (intel_crtc_to_shared_dpll(intel_crtc))
4930 intel_enable_shared_dpll(intel_crtc);
4932 if (intel_crtc->config->has_dp_encoder)
4933 intel_dp_set_m_n(intel_crtc, M1_N1);
4935 intel_set_pipe_timings(intel_crtc);
4937 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4938 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4939 intel_crtc->config->pixel_multiplier - 1);
4942 if (intel_crtc->config->has_pch_encoder) {
4943 intel_cpu_transcoder_set_m_n(intel_crtc,
4944 &intel_crtc->config->fdi_m_n, NULL);
4947 haswell_set_pipeconf(crtc);
4949 intel_set_pipe_csc(crtc);
4951 intel_crtc->active = true;
4953 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4954 for_each_encoder_on_crtc(dev, crtc, encoder)
4955 if (encoder->pre_enable)
4956 encoder->pre_enable(encoder);
4958 if (intel_crtc->config->has_pch_encoder) {
4959 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4961 dev_priv->display.fdi_link_train(crtc);
4964 intel_ddi_enable_pipe_clock(intel_crtc);
4966 if (INTEL_INFO(dev)->gen == 9)
4967 skylake_pfit_enable(intel_crtc);
4968 else if (INTEL_INFO(dev)->gen < 9)
4969 ironlake_pfit_enable(intel_crtc);
4971 MISSING_CASE(INTEL_INFO(dev)->gen);
4974 * On ILK+ LUT must be loaded before the pipe is running but with
4977 intel_crtc_load_lut(crtc);
4979 intel_ddi_set_pipe_settings(crtc);
4980 intel_ddi_enable_transcoder_func(crtc);
4982 intel_update_watermarks(crtc);
4983 intel_enable_pipe(intel_crtc);
4985 if (intel_crtc->config->has_pch_encoder)
4986 lpt_pch_enable(crtc);
4988 if (intel_crtc->config->dp_encoder_is_mst)
4989 intel_ddi_set_vc_payload_alloc(crtc, true);
4991 assert_vblank_disabled(crtc);
4992 drm_crtc_vblank_on(crtc);
4994 for_each_encoder_on_crtc(dev, crtc, encoder) {
4995 encoder->enable(encoder);
4996 intel_opregion_notify_encoder(encoder, true);
4999 /* If we change the relative order between pipe/planes enabling, we need
5000 * to change the workaround. */
5001 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5002 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5003 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5004 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5008 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5010 struct drm_device *dev = crtc->base.dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 int pipe = crtc->pipe;
5014 /* To avoid upsetting the power well on haswell only disable the pfit if
5015 * it's in use. The hw state code will make sure we get this right. */
5016 if (crtc->config->pch_pfit.enabled) {
5017 I915_WRITE(PF_CTL(pipe), 0);
5018 I915_WRITE(PF_WIN_POS(pipe), 0);
5019 I915_WRITE(PF_WIN_SZ(pipe), 0);
5023 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 struct intel_encoder *encoder;
5029 int pipe = intel_crtc->pipe;
5032 for_each_encoder_on_crtc(dev, crtc, encoder)
5033 encoder->disable(encoder);
5035 drm_crtc_vblank_off(crtc);
5036 assert_vblank_disabled(crtc);
5038 if (intel_crtc->config->has_pch_encoder)
5039 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5041 intel_disable_pipe(intel_crtc);
5043 ironlake_pfit_disable(intel_crtc);
5045 if (intel_crtc->config->has_pch_encoder)
5046 ironlake_fdi_disable(crtc);
5048 for_each_encoder_on_crtc(dev, crtc, encoder)
5049 if (encoder->post_disable)
5050 encoder->post_disable(encoder);
5052 if (intel_crtc->config->has_pch_encoder) {
5053 ironlake_disable_pch_transcoder(dev_priv, pipe);
5055 if (HAS_PCH_CPT(dev)) {
5056 /* disable TRANS_DP_CTL */
5057 reg = TRANS_DP_CTL(pipe);
5058 temp = I915_READ(reg);
5059 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5060 TRANS_DP_PORT_SEL_MASK);
5061 temp |= TRANS_DP_PORT_SEL_NONE;
5062 I915_WRITE(reg, temp);
5064 /* disable DPLL_SEL */
5065 temp = I915_READ(PCH_DPLL_SEL);
5066 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5067 I915_WRITE(PCH_DPLL_SEL, temp);
5070 ironlake_fdi_pll_disable(intel_crtc);
5073 intel_crtc->active = false;
5074 intel_update_watermarks(crtc);
5077 static void haswell_crtc_disable(struct drm_crtc *crtc)
5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082 struct intel_encoder *encoder;
5083 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5085 for_each_encoder_on_crtc(dev, crtc, encoder) {
5086 intel_opregion_notify_encoder(encoder, false);
5087 encoder->disable(encoder);
5090 drm_crtc_vblank_off(crtc);
5091 assert_vblank_disabled(crtc);
5093 if (intel_crtc->config->has_pch_encoder)
5094 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5096 intel_disable_pipe(intel_crtc);
5098 if (intel_crtc->config->dp_encoder_is_mst)
5099 intel_ddi_set_vc_payload_alloc(crtc, false);
5101 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5103 if (INTEL_INFO(dev)->gen == 9)
5104 skylake_scaler_disable(intel_crtc);
5105 else if (INTEL_INFO(dev)->gen < 9)
5106 ironlake_pfit_disable(intel_crtc);
5108 MISSING_CASE(INTEL_INFO(dev)->gen);
5110 intel_ddi_disable_pipe_clock(intel_crtc);
5112 if (intel_crtc->config->has_pch_encoder) {
5113 lpt_disable_pch_transcoder(dev_priv);
5114 intel_ddi_fdi_disable(crtc);
5117 for_each_encoder_on_crtc(dev, crtc, encoder)
5118 if (encoder->post_disable)
5119 encoder->post_disable(encoder);
5121 intel_crtc->active = false;
5122 intel_update_watermarks(crtc);
5125 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5127 struct drm_device *dev = crtc->base.dev;
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct intel_crtc_state *pipe_config = crtc->config;
5131 if (!pipe_config->gmch_pfit.control)
5135 * The panel fitter should only be adjusted whilst the pipe is disabled,
5136 * according to register description and PRM.
5138 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5139 assert_pipe_disabled(dev_priv, crtc->pipe);
5141 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5142 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5144 /* Border color in case we don't scale up to the full screen. Black by
5145 * default, change to something else for debugging. */
5146 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5149 static enum intel_display_power_domain port_to_power_domain(enum port port)
5154 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5156 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5158 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5160 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5163 return POWER_DOMAIN_PORT_OTHER;
5167 #define for_each_power_domain(domain, mask) \
5168 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5169 if ((1 << (domain)) & (mask))
5171 enum intel_display_power_domain
5172 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5174 struct drm_device *dev = intel_encoder->base.dev;
5175 struct intel_digital_port *intel_dig_port;
5177 switch (intel_encoder->type) {
5178 case INTEL_OUTPUT_UNKNOWN:
5179 /* Only DDI platforms should ever use this output type */
5180 WARN_ON_ONCE(!HAS_DDI(dev));
5181 case INTEL_OUTPUT_DISPLAYPORT:
5182 case INTEL_OUTPUT_HDMI:
5183 case INTEL_OUTPUT_EDP:
5184 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5185 return port_to_power_domain(intel_dig_port->port);
5186 case INTEL_OUTPUT_DP_MST:
5187 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5188 return port_to_power_domain(intel_dig_port->port);
5189 case INTEL_OUTPUT_ANALOG:
5190 return POWER_DOMAIN_PORT_CRT;
5191 case INTEL_OUTPUT_DSI:
5192 return POWER_DOMAIN_PORT_DSI;
5194 return POWER_DOMAIN_PORT_OTHER;
5198 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5200 struct drm_device *dev = crtc->dev;
5201 struct intel_encoder *intel_encoder;
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203 enum pipe pipe = intel_crtc->pipe;
5205 enum transcoder transcoder;
5207 if (!crtc->state->active)
5210 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5212 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5213 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5214 if (intel_crtc->config->pch_pfit.enabled ||
5215 intel_crtc->config->pch_pfit.force_thru)
5216 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5218 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5219 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5224 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5226 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 enum intel_display_power_domain domain;
5229 unsigned long domains, new_domains, old_domains;
5231 old_domains = intel_crtc->enabled_power_domains;
5232 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5234 domains = new_domains & ~old_domains;
5236 for_each_power_domain(domain, domains)
5237 intel_display_power_get(dev_priv, domain);
5239 return old_domains & ~new_domains;
5242 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5243 unsigned long domains)
5245 enum intel_display_power_domain domain;
5247 for_each_power_domain(domain, domains)
5248 intel_display_power_put(dev_priv, domain);
5251 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5253 struct drm_device *dev = state->dev;
5254 struct drm_i915_private *dev_priv = dev->dev_private;
5255 unsigned long put_domains[I915_MAX_PIPES] = {};
5256 struct drm_crtc_state *crtc_state;
5257 struct drm_crtc *crtc;
5260 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5261 if (needs_modeset(crtc->state))
5262 put_domains[to_intel_crtc(crtc)->pipe] =
5263 modeset_get_crtc_power_domains(crtc);
5266 if (dev_priv->display.modeset_commit_cdclk) {
5267 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5269 if (cdclk != dev_priv->cdclk_freq &&
5270 !WARN_ON(!state->allow_modeset))
5271 dev_priv->display.modeset_commit_cdclk(state);
5274 for (i = 0; i < I915_MAX_PIPES; i++)
5276 modeset_put_power_domains(dev_priv, put_domains[i]);
5279 static void intel_update_max_cdclk(struct drm_device *dev)
5281 struct drm_i915_private *dev_priv = dev->dev_private;
5283 if (IS_SKYLAKE(dev)) {
5284 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5286 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5287 dev_priv->max_cdclk_freq = 675000;
5288 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5289 dev_priv->max_cdclk_freq = 540000;
5290 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5291 dev_priv->max_cdclk_freq = 450000;
5293 dev_priv->max_cdclk_freq = 337500;
5294 } else if (IS_BROADWELL(dev)) {
5296 * FIXME with extra cooling we can allow
5297 * 540 MHz for ULX and 675 Mhz for ULT.
5298 * How can we know if extra cooling is
5299 * available? PCI ID, VTB, something else?
5301 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5302 dev_priv->max_cdclk_freq = 450000;
5303 else if (IS_BDW_ULX(dev))
5304 dev_priv->max_cdclk_freq = 450000;
5305 else if (IS_BDW_ULT(dev))
5306 dev_priv->max_cdclk_freq = 540000;
5308 dev_priv->max_cdclk_freq = 675000;
5309 } else if (IS_CHERRYVIEW(dev)) {
5310 dev_priv->max_cdclk_freq = 320000;
5311 } else if (IS_VALLEYVIEW(dev)) {
5312 dev_priv->max_cdclk_freq = 400000;
5314 /* otherwise assume cdclk is fixed */
5315 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5318 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5319 dev_priv->max_cdclk_freq);
5322 static void intel_update_cdclk(struct drm_device *dev)
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5326 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5327 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5328 dev_priv->cdclk_freq);
5331 * Program the gmbus_freq based on the cdclk frequency.
5332 * BSpec erroneously claims we should aim for 4MHz, but
5333 * in fact 1MHz is the correct frequency.
5335 if (IS_VALLEYVIEW(dev)) {
5337 * Program the gmbus_freq based on the cdclk frequency.
5338 * BSpec erroneously claims we should aim for 4MHz, but
5339 * in fact 1MHz is the correct frequency.
5341 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5344 if (dev_priv->max_cdclk_freq == 0)
5345 intel_update_max_cdclk(dev);
5348 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5350 struct drm_i915_private *dev_priv = dev->dev_private;
5353 uint32_t current_freq;
5356 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5357 switch (frequency) {
5359 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5360 ratio = BXT_DE_PLL_RATIO(60);
5363 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5364 ratio = BXT_DE_PLL_RATIO(60);
5367 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5368 ratio = BXT_DE_PLL_RATIO(60);
5371 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5372 ratio = BXT_DE_PLL_RATIO(60);
5375 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5376 ratio = BXT_DE_PLL_RATIO(65);
5380 * Bypass frequency with DE PLL disabled. Init ratio, divider
5381 * to suppress GCC warning.
5387 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5392 mutex_lock(&dev_priv->rps.hw_lock);
5393 /* Inform power controller of upcoming frequency change */
5394 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396 mutex_unlock(&dev_priv->rps.hw_lock);
5399 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5404 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5405 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5406 current_freq = current_freq * 500 + 1000;
5409 * DE PLL has to be disabled when
5410 * - setting to 19.2MHz (bypass, PLL isn't used)
5411 * - before setting to 624MHz (PLL needs toggling)
5412 * - before setting to any frequency from 624MHz (PLL needs toggling)
5414 if (frequency == 19200 || frequency == 624000 ||
5415 current_freq == 624000) {
5416 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420 DRM_ERROR("timout waiting for DE PLL unlock\n");
5423 if (frequency != 19200) {
5426 val = I915_READ(BXT_DE_PLL_CTL);
5427 val &= ~BXT_DE_PLL_RATIO_MASK;
5429 I915_WRITE(BXT_DE_PLL_CTL, val);
5431 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5434 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436 val = I915_READ(CDCLK_CTL);
5437 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5440 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5443 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5444 if (frequency >= 500000)
5445 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5448 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5449 val |= (frequency - 1000) / 500;
5450 I915_WRITE(CDCLK_CTL, val);
5453 mutex_lock(&dev_priv->rps.hw_lock);
5454 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5455 DIV_ROUND_UP(frequency, 25000));
5456 mutex_unlock(&dev_priv->rps.hw_lock);
5459 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5464 intel_update_cdclk(dev);
5467 void broxton_init_cdclk(struct drm_device *dev)
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5473 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5474 * or else the reset will hang because there is no PCH to respond.
5475 * Move the handshake programming to initialization sequence.
5476 * Previously was left up to BIOS.
5478 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5479 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5480 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482 /* Enable PG1 for cdclk */
5483 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485 /* check if cd clock is enabled */
5486 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5487 DRM_DEBUG_KMS("Display already initialized\n");
5493 * - The initial CDCLK needs to be read from VBT.
5494 * Need to make this change after VBT has changes for BXT.
5495 * - check if setting the max (or any) cdclk freq is really necessary
5496 * here, it belongs to modeset time
5498 broxton_set_cdclk(dev, 624000);
5500 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5501 POSTING_READ(DBUF_CTL);
5505 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5506 DRM_ERROR("DBuf power enable timeout!\n");
5509 void broxton_uninit_cdclk(struct drm_device *dev)
5511 struct drm_i915_private *dev_priv = dev->dev_private;
5513 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5514 POSTING_READ(DBUF_CTL);
5518 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5519 DRM_ERROR("DBuf power disable timeout!\n");
5521 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5522 broxton_set_cdclk(dev, 19200);
5524 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5527 static const struct skl_cdclk_entry {
5530 } skl_cdclk_frequencies[] = {
5531 { .freq = 308570, .vco = 8640 },
5532 { .freq = 337500, .vco = 8100 },
5533 { .freq = 432000, .vco = 8640 },
5534 { .freq = 450000, .vco = 8100 },
5535 { .freq = 540000, .vco = 8100 },
5536 { .freq = 617140, .vco = 8640 },
5537 { .freq = 675000, .vco = 8100 },
5540 static unsigned int skl_cdclk_decimal(unsigned int freq)
5542 return (freq - 1000) / 500;
5545 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5549 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5550 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552 if (e->freq == freq)
5560 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562 unsigned int min_freq;
5565 /* select the minimum CDCLK before enabling DPLL 0 */
5566 val = I915_READ(CDCLK_CTL);
5567 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5568 val |= CDCLK_FREQ_337_308;
5570 if (required_vco == 8640)
5575 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577 I915_WRITE(CDCLK_CTL, val);
5578 POSTING_READ(CDCLK_CTL);
5581 * We always enable DPLL0 with the lowest link rate possible, but still
5582 * taking into account the VCO required to operate the eDP panel at the
5583 * desired frequency. The usual DP link rates operate with a VCO of
5584 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5585 * The modeset code is responsible for the selection of the exact link
5586 * rate later on, with the constraint of choosing a frequency that
5587 * works with required_vco.
5589 val = I915_READ(DPLL_CTRL1);
5591 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5592 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5593 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5594 if (required_vco == 8640)
5595 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5598 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5601 I915_WRITE(DPLL_CTRL1, val);
5602 POSTING_READ(DPLL_CTRL1);
5604 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5607 DRM_ERROR("DPLL0 not locked\n");
5610 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5615 /* inform PCU we want to change CDCLK */
5616 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5617 mutex_lock(&dev_priv->rps.hw_lock);
5618 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5619 mutex_unlock(&dev_priv->rps.hw_lock);
5621 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5624 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5628 for (i = 0; i < 15; i++) {
5629 if (skl_cdclk_pcu_ready(dev_priv))
5637 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639 struct drm_device *dev = dev_priv->dev;
5640 u32 freq_select, pcu_ack;
5642 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5644 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5645 DRM_ERROR("failed to inform PCU about cdclk change\n");
5653 freq_select = CDCLK_FREQ_450_432;
5657 freq_select = CDCLK_FREQ_540;
5663 freq_select = CDCLK_FREQ_337_308;
5668 freq_select = CDCLK_FREQ_675_617;
5673 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5674 POSTING_READ(CDCLK_CTL);
5676 /* inform PCU of the change */
5677 mutex_lock(&dev_priv->rps.hw_lock);
5678 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5679 mutex_unlock(&dev_priv->rps.hw_lock);
5681 intel_update_cdclk(dev);
5684 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5686 /* disable DBUF power */
5687 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5688 POSTING_READ(DBUF_CTL);
5692 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5693 DRM_ERROR("DBuf power disable timeout\n");
5696 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5697 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5698 DRM_ERROR("Couldn't disable DPLL0\n");
5700 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5703 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5706 unsigned int required_vco;
5708 /* enable PCH reset handshake */
5709 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5710 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5712 /* enable PG1 and Misc I/O */
5713 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5715 /* DPLL0 not enabled (happens on early BIOS versions) */
5716 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5718 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5719 skl_dpll0_enable(dev_priv, required_vco);
5722 /* set CDCLK to the frequency the BIOS chose */
5723 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725 /* enable DBUF power */
5726 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5727 POSTING_READ(DBUF_CTL);
5731 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5732 DRM_ERROR("DBuf power enable timeout\n");
5735 /* returns HPLL frequency in kHz */
5736 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5738 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5740 /* Obtain SKU information */
5741 mutex_lock(&dev_priv->sb_lock);
5742 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5743 CCK_FUSE_HPLL_FREQ_MASK;
5744 mutex_unlock(&dev_priv->sb_lock);
5746 return vco_freq[hpll_freq] * 1000;
5749 /* Adjust CDclk dividers to allow high res or save power if possible */
5750 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5755 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5756 != dev_priv->cdclk_freq);
5758 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5760 else if (cdclk == 266667)
5765 mutex_lock(&dev_priv->rps.hw_lock);
5766 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5767 val &= ~DSPFREQGUAR_MASK;
5768 val |= (cmd << DSPFREQGUAR_SHIFT);
5769 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5770 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5771 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5773 DRM_ERROR("timed out waiting for CDclk change\n");
5775 mutex_unlock(&dev_priv->rps.hw_lock);
5777 mutex_lock(&dev_priv->sb_lock);
5779 if (cdclk == 400000) {
5782 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5784 /* adjust cdclk divider */
5785 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5786 val &= ~DISPLAY_FREQUENCY_VALUES;
5788 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5790 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5791 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5793 DRM_ERROR("timed out waiting for CDclk change\n");
5796 /* adjust self-refresh exit latency value */
5797 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5801 * For high bandwidth configs, we set a higher latency in the bunit
5802 * so that the core display fetch happens in time to avoid underruns.
5804 if (cdclk == 400000)
5805 val |= 4500 / 250; /* 4.5 usec */
5807 val |= 3000 / 250; /* 3.0 usec */
5808 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5810 mutex_unlock(&dev_priv->sb_lock);
5812 intel_update_cdclk(dev);
5815 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5820 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5821 != dev_priv->cdclk_freq);
5830 MISSING_CASE(cdclk);
5835 * Specs are full of misinformation, but testing on actual
5836 * hardware has shown that we just need to write the desired
5837 * CCK divider into the Punit register.
5839 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5841 mutex_lock(&dev_priv->rps.hw_lock);
5842 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5843 val &= ~DSPFREQGUAR_MASK_CHV;
5844 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5845 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5846 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5847 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5849 DRM_ERROR("timed out waiting for CDclk change\n");
5851 mutex_unlock(&dev_priv->rps.hw_lock);
5853 intel_update_cdclk(dev);
5856 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5859 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5860 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5863 * Really only a few cases to deal with, as only 4 CDclks are supported:
5866 * 320/333MHz (depends on HPLL freq)
5868 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5869 * of the lower bin and adjust if needed.
5871 * We seem to get an unstable or solid color picture at 200MHz.
5872 * Not sure what's wrong. For now use 200MHz only when all pipes
5875 if (!IS_CHERRYVIEW(dev_priv) &&
5876 max_pixclk > freq_320*limit/100)
5878 else if (max_pixclk > 266667*limit/100)
5880 else if (max_pixclk > 0)
5886 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5891 * - remove the guardband, it's not needed on BXT
5892 * - set 19.2MHz bypass frequency if there are no active pipes
5894 if (max_pixclk > 576000*9/10)
5896 else if (max_pixclk > 384000*9/10)
5898 else if (max_pixclk > 288000*9/10)
5900 else if (max_pixclk > 144000*9/10)
5906 /* Compute the max pixel clock for new configuration. Uses atomic state if
5907 * that's non-NULL, look at current state otherwise. */
5908 static int intel_mode_max_pixclk(struct drm_device *dev,
5909 struct drm_atomic_state *state)
5911 struct intel_crtc *intel_crtc;
5912 struct intel_crtc_state *crtc_state;
5915 for_each_intel_crtc(dev, intel_crtc) {
5916 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5917 if (IS_ERR(crtc_state))
5918 return PTR_ERR(crtc_state);
5920 if (!crtc_state->base.enable)
5923 max_pixclk = max(max_pixclk,
5924 crtc_state->base.adjusted_mode.crtc_clock);
5930 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5932 struct drm_device *dev = state->dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 int max_pixclk = intel_mode_max_pixclk(dev, state);
5939 to_intel_atomic_state(state)->cdclk =
5940 valleyview_calc_cdclk(dev_priv, max_pixclk);
5945 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5947 struct drm_device *dev = state->dev;
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949 int max_pixclk = intel_mode_max_pixclk(dev, state);
5954 to_intel_atomic_state(state)->cdclk =
5955 broxton_calc_cdclk(dev_priv, max_pixclk);
5960 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5962 unsigned int credits, default_credits;
5964 if (IS_CHERRYVIEW(dev_priv))
5965 default_credits = PFI_CREDIT(12);
5967 default_credits = PFI_CREDIT(8);
5969 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5970 /* CHV suggested value is 31 or 63 */
5971 if (IS_CHERRYVIEW(dev_priv))
5972 credits = PFI_CREDIT_63;
5974 credits = PFI_CREDIT(15);
5976 credits = default_credits;
5980 * WA - write default credits before re-programming
5981 * FIXME: should we also set the resend bit here?
5983 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5986 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5987 credits | PFI_CREDIT_RESEND);
5990 * FIXME is this guaranteed to clear
5991 * immediately or should we poll for it?
5993 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5996 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5998 struct drm_device *dev = old_state->dev;
5999 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6003 * FIXME: We can end up here with all power domains off, yet
6004 * with a CDCLK frequency other than the minimum. To account
6005 * for this take the PIPE-A power domain, which covers the HW
6006 * blocks needed for the following programming. This can be
6007 * removed once it's guaranteed that we get here either with
6008 * the minimum CDCLK set, or the required power domains
6011 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6013 if (IS_CHERRYVIEW(dev))
6014 cherryview_set_cdclk(dev, req_cdclk);
6016 valleyview_set_cdclk(dev, req_cdclk);
6018 vlv_program_pfi_credits(dev_priv);
6020 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6023 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6025 struct drm_device *dev = crtc->dev;
6026 struct drm_i915_private *dev_priv = to_i915(dev);
6027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6028 struct intel_encoder *encoder;
6029 int pipe = intel_crtc->pipe;
6032 if (WARN_ON(intel_crtc->active))
6035 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6038 if (IS_CHERRYVIEW(dev))
6039 chv_prepare_pll(intel_crtc, intel_crtc->config);
6041 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6044 if (intel_crtc->config->has_dp_encoder)
6045 intel_dp_set_m_n(intel_crtc, M1_N1);
6047 intel_set_pipe_timings(intel_crtc);
6049 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6052 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6053 I915_WRITE(CHV_CANVAS(pipe), 0);
6056 i9xx_set_pipeconf(intel_crtc);
6058 intel_crtc->active = true;
6060 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6062 for_each_encoder_on_crtc(dev, crtc, encoder)
6063 if (encoder->pre_pll_enable)
6064 encoder->pre_pll_enable(encoder);
6067 if (IS_CHERRYVIEW(dev))
6068 chv_enable_pll(intel_crtc, intel_crtc->config);
6070 vlv_enable_pll(intel_crtc, intel_crtc->config);
6073 for_each_encoder_on_crtc(dev, crtc, encoder)
6074 if (encoder->pre_enable)
6075 encoder->pre_enable(encoder);
6077 i9xx_pfit_enable(intel_crtc);
6079 intel_crtc_load_lut(crtc);
6081 intel_enable_pipe(intel_crtc);
6083 assert_vblank_disabled(crtc);
6084 drm_crtc_vblank_on(crtc);
6086 for_each_encoder_on_crtc(dev, crtc, encoder)
6087 encoder->enable(encoder);
6090 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6092 struct drm_device *dev = crtc->base.dev;
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6095 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6096 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6099 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6101 struct drm_device *dev = crtc->dev;
6102 struct drm_i915_private *dev_priv = to_i915(dev);
6103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6104 struct intel_encoder *encoder;
6105 int pipe = intel_crtc->pipe;
6107 if (WARN_ON(intel_crtc->active))
6110 i9xx_set_pll_dividers(intel_crtc);
6112 if (intel_crtc->config->has_dp_encoder)
6113 intel_dp_set_m_n(intel_crtc, M1_N1);
6115 intel_set_pipe_timings(intel_crtc);
6117 i9xx_set_pipeconf(intel_crtc);
6119 intel_crtc->active = true;
6122 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6124 for_each_encoder_on_crtc(dev, crtc, encoder)
6125 if (encoder->pre_enable)
6126 encoder->pre_enable(encoder);
6128 i9xx_enable_pll(intel_crtc);
6130 i9xx_pfit_enable(intel_crtc);
6132 intel_crtc_load_lut(crtc);
6134 intel_update_watermarks(crtc);
6135 intel_enable_pipe(intel_crtc);
6137 assert_vblank_disabled(crtc);
6138 drm_crtc_vblank_on(crtc);
6140 for_each_encoder_on_crtc(dev, crtc, encoder)
6141 encoder->enable(encoder);
6144 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6146 struct drm_device *dev = crtc->base.dev;
6147 struct drm_i915_private *dev_priv = dev->dev_private;
6149 if (!crtc->config->gmch_pfit.control)
6152 assert_pipe_disabled(dev_priv, crtc->pipe);
6154 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6155 I915_READ(PFIT_CONTROL));
6156 I915_WRITE(PFIT_CONTROL, 0);
6159 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6161 struct drm_device *dev = crtc->dev;
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164 struct intel_encoder *encoder;
6165 int pipe = intel_crtc->pipe;
6168 * On gen2 planes are double buffered but the pipe isn't, so we must
6169 * wait for planes to fully turn off before disabling the pipe.
6170 * We also need to wait on all gmch platforms because of the
6171 * self-refresh mode constraint explained above.
6173 intel_wait_for_vblank(dev, pipe);
6175 for_each_encoder_on_crtc(dev, crtc, encoder)
6176 encoder->disable(encoder);
6178 drm_crtc_vblank_off(crtc);
6179 assert_vblank_disabled(crtc);
6181 intel_disable_pipe(intel_crtc);
6183 i9xx_pfit_disable(intel_crtc);
6185 for_each_encoder_on_crtc(dev, crtc, encoder)
6186 if (encoder->post_disable)
6187 encoder->post_disable(encoder);
6189 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6190 if (IS_CHERRYVIEW(dev))
6191 chv_disable_pll(dev_priv, pipe);
6192 else if (IS_VALLEYVIEW(dev))
6193 vlv_disable_pll(dev_priv, pipe);
6195 i9xx_disable_pll(intel_crtc);
6199 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6201 intel_crtc->active = false;
6202 intel_update_watermarks(crtc);
6205 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6209 enum intel_display_power_domain domain;
6210 unsigned long domains;
6212 if (!intel_crtc->active)
6215 if (to_intel_plane_state(crtc->primary->state)->visible) {
6216 intel_crtc_wait_for_pending_flips(crtc);
6217 intel_pre_disable_primary(crtc);
6220 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6221 dev_priv->display.crtc_disable(crtc);
6222 intel_disable_shared_dpll(intel_crtc);
6224 domains = intel_crtc->enabled_power_domains;
6225 for_each_power_domain(domain, domains)
6226 intel_display_power_put(dev_priv, domain);
6227 intel_crtc->enabled_power_domains = 0;
6231 * turn all crtc's off, but do not adjust state
6232 * This has to be paired with a call to intel_modeset_setup_hw_state.
6234 int intel_display_suspend(struct drm_device *dev)
6236 struct drm_mode_config *config = &dev->mode_config;
6237 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6238 struct drm_atomic_state *state;
6239 struct drm_crtc *crtc;
6240 unsigned crtc_mask = 0;
6246 lockdep_assert_held(&ctx->ww_ctx);
6247 state = drm_atomic_state_alloc(dev);
6248 if (WARN_ON(!state))
6251 state->acquire_ctx = ctx;
6252 state->allow_modeset = true;
6254 for_each_crtc(dev, crtc) {
6255 struct drm_crtc_state *crtc_state =
6256 drm_atomic_get_crtc_state(state, crtc);
6258 ret = PTR_ERR_OR_ZERO(crtc_state);
6262 if (!crtc_state->active)
6265 crtc_state->active = false;
6266 crtc_mask |= 1 << drm_crtc_index(crtc);
6270 ret = drm_atomic_commit(state);
6273 for_each_crtc(dev, crtc)
6274 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6275 crtc->state->active = true;
6283 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6284 drm_atomic_state_free(state);
6288 void intel_encoder_destroy(struct drm_encoder *encoder)
6290 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6292 drm_encoder_cleanup(encoder);
6293 kfree(intel_encoder);
6296 /* Cross check the actual hw state with our own modeset state tracking (and it's
6297 * internal consistency). */
6298 static void intel_connector_check_state(struct intel_connector *connector)
6300 struct drm_crtc *crtc = connector->base.state->crtc;
6302 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6303 connector->base.base.id,
6304 connector->base.name);
6306 if (connector->get_hw_state(connector)) {
6307 struct drm_encoder *encoder = &connector->encoder->base;
6308 struct drm_connector_state *conn_state = connector->base.state;
6310 I915_STATE_WARN(!crtc,
6311 "connector enabled without attached crtc\n");
6316 I915_STATE_WARN(!crtc->state->active,
6317 "connector is active, but attached crtc isn't\n");
6322 I915_STATE_WARN(conn_state->best_encoder != encoder,
6323 "atomic encoder doesn't match attached encoder\n");
6325 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6326 "attached encoder crtc differs from connector crtc\n");
6328 I915_STATE_WARN(crtc && crtc->state->active,
6329 "attached crtc is active, but connector isn't\n");
6330 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6331 "best encoder set without crtc!\n");
6335 int intel_connector_init(struct intel_connector *connector)
6337 struct drm_connector_state *connector_state;
6339 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6340 if (!connector_state)
6343 connector->base.state = connector_state;
6347 struct intel_connector *intel_connector_alloc(void)
6349 struct intel_connector *connector;
6351 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6355 if (intel_connector_init(connector) < 0) {
6363 /* Simple connector->get_hw_state implementation for encoders that support only
6364 * one connector and no cloning and hence the encoder state determines the state
6365 * of the connector. */
6366 bool intel_connector_get_hw_state(struct intel_connector *connector)
6369 struct intel_encoder *encoder = connector->encoder;
6371 return encoder->get_hw_state(encoder, &pipe);
6374 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6376 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6377 return crtc_state->fdi_lanes;
6382 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6383 struct intel_crtc_state *pipe_config)
6385 struct drm_atomic_state *state = pipe_config->base.state;
6386 struct intel_crtc *other_crtc;
6387 struct intel_crtc_state *other_crtc_state;
6389 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6390 pipe_name(pipe), pipe_config->fdi_lanes);
6391 if (pipe_config->fdi_lanes > 4) {
6392 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6393 pipe_name(pipe), pipe_config->fdi_lanes);
6397 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6398 if (pipe_config->fdi_lanes > 2) {
6399 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6400 pipe_config->fdi_lanes);
6407 if (INTEL_INFO(dev)->num_pipes == 2)
6410 /* Ivybridge 3 pipe is really complicated */
6415 if (pipe_config->fdi_lanes <= 2)
6418 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6420 intel_atomic_get_crtc_state(state, other_crtc);
6421 if (IS_ERR(other_crtc_state))
6422 return PTR_ERR(other_crtc_state);
6424 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6425 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6426 pipe_name(pipe), pipe_config->fdi_lanes);
6431 if (pipe_config->fdi_lanes > 2) {
6432 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6433 pipe_name(pipe), pipe_config->fdi_lanes);
6437 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6439 intel_atomic_get_crtc_state(state, other_crtc);
6440 if (IS_ERR(other_crtc_state))
6441 return PTR_ERR(other_crtc_state);
6443 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6444 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6454 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6455 struct intel_crtc_state *pipe_config)
6457 struct drm_device *dev = intel_crtc->base.dev;
6458 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6459 int lane, link_bw, fdi_dotclock, ret;
6460 bool needs_recompute = false;
6463 /* FDI is a binary signal running at ~2.7GHz, encoding
6464 * each output octet as 10 bits. The actual frequency
6465 * is stored as a divider into a 100MHz clock, and the
6466 * mode pixel clock is stored in units of 1KHz.
6467 * Hence the bw of each lane in terms of the mode signal
6470 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6472 fdi_dotclock = adjusted_mode->crtc_clock;
6474 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6475 pipe_config->pipe_bpp);
6477 pipe_config->fdi_lanes = lane;
6479 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6480 link_bw, &pipe_config->fdi_m_n);
6482 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6483 intel_crtc->pipe, pipe_config);
6484 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6485 pipe_config->pipe_bpp -= 2*3;
6486 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6487 pipe_config->pipe_bpp);
6488 needs_recompute = true;
6489 pipe_config->bw_constrained = true;
6494 if (needs_recompute)
6500 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6501 struct intel_crtc_state *pipe_config)
6503 if (pipe_config->pipe_bpp > 24)
6506 /* HSW can handle pixel rate up to cdclk? */
6507 if (IS_HASWELL(dev_priv->dev))
6511 * We compare against max which means we must take
6512 * the increased cdclk requirement into account when
6513 * calculating the new cdclk.
6515 * Should measure whether using a lower cdclk w/o IPS
6517 return ilk_pipe_pixel_rate(pipe_config) <=
6518 dev_priv->max_cdclk_freq * 95 / 100;
6521 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6522 struct intel_crtc_state *pipe_config)
6524 struct drm_device *dev = crtc->base.dev;
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6527 pipe_config->ips_enabled = i915.enable_ips &&
6528 hsw_crtc_supports_ips(crtc) &&
6529 pipe_config_supports_ips(dev_priv, pipe_config);
6532 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6533 struct intel_crtc_state *pipe_config)
6535 struct drm_device *dev = crtc->base.dev;
6536 struct drm_i915_private *dev_priv = dev->dev_private;
6537 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6539 /* FIXME should check pixel clock limits on all platforms */
6540 if (INTEL_INFO(dev)->gen < 4) {
6541 int clock_limit = dev_priv->max_cdclk_freq;
6544 * Enable pixel doubling when the dot clock
6545 * is > 90% of the (display) core speed.
6547 * GDG double wide on either pipe,
6548 * otherwise pipe A only.
6550 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6551 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6553 pipe_config->double_wide = true;
6556 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6561 * Pipe horizontal size must be even in:
6563 * - LVDS dual channel mode
6564 * - Double wide pipe
6566 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6567 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6568 pipe_config->pipe_src_w &= ~1;
6570 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6571 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6573 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6574 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6578 hsw_compute_ips_config(crtc, pipe_config);
6580 if (pipe_config->has_pch_encoder)
6581 return ironlake_fdi_compute_config(crtc, pipe_config);
6586 static int skylake_get_display_clock_speed(struct drm_device *dev)
6588 struct drm_i915_private *dev_priv = to_i915(dev);
6589 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6590 uint32_t cdctl = I915_READ(CDCLK_CTL);
6593 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6594 return 24000; /* 24MHz is the cd freq with NSSC ref */
6596 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6599 linkrate = (I915_READ(DPLL_CTRL1) &
6600 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6602 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6603 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6605 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6606 case CDCLK_FREQ_450_432:
6608 case CDCLK_FREQ_337_308:
6610 case CDCLK_FREQ_675_617:
6613 WARN(1, "Unknown cd freq selection\n");
6617 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6618 case CDCLK_FREQ_450_432:
6620 case CDCLK_FREQ_337_308:
6622 case CDCLK_FREQ_675_617:
6625 WARN(1, "Unknown cd freq selection\n");
6629 /* error case, do as if DPLL0 isn't enabled */
6633 static int broxton_get_display_clock_speed(struct drm_device *dev)
6635 struct drm_i915_private *dev_priv = to_i915(dev);
6636 uint32_t cdctl = I915_READ(CDCLK_CTL);
6637 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6638 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6641 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6644 cdclk = 19200 * pll_ratio / 2;
6646 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6647 case BXT_CDCLK_CD2X_DIV_SEL_1:
6648 return cdclk; /* 576MHz or 624MHz */
6649 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6650 return cdclk * 2 / 3; /* 384MHz */
6651 case BXT_CDCLK_CD2X_DIV_SEL_2:
6652 return cdclk / 2; /* 288MHz */
6653 case BXT_CDCLK_CD2X_DIV_SEL_4:
6654 return cdclk / 4; /* 144MHz */
6657 /* error case, do as if DE PLL isn't enabled */
6661 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 uint32_t lcpll = I915_READ(LCPLL_CTL);
6665 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6667 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6669 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6671 else if (freq == LCPLL_CLK_FREQ_450)
6673 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6675 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6681 static int haswell_get_display_clock_speed(struct drm_device *dev)
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684 uint32_t lcpll = I915_READ(LCPLL_CTL);
6685 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6687 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6689 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6691 else if (freq == LCPLL_CLK_FREQ_450)
6693 else if (IS_HSW_ULT(dev))
6699 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6705 if (dev_priv->hpll_freq == 0)
6706 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6708 mutex_lock(&dev_priv->sb_lock);
6709 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6710 mutex_unlock(&dev_priv->sb_lock);
6712 divider = val & DISPLAY_FREQUENCY_VALUES;
6714 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6715 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6716 "cdclk change in progress\n");
6718 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6721 static int ilk_get_display_clock_speed(struct drm_device *dev)
6726 static int i945_get_display_clock_speed(struct drm_device *dev)
6731 static int i915_get_display_clock_speed(struct drm_device *dev)
6736 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6741 static int pnv_get_display_clock_speed(struct drm_device *dev)
6745 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6747 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6748 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6750 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6752 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6754 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6757 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6758 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6760 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6765 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6769 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6771 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6774 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6775 case GC_DISPLAY_CLOCK_333_MHZ:
6778 case GC_DISPLAY_CLOCK_190_200_MHZ:
6784 static int i865_get_display_clock_speed(struct drm_device *dev)
6789 static int i85x_get_display_clock_speed(struct drm_device *dev)
6794 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6795 * encoding is different :(
6796 * FIXME is this the right way to detect 852GM/852GMV?
6798 if (dev->pdev->revision == 0x1)
6801 pci_bus_read_config_word(dev->pdev->bus,
6802 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6804 /* Assume that the hardware is in the high speed state. This
6805 * should be the default.
6807 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6808 case GC_CLOCK_133_200:
6809 case GC_CLOCK_133_200_2:
6810 case GC_CLOCK_100_200:
6812 case GC_CLOCK_166_250:
6814 case GC_CLOCK_100_133:
6816 case GC_CLOCK_133_266:
6817 case GC_CLOCK_133_266_2:
6818 case GC_CLOCK_166_266:
6822 /* Shouldn't happen */
6826 static int i830_get_display_clock_speed(struct drm_device *dev)
6831 static unsigned int intel_hpll_vco(struct drm_device *dev)
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6834 static const unsigned int blb_vco[8] = {
6841 static const unsigned int pnv_vco[8] = {
6848 static const unsigned int cl_vco[8] = {
6857 static const unsigned int elk_vco[8] = {
6863 static const unsigned int ctg_vco[8] = {
6871 const unsigned int *vco_table;
6875 /* FIXME other chipsets? */
6877 vco_table = ctg_vco;
6878 else if (IS_G4X(dev))
6879 vco_table = elk_vco;
6880 else if (IS_CRESTLINE(dev))
6882 else if (IS_PINEVIEW(dev))
6883 vco_table = pnv_vco;
6884 else if (IS_G33(dev))
6885 vco_table = blb_vco;
6889 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6891 vco = vco_table[tmp & 0x7];
6893 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6895 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6900 static int gm45_get_display_clock_speed(struct drm_device *dev)
6902 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6905 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6907 cdclk_sel = (tmp >> 12) & 0x1;
6913 return cdclk_sel ? 333333 : 222222;
6915 return cdclk_sel ? 320000 : 228571;
6917 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6922 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6924 static const uint8_t div_3200[] = { 16, 10, 8 };
6925 static const uint8_t div_4000[] = { 20, 12, 10 };
6926 static const uint8_t div_5333[] = { 24, 16, 14 };
6927 const uint8_t *div_table;
6928 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6931 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6933 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6935 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6940 div_table = div_3200;
6943 div_table = div_4000;
6946 div_table = div_5333;
6952 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6955 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6959 static int g33_get_display_clock_speed(struct drm_device *dev)
6961 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6962 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6963 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6964 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6965 const uint8_t *div_table;
6966 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6969 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6971 cdclk_sel = (tmp >> 4) & 0x7;
6973 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6978 div_table = div_3200;
6981 div_table = div_4000;
6984 div_table = div_4800;
6987 div_table = div_5333;
6993 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6996 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7001 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7003 while (*num > DATA_LINK_M_N_MASK ||
7004 *den > DATA_LINK_M_N_MASK) {
7010 static void compute_m_n(unsigned int m, unsigned int n,
7011 uint32_t *ret_m, uint32_t *ret_n)
7013 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7014 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7015 intel_reduce_m_n_ratio(ret_m, ret_n);
7019 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7020 int pixel_clock, int link_clock,
7021 struct intel_link_m_n *m_n)
7025 compute_m_n(bits_per_pixel * pixel_clock,
7026 link_clock * nlanes * 8,
7027 &m_n->gmch_m, &m_n->gmch_n);
7029 compute_m_n(pixel_clock, link_clock,
7030 &m_n->link_m, &m_n->link_n);
7033 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7035 if (i915.panel_use_ssc >= 0)
7036 return i915.panel_use_ssc != 0;
7037 return dev_priv->vbt.lvds_use_ssc
7038 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7041 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7044 struct drm_device *dev = crtc_state->base.crtc->dev;
7045 struct drm_i915_private *dev_priv = dev->dev_private;
7048 WARN_ON(!crtc_state->base.state);
7050 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7052 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7053 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7054 refclk = dev_priv->vbt.lvds_ssc_freq;
7055 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7056 } else if (!IS_GEN2(dev)) {
7065 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7067 return (1 << dpll->n) << 16 | dpll->m2;
7070 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7072 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7075 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7076 struct intel_crtc_state *crtc_state,
7077 intel_clock_t *reduced_clock)
7079 struct drm_device *dev = crtc->base.dev;
7082 if (IS_PINEVIEW(dev)) {
7083 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7085 fp2 = pnv_dpll_compute_fp(reduced_clock);
7087 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7089 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7092 crtc_state->dpll_hw_state.fp0 = fp;
7094 crtc->lowfreq_avail = false;
7095 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7097 crtc_state->dpll_hw_state.fp1 = fp2;
7098 crtc->lowfreq_avail = true;
7100 crtc_state->dpll_hw_state.fp1 = fp;
7104 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7110 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7111 * and set it to a reasonable value instead.
7113 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7114 reg_val &= 0xffffff00;
7115 reg_val |= 0x00000030;
7116 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7118 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7119 reg_val &= 0x8cffffff;
7120 reg_val = 0x8c000000;
7121 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7123 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7124 reg_val &= 0xffffff00;
7125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7127 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7128 reg_val &= 0x00ffffff;
7129 reg_val |= 0xb0000000;
7130 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7133 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7134 struct intel_link_m_n *m_n)
7136 struct drm_device *dev = crtc->base.dev;
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 int pipe = crtc->pipe;
7140 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7141 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7142 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7143 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7147 struct intel_link_m_n *m_n,
7148 struct intel_link_m_n *m2_n2)
7150 struct drm_device *dev = crtc->base.dev;
7151 struct drm_i915_private *dev_priv = dev->dev_private;
7152 int pipe = crtc->pipe;
7153 enum transcoder transcoder = crtc->config->cpu_transcoder;
7155 if (INTEL_INFO(dev)->gen >= 5) {
7156 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7157 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7158 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7159 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7160 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7161 * for gen < 8) and if DRRS is supported (to make sure the
7162 * registers are not unnecessarily accessed).
7164 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7165 crtc->config->has_drrs) {
7166 I915_WRITE(PIPE_DATA_M2(transcoder),
7167 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7168 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7169 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7170 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7173 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7174 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7175 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7176 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7180 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7182 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7185 dp_m_n = &crtc->config->dp_m_n;
7186 dp_m2_n2 = &crtc->config->dp_m2_n2;
7187 } else if (m_n == M2_N2) {
7190 * M2_N2 registers are not supported. Hence m2_n2 divider value
7191 * needs to be programmed into M1_N1.
7193 dp_m_n = &crtc->config->dp_m2_n2;
7195 DRM_ERROR("Unsupported divider value\n");
7199 if (crtc->config->has_pch_encoder)
7200 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7202 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7205 static void vlv_compute_dpll(struct intel_crtc *crtc,
7206 struct intel_crtc_state *pipe_config)
7211 * Enable DPIO clock input. We should never disable the reference
7212 * clock for pipe B, since VGA hotplug / manual detection depends
7215 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7216 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7217 /* We should never disable this, set it here for state tracking */
7218 if (crtc->pipe == PIPE_B)
7219 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7220 dpll |= DPLL_VCO_ENABLE;
7221 pipe_config->dpll_hw_state.dpll = dpll;
7223 dpll_md = (pipe_config->pixel_multiplier - 1)
7224 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7225 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7228 static void vlv_prepare_pll(struct intel_crtc *crtc,
7229 const struct intel_crtc_state *pipe_config)
7231 struct drm_device *dev = crtc->base.dev;
7232 struct drm_i915_private *dev_priv = dev->dev_private;
7233 int pipe = crtc->pipe;
7235 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7236 u32 coreclk, reg_val;
7238 mutex_lock(&dev_priv->sb_lock);
7240 bestn = pipe_config->dpll.n;
7241 bestm1 = pipe_config->dpll.m1;
7242 bestm2 = pipe_config->dpll.m2;
7243 bestp1 = pipe_config->dpll.p1;
7244 bestp2 = pipe_config->dpll.p2;
7246 /* See eDP HDMI DPIO driver vbios notes doc */
7248 /* PLL B needs special handling */
7250 vlv_pllb_recal_opamp(dev_priv, pipe);
7252 /* Set up Tx target for periodic Rcomp update */
7253 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7255 /* Disable target IRef on PLL */
7256 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7257 reg_val &= 0x00ffffff;
7258 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7260 /* Disable fast lock */
7261 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7263 /* Set idtafcrecal before PLL is enabled */
7264 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7265 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7266 mdiv |= ((bestn << DPIO_N_SHIFT));
7267 mdiv |= (1 << DPIO_K_SHIFT);
7270 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7271 * but we don't support that).
7272 * Note: don't use the DAC post divider as it seems unstable.
7274 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7277 mdiv |= DPIO_ENABLE_CALIBRATION;
7278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7280 /* Set HBR and RBR LPF coefficients */
7281 if (pipe_config->port_clock == 162000 ||
7282 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7283 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7290 if (pipe_config->has_dp_encoder) {
7291 /* Use SSC source */
7293 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7298 } else { /* HDMI or VGA */
7299 /* Use bend source */
7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7308 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7309 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7310 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7311 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7312 coreclk |= 0x01000000;
7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7316 mutex_unlock(&dev_priv->sb_lock);
7319 static void chv_compute_dpll(struct intel_crtc *crtc,
7320 struct intel_crtc_state *pipe_config)
7322 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7323 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7325 if (crtc->pipe != PIPE_A)
7326 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7328 pipe_config->dpll_hw_state.dpll_md =
7329 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7332 static void chv_prepare_pll(struct intel_crtc *crtc,
7333 const struct intel_crtc_state *pipe_config)
7335 struct drm_device *dev = crtc->base.dev;
7336 struct drm_i915_private *dev_priv = dev->dev_private;
7337 int pipe = crtc->pipe;
7338 int dpll_reg = DPLL(crtc->pipe);
7339 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7340 u32 loopfilter, tribuf_calcntr;
7341 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7345 bestn = pipe_config->dpll.n;
7346 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7347 bestm1 = pipe_config->dpll.m1;
7348 bestm2 = pipe_config->dpll.m2 >> 22;
7349 bestp1 = pipe_config->dpll.p1;
7350 bestp2 = pipe_config->dpll.p2;
7351 vco = pipe_config->dpll.vco;
7356 * Enable Refclk and SSC
7358 I915_WRITE(dpll_reg,
7359 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7361 mutex_lock(&dev_priv->sb_lock);
7363 /* p1 and p2 divider */
7364 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7365 5 << DPIO_CHV_S1_DIV_SHIFT |
7366 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7367 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7368 1 << DPIO_CHV_K_DIV_SHIFT);
7370 /* Feedback post-divider - m2 */
7371 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7373 /* Feedback refclk divider - n and m1 */
7374 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7375 DPIO_CHV_M1_DIV_BY_2 |
7376 1 << DPIO_CHV_N_DIV_SHIFT);
7378 /* M2 fraction division */
7380 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7382 /* M2 fraction division enable */
7383 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7384 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7385 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7387 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7388 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7390 /* Program digital lock detect threshold */
7391 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7392 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7393 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7394 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7396 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7397 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7400 if (vco == 5400000) {
7401 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7402 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7403 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7404 tribuf_calcntr = 0x9;
7405 } else if (vco <= 6200000) {
7406 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7407 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7408 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7409 tribuf_calcntr = 0x9;
7410 } else if (vco <= 6480000) {
7411 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7412 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7413 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7414 tribuf_calcntr = 0x8;
7416 /* Not supported. Apply the same limits as in the max case */
7417 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7418 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7419 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7422 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7424 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7425 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7426 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7427 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7430 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7431 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7434 mutex_unlock(&dev_priv->sb_lock);
7438 * vlv_force_pll_on - forcibly enable just the PLL
7439 * @dev_priv: i915 private structure
7440 * @pipe: pipe PLL to enable
7441 * @dpll: PLL configuration
7443 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7444 * in cases where we need the PLL enabled even when @pipe is not going to
7447 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7448 const struct dpll *dpll)
7450 struct intel_crtc *crtc =
7451 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7452 struct intel_crtc_state pipe_config = {
7453 .base.crtc = &crtc->base,
7454 .pixel_multiplier = 1,
7458 if (IS_CHERRYVIEW(dev)) {
7459 chv_compute_dpll(crtc, &pipe_config);
7460 chv_prepare_pll(crtc, &pipe_config);
7461 chv_enable_pll(crtc, &pipe_config);
7463 vlv_compute_dpll(crtc, &pipe_config);
7464 vlv_prepare_pll(crtc, &pipe_config);
7465 vlv_enable_pll(crtc, &pipe_config);
7470 * vlv_force_pll_off - forcibly disable just the PLL
7471 * @dev_priv: i915 private structure
7472 * @pipe: pipe PLL to disable
7474 * Disable the PLL for @pipe. To be used in cases where we need
7475 * the PLL enabled even when @pipe is not going to be enabled.
7477 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7479 if (IS_CHERRYVIEW(dev))
7480 chv_disable_pll(to_i915(dev), pipe);
7482 vlv_disable_pll(to_i915(dev), pipe);
7485 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7486 struct intel_crtc_state *crtc_state,
7487 intel_clock_t *reduced_clock,
7490 struct drm_device *dev = crtc->base.dev;
7491 struct drm_i915_private *dev_priv = dev->dev_private;
7494 struct dpll *clock = &crtc_state->dpll;
7496 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7498 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7499 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7501 dpll = DPLL_VGA_MODE_DIS;
7503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7504 dpll |= DPLLB_MODE_LVDS;
7506 dpll |= DPLLB_MODE_DAC_SERIAL;
7508 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7509 dpll |= (crtc_state->pixel_multiplier - 1)
7510 << SDVO_MULTIPLIER_SHIFT_HIRES;
7514 dpll |= DPLL_SDVO_HIGH_SPEED;
7516 if (crtc_state->has_dp_encoder)
7517 dpll |= DPLL_SDVO_HIGH_SPEED;
7519 /* compute bitmask from p1 value */
7520 if (IS_PINEVIEW(dev))
7521 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7523 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7524 if (IS_G4X(dev) && reduced_clock)
7525 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7527 switch (clock->p2) {
7529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7535 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7538 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7541 if (INTEL_INFO(dev)->gen >= 4)
7542 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7544 if (crtc_state->sdvo_tv_clock)
7545 dpll |= PLL_REF_INPUT_TVCLKINBC;
7546 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7547 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7548 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7550 dpll |= PLL_REF_INPUT_DREFCLK;
7552 dpll |= DPLL_VCO_ENABLE;
7553 crtc_state->dpll_hw_state.dpll = dpll;
7555 if (INTEL_INFO(dev)->gen >= 4) {
7556 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7557 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7558 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7562 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7563 struct intel_crtc_state *crtc_state,
7564 intel_clock_t *reduced_clock,
7567 struct drm_device *dev = crtc->base.dev;
7568 struct drm_i915_private *dev_priv = dev->dev_private;
7570 struct dpll *clock = &crtc_state->dpll;
7572 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7574 dpll = DPLL_VGA_MODE_DIS;
7576 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7577 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7580 dpll |= PLL_P1_DIVIDE_BY_TWO;
7582 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7584 dpll |= PLL_P2_DIVIDE_BY_4;
7587 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7588 dpll |= DPLL_DVO_2X_MODE;
7590 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7591 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7592 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7594 dpll |= PLL_REF_INPUT_DREFCLK;
7596 dpll |= DPLL_VCO_ENABLE;
7597 crtc_state->dpll_hw_state.dpll = dpll;
7600 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7602 struct drm_device *dev = intel_crtc->base.dev;
7603 struct drm_i915_private *dev_priv = dev->dev_private;
7604 enum pipe pipe = intel_crtc->pipe;
7605 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7606 struct drm_display_mode *adjusted_mode =
7607 &intel_crtc->config->base.adjusted_mode;
7608 uint32_t crtc_vtotal, crtc_vblank_end;
7611 /* We need to be careful not to changed the adjusted mode, for otherwise
7612 * the hw state checker will get angry at the mismatch. */
7613 crtc_vtotal = adjusted_mode->crtc_vtotal;
7614 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7616 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7617 /* the chip adds 2 halflines automatically */
7619 crtc_vblank_end -= 1;
7621 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7622 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7624 vsyncshift = adjusted_mode->crtc_hsync_start -
7625 adjusted_mode->crtc_htotal / 2;
7627 vsyncshift += adjusted_mode->crtc_htotal;
7630 if (INTEL_INFO(dev)->gen > 3)
7631 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7633 I915_WRITE(HTOTAL(cpu_transcoder),
7634 (adjusted_mode->crtc_hdisplay - 1) |
7635 ((adjusted_mode->crtc_htotal - 1) << 16));
7636 I915_WRITE(HBLANK(cpu_transcoder),
7637 (adjusted_mode->crtc_hblank_start - 1) |
7638 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7639 I915_WRITE(HSYNC(cpu_transcoder),
7640 (adjusted_mode->crtc_hsync_start - 1) |
7641 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7643 I915_WRITE(VTOTAL(cpu_transcoder),
7644 (adjusted_mode->crtc_vdisplay - 1) |
7645 ((crtc_vtotal - 1) << 16));
7646 I915_WRITE(VBLANK(cpu_transcoder),
7647 (adjusted_mode->crtc_vblank_start - 1) |
7648 ((crtc_vblank_end - 1) << 16));
7649 I915_WRITE(VSYNC(cpu_transcoder),
7650 (adjusted_mode->crtc_vsync_start - 1) |
7651 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7653 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7654 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7655 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7657 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7658 (pipe == PIPE_B || pipe == PIPE_C))
7659 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7661 /* pipesrc controls the size that is scaled from, which should
7662 * always be the user's requested size.
7664 I915_WRITE(PIPESRC(pipe),
7665 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7666 (intel_crtc->config->pipe_src_h - 1));
7669 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7670 struct intel_crtc_state *pipe_config)
7672 struct drm_device *dev = crtc->base.dev;
7673 struct drm_i915_private *dev_priv = dev->dev_private;
7674 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7677 tmp = I915_READ(HTOTAL(cpu_transcoder));
7678 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7679 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7680 tmp = I915_READ(HBLANK(cpu_transcoder));
7681 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7682 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7683 tmp = I915_READ(HSYNC(cpu_transcoder));
7684 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7685 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7687 tmp = I915_READ(VTOTAL(cpu_transcoder));
7688 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7689 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7690 tmp = I915_READ(VBLANK(cpu_transcoder));
7691 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7692 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7693 tmp = I915_READ(VSYNC(cpu_transcoder));
7694 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7695 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7697 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7698 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7699 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7700 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7703 tmp = I915_READ(PIPESRC(crtc->pipe));
7704 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7705 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7707 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7708 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7711 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7712 struct intel_crtc_state *pipe_config)
7714 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7715 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7716 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7717 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7719 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7720 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7721 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7722 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7724 mode->flags = pipe_config->base.adjusted_mode.flags;
7725 mode->type = DRM_MODE_TYPE_DRIVER;
7727 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7728 mode->flags |= pipe_config->base.adjusted_mode.flags;
7730 mode->hsync = drm_mode_hsync(mode);
7731 mode->vrefresh = drm_mode_vrefresh(mode);
7732 drm_mode_set_name(mode);
7735 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7737 struct drm_device *dev = intel_crtc->base.dev;
7738 struct drm_i915_private *dev_priv = dev->dev_private;
7743 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7744 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7745 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7747 if (intel_crtc->config->double_wide)
7748 pipeconf |= PIPECONF_DOUBLE_WIDE;
7750 /* only g4x and later have fancy bpc/dither controls */
7751 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7752 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7753 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7754 pipeconf |= PIPECONF_DITHER_EN |
7755 PIPECONF_DITHER_TYPE_SP;
7757 switch (intel_crtc->config->pipe_bpp) {
7759 pipeconf |= PIPECONF_6BPC;
7762 pipeconf |= PIPECONF_8BPC;
7765 pipeconf |= PIPECONF_10BPC;
7768 /* Case prevented by intel_choose_pipe_bpp_dither. */
7773 if (HAS_PIPE_CXSR(dev)) {
7774 if (intel_crtc->lowfreq_avail) {
7775 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7776 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7778 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7782 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7783 if (INTEL_INFO(dev)->gen < 4 ||
7784 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7785 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7787 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7789 pipeconf |= PIPECONF_PROGRESSIVE;
7791 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7792 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7794 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7795 POSTING_READ(PIPECONF(intel_crtc->pipe));
7798 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7799 struct intel_crtc_state *crtc_state)
7801 struct drm_device *dev = crtc->base.dev;
7802 struct drm_i915_private *dev_priv = dev->dev_private;
7803 int refclk, num_connectors = 0;
7804 intel_clock_t clock;
7806 bool is_dsi = false;
7807 struct intel_encoder *encoder;
7808 const intel_limit_t *limit;
7809 struct drm_atomic_state *state = crtc_state->base.state;
7810 struct drm_connector *connector;
7811 struct drm_connector_state *connector_state;
7814 memset(&crtc_state->dpll_hw_state, 0,
7815 sizeof(crtc_state->dpll_hw_state));
7817 for_each_connector_in_state(state, connector, connector_state, i) {
7818 if (connector_state->crtc != &crtc->base)
7821 encoder = to_intel_encoder(connector_state->best_encoder);
7823 switch (encoder->type) {
7824 case INTEL_OUTPUT_DSI:
7837 if (!crtc_state->clock_set) {
7838 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7841 * Returns a set of divisors for the desired target clock with
7842 * the given refclk, or FALSE. The returned values represent
7843 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7846 limit = intel_limit(crtc_state, refclk);
7847 ok = dev_priv->display.find_dpll(limit, crtc_state,
7848 crtc_state->port_clock,
7849 refclk, NULL, &clock);
7851 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7855 /* Compat-code for transition, will disappear. */
7856 crtc_state->dpll.n = clock.n;
7857 crtc_state->dpll.m1 = clock.m1;
7858 crtc_state->dpll.m2 = clock.m2;
7859 crtc_state->dpll.p1 = clock.p1;
7860 crtc_state->dpll.p2 = clock.p2;
7864 i8xx_compute_dpll(crtc, crtc_state, NULL,
7866 } else if (IS_CHERRYVIEW(dev)) {
7867 chv_compute_dpll(crtc, crtc_state);
7868 } else if (IS_VALLEYVIEW(dev)) {
7869 vlv_compute_dpll(crtc, crtc_state);
7871 i9xx_compute_dpll(crtc, crtc_state, NULL,
7878 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7879 struct intel_crtc_state *pipe_config)
7881 struct drm_device *dev = crtc->base.dev;
7882 struct drm_i915_private *dev_priv = dev->dev_private;
7885 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7888 tmp = I915_READ(PFIT_CONTROL);
7889 if (!(tmp & PFIT_ENABLE))
7892 /* Check whether the pfit is attached to our pipe. */
7893 if (INTEL_INFO(dev)->gen < 4) {
7894 if (crtc->pipe != PIPE_B)
7897 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7901 pipe_config->gmch_pfit.control = tmp;
7902 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7903 if (INTEL_INFO(dev)->gen < 5)
7904 pipe_config->gmch_pfit.lvds_border_bits =
7905 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7908 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7909 struct intel_crtc_state *pipe_config)
7911 struct drm_device *dev = crtc->base.dev;
7912 struct drm_i915_private *dev_priv = dev->dev_private;
7913 int pipe = pipe_config->cpu_transcoder;
7914 intel_clock_t clock;
7916 int refclk = 100000;
7918 /* In case of MIPI DPLL will not even be used */
7919 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7922 mutex_lock(&dev_priv->sb_lock);
7923 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7924 mutex_unlock(&dev_priv->sb_lock);
7926 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7927 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7928 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7929 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7930 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7932 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7936 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7937 struct intel_initial_plane_config *plane_config)
7939 struct drm_device *dev = crtc->base.dev;
7940 struct drm_i915_private *dev_priv = dev->dev_private;
7941 u32 val, base, offset;
7942 int pipe = crtc->pipe, plane = crtc->plane;
7943 int fourcc, pixel_format;
7944 unsigned int aligned_height;
7945 struct drm_framebuffer *fb;
7946 struct intel_framebuffer *intel_fb;
7948 val = I915_READ(DSPCNTR(plane));
7949 if (!(val & DISPLAY_PLANE_ENABLE))
7952 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7954 DRM_DEBUG_KMS("failed to alloc fb\n");
7958 fb = &intel_fb->base;
7960 if (INTEL_INFO(dev)->gen >= 4) {
7961 if (val & DISPPLANE_TILED) {
7962 plane_config->tiling = I915_TILING_X;
7963 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7967 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7968 fourcc = i9xx_format_to_fourcc(pixel_format);
7969 fb->pixel_format = fourcc;
7970 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7972 if (INTEL_INFO(dev)->gen >= 4) {
7973 if (plane_config->tiling)
7974 offset = I915_READ(DSPTILEOFF(plane));
7976 offset = I915_READ(DSPLINOFF(plane));
7977 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7979 base = I915_READ(DSPADDR(plane));
7981 plane_config->base = base;
7983 val = I915_READ(PIPESRC(pipe));
7984 fb->width = ((val >> 16) & 0xfff) + 1;
7985 fb->height = ((val >> 0) & 0xfff) + 1;
7987 val = I915_READ(DSPSTRIDE(pipe));
7988 fb->pitches[0] = val & 0xffffffc0;
7990 aligned_height = intel_fb_align_height(dev, fb->height,
7994 plane_config->size = fb->pitches[0] * aligned_height;
7996 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7997 pipe_name(pipe), plane, fb->width, fb->height,
7998 fb->bits_per_pixel, base, fb->pitches[0],
7999 plane_config->size);
8001 plane_config->fb = intel_fb;
8004 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8005 struct intel_crtc_state *pipe_config)
8007 struct drm_device *dev = crtc->base.dev;
8008 struct drm_i915_private *dev_priv = dev->dev_private;
8009 int pipe = pipe_config->cpu_transcoder;
8010 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8011 intel_clock_t clock;
8012 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8013 int refclk = 100000;
8015 mutex_lock(&dev_priv->sb_lock);
8016 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8017 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8018 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8019 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8020 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8021 mutex_unlock(&dev_priv->sb_lock);
8023 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8024 clock.m2 = (pll_dw0 & 0xff) << 22;
8025 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8026 clock.m2 |= pll_dw2 & 0x3fffff;
8027 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8028 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8029 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8031 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8034 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8035 struct intel_crtc_state *pipe_config)
8037 struct drm_device *dev = crtc->base.dev;
8038 struct drm_i915_private *dev_priv = dev->dev_private;
8041 if (!intel_display_power_is_enabled(dev_priv,
8042 POWER_DOMAIN_PIPE(crtc->pipe)))
8045 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8046 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8048 tmp = I915_READ(PIPECONF(crtc->pipe));
8049 if (!(tmp & PIPECONF_ENABLE))
8052 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8053 switch (tmp & PIPECONF_BPC_MASK) {
8055 pipe_config->pipe_bpp = 18;
8058 pipe_config->pipe_bpp = 24;
8060 case PIPECONF_10BPC:
8061 pipe_config->pipe_bpp = 30;
8068 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8069 pipe_config->limited_color_range = true;
8071 if (INTEL_INFO(dev)->gen < 4)
8072 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8074 intel_get_pipe_timings(crtc, pipe_config);
8076 i9xx_get_pfit_config(crtc, pipe_config);
8078 if (INTEL_INFO(dev)->gen >= 4) {
8079 tmp = I915_READ(DPLL_MD(crtc->pipe));
8080 pipe_config->pixel_multiplier =
8081 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8082 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8083 pipe_config->dpll_hw_state.dpll_md = tmp;
8084 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8085 tmp = I915_READ(DPLL(crtc->pipe));
8086 pipe_config->pixel_multiplier =
8087 ((tmp & SDVO_MULTIPLIER_MASK)
8088 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8090 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8091 * port and will be fixed up in the encoder->get_config
8093 pipe_config->pixel_multiplier = 1;
8095 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8096 if (!IS_VALLEYVIEW(dev)) {
8098 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8099 * on 830. Filter it out here so that we don't
8100 * report errors due to that.
8103 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8105 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8106 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8108 /* Mask out read-only status bits. */
8109 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8110 DPLL_PORTC_READY_MASK |
8111 DPLL_PORTB_READY_MASK);
8114 if (IS_CHERRYVIEW(dev))
8115 chv_crtc_clock_get(crtc, pipe_config);
8116 else if (IS_VALLEYVIEW(dev))
8117 vlv_crtc_clock_get(crtc, pipe_config);
8119 i9xx_crtc_clock_get(crtc, pipe_config);
8124 static void ironlake_init_pch_refclk(struct drm_device *dev)
8126 struct drm_i915_private *dev_priv = dev->dev_private;
8127 struct intel_encoder *encoder;
8129 bool has_lvds = false;
8130 bool has_cpu_edp = false;
8131 bool has_panel = false;
8132 bool has_ck505 = false;
8133 bool can_ssc = false;
8135 /* We need to take the global config into account */
8136 for_each_intel_encoder(dev, encoder) {
8137 switch (encoder->type) {
8138 case INTEL_OUTPUT_LVDS:
8142 case INTEL_OUTPUT_EDP:
8144 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8152 if (HAS_PCH_IBX(dev)) {
8153 has_ck505 = dev_priv->vbt.display_clock_mode;
8154 can_ssc = has_ck505;
8160 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8161 has_panel, has_lvds, has_ck505);
8163 /* Ironlake: try to setup display ref clock before DPLL
8164 * enabling. This is only under driver's control after
8165 * PCH B stepping, previous chipset stepping should be
8166 * ignoring this setting.
8168 val = I915_READ(PCH_DREF_CONTROL);
8170 /* As we must carefully and slowly disable/enable each source in turn,
8171 * compute the final state we want first and check if we need to
8172 * make any changes at all.
8175 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8177 final |= DREF_NONSPREAD_CK505_ENABLE;
8179 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8181 final &= ~DREF_SSC_SOURCE_MASK;
8182 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8183 final &= ~DREF_SSC1_ENABLE;
8186 final |= DREF_SSC_SOURCE_ENABLE;
8188 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8189 final |= DREF_SSC1_ENABLE;
8192 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8193 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8195 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8197 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8199 final |= DREF_SSC_SOURCE_DISABLE;
8200 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8206 /* Always enable nonspread source */
8207 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8210 val |= DREF_NONSPREAD_CK505_ENABLE;
8212 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8215 val &= ~DREF_SSC_SOURCE_MASK;
8216 val |= DREF_SSC_SOURCE_ENABLE;
8218 /* SSC must be turned on before enabling the CPU output */
8219 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8220 DRM_DEBUG_KMS("Using SSC on panel\n");
8221 val |= DREF_SSC1_ENABLE;
8223 val &= ~DREF_SSC1_ENABLE;
8225 /* Get SSC going before enabling the outputs */
8226 I915_WRITE(PCH_DREF_CONTROL, val);
8227 POSTING_READ(PCH_DREF_CONTROL);
8230 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8232 /* Enable CPU source on CPU attached eDP */
8234 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8235 DRM_DEBUG_KMS("Using SSC on eDP\n");
8236 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8238 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8240 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8242 I915_WRITE(PCH_DREF_CONTROL, val);
8243 POSTING_READ(PCH_DREF_CONTROL);
8246 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8248 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8250 /* Turn off CPU output */
8251 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8253 I915_WRITE(PCH_DREF_CONTROL, val);
8254 POSTING_READ(PCH_DREF_CONTROL);
8257 /* Turn off the SSC source */
8258 val &= ~DREF_SSC_SOURCE_MASK;
8259 val |= DREF_SSC_SOURCE_DISABLE;
8262 val &= ~DREF_SSC1_ENABLE;
8264 I915_WRITE(PCH_DREF_CONTROL, val);
8265 POSTING_READ(PCH_DREF_CONTROL);
8269 BUG_ON(val != final);
8272 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8276 tmp = I915_READ(SOUTH_CHICKEN2);
8277 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8278 I915_WRITE(SOUTH_CHICKEN2, tmp);
8280 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8281 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8282 DRM_ERROR("FDI mPHY reset assert timeout\n");
8284 tmp = I915_READ(SOUTH_CHICKEN2);
8285 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8286 I915_WRITE(SOUTH_CHICKEN2, tmp);
8288 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8289 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8290 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8293 /* WaMPhyProgramming:hsw */
8294 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8298 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8299 tmp &= ~(0xFF << 24);
8300 tmp |= (0x12 << 24);
8301 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8303 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8305 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8307 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8309 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8311 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8312 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8313 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8315 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8316 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8317 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8319 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8322 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8324 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8327 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8329 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8332 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8334 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8337 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8339 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8340 tmp &= ~(0xFF << 16);
8341 tmp |= (0x1C << 16);
8342 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8344 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8345 tmp &= ~(0xFF << 16);
8346 tmp |= (0x1C << 16);
8347 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8349 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8351 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8353 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8355 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8357 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8358 tmp &= ~(0xF << 28);
8360 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8362 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8363 tmp &= ~(0xF << 28);
8365 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8368 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8369 * Programming" based on the parameters passed:
8370 * - Sequence to enable CLKOUT_DP
8371 * - Sequence to enable CLKOUT_DP without spread
8372 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8374 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8377 struct drm_i915_private *dev_priv = dev->dev_private;
8380 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8382 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8383 with_fdi, "LP PCH doesn't have FDI\n"))
8386 mutex_lock(&dev_priv->sb_lock);
8388 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8389 tmp &= ~SBI_SSCCTL_DISABLE;
8390 tmp |= SBI_SSCCTL_PATHALT;
8391 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8396 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8397 tmp &= ~SBI_SSCCTL_PATHALT;
8398 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8401 lpt_reset_fdi_mphy(dev_priv);
8402 lpt_program_fdi_mphy(dev_priv);
8406 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8407 SBI_GEN0 : SBI_DBUFF0;
8408 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8409 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8410 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8412 mutex_unlock(&dev_priv->sb_lock);
8415 /* Sequence to disable CLKOUT_DP */
8416 static void lpt_disable_clkout_dp(struct drm_device *dev)
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8421 mutex_lock(&dev_priv->sb_lock);
8423 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8424 SBI_GEN0 : SBI_DBUFF0;
8425 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8426 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8427 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8429 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8430 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8431 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8432 tmp |= SBI_SSCCTL_PATHALT;
8433 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8436 tmp |= SBI_SSCCTL_DISABLE;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8440 mutex_unlock(&dev_priv->sb_lock);
8443 static void lpt_init_pch_refclk(struct drm_device *dev)
8445 struct intel_encoder *encoder;
8446 bool has_vga = false;
8448 for_each_intel_encoder(dev, encoder) {
8449 switch (encoder->type) {
8450 case INTEL_OUTPUT_ANALOG:
8459 lpt_enable_clkout_dp(dev, true, true);
8461 lpt_disable_clkout_dp(dev);
8465 * Initialize reference clocks when the driver loads
8467 void intel_init_pch_refclk(struct drm_device *dev)
8469 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8470 ironlake_init_pch_refclk(dev);
8471 else if (HAS_PCH_LPT(dev))
8472 lpt_init_pch_refclk(dev);
8475 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8477 struct drm_device *dev = crtc_state->base.crtc->dev;
8478 struct drm_i915_private *dev_priv = dev->dev_private;
8479 struct drm_atomic_state *state = crtc_state->base.state;
8480 struct drm_connector *connector;
8481 struct drm_connector_state *connector_state;
8482 struct intel_encoder *encoder;
8483 int num_connectors = 0, i;
8484 bool is_lvds = false;
8486 for_each_connector_in_state(state, connector, connector_state, i) {
8487 if (connector_state->crtc != crtc_state->base.crtc)
8490 encoder = to_intel_encoder(connector_state->best_encoder);
8492 switch (encoder->type) {
8493 case INTEL_OUTPUT_LVDS:
8502 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8503 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8504 dev_priv->vbt.lvds_ssc_freq);
8505 return dev_priv->vbt.lvds_ssc_freq;
8511 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8513 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8515 int pipe = intel_crtc->pipe;
8520 switch (intel_crtc->config->pipe_bpp) {
8522 val |= PIPECONF_6BPC;
8525 val |= PIPECONF_8BPC;
8528 val |= PIPECONF_10BPC;
8531 val |= PIPECONF_12BPC;
8534 /* Case prevented by intel_choose_pipe_bpp_dither. */
8538 if (intel_crtc->config->dither)
8539 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8541 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8542 val |= PIPECONF_INTERLACED_ILK;
8544 val |= PIPECONF_PROGRESSIVE;
8546 if (intel_crtc->config->limited_color_range)
8547 val |= PIPECONF_COLOR_RANGE_SELECT;
8549 I915_WRITE(PIPECONF(pipe), val);
8550 POSTING_READ(PIPECONF(pipe));
8554 * Set up the pipe CSC unit.
8556 * Currently only full range RGB to limited range RGB conversion
8557 * is supported, but eventually this should handle various
8558 * RGB<->YCbCr scenarios as well.
8560 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8562 struct drm_device *dev = crtc->dev;
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565 int pipe = intel_crtc->pipe;
8566 uint16_t coeff = 0x7800; /* 1.0 */
8569 * TODO: Check what kind of values actually come out of the pipe
8570 * with these coeff/postoff values and adjust to get the best
8571 * accuracy. Perhaps we even need to take the bpc value into
8575 if (intel_crtc->config->limited_color_range)
8576 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8579 * GY/GU and RY/RU should be the other way around according
8580 * to BSpec, but reality doesn't agree. Just set them up in
8581 * a way that results in the correct picture.
8583 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8584 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8586 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8587 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8589 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8590 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8592 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8593 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8594 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8596 if (INTEL_INFO(dev)->gen > 6) {
8597 uint16_t postoff = 0;
8599 if (intel_crtc->config->limited_color_range)
8600 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8602 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8603 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8604 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8606 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8608 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8610 if (intel_crtc->config->limited_color_range)
8611 mode |= CSC_BLACK_SCREEN_OFFSET;
8613 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8617 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8619 struct drm_device *dev = crtc->dev;
8620 struct drm_i915_private *dev_priv = dev->dev_private;
8621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8622 enum pipe pipe = intel_crtc->pipe;
8623 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8628 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8629 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8631 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8632 val |= PIPECONF_INTERLACED_ILK;
8634 val |= PIPECONF_PROGRESSIVE;
8636 I915_WRITE(PIPECONF(cpu_transcoder), val);
8637 POSTING_READ(PIPECONF(cpu_transcoder));
8639 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8640 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8642 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8645 switch (intel_crtc->config->pipe_bpp) {
8647 val |= PIPEMISC_DITHER_6_BPC;
8650 val |= PIPEMISC_DITHER_8_BPC;
8653 val |= PIPEMISC_DITHER_10_BPC;
8656 val |= PIPEMISC_DITHER_12_BPC;
8659 /* Case prevented by pipe_config_set_bpp. */
8663 if (intel_crtc->config->dither)
8664 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8666 I915_WRITE(PIPEMISC(pipe), val);
8670 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8671 struct intel_crtc_state *crtc_state,
8672 intel_clock_t *clock,
8673 bool *has_reduced_clock,
8674 intel_clock_t *reduced_clock)
8676 struct drm_device *dev = crtc->dev;
8677 struct drm_i915_private *dev_priv = dev->dev_private;
8679 const intel_limit_t *limit;
8682 refclk = ironlake_get_refclk(crtc_state);
8685 * Returns a set of divisors for the desired target clock with the given
8686 * refclk, or FALSE. The returned values represent the clock equation:
8687 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8689 limit = intel_limit(crtc_state, refclk);
8690 ret = dev_priv->display.find_dpll(limit, crtc_state,
8691 crtc_state->port_clock,
8692 refclk, NULL, clock);
8699 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8702 * Account for spread spectrum to avoid
8703 * oversubscribing the link. Max center spread
8704 * is 2.5%; use 5% for safety's sake.
8706 u32 bps = target_clock * bpp * 21 / 20;
8707 return DIV_ROUND_UP(bps, link_bw * 8);
8710 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8712 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8715 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8716 struct intel_crtc_state *crtc_state,
8718 intel_clock_t *reduced_clock, u32 *fp2)
8720 struct drm_crtc *crtc = &intel_crtc->base;
8721 struct drm_device *dev = crtc->dev;
8722 struct drm_i915_private *dev_priv = dev->dev_private;
8723 struct drm_atomic_state *state = crtc_state->base.state;
8724 struct drm_connector *connector;
8725 struct drm_connector_state *connector_state;
8726 struct intel_encoder *encoder;
8728 int factor, num_connectors = 0, i;
8729 bool is_lvds = false, is_sdvo = false;
8731 for_each_connector_in_state(state, connector, connector_state, i) {
8732 if (connector_state->crtc != crtc_state->base.crtc)
8735 encoder = to_intel_encoder(connector_state->best_encoder);
8737 switch (encoder->type) {
8738 case INTEL_OUTPUT_LVDS:
8741 case INTEL_OUTPUT_SDVO:
8742 case INTEL_OUTPUT_HDMI:
8752 /* Enable autotuning of the PLL clock (if permissible) */
8755 if ((intel_panel_use_ssc(dev_priv) &&
8756 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8757 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8759 } else if (crtc_state->sdvo_tv_clock)
8762 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8765 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8771 dpll |= DPLLB_MODE_LVDS;
8773 dpll |= DPLLB_MODE_DAC_SERIAL;
8775 dpll |= (crtc_state->pixel_multiplier - 1)
8776 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8779 dpll |= DPLL_SDVO_HIGH_SPEED;
8780 if (crtc_state->has_dp_encoder)
8781 dpll |= DPLL_SDVO_HIGH_SPEED;
8783 /* compute bitmask from p1 value */
8784 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8788 switch (crtc_state->dpll.p2) {
8790 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8793 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8803 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8806 dpll |= PLL_REF_INPUT_DREFCLK;
8808 return dpll | DPLL_VCO_ENABLE;
8811 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8812 struct intel_crtc_state *crtc_state)
8814 struct drm_device *dev = crtc->base.dev;
8815 intel_clock_t clock, reduced_clock;
8816 u32 dpll = 0, fp = 0, fp2 = 0;
8817 bool ok, has_reduced_clock = false;
8818 bool is_lvds = false;
8819 struct intel_shared_dpll *pll;
8821 memset(&crtc_state->dpll_hw_state, 0,
8822 sizeof(crtc_state->dpll_hw_state));
8824 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8826 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8827 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8829 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8830 &has_reduced_clock, &reduced_clock);
8831 if (!ok && !crtc_state->clock_set) {
8832 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8835 /* Compat-code for transition, will disappear. */
8836 if (!crtc_state->clock_set) {
8837 crtc_state->dpll.n = clock.n;
8838 crtc_state->dpll.m1 = clock.m1;
8839 crtc_state->dpll.m2 = clock.m2;
8840 crtc_state->dpll.p1 = clock.p1;
8841 crtc_state->dpll.p2 = clock.p2;
8844 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8845 if (crtc_state->has_pch_encoder) {
8846 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8847 if (has_reduced_clock)
8848 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8850 dpll = ironlake_compute_dpll(crtc, crtc_state,
8851 &fp, &reduced_clock,
8852 has_reduced_clock ? &fp2 : NULL);
8854 crtc_state->dpll_hw_state.dpll = dpll;
8855 crtc_state->dpll_hw_state.fp0 = fp;
8856 if (has_reduced_clock)
8857 crtc_state->dpll_hw_state.fp1 = fp2;
8859 crtc_state->dpll_hw_state.fp1 = fp;
8861 pll = intel_get_shared_dpll(crtc, crtc_state);
8863 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8864 pipe_name(crtc->pipe));
8869 if (is_lvds && has_reduced_clock)
8870 crtc->lowfreq_avail = true;
8872 crtc->lowfreq_avail = false;
8877 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8878 struct intel_link_m_n *m_n)
8880 struct drm_device *dev = crtc->base.dev;
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 enum pipe pipe = crtc->pipe;
8884 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8885 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8886 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8888 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8889 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8890 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8893 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8894 enum transcoder transcoder,
8895 struct intel_link_m_n *m_n,
8896 struct intel_link_m_n *m2_n2)
8898 struct drm_device *dev = crtc->base.dev;
8899 struct drm_i915_private *dev_priv = dev->dev_private;
8900 enum pipe pipe = crtc->pipe;
8902 if (INTEL_INFO(dev)->gen >= 5) {
8903 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8904 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8905 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8907 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8908 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8909 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8910 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8911 * gen < 8) and if DRRS is supported (to make sure the
8912 * registers are not unnecessarily read).
8914 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8915 crtc->config->has_drrs) {
8916 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8917 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8918 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8920 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8921 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8922 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8925 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8926 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8927 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8929 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8930 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8931 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8935 void intel_dp_get_m_n(struct intel_crtc *crtc,
8936 struct intel_crtc_state *pipe_config)
8938 if (pipe_config->has_pch_encoder)
8939 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8941 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8942 &pipe_config->dp_m_n,
8943 &pipe_config->dp_m2_n2);
8946 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8947 struct intel_crtc_state *pipe_config)
8949 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8950 &pipe_config->fdi_m_n, NULL);
8953 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8954 struct intel_crtc_state *pipe_config)
8956 struct drm_device *dev = crtc->base.dev;
8957 struct drm_i915_private *dev_priv = dev->dev_private;
8958 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8959 uint32_t ps_ctrl = 0;
8963 /* find scaler attached to this pipe */
8964 for (i = 0; i < crtc->num_scalers; i++) {
8965 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8966 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8968 pipe_config->pch_pfit.enabled = true;
8969 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8970 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8975 scaler_state->scaler_id = id;
8977 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8979 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8984 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8985 struct intel_initial_plane_config *plane_config)
8987 struct drm_device *dev = crtc->base.dev;
8988 struct drm_i915_private *dev_priv = dev->dev_private;
8989 u32 val, base, offset, stride_mult, tiling;
8990 int pipe = crtc->pipe;
8991 int fourcc, pixel_format;
8992 unsigned int aligned_height;
8993 struct drm_framebuffer *fb;
8994 struct intel_framebuffer *intel_fb;
8996 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8998 DRM_DEBUG_KMS("failed to alloc fb\n");
9002 fb = &intel_fb->base;
9004 val = I915_READ(PLANE_CTL(pipe, 0));
9005 if (!(val & PLANE_CTL_ENABLE))
9008 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9009 fourcc = skl_format_to_fourcc(pixel_format,
9010 val & PLANE_CTL_ORDER_RGBX,
9011 val & PLANE_CTL_ALPHA_MASK);
9012 fb->pixel_format = fourcc;
9013 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9015 tiling = val & PLANE_CTL_TILED_MASK;
9017 case PLANE_CTL_TILED_LINEAR:
9018 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9020 case PLANE_CTL_TILED_X:
9021 plane_config->tiling = I915_TILING_X;
9022 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9024 case PLANE_CTL_TILED_Y:
9025 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9027 case PLANE_CTL_TILED_YF:
9028 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9031 MISSING_CASE(tiling);
9035 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9036 plane_config->base = base;
9038 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9040 val = I915_READ(PLANE_SIZE(pipe, 0));
9041 fb->height = ((val >> 16) & 0xfff) + 1;
9042 fb->width = ((val >> 0) & 0x1fff) + 1;
9044 val = I915_READ(PLANE_STRIDE(pipe, 0));
9045 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9047 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9049 aligned_height = intel_fb_align_height(dev, fb->height,
9053 plane_config->size = fb->pitches[0] * aligned_height;
9055 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9056 pipe_name(pipe), fb->width, fb->height,
9057 fb->bits_per_pixel, base, fb->pitches[0],
9058 plane_config->size);
9060 plane_config->fb = intel_fb;
9067 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9068 struct intel_crtc_state *pipe_config)
9070 struct drm_device *dev = crtc->base.dev;
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9074 tmp = I915_READ(PF_CTL(crtc->pipe));
9076 if (tmp & PF_ENABLE) {
9077 pipe_config->pch_pfit.enabled = true;
9078 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9079 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9081 /* We currently do not free assignements of panel fitters on
9082 * ivb/hsw (since we don't use the higher upscaling modes which
9083 * differentiates them) so just WARN about this case for now. */
9085 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9086 PF_PIPE_SEL_IVB(crtc->pipe));
9092 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9093 struct intel_initial_plane_config *plane_config)
9095 struct drm_device *dev = crtc->base.dev;
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 u32 val, base, offset;
9098 int pipe = crtc->pipe;
9099 int fourcc, pixel_format;
9100 unsigned int aligned_height;
9101 struct drm_framebuffer *fb;
9102 struct intel_framebuffer *intel_fb;
9104 val = I915_READ(DSPCNTR(pipe));
9105 if (!(val & DISPLAY_PLANE_ENABLE))
9108 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9110 DRM_DEBUG_KMS("failed to alloc fb\n");
9114 fb = &intel_fb->base;
9116 if (INTEL_INFO(dev)->gen >= 4) {
9117 if (val & DISPPLANE_TILED) {
9118 plane_config->tiling = I915_TILING_X;
9119 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9123 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9124 fourcc = i9xx_format_to_fourcc(pixel_format);
9125 fb->pixel_format = fourcc;
9126 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9128 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9129 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9130 offset = I915_READ(DSPOFFSET(pipe));
9132 if (plane_config->tiling)
9133 offset = I915_READ(DSPTILEOFF(pipe));
9135 offset = I915_READ(DSPLINOFF(pipe));
9137 plane_config->base = base;
9139 val = I915_READ(PIPESRC(pipe));
9140 fb->width = ((val >> 16) & 0xfff) + 1;
9141 fb->height = ((val >> 0) & 0xfff) + 1;
9143 val = I915_READ(DSPSTRIDE(pipe));
9144 fb->pitches[0] = val & 0xffffffc0;
9146 aligned_height = intel_fb_align_height(dev, fb->height,
9150 plane_config->size = fb->pitches[0] * aligned_height;
9152 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9153 pipe_name(pipe), fb->width, fb->height,
9154 fb->bits_per_pixel, base, fb->pitches[0],
9155 plane_config->size);
9157 plane_config->fb = intel_fb;
9160 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9161 struct intel_crtc_state *pipe_config)
9163 struct drm_device *dev = crtc->base.dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9167 if (!intel_display_power_is_enabled(dev_priv,
9168 POWER_DOMAIN_PIPE(crtc->pipe)))
9171 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9172 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9174 tmp = I915_READ(PIPECONF(crtc->pipe));
9175 if (!(tmp & PIPECONF_ENABLE))
9178 switch (tmp & PIPECONF_BPC_MASK) {
9180 pipe_config->pipe_bpp = 18;
9183 pipe_config->pipe_bpp = 24;
9185 case PIPECONF_10BPC:
9186 pipe_config->pipe_bpp = 30;
9188 case PIPECONF_12BPC:
9189 pipe_config->pipe_bpp = 36;
9195 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9196 pipe_config->limited_color_range = true;
9198 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9199 struct intel_shared_dpll *pll;
9201 pipe_config->has_pch_encoder = true;
9203 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9204 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9205 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9207 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9209 if (HAS_PCH_IBX(dev_priv->dev)) {
9210 pipe_config->shared_dpll =
9211 (enum intel_dpll_id) crtc->pipe;
9213 tmp = I915_READ(PCH_DPLL_SEL);
9214 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9215 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9217 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9220 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9222 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9223 &pipe_config->dpll_hw_state));
9225 tmp = pipe_config->dpll_hw_state.dpll;
9226 pipe_config->pixel_multiplier =
9227 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9228 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9230 ironlake_pch_clock_get(crtc, pipe_config);
9232 pipe_config->pixel_multiplier = 1;
9235 intel_get_pipe_timings(crtc, pipe_config);
9237 ironlake_get_pfit_config(crtc, pipe_config);
9242 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9244 struct drm_device *dev = dev_priv->dev;
9245 struct intel_crtc *crtc;
9247 for_each_intel_crtc(dev, crtc)
9248 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9249 pipe_name(crtc->pipe));
9251 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9252 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9253 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9254 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9255 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9256 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9257 "CPU PWM1 enabled\n");
9258 if (IS_HASWELL(dev))
9259 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9260 "CPU PWM2 enabled\n");
9261 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9262 "PCH PWM1 enabled\n");
9263 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9264 "Utility pin enabled\n");
9265 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9268 * In theory we can still leave IRQs enabled, as long as only the HPD
9269 * interrupts remain enabled. We used to check for that, but since it's
9270 * gen-specific and since we only disable LCPLL after we fully disable
9271 * the interrupts, the check below should be enough.
9273 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9276 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9278 struct drm_device *dev = dev_priv->dev;
9280 if (IS_HASWELL(dev))
9281 return I915_READ(D_COMP_HSW);
9283 return I915_READ(D_COMP_BDW);
9286 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9288 struct drm_device *dev = dev_priv->dev;
9290 if (IS_HASWELL(dev)) {
9291 mutex_lock(&dev_priv->rps.hw_lock);
9292 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9294 DRM_ERROR("Failed to write to D_COMP\n");
9295 mutex_unlock(&dev_priv->rps.hw_lock);
9297 I915_WRITE(D_COMP_BDW, val);
9298 POSTING_READ(D_COMP_BDW);
9303 * This function implements pieces of two sequences from BSpec:
9304 * - Sequence for display software to disable LCPLL
9305 * - Sequence for display software to allow package C8+
9306 * The steps implemented here are just the steps that actually touch the LCPLL
9307 * register. Callers should take care of disabling all the display engine
9308 * functions, doing the mode unset, fixing interrupts, etc.
9310 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9311 bool switch_to_fclk, bool allow_power_down)
9315 assert_can_disable_lcpll(dev_priv);
9317 val = I915_READ(LCPLL_CTL);
9319 if (switch_to_fclk) {
9320 val |= LCPLL_CD_SOURCE_FCLK;
9321 I915_WRITE(LCPLL_CTL, val);
9323 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9324 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9325 DRM_ERROR("Switching to FCLK failed\n");
9327 val = I915_READ(LCPLL_CTL);
9330 val |= LCPLL_PLL_DISABLE;
9331 I915_WRITE(LCPLL_CTL, val);
9332 POSTING_READ(LCPLL_CTL);
9334 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9335 DRM_ERROR("LCPLL still locked\n");
9337 val = hsw_read_dcomp(dev_priv);
9338 val |= D_COMP_COMP_DISABLE;
9339 hsw_write_dcomp(dev_priv, val);
9342 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9344 DRM_ERROR("D_COMP RCOMP still in progress\n");
9346 if (allow_power_down) {
9347 val = I915_READ(LCPLL_CTL);
9348 val |= LCPLL_POWER_DOWN_ALLOW;
9349 I915_WRITE(LCPLL_CTL, val);
9350 POSTING_READ(LCPLL_CTL);
9355 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9358 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9362 val = I915_READ(LCPLL_CTL);
9364 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9365 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9369 * Make sure we're not on PC8 state before disabling PC8, otherwise
9370 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9372 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9374 if (val & LCPLL_POWER_DOWN_ALLOW) {
9375 val &= ~LCPLL_POWER_DOWN_ALLOW;
9376 I915_WRITE(LCPLL_CTL, val);
9377 POSTING_READ(LCPLL_CTL);
9380 val = hsw_read_dcomp(dev_priv);
9381 val |= D_COMP_COMP_FORCE;
9382 val &= ~D_COMP_COMP_DISABLE;
9383 hsw_write_dcomp(dev_priv, val);
9385 val = I915_READ(LCPLL_CTL);
9386 val &= ~LCPLL_PLL_DISABLE;
9387 I915_WRITE(LCPLL_CTL, val);
9389 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9390 DRM_ERROR("LCPLL not locked yet\n");
9392 if (val & LCPLL_CD_SOURCE_FCLK) {
9393 val = I915_READ(LCPLL_CTL);
9394 val &= ~LCPLL_CD_SOURCE_FCLK;
9395 I915_WRITE(LCPLL_CTL, val);
9397 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9398 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9399 DRM_ERROR("Switching back to LCPLL failed\n");
9402 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9403 intel_update_cdclk(dev_priv->dev);
9407 * Package states C8 and deeper are really deep PC states that can only be
9408 * reached when all the devices on the system allow it, so even if the graphics
9409 * device allows PC8+, it doesn't mean the system will actually get to these
9410 * states. Our driver only allows PC8+ when going into runtime PM.
9412 * The requirements for PC8+ are that all the outputs are disabled, the power
9413 * well is disabled and most interrupts are disabled, and these are also
9414 * requirements for runtime PM. When these conditions are met, we manually do
9415 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9416 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9419 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9420 * the state of some registers, so when we come back from PC8+ we need to
9421 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9422 * need to take care of the registers kept by RC6. Notice that this happens even
9423 * if we don't put the device in PCI D3 state (which is what currently happens
9424 * because of the runtime PM support).
9426 * For more, read "Display Sequences for Package C8" on the hardware
9429 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9431 struct drm_device *dev = dev_priv->dev;
9434 DRM_DEBUG_KMS("Enabling package C8+\n");
9436 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9437 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9438 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9439 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9442 lpt_disable_clkout_dp(dev);
9443 hsw_disable_lcpll(dev_priv, true, true);
9446 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9448 struct drm_device *dev = dev_priv->dev;
9451 DRM_DEBUG_KMS("Disabling package C8+\n");
9453 hsw_restore_lcpll(dev_priv);
9454 lpt_init_pch_refclk(dev);
9456 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9457 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9458 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9459 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9462 intel_prepare_ddi(dev);
9465 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9467 struct drm_device *dev = old_state->dev;
9468 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9470 broxton_set_cdclk(dev, req_cdclk);
9473 /* compute the max rate for new configuration */
9474 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9476 struct intel_crtc *intel_crtc;
9477 struct intel_crtc_state *crtc_state;
9478 int max_pixel_rate = 0;
9480 for_each_intel_crtc(state->dev, intel_crtc) {
9483 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9484 if (IS_ERR(crtc_state))
9485 return PTR_ERR(crtc_state);
9487 if (!crtc_state->base.enable)
9490 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9492 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9493 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9494 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9496 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9499 return max_pixel_rate;
9502 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9504 struct drm_i915_private *dev_priv = dev->dev_private;
9508 if (WARN((I915_READ(LCPLL_CTL) &
9509 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9510 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9511 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9512 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9513 "trying to change cdclk frequency with cdclk not enabled\n"))
9516 mutex_lock(&dev_priv->rps.hw_lock);
9517 ret = sandybridge_pcode_write(dev_priv,
9518 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9519 mutex_unlock(&dev_priv->rps.hw_lock);
9521 DRM_ERROR("failed to inform pcode about cdclk change\n");
9525 val = I915_READ(LCPLL_CTL);
9526 val |= LCPLL_CD_SOURCE_FCLK;
9527 I915_WRITE(LCPLL_CTL, val);
9529 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9530 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9531 DRM_ERROR("Switching to FCLK failed\n");
9533 val = I915_READ(LCPLL_CTL);
9534 val &= ~LCPLL_CLK_FREQ_MASK;
9538 val |= LCPLL_CLK_FREQ_450;
9542 val |= LCPLL_CLK_FREQ_54O_BDW;
9546 val |= LCPLL_CLK_FREQ_337_5_BDW;
9550 val |= LCPLL_CLK_FREQ_675_BDW;
9554 WARN(1, "invalid cdclk frequency\n");
9558 I915_WRITE(LCPLL_CTL, val);
9560 val = I915_READ(LCPLL_CTL);
9561 val &= ~LCPLL_CD_SOURCE_FCLK;
9562 I915_WRITE(LCPLL_CTL, val);
9564 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9565 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9566 DRM_ERROR("Switching back to LCPLL failed\n");
9568 mutex_lock(&dev_priv->rps.hw_lock);
9569 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9570 mutex_unlock(&dev_priv->rps.hw_lock);
9572 intel_update_cdclk(dev);
9574 WARN(cdclk != dev_priv->cdclk_freq,
9575 "cdclk requested %d kHz but got %d kHz\n",
9576 cdclk, dev_priv->cdclk_freq);
9579 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9581 struct drm_i915_private *dev_priv = to_i915(state->dev);
9582 int max_pixclk = ilk_max_pixel_rate(state);
9586 * FIXME should also account for plane ratio
9587 * once 64bpp pixel formats are supported.
9589 if (max_pixclk > 540000)
9591 else if (max_pixclk > 450000)
9593 else if (max_pixclk > 337500)
9599 * FIXME move the cdclk caclulation to
9600 * compute_config() so we can fail gracegully.
9602 if (cdclk > dev_priv->max_cdclk_freq) {
9603 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9604 cdclk, dev_priv->max_cdclk_freq);
9605 cdclk = dev_priv->max_cdclk_freq;
9608 to_intel_atomic_state(state)->cdclk = cdclk;
9613 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9615 struct drm_device *dev = old_state->dev;
9616 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9618 broadwell_set_cdclk(dev, req_cdclk);
9621 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9622 struct intel_crtc_state *crtc_state)
9624 if (!intel_ddi_pll_select(crtc, crtc_state))
9627 crtc->lowfreq_avail = false;
9632 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9634 struct intel_crtc_state *pipe_config)
9638 pipe_config->ddi_pll_sel = SKL_DPLL0;
9639 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9642 pipe_config->ddi_pll_sel = SKL_DPLL1;
9643 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9646 pipe_config->ddi_pll_sel = SKL_DPLL2;
9647 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9650 DRM_ERROR("Incorrect port type\n");
9654 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9656 struct intel_crtc_state *pipe_config)
9658 u32 temp, dpll_ctl1;
9660 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9661 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9663 switch (pipe_config->ddi_pll_sel) {
9666 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9667 * of the shared DPLL framework and thus needs to be read out
9670 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9671 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9674 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9677 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9680 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9685 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9687 struct intel_crtc_state *pipe_config)
9689 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9691 switch (pipe_config->ddi_pll_sel) {
9692 case PORT_CLK_SEL_WRPLL1:
9693 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9695 case PORT_CLK_SEL_WRPLL2:
9696 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9701 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9702 struct intel_crtc_state *pipe_config)
9704 struct drm_device *dev = crtc->base.dev;
9705 struct drm_i915_private *dev_priv = dev->dev_private;
9706 struct intel_shared_dpll *pll;
9710 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9712 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9714 if (IS_SKYLAKE(dev))
9715 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9716 else if (IS_BROXTON(dev))
9717 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9719 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9721 if (pipe_config->shared_dpll >= 0) {
9722 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9724 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9725 &pipe_config->dpll_hw_state));
9729 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9730 * DDI E. So just check whether this pipe is wired to DDI E and whether
9731 * the PCH transcoder is on.
9733 if (INTEL_INFO(dev)->gen < 9 &&
9734 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9735 pipe_config->has_pch_encoder = true;
9737 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9738 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9739 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9741 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9745 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9746 struct intel_crtc_state *pipe_config)
9748 struct drm_device *dev = crtc->base.dev;
9749 struct drm_i915_private *dev_priv = dev->dev_private;
9750 enum intel_display_power_domain pfit_domain;
9753 if (!intel_display_power_is_enabled(dev_priv,
9754 POWER_DOMAIN_PIPE(crtc->pipe)))
9757 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9758 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9760 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9761 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9762 enum pipe trans_edp_pipe;
9763 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9765 WARN(1, "unknown pipe linked to edp transcoder\n");
9766 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9767 case TRANS_DDI_EDP_INPUT_A_ON:
9768 trans_edp_pipe = PIPE_A;
9770 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9771 trans_edp_pipe = PIPE_B;
9773 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9774 trans_edp_pipe = PIPE_C;
9778 if (trans_edp_pipe == crtc->pipe)
9779 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9782 if (!intel_display_power_is_enabled(dev_priv,
9783 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9786 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9787 if (!(tmp & PIPECONF_ENABLE))
9790 haswell_get_ddi_port_state(crtc, pipe_config);
9792 intel_get_pipe_timings(crtc, pipe_config);
9794 if (INTEL_INFO(dev)->gen >= 9) {
9795 skl_init_scalers(dev, crtc, pipe_config);
9798 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9800 if (INTEL_INFO(dev)->gen >= 9) {
9801 pipe_config->scaler_state.scaler_id = -1;
9802 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9805 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9806 if (INTEL_INFO(dev)->gen == 9)
9807 skylake_get_pfit_config(crtc, pipe_config);
9808 else if (INTEL_INFO(dev)->gen < 9)
9809 ironlake_get_pfit_config(crtc, pipe_config);
9811 MISSING_CASE(INTEL_INFO(dev)->gen);
9814 if (IS_HASWELL(dev))
9815 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9816 (I915_READ(IPS_CTL) & IPS_ENABLE);
9818 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9819 pipe_config->pixel_multiplier =
9820 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9822 pipe_config->pixel_multiplier = 1;
9828 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9830 struct drm_device *dev = crtc->dev;
9831 struct drm_i915_private *dev_priv = dev->dev_private;
9832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9833 uint32_t cntl = 0, size = 0;
9836 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9837 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9838 unsigned int stride = roundup_pow_of_two(width) * 4;
9842 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9853 cntl |= CURSOR_ENABLE |
9854 CURSOR_GAMMA_ENABLE |
9855 CURSOR_FORMAT_ARGB |
9856 CURSOR_STRIDE(stride);
9858 size = (height << 12) | width;
9861 if (intel_crtc->cursor_cntl != 0 &&
9862 (intel_crtc->cursor_base != base ||
9863 intel_crtc->cursor_size != size ||
9864 intel_crtc->cursor_cntl != cntl)) {
9865 /* On these chipsets we can only modify the base/size/stride
9866 * whilst the cursor is disabled.
9868 I915_WRITE(_CURACNTR, 0);
9869 POSTING_READ(_CURACNTR);
9870 intel_crtc->cursor_cntl = 0;
9873 if (intel_crtc->cursor_base != base) {
9874 I915_WRITE(_CURABASE, base);
9875 intel_crtc->cursor_base = base;
9878 if (intel_crtc->cursor_size != size) {
9879 I915_WRITE(CURSIZE, size);
9880 intel_crtc->cursor_size = size;
9883 if (intel_crtc->cursor_cntl != cntl) {
9884 I915_WRITE(_CURACNTR, cntl);
9885 POSTING_READ(_CURACNTR);
9886 intel_crtc->cursor_cntl = cntl;
9890 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9892 struct drm_device *dev = crtc->dev;
9893 struct drm_i915_private *dev_priv = dev->dev_private;
9894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9895 int pipe = intel_crtc->pipe;
9900 cntl = MCURSOR_GAMMA_ENABLE;
9901 switch (intel_crtc->base.cursor->state->crtc_w) {
9903 cntl |= CURSOR_MODE_64_ARGB_AX;
9906 cntl |= CURSOR_MODE_128_ARGB_AX;
9909 cntl |= CURSOR_MODE_256_ARGB_AX;
9912 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9915 cntl |= pipe << 28; /* Connect to correct pipe */
9917 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9918 cntl |= CURSOR_PIPE_CSC_ENABLE;
9921 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9922 cntl |= CURSOR_ROTATE_180;
9924 if (intel_crtc->cursor_cntl != cntl) {
9925 I915_WRITE(CURCNTR(pipe), cntl);
9926 POSTING_READ(CURCNTR(pipe));
9927 intel_crtc->cursor_cntl = cntl;
9930 /* and commit changes on next vblank */
9931 I915_WRITE(CURBASE(pipe), base);
9932 POSTING_READ(CURBASE(pipe));
9934 intel_crtc->cursor_base = base;
9937 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9938 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9941 struct drm_device *dev = crtc->dev;
9942 struct drm_i915_private *dev_priv = dev->dev_private;
9943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9944 int pipe = intel_crtc->pipe;
9945 int x = crtc->cursor_x;
9946 int y = crtc->cursor_y;
9947 u32 base = 0, pos = 0;
9950 base = intel_crtc->cursor_addr;
9952 if (x >= intel_crtc->config->pipe_src_w)
9955 if (y >= intel_crtc->config->pipe_src_h)
9959 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9962 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9965 pos |= x << CURSOR_X_SHIFT;
9968 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9971 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9974 pos |= y << CURSOR_Y_SHIFT;
9976 if (base == 0 && intel_crtc->cursor_base == 0)
9979 I915_WRITE(CURPOS(pipe), pos);
9981 /* ILK+ do this automagically */
9982 if (HAS_GMCH_DISPLAY(dev) &&
9983 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9984 base += (intel_crtc->base.cursor->state->crtc_h *
9985 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9988 if (IS_845G(dev) || IS_I865G(dev))
9989 i845_update_cursor(crtc, base);
9991 i9xx_update_cursor(crtc, base);
9994 static bool cursor_size_ok(struct drm_device *dev,
9995 uint32_t width, uint32_t height)
9997 if (width == 0 || height == 0)
10001 * 845g/865g are special in that they are only limited by
10002 * the width of their cursors, the height is arbitrary up to
10003 * the precision of the register. Everything else requires
10004 * square cursors, limited to a few power-of-two sizes.
10006 if (IS_845G(dev) || IS_I865G(dev)) {
10007 if ((width & 63) != 0)
10010 if (width > (IS_845G(dev) ? 64 : 512))
10016 switch (width | height) {
10031 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10032 u16 *blue, uint32_t start, uint32_t size)
10034 int end = (start + size > 256) ? 256 : start + size, i;
10035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10037 for (i = start; i < end; i++) {
10038 intel_crtc->lut_r[i] = red[i] >> 8;
10039 intel_crtc->lut_g[i] = green[i] >> 8;
10040 intel_crtc->lut_b[i] = blue[i] >> 8;
10043 intel_crtc_load_lut(crtc);
10046 /* VESA 640x480x72Hz mode to set on the pipe */
10047 static struct drm_display_mode load_detect_mode = {
10048 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10049 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10052 struct drm_framebuffer *
10053 __intel_framebuffer_create(struct drm_device *dev,
10054 struct drm_mode_fb_cmd2 *mode_cmd,
10055 struct drm_i915_gem_object *obj)
10057 struct intel_framebuffer *intel_fb;
10060 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10062 drm_gem_object_unreference(&obj->base);
10063 return ERR_PTR(-ENOMEM);
10066 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10070 return &intel_fb->base;
10072 drm_gem_object_unreference(&obj->base);
10075 return ERR_PTR(ret);
10078 static struct drm_framebuffer *
10079 intel_framebuffer_create(struct drm_device *dev,
10080 struct drm_mode_fb_cmd2 *mode_cmd,
10081 struct drm_i915_gem_object *obj)
10083 struct drm_framebuffer *fb;
10086 ret = i915_mutex_lock_interruptible(dev);
10088 return ERR_PTR(ret);
10089 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10090 mutex_unlock(&dev->struct_mutex);
10096 intel_framebuffer_pitch_for_width(int width, int bpp)
10098 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10099 return ALIGN(pitch, 64);
10103 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10105 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10106 return PAGE_ALIGN(pitch * mode->vdisplay);
10109 static struct drm_framebuffer *
10110 intel_framebuffer_create_for_mode(struct drm_device *dev,
10111 struct drm_display_mode *mode,
10112 int depth, int bpp)
10114 struct drm_i915_gem_object *obj;
10115 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10117 obj = i915_gem_alloc_object(dev,
10118 intel_framebuffer_size_for_mode(mode, bpp));
10120 return ERR_PTR(-ENOMEM);
10122 mode_cmd.width = mode->hdisplay;
10123 mode_cmd.height = mode->vdisplay;
10124 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10126 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10128 return intel_framebuffer_create(dev, &mode_cmd, obj);
10131 static struct drm_framebuffer *
10132 mode_fits_in_fbdev(struct drm_device *dev,
10133 struct drm_display_mode *mode)
10135 #ifdef CONFIG_DRM_FBDEV_EMULATION
10136 struct drm_i915_private *dev_priv = dev->dev_private;
10137 struct drm_i915_gem_object *obj;
10138 struct drm_framebuffer *fb;
10140 if (!dev_priv->fbdev)
10143 if (!dev_priv->fbdev->fb)
10146 obj = dev_priv->fbdev->fb->obj;
10149 fb = &dev_priv->fbdev->fb->base;
10150 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10151 fb->bits_per_pixel))
10154 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10163 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10164 struct drm_crtc *crtc,
10165 struct drm_display_mode *mode,
10166 struct drm_framebuffer *fb,
10169 struct drm_plane_state *plane_state;
10170 int hdisplay, vdisplay;
10173 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10174 if (IS_ERR(plane_state))
10175 return PTR_ERR(plane_state);
10178 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10180 hdisplay = vdisplay = 0;
10182 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10185 drm_atomic_set_fb_for_plane(plane_state, fb);
10186 plane_state->crtc_x = 0;
10187 plane_state->crtc_y = 0;
10188 plane_state->crtc_w = hdisplay;
10189 plane_state->crtc_h = vdisplay;
10190 plane_state->src_x = x << 16;
10191 plane_state->src_y = y << 16;
10192 plane_state->src_w = hdisplay << 16;
10193 plane_state->src_h = vdisplay << 16;
10198 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10199 struct drm_display_mode *mode,
10200 struct intel_load_detect_pipe *old,
10201 struct drm_modeset_acquire_ctx *ctx)
10203 struct intel_crtc *intel_crtc;
10204 struct intel_encoder *intel_encoder =
10205 intel_attached_encoder(connector);
10206 struct drm_crtc *possible_crtc;
10207 struct drm_encoder *encoder = &intel_encoder->base;
10208 struct drm_crtc *crtc = NULL;
10209 struct drm_device *dev = encoder->dev;
10210 struct drm_framebuffer *fb;
10211 struct drm_mode_config *config = &dev->mode_config;
10212 struct drm_atomic_state *state = NULL;
10213 struct drm_connector_state *connector_state;
10214 struct intel_crtc_state *crtc_state;
10217 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10218 connector->base.id, connector->name,
10219 encoder->base.id, encoder->name);
10222 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10227 * Algorithm gets a little messy:
10229 * - if the connector already has an assigned crtc, use it (but make
10230 * sure it's on first)
10232 * - try to find the first unused crtc that can drive this connector,
10233 * and use that if we find one
10236 /* See if we already have a CRTC for this connector */
10237 if (encoder->crtc) {
10238 crtc = encoder->crtc;
10240 ret = drm_modeset_lock(&crtc->mutex, ctx);
10243 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10247 old->dpms_mode = connector->dpms;
10248 old->load_detect_temp = false;
10250 /* Make sure the crtc and connector are running */
10251 if (connector->dpms != DRM_MODE_DPMS_ON)
10252 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10257 /* Find an unused one (if possible) */
10258 for_each_crtc(dev, possible_crtc) {
10260 if (!(encoder->possible_crtcs & (1 << i)))
10262 if (possible_crtc->state->enable)
10265 crtc = possible_crtc;
10270 * If we didn't find an unused CRTC, don't use any.
10273 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10277 ret = drm_modeset_lock(&crtc->mutex, ctx);
10280 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10284 intel_crtc = to_intel_crtc(crtc);
10285 old->dpms_mode = connector->dpms;
10286 old->load_detect_temp = true;
10287 old->release_fb = NULL;
10289 state = drm_atomic_state_alloc(dev);
10293 state->acquire_ctx = ctx;
10295 connector_state = drm_atomic_get_connector_state(state, connector);
10296 if (IS_ERR(connector_state)) {
10297 ret = PTR_ERR(connector_state);
10301 connector_state->crtc = crtc;
10302 connector_state->best_encoder = &intel_encoder->base;
10304 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10305 if (IS_ERR(crtc_state)) {
10306 ret = PTR_ERR(crtc_state);
10310 crtc_state->base.active = crtc_state->base.enable = true;
10313 mode = &load_detect_mode;
10315 /* We need a framebuffer large enough to accommodate all accesses
10316 * that the plane may generate whilst we perform load detection.
10317 * We can not rely on the fbcon either being present (we get called
10318 * during its initialisation to detect all boot displays, or it may
10319 * not even exist) or that it is large enough to satisfy the
10322 fb = mode_fits_in_fbdev(dev, mode);
10324 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10325 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10326 old->release_fb = fb;
10328 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10330 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10334 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10338 drm_mode_copy(&crtc_state->base.mode, mode);
10340 if (drm_atomic_commit(state)) {
10341 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10342 if (old->release_fb)
10343 old->release_fb->funcs->destroy(old->release_fb);
10346 crtc->primary->crtc = crtc;
10348 /* let the connector get through one full cycle before testing */
10349 intel_wait_for_vblank(dev, intel_crtc->pipe);
10353 drm_atomic_state_free(state);
10356 if (ret == -EDEADLK) {
10357 drm_modeset_backoff(ctx);
10364 void intel_release_load_detect_pipe(struct drm_connector *connector,
10365 struct intel_load_detect_pipe *old,
10366 struct drm_modeset_acquire_ctx *ctx)
10368 struct drm_device *dev = connector->dev;
10369 struct intel_encoder *intel_encoder =
10370 intel_attached_encoder(connector);
10371 struct drm_encoder *encoder = &intel_encoder->base;
10372 struct drm_crtc *crtc = encoder->crtc;
10373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10374 struct drm_atomic_state *state;
10375 struct drm_connector_state *connector_state;
10376 struct intel_crtc_state *crtc_state;
10379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10380 connector->base.id, connector->name,
10381 encoder->base.id, encoder->name);
10383 if (old->load_detect_temp) {
10384 state = drm_atomic_state_alloc(dev);
10388 state->acquire_ctx = ctx;
10390 connector_state = drm_atomic_get_connector_state(state, connector);
10391 if (IS_ERR(connector_state))
10394 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10395 if (IS_ERR(crtc_state))
10398 connector_state->best_encoder = NULL;
10399 connector_state->crtc = NULL;
10401 crtc_state->base.enable = crtc_state->base.active = false;
10403 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10408 ret = drm_atomic_commit(state);
10412 if (old->release_fb) {
10413 drm_framebuffer_unregister_private(old->release_fb);
10414 drm_framebuffer_unreference(old->release_fb);
10420 /* Switch crtc and encoder back off if necessary */
10421 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10422 connector->funcs->dpms(connector, old->dpms_mode);
10426 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10427 drm_atomic_state_free(state);
10430 static int i9xx_pll_refclk(struct drm_device *dev,
10431 const struct intel_crtc_state *pipe_config)
10433 struct drm_i915_private *dev_priv = dev->dev_private;
10434 u32 dpll = pipe_config->dpll_hw_state.dpll;
10436 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10437 return dev_priv->vbt.lvds_ssc_freq;
10438 else if (HAS_PCH_SPLIT(dev))
10440 else if (!IS_GEN2(dev))
10446 /* Returns the clock of the currently programmed mode of the given pipe. */
10447 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10448 struct intel_crtc_state *pipe_config)
10450 struct drm_device *dev = crtc->base.dev;
10451 struct drm_i915_private *dev_priv = dev->dev_private;
10452 int pipe = pipe_config->cpu_transcoder;
10453 u32 dpll = pipe_config->dpll_hw_state.dpll;
10455 intel_clock_t clock;
10457 int refclk = i9xx_pll_refclk(dev, pipe_config);
10459 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10460 fp = pipe_config->dpll_hw_state.fp0;
10462 fp = pipe_config->dpll_hw_state.fp1;
10464 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10465 if (IS_PINEVIEW(dev)) {
10466 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10467 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10469 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10470 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10473 if (!IS_GEN2(dev)) {
10474 if (IS_PINEVIEW(dev))
10475 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10476 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10478 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10479 DPLL_FPA01_P1_POST_DIV_SHIFT);
10481 switch (dpll & DPLL_MODE_MASK) {
10482 case DPLLB_MODE_DAC_SERIAL:
10483 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10486 case DPLLB_MODE_LVDS:
10487 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10491 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10492 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10496 if (IS_PINEVIEW(dev))
10497 port_clock = pnv_calc_dpll_params(refclk, &clock);
10499 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10501 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10502 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10505 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10506 DPLL_FPA01_P1_POST_DIV_SHIFT);
10508 if (lvds & LVDS_CLKB_POWER_UP)
10513 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10516 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10517 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10519 if (dpll & PLL_P2_DIVIDE_BY_4)
10525 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10529 * This value includes pixel_multiplier. We will use
10530 * port_clock to compute adjusted_mode.crtc_clock in the
10531 * encoder's get_config() function.
10533 pipe_config->port_clock = port_clock;
10536 int intel_dotclock_calculate(int link_freq,
10537 const struct intel_link_m_n *m_n)
10540 * The calculation for the data clock is:
10541 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10542 * But we want to avoid losing precison if possible, so:
10543 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10545 * and the link clock is simpler:
10546 * link_clock = (m * link_clock) / n
10552 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10555 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10556 struct intel_crtc_state *pipe_config)
10558 struct drm_device *dev = crtc->base.dev;
10560 /* read out port_clock from the DPLL */
10561 i9xx_crtc_clock_get(crtc, pipe_config);
10564 * This value does not include pixel_multiplier.
10565 * We will check that port_clock and adjusted_mode.crtc_clock
10566 * agree once we know their relationship in the encoder's
10567 * get_config() function.
10569 pipe_config->base.adjusted_mode.crtc_clock =
10570 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10571 &pipe_config->fdi_m_n);
10574 /** Returns the currently programmed mode of the given pipe. */
10575 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10576 struct drm_crtc *crtc)
10578 struct drm_i915_private *dev_priv = dev->dev_private;
10579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10580 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10581 struct drm_display_mode *mode;
10582 struct intel_crtc_state pipe_config;
10583 int htot = I915_READ(HTOTAL(cpu_transcoder));
10584 int hsync = I915_READ(HSYNC(cpu_transcoder));
10585 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10586 int vsync = I915_READ(VSYNC(cpu_transcoder));
10587 enum pipe pipe = intel_crtc->pipe;
10589 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10594 * Construct a pipe_config sufficient for getting the clock info
10595 * back out of crtc_clock_get.
10597 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10598 * to use a real value here instead.
10600 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10601 pipe_config.pixel_multiplier = 1;
10602 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10603 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10604 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10605 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10607 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10608 mode->hdisplay = (htot & 0xffff) + 1;
10609 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10610 mode->hsync_start = (hsync & 0xffff) + 1;
10611 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10612 mode->vdisplay = (vtot & 0xffff) + 1;
10613 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10614 mode->vsync_start = (vsync & 0xffff) + 1;
10615 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10617 drm_mode_set_name(mode);
10622 void intel_mark_busy(struct drm_device *dev)
10624 struct drm_i915_private *dev_priv = dev->dev_private;
10626 if (dev_priv->mm.busy)
10629 intel_runtime_pm_get(dev_priv);
10630 i915_update_gfx_val(dev_priv);
10631 if (INTEL_INFO(dev)->gen >= 6)
10632 gen6_rps_busy(dev_priv);
10633 dev_priv->mm.busy = true;
10636 void intel_mark_idle(struct drm_device *dev)
10638 struct drm_i915_private *dev_priv = dev->dev_private;
10640 if (!dev_priv->mm.busy)
10643 dev_priv->mm.busy = false;
10645 if (INTEL_INFO(dev)->gen >= 6)
10646 gen6_rps_idle(dev->dev_private);
10648 intel_runtime_pm_put(dev_priv);
10651 static void intel_crtc_destroy(struct drm_crtc *crtc)
10653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10654 struct drm_device *dev = crtc->dev;
10655 struct intel_unpin_work *work;
10657 spin_lock_irq(&dev->event_lock);
10658 work = intel_crtc->unpin_work;
10659 intel_crtc->unpin_work = NULL;
10660 spin_unlock_irq(&dev->event_lock);
10663 cancel_work_sync(&work->work);
10667 drm_crtc_cleanup(crtc);
10672 static void intel_unpin_work_fn(struct work_struct *__work)
10674 struct intel_unpin_work *work =
10675 container_of(__work, struct intel_unpin_work, work);
10676 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10677 struct drm_device *dev = crtc->base.dev;
10678 struct drm_plane *primary = crtc->base.primary;
10680 mutex_lock(&dev->struct_mutex);
10681 intel_unpin_fb_obj(work->old_fb, primary->state);
10682 drm_gem_object_unreference(&work->pending_flip_obj->base);
10684 if (work->flip_queued_req)
10685 i915_gem_request_assign(&work->flip_queued_req, NULL);
10686 mutex_unlock(&dev->struct_mutex);
10688 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10689 drm_framebuffer_unreference(work->old_fb);
10691 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10692 atomic_dec(&crtc->unpin_work_count);
10697 static void do_intel_finish_page_flip(struct drm_device *dev,
10698 struct drm_crtc *crtc)
10700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10701 struct intel_unpin_work *work;
10702 unsigned long flags;
10704 /* Ignore early vblank irqs */
10705 if (intel_crtc == NULL)
10709 * This is called both by irq handlers and the reset code (to complete
10710 * lost pageflips) so needs the full irqsave spinlocks.
10712 spin_lock_irqsave(&dev->event_lock, flags);
10713 work = intel_crtc->unpin_work;
10715 /* Ensure we don't miss a work->pending update ... */
10718 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10719 spin_unlock_irqrestore(&dev->event_lock, flags);
10723 page_flip_completed(intel_crtc);
10725 spin_unlock_irqrestore(&dev->event_lock, flags);
10728 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10730 struct drm_i915_private *dev_priv = dev->dev_private;
10731 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10733 do_intel_finish_page_flip(dev, crtc);
10736 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10738 struct drm_i915_private *dev_priv = dev->dev_private;
10739 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10741 do_intel_finish_page_flip(dev, crtc);
10744 /* Is 'a' after or equal to 'b'? */
10745 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10747 return !((a - b) & 0x80000000);
10750 static bool page_flip_finished(struct intel_crtc *crtc)
10752 struct drm_device *dev = crtc->base.dev;
10753 struct drm_i915_private *dev_priv = dev->dev_private;
10755 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10756 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10760 * The relevant registers doen't exist on pre-ctg.
10761 * As the flip done interrupt doesn't trigger for mmio
10762 * flips on gmch platforms, a flip count check isn't
10763 * really needed there. But since ctg has the registers,
10764 * include it in the check anyway.
10766 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10770 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10771 * used the same base address. In that case the mmio flip might
10772 * have completed, but the CS hasn't even executed the flip yet.
10774 * A flip count check isn't enough as the CS might have updated
10775 * the base address just after start of vblank, but before we
10776 * managed to process the interrupt. This means we'd complete the
10777 * CS flip too soon.
10779 * Combining both checks should get us a good enough result. It may
10780 * still happen that the CS flip has been executed, but has not
10781 * yet actually completed. But in case the base address is the same
10782 * anyway, we don't really care.
10784 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10785 crtc->unpin_work->gtt_offset &&
10786 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10787 crtc->unpin_work->flip_count);
10790 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10792 struct drm_i915_private *dev_priv = dev->dev_private;
10793 struct intel_crtc *intel_crtc =
10794 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10795 unsigned long flags;
10799 * This is called both by irq handlers and the reset code (to complete
10800 * lost pageflips) so needs the full irqsave spinlocks.
10802 * NB: An MMIO update of the plane base pointer will also
10803 * generate a page-flip completion irq, i.e. every modeset
10804 * is also accompanied by a spurious intel_prepare_page_flip().
10806 spin_lock_irqsave(&dev->event_lock, flags);
10807 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10808 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10809 spin_unlock_irqrestore(&dev->event_lock, flags);
10812 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10814 /* Ensure that the work item is consistent when activating it ... */
10816 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10817 /* and that it is marked active as soon as the irq could fire. */
10821 static int intel_gen2_queue_flip(struct drm_device *dev,
10822 struct drm_crtc *crtc,
10823 struct drm_framebuffer *fb,
10824 struct drm_i915_gem_object *obj,
10825 struct drm_i915_gem_request *req,
10828 struct intel_engine_cs *ring = req->ring;
10829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10833 ret = intel_ring_begin(req, 6);
10837 /* Can't queue multiple flips, so wait for the previous
10838 * one to finish before executing the next.
10840 if (intel_crtc->plane)
10841 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10843 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10844 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10845 intel_ring_emit(ring, MI_NOOP);
10846 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10847 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10848 intel_ring_emit(ring, fb->pitches[0]);
10849 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10850 intel_ring_emit(ring, 0); /* aux display base address, unused */
10852 intel_mark_page_flip_active(intel_crtc);
10856 static int intel_gen3_queue_flip(struct drm_device *dev,
10857 struct drm_crtc *crtc,
10858 struct drm_framebuffer *fb,
10859 struct drm_i915_gem_object *obj,
10860 struct drm_i915_gem_request *req,
10863 struct intel_engine_cs *ring = req->ring;
10864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10868 ret = intel_ring_begin(req, 6);
10872 if (intel_crtc->plane)
10873 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10875 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10876 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10877 intel_ring_emit(ring, MI_NOOP);
10878 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10879 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10880 intel_ring_emit(ring, fb->pitches[0]);
10881 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10882 intel_ring_emit(ring, MI_NOOP);
10884 intel_mark_page_flip_active(intel_crtc);
10888 static int intel_gen4_queue_flip(struct drm_device *dev,
10889 struct drm_crtc *crtc,
10890 struct drm_framebuffer *fb,
10891 struct drm_i915_gem_object *obj,
10892 struct drm_i915_gem_request *req,
10895 struct intel_engine_cs *ring = req->ring;
10896 struct drm_i915_private *dev_priv = dev->dev_private;
10897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10898 uint32_t pf, pipesrc;
10901 ret = intel_ring_begin(req, 4);
10905 /* i965+ uses the linear or tiled offsets from the
10906 * Display Registers (which do not change across a page-flip)
10907 * so we need only reprogram the base address.
10909 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10910 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10911 intel_ring_emit(ring, fb->pitches[0]);
10912 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10915 /* XXX Enabling the panel-fitter across page-flip is so far
10916 * untested on non-native modes, so ignore it for now.
10917 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10920 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10921 intel_ring_emit(ring, pf | pipesrc);
10923 intel_mark_page_flip_active(intel_crtc);
10927 static int intel_gen6_queue_flip(struct drm_device *dev,
10928 struct drm_crtc *crtc,
10929 struct drm_framebuffer *fb,
10930 struct drm_i915_gem_object *obj,
10931 struct drm_i915_gem_request *req,
10934 struct intel_engine_cs *ring = req->ring;
10935 struct drm_i915_private *dev_priv = dev->dev_private;
10936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10937 uint32_t pf, pipesrc;
10940 ret = intel_ring_begin(req, 4);
10944 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10945 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10946 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10947 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10949 /* Contrary to the suggestions in the documentation,
10950 * "Enable Panel Fitter" does not seem to be required when page
10951 * flipping with a non-native mode, and worse causes a normal
10953 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10956 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10957 intel_ring_emit(ring, pf | pipesrc);
10959 intel_mark_page_flip_active(intel_crtc);
10963 static int intel_gen7_queue_flip(struct drm_device *dev,
10964 struct drm_crtc *crtc,
10965 struct drm_framebuffer *fb,
10966 struct drm_i915_gem_object *obj,
10967 struct drm_i915_gem_request *req,
10970 struct intel_engine_cs *ring = req->ring;
10971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10972 uint32_t plane_bit = 0;
10975 switch (intel_crtc->plane) {
10977 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10980 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10983 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10986 WARN_ONCE(1, "unknown plane in flip command\n");
10991 if (ring->id == RCS) {
10994 * On Gen 8, SRM is now taking an extra dword to accommodate
10995 * 48bits addresses, and we need a NOOP for the batch size to
11003 * BSpec MI_DISPLAY_FLIP for IVB:
11004 * "The full packet must be contained within the same cache line."
11006 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11007 * cacheline, if we ever start emitting more commands before
11008 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11009 * then do the cacheline alignment, and finally emit the
11012 ret = intel_ring_cacheline_align(req);
11016 ret = intel_ring_begin(req, len);
11020 /* Unmask the flip-done completion message. Note that the bspec says that
11021 * we should do this for both the BCS and RCS, and that we must not unmask
11022 * more than one flip event at any time (or ensure that one flip message
11023 * can be sent by waiting for flip-done prior to queueing new flips).
11024 * Experimentation says that BCS works despite DERRMR masking all
11025 * flip-done completion events and that unmasking all planes at once
11026 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11027 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11029 if (ring->id == RCS) {
11030 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11031 intel_ring_emit(ring, DERRMR);
11032 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11033 DERRMR_PIPEB_PRI_FLIP_DONE |
11034 DERRMR_PIPEC_PRI_FLIP_DONE));
11036 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11037 MI_SRM_LRM_GLOBAL_GTT);
11039 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11040 MI_SRM_LRM_GLOBAL_GTT);
11041 intel_ring_emit(ring, DERRMR);
11042 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11043 if (IS_GEN8(dev)) {
11044 intel_ring_emit(ring, 0);
11045 intel_ring_emit(ring, MI_NOOP);
11049 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11050 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11051 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11052 intel_ring_emit(ring, (MI_NOOP));
11054 intel_mark_page_flip_active(intel_crtc);
11058 static bool use_mmio_flip(struct intel_engine_cs *ring,
11059 struct drm_i915_gem_object *obj)
11062 * This is not being used for older platforms, because
11063 * non-availability of flip done interrupt forces us to use
11064 * CS flips. Older platforms derive flip done using some clever
11065 * tricks involving the flip_pending status bits and vblank irqs.
11066 * So using MMIO flips there would disrupt this mechanism.
11072 if (INTEL_INFO(ring->dev)->gen < 5)
11075 if (i915.use_mmio_flip < 0)
11077 else if (i915.use_mmio_flip > 0)
11079 else if (i915.enable_execlists)
11082 return ring != i915_gem_request_get_ring(obj->last_write_req);
11085 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11087 struct drm_device *dev = intel_crtc->base.dev;
11088 struct drm_i915_private *dev_priv = dev->dev_private;
11089 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11090 const enum pipe pipe = intel_crtc->pipe;
11093 ctl = I915_READ(PLANE_CTL(pipe, 0));
11094 ctl &= ~PLANE_CTL_TILED_MASK;
11095 switch (fb->modifier[0]) {
11096 case DRM_FORMAT_MOD_NONE:
11098 case I915_FORMAT_MOD_X_TILED:
11099 ctl |= PLANE_CTL_TILED_X;
11101 case I915_FORMAT_MOD_Y_TILED:
11102 ctl |= PLANE_CTL_TILED_Y;
11104 case I915_FORMAT_MOD_Yf_TILED:
11105 ctl |= PLANE_CTL_TILED_YF;
11108 MISSING_CASE(fb->modifier[0]);
11112 * The stride is either expressed as a multiple of 64 bytes chunks for
11113 * linear buffers or in number of tiles for tiled buffers.
11115 stride = fb->pitches[0] /
11116 intel_fb_stride_alignment(dev, fb->modifier[0],
11120 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11121 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11123 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11124 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11126 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11127 POSTING_READ(PLANE_SURF(pipe, 0));
11130 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11132 struct drm_device *dev = intel_crtc->base.dev;
11133 struct drm_i915_private *dev_priv = dev->dev_private;
11134 struct intel_framebuffer *intel_fb =
11135 to_intel_framebuffer(intel_crtc->base.primary->fb);
11136 struct drm_i915_gem_object *obj = intel_fb->obj;
11140 reg = DSPCNTR(intel_crtc->plane);
11141 dspcntr = I915_READ(reg);
11143 if (obj->tiling_mode != I915_TILING_NONE)
11144 dspcntr |= DISPPLANE_TILED;
11146 dspcntr &= ~DISPPLANE_TILED;
11148 I915_WRITE(reg, dspcntr);
11150 I915_WRITE(DSPSURF(intel_crtc->plane),
11151 intel_crtc->unpin_work->gtt_offset);
11152 POSTING_READ(DSPSURF(intel_crtc->plane));
11157 * XXX: This is the temporary way to update the plane registers until we get
11158 * around to using the usual plane update functions for MMIO flips
11160 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11162 struct drm_device *dev = intel_crtc->base.dev;
11163 u32 start_vbl_count;
11165 intel_mark_page_flip_active(intel_crtc);
11167 intel_pipe_update_start(intel_crtc, &start_vbl_count);
11169 if (INTEL_INFO(dev)->gen >= 9)
11170 skl_do_mmio_flip(intel_crtc);
11172 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11173 ilk_do_mmio_flip(intel_crtc);
11175 intel_pipe_update_end(intel_crtc, start_vbl_count);
11178 static void intel_mmio_flip_work_func(struct work_struct *work)
11180 struct intel_mmio_flip *mmio_flip =
11181 container_of(work, struct intel_mmio_flip, work);
11183 if (mmio_flip->req)
11184 WARN_ON(__i915_wait_request(mmio_flip->req,
11185 mmio_flip->crtc->reset_counter,
11187 &mmio_flip->i915->rps.mmioflips));
11189 intel_do_mmio_flip(mmio_flip->crtc);
11191 i915_gem_request_unreference__unlocked(mmio_flip->req);
11195 static int intel_queue_mmio_flip(struct drm_device *dev,
11196 struct drm_crtc *crtc,
11197 struct drm_framebuffer *fb,
11198 struct drm_i915_gem_object *obj,
11199 struct intel_engine_cs *ring,
11202 struct intel_mmio_flip *mmio_flip;
11204 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11205 if (mmio_flip == NULL)
11208 mmio_flip->i915 = to_i915(dev);
11209 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11210 mmio_flip->crtc = to_intel_crtc(crtc);
11212 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11213 schedule_work(&mmio_flip->work);
11218 static int intel_default_queue_flip(struct drm_device *dev,
11219 struct drm_crtc *crtc,
11220 struct drm_framebuffer *fb,
11221 struct drm_i915_gem_object *obj,
11222 struct drm_i915_gem_request *req,
11228 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11229 struct drm_crtc *crtc)
11231 struct drm_i915_private *dev_priv = dev->dev_private;
11232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11233 struct intel_unpin_work *work = intel_crtc->unpin_work;
11236 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11239 if (!work->enable_stall_check)
11242 if (work->flip_ready_vblank == 0) {
11243 if (work->flip_queued_req &&
11244 !i915_gem_request_completed(work->flip_queued_req, true))
11247 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11250 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11253 /* Potential stall - if we see that the flip has happened,
11254 * assume a missed interrupt. */
11255 if (INTEL_INFO(dev)->gen >= 4)
11256 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11258 addr = I915_READ(DSPADDR(intel_crtc->plane));
11260 /* There is a potential issue here with a false positive after a flip
11261 * to the same address. We could address this by checking for a
11262 * non-incrementing frame counter.
11264 return addr == work->gtt_offset;
11267 void intel_check_page_flip(struct drm_device *dev, int pipe)
11269 struct drm_i915_private *dev_priv = dev->dev_private;
11270 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11272 struct intel_unpin_work *work;
11274 WARN_ON(!in_interrupt());
11279 spin_lock(&dev->event_lock);
11280 work = intel_crtc->unpin_work;
11281 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11282 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11283 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11284 page_flip_completed(intel_crtc);
11287 if (work != NULL &&
11288 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11289 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11290 spin_unlock(&dev->event_lock);
11293 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11294 struct drm_framebuffer *fb,
11295 struct drm_pending_vblank_event *event,
11296 uint32_t page_flip_flags)
11298 struct drm_device *dev = crtc->dev;
11299 struct drm_i915_private *dev_priv = dev->dev_private;
11300 struct drm_framebuffer *old_fb = crtc->primary->fb;
11301 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11303 struct drm_plane *primary = crtc->primary;
11304 enum pipe pipe = intel_crtc->pipe;
11305 struct intel_unpin_work *work;
11306 struct intel_engine_cs *ring;
11308 struct drm_i915_gem_request *request = NULL;
11312 * drm_mode_page_flip_ioctl() should already catch this, but double
11313 * check to be safe. In the future we may enable pageflipping from
11314 * a disabled primary plane.
11316 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11319 /* Can't change pixel format via MI display flips. */
11320 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11324 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11325 * Note that pitch changes could also affect these register.
11327 if (INTEL_INFO(dev)->gen > 3 &&
11328 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11329 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11332 if (i915_terminally_wedged(&dev_priv->gpu_error))
11335 work = kzalloc(sizeof(*work), GFP_KERNEL);
11339 work->event = event;
11341 work->old_fb = old_fb;
11342 INIT_WORK(&work->work, intel_unpin_work_fn);
11344 ret = drm_crtc_vblank_get(crtc);
11348 /* We borrow the event spin lock for protecting unpin_work */
11349 spin_lock_irq(&dev->event_lock);
11350 if (intel_crtc->unpin_work) {
11351 /* Before declaring the flip queue wedged, check if
11352 * the hardware completed the operation behind our backs.
11354 if (__intel_pageflip_stall_check(dev, crtc)) {
11355 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11356 page_flip_completed(intel_crtc);
11358 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11359 spin_unlock_irq(&dev->event_lock);
11361 drm_crtc_vblank_put(crtc);
11366 intel_crtc->unpin_work = work;
11367 spin_unlock_irq(&dev->event_lock);
11369 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11370 flush_workqueue(dev_priv->wq);
11372 /* Reference the objects for the scheduled work. */
11373 drm_framebuffer_reference(work->old_fb);
11374 drm_gem_object_reference(&obj->base);
11376 crtc->primary->fb = fb;
11377 update_state_fb(crtc->primary);
11379 work->pending_flip_obj = obj;
11381 ret = i915_mutex_lock_interruptible(dev);
11385 atomic_inc(&intel_crtc->unpin_work_count);
11386 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11388 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11389 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11391 if (IS_VALLEYVIEW(dev)) {
11392 ring = &dev_priv->ring[BCS];
11393 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11394 /* vlv: DISPLAY_FLIP fails to change tiling */
11396 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11397 ring = &dev_priv->ring[BCS];
11398 } else if (INTEL_INFO(dev)->gen >= 7) {
11399 ring = i915_gem_request_get_ring(obj->last_write_req);
11400 if (ring == NULL || ring->id != RCS)
11401 ring = &dev_priv->ring[BCS];
11403 ring = &dev_priv->ring[RCS];
11406 mmio_flip = use_mmio_flip(ring, obj);
11408 /* When using CS flips, we want to emit semaphores between rings.
11409 * However, when using mmio flips we will create a task to do the
11410 * synchronisation, so all we want here is to pin the framebuffer
11411 * into the display plane and skip any waits.
11413 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11414 crtc->primary->state,
11415 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11417 goto cleanup_pending;
11419 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11420 + intel_crtc->dspaddr_offset;
11423 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11426 goto cleanup_unpin;
11428 i915_gem_request_assign(&work->flip_queued_req,
11429 obj->last_write_req);
11432 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11434 goto cleanup_unpin;
11437 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11440 goto cleanup_unpin;
11442 i915_gem_request_assign(&work->flip_queued_req, request);
11446 i915_add_request_no_flush(request);
11448 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11449 work->enable_stall_check = true;
11451 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11452 to_intel_plane(primary)->frontbuffer_bit);
11453 mutex_unlock(&dev->struct_mutex);
11455 intel_fbc_disable_crtc(intel_crtc);
11456 intel_frontbuffer_flip_prepare(dev,
11457 to_intel_plane(primary)->frontbuffer_bit);
11459 trace_i915_flip_request(intel_crtc->plane, obj);
11464 intel_unpin_fb_obj(fb, crtc->primary->state);
11467 i915_gem_request_cancel(request);
11468 atomic_dec(&intel_crtc->unpin_work_count);
11469 mutex_unlock(&dev->struct_mutex);
11471 crtc->primary->fb = old_fb;
11472 update_state_fb(crtc->primary);
11474 drm_gem_object_unreference_unlocked(&obj->base);
11475 drm_framebuffer_unreference(work->old_fb);
11477 spin_lock_irq(&dev->event_lock);
11478 intel_crtc->unpin_work = NULL;
11479 spin_unlock_irq(&dev->event_lock);
11481 drm_crtc_vblank_put(crtc);
11486 struct drm_atomic_state *state;
11487 struct drm_plane_state *plane_state;
11490 state = drm_atomic_state_alloc(dev);
11493 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11496 plane_state = drm_atomic_get_plane_state(state, primary);
11497 ret = PTR_ERR_OR_ZERO(plane_state);
11499 drm_atomic_set_fb_for_plane(plane_state, fb);
11501 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11503 ret = drm_atomic_commit(state);
11506 if (ret == -EDEADLK) {
11507 drm_modeset_backoff(state->acquire_ctx);
11508 drm_atomic_state_clear(state);
11513 drm_atomic_state_free(state);
11515 if (ret == 0 && event) {
11516 spin_lock_irq(&dev->event_lock);
11517 drm_send_vblank_event(dev, pipe, event);
11518 spin_unlock_irq(&dev->event_lock);
11526 * intel_wm_need_update - Check whether watermarks need updating
11527 * @plane: drm plane
11528 * @state: new plane state
11530 * Check current plane state versus the new one to determine whether
11531 * watermarks need to be recalculated.
11533 * Returns true or false.
11535 static bool intel_wm_need_update(struct drm_plane *plane,
11536 struct drm_plane_state *state)
11538 /* Update watermarks on tiling changes. */
11539 if (!plane->state->fb || !state->fb ||
11540 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11541 plane->state->rotation != state->rotation)
11544 if (plane->state->crtc_w != state->crtc_w)
11550 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11551 struct drm_plane_state *plane_state)
11553 struct drm_crtc *crtc = crtc_state->crtc;
11554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11555 struct drm_plane *plane = plane_state->plane;
11556 struct drm_device *dev = crtc->dev;
11557 struct drm_i915_private *dev_priv = dev->dev_private;
11558 struct intel_plane_state *old_plane_state =
11559 to_intel_plane_state(plane->state);
11560 int idx = intel_crtc->base.base.id, ret;
11561 int i = drm_plane_index(plane);
11562 bool mode_changed = needs_modeset(crtc_state);
11563 bool was_crtc_enabled = crtc->state->active;
11564 bool is_crtc_enabled = crtc_state->active;
11566 bool turn_off, turn_on, visible, was_visible;
11567 struct drm_framebuffer *fb = plane_state->fb;
11569 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11570 plane->type != DRM_PLANE_TYPE_CURSOR) {
11571 ret = skl_update_scaler_plane(
11572 to_intel_crtc_state(crtc_state),
11573 to_intel_plane_state(plane_state));
11579 * Disabling a plane is always okay; we just need to update
11580 * fb tracking in a special way since cleanup_fb() won't
11581 * get called by the plane helpers.
11583 if (old_plane_state->base.fb && !fb)
11584 intel_crtc->atomic.disabled_planes |= 1 << i;
11586 was_visible = old_plane_state->visible;
11587 visible = to_intel_plane_state(plane_state)->visible;
11589 if (!was_crtc_enabled && WARN_ON(was_visible))
11590 was_visible = false;
11592 if (!is_crtc_enabled && WARN_ON(visible))
11595 if (!was_visible && !visible)
11598 turn_off = was_visible && (!visible || mode_changed);
11599 turn_on = visible && (!was_visible || mode_changed);
11601 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11602 plane->base.id, fb ? fb->base.id : -1);
11604 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11605 plane->base.id, was_visible, visible,
11606 turn_off, turn_on, mode_changed);
11609 intel_crtc->atomic.update_wm_pre = true;
11610 /* must disable cxsr around plane enable/disable */
11611 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11612 intel_crtc->atomic.disable_cxsr = true;
11613 /* to potentially re-enable cxsr */
11614 intel_crtc->atomic.wait_vblank = true;
11615 intel_crtc->atomic.update_wm_post = true;
11617 } else if (turn_off) {
11618 intel_crtc->atomic.update_wm_post = true;
11619 /* must disable cxsr around plane enable/disable */
11620 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11621 if (is_crtc_enabled)
11622 intel_crtc->atomic.wait_vblank = true;
11623 intel_crtc->atomic.disable_cxsr = true;
11625 } else if (intel_wm_need_update(plane, plane_state)) {
11626 intel_crtc->atomic.update_wm_pre = true;
11630 intel_crtc->atomic.fb_bits |=
11631 to_intel_plane(plane)->frontbuffer_bit;
11633 switch (plane->type) {
11634 case DRM_PLANE_TYPE_PRIMARY:
11635 intel_crtc->atomic.wait_for_flips = true;
11636 intel_crtc->atomic.pre_disable_primary = turn_off;
11637 intel_crtc->atomic.post_enable_primary = turn_on;
11641 * FIXME: Actually if we will still have any other
11642 * plane enabled on the pipe we could let IPS enabled
11643 * still, but for now lets consider that when we make
11644 * primary invisible by setting DSPCNTR to 0 on
11645 * update_primary_plane function IPS needs to be
11648 intel_crtc->atomic.disable_ips = true;
11650 intel_crtc->atomic.disable_fbc = true;
11654 * FBC does not work on some platforms for rotated
11655 * planes, so disable it when rotation is not 0 and
11656 * update it when rotation is set back to 0.
11658 * FIXME: This is redundant with the fbc update done in
11659 * the primary plane enable function except that that
11660 * one is done too late. We eventually need to unify
11665 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11666 dev_priv->fbc.crtc == intel_crtc &&
11667 plane_state->rotation != BIT(DRM_ROTATE_0))
11668 intel_crtc->atomic.disable_fbc = true;
11671 * BDW signals flip done immediately if the plane
11672 * is disabled, even if the plane enable is already
11673 * armed to occur at the next vblank :(
11675 if (turn_on && IS_BROADWELL(dev))
11676 intel_crtc->atomic.wait_vblank = true;
11678 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11680 case DRM_PLANE_TYPE_CURSOR:
11682 case DRM_PLANE_TYPE_OVERLAY:
11683 if (turn_off && !mode_changed) {
11684 intel_crtc->atomic.wait_vblank = true;
11685 intel_crtc->atomic.update_sprite_watermarks |=
11692 static bool encoders_cloneable(const struct intel_encoder *a,
11693 const struct intel_encoder *b)
11695 /* masks could be asymmetric, so check both ways */
11696 return a == b || (a->cloneable & (1 << b->type) &&
11697 b->cloneable & (1 << a->type));
11700 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11701 struct intel_crtc *crtc,
11702 struct intel_encoder *encoder)
11704 struct intel_encoder *source_encoder;
11705 struct drm_connector *connector;
11706 struct drm_connector_state *connector_state;
11709 for_each_connector_in_state(state, connector, connector_state, i) {
11710 if (connector_state->crtc != &crtc->base)
11714 to_intel_encoder(connector_state->best_encoder);
11715 if (!encoders_cloneable(encoder, source_encoder))
11722 static bool check_encoder_cloning(struct drm_atomic_state *state,
11723 struct intel_crtc *crtc)
11725 struct intel_encoder *encoder;
11726 struct drm_connector *connector;
11727 struct drm_connector_state *connector_state;
11730 for_each_connector_in_state(state, connector, connector_state, i) {
11731 if (connector_state->crtc != &crtc->base)
11734 encoder = to_intel_encoder(connector_state->best_encoder);
11735 if (!check_single_encoder_cloning(state, crtc, encoder))
11742 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11743 struct drm_crtc_state *crtc_state)
11745 struct drm_device *dev = crtc->dev;
11746 struct drm_i915_private *dev_priv = dev->dev_private;
11747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11748 struct intel_crtc_state *pipe_config =
11749 to_intel_crtc_state(crtc_state);
11750 struct drm_atomic_state *state = crtc_state->state;
11752 bool mode_changed = needs_modeset(crtc_state);
11754 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11755 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11759 if (mode_changed && !crtc_state->active)
11760 intel_crtc->atomic.update_wm_post = true;
11762 if (mode_changed && crtc_state->enable &&
11763 dev_priv->display.crtc_compute_clock &&
11764 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11765 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11772 if (INTEL_INFO(dev)->gen >= 9) {
11774 ret = skl_update_scaler_crtc(pipe_config);
11777 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11784 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11785 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11786 .load_lut = intel_crtc_load_lut,
11787 .atomic_begin = intel_begin_crtc_commit,
11788 .atomic_flush = intel_finish_crtc_commit,
11789 .atomic_check = intel_crtc_atomic_check,
11792 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11794 struct intel_connector *connector;
11796 for_each_intel_connector(dev, connector) {
11797 if (connector->base.encoder) {
11798 connector->base.state->best_encoder =
11799 connector->base.encoder;
11800 connector->base.state->crtc =
11801 connector->base.encoder->crtc;
11803 connector->base.state->best_encoder = NULL;
11804 connector->base.state->crtc = NULL;
11810 connected_sink_compute_bpp(struct intel_connector *connector,
11811 struct intel_crtc_state *pipe_config)
11813 int bpp = pipe_config->pipe_bpp;
11815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11816 connector->base.base.id,
11817 connector->base.name);
11819 /* Don't use an invalid EDID bpc value */
11820 if (connector->base.display_info.bpc &&
11821 connector->base.display_info.bpc * 3 < bpp) {
11822 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11823 bpp, connector->base.display_info.bpc*3);
11824 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11827 /* Clamp bpp to 8 on screens without EDID 1.4 */
11828 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11829 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11831 pipe_config->pipe_bpp = 24;
11836 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11837 struct intel_crtc_state *pipe_config)
11839 struct drm_device *dev = crtc->base.dev;
11840 struct drm_atomic_state *state;
11841 struct drm_connector *connector;
11842 struct drm_connector_state *connector_state;
11845 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11847 else if (INTEL_INFO(dev)->gen >= 5)
11853 pipe_config->pipe_bpp = bpp;
11855 state = pipe_config->base.state;
11857 /* Clamp display bpp to EDID value */
11858 for_each_connector_in_state(state, connector, connector_state, i) {
11859 if (connector_state->crtc != &crtc->base)
11862 connected_sink_compute_bpp(to_intel_connector(connector),
11869 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11871 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11872 "type: 0x%x flags: 0x%x\n",
11874 mode->crtc_hdisplay, mode->crtc_hsync_start,
11875 mode->crtc_hsync_end, mode->crtc_htotal,
11876 mode->crtc_vdisplay, mode->crtc_vsync_start,
11877 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11880 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11881 struct intel_crtc_state *pipe_config,
11882 const char *context)
11884 struct drm_device *dev = crtc->base.dev;
11885 struct drm_plane *plane;
11886 struct intel_plane *intel_plane;
11887 struct intel_plane_state *state;
11888 struct drm_framebuffer *fb;
11890 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11891 context, pipe_config, pipe_name(crtc->pipe));
11893 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11894 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11895 pipe_config->pipe_bpp, pipe_config->dither);
11896 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11897 pipe_config->has_pch_encoder,
11898 pipe_config->fdi_lanes,
11899 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11900 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11901 pipe_config->fdi_m_n.tu);
11902 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11903 pipe_config->has_dp_encoder,
11904 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11905 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11906 pipe_config->dp_m_n.tu);
11908 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11909 pipe_config->has_dp_encoder,
11910 pipe_config->dp_m2_n2.gmch_m,
11911 pipe_config->dp_m2_n2.gmch_n,
11912 pipe_config->dp_m2_n2.link_m,
11913 pipe_config->dp_m2_n2.link_n,
11914 pipe_config->dp_m2_n2.tu);
11916 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11917 pipe_config->has_audio,
11918 pipe_config->has_infoframe);
11920 DRM_DEBUG_KMS("requested mode:\n");
11921 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11922 DRM_DEBUG_KMS("adjusted mode:\n");
11923 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11924 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11925 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11926 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11927 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11928 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11930 pipe_config->scaler_state.scaler_users,
11931 pipe_config->scaler_state.scaler_id);
11932 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11933 pipe_config->gmch_pfit.control,
11934 pipe_config->gmch_pfit.pgm_ratios,
11935 pipe_config->gmch_pfit.lvds_border_bits);
11936 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11937 pipe_config->pch_pfit.pos,
11938 pipe_config->pch_pfit.size,
11939 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11940 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11941 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11943 if (IS_BROXTON(dev)) {
11944 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11945 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11946 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11947 pipe_config->ddi_pll_sel,
11948 pipe_config->dpll_hw_state.ebb0,
11949 pipe_config->dpll_hw_state.ebb4,
11950 pipe_config->dpll_hw_state.pll0,
11951 pipe_config->dpll_hw_state.pll1,
11952 pipe_config->dpll_hw_state.pll2,
11953 pipe_config->dpll_hw_state.pll3,
11954 pipe_config->dpll_hw_state.pll6,
11955 pipe_config->dpll_hw_state.pll8,
11956 pipe_config->dpll_hw_state.pll9,
11957 pipe_config->dpll_hw_state.pll10,
11958 pipe_config->dpll_hw_state.pcsdw12);
11959 } else if (IS_SKYLAKE(dev)) {
11960 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11961 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11962 pipe_config->ddi_pll_sel,
11963 pipe_config->dpll_hw_state.ctrl1,
11964 pipe_config->dpll_hw_state.cfgcr1,
11965 pipe_config->dpll_hw_state.cfgcr2);
11966 } else if (HAS_DDI(dev)) {
11967 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11968 pipe_config->ddi_pll_sel,
11969 pipe_config->dpll_hw_state.wrpll);
11971 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11972 "fp0: 0x%x, fp1: 0x%x\n",
11973 pipe_config->dpll_hw_state.dpll,
11974 pipe_config->dpll_hw_state.dpll_md,
11975 pipe_config->dpll_hw_state.fp0,
11976 pipe_config->dpll_hw_state.fp1);
11979 DRM_DEBUG_KMS("planes on this crtc\n");
11980 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11981 intel_plane = to_intel_plane(plane);
11982 if (intel_plane->pipe != crtc->pipe)
11985 state = to_intel_plane_state(plane->state);
11986 fb = state->base.fb;
11988 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11989 "disabled, scaler_id = %d\n",
11990 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11991 plane->base.id, intel_plane->pipe,
11992 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11993 drm_plane_index(plane), state->scaler_id);
11997 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11998 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11999 plane->base.id, intel_plane->pipe,
12000 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12001 drm_plane_index(plane));
12002 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12003 fb->base.id, fb->width, fb->height, fb->pixel_format);
12004 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12006 state->src.x1 >> 16, state->src.y1 >> 16,
12007 drm_rect_width(&state->src) >> 16,
12008 drm_rect_height(&state->src) >> 16,
12009 state->dst.x1, state->dst.y1,
12010 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12014 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12016 struct drm_device *dev = state->dev;
12017 struct intel_encoder *encoder;
12018 struct drm_connector *connector;
12019 struct drm_connector_state *connector_state;
12020 unsigned int used_ports = 0;
12024 * Walk the connector list instead of the encoder
12025 * list to detect the problem on ddi platforms
12026 * where there's just one encoder per digital port.
12028 for_each_connector_in_state(state, connector, connector_state, i) {
12029 if (!connector_state->best_encoder)
12032 encoder = to_intel_encoder(connector_state->best_encoder);
12034 WARN_ON(!connector_state->crtc);
12036 switch (encoder->type) {
12037 unsigned int port_mask;
12038 case INTEL_OUTPUT_UNKNOWN:
12039 if (WARN_ON(!HAS_DDI(dev)))
12041 case INTEL_OUTPUT_DISPLAYPORT:
12042 case INTEL_OUTPUT_HDMI:
12043 case INTEL_OUTPUT_EDP:
12044 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12046 /* the same port mustn't appear more than once */
12047 if (used_ports & port_mask)
12050 used_ports |= port_mask;
12060 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12062 struct drm_crtc_state tmp_state;
12063 struct intel_crtc_scaler_state scaler_state;
12064 struct intel_dpll_hw_state dpll_hw_state;
12065 enum intel_dpll_id shared_dpll;
12066 uint32_t ddi_pll_sel;
12069 /* FIXME: before the switch to atomic started, a new pipe_config was
12070 * kzalloc'd. Code that depends on any field being zero should be
12071 * fixed, so that the crtc_state can be safely duplicated. For now,
12072 * only fields that are know to not cause problems are preserved. */
12074 tmp_state = crtc_state->base;
12075 scaler_state = crtc_state->scaler_state;
12076 shared_dpll = crtc_state->shared_dpll;
12077 dpll_hw_state = crtc_state->dpll_hw_state;
12078 ddi_pll_sel = crtc_state->ddi_pll_sel;
12079 force_thru = crtc_state->pch_pfit.force_thru;
12081 memset(crtc_state, 0, sizeof *crtc_state);
12083 crtc_state->base = tmp_state;
12084 crtc_state->scaler_state = scaler_state;
12085 crtc_state->shared_dpll = shared_dpll;
12086 crtc_state->dpll_hw_state = dpll_hw_state;
12087 crtc_state->ddi_pll_sel = ddi_pll_sel;
12088 crtc_state->pch_pfit.force_thru = force_thru;
12092 intel_modeset_pipe_config(struct drm_crtc *crtc,
12093 struct intel_crtc_state *pipe_config)
12095 struct drm_atomic_state *state = pipe_config->base.state;
12096 struct intel_encoder *encoder;
12097 struct drm_connector *connector;
12098 struct drm_connector_state *connector_state;
12099 int base_bpp, ret = -EINVAL;
12103 clear_intel_crtc_state(pipe_config);
12105 pipe_config->cpu_transcoder =
12106 (enum transcoder) to_intel_crtc(crtc)->pipe;
12109 * Sanitize sync polarity flags based on requested ones. If neither
12110 * positive or negative polarity is requested, treat this as meaning
12111 * negative polarity.
12113 if (!(pipe_config->base.adjusted_mode.flags &
12114 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12115 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12117 if (!(pipe_config->base.adjusted_mode.flags &
12118 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12119 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12121 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12122 * plane pixel format and any sink constraints into account. Returns the
12123 * source plane bpp so that dithering can be selected on mismatches
12124 * after encoders and crtc also have had their say. */
12125 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12131 * Determine the real pipe dimensions. Note that stereo modes can
12132 * increase the actual pipe size due to the frame doubling and
12133 * insertion of additional space for blanks between the frame. This
12134 * is stored in the crtc timings. We use the requested mode to do this
12135 * computation to clearly distinguish it from the adjusted mode, which
12136 * can be changed by the connectors in the below retry loop.
12138 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12139 &pipe_config->pipe_src_w,
12140 &pipe_config->pipe_src_h);
12143 /* Ensure the port clock defaults are reset when retrying. */
12144 pipe_config->port_clock = 0;
12145 pipe_config->pixel_multiplier = 1;
12147 /* Fill in default crtc timings, allow encoders to overwrite them. */
12148 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12149 CRTC_STEREO_DOUBLE);
12151 /* Pass our mode to the connectors and the CRTC to give them a chance to
12152 * adjust it according to limitations or connector properties, and also
12153 * a chance to reject the mode entirely.
12155 for_each_connector_in_state(state, connector, connector_state, i) {
12156 if (connector_state->crtc != crtc)
12159 encoder = to_intel_encoder(connector_state->best_encoder);
12161 if (!(encoder->compute_config(encoder, pipe_config))) {
12162 DRM_DEBUG_KMS("Encoder config failure\n");
12167 /* Set default port clock if not overwritten by the encoder. Needs to be
12168 * done afterwards in case the encoder adjusts the mode. */
12169 if (!pipe_config->port_clock)
12170 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12171 * pipe_config->pixel_multiplier;
12173 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12175 DRM_DEBUG_KMS("CRTC fixup failed\n");
12179 if (ret == RETRY) {
12180 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12185 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12187 goto encoder_retry;
12190 /* Dithering seems to not pass-through bits correctly when it should, so
12191 * only enable it on 6bpc panels. */
12192 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12193 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12194 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12201 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12203 struct drm_crtc *crtc;
12204 struct drm_crtc_state *crtc_state;
12207 /* Double check state. */
12208 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12209 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12211 /* Update hwmode for vblank functions */
12212 if (crtc->state->active)
12213 crtc->hwmode = crtc->state->adjusted_mode;
12215 crtc->hwmode.crtc_clock = 0;
12219 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12223 if (clock1 == clock2)
12226 if (!clock1 || !clock2)
12229 diff = abs(clock1 - clock2);
12231 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12237 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12238 list_for_each_entry((intel_crtc), \
12239 &(dev)->mode_config.crtc_list, \
12241 if (mask & (1 <<(intel_crtc)->pipe))
12245 intel_compare_m_n(unsigned int m, unsigned int n,
12246 unsigned int m2, unsigned int n2,
12249 if (m == m2 && n == n2)
12252 if (exact || !m || !n || !m2 || !n2)
12255 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12262 } else if (m < m2) {
12269 return m == m2 && n == n2;
12273 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12274 struct intel_link_m_n *m2_n2,
12277 if (m_n->tu == m2_n2->tu &&
12278 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12279 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12280 intel_compare_m_n(m_n->link_m, m_n->link_n,
12281 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12292 intel_pipe_config_compare(struct drm_device *dev,
12293 struct intel_crtc_state *current_config,
12294 struct intel_crtc_state *pipe_config,
12299 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12302 DRM_ERROR(fmt, ##__VA_ARGS__); \
12304 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12307 #define PIPE_CONF_CHECK_X(name) \
12308 if (current_config->name != pipe_config->name) { \
12309 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12310 "(expected 0x%08x, found 0x%08x)\n", \
12311 current_config->name, \
12312 pipe_config->name); \
12316 #define PIPE_CONF_CHECK_I(name) \
12317 if (current_config->name != pipe_config->name) { \
12318 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12319 "(expected %i, found %i)\n", \
12320 current_config->name, \
12321 pipe_config->name); \
12325 #define PIPE_CONF_CHECK_M_N(name) \
12326 if (!intel_compare_link_m_n(¤t_config->name, \
12327 &pipe_config->name,\
12329 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12330 "(expected tu %i gmch %i/%i link %i/%i, " \
12331 "found tu %i, gmch %i/%i link %i/%i)\n", \
12332 current_config->name.tu, \
12333 current_config->name.gmch_m, \
12334 current_config->name.gmch_n, \
12335 current_config->name.link_m, \
12336 current_config->name.link_n, \
12337 pipe_config->name.tu, \
12338 pipe_config->name.gmch_m, \
12339 pipe_config->name.gmch_n, \
12340 pipe_config->name.link_m, \
12341 pipe_config->name.link_n); \
12345 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12346 if (!intel_compare_link_m_n(¤t_config->name, \
12347 &pipe_config->name, adjust) && \
12348 !intel_compare_link_m_n(¤t_config->alt_name, \
12349 &pipe_config->name, adjust)) { \
12350 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12351 "(expected tu %i gmch %i/%i link %i/%i, " \
12352 "or tu %i gmch %i/%i link %i/%i, " \
12353 "found tu %i, gmch %i/%i link %i/%i)\n", \
12354 current_config->name.tu, \
12355 current_config->name.gmch_m, \
12356 current_config->name.gmch_n, \
12357 current_config->name.link_m, \
12358 current_config->name.link_n, \
12359 current_config->alt_name.tu, \
12360 current_config->alt_name.gmch_m, \
12361 current_config->alt_name.gmch_n, \
12362 current_config->alt_name.link_m, \
12363 current_config->alt_name.link_n, \
12364 pipe_config->name.tu, \
12365 pipe_config->name.gmch_m, \
12366 pipe_config->name.gmch_n, \
12367 pipe_config->name.link_m, \
12368 pipe_config->name.link_n); \
12372 /* This is required for BDW+ where there is only one set of registers for
12373 * switching between high and low RR.
12374 * This macro can be used whenever a comparison has to be made between one
12375 * hw state and multiple sw state variables.
12377 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12378 if ((current_config->name != pipe_config->name) && \
12379 (current_config->alt_name != pipe_config->name)) { \
12380 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12381 "(expected %i or %i, found %i)\n", \
12382 current_config->name, \
12383 current_config->alt_name, \
12384 pipe_config->name); \
12388 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12389 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12390 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12391 "(expected %i, found %i)\n", \
12392 current_config->name & (mask), \
12393 pipe_config->name & (mask)); \
12397 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12398 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12399 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12400 "(expected %i, found %i)\n", \
12401 current_config->name, \
12402 pipe_config->name); \
12406 #define PIPE_CONF_QUIRK(quirk) \
12407 ((current_config->quirks | pipe_config->quirks) & (quirk))
12409 PIPE_CONF_CHECK_I(cpu_transcoder);
12411 PIPE_CONF_CHECK_I(has_pch_encoder);
12412 PIPE_CONF_CHECK_I(fdi_lanes);
12413 PIPE_CONF_CHECK_M_N(fdi_m_n);
12415 PIPE_CONF_CHECK_I(has_dp_encoder);
12417 if (INTEL_INFO(dev)->gen < 8) {
12418 PIPE_CONF_CHECK_M_N(dp_m_n);
12420 PIPE_CONF_CHECK_I(has_drrs);
12421 if (current_config->has_drrs)
12422 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12424 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12426 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12427 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12428 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12429 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12433 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12434 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12435 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12436 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12437 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12438 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12440 PIPE_CONF_CHECK_I(pixel_multiplier);
12441 PIPE_CONF_CHECK_I(has_hdmi_sink);
12442 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12443 IS_VALLEYVIEW(dev))
12444 PIPE_CONF_CHECK_I(limited_color_range);
12445 PIPE_CONF_CHECK_I(has_infoframe);
12447 PIPE_CONF_CHECK_I(has_audio);
12449 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12450 DRM_MODE_FLAG_INTERLACE);
12452 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12453 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12454 DRM_MODE_FLAG_PHSYNC);
12455 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12456 DRM_MODE_FLAG_NHSYNC);
12457 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12458 DRM_MODE_FLAG_PVSYNC);
12459 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12460 DRM_MODE_FLAG_NVSYNC);
12463 PIPE_CONF_CHECK_I(pipe_src_w);
12464 PIPE_CONF_CHECK_I(pipe_src_h);
12466 PIPE_CONF_CHECK_I(gmch_pfit.control);
12467 /* pfit ratios are autocomputed by the hw on gen4+ */
12468 if (INTEL_INFO(dev)->gen < 4)
12469 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12470 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12472 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12473 if (current_config->pch_pfit.enabled) {
12474 PIPE_CONF_CHECK_I(pch_pfit.pos);
12475 PIPE_CONF_CHECK_I(pch_pfit.size);
12478 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12480 /* BDW+ don't expose a synchronous way to read the state */
12481 if (IS_HASWELL(dev))
12482 PIPE_CONF_CHECK_I(ips_enabled);
12484 PIPE_CONF_CHECK_I(double_wide);
12486 PIPE_CONF_CHECK_X(ddi_pll_sel);
12488 PIPE_CONF_CHECK_I(shared_dpll);
12489 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12490 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12491 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12492 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12493 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12494 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12495 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12496 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12498 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12499 PIPE_CONF_CHECK_I(pipe_bpp);
12501 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12502 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12504 #undef PIPE_CONF_CHECK_X
12505 #undef PIPE_CONF_CHECK_I
12506 #undef PIPE_CONF_CHECK_I_ALT
12507 #undef PIPE_CONF_CHECK_FLAGS
12508 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12509 #undef PIPE_CONF_QUIRK
12510 #undef INTEL_ERR_OR_DBG_KMS
12515 static void check_wm_state(struct drm_device *dev)
12517 struct drm_i915_private *dev_priv = dev->dev_private;
12518 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12519 struct intel_crtc *intel_crtc;
12522 if (INTEL_INFO(dev)->gen < 9)
12525 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12526 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12528 for_each_intel_crtc(dev, intel_crtc) {
12529 struct skl_ddb_entry *hw_entry, *sw_entry;
12530 const enum pipe pipe = intel_crtc->pipe;
12532 if (!intel_crtc->active)
12536 for_each_plane(dev_priv, pipe, plane) {
12537 hw_entry = &hw_ddb.plane[pipe][plane];
12538 sw_entry = &sw_ddb->plane[pipe][plane];
12540 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12543 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12544 "(expected (%u,%u), found (%u,%u))\n",
12545 pipe_name(pipe), plane + 1,
12546 sw_entry->start, sw_entry->end,
12547 hw_entry->start, hw_entry->end);
12551 hw_entry = &hw_ddb.cursor[pipe];
12552 sw_entry = &sw_ddb->cursor[pipe];
12554 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12557 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12558 "(expected (%u,%u), found (%u,%u))\n",
12560 sw_entry->start, sw_entry->end,
12561 hw_entry->start, hw_entry->end);
12566 check_connector_state(struct drm_device *dev,
12567 struct drm_atomic_state *old_state)
12569 struct drm_connector_state *old_conn_state;
12570 struct drm_connector *connector;
12573 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12574 struct drm_encoder *encoder = connector->encoder;
12575 struct drm_connector_state *state = connector->state;
12577 /* This also checks the encoder/connector hw state with the
12578 * ->get_hw_state callbacks. */
12579 intel_connector_check_state(to_intel_connector(connector));
12581 I915_STATE_WARN(state->best_encoder != encoder,
12582 "connector's atomic encoder doesn't match legacy encoder\n");
12587 check_encoder_state(struct drm_device *dev)
12589 struct intel_encoder *encoder;
12590 struct intel_connector *connector;
12592 for_each_intel_encoder(dev, encoder) {
12593 bool enabled = false;
12596 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12597 encoder->base.base.id,
12598 encoder->base.name);
12600 for_each_intel_connector(dev, connector) {
12601 if (connector->base.state->best_encoder != &encoder->base)
12605 I915_STATE_WARN(connector->base.state->crtc !=
12606 encoder->base.crtc,
12607 "connector's crtc doesn't match encoder crtc\n");
12610 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12611 "encoder's enabled state mismatch "
12612 "(expected %i, found %i)\n",
12613 !!encoder->base.crtc, enabled);
12615 if (!encoder->base.crtc) {
12618 active = encoder->get_hw_state(encoder, &pipe);
12619 I915_STATE_WARN(active,
12620 "encoder detached but still enabled on pipe %c.\n",
12627 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12629 struct drm_i915_private *dev_priv = dev->dev_private;
12630 struct intel_encoder *encoder;
12631 struct drm_crtc_state *old_crtc_state;
12632 struct drm_crtc *crtc;
12635 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12637 struct intel_crtc_state *pipe_config, *sw_config;
12640 if (!needs_modeset(crtc->state))
12643 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12644 pipe_config = to_intel_crtc_state(old_crtc_state);
12645 memset(pipe_config, 0, sizeof(*pipe_config));
12646 pipe_config->base.crtc = crtc;
12647 pipe_config->base.state = old_state;
12649 DRM_DEBUG_KMS("[CRTC:%d]\n",
12652 active = dev_priv->display.get_pipe_config(intel_crtc,
12655 /* hw state is inconsistent with the pipe quirk */
12656 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12657 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12658 active = crtc->state->active;
12660 I915_STATE_WARN(crtc->state->active != active,
12661 "crtc active state doesn't match with hw state "
12662 "(expected %i, found %i)\n", crtc->state->active, active);
12664 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12665 "transitional active state does not match atomic hw state "
12666 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12668 for_each_encoder_on_crtc(dev, crtc, encoder) {
12671 active = encoder->get_hw_state(encoder, &pipe);
12672 I915_STATE_WARN(active != crtc->state->active,
12673 "[ENCODER:%i] active %i with crtc active %i\n",
12674 encoder->base.base.id, active, crtc->state->active);
12676 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12677 "Encoder connected to wrong pipe %c\n",
12681 encoder->get_config(encoder, pipe_config);
12684 if (!crtc->state->active)
12687 sw_config = to_intel_crtc_state(crtc->state);
12688 if (!intel_pipe_config_compare(dev, sw_config,
12689 pipe_config, false)) {
12690 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12691 intel_dump_pipe_config(intel_crtc, pipe_config,
12693 intel_dump_pipe_config(intel_crtc, sw_config,
12700 check_shared_dpll_state(struct drm_device *dev)
12702 struct drm_i915_private *dev_priv = dev->dev_private;
12703 struct intel_crtc *crtc;
12704 struct intel_dpll_hw_state dpll_hw_state;
12707 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12708 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12709 int enabled_crtcs = 0, active_crtcs = 0;
12712 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12714 DRM_DEBUG_KMS("%s\n", pll->name);
12716 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12718 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12719 "more active pll users than references: %i vs %i\n",
12720 pll->active, hweight32(pll->config.crtc_mask));
12721 I915_STATE_WARN(pll->active && !pll->on,
12722 "pll in active use but not on in sw tracking\n");
12723 I915_STATE_WARN(pll->on && !pll->active,
12724 "pll in on but not on in use in sw tracking\n");
12725 I915_STATE_WARN(pll->on != active,
12726 "pll on state mismatch (expected %i, found %i)\n",
12729 for_each_intel_crtc(dev, crtc) {
12730 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12732 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12735 I915_STATE_WARN(pll->active != active_crtcs,
12736 "pll active crtcs mismatch (expected %i, found %i)\n",
12737 pll->active, active_crtcs);
12738 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12739 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12740 hweight32(pll->config.crtc_mask), enabled_crtcs);
12742 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12743 sizeof(dpll_hw_state)),
12744 "pll hw state mismatch\n");
12749 intel_modeset_check_state(struct drm_device *dev,
12750 struct drm_atomic_state *old_state)
12752 check_wm_state(dev);
12753 check_connector_state(dev, old_state);
12754 check_encoder_state(dev);
12755 check_crtc_state(dev, old_state);
12756 check_shared_dpll_state(dev);
12759 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12763 * FDI already provided one idea for the dotclock.
12764 * Yell if the encoder disagrees.
12766 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12767 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12768 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12771 static void update_scanline_offset(struct intel_crtc *crtc)
12773 struct drm_device *dev = crtc->base.dev;
12776 * The scanline counter increments at the leading edge of hsync.
12778 * On most platforms it starts counting from vtotal-1 on the
12779 * first active line. That means the scanline counter value is
12780 * always one less than what we would expect. Ie. just after
12781 * start of vblank, which also occurs at start of hsync (on the
12782 * last active line), the scanline counter will read vblank_start-1.
12784 * On gen2 the scanline counter starts counting from 1 instead
12785 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12786 * to keep the value positive), instead of adding one.
12788 * On HSW+ the behaviour of the scanline counter depends on the output
12789 * type. For DP ports it behaves like most other platforms, but on HDMI
12790 * there's an extra 1 line difference. So we need to add two instead of
12791 * one to the value.
12793 if (IS_GEN2(dev)) {
12794 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12797 vtotal = mode->crtc_vtotal;
12798 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12801 crtc->scanline_offset = vtotal - 1;
12802 } else if (HAS_DDI(dev) &&
12803 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12804 crtc->scanline_offset = 2;
12806 crtc->scanline_offset = 1;
12809 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12811 struct drm_device *dev = state->dev;
12812 struct drm_i915_private *dev_priv = to_i915(dev);
12813 struct intel_shared_dpll_config *shared_dpll = NULL;
12814 struct intel_crtc *intel_crtc;
12815 struct intel_crtc_state *intel_crtc_state;
12816 struct drm_crtc *crtc;
12817 struct drm_crtc_state *crtc_state;
12820 if (!dev_priv->display.crtc_compute_clock)
12823 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12826 intel_crtc = to_intel_crtc(crtc);
12827 intel_crtc_state = to_intel_crtc_state(crtc_state);
12828 dpll = intel_crtc_state->shared_dpll;
12830 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12833 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12836 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12838 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12843 * This implements the workaround described in the "notes" section of the mode
12844 * set sequence documentation. When going from no pipes or single pipe to
12845 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12846 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12848 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12850 struct drm_crtc_state *crtc_state;
12851 struct intel_crtc *intel_crtc;
12852 struct drm_crtc *crtc;
12853 struct intel_crtc_state *first_crtc_state = NULL;
12854 struct intel_crtc_state *other_crtc_state = NULL;
12855 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12858 /* look at all crtc's that are going to be enabled in during modeset */
12859 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12860 intel_crtc = to_intel_crtc(crtc);
12862 if (!crtc_state->active || !needs_modeset(crtc_state))
12865 if (first_crtc_state) {
12866 other_crtc_state = to_intel_crtc_state(crtc_state);
12869 first_crtc_state = to_intel_crtc_state(crtc_state);
12870 first_pipe = intel_crtc->pipe;
12874 /* No workaround needed? */
12875 if (!first_crtc_state)
12878 /* w/a possibly needed, check how many crtc's are already enabled. */
12879 for_each_intel_crtc(state->dev, intel_crtc) {
12880 struct intel_crtc_state *pipe_config;
12882 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12883 if (IS_ERR(pipe_config))
12884 return PTR_ERR(pipe_config);
12886 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12888 if (!pipe_config->base.active ||
12889 needs_modeset(&pipe_config->base))
12892 /* 2 or more enabled crtcs means no need for w/a */
12893 if (enabled_pipe != INVALID_PIPE)
12896 enabled_pipe = intel_crtc->pipe;
12899 if (enabled_pipe != INVALID_PIPE)
12900 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12901 else if (other_crtc_state)
12902 other_crtc_state->hsw_workaround_pipe = first_pipe;
12907 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12909 struct drm_crtc *crtc;
12910 struct drm_crtc_state *crtc_state;
12913 /* add all active pipes to the state */
12914 for_each_crtc(state->dev, crtc) {
12915 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12916 if (IS_ERR(crtc_state))
12917 return PTR_ERR(crtc_state);
12919 if (!crtc_state->active || needs_modeset(crtc_state))
12922 crtc_state->mode_changed = true;
12924 ret = drm_atomic_add_affected_connectors(state, crtc);
12928 ret = drm_atomic_add_affected_planes(state, crtc);
12937 static int intel_modeset_checks(struct drm_atomic_state *state)
12939 struct drm_device *dev = state->dev;
12940 struct drm_i915_private *dev_priv = dev->dev_private;
12943 if (!check_digital_port_conflicts(state)) {
12944 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12949 * See if the config requires any additional preparation, e.g.
12950 * to adjust global state with pipes off. We need to do this
12951 * here so we can get the modeset_pipe updated config for the new
12952 * mode set on this crtc. For other crtcs we need to use the
12953 * adjusted_mode bits in the crtc directly.
12955 if (dev_priv->display.modeset_calc_cdclk) {
12956 unsigned int cdclk;
12958 ret = dev_priv->display.modeset_calc_cdclk(state);
12960 cdclk = to_intel_atomic_state(state)->cdclk;
12961 if (!ret && cdclk != dev_priv->cdclk_freq)
12962 ret = intel_modeset_all_pipes(state);
12967 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12969 intel_modeset_clear_plls(state);
12971 if (IS_HASWELL(dev))
12972 return haswell_mode_set_planes_workaround(state);
12978 * intel_atomic_check - validate state object
12980 * @state: state to validate
12982 static int intel_atomic_check(struct drm_device *dev,
12983 struct drm_atomic_state *state)
12985 struct drm_crtc *crtc;
12986 struct drm_crtc_state *crtc_state;
12988 bool any_ms = false;
12990 ret = drm_atomic_helper_check_modeset(dev, state);
12994 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12995 struct intel_crtc_state *pipe_config =
12996 to_intel_crtc_state(crtc_state);
12998 /* Catch I915_MODE_FLAG_INHERITED */
12999 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13000 crtc_state->mode_changed = true;
13002 if (!crtc_state->enable) {
13003 if (needs_modeset(crtc_state))
13008 if (!needs_modeset(crtc_state))
13011 /* FIXME: For only active_changed we shouldn't need to do any
13012 * state recomputation at all. */
13014 ret = drm_atomic_add_affected_connectors(state, crtc);
13018 ret = intel_modeset_pipe_config(crtc, pipe_config);
13022 if (i915.fastboot &&
13023 intel_pipe_config_compare(state->dev,
13024 to_intel_crtc_state(crtc->state),
13025 pipe_config, true)) {
13026 crtc_state->mode_changed = false;
13029 if (needs_modeset(crtc_state)) {
13032 ret = drm_atomic_add_affected_planes(state, crtc);
13037 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13038 needs_modeset(crtc_state) ?
13039 "[modeset]" : "[fastset]");
13043 ret = intel_modeset_checks(state);
13048 to_intel_atomic_state(state)->cdclk =
13049 to_i915(state->dev)->cdclk_freq;
13051 return drm_atomic_helper_check_planes(state->dev, state);
13055 * intel_atomic_commit - commit validated state object
13057 * @state: the top-level driver state object
13058 * @async: asynchronous commit
13060 * This function commits a top-level state object that has been validated
13061 * with drm_atomic_helper_check().
13063 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13064 * we can only handle plane-related operations and do not yet support
13065 * asynchronous commit.
13068 * Zero for success or -errno.
13070 static int intel_atomic_commit(struct drm_device *dev,
13071 struct drm_atomic_state *state,
13074 struct drm_i915_private *dev_priv = dev->dev_private;
13075 struct drm_crtc *crtc;
13076 struct drm_crtc_state *crtc_state;
13079 bool any_ms = false;
13082 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13086 ret = drm_atomic_helper_prepare_planes(dev, state);
13090 drm_atomic_helper_swap_state(dev, state);
13092 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13095 if (!needs_modeset(crtc->state))
13099 intel_pre_plane_update(intel_crtc);
13101 if (crtc_state->active) {
13102 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13103 dev_priv->display.crtc_disable(crtc);
13104 intel_crtc->active = false;
13105 intel_disable_shared_dpll(intel_crtc);
13109 /* Only after disabling all output pipelines that will be changed can we
13110 * update the the output configuration. */
13111 intel_modeset_update_crtc_state(state);
13114 intel_shared_dpll_commit(state);
13116 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13117 modeset_update_crtc_power_domains(state);
13120 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13121 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13123 bool modeset = needs_modeset(crtc->state);
13125 if (modeset && crtc->state->active) {
13126 update_scanline_offset(to_intel_crtc(crtc));
13127 dev_priv->display.crtc_enable(crtc);
13131 intel_pre_plane_update(intel_crtc);
13133 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13134 intel_post_plane_update(intel_crtc);
13137 /* FIXME: add subpixel order */
13139 drm_atomic_helper_wait_for_vblanks(dev, state);
13140 drm_atomic_helper_cleanup_planes(dev, state);
13143 intel_modeset_check_state(dev, state);
13145 drm_atomic_state_free(state);
13150 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13152 struct drm_device *dev = crtc->dev;
13153 struct drm_atomic_state *state;
13154 struct drm_crtc_state *crtc_state;
13157 state = drm_atomic_state_alloc(dev);
13159 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13164 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13167 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13168 ret = PTR_ERR_OR_ZERO(crtc_state);
13170 if (!crtc_state->active)
13173 crtc_state->mode_changed = true;
13174 ret = drm_atomic_commit(state);
13177 if (ret == -EDEADLK) {
13178 drm_atomic_state_clear(state);
13179 drm_modeset_backoff(state->acquire_ctx);
13185 drm_atomic_state_free(state);
13188 #undef for_each_intel_crtc_masked
13190 static const struct drm_crtc_funcs intel_crtc_funcs = {
13191 .gamma_set = intel_crtc_gamma_set,
13192 .set_config = drm_atomic_helper_set_config,
13193 .destroy = intel_crtc_destroy,
13194 .page_flip = intel_crtc_page_flip,
13195 .atomic_duplicate_state = intel_crtc_duplicate_state,
13196 .atomic_destroy_state = intel_crtc_destroy_state,
13199 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13200 struct intel_shared_dpll *pll,
13201 struct intel_dpll_hw_state *hw_state)
13205 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13208 val = I915_READ(PCH_DPLL(pll->id));
13209 hw_state->dpll = val;
13210 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13211 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13213 return val & DPLL_VCO_ENABLE;
13216 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13217 struct intel_shared_dpll *pll)
13219 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13220 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13223 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13224 struct intel_shared_dpll *pll)
13226 /* PCH refclock must be enabled first */
13227 ibx_assert_pch_refclk_enabled(dev_priv);
13229 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13231 /* Wait for the clocks to stabilize. */
13232 POSTING_READ(PCH_DPLL(pll->id));
13235 /* The pixel multiplier can only be updated once the
13236 * DPLL is enabled and the clocks are stable.
13238 * So write it again.
13240 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13241 POSTING_READ(PCH_DPLL(pll->id));
13245 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13246 struct intel_shared_dpll *pll)
13248 struct drm_device *dev = dev_priv->dev;
13249 struct intel_crtc *crtc;
13251 /* Make sure no transcoder isn't still depending on us. */
13252 for_each_intel_crtc(dev, crtc) {
13253 if (intel_crtc_to_shared_dpll(crtc) == pll)
13254 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13257 I915_WRITE(PCH_DPLL(pll->id), 0);
13258 POSTING_READ(PCH_DPLL(pll->id));
13262 static char *ibx_pch_dpll_names[] = {
13267 static void ibx_pch_dpll_init(struct drm_device *dev)
13269 struct drm_i915_private *dev_priv = dev->dev_private;
13272 dev_priv->num_shared_dpll = 2;
13274 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13275 dev_priv->shared_dplls[i].id = i;
13276 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13277 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13278 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13279 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13280 dev_priv->shared_dplls[i].get_hw_state =
13281 ibx_pch_dpll_get_hw_state;
13285 static void intel_shared_dpll_init(struct drm_device *dev)
13287 struct drm_i915_private *dev_priv = dev->dev_private;
13289 intel_update_cdclk(dev);
13292 intel_ddi_pll_init(dev);
13293 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13294 ibx_pch_dpll_init(dev);
13296 dev_priv->num_shared_dpll = 0;
13298 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13302 * intel_prepare_plane_fb - Prepare fb for usage on plane
13303 * @plane: drm plane to prepare for
13304 * @fb: framebuffer to prepare for presentation
13306 * Prepares a framebuffer for usage on a display plane. Generally this
13307 * involves pinning the underlying object and updating the frontbuffer tracking
13308 * bits. Some older platforms need special physical address handling for
13311 * Returns 0 on success, negative error code on failure.
13314 intel_prepare_plane_fb(struct drm_plane *plane,
13315 struct drm_framebuffer *fb,
13316 const struct drm_plane_state *new_state)
13318 struct drm_device *dev = plane->dev;
13319 struct intel_plane *intel_plane = to_intel_plane(plane);
13320 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13321 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13327 mutex_lock(&dev->struct_mutex);
13329 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13330 INTEL_INFO(dev)->cursor_needs_physical) {
13331 int align = IS_I830(dev) ? 16 * 1024 : 256;
13332 ret = i915_gem_object_attach_phys(obj, align);
13334 DRM_DEBUG_KMS("failed to attach phys object\n");
13336 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13340 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13342 mutex_unlock(&dev->struct_mutex);
13348 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13349 * @plane: drm plane to clean up for
13350 * @fb: old framebuffer that was on plane
13352 * Cleans up a framebuffer that has just been removed from a plane.
13355 intel_cleanup_plane_fb(struct drm_plane *plane,
13356 struct drm_framebuffer *fb,
13357 const struct drm_plane_state *old_state)
13359 struct drm_device *dev = plane->dev;
13360 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13365 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13366 !INTEL_INFO(dev)->cursor_needs_physical) {
13367 mutex_lock(&dev->struct_mutex);
13368 intel_unpin_fb_obj(fb, old_state);
13369 mutex_unlock(&dev->struct_mutex);
13374 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13377 struct drm_device *dev;
13378 struct drm_i915_private *dev_priv;
13379 int crtc_clock, cdclk;
13381 if (!intel_crtc || !crtc_state)
13382 return DRM_PLANE_HELPER_NO_SCALING;
13384 dev = intel_crtc->base.dev;
13385 dev_priv = dev->dev_private;
13386 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13387 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13389 if (!crtc_clock || !cdclk)
13390 return DRM_PLANE_HELPER_NO_SCALING;
13393 * skl max scale is lower of:
13394 * close to 3 but not 3, -1 is for that purpose
13398 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13404 intel_check_primary_plane(struct drm_plane *plane,
13405 struct intel_crtc_state *crtc_state,
13406 struct intel_plane_state *state)
13408 struct drm_crtc *crtc = state->base.crtc;
13409 struct drm_framebuffer *fb = state->base.fb;
13410 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13411 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13412 bool can_position = false;
13414 /* use scaler when colorkey is not required */
13415 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13416 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13418 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13419 can_position = true;
13422 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13423 &state->dst, &state->clip,
13424 min_scale, max_scale,
13425 can_position, true,
13430 intel_commit_primary_plane(struct drm_plane *plane,
13431 struct intel_plane_state *state)
13433 struct drm_crtc *crtc = state->base.crtc;
13434 struct drm_framebuffer *fb = state->base.fb;
13435 struct drm_device *dev = plane->dev;
13436 struct drm_i915_private *dev_priv = dev->dev_private;
13437 struct intel_crtc *intel_crtc;
13438 struct drm_rect *src = &state->src;
13440 crtc = crtc ? crtc : plane->crtc;
13441 intel_crtc = to_intel_crtc(crtc);
13444 crtc->x = src->x1 >> 16;
13445 crtc->y = src->y1 >> 16;
13447 if (!crtc->state->active)
13450 if (state->visible)
13451 /* FIXME: kill this fastboot hack */
13452 intel_update_pipe_size(intel_crtc);
13454 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13458 intel_disable_primary_plane(struct drm_plane *plane,
13459 struct drm_crtc *crtc)
13461 struct drm_device *dev = plane->dev;
13462 struct drm_i915_private *dev_priv = dev->dev_private;
13464 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13467 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13468 struct drm_crtc_state *old_crtc_state)
13470 struct drm_device *dev = crtc->dev;
13471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13473 if (intel_crtc->atomic.update_wm_pre)
13474 intel_update_watermarks(crtc);
13476 /* Perform vblank evasion around commit operation */
13477 if (crtc->state->active)
13478 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13480 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13481 skl_detach_scalers(intel_crtc);
13484 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13485 struct drm_crtc_state *old_crtc_state)
13487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13489 if (crtc->state->active)
13490 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13494 * intel_plane_destroy - destroy a plane
13495 * @plane: plane to destroy
13497 * Common destruction function for all types of planes (primary, cursor,
13500 void intel_plane_destroy(struct drm_plane *plane)
13502 struct intel_plane *intel_plane = to_intel_plane(plane);
13503 drm_plane_cleanup(plane);
13504 kfree(intel_plane);
13507 const struct drm_plane_funcs intel_plane_funcs = {
13508 .update_plane = drm_atomic_helper_update_plane,
13509 .disable_plane = drm_atomic_helper_disable_plane,
13510 .destroy = intel_plane_destroy,
13511 .set_property = drm_atomic_helper_plane_set_property,
13512 .atomic_get_property = intel_plane_atomic_get_property,
13513 .atomic_set_property = intel_plane_atomic_set_property,
13514 .atomic_duplicate_state = intel_plane_duplicate_state,
13515 .atomic_destroy_state = intel_plane_destroy_state,
13519 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13522 struct intel_plane *primary;
13523 struct intel_plane_state *state;
13524 const uint32_t *intel_primary_formats;
13525 unsigned int num_formats;
13527 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13528 if (primary == NULL)
13531 state = intel_create_plane_state(&primary->base);
13536 primary->base.state = &state->base;
13538 primary->can_scale = false;
13539 primary->max_downscale = 1;
13540 if (INTEL_INFO(dev)->gen >= 9) {
13541 primary->can_scale = true;
13542 state->scaler_id = -1;
13544 primary->pipe = pipe;
13545 primary->plane = pipe;
13546 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13547 primary->check_plane = intel_check_primary_plane;
13548 primary->commit_plane = intel_commit_primary_plane;
13549 primary->disable_plane = intel_disable_primary_plane;
13550 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13551 primary->plane = !pipe;
13553 if (INTEL_INFO(dev)->gen >= 9) {
13554 intel_primary_formats = skl_primary_formats;
13555 num_formats = ARRAY_SIZE(skl_primary_formats);
13556 } else if (INTEL_INFO(dev)->gen >= 4) {
13557 intel_primary_formats = i965_primary_formats;
13558 num_formats = ARRAY_SIZE(i965_primary_formats);
13560 intel_primary_formats = i8xx_primary_formats;
13561 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13564 drm_universal_plane_init(dev, &primary->base, 0,
13565 &intel_plane_funcs,
13566 intel_primary_formats, num_formats,
13567 DRM_PLANE_TYPE_PRIMARY);
13569 if (INTEL_INFO(dev)->gen >= 4)
13570 intel_create_rotation_property(dev, primary);
13572 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13574 return &primary->base;
13577 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13579 if (!dev->mode_config.rotation_property) {
13580 unsigned long flags = BIT(DRM_ROTATE_0) |
13581 BIT(DRM_ROTATE_180);
13583 if (INTEL_INFO(dev)->gen >= 9)
13584 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13586 dev->mode_config.rotation_property =
13587 drm_mode_create_rotation_property(dev, flags);
13589 if (dev->mode_config.rotation_property)
13590 drm_object_attach_property(&plane->base.base,
13591 dev->mode_config.rotation_property,
13592 plane->base.state->rotation);
13596 intel_check_cursor_plane(struct drm_plane *plane,
13597 struct intel_crtc_state *crtc_state,
13598 struct intel_plane_state *state)
13600 struct drm_crtc *crtc = crtc_state->base.crtc;
13601 struct drm_framebuffer *fb = state->base.fb;
13602 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13606 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13607 &state->dst, &state->clip,
13608 DRM_PLANE_HELPER_NO_SCALING,
13609 DRM_PLANE_HELPER_NO_SCALING,
13610 true, true, &state->visible);
13614 /* if we want to turn off the cursor ignore width and height */
13618 /* Check for which cursor types we support */
13619 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13620 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13621 state->base.crtc_w, state->base.crtc_h);
13625 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13626 if (obj->base.size < stride * state->base.crtc_h) {
13627 DRM_DEBUG_KMS("buffer is too small\n");
13631 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13632 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13640 intel_disable_cursor_plane(struct drm_plane *plane,
13641 struct drm_crtc *crtc)
13643 intel_crtc_update_cursor(crtc, false);
13647 intel_commit_cursor_plane(struct drm_plane *plane,
13648 struct intel_plane_state *state)
13650 struct drm_crtc *crtc = state->base.crtc;
13651 struct drm_device *dev = plane->dev;
13652 struct intel_crtc *intel_crtc;
13653 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13656 crtc = crtc ? crtc : plane->crtc;
13657 intel_crtc = to_intel_crtc(crtc);
13659 plane->fb = state->base.fb;
13660 crtc->cursor_x = state->base.crtc_x;
13661 crtc->cursor_y = state->base.crtc_y;
13663 if (intel_crtc->cursor_bo == obj)
13668 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13669 addr = i915_gem_obj_ggtt_offset(obj);
13671 addr = obj->phys_handle->busaddr;
13673 intel_crtc->cursor_addr = addr;
13674 intel_crtc->cursor_bo = obj;
13677 if (crtc->state->active)
13678 intel_crtc_update_cursor(crtc, state->visible);
13681 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13684 struct intel_plane *cursor;
13685 struct intel_plane_state *state;
13687 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13688 if (cursor == NULL)
13691 state = intel_create_plane_state(&cursor->base);
13696 cursor->base.state = &state->base;
13698 cursor->can_scale = false;
13699 cursor->max_downscale = 1;
13700 cursor->pipe = pipe;
13701 cursor->plane = pipe;
13702 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13703 cursor->check_plane = intel_check_cursor_plane;
13704 cursor->commit_plane = intel_commit_cursor_plane;
13705 cursor->disable_plane = intel_disable_cursor_plane;
13707 drm_universal_plane_init(dev, &cursor->base, 0,
13708 &intel_plane_funcs,
13709 intel_cursor_formats,
13710 ARRAY_SIZE(intel_cursor_formats),
13711 DRM_PLANE_TYPE_CURSOR);
13713 if (INTEL_INFO(dev)->gen >= 4) {
13714 if (!dev->mode_config.rotation_property)
13715 dev->mode_config.rotation_property =
13716 drm_mode_create_rotation_property(dev,
13717 BIT(DRM_ROTATE_0) |
13718 BIT(DRM_ROTATE_180));
13719 if (dev->mode_config.rotation_property)
13720 drm_object_attach_property(&cursor->base.base,
13721 dev->mode_config.rotation_property,
13722 state->base.rotation);
13725 if (INTEL_INFO(dev)->gen >=9)
13726 state->scaler_id = -1;
13728 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13730 return &cursor->base;
13733 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13734 struct intel_crtc_state *crtc_state)
13737 struct intel_scaler *intel_scaler;
13738 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13740 for (i = 0; i < intel_crtc->num_scalers; i++) {
13741 intel_scaler = &scaler_state->scalers[i];
13742 intel_scaler->in_use = 0;
13743 intel_scaler->mode = PS_SCALER_MODE_DYN;
13746 scaler_state->scaler_id = -1;
13749 static void intel_crtc_init(struct drm_device *dev, int pipe)
13751 struct drm_i915_private *dev_priv = dev->dev_private;
13752 struct intel_crtc *intel_crtc;
13753 struct intel_crtc_state *crtc_state = NULL;
13754 struct drm_plane *primary = NULL;
13755 struct drm_plane *cursor = NULL;
13758 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13759 if (intel_crtc == NULL)
13762 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13765 intel_crtc->config = crtc_state;
13766 intel_crtc->base.state = &crtc_state->base;
13767 crtc_state->base.crtc = &intel_crtc->base;
13769 /* initialize shared scalers */
13770 if (INTEL_INFO(dev)->gen >= 9) {
13771 if (pipe == PIPE_C)
13772 intel_crtc->num_scalers = 1;
13774 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13776 skl_init_scalers(dev, intel_crtc, crtc_state);
13779 primary = intel_primary_plane_create(dev, pipe);
13783 cursor = intel_cursor_plane_create(dev, pipe);
13787 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13788 cursor, &intel_crtc_funcs);
13792 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13793 for (i = 0; i < 256; i++) {
13794 intel_crtc->lut_r[i] = i;
13795 intel_crtc->lut_g[i] = i;
13796 intel_crtc->lut_b[i] = i;
13800 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13801 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13803 intel_crtc->pipe = pipe;
13804 intel_crtc->plane = pipe;
13805 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13806 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13807 intel_crtc->plane = !pipe;
13810 intel_crtc->cursor_base = ~0;
13811 intel_crtc->cursor_cntl = ~0;
13812 intel_crtc->cursor_size = ~0;
13814 intel_crtc->wm.cxsr_allowed = true;
13816 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13817 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13818 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13819 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13821 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13823 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13828 drm_plane_cleanup(primary);
13830 drm_plane_cleanup(cursor);
13835 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13837 struct drm_encoder *encoder = connector->base.encoder;
13838 struct drm_device *dev = connector->base.dev;
13840 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13842 if (!encoder || WARN_ON(!encoder->crtc))
13843 return INVALID_PIPE;
13845 return to_intel_crtc(encoder->crtc)->pipe;
13848 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13849 struct drm_file *file)
13851 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13852 struct drm_crtc *drmmode_crtc;
13853 struct intel_crtc *crtc;
13855 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13857 if (!drmmode_crtc) {
13858 DRM_ERROR("no such CRTC id\n");
13862 crtc = to_intel_crtc(drmmode_crtc);
13863 pipe_from_crtc_id->pipe = crtc->pipe;
13868 static int intel_encoder_clones(struct intel_encoder *encoder)
13870 struct drm_device *dev = encoder->base.dev;
13871 struct intel_encoder *source_encoder;
13872 int index_mask = 0;
13875 for_each_intel_encoder(dev, source_encoder) {
13876 if (encoders_cloneable(encoder, source_encoder))
13877 index_mask |= (1 << entry);
13885 static bool has_edp_a(struct drm_device *dev)
13887 struct drm_i915_private *dev_priv = dev->dev_private;
13889 if (!IS_MOBILE(dev))
13892 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13895 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13901 static bool intel_crt_present(struct drm_device *dev)
13903 struct drm_i915_private *dev_priv = dev->dev_private;
13905 if (INTEL_INFO(dev)->gen >= 9)
13908 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13911 if (IS_CHERRYVIEW(dev))
13914 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13920 static void intel_setup_outputs(struct drm_device *dev)
13922 struct drm_i915_private *dev_priv = dev->dev_private;
13923 struct intel_encoder *encoder;
13924 bool dpd_is_edp = false;
13926 intel_lvds_init(dev);
13928 if (intel_crt_present(dev))
13929 intel_crt_init(dev);
13931 if (IS_BROXTON(dev)) {
13933 * FIXME: Broxton doesn't support port detection via the
13934 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13935 * detect the ports.
13937 intel_ddi_init(dev, PORT_A);
13938 intel_ddi_init(dev, PORT_B);
13939 intel_ddi_init(dev, PORT_C);
13940 } else if (HAS_DDI(dev)) {
13944 * Haswell uses DDI functions to detect digital outputs.
13945 * On SKL pre-D0 the strap isn't connected, so we assume
13948 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13949 /* WaIgnoreDDIAStrap: skl */
13950 if (found || IS_SKYLAKE(dev))
13951 intel_ddi_init(dev, PORT_A);
13953 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13955 found = I915_READ(SFUSE_STRAP);
13957 if (found & SFUSE_STRAP_DDIB_DETECTED)
13958 intel_ddi_init(dev, PORT_B);
13959 if (found & SFUSE_STRAP_DDIC_DETECTED)
13960 intel_ddi_init(dev, PORT_C);
13961 if (found & SFUSE_STRAP_DDID_DETECTED)
13962 intel_ddi_init(dev, PORT_D);
13963 } else if (HAS_PCH_SPLIT(dev)) {
13965 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13967 if (has_edp_a(dev))
13968 intel_dp_init(dev, DP_A, PORT_A);
13970 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13971 /* PCH SDVOB multiplex with HDMIB */
13972 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13974 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13975 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13976 intel_dp_init(dev, PCH_DP_B, PORT_B);
13979 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13980 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13982 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13983 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13985 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13986 intel_dp_init(dev, PCH_DP_C, PORT_C);
13988 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13989 intel_dp_init(dev, PCH_DP_D, PORT_D);
13990 } else if (IS_VALLEYVIEW(dev)) {
13992 * The DP_DETECTED bit is the latched state of the DDC
13993 * SDA pin at boot. However since eDP doesn't require DDC
13994 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13995 * eDP ports may have been muxed to an alternate function.
13996 * Thus we can't rely on the DP_DETECTED bit alone to detect
13997 * eDP ports. Consult the VBT as well as DP_DETECTED to
13998 * detect eDP ports.
14000 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14001 !intel_dp_is_edp(dev, PORT_B))
14002 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14004 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14005 intel_dp_is_edp(dev, PORT_B))
14006 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14008 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14009 !intel_dp_is_edp(dev, PORT_C))
14010 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14012 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14013 intel_dp_is_edp(dev, PORT_C))
14014 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14016 if (IS_CHERRYVIEW(dev)) {
14017 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14018 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14020 /* eDP not supported on port D, so don't check VBT */
14021 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14022 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14025 intel_dsi_init(dev);
14026 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14027 bool found = false;
14029 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14030 DRM_DEBUG_KMS("probing SDVOB\n");
14031 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14032 if (!found && IS_G4X(dev)) {
14033 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14034 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14037 if (!found && IS_G4X(dev))
14038 intel_dp_init(dev, DP_B, PORT_B);
14041 /* Before G4X SDVOC doesn't have its own detect register */
14043 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14044 DRM_DEBUG_KMS("probing SDVOC\n");
14045 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14048 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14051 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14052 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14055 intel_dp_init(dev, DP_C, PORT_C);
14059 (I915_READ(DP_D) & DP_DETECTED))
14060 intel_dp_init(dev, DP_D, PORT_D);
14061 } else if (IS_GEN2(dev))
14062 intel_dvo_init(dev);
14064 if (SUPPORTS_TV(dev))
14065 intel_tv_init(dev);
14067 intel_psr_init(dev);
14069 for_each_intel_encoder(dev, encoder) {
14070 encoder->base.possible_crtcs = encoder->crtc_mask;
14071 encoder->base.possible_clones =
14072 intel_encoder_clones(encoder);
14075 intel_init_pch_refclk(dev);
14077 drm_helper_move_panel_connectors_to_head(dev);
14080 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14082 struct drm_device *dev = fb->dev;
14083 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14085 drm_framebuffer_cleanup(fb);
14086 mutex_lock(&dev->struct_mutex);
14087 WARN_ON(!intel_fb->obj->framebuffer_references--);
14088 drm_gem_object_unreference(&intel_fb->obj->base);
14089 mutex_unlock(&dev->struct_mutex);
14093 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14094 struct drm_file *file,
14095 unsigned int *handle)
14097 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14098 struct drm_i915_gem_object *obj = intel_fb->obj;
14100 return drm_gem_handle_create(file, &obj->base, handle);
14103 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14104 struct drm_file *file,
14105 unsigned flags, unsigned color,
14106 struct drm_clip_rect *clips,
14107 unsigned num_clips)
14109 struct drm_device *dev = fb->dev;
14110 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14111 struct drm_i915_gem_object *obj = intel_fb->obj;
14113 mutex_lock(&dev->struct_mutex);
14114 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14115 mutex_unlock(&dev->struct_mutex);
14120 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14121 .destroy = intel_user_framebuffer_destroy,
14122 .create_handle = intel_user_framebuffer_create_handle,
14123 .dirty = intel_user_framebuffer_dirty,
14127 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14128 uint32_t pixel_format)
14130 u32 gen = INTEL_INFO(dev)->gen;
14133 /* "The stride in bytes must not exceed the of the size of 8K
14134 * pixels and 32K bytes."
14136 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14137 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14139 } else if (gen >= 4) {
14140 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14144 } else if (gen >= 3) {
14145 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14150 /* XXX DSPC is limited to 4k tiled */
14155 static int intel_framebuffer_init(struct drm_device *dev,
14156 struct intel_framebuffer *intel_fb,
14157 struct drm_mode_fb_cmd2 *mode_cmd,
14158 struct drm_i915_gem_object *obj)
14160 unsigned int aligned_height;
14162 u32 pitch_limit, stride_alignment;
14164 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14166 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14167 /* Enforce that fb modifier and tiling mode match, but only for
14168 * X-tiled. This is needed for FBC. */
14169 if (!!(obj->tiling_mode == I915_TILING_X) !=
14170 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14171 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14175 if (obj->tiling_mode == I915_TILING_X)
14176 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14177 else if (obj->tiling_mode == I915_TILING_Y) {
14178 DRM_DEBUG("No Y tiling for legacy addfb\n");
14183 /* Passed in modifier sanity checking. */
14184 switch (mode_cmd->modifier[0]) {
14185 case I915_FORMAT_MOD_Y_TILED:
14186 case I915_FORMAT_MOD_Yf_TILED:
14187 if (INTEL_INFO(dev)->gen < 9) {
14188 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14189 mode_cmd->modifier[0]);
14192 case DRM_FORMAT_MOD_NONE:
14193 case I915_FORMAT_MOD_X_TILED:
14196 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14197 mode_cmd->modifier[0]);
14201 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14202 mode_cmd->pixel_format);
14203 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14204 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14205 mode_cmd->pitches[0], stride_alignment);
14209 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14210 mode_cmd->pixel_format);
14211 if (mode_cmd->pitches[0] > pitch_limit) {
14212 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14213 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14214 "tiled" : "linear",
14215 mode_cmd->pitches[0], pitch_limit);
14219 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14220 mode_cmd->pitches[0] != obj->stride) {
14221 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14222 mode_cmd->pitches[0], obj->stride);
14226 /* Reject formats not supported by any plane early. */
14227 switch (mode_cmd->pixel_format) {
14228 case DRM_FORMAT_C8:
14229 case DRM_FORMAT_RGB565:
14230 case DRM_FORMAT_XRGB8888:
14231 case DRM_FORMAT_ARGB8888:
14233 case DRM_FORMAT_XRGB1555:
14234 if (INTEL_INFO(dev)->gen > 3) {
14235 DRM_DEBUG("unsupported pixel format: %s\n",
14236 drm_get_format_name(mode_cmd->pixel_format));
14240 case DRM_FORMAT_ABGR8888:
14241 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14242 DRM_DEBUG("unsupported pixel format: %s\n",
14243 drm_get_format_name(mode_cmd->pixel_format));
14247 case DRM_FORMAT_XBGR8888:
14248 case DRM_FORMAT_XRGB2101010:
14249 case DRM_FORMAT_XBGR2101010:
14250 if (INTEL_INFO(dev)->gen < 4) {
14251 DRM_DEBUG("unsupported pixel format: %s\n",
14252 drm_get_format_name(mode_cmd->pixel_format));
14256 case DRM_FORMAT_ABGR2101010:
14257 if (!IS_VALLEYVIEW(dev)) {
14258 DRM_DEBUG("unsupported pixel format: %s\n",
14259 drm_get_format_name(mode_cmd->pixel_format));
14263 case DRM_FORMAT_YUYV:
14264 case DRM_FORMAT_UYVY:
14265 case DRM_FORMAT_YVYU:
14266 case DRM_FORMAT_VYUY:
14267 if (INTEL_INFO(dev)->gen < 5) {
14268 DRM_DEBUG("unsupported pixel format: %s\n",
14269 drm_get_format_name(mode_cmd->pixel_format));
14274 DRM_DEBUG("unsupported pixel format: %s\n",
14275 drm_get_format_name(mode_cmd->pixel_format));
14279 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14280 if (mode_cmd->offsets[0] != 0)
14283 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14284 mode_cmd->pixel_format,
14285 mode_cmd->modifier[0]);
14286 /* FIXME drm helper for size checks (especially planar formats)? */
14287 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14290 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14291 intel_fb->obj = obj;
14292 intel_fb->obj->framebuffer_references++;
14294 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14296 DRM_ERROR("framebuffer init failed %d\n", ret);
14303 static struct drm_framebuffer *
14304 intel_user_framebuffer_create(struct drm_device *dev,
14305 struct drm_file *filp,
14306 struct drm_mode_fb_cmd2 *mode_cmd)
14308 struct drm_i915_gem_object *obj;
14310 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14311 mode_cmd->handles[0]));
14312 if (&obj->base == NULL)
14313 return ERR_PTR(-ENOENT);
14315 return intel_framebuffer_create(dev, mode_cmd, obj);
14318 #ifndef CONFIG_DRM_FBDEV_EMULATION
14319 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14324 static const struct drm_mode_config_funcs intel_mode_funcs = {
14325 .fb_create = intel_user_framebuffer_create,
14326 .output_poll_changed = intel_fbdev_output_poll_changed,
14327 .atomic_check = intel_atomic_check,
14328 .atomic_commit = intel_atomic_commit,
14329 .atomic_state_alloc = intel_atomic_state_alloc,
14330 .atomic_state_clear = intel_atomic_state_clear,
14333 /* Set up chip specific display functions */
14334 static void intel_init_display(struct drm_device *dev)
14336 struct drm_i915_private *dev_priv = dev->dev_private;
14338 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14339 dev_priv->display.find_dpll = g4x_find_best_dpll;
14340 else if (IS_CHERRYVIEW(dev))
14341 dev_priv->display.find_dpll = chv_find_best_dpll;
14342 else if (IS_VALLEYVIEW(dev))
14343 dev_priv->display.find_dpll = vlv_find_best_dpll;
14344 else if (IS_PINEVIEW(dev))
14345 dev_priv->display.find_dpll = pnv_find_best_dpll;
14347 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14349 if (INTEL_INFO(dev)->gen >= 9) {
14350 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14351 dev_priv->display.get_initial_plane_config =
14352 skylake_get_initial_plane_config;
14353 dev_priv->display.crtc_compute_clock =
14354 haswell_crtc_compute_clock;
14355 dev_priv->display.crtc_enable = haswell_crtc_enable;
14356 dev_priv->display.crtc_disable = haswell_crtc_disable;
14357 dev_priv->display.update_primary_plane =
14358 skylake_update_primary_plane;
14359 } else if (HAS_DDI(dev)) {
14360 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14361 dev_priv->display.get_initial_plane_config =
14362 ironlake_get_initial_plane_config;
14363 dev_priv->display.crtc_compute_clock =
14364 haswell_crtc_compute_clock;
14365 dev_priv->display.crtc_enable = haswell_crtc_enable;
14366 dev_priv->display.crtc_disable = haswell_crtc_disable;
14367 dev_priv->display.update_primary_plane =
14368 ironlake_update_primary_plane;
14369 } else if (HAS_PCH_SPLIT(dev)) {
14370 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14371 dev_priv->display.get_initial_plane_config =
14372 ironlake_get_initial_plane_config;
14373 dev_priv->display.crtc_compute_clock =
14374 ironlake_crtc_compute_clock;
14375 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14376 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14377 dev_priv->display.update_primary_plane =
14378 ironlake_update_primary_plane;
14379 } else if (IS_VALLEYVIEW(dev)) {
14380 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14381 dev_priv->display.get_initial_plane_config =
14382 i9xx_get_initial_plane_config;
14383 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14384 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14385 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14386 dev_priv->display.update_primary_plane =
14387 i9xx_update_primary_plane;
14389 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14390 dev_priv->display.get_initial_plane_config =
14391 i9xx_get_initial_plane_config;
14392 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14393 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14394 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14395 dev_priv->display.update_primary_plane =
14396 i9xx_update_primary_plane;
14399 /* Returns the core display clock speed */
14400 if (IS_SKYLAKE(dev))
14401 dev_priv->display.get_display_clock_speed =
14402 skylake_get_display_clock_speed;
14403 else if (IS_BROXTON(dev))
14404 dev_priv->display.get_display_clock_speed =
14405 broxton_get_display_clock_speed;
14406 else if (IS_BROADWELL(dev))
14407 dev_priv->display.get_display_clock_speed =
14408 broadwell_get_display_clock_speed;
14409 else if (IS_HASWELL(dev))
14410 dev_priv->display.get_display_clock_speed =
14411 haswell_get_display_clock_speed;
14412 else if (IS_VALLEYVIEW(dev))
14413 dev_priv->display.get_display_clock_speed =
14414 valleyview_get_display_clock_speed;
14415 else if (IS_GEN5(dev))
14416 dev_priv->display.get_display_clock_speed =
14417 ilk_get_display_clock_speed;
14418 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14419 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14420 dev_priv->display.get_display_clock_speed =
14421 i945_get_display_clock_speed;
14422 else if (IS_GM45(dev))
14423 dev_priv->display.get_display_clock_speed =
14424 gm45_get_display_clock_speed;
14425 else if (IS_CRESTLINE(dev))
14426 dev_priv->display.get_display_clock_speed =
14427 i965gm_get_display_clock_speed;
14428 else if (IS_PINEVIEW(dev))
14429 dev_priv->display.get_display_clock_speed =
14430 pnv_get_display_clock_speed;
14431 else if (IS_G33(dev) || IS_G4X(dev))
14432 dev_priv->display.get_display_clock_speed =
14433 g33_get_display_clock_speed;
14434 else if (IS_I915G(dev))
14435 dev_priv->display.get_display_clock_speed =
14436 i915_get_display_clock_speed;
14437 else if (IS_I945GM(dev) || IS_845G(dev))
14438 dev_priv->display.get_display_clock_speed =
14439 i9xx_misc_get_display_clock_speed;
14440 else if (IS_PINEVIEW(dev))
14441 dev_priv->display.get_display_clock_speed =
14442 pnv_get_display_clock_speed;
14443 else if (IS_I915GM(dev))
14444 dev_priv->display.get_display_clock_speed =
14445 i915gm_get_display_clock_speed;
14446 else if (IS_I865G(dev))
14447 dev_priv->display.get_display_clock_speed =
14448 i865_get_display_clock_speed;
14449 else if (IS_I85X(dev))
14450 dev_priv->display.get_display_clock_speed =
14451 i85x_get_display_clock_speed;
14453 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14454 dev_priv->display.get_display_clock_speed =
14455 i830_get_display_clock_speed;
14458 if (IS_GEN5(dev)) {
14459 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14460 } else if (IS_GEN6(dev)) {
14461 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14462 } else if (IS_IVYBRIDGE(dev)) {
14463 /* FIXME: detect B0+ stepping and use auto training */
14464 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14465 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14466 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14467 if (IS_BROADWELL(dev)) {
14468 dev_priv->display.modeset_commit_cdclk =
14469 broadwell_modeset_commit_cdclk;
14470 dev_priv->display.modeset_calc_cdclk =
14471 broadwell_modeset_calc_cdclk;
14473 } else if (IS_VALLEYVIEW(dev)) {
14474 dev_priv->display.modeset_commit_cdclk =
14475 valleyview_modeset_commit_cdclk;
14476 dev_priv->display.modeset_calc_cdclk =
14477 valleyview_modeset_calc_cdclk;
14478 } else if (IS_BROXTON(dev)) {
14479 dev_priv->display.modeset_commit_cdclk =
14480 broxton_modeset_commit_cdclk;
14481 dev_priv->display.modeset_calc_cdclk =
14482 broxton_modeset_calc_cdclk;
14485 switch (INTEL_INFO(dev)->gen) {
14487 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14491 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14496 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14500 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14503 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14504 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14507 /* Drop through - unsupported since execlist only. */
14509 /* Default just returns -ENODEV to indicate unsupported */
14510 dev_priv->display.queue_flip = intel_default_queue_flip;
14513 intel_panel_init_backlight_funcs(dev);
14515 mutex_init(&dev_priv->pps_mutex);
14519 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14520 * resume, or other times. This quirk makes sure that's the case for
14521 * affected systems.
14523 static void quirk_pipea_force(struct drm_device *dev)
14525 struct drm_i915_private *dev_priv = dev->dev_private;
14527 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14528 DRM_INFO("applying pipe a force quirk\n");
14531 static void quirk_pipeb_force(struct drm_device *dev)
14533 struct drm_i915_private *dev_priv = dev->dev_private;
14535 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14536 DRM_INFO("applying pipe b force quirk\n");
14540 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14542 static void quirk_ssc_force_disable(struct drm_device *dev)
14544 struct drm_i915_private *dev_priv = dev->dev_private;
14545 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14546 DRM_INFO("applying lvds SSC disable quirk\n");
14550 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14553 static void quirk_invert_brightness(struct drm_device *dev)
14555 struct drm_i915_private *dev_priv = dev->dev_private;
14556 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14557 DRM_INFO("applying inverted panel brightness quirk\n");
14560 /* Some VBT's incorrectly indicate no backlight is present */
14561 static void quirk_backlight_present(struct drm_device *dev)
14563 struct drm_i915_private *dev_priv = dev->dev_private;
14564 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14565 DRM_INFO("applying backlight present quirk\n");
14568 struct intel_quirk {
14570 int subsystem_vendor;
14571 int subsystem_device;
14572 void (*hook)(struct drm_device *dev);
14575 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14576 struct intel_dmi_quirk {
14577 void (*hook)(struct drm_device *dev);
14578 const struct dmi_system_id (*dmi_id_list)[];
14581 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14583 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14587 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14589 .dmi_id_list = &(const struct dmi_system_id[]) {
14591 .callback = intel_dmi_reverse_brightness,
14592 .ident = "NCR Corporation",
14593 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14594 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14597 { } /* terminating entry */
14599 .hook = quirk_invert_brightness,
14603 static struct intel_quirk intel_quirks[] = {
14604 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14605 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14607 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14608 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14610 /* 830 needs to leave pipe A & dpll A up */
14611 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14613 /* 830 needs to leave pipe B & dpll B up */
14614 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14616 /* Lenovo U160 cannot use SSC on LVDS */
14617 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14619 /* Sony Vaio Y cannot use SSC on LVDS */
14620 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14622 /* Acer Aspire 5734Z must invert backlight brightness */
14623 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14625 /* Acer/eMachines G725 */
14626 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14628 /* Acer/eMachines e725 */
14629 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14631 /* Acer/Packard Bell NCL20 */
14632 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14634 /* Acer Aspire 4736Z */
14635 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14637 /* Acer Aspire 5336 */
14638 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14640 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14641 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14643 /* Acer C720 Chromebook (Core i3 4005U) */
14644 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14646 /* Apple Macbook 2,1 (Core 2 T7400) */
14647 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14649 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14650 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14652 /* HP Chromebook 14 (Celeron 2955U) */
14653 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14655 /* Dell Chromebook 11 */
14656 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14659 static void intel_init_quirks(struct drm_device *dev)
14661 struct pci_dev *d = dev->pdev;
14664 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14665 struct intel_quirk *q = &intel_quirks[i];
14667 if (d->device == q->device &&
14668 (d->subsystem_vendor == q->subsystem_vendor ||
14669 q->subsystem_vendor == PCI_ANY_ID) &&
14670 (d->subsystem_device == q->subsystem_device ||
14671 q->subsystem_device == PCI_ANY_ID))
14674 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14675 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14676 intel_dmi_quirks[i].hook(dev);
14680 /* Disable the VGA plane that we never use */
14681 static void i915_disable_vga(struct drm_device *dev)
14683 struct drm_i915_private *dev_priv = dev->dev_private;
14685 u32 vga_reg = i915_vgacntrl_reg(dev);
14687 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14688 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14689 outb(SR01, VGA_SR_INDEX);
14690 sr1 = inb(VGA_SR_DATA);
14691 outb(sr1 | 1<<5, VGA_SR_DATA);
14692 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14695 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14696 POSTING_READ(vga_reg);
14699 void intel_modeset_init_hw(struct drm_device *dev)
14701 intel_update_cdclk(dev);
14702 intel_prepare_ddi(dev);
14703 intel_init_clock_gating(dev);
14704 intel_enable_gt_powersave(dev);
14707 void intel_modeset_init(struct drm_device *dev)
14709 struct drm_i915_private *dev_priv = dev->dev_private;
14712 struct intel_crtc *crtc;
14714 drm_mode_config_init(dev);
14716 dev->mode_config.min_width = 0;
14717 dev->mode_config.min_height = 0;
14719 dev->mode_config.preferred_depth = 24;
14720 dev->mode_config.prefer_shadow = 1;
14722 dev->mode_config.allow_fb_modifiers = true;
14724 dev->mode_config.funcs = &intel_mode_funcs;
14726 intel_init_quirks(dev);
14728 intel_init_pm(dev);
14730 if (INTEL_INFO(dev)->num_pipes == 0)
14733 intel_init_display(dev);
14734 intel_init_audio(dev);
14736 if (IS_GEN2(dev)) {
14737 dev->mode_config.max_width = 2048;
14738 dev->mode_config.max_height = 2048;
14739 } else if (IS_GEN3(dev)) {
14740 dev->mode_config.max_width = 4096;
14741 dev->mode_config.max_height = 4096;
14743 dev->mode_config.max_width = 8192;
14744 dev->mode_config.max_height = 8192;
14747 if (IS_845G(dev) || IS_I865G(dev)) {
14748 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14749 dev->mode_config.cursor_height = 1023;
14750 } else if (IS_GEN2(dev)) {
14751 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14752 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14754 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14755 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14758 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14760 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14761 INTEL_INFO(dev)->num_pipes,
14762 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14764 for_each_pipe(dev_priv, pipe) {
14765 intel_crtc_init(dev, pipe);
14766 for_each_sprite(dev_priv, pipe, sprite) {
14767 ret = intel_plane_init(dev, pipe, sprite);
14769 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14770 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14774 intel_init_dpio(dev);
14776 intel_shared_dpll_init(dev);
14778 /* Just disable it once at startup */
14779 i915_disable_vga(dev);
14780 intel_setup_outputs(dev);
14782 /* Just in case the BIOS is doing something questionable. */
14783 intel_fbc_disable(dev_priv);
14785 drm_modeset_lock_all(dev);
14786 intel_modeset_setup_hw_state(dev);
14787 drm_modeset_unlock_all(dev);
14789 for_each_intel_crtc(dev, crtc) {
14790 struct intel_initial_plane_config plane_config = {};
14796 * Note that reserving the BIOS fb up front prevents us
14797 * from stuffing other stolen allocations like the ring
14798 * on top. This prevents some ugliness at boot time, and
14799 * can even allow for smooth boot transitions if the BIOS
14800 * fb is large enough for the active pipe configuration.
14802 dev_priv->display.get_initial_plane_config(crtc,
14806 * If the fb is shared between multiple heads, we'll
14807 * just get the first one.
14809 intel_find_initial_plane_obj(crtc, &plane_config);
14813 static void intel_enable_pipe_a(struct drm_device *dev)
14815 struct intel_connector *connector;
14816 struct drm_connector *crt = NULL;
14817 struct intel_load_detect_pipe load_detect_temp;
14818 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14820 /* We can't just switch on the pipe A, we need to set things up with a
14821 * proper mode and output configuration. As a gross hack, enable pipe A
14822 * by enabling the load detect pipe once. */
14823 for_each_intel_connector(dev, connector) {
14824 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14825 crt = &connector->base;
14833 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14834 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14838 intel_check_plane_mapping(struct intel_crtc *crtc)
14840 struct drm_device *dev = crtc->base.dev;
14841 struct drm_i915_private *dev_priv = dev->dev_private;
14844 if (INTEL_INFO(dev)->num_pipes == 1)
14847 reg = DSPCNTR(!crtc->plane);
14848 val = I915_READ(reg);
14850 if ((val & DISPLAY_PLANE_ENABLE) &&
14851 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14857 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14859 struct drm_device *dev = crtc->base.dev;
14860 struct drm_i915_private *dev_priv = dev->dev_private;
14861 struct intel_encoder *encoder;
14865 /* Clear any frame start delays used for debugging left by the BIOS */
14866 reg = PIPECONF(crtc->config->cpu_transcoder);
14867 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14869 /* restore vblank interrupts to correct state */
14870 drm_crtc_vblank_reset(&crtc->base);
14871 if (crtc->active) {
14872 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14873 update_scanline_offset(crtc);
14874 drm_crtc_vblank_on(&crtc->base);
14877 /* We need to sanitize the plane -> pipe mapping first because this will
14878 * disable the crtc (and hence change the state) if it is wrong. Note
14879 * that gen4+ has a fixed plane -> pipe mapping. */
14880 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14883 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14884 crtc->base.base.id);
14886 /* Pipe has the wrong plane attached and the plane is active.
14887 * Temporarily change the plane mapping and disable everything
14889 plane = crtc->plane;
14890 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14891 crtc->plane = !plane;
14892 intel_crtc_disable_noatomic(&crtc->base);
14893 crtc->plane = plane;
14896 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14897 crtc->pipe == PIPE_A && !crtc->active) {
14898 /* BIOS forgot to enable pipe A, this mostly happens after
14899 * resume. Force-enable the pipe to fix this, the update_dpms
14900 * call below we restore the pipe to the right state, but leave
14901 * the required bits on. */
14902 intel_enable_pipe_a(dev);
14905 /* Adjust the state of the output pipe according to whether we
14906 * have active connectors/encoders. */
14908 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14914 intel_crtc_disable_noatomic(&crtc->base);
14916 if (crtc->active != crtc->base.state->active) {
14918 /* This can happen either due to bugs in the get_hw_state
14919 * functions or because of calls to intel_crtc_disable_noatomic,
14920 * or because the pipe is force-enabled due to the
14922 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14923 crtc->base.base.id,
14924 crtc->base.state->enable ? "enabled" : "disabled",
14925 crtc->active ? "enabled" : "disabled");
14927 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14928 crtc->base.state->active = crtc->active;
14929 crtc->base.enabled = crtc->active;
14931 /* Because we only establish the connector -> encoder ->
14932 * crtc links if something is active, this means the
14933 * crtc is now deactivated. Break the links. connector
14934 * -> encoder links are only establish when things are
14935 * actually up, hence no need to break them. */
14936 WARN_ON(crtc->active);
14938 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14939 encoder->base.crtc = NULL;
14942 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14944 * We start out with underrun reporting disabled to avoid races.
14945 * For correct bookkeeping mark this on active crtcs.
14947 * Also on gmch platforms we dont have any hardware bits to
14948 * disable the underrun reporting. Which means we need to start
14949 * out with underrun reporting disabled also on inactive pipes,
14950 * since otherwise we'll complain about the garbage we read when
14951 * e.g. coming up after runtime pm.
14953 * No protection against concurrent access is required - at
14954 * worst a fifo underrun happens which also sets this to false.
14956 crtc->cpu_fifo_underrun_disabled = true;
14957 crtc->pch_fifo_underrun_disabled = true;
14961 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14963 struct intel_connector *connector;
14964 struct drm_device *dev = encoder->base.dev;
14965 bool active = false;
14967 /* We need to check both for a crtc link (meaning that the
14968 * encoder is active and trying to read from a pipe) and the
14969 * pipe itself being active. */
14970 bool has_active_crtc = encoder->base.crtc &&
14971 to_intel_crtc(encoder->base.crtc)->active;
14973 for_each_intel_connector(dev, connector) {
14974 if (connector->base.encoder != &encoder->base)
14981 if (active && !has_active_crtc) {
14982 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14983 encoder->base.base.id,
14984 encoder->base.name);
14986 /* Connector is active, but has no active pipe. This is
14987 * fallout from our resume register restoring. Disable
14988 * the encoder manually again. */
14989 if (encoder->base.crtc) {
14990 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14991 encoder->base.base.id,
14992 encoder->base.name);
14993 encoder->disable(encoder);
14994 if (encoder->post_disable)
14995 encoder->post_disable(encoder);
14997 encoder->base.crtc = NULL;
14999 /* Inconsistent output/port/pipe state happens presumably due to
15000 * a bug in one of the get_hw_state functions. Or someplace else
15001 * in our code, like the register restore mess on resume. Clamp
15002 * things to off as a safer default. */
15003 for_each_intel_connector(dev, connector) {
15004 if (connector->encoder != encoder)
15006 connector->base.dpms = DRM_MODE_DPMS_OFF;
15007 connector->base.encoder = NULL;
15010 /* Enabled encoders without active connectors will be fixed in
15011 * the crtc fixup. */
15014 void i915_redisable_vga_power_on(struct drm_device *dev)
15016 struct drm_i915_private *dev_priv = dev->dev_private;
15017 u32 vga_reg = i915_vgacntrl_reg(dev);
15019 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15020 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15021 i915_disable_vga(dev);
15025 void i915_redisable_vga(struct drm_device *dev)
15027 struct drm_i915_private *dev_priv = dev->dev_private;
15029 /* This function can be called both from intel_modeset_setup_hw_state or
15030 * at a very early point in our resume sequence, where the power well
15031 * structures are not yet restored. Since this function is at a very
15032 * paranoid "someone might have enabled VGA while we were not looking"
15033 * level, just check if the power well is enabled instead of trying to
15034 * follow the "don't touch the power well if we don't need it" policy
15035 * the rest of the driver uses. */
15036 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15039 i915_redisable_vga_power_on(dev);
15042 static bool primary_get_hw_state(struct intel_crtc *crtc)
15044 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15046 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15049 static void readout_plane_state(struct intel_crtc *crtc,
15050 struct intel_crtc_state *crtc_state)
15052 struct intel_plane *p;
15053 struct intel_plane_state *plane_state;
15054 bool active = crtc_state->base.active;
15056 for_each_intel_plane(crtc->base.dev, p) {
15057 if (crtc->pipe != p->pipe)
15060 plane_state = to_intel_plane_state(p->base.state);
15062 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15063 plane_state->visible = primary_get_hw_state(crtc);
15066 p->disable_plane(&p->base, &crtc->base);
15068 plane_state->visible = false;
15073 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15075 struct drm_i915_private *dev_priv = dev->dev_private;
15077 struct intel_crtc *crtc;
15078 struct intel_encoder *encoder;
15079 struct intel_connector *connector;
15082 for_each_intel_crtc(dev, crtc) {
15083 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15084 memset(crtc->config, 0, sizeof(*crtc->config));
15085 crtc->config->base.crtc = &crtc->base;
15087 crtc->active = dev_priv->display.get_pipe_config(crtc,
15090 crtc->base.state->active = crtc->active;
15091 crtc->base.enabled = crtc->active;
15093 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15094 if (crtc->base.state->active) {
15095 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15096 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15097 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15100 * The initial mode needs to be set in order to keep
15101 * the atomic core happy. It wants a valid mode if the
15102 * crtc's enabled, so we do the above call.
15104 * At this point some state updated by the connectors
15105 * in their ->detect() callback has not run yet, so
15106 * no recalculation can be done yet.
15108 * Even if we could do a recalculation and modeset
15109 * right now it would cause a double modeset if
15110 * fbdev or userspace chooses a different initial mode.
15112 * If that happens, someone indicated they wanted a
15113 * mode change, which means it's safe to do a full
15116 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15119 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15120 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15122 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15123 crtc->base.base.id,
15124 crtc->active ? "enabled" : "disabled");
15127 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15128 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15130 pll->on = pll->get_hw_state(dev_priv, pll,
15131 &pll->config.hw_state);
15133 pll->config.crtc_mask = 0;
15134 for_each_intel_crtc(dev, crtc) {
15135 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15137 pll->config.crtc_mask |= 1 << crtc->pipe;
15141 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15142 pll->name, pll->config.crtc_mask, pll->on);
15144 if (pll->config.crtc_mask)
15145 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15148 for_each_intel_encoder(dev, encoder) {
15151 if (encoder->get_hw_state(encoder, &pipe)) {
15152 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15153 encoder->base.crtc = &crtc->base;
15154 encoder->get_config(encoder, crtc->config);
15156 encoder->base.crtc = NULL;
15159 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15160 encoder->base.base.id,
15161 encoder->base.name,
15162 encoder->base.crtc ? "enabled" : "disabled",
15166 for_each_intel_connector(dev, connector) {
15167 if (connector->get_hw_state(connector)) {
15168 connector->base.dpms = DRM_MODE_DPMS_ON;
15169 connector->base.encoder = &connector->encoder->base;
15171 connector->base.dpms = DRM_MODE_DPMS_OFF;
15172 connector->base.encoder = NULL;
15174 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15175 connector->base.base.id,
15176 connector->base.name,
15177 connector->base.encoder ? "enabled" : "disabled");
15181 /* Scan out the current hw modeset state,
15182 * and sanitizes it to the current state
15185 intel_modeset_setup_hw_state(struct drm_device *dev)
15187 struct drm_i915_private *dev_priv = dev->dev_private;
15189 struct intel_crtc *crtc;
15190 struct intel_encoder *encoder;
15193 intel_modeset_readout_hw_state(dev);
15195 /* HW state is read out, now we need to sanitize this mess. */
15196 for_each_intel_encoder(dev, encoder) {
15197 intel_sanitize_encoder(encoder);
15200 for_each_pipe(dev_priv, pipe) {
15201 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15202 intel_sanitize_crtc(crtc);
15203 intel_dump_pipe_config(crtc, crtc->config,
15204 "[setup_hw_state]");
15207 intel_modeset_update_connector_atomic_state(dev);
15209 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15210 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15212 if (!pll->on || pll->active)
15215 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15217 pll->disable(dev_priv, pll);
15221 if (IS_VALLEYVIEW(dev))
15222 vlv_wm_get_hw_state(dev);
15223 else if (IS_GEN9(dev))
15224 skl_wm_get_hw_state(dev);
15225 else if (HAS_PCH_SPLIT(dev))
15226 ilk_wm_get_hw_state(dev);
15228 for_each_intel_crtc(dev, crtc) {
15229 unsigned long put_domains;
15231 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15232 if (WARN_ON(put_domains))
15233 modeset_put_power_domains(dev_priv, put_domains);
15235 intel_display_set_init_power(dev_priv, false);
15238 void intel_display_resume(struct drm_device *dev)
15240 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15241 struct intel_connector *conn;
15242 struct intel_plane *plane;
15243 struct drm_crtc *crtc;
15249 state->acquire_ctx = dev->mode_config.acquire_ctx;
15251 /* preserve complete old state, including dpll */
15252 intel_atomic_get_shared_dpll_state(state);
15254 for_each_crtc(dev, crtc) {
15255 struct drm_crtc_state *crtc_state =
15256 drm_atomic_get_crtc_state(state, crtc);
15258 ret = PTR_ERR_OR_ZERO(crtc_state);
15262 /* force a restore */
15263 crtc_state->mode_changed = true;
15266 for_each_intel_plane(dev, plane) {
15267 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15272 for_each_intel_connector(dev, conn) {
15273 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15278 intel_modeset_setup_hw_state(dev);
15280 i915_redisable_vga(dev);
15281 ret = drm_atomic_commit(state);
15286 DRM_ERROR("Restoring old state failed with %i\n", ret);
15287 drm_atomic_state_free(state);
15290 void intel_modeset_gem_init(struct drm_device *dev)
15292 struct drm_i915_private *dev_priv = dev->dev_private;
15293 struct drm_crtc *c;
15294 struct drm_i915_gem_object *obj;
15297 mutex_lock(&dev->struct_mutex);
15298 intel_init_gt_powersave(dev);
15299 mutex_unlock(&dev->struct_mutex);
15302 * There may be no VBT; and if the BIOS enabled SSC we can
15303 * just keep using it to avoid unnecessary flicker. Whereas if the
15304 * BIOS isn't using it, don't assume it will work even if the VBT
15305 * indicates as much.
15307 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15308 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15311 intel_modeset_init_hw(dev);
15313 intel_setup_overlay(dev);
15316 * Make sure any fbs we allocated at startup are properly
15317 * pinned & fenced. When we do the allocation it's too early
15320 for_each_crtc(dev, c) {
15321 obj = intel_fb_obj(c->primary->fb);
15325 mutex_lock(&dev->struct_mutex);
15326 ret = intel_pin_and_fence_fb_obj(c->primary,
15330 mutex_unlock(&dev->struct_mutex);
15332 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15333 to_intel_crtc(c)->pipe);
15334 drm_framebuffer_unreference(c->primary->fb);
15335 c->primary->fb = NULL;
15336 c->primary->crtc = c->primary->state->crtc = NULL;
15337 update_state_fb(c->primary);
15338 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15342 intel_backlight_register(dev);
15345 void intel_connector_unregister(struct intel_connector *intel_connector)
15347 struct drm_connector *connector = &intel_connector->base;
15349 intel_panel_destroy_backlight(connector);
15350 drm_connector_unregister(connector);
15353 void intel_modeset_cleanup(struct drm_device *dev)
15355 struct drm_i915_private *dev_priv = dev->dev_private;
15356 struct drm_connector *connector;
15358 intel_disable_gt_powersave(dev);
15360 intel_backlight_unregister(dev);
15363 * Interrupts and polling as the first thing to avoid creating havoc.
15364 * Too much stuff here (turning of connectors, ...) would
15365 * experience fancy races otherwise.
15367 intel_irq_uninstall(dev_priv);
15370 * Due to the hpd irq storm handling the hotplug work can re-arm the
15371 * poll handlers. Hence disable polling after hpd handling is shut down.
15373 drm_kms_helper_poll_fini(dev);
15375 intel_unregister_dsm_handler();
15377 intel_fbc_disable(dev_priv);
15379 /* flush any delayed tasks or pending work */
15380 flush_scheduled_work();
15382 /* destroy the backlight and sysfs files before encoders/connectors */
15383 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15384 struct intel_connector *intel_connector;
15386 intel_connector = to_intel_connector(connector);
15387 intel_connector->unregister(intel_connector);
15390 drm_mode_config_cleanup(dev);
15392 intel_cleanup_overlay(dev);
15394 mutex_lock(&dev->struct_mutex);
15395 intel_cleanup_gt_powersave(dev);
15396 mutex_unlock(&dev->struct_mutex);
15400 * Return which encoder is currently attached for connector.
15402 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15404 return &intel_attached_encoder(connector)->base;
15407 void intel_connector_attach_encoder(struct intel_connector *connector,
15408 struct intel_encoder *encoder)
15410 connector->encoder = encoder;
15411 drm_mode_connector_attach_encoder(&connector->base,
15416 * set vga decode state - true == enable VGA decode
15418 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15420 struct drm_i915_private *dev_priv = dev->dev_private;
15421 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15424 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15425 DRM_ERROR("failed to read control word\n");
15429 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15433 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15435 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15437 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15438 DRM_ERROR("failed to write control word\n");
15445 struct intel_display_error_state {
15447 u32 power_well_driver;
15449 int num_transcoders;
15451 struct intel_cursor_error_state {
15456 } cursor[I915_MAX_PIPES];
15458 struct intel_pipe_error_state {
15459 bool power_domain_on;
15462 } pipe[I915_MAX_PIPES];
15464 struct intel_plane_error_state {
15472 } plane[I915_MAX_PIPES];
15474 struct intel_transcoder_error_state {
15475 bool power_domain_on;
15476 enum transcoder cpu_transcoder;
15489 struct intel_display_error_state *
15490 intel_display_capture_error_state(struct drm_device *dev)
15492 struct drm_i915_private *dev_priv = dev->dev_private;
15493 struct intel_display_error_state *error;
15494 int transcoders[] = {
15502 if (INTEL_INFO(dev)->num_pipes == 0)
15505 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15509 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15510 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15512 for_each_pipe(dev_priv, i) {
15513 error->pipe[i].power_domain_on =
15514 __intel_display_power_is_enabled(dev_priv,
15515 POWER_DOMAIN_PIPE(i));
15516 if (!error->pipe[i].power_domain_on)
15519 error->cursor[i].control = I915_READ(CURCNTR(i));
15520 error->cursor[i].position = I915_READ(CURPOS(i));
15521 error->cursor[i].base = I915_READ(CURBASE(i));
15523 error->plane[i].control = I915_READ(DSPCNTR(i));
15524 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15525 if (INTEL_INFO(dev)->gen <= 3) {
15526 error->plane[i].size = I915_READ(DSPSIZE(i));
15527 error->plane[i].pos = I915_READ(DSPPOS(i));
15529 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15530 error->plane[i].addr = I915_READ(DSPADDR(i));
15531 if (INTEL_INFO(dev)->gen >= 4) {
15532 error->plane[i].surface = I915_READ(DSPSURF(i));
15533 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15536 error->pipe[i].source = I915_READ(PIPESRC(i));
15538 if (HAS_GMCH_DISPLAY(dev))
15539 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15542 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15543 if (HAS_DDI(dev_priv->dev))
15544 error->num_transcoders++; /* Account for eDP. */
15546 for (i = 0; i < error->num_transcoders; i++) {
15547 enum transcoder cpu_transcoder = transcoders[i];
15549 error->transcoder[i].power_domain_on =
15550 __intel_display_power_is_enabled(dev_priv,
15551 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15552 if (!error->transcoder[i].power_domain_on)
15555 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15557 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15558 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15559 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15560 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15561 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15562 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15563 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15569 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15572 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15573 struct drm_device *dev,
15574 struct intel_display_error_state *error)
15576 struct drm_i915_private *dev_priv = dev->dev_private;
15582 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15583 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15584 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15585 error->power_well_driver);
15586 for_each_pipe(dev_priv, i) {
15587 err_printf(m, "Pipe [%d]:\n", i);
15588 err_printf(m, " Power: %s\n",
15589 error->pipe[i].power_domain_on ? "on" : "off");
15590 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15591 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15593 err_printf(m, "Plane [%d]:\n", i);
15594 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15595 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15596 if (INTEL_INFO(dev)->gen <= 3) {
15597 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15598 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15600 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15601 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15602 if (INTEL_INFO(dev)->gen >= 4) {
15603 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15604 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15607 err_printf(m, "Cursor [%d]:\n", i);
15608 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15609 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15610 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15613 for (i = 0; i < error->num_transcoders; i++) {
15614 err_printf(m, "CPU transcoder: %c\n",
15615 transcoder_name(error->transcoder[i].cpu_transcoder));
15616 err_printf(m, " Power: %s\n",
15617 error->transcoder[i].power_domain_on ? "on" : "off");
15618 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15619 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15620 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15621 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15622 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15623 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15624 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15628 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15630 struct intel_crtc *crtc;
15632 for_each_intel_crtc(dev, crtc) {
15633 struct intel_unpin_work *work;
15635 spin_lock_irq(&dev->event_lock);
15637 work = crtc->unpin_work;
15639 if (work && work->event &&
15640 work->event->base.file_priv == file) {
15641 kfree(work->event);
15642 work->event = NULL;
15645 spin_unlock_irq(&dev->event_lock);