2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
101 static inline u32 /* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device *dev)
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
111 static const intel_limit_t intel_limits_i8xx_dvo = {
112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
122 .find_pll = intel_find_best_PLL,
125 static const intel_limit_t intel_limits_i8xx_lvds = {
126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
136 .find_pll = intel_find_best_PLL,
139 static const intel_limit_t intel_limits_i9xx_sdvo = {
140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
150 .find_pll = intel_find_best_PLL,
153 static const intel_limit_t intel_limits_i9xx_lvds = {
154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
164 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_g4x_sdvo = {
169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
181 .find_pll = intel_g4x_find_best_PLL,
184 static const intel_limit_t intel_limits_g4x_hdmi = {
185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
195 .find_pll = intel_g4x_find_best_PLL,
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
225 .find_pll = intel_g4x_find_best_PLL,
228 static const intel_limit_t intel_limits_g4x_display_port = {
229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 10, .p2_fast = 10 },
239 .find_pll = intel_find_pll_g4x_dp,
242 static const intel_limit_t intel_limits_pineview_sdvo = {
243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
255 .find_pll = intel_find_best_PLL,
258 static const intel_limit_t intel_limits_pineview_lvds = {
259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
269 .find_pll = intel_find_best_PLL,
272 /* Ironlake / Sandybridge
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
277 static const intel_limit_t intel_limits_ironlake_dac = {
278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
288 .find_pll = intel_g4x_find_best_PLL,
291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
302 .find_pll = intel_g4x_find_best_PLL,
305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
316 .find_pll = intel_g4x_find_best_PLL,
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
348 static const intel_limit_t intel_limits_ironlake_display_port = {
349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 10, .p2_fast = 10 },
359 .find_pll = intel_find_pll_ironlake_dp,
362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
380 val = I915_READ(DPIO_DATA);
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
387 static void vlv_init_dpio(struct drm_device *dev)
389 struct drm_i915_private *dev_priv = dev->dev_private;
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
404 static const struct dmi_system_id intel_dual_link_lvds[] = {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
413 { } /* terminating entry */
416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
425 if (dmi_check_system(intel_dual_link_lvds))
428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449 const intel_limit_t *limit;
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
453 /* LVDS dual channel */
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_dual_lvds_100m;
457 limit = &intel_limits_ironlake_dual_lvds;
459 if (refclk == 100000)
460 limit = &intel_limits_ironlake_single_lvds_100m;
462 limit = &intel_limits_ironlake_single_lvds;
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
466 limit = &intel_limits_ironlake_display_port;
468 limit = &intel_limits_ironlake_dac;
473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
480 if (is_dual_link_lvds(dev_priv, LVDS))
481 /* LVDS with dual channel */
482 limit = &intel_limits_g4x_dual_channel_lvds;
484 /* LVDS with dual channel */
485 limit = &intel_limits_g4x_single_channel_lvds;
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
488 limit = &intel_limits_g4x_hdmi;
489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
490 limit = &intel_limits_g4x_sdvo;
491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
492 limit = &intel_limits_g4x_display_port;
493 } else /* The option is for other outputs */
494 limit = &intel_limits_i9xx_sdvo;
499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
504 if (HAS_PCH_SPLIT(dev))
505 limit = intel_ironlake_limit(crtc, refclk);
506 else if (IS_G4X(dev)) {
507 limit = intel_g4x_limit(crtc);
508 } else if (IS_PINEVIEW(dev)) {
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_pineview_lvds;
512 limit = &intel_limits_pineview_sdvo;
513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
517 limit = &intel_limits_i9xx_sdvo;
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
520 limit = &intel_limits_i8xx_lvds;
522 limit = &intel_limits_i8xx_dvo;
527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
528 static void pineview_clock(int refclk, intel_clock_t *clock)
530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
549 * Returns whether any output on the specified pipe is of the specified type
551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
564 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
570 static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->p < limit->p.min || limit->p.max < clock->p)
577 INTELPllInvalid("p out of range\n");
578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
579 INTELPllInvalid("m2 out of range\n");
580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
581 INTELPllInvalid("m1 out of range\n");
582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
583 INTELPllInvalid("m1 <= m2\n");
584 if (clock->m < limit->m.min || limit->m.max < clock->m)
585 INTELPllInvalid("m out of range\n");
586 if (clock->n < limit->n.min || limit->n.max < clock->n)
587 INTELPllInvalid("n out of range\n");
588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
589 INTELPllInvalid("vco out of range\n");
590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
594 INTELPllInvalid("dot out of range\n");
600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
611 (I915_READ(LVDS)) != 0) {
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
618 if (is_dual_link_lvds(dev_priv, LVDS))
619 clock.p2 = limit->p2.p2_fast;
621 clock.p2 = limit->p2.p2_slow;
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
626 clock.p2 = limit->p2.p2_fast;
629 memset(best_clock, 0, sizeof(*best_clock));
631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
644 intel_clock(dev, refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
649 clock.p != match_clock->p)
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
662 return (err != target);
666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if (HAS_PCH_SPLIT(dev))
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
688 clock.p2 = limit->p2.p2_fast;
690 clock.p2 = limit->p2.p2_slow;
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
695 clock.p2 = limit->p2.p2_fast;
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
700 /* based on hardware requirement, prefer smaller n to precision */
701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
702 /* based on hardware requirement, prefere larger m1,m2 */
703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
711 intel_clock(dev, refclk, &clock);
712 if (!intel_PLL_is_valid(dev, limit,
716 clock.p != match_clock->p)
719 this_err = abs(clock.dot - target);
720 if (this_err < err_most) {
734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
738 struct drm_device *dev = crtc->dev;
741 if (target < 200000) {
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
766 if (target < 200000) {
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
787 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
792 frame = I915_READ(frame_reg);
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
799 * intel_wait_for_vblank - wait for vblank on a given pipe
801 * @pipe: pipe to wait for
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
806 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 int pipestat_reg = PIPESTAT(pipe);
811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
832 /* Wait for vblank interrupt bit to set */
833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
836 DRM_DEBUG_KMS("vblank wait timed out\n");
840 * intel_wait_for_pipe_off - wait for pipe to turn off
842 * @pipe: pipe to wait for
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
849 * wait for the pipe register state bit to turn off
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
856 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
858 struct drm_i915_private *dev_priv = dev->dev_private;
860 if (INTEL_INFO(dev)->gen >= 4) {
861 int reg = PIPECONF(pipe);
863 /* Wait for the Pipe State to go off */
864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
868 u32 last_line, line_mask;
869 int reg = PIPEDSL(pipe);
870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
873 line_mask = DSL_LINEMASK_GEN2;
875 line_mask = DSL_LINEMASK_GEN3;
877 /* Wait for the display line to settle */
879 last_line = I915_READ(reg) & line_mask;
881 } while (((I915_READ(reg) & line_mask) != last_line) &&
882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
888 static const char *state_string(bool enabled)
890 return enabled ? "on" : "off";
893 /* Only for pre-ILK configs */
894 static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
912 static void assert_pch_pll(struct drm_i915_private *dev_priv,
913 struct intel_pch_pll *pll,
914 struct intel_crtc *crtc,
920 if (HAS_PCH_LPT(dev_priv->dev)) {
921 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
926 "asserting PCH PLL %s with no PLL\n", state_string(state)))
929 val = I915_READ(pll->pll_reg);
930 cur_state = !!(val & DPLL_VCO_ENABLE);
931 WARN(cur_state != state,
932 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
933 pll->pll_reg, state_string(state), state_string(cur_state), val);
935 /* Make sure the selected PLL is correctly attached to the transcoder */
936 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
939 pch_dpll = I915_READ(PCH_DPLL_SEL);
940 cur_state = pll->pll_reg == _PCH_DPLL_B;
941 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
942 "PLL[%d] not attached to this transcoder %d: %08x\n",
943 cur_state, crtc->pipe, pch_dpll)) {
944 cur_state = !!(val >> (4*crtc->pipe + 3));
945 WARN(cur_state != state,
946 "PLL[%d] not %s on this transcoder %d: %08x\n",
947 pll->pll_reg == _PCH_DPLL_B,
954 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
955 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
957 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
958 enum pipe pipe, bool state)
964 if (IS_HASWELL(dev_priv->dev)) {
965 /* On Haswell, DDI is used instead of FDI_TX_CTL */
966 reg = DDI_FUNC_CTL(pipe);
967 val = I915_READ(reg);
968 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
970 reg = FDI_TX_CTL(pipe);
971 val = I915_READ(reg);
972 cur_state = !!(val & FDI_TX_ENABLE);
974 WARN(cur_state != state,
975 "FDI TX state assertion failure (expected %s, current %s)\n",
976 state_string(state), state_string(cur_state));
978 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
979 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
981 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
982 enum pipe pipe, bool state)
988 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
989 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
992 reg = FDI_RX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_RX_ENABLE);
996 WARN(cur_state != state,
997 "FDI RX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
1000 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1001 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1003 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1009 /* ILK FDI PLL is always enabled */
1010 if (dev_priv->info->gen == 5)
1013 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1014 if (IS_HASWELL(dev_priv->dev))
1017 reg = FDI_TX_CTL(pipe);
1018 val = I915_READ(reg);
1019 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1022 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1028 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1029 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1032 reg = FDI_RX_CTL(pipe);
1033 val = I915_READ(reg);
1034 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1037 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1040 int pp_reg, lvds_reg;
1042 enum pipe panel_pipe = PIPE_A;
1045 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1046 pp_reg = PCH_PP_CONTROL;
1047 lvds_reg = PCH_LVDS;
1049 pp_reg = PP_CONTROL;
1053 val = I915_READ(pp_reg);
1054 if (!(val & PANEL_POWER_ON) ||
1055 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1058 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1059 panel_pipe = PIPE_B;
1061 WARN(panel_pipe == pipe && locked,
1062 "panel assertion failure, pipe %c regs locked\n",
1066 void assert_pipe(struct drm_i915_private *dev_priv,
1067 enum pipe pipe, bool state)
1073 /* if we need the pipe A quirk it must be always on */
1074 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1077 reg = PIPECONF(pipe);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 WARN(cur_state != state,
1081 "pipe %c assertion failure (expected %s, current %s)\n",
1082 pipe_name(pipe), state_string(state), state_string(cur_state));
1085 static void assert_plane(struct drm_i915_private *dev_priv,
1086 enum plane plane, bool state)
1092 reg = DSPCNTR(plane);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1095 WARN(cur_state != state,
1096 "plane %c assertion failure (expected %s, current %s)\n",
1097 plane_name(plane), state_string(state), state_string(cur_state));
1100 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1101 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1103 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1110 /* Planes are fixed to pipes on ILK+ */
1111 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1112 reg = DSPCNTR(pipe);
1113 val = I915_READ(reg);
1114 WARN((val & DISPLAY_PLANE_ENABLE),
1115 "plane %c assertion failure, should be disabled but not\n",
1120 /* Need to check both planes against the pipe */
1121 for (i = 0; i < 2; i++) {
1123 val = I915_READ(reg);
1124 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1125 DISPPLANE_SEL_PIPE_SHIFT;
1126 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1127 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1128 plane_name(i), pipe_name(pipe));
1132 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1137 if (HAS_PCH_LPT(dev_priv->dev)) {
1138 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1142 val = I915_READ(PCH_DREF_CONTROL);
1143 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1144 DREF_SUPERSPREAD_SOURCE_MASK));
1145 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1148 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1155 reg = TRANSCONF(pipe);
1156 val = I915_READ(reg);
1157 enabled = !!(val & TRANS_ENABLE);
1159 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1163 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, u32 port_sel, u32 val)
1166 if ((val & DP_PORT_EN) == 0)
1169 if (HAS_PCH_CPT(dev_priv->dev)) {
1170 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1171 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1172 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1175 if ((val & DP_PIPE_MASK) != (pipe << 30))
1181 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, u32 val)
1184 if ((val & PORT_ENABLE) == 0)
1187 if (HAS_PCH_CPT(dev_priv->dev)) {
1188 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1191 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1197 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1198 enum pipe pipe, u32 val)
1200 if ((val & LVDS_PORT_EN) == 0)
1203 if (HAS_PCH_CPT(dev_priv->dev)) {
1204 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1207 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1213 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, u32 val)
1216 if ((val & ADPA_DAC_ENABLE) == 0)
1218 if (HAS_PCH_CPT(dev_priv->dev)) {
1219 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1222 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1228 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe, int reg, u32 port_sel)
1231 u32 val = I915_READ(reg);
1232 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1233 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1234 reg, pipe_name(pipe));
1237 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, int reg)
1240 u32 val = I915_READ(reg);
1241 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1242 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1243 reg, pipe_name(pipe));
1246 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1252 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1253 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1254 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1257 val = I915_READ(reg);
1258 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1259 "PCH VGA enabled on transcoder %c, should be disabled\n",
1263 val = I915_READ(reg);
1264 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1265 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1268 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1269 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1270 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1274 * intel_enable_pll - enable a PLL
1275 * @dev_priv: i915 private structure
1276 * @pipe: pipe PLL to enable
1278 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1279 * make sure the PLL reg is writable first though, since the panel write
1280 * protect mechanism may be enabled.
1282 * Note! This is for pre-ILK only.
1284 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1289 /* No really, not for ILK+ */
1290 BUG_ON(dev_priv->info->gen >= 5);
1292 /* PLL is protected by panel, make sure we can write it */
1293 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1294 assert_panel_unlocked(dev_priv, pipe);
1297 val = I915_READ(reg);
1298 val |= DPLL_VCO_ENABLE;
1300 /* We do this three times for luck */
1301 I915_WRITE(reg, val);
1303 udelay(150); /* wait for warmup */
1304 I915_WRITE(reg, val);
1306 udelay(150); /* wait for warmup */
1307 I915_WRITE(reg, val);
1309 udelay(150); /* wait for warmup */
1313 * intel_disable_pll - disable a PLL
1314 * @dev_priv: i915 private structure
1315 * @pipe: pipe PLL to disable
1317 * Disable the PLL for @pipe, making sure the pipe is off first.
1319 * Note! This is for pre-ILK only.
1321 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1326 /* Don't disable pipe A or pipe A PLLs if needed */
1327 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1330 /* Make sure the pipe isn't still relying on us */
1331 assert_pipe_disabled(dev_priv, pipe);
1334 val = I915_READ(reg);
1335 val &= ~DPLL_VCO_ENABLE;
1336 I915_WRITE(reg, val);
1342 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1344 unsigned long flags;
1346 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1347 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1349 DRM_ERROR("timeout waiting for SBI to become ready\n");
1353 I915_WRITE(SBI_ADDR,
1355 I915_WRITE(SBI_DATA,
1357 I915_WRITE(SBI_CTL_STAT,
1361 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1363 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1368 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1372 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1374 unsigned long flags;
1377 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1378 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1380 DRM_ERROR("timeout waiting for SBI to become ready\n");
1384 I915_WRITE(SBI_ADDR,
1386 I915_WRITE(SBI_CTL_STAT,
1390 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1392 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1396 value = I915_READ(SBI_DATA);
1399 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1404 * intel_enable_pch_pll - enable PCH PLL
1405 * @dev_priv: i915 private structure
1406 * @pipe: pipe PLL to enable
1408 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1409 * drives the transcoder clock.
1411 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1413 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1414 struct intel_pch_pll *pll;
1418 /* PCH PLLs only available on ILK, SNB and IVB */
1419 BUG_ON(dev_priv->info->gen < 5);
1420 pll = intel_crtc->pch_pll;
1424 if (WARN_ON(pll->refcount == 0))
1427 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1428 pll->pll_reg, pll->active, pll->on,
1429 intel_crtc->base.base.id);
1431 /* PCH refclock must be enabled first */
1432 assert_pch_refclk_enabled(dev_priv);
1434 if (pll->active++ && pll->on) {
1435 assert_pch_pll_enabled(dev_priv, pll, NULL);
1439 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1442 val = I915_READ(reg);
1443 val |= DPLL_VCO_ENABLE;
1444 I915_WRITE(reg, val);
1451 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1453 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1454 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1458 /* PCH only available on ILK+ */
1459 BUG_ON(dev_priv->info->gen < 5);
1463 if (WARN_ON(pll->refcount == 0))
1466 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1467 pll->pll_reg, pll->active, pll->on,
1468 intel_crtc->base.base.id);
1470 if (WARN_ON(pll->active == 0)) {
1471 assert_pch_pll_disabled(dev_priv, pll, NULL);
1475 if (--pll->active) {
1476 assert_pch_pll_enabled(dev_priv, pll, NULL);
1480 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1482 /* Make sure transcoder isn't still depending on us */
1483 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1486 val = I915_READ(reg);
1487 val &= ~DPLL_VCO_ENABLE;
1488 I915_WRITE(reg, val);
1495 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1499 u32 val, pipeconf_val;
1500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1502 /* PCH only available on ILK+ */
1503 BUG_ON(dev_priv->info->gen < 5);
1505 /* Make sure PCH DPLL is enabled */
1506 assert_pch_pll_enabled(dev_priv,
1507 to_intel_crtc(crtc)->pch_pll,
1508 to_intel_crtc(crtc));
1510 /* FDI must be feeding us bits for PCH ports */
1511 assert_fdi_tx_enabled(dev_priv, pipe);
1512 assert_fdi_rx_enabled(dev_priv, pipe);
1514 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1515 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1518 reg = TRANSCONF(pipe);
1519 val = I915_READ(reg);
1520 pipeconf_val = I915_READ(PIPECONF(pipe));
1522 if (HAS_PCH_IBX(dev_priv->dev)) {
1524 * make the BPC in transcoder be consistent with
1525 * that in pipeconf reg.
1527 val &= ~PIPE_BPC_MASK;
1528 val |= pipeconf_val & PIPE_BPC_MASK;
1531 val &= ~TRANS_INTERLACE_MASK;
1532 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1533 if (HAS_PCH_IBX(dev_priv->dev) &&
1534 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1535 val |= TRANS_LEGACY_INTERLACED_ILK;
1537 val |= TRANS_INTERLACED;
1539 val |= TRANS_PROGRESSIVE;
1541 I915_WRITE(reg, val | TRANS_ENABLE);
1542 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1543 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1546 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1552 /* FDI relies on the transcoder */
1553 assert_fdi_tx_disabled(dev_priv, pipe);
1554 assert_fdi_rx_disabled(dev_priv, pipe);
1556 /* Ports must be off as well */
1557 assert_pch_ports_disabled(dev_priv, pipe);
1559 reg = TRANSCONF(pipe);
1560 val = I915_READ(reg);
1561 val &= ~TRANS_ENABLE;
1562 I915_WRITE(reg, val);
1563 /* wait for PCH transcoder off, transcoder state */
1564 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1565 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1569 * intel_enable_pipe - enable a pipe, asserting requirements
1570 * @dev_priv: i915 private structure
1571 * @pipe: pipe to enable
1572 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1574 * Enable @pipe, making sure that various hardware specific requirements
1575 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1577 * @pipe should be %PIPE_A or %PIPE_B.
1579 * Will wait until the pipe is actually running (i.e. first vblank) before
1582 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1589 * A pipe without a PLL won't actually be able to drive bits from
1590 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1593 if (!HAS_PCH_SPLIT(dev_priv->dev))
1594 assert_pll_enabled(dev_priv, pipe);
1597 /* if driving the PCH, we need FDI enabled */
1598 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1599 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1601 /* FIXME: assert CPU port conditions for SNB+ */
1604 reg = PIPECONF(pipe);
1605 val = I915_READ(reg);
1606 if (val & PIPECONF_ENABLE)
1609 I915_WRITE(reg, val | PIPECONF_ENABLE);
1610 intel_wait_for_vblank(dev_priv->dev, pipe);
1614 * intel_disable_pipe - disable a pipe, asserting requirements
1615 * @dev_priv: i915 private structure
1616 * @pipe: pipe to disable
1618 * Disable @pipe, making sure that various hardware specific requirements
1619 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1621 * @pipe should be %PIPE_A or %PIPE_B.
1623 * Will wait until the pipe has shut down before returning.
1625 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1632 * Make sure planes won't keep trying to pump pixels to us,
1633 * or we might hang the display.
1635 assert_planes_disabled(dev_priv, pipe);
1637 /* Don't disable pipe A or pipe A PLLs if needed */
1638 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1641 reg = PIPECONF(pipe);
1642 val = I915_READ(reg);
1643 if ((val & PIPECONF_ENABLE) == 0)
1646 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1647 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1651 * Plane regs are double buffered, going from enabled->disabled needs a
1652 * trigger in order to latch. The display address reg provides this.
1654 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1657 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1658 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1662 * intel_enable_plane - enable a display plane on a given pipe
1663 * @dev_priv: i915 private structure
1664 * @plane: plane to enable
1665 * @pipe: pipe being fed
1667 * Enable @plane on @pipe, making sure that @pipe is running first.
1669 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1670 enum plane plane, enum pipe pipe)
1675 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1676 assert_pipe_enabled(dev_priv, pipe);
1678 reg = DSPCNTR(plane);
1679 val = I915_READ(reg);
1680 if (val & DISPLAY_PLANE_ENABLE)
1683 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1684 intel_flush_display_plane(dev_priv, plane);
1685 intel_wait_for_vblank(dev_priv->dev, pipe);
1689 * intel_disable_plane - disable a display plane
1690 * @dev_priv: i915 private structure
1691 * @plane: plane to disable
1692 * @pipe: pipe consuming the data
1694 * Disable @plane; should be an independent operation.
1696 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1697 enum plane plane, enum pipe pipe)
1702 reg = DSPCNTR(plane);
1703 val = I915_READ(reg);
1704 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1707 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1708 intel_flush_display_plane(dev_priv, plane);
1709 intel_wait_for_vblank(dev_priv->dev, pipe);
1712 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1713 enum pipe pipe, int reg, u32 port_sel)
1715 u32 val = I915_READ(reg);
1716 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1717 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1718 I915_WRITE(reg, val & ~DP_PORT_EN);
1722 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1723 enum pipe pipe, int reg)
1725 u32 val = I915_READ(reg);
1726 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1727 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1729 I915_WRITE(reg, val & ~PORT_ENABLE);
1733 /* Disable any ports connected to this transcoder */
1734 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1739 val = I915_READ(PCH_PP_CONTROL);
1740 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1742 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1743 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1744 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1747 val = I915_READ(reg);
1748 if (adpa_pipe_enabled(dev_priv, val, pipe))
1749 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1752 val = I915_READ(reg);
1753 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1754 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1755 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1760 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1761 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1762 disable_pch_hdmi(dev_priv, pipe, HDMID);
1766 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1767 struct drm_i915_gem_object *obj,
1768 struct intel_ring_buffer *pipelined)
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1774 switch (obj->tiling_mode) {
1775 case I915_TILING_NONE:
1776 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1777 alignment = 128 * 1024;
1778 else if (INTEL_INFO(dev)->gen >= 4)
1779 alignment = 4 * 1024;
1781 alignment = 64 * 1024;
1784 /* pin() will align the object as required by fence */
1788 /* FIXME: Is this true? */
1789 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1795 dev_priv->mm.interruptible = false;
1796 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1798 goto err_interruptible;
1800 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1801 * fence, whereas 965+ only requires a fence if using
1802 * framebuffer compression. For simplicity, we always install
1803 * a fence as the cost is not that onerous.
1805 ret = i915_gem_object_get_fence(obj);
1809 i915_gem_object_pin_fence(obj);
1811 dev_priv->mm.interruptible = true;
1815 i915_gem_object_unpin(obj);
1817 dev_priv->mm.interruptible = true;
1821 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1823 i915_gem_object_unpin_fence(obj);
1824 i915_gem_object_unpin(obj);
1827 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1830 struct drm_device *dev = crtc->dev;
1831 struct drm_i915_private *dev_priv = dev->dev_private;
1832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1833 struct intel_framebuffer *intel_fb;
1834 struct drm_i915_gem_object *obj;
1835 int plane = intel_crtc->plane;
1836 unsigned long Start, Offset;
1845 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1849 intel_fb = to_intel_framebuffer(fb);
1850 obj = intel_fb->obj;
1852 reg = DSPCNTR(plane);
1853 dspcntr = I915_READ(reg);
1854 /* Mask out pixel format bits in case we change it */
1855 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1856 switch (fb->bits_per_pixel) {
1858 dspcntr |= DISPPLANE_8BPP;
1861 if (fb->depth == 15)
1862 dspcntr |= DISPPLANE_15_16BPP;
1864 dspcntr |= DISPPLANE_16BPP;
1868 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1871 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1874 if (INTEL_INFO(dev)->gen >= 4) {
1875 if (obj->tiling_mode != I915_TILING_NONE)
1876 dspcntr |= DISPPLANE_TILED;
1878 dspcntr &= ~DISPPLANE_TILED;
1881 I915_WRITE(reg, dspcntr);
1883 Start = obj->gtt_offset;
1884 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1886 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1887 Start, Offset, x, y, fb->pitches[0]);
1888 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1889 if (INTEL_INFO(dev)->gen >= 4) {
1890 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1891 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1892 I915_WRITE(DSPADDR(plane), Offset);
1894 I915_WRITE(DSPADDR(plane), Start + Offset);
1900 static int ironlake_update_plane(struct drm_crtc *crtc,
1901 struct drm_framebuffer *fb, int x, int y)
1903 struct drm_device *dev = crtc->dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1906 struct intel_framebuffer *intel_fb;
1907 struct drm_i915_gem_object *obj;
1908 int plane = intel_crtc->plane;
1909 unsigned long Start, Offset;
1919 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1923 intel_fb = to_intel_framebuffer(fb);
1924 obj = intel_fb->obj;
1926 reg = DSPCNTR(plane);
1927 dspcntr = I915_READ(reg);
1928 /* Mask out pixel format bits in case we change it */
1929 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1930 switch (fb->bits_per_pixel) {
1932 dspcntr |= DISPPLANE_8BPP;
1935 if (fb->depth != 16)
1938 dspcntr |= DISPPLANE_16BPP;
1942 if (fb->depth == 24)
1943 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1944 else if (fb->depth == 30)
1945 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1950 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1954 if (obj->tiling_mode != I915_TILING_NONE)
1955 dspcntr |= DISPPLANE_TILED;
1957 dspcntr &= ~DISPPLANE_TILED;
1960 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1962 I915_WRITE(reg, dspcntr);
1964 Start = obj->gtt_offset;
1965 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1967 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1968 Start, Offset, x, y, fb->pitches[0]);
1969 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1970 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1971 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1972 I915_WRITE(DSPADDR(plane), Offset);
1978 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1980 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1981 int x, int y, enum mode_set_atomic state)
1983 struct drm_device *dev = crtc->dev;
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1986 if (dev_priv->display.disable_fbc)
1987 dev_priv->display.disable_fbc(dev);
1988 intel_increase_pllclock(crtc);
1990 return dev_priv->display.update_plane(crtc, fb, x, y);
1994 intel_finish_fb(struct drm_framebuffer *old_fb)
1996 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1997 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1998 bool was_interruptible = dev_priv->mm.interruptible;
2001 wait_event(dev_priv->pending_flip_queue,
2002 atomic_read(&dev_priv->mm.wedged) ||
2003 atomic_read(&obj->pending_flip) == 0);
2005 /* Big Hammer, we also need to ensure that any pending
2006 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2007 * current scanout is retired before unpinning the old
2010 * This should only fail upon a hung GPU, in which case we
2011 * can safely continue.
2013 dev_priv->mm.interruptible = false;
2014 ret = i915_gem_object_finish_gpu(obj);
2015 dev_priv->mm.interruptible = was_interruptible;
2021 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2022 struct drm_framebuffer *old_fb)
2024 struct drm_device *dev = crtc->dev;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 struct drm_i915_master_private *master_priv;
2027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 DRM_ERROR("No FB bound\n");
2036 if(intel_crtc->plane > dev_priv->num_pipe) {
2037 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2039 dev_priv->num_pipe);
2043 mutex_lock(&dev->struct_mutex);
2044 ret = intel_pin_and_fence_fb_obj(dev,
2045 to_intel_framebuffer(crtc->fb)->obj,
2048 mutex_unlock(&dev->struct_mutex);
2049 DRM_ERROR("pin & fence failed\n");
2054 intel_finish_fb(old_fb);
2056 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2058 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2059 mutex_unlock(&dev->struct_mutex);
2060 DRM_ERROR("failed to update base address\n");
2065 intel_wait_for_vblank(dev, intel_crtc->pipe);
2066 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2069 intel_update_fbc(dev);
2070 mutex_unlock(&dev->struct_mutex);
2072 if (!dev->primary->master)
2075 master_priv = dev->primary->master->driver_priv;
2076 if (!master_priv->sarea_priv)
2079 if (intel_crtc->pipe) {
2080 master_priv->sarea_priv->pipeB_x = x;
2081 master_priv->sarea_priv->pipeB_y = y;
2083 master_priv->sarea_priv->pipeA_x = x;
2084 master_priv->sarea_priv->pipeA_y = y;
2090 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2096 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2097 dpa_ctl = I915_READ(DP_A);
2098 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2100 if (clock < 200000) {
2102 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2103 /* workaround for 160Mhz:
2104 1) program 0x4600c bits 15:0 = 0x8124
2105 2) program 0x46010 bit 0 = 1
2106 3) program 0x46034 bit 24 = 1
2107 4) program 0x64000 bit 14 = 1
2109 temp = I915_READ(0x4600c);
2111 I915_WRITE(0x4600c, temp | 0x8124);
2113 temp = I915_READ(0x46010);
2114 I915_WRITE(0x46010, temp | 1);
2116 temp = I915_READ(0x46034);
2117 I915_WRITE(0x46034, temp | (1 << 24));
2119 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2121 I915_WRITE(DP_A, dpa_ctl);
2127 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2129 struct drm_device *dev = crtc->dev;
2130 struct drm_i915_private *dev_priv = dev->dev_private;
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132 int pipe = intel_crtc->pipe;
2135 /* enable normal train */
2136 reg = FDI_TX_CTL(pipe);
2137 temp = I915_READ(reg);
2138 if (IS_IVYBRIDGE(dev)) {
2139 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2140 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2142 temp &= ~FDI_LINK_TRAIN_NONE;
2143 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2145 I915_WRITE(reg, temp);
2147 reg = FDI_RX_CTL(pipe);
2148 temp = I915_READ(reg);
2149 if (HAS_PCH_CPT(dev)) {
2150 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2151 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2153 temp &= ~FDI_LINK_TRAIN_NONE;
2154 temp |= FDI_LINK_TRAIN_NONE;
2156 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2158 /* wait one idle pattern time */
2162 /* IVB wants error correction enabled */
2163 if (IS_IVYBRIDGE(dev))
2164 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2165 FDI_FE_ERRC_ENABLE);
2168 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 u32 flags = I915_READ(SOUTH_CHICKEN1);
2173 flags |= FDI_PHASE_SYNC_OVR(pipe);
2174 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2175 flags |= FDI_PHASE_SYNC_EN(pipe);
2176 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2177 POSTING_READ(SOUTH_CHICKEN1);
2180 /* The FDI link training functions for ILK/Ibexpeak. */
2181 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2183 struct drm_device *dev = crtc->dev;
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2186 int pipe = intel_crtc->pipe;
2187 int plane = intel_crtc->plane;
2188 u32 reg, temp, tries;
2190 /* FDI needs bits from pipe & plane first */
2191 assert_pipe_enabled(dev_priv, pipe);
2192 assert_plane_enabled(dev_priv, plane);
2194 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2196 reg = FDI_RX_IMR(pipe);
2197 temp = I915_READ(reg);
2198 temp &= ~FDI_RX_SYMBOL_LOCK;
2199 temp &= ~FDI_RX_BIT_LOCK;
2200 I915_WRITE(reg, temp);
2204 /* enable CPU FDI TX and PCH FDI RX */
2205 reg = FDI_TX_CTL(pipe);
2206 temp = I915_READ(reg);
2208 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2209 temp &= ~FDI_LINK_TRAIN_NONE;
2210 temp |= FDI_LINK_TRAIN_PATTERN_1;
2211 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2213 reg = FDI_RX_CTL(pipe);
2214 temp = I915_READ(reg);
2215 temp &= ~FDI_LINK_TRAIN_NONE;
2216 temp |= FDI_LINK_TRAIN_PATTERN_1;
2217 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2222 /* Ironlake workaround, enable clock pointer after FDI enable*/
2223 if (HAS_PCH_IBX(dev)) {
2224 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2225 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2226 FDI_RX_PHASE_SYNC_POINTER_EN);
2229 reg = FDI_RX_IIR(pipe);
2230 for (tries = 0; tries < 5; tries++) {
2231 temp = I915_READ(reg);
2232 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2234 if ((temp & FDI_RX_BIT_LOCK)) {
2235 DRM_DEBUG_KMS("FDI train 1 done.\n");
2236 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2241 DRM_ERROR("FDI train 1 fail!\n");
2244 reg = FDI_TX_CTL(pipe);
2245 temp = I915_READ(reg);
2246 temp &= ~FDI_LINK_TRAIN_NONE;
2247 temp |= FDI_LINK_TRAIN_PATTERN_2;
2248 I915_WRITE(reg, temp);
2250 reg = FDI_RX_CTL(pipe);
2251 temp = I915_READ(reg);
2252 temp &= ~FDI_LINK_TRAIN_NONE;
2253 temp |= FDI_LINK_TRAIN_PATTERN_2;
2254 I915_WRITE(reg, temp);
2259 reg = FDI_RX_IIR(pipe);
2260 for (tries = 0; tries < 5; tries++) {
2261 temp = I915_READ(reg);
2262 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2264 if (temp & FDI_RX_SYMBOL_LOCK) {
2265 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2266 DRM_DEBUG_KMS("FDI train 2 done.\n");
2271 DRM_ERROR("FDI train 2 fail!\n");
2273 DRM_DEBUG_KMS("FDI train done\n");
2277 static const int snb_b_fdi_train_param[] = {
2278 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2279 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2280 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2281 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2284 /* The FDI link training functions for SNB/Cougarpoint. */
2285 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2287 struct drm_device *dev = crtc->dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290 int pipe = intel_crtc->pipe;
2291 u32 reg, temp, i, retry;
2293 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2295 reg = FDI_RX_IMR(pipe);
2296 temp = I915_READ(reg);
2297 temp &= ~FDI_RX_SYMBOL_LOCK;
2298 temp &= ~FDI_RX_BIT_LOCK;
2299 I915_WRITE(reg, temp);
2304 /* enable CPU FDI TX and PCH FDI RX */
2305 reg = FDI_TX_CTL(pipe);
2306 temp = I915_READ(reg);
2308 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2309 temp &= ~FDI_LINK_TRAIN_NONE;
2310 temp |= FDI_LINK_TRAIN_PATTERN_1;
2311 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2313 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2314 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2316 reg = FDI_RX_CTL(pipe);
2317 temp = I915_READ(reg);
2318 if (HAS_PCH_CPT(dev)) {
2319 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2320 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2322 temp &= ~FDI_LINK_TRAIN_NONE;
2323 temp |= FDI_LINK_TRAIN_PATTERN_1;
2325 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2330 if (HAS_PCH_CPT(dev))
2331 cpt_phase_pointer_enable(dev, pipe);
2333 for (i = 0; i < 4; i++) {
2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
2336 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337 temp |= snb_b_fdi_train_param[i];
2338 I915_WRITE(reg, temp);
2343 for (retry = 0; retry < 5; retry++) {
2344 reg = FDI_RX_IIR(pipe);
2345 temp = I915_READ(reg);
2346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2347 if (temp & FDI_RX_BIT_LOCK) {
2348 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2349 DRM_DEBUG_KMS("FDI train 1 done.\n");
2358 DRM_ERROR("FDI train 1 fail!\n");
2361 reg = FDI_TX_CTL(pipe);
2362 temp = I915_READ(reg);
2363 temp &= ~FDI_LINK_TRAIN_NONE;
2364 temp |= FDI_LINK_TRAIN_PATTERN_2;
2366 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2368 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2370 I915_WRITE(reg, temp);
2372 reg = FDI_RX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 if (HAS_PCH_CPT(dev)) {
2375 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2376 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2378 temp &= ~FDI_LINK_TRAIN_NONE;
2379 temp |= FDI_LINK_TRAIN_PATTERN_2;
2381 I915_WRITE(reg, temp);
2386 for (i = 0; i < 4; i++) {
2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2390 temp |= snb_b_fdi_train_param[i];
2391 I915_WRITE(reg, temp);
2396 for (retry = 0; retry < 5; retry++) {
2397 reg = FDI_RX_IIR(pipe);
2398 temp = I915_READ(reg);
2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400 if (temp & FDI_RX_SYMBOL_LOCK) {
2401 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2411 DRM_ERROR("FDI train 2 fail!\n");
2413 DRM_DEBUG_KMS("FDI train done.\n");
2416 /* Manual link training for Ivy Bridge A0 parts */
2417 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2419 struct drm_device *dev = crtc->dev;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422 int pipe = intel_crtc->pipe;
2425 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2427 reg = FDI_RX_IMR(pipe);
2428 temp = I915_READ(reg);
2429 temp &= ~FDI_RX_SYMBOL_LOCK;
2430 temp &= ~FDI_RX_BIT_LOCK;
2431 I915_WRITE(reg, temp);
2436 /* enable CPU FDI TX and PCH FDI RX */
2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
2440 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2441 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2442 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2443 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2444 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2445 temp |= FDI_COMPOSITE_SYNC;
2446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2448 reg = FDI_RX_CTL(pipe);
2449 temp = I915_READ(reg);
2450 temp &= ~FDI_LINK_TRAIN_AUTO;
2451 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2452 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2453 temp |= FDI_COMPOSITE_SYNC;
2454 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2459 if (HAS_PCH_CPT(dev))
2460 cpt_phase_pointer_enable(dev, pipe);
2462 for (i = 0; i < 4; i++) {
2463 reg = FDI_TX_CTL(pipe);
2464 temp = I915_READ(reg);
2465 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2466 temp |= snb_b_fdi_train_param[i];
2467 I915_WRITE(reg, temp);
2472 reg = FDI_RX_IIR(pipe);
2473 temp = I915_READ(reg);
2474 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476 if (temp & FDI_RX_BIT_LOCK ||
2477 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2478 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2479 DRM_DEBUG_KMS("FDI train 1 done.\n");
2484 DRM_ERROR("FDI train 1 fail!\n");
2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2490 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2493 I915_WRITE(reg, temp);
2495 reg = FDI_RX_CTL(pipe);
2496 temp = I915_READ(reg);
2497 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2498 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2499 I915_WRITE(reg, temp);
2504 for (i = 0; i < 4; i++) {
2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
2507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508 temp |= snb_b_fdi_train_param[i];
2509 I915_WRITE(reg, temp);
2514 reg = FDI_RX_IIR(pipe);
2515 temp = I915_READ(reg);
2516 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2518 if (temp & FDI_RX_SYMBOL_LOCK) {
2519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2520 DRM_DEBUG_KMS("FDI train 2 done.\n");
2525 DRM_ERROR("FDI train 2 fail!\n");
2527 DRM_DEBUG_KMS("FDI train done.\n");
2530 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2532 struct drm_device *dev = crtc->dev;
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2535 int pipe = intel_crtc->pipe;
2538 /* Write the TU size bits so error detection works */
2539 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2540 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2542 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2543 reg = FDI_RX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~((0x7 << 19) | (0x7 << 16));
2546 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2547 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2548 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2553 /* Switch from Rawclk to PCDclk */
2554 temp = I915_READ(reg);
2555 I915_WRITE(reg, temp | FDI_PCDCLK);
2560 /* On Haswell, the PLL configuration for ports and pipes is handled
2561 * separately, as part of DDI setup */
2562 if (!IS_HASWELL(dev)) {
2563 /* Enable CPU FDI TX PLL, always on for Ironlake */
2564 reg = FDI_TX_CTL(pipe);
2565 temp = I915_READ(reg);
2566 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2567 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2575 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 u32 flags = I915_READ(SOUTH_CHICKEN1);
2580 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2581 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2582 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2583 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2584 POSTING_READ(SOUTH_CHICKEN1);
2586 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2588 struct drm_device *dev = crtc->dev;
2589 struct drm_i915_private *dev_priv = dev->dev_private;
2590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2591 int pipe = intel_crtc->pipe;
2594 /* disable CPU FDI tx and PCH FDI rx */
2595 reg = FDI_TX_CTL(pipe);
2596 temp = I915_READ(reg);
2597 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2600 reg = FDI_RX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~(0x7 << 16);
2603 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2604 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2609 /* Ironlake workaround, disable clock pointer after downing FDI */
2610 if (HAS_PCH_IBX(dev)) {
2611 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2612 I915_WRITE(FDI_RX_CHICKEN(pipe),
2613 I915_READ(FDI_RX_CHICKEN(pipe) &
2614 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2615 } else if (HAS_PCH_CPT(dev)) {
2616 cpt_phase_pointer_disable(dev, pipe);
2619 /* still set train pattern 1 */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~FDI_LINK_TRAIN_NONE;
2623 temp |= FDI_LINK_TRAIN_PATTERN_1;
2624 I915_WRITE(reg, temp);
2626 reg = FDI_RX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 if (HAS_PCH_CPT(dev)) {
2629 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2630 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2632 temp &= ~FDI_LINK_TRAIN_NONE;
2633 temp |= FDI_LINK_TRAIN_PATTERN_1;
2635 /* BPC in FDI rx is consistent with that in PIPECONF */
2636 temp &= ~(0x07 << 16);
2637 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2638 I915_WRITE(reg, temp);
2644 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2646 struct drm_device *dev = crtc->dev;
2648 if (crtc->fb == NULL)
2651 mutex_lock(&dev->struct_mutex);
2652 intel_finish_fb(crtc->fb);
2653 mutex_unlock(&dev->struct_mutex);
2656 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2658 struct drm_device *dev = crtc->dev;
2659 struct drm_mode_config *mode_config = &dev->mode_config;
2660 struct intel_encoder *encoder;
2663 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2664 * must be driven by its own crtc; no sharing is possible.
2666 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2667 if (encoder->base.crtc != crtc)
2670 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2671 * CPU handles all others */
2672 if (IS_HASWELL(dev)) {
2673 /* It is still unclear how this will work on PPT, so throw up a warning */
2674 WARN_ON(!HAS_PCH_LPT(dev));
2676 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2677 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2680 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2686 switch (encoder->type) {
2687 case INTEL_OUTPUT_EDP:
2688 if (!intel_encoder_is_pch_edp(&encoder->base))
2697 /* Program iCLKIP clock to the desired frequency */
2698 static void lpt_program_iclkip(struct drm_crtc *crtc)
2700 struct drm_device *dev = crtc->dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2705 /* It is necessary to ungate the pixclk gate prior to programming
2706 * the divisors, and gate it back when it is done.
2708 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2710 /* Disable SSCCTL */
2711 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2712 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2713 SBI_SSCCTL_DISABLE);
2715 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2716 if (crtc->mode.clock == 20000) {
2721 /* The iCLK virtual clock root frequency is in MHz,
2722 * but the crtc->mode.clock in in KHz. To get the divisors,
2723 * it is necessary to divide one by another, so we
2724 * convert the virtual clock precision to KHz here for higher
2727 u32 iclk_virtual_root_freq = 172800 * 1000;
2728 u32 iclk_pi_range = 64;
2729 u32 desired_divisor, msb_divisor_value, pi_value;
2731 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2732 msb_divisor_value = desired_divisor / iclk_pi_range;
2733 pi_value = desired_divisor % iclk_pi_range;
2736 divsel = msb_divisor_value - 2;
2737 phaseinc = pi_value;
2740 /* This should not happen with any sane values */
2741 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2742 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2743 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2744 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2746 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2753 /* Program SSCDIVINTPHASE6 */
2754 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2755 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2756 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2757 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2758 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2759 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2760 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2762 intel_sbi_write(dev_priv,
2763 SBI_SSCDIVINTPHASE6,
2766 /* Program SSCAUXDIV */
2767 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2768 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2769 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2770 intel_sbi_write(dev_priv,
2775 /* Enable modulator and associated divider */
2776 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2777 temp &= ~SBI_SSCCTL_DISABLE;
2778 intel_sbi_write(dev_priv,
2782 /* Wait for initialization time */
2785 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2789 * Enable PCH resources required for PCH ports:
2791 * - FDI training & RX/TX
2792 * - update transcoder timings
2793 * - DP transcoding bits
2796 static void ironlake_pch_enable(struct drm_crtc *crtc)
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2804 assert_transcoder_disabled(dev_priv, pipe);
2806 /* For PCH output, training FDI link */
2807 dev_priv->display.fdi_link_train(crtc);
2809 intel_enable_pch_pll(intel_crtc);
2811 if (HAS_PCH_LPT(dev)) {
2812 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2813 lpt_program_iclkip(crtc);
2814 } else if (HAS_PCH_CPT(dev)) {
2817 temp = I915_READ(PCH_DPLL_SEL);
2821 temp |= TRANSA_DPLL_ENABLE;
2822 sel = TRANSA_DPLLB_SEL;
2825 temp |= TRANSB_DPLL_ENABLE;
2826 sel = TRANSB_DPLLB_SEL;
2829 temp |= TRANSC_DPLL_ENABLE;
2830 sel = TRANSC_DPLLB_SEL;
2833 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2837 I915_WRITE(PCH_DPLL_SEL, temp);
2840 /* set transcoder timing, panel must allow it */
2841 assert_panel_unlocked(dev_priv, pipe);
2842 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2843 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2844 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2846 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2847 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2848 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2849 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2851 if (!IS_HASWELL(dev))
2852 intel_fdi_normal_train(crtc);
2854 /* For PCH DP, enable TRANS_DP_CTL */
2855 if (HAS_PCH_CPT(dev) &&
2856 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2857 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2858 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2859 reg = TRANS_DP_CTL(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2862 TRANS_DP_SYNC_MASK |
2864 temp |= (TRANS_DP_OUTPUT_ENABLE |
2865 TRANS_DP_ENH_FRAMING);
2866 temp |= bpc << 9; /* same format but at 11:9 */
2868 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2869 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2870 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2871 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2873 switch (intel_trans_dp_port_sel(crtc)) {
2875 temp |= TRANS_DP_PORT_SEL_B;
2878 temp |= TRANS_DP_PORT_SEL_C;
2881 temp |= TRANS_DP_PORT_SEL_D;
2884 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2885 temp |= TRANS_DP_PORT_SEL_B;
2889 I915_WRITE(reg, temp);
2892 intel_enable_transcoder(dev_priv, pipe);
2895 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2897 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2902 if (pll->refcount == 0) {
2903 WARN(1, "bad PCH PLL refcount\n");
2908 intel_crtc->pch_pll = NULL;
2911 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2913 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2914 struct intel_pch_pll *pll;
2917 pll = intel_crtc->pch_pll;
2919 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2920 intel_crtc->base.base.id, pll->pll_reg);
2924 if (HAS_PCH_IBX(dev_priv->dev)) {
2925 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
2926 i = intel_crtc->pipe;
2927 pll = &dev_priv->pch_plls[i];
2929 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
2930 intel_crtc->base.base.id, pll->pll_reg);
2935 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2936 pll = &dev_priv->pch_plls[i];
2938 /* Only want to check enabled timings first */
2939 if (pll->refcount == 0)
2942 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2943 fp == I915_READ(pll->fp0_reg)) {
2944 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2945 intel_crtc->base.base.id,
2946 pll->pll_reg, pll->refcount, pll->active);
2952 /* Ok no matching timings, maybe there's a free one? */
2953 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2954 pll = &dev_priv->pch_plls[i];
2955 if (pll->refcount == 0) {
2956 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2957 intel_crtc->base.base.id, pll->pll_reg);
2965 intel_crtc->pch_pll = pll;
2967 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2968 prepare: /* separate function? */
2969 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2971 /* Wait for the clocks to stabilize before rewriting the regs */
2972 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2973 POSTING_READ(pll->pll_reg);
2976 I915_WRITE(pll->fp0_reg, fp);
2977 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2982 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2988 temp = I915_READ(dslreg);
2990 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2991 /* Without this, mode sets may fail silently on FDI */
2992 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2994 I915_WRITE(tc2reg, 0);
2995 if (wait_for(I915_READ(dslreg) != temp, 5))
2996 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3000 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3002 struct drm_device *dev = crtc->dev;
3003 struct drm_i915_private *dev_priv = dev->dev_private;
3004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3005 int pipe = intel_crtc->pipe;
3006 int plane = intel_crtc->plane;
3010 if (intel_crtc->active)
3013 intel_crtc->active = true;
3014 intel_update_watermarks(dev);
3016 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3017 temp = I915_READ(PCH_LVDS);
3018 if ((temp & LVDS_PORT_EN) == 0)
3019 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3022 is_pch_port = intel_crtc_driving_pch(crtc);
3025 ironlake_fdi_pll_enable(crtc);
3027 ironlake_fdi_disable(crtc);
3029 /* Enable panel fitting for LVDS */
3030 if (dev_priv->pch_pf_size &&
3031 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3032 /* Force use of hard-coded filter coefficients
3033 * as some pre-programmed values are broken,
3036 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3037 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3038 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3042 * On ILK+ LUT must be loaded before the pipe is running but with
3045 intel_crtc_load_lut(crtc);
3047 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3048 intel_enable_plane(dev_priv, plane, pipe);
3051 ironlake_pch_enable(crtc);
3053 mutex_lock(&dev->struct_mutex);
3054 intel_update_fbc(dev);
3055 mutex_unlock(&dev->struct_mutex);
3057 intel_crtc_update_cursor(crtc, true);
3060 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3062 struct drm_device *dev = crtc->dev;
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3065 int pipe = intel_crtc->pipe;
3066 int plane = intel_crtc->plane;
3069 if (!intel_crtc->active)
3072 intel_crtc_wait_for_pending_flips(crtc);
3073 drm_vblank_off(dev, pipe);
3074 intel_crtc_update_cursor(crtc, false);
3076 intel_disable_plane(dev_priv, plane, pipe);
3078 if (dev_priv->cfb_plane == plane)
3079 intel_disable_fbc(dev);
3081 intel_disable_pipe(dev_priv, pipe);
3084 I915_WRITE(PF_CTL(pipe), 0);
3085 I915_WRITE(PF_WIN_SZ(pipe), 0);
3087 ironlake_fdi_disable(crtc);
3089 /* This is a horrible layering violation; we should be doing this in
3090 * the connector/encoder ->prepare instead, but we don't always have
3091 * enough information there about the config to know whether it will
3092 * actually be necessary or just cause undesired flicker.
3094 intel_disable_pch_ports(dev_priv, pipe);
3096 intel_disable_transcoder(dev_priv, pipe);
3098 if (HAS_PCH_CPT(dev)) {
3099 /* disable TRANS_DP_CTL */
3100 reg = TRANS_DP_CTL(pipe);
3101 temp = I915_READ(reg);
3102 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3103 temp |= TRANS_DP_PORT_SEL_NONE;
3104 I915_WRITE(reg, temp);
3106 /* disable DPLL_SEL */
3107 temp = I915_READ(PCH_DPLL_SEL);
3110 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3113 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3116 /* C shares PLL A or B */
3117 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3122 I915_WRITE(PCH_DPLL_SEL, temp);
3125 /* disable PCH DPLL */
3126 intel_disable_pch_pll(intel_crtc);
3128 /* Switch from PCDclk to Rawclk */
3129 reg = FDI_RX_CTL(pipe);
3130 temp = I915_READ(reg);
3131 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3133 /* Disable CPU FDI TX PLL */
3134 reg = FDI_TX_CTL(pipe);
3135 temp = I915_READ(reg);
3136 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3141 reg = FDI_RX_CTL(pipe);
3142 temp = I915_READ(reg);
3143 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3145 /* Wait for the clocks to turn off. */
3149 intel_crtc->active = false;
3150 intel_update_watermarks(dev);
3152 mutex_lock(&dev->struct_mutex);
3153 intel_update_fbc(dev);
3154 mutex_unlock(&dev->struct_mutex);
3157 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3160 int pipe = intel_crtc->pipe;
3161 int plane = intel_crtc->plane;
3163 /* XXX: When our outputs are all unaware of DPMS modes other than off
3164 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3167 case DRM_MODE_DPMS_ON:
3168 case DRM_MODE_DPMS_STANDBY:
3169 case DRM_MODE_DPMS_SUSPEND:
3170 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3171 ironlake_crtc_enable(crtc);
3174 case DRM_MODE_DPMS_OFF:
3175 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3176 ironlake_crtc_disable(crtc);
3181 static void ironlake_crtc_off(struct drm_crtc *crtc)
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184 intel_put_pch_pll(intel_crtc);
3187 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3189 if (!enable && intel_crtc->overlay) {
3190 struct drm_device *dev = intel_crtc->base.dev;
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3193 mutex_lock(&dev->struct_mutex);
3194 dev_priv->mm.interruptible = false;
3195 (void) intel_overlay_switch_off(intel_crtc->overlay);
3196 dev_priv->mm.interruptible = true;
3197 mutex_unlock(&dev->struct_mutex);
3200 /* Let userspace switch the overlay on again. In most cases userspace
3201 * has to recompute where to put it anyway.
3205 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3207 struct drm_device *dev = crtc->dev;
3208 struct drm_i915_private *dev_priv = dev->dev_private;
3209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3210 int pipe = intel_crtc->pipe;
3211 int plane = intel_crtc->plane;
3213 if (intel_crtc->active)
3216 intel_crtc->active = true;
3217 intel_update_watermarks(dev);
3219 intel_enable_pll(dev_priv, pipe);
3220 intel_enable_pipe(dev_priv, pipe, false);
3221 intel_enable_plane(dev_priv, plane, pipe);
3223 intel_crtc_load_lut(crtc);
3224 intel_update_fbc(dev);
3226 /* Give the overlay scaler a chance to enable if it's on this pipe */
3227 intel_crtc_dpms_overlay(intel_crtc, true);
3228 intel_crtc_update_cursor(crtc, true);
3231 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3233 struct drm_device *dev = crtc->dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3236 int pipe = intel_crtc->pipe;
3237 int plane = intel_crtc->plane;
3239 if (!intel_crtc->active)
3242 /* Give the overlay scaler a chance to disable if it's on this pipe */
3243 intel_crtc_wait_for_pending_flips(crtc);
3244 drm_vblank_off(dev, pipe);
3245 intel_crtc_dpms_overlay(intel_crtc, false);
3246 intel_crtc_update_cursor(crtc, false);
3248 if (dev_priv->cfb_plane == plane)
3249 intel_disable_fbc(dev);
3251 intel_disable_plane(dev_priv, plane, pipe);
3252 intel_disable_pipe(dev_priv, pipe);
3253 intel_disable_pll(dev_priv, pipe);
3255 intel_crtc->active = false;
3256 intel_update_fbc(dev);
3257 intel_update_watermarks(dev);
3260 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3262 /* XXX: When our outputs are all unaware of DPMS modes other than off
3263 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3266 case DRM_MODE_DPMS_ON:
3267 case DRM_MODE_DPMS_STANDBY:
3268 case DRM_MODE_DPMS_SUSPEND:
3269 i9xx_crtc_enable(crtc);
3271 case DRM_MODE_DPMS_OFF:
3272 i9xx_crtc_disable(crtc);
3277 static void i9xx_crtc_off(struct drm_crtc *crtc)
3282 * Sets the power management mode of the pipe and plane.
3284 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct drm_i915_master_private *master_priv;
3289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290 int pipe = intel_crtc->pipe;
3293 if (intel_crtc->dpms_mode == mode)
3296 intel_crtc->dpms_mode = mode;
3298 dev_priv->display.dpms(crtc, mode);
3300 if (!dev->primary->master)
3303 master_priv = dev->primary->master->driver_priv;
3304 if (!master_priv->sarea_priv)
3307 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3311 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3312 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3315 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3316 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3319 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3324 static void intel_crtc_disable(struct drm_crtc *crtc)
3326 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3327 struct drm_device *dev = crtc->dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3330 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3331 dev_priv->display.off(crtc);
3333 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3334 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3337 mutex_lock(&dev->struct_mutex);
3338 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3339 mutex_unlock(&dev->struct_mutex);
3343 /* Prepare for a mode set.
3345 * Note we could be a lot smarter here. We need to figure out which outputs
3346 * will be enabled, which disabled (in short, how the config will changes)
3347 * and perform the minimum necessary steps to accomplish that, e.g. updating
3348 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3349 * panel fitting is in the proper state, etc.
3351 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3353 i9xx_crtc_disable(crtc);
3356 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3358 i9xx_crtc_enable(crtc);
3361 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3363 ironlake_crtc_disable(crtc);
3366 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3368 ironlake_crtc_enable(crtc);
3371 void intel_encoder_prepare(struct drm_encoder *encoder)
3373 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3374 /* lvds has its own version of prepare see intel_lvds_prepare */
3375 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3378 void intel_encoder_commit(struct drm_encoder *encoder)
3380 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3381 struct drm_device *dev = encoder->dev;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3384 /* lvds has its own version of commit see intel_lvds_commit */
3385 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3387 if (HAS_PCH_CPT(dev))
3388 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3391 void intel_encoder_destroy(struct drm_encoder *encoder)
3393 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3395 drm_encoder_cleanup(encoder);
3396 kfree(intel_encoder);
3399 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3400 struct drm_display_mode *mode,
3401 struct drm_display_mode *adjusted_mode)
3403 struct drm_device *dev = crtc->dev;
3405 if (HAS_PCH_SPLIT(dev)) {
3406 /* FDI link clock is fixed at 2.7G */
3407 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3411 /* All interlaced capable intel hw wants timings in frames. Note though
3412 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3413 * timings, so we need to be careful not to clobber these.*/
3414 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3415 drm_mode_set_crtcinfo(adjusted_mode, 0);
3420 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3422 return 400000; /* FIXME */
3425 static int i945_get_display_clock_speed(struct drm_device *dev)
3430 static int i915_get_display_clock_speed(struct drm_device *dev)
3435 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3440 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3444 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3446 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3449 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3450 case GC_DISPLAY_CLOCK_333_MHZ:
3453 case GC_DISPLAY_CLOCK_190_200_MHZ:
3459 static int i865_get_display_clock_speed(struct drm_device *dev)
3464 static int i855_get_display_clock_speed(struct drm_device *dev)
3467 /* Assume that the hardware is in the high speed state. This
3468 * should be the default.
3470 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3471 case GC_CLOCK_133_200:
3472 case GC_CLOCK_100_200:
3474 case GC_CLOCK_166_250:
3476 case GC_CLOCK_100_133:
3480 /* Shouldn't happen */
3484 static int i830_get_display_clock_speed(struct drm_device *dev)
3498 fdi_reduce_ratio(u32 *num, u32 *den)
3500 while (*num > 0xffffff || *den > 0xffffff) {
3507 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3508 int link_clock, struct fdi_m_n *m_n)
3510 m_n->tu = 64; /* default size */
3512 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3513 m_n->gmch_m = bits_per_pixel * pixel_clock;
3514 m_n->gmch_n = link_clock * nlanes * 8;
3515 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3517 m_n->link_m = pixel_clock;
3518 m_n->link_n = link_clock;
3519 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3522 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3524 if (i915_panel_use_ssc >= 0)
3525 return i915_panel_use_ssc != 0;
3526 return dev_priv->lvds_use_ssc
3527 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3531 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3532 * @crtc: CRTC structure
3533 * @mode: requested mode
3535 * A pipe may be connected to one or more outputs. Based on the depth of the
3536 * attached framebuffer, choose a good color depth to use on the pipe.
3538 * If possible, match the pipe depth to the fb depth. In some cases, this
3539 * isn't ideal, because the connected output supports a lesser or restricted
3540 * set of depths. Resolve that here:
3541 * LVDS typically supports only 6bpc, so clamp down in that case
3542 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3543 * Displays may support a restricted set as well, check EDID and clamp as
3545 * DP may want to dither down to 6bpc to fit larger modes
3548 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3549 * true if they don't match).
3551 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3552 unsigned int *pipe_bpp,
3553 struct drm_display_mode *mode)
3555 struct drm_device *dev = crtc->dev;
3556 struct drm_i915_private *dev_priv = dev->dev_private;
3557 struct drm_encoder *encoder;
3558 struct drm_connector *connector;
3559 unsigned int display_bpc = UINT_MAX, bpc;
3561 /* Walk the encoders & connectors on this crtc, get min bpc */
3562 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3563 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3565 if (encoder->crtc != crtc)
3568 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3569 unsigned int lvds_bpc;
3571 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3577 if (lvds_bpc < display_bpc) {
3578 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3579 display_bpc = lvds_bpc;
3584 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3585 /* Use VBT settings if we have an eDP panel */
3586 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3588 if (edp_bpc < display_bpc) {
3589 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3590 display_bpc = edp_bpc;
3595 /* Not one of the known troublemakers, check the EDID */
3596 list_for_each_entry(connector, &dev->mode_config.connector_list,
3598 if (connector->encoder != encoder)
3601 /* Don't use an invalid EDID bpc value */
3602 if (connector->display_info.bpc &&
3603 connector->display_info.bpc < display_bpc) {
3604 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3605 display_bpc = connector->display_info.bpc;
3610 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3611 * through, clamp it down. (Note: >12bpc will be caught below.)
3613 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3614 if (display_bpc > 8 && display_bpc < 12) {
3615 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3618 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3624 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3625 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3630 * We could just drive the pipe at the highest bpc all the time and
3631 * enable dithering as needed, but that costs bandwidth. So choose
3632 * the minimum value that expresses the full color range of the fb but
3633 * also stays within the max display bpc discovered above.
3636 switch (crtc->fb->depth) {
3638 bpc = 8; /* since we go through a colormap */
3642 bpc = 6; /* min is 18bpp */
3654 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3655 bpc = min((unsigned int)8, display_bpc);
3659 display_bpc = min(display_bpc, bpc);
3661 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3664 *pipe_bpp = display_bpc * 3;
3666 return display_bpc != bpc;
3669 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3671 struct drm_device *dev = crtc->dev;
3672 struct drm_i915_private *dev_priv = dev->dev_private;
3675 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3676 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3677 refclk = dev_priv->lvds_ssc_freq * 1000;
3678 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3680 } else if (!IS_GEN2(dev)) {
3689 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3690 intel_clock_t *clock)
3692 /* SDVO TV has fixed PLL values depend on its clock range,
3693 this mirrors vbios setting. */
3694 if (adjusted_mode->clock >= 100000
3695 && adjusted_mode->clock < 140500) {
3701 } else if (adjusted_mode->clock >= 140500
3702 && adjusted_mode->clock <= 200000) {
3711 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3712 intel_clock_t *clock,
3713 intel_clock_t *reduced_clock)
3715 struct drm_device *dev = crtc->dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3718 int pipe = intel_crtc->pipe;
3721 if (IS_PINEVIEW(dev)) {
3722 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3724 fp2 = (1 << reduced_clock->n) << 16 |
3725 reduced_clock->m1 << 8 | reduced_clock->m2;
3727 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3729 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3733 I915_WRITE(FP0(pipe), fp);
3735 intel_crtc->lowfreq_avail = false;
3736 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3737 reduced_clock && i915_powersave) {
3738 I915_WRITE(FP1(pipe), fp2);
3739 intel_crtc->lowfreq_avail = true;
3741 I915_WRITE(FP1(pipe), fp);
3745 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3746 struct drm_display_mode *adjusted_mode)
3748 struct drm_device *dev = crtc->dev;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751 int pipe = intel_crtc->pipe;
3754 temp = I915_READ(LVDS);
3755 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3757 temp |= LVDS_PIPEB_SELECT;
3759 temp &= ~LVDS_PIPEB_SELECT;
3761 /* set the corresponsding LVDS_BORDER bit */
3762 temp |= dev_priv->lvds_border_bits;
3763 /* Set the B0-B3 data pairs corresponding to whether we're going to
3764 * set the DPLLs for dual-channel mode or not.
3767 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3769 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3771 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3772 * appropriately here, but we need to look more thoroughly into how
3773 * panels behave in the two modes.
3775 /* set the dithering flag on LVDS as needed */
3776 if (INTEL_INFO(dev)->gen >= 4) {
3777 if (dev_priv->lvds_dither)
3778 temp |= LVDS_ENABLE_DITHER;
3780 temp &= ~LVDS_ENABLE_DITHER;
3782 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3783 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3784 temp |= LVDS_HSYNC_POLARITY;
3785 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3786 temp |= LVDS_VSYNC_POLARITY;
3787 I915_WRITE(LVDS, temp);
3790 static void i9xx_update_pll(struct drm_crtc *crtc,
3791 struct drm_display_mode *mode,
3792 struct drm_display_mode *adjusted_mode,
3793 intel_clock_t *clock, intel_clock_t *reduced_clock,
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799 int pipe = intel_crtc->pipe;
3803 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3804 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3806 dpll = DPLL_VGA_MODE_DIS;
3808 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3809 dpll |= DPLLB_MODE_LVDS;
3811 dpll |= DPLLB_MODE_DAC_SERIAL;
3813 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3814 if (pixel_multiplier > 1) {
3815 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3816 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3818 dpll |= DPLL_DVO_HIGH_SPEED;
3820 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3821 dpll |= DPLL_DVO_HIGH_SPEED;
3823 /* compute bitmask from p1 value */
3824 if (IS_PINEVIEW(dev))
3825 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3827 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3828 if (IS_G4X(dev) && reduced_clock)
3829 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3831 switch (clock->p2) {
3833 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3836 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3839 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3842 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3845 if (INTEL_INFO(dev)->gen >= 4)
3846 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3848 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3849 dpll |= PLL_REF_INPUT_TVCLKINBC;
3850 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3851 /* XXX: just matching BIOS for now */
3852 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3854 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3855 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3856 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3858 dpll |= PLL_REF_INPUT_DREFCLK;
3860 dpll |= DPLL_VCO_ENABLE;
3861 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3862 POSTING_READ(DPLL(pipe));
3865 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3866 * This is an exception to the general rule that mode_set doesn't turn
3869 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3870 intel_update_lvds(crtc, clock, adjusted_mode);
3872 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3873 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3875 I915_WRITE(DPLL(pipe), dpll);
3877 /* Wait for the clocks to stabilize. */
3878 POSTING_READ(DPLL(pipe));
3881 if (INTEL_INFO(dev)->gen >= 4) {
3884 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3886 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3890 I915_WRITE(DPLL_MD(pipe), temp);
3892 /* The pixel multiplier can only be updated once the
3893 * DPLL is enabled and the clocks are stable.
3895 * So write it again.
3897 I915_WRITE(DPLL(pipe), dpll);
3901 static void i8xx_update_pll(struct drm_crtc *crtc,
3902 struct drm_display_mode *adjusted_mode,
3903 intel_clock_t *clock,
3906 struct drm_device *dev = crtc->dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909 int pipe = intel_crtc->pipe;
3912 dpll = DPLL_VGA_MODE_DIS;
3914 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3915 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3918 dpll |= PLL_P1_DIVIDE_BY_TWO;
3920 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3922 dpll |= PLL_P2_DIVIDE_BY_4;
3925 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3926 /* XXX: just matching BIOS for now */
3927 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3929 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3930 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3931 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3933 dpll |= PLL_REF_INPUT_DREFCLK;
3935 dpll |= DPLL_VCO_ENABLE;
3936 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3937 POSTING_READ(DPLL(pipe));
3940 I915_WRITE(DPLL(pipe), dpll);
3942 /* Wait for the clocks to stabilize. */
3943 POSTING_READ(DPLL(pipe));
3946 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3947 * This is an exception to the general rule that mode_set doesn't turn
3950 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3951 intel_update_lvds(crtc, clock, adjusted_mode);
3953 /* The pixel multiplier can only be updated once the
3954 * DPLL is enabled and the clocks are stable.
3956 * So write it again.
3958 I915_WRITE(DPLL(pipe), dpll);
3961 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3962 struct drm_display_mode *mode,
3963 struct drm_display_mode *adjusted_mode,
3965 struct drm_framebuffer *old_fb)
3967 struct drm_device *dev = crtc->dev;
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3970 int pipe = intel_crtc->pipe;
3971 int plane = intel_crtc->plane;
3972 int refclk, num_connectors = 0;
3973 intel_clock_t clock, reduced_clock;
3974 u32 dspcntr, pipeconf, vsyncshift;
3975 bool ok, has_reduced_clock = false, is_sdvo = false;
3976 bool is_lvds = false, is_tv = false, is_dp = false;
3977 struct drm_mode_config *mode_config = &dev->mode_config;
3978 struct intel_encoder *encoder;
3979 const intel_limit_t *limit;
3982 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3983 if (encoder->base.crtc != crtc)
3986 switch (encoder->type) {
3987 case INTEL_OUTPUT_LVDS:
3990 case INTEL_OUTPUT_SDVO:
3991 case INTEL_OUTPUT_HDMI:
3993 if (encoder->needs_tv_clock)
3996 case INTEL_OUTPUT_TVOUT:
3999 case INTEL_OUTPUT_DISPLAYPORT:
4007 refclk = i9xx_get_refclk(crtc, num_connectors);
4010 * Returns a set of divisors for the desired target clock with the given
4011 * refclk, or FALSE. The returned values represent the clock equation:
4012 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4014 limit = intel_limit(crtc, refclk);
4015 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4018 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4022 /* Ensure that the cursor is valid for the new mode before changing... */
4023 intel_crtc_update_cursor(crtc, true);
4025 if (is_lvds && dev_priv->lvds_downclock_avail) {
4027 * Ensure we match the reduced clock's P to the target clock.
4028 * If the clocks don't match, we can't switch the display clock
4029 * by using the FP0/FP1. In such case we will disable the LVDS
4030 * downclock feature.
4032 has_reduced_clock = limit->find_pll(limit, crtc,
4033 dev_priv->lvds_downclock,
4039 if (is_sdvo && is_tv)
4040 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4042 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4043 &reduced_clock : NULL);
4046 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4048 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4049 has_reduced_clock ? &reduced_clock : NULL,
4052 /* setup pipeconf */
4053 pipeconf = I915_READ(PIPECONF(pipe));
4055 /* Set up the display plane register */
4056 dspcntr = DISPPLANE_GAMMA_ENABLE;
4059 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4061 dspcntr |= DISPPLANE_SEL_PIPE_B;
4063 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4064 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4067 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4071 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4072 pipeconf |= PIPECONF_DOUBLE_WIDE;
4074 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4077 /* default to 8bpc */
4078 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4080 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4081 pipeconf |= PIPECONF_BPP_6 |
4082 PIPECONF_DITHER_EN |
4083 PIPECONF_DITHER_TYPE_SP;
4087 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4088 drm_mode_debug_printmodeline(mode);
4090 if (HAS_PIPE_CXSR(dev)) {
4091 if (intel_crtc->lowfreq_avail) {
4092 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4093 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4095 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4096 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4100 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4101 if (!IS_GEN2(dev) &&
4102 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4103 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4104 /* the chip adds 2 halflines automatically */
4105 adjusted_mode->crtc_vtotal -= 1;
4106 adjusted_mode->crtc_vblank_end -= 1;
4107 vsyncshift = adjusted_mode->crtc_hsync_start
4108 - adjusted_mode->crtc_htotal/2;
4110 pipeconf |= PIPECONF_PROGRESSIVE;
4115 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4117 I915_WRITE(HTOTAL(pipe),
4118 (adjusted_mode->crtc_hdisplay - 1) |
4119 ((adjusted_mode->crtc_htotal - 1) << 16));
4120 I915_WRITE(HBLANK(pipe),
4121 (adjusted_mode->crtc_hblank_start - 1) |
4122 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4123 I915_WRITE(HSYNC(pipe),
4124 (adjusted_mode->crtc_hsync_start - 1) |
4125 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4127 I915_WRITE(VTOTAL(pipe),
4128 (adjusted_mode->crtc_vdisplay - 1) |
4129 ((adjusted_mode->crtc_vtotal - 1) << 16));
4130 I915_WRITE(VBLANK(pipe),
4131 (adjusted_mode->crtc_vblank_start - 1) |
4132 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4133 I915_WRITE(VSYNC(pipe),
4134 (adjusted_mode->crtc_vsync_start - 1) |
4135 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4137 /* pipesrc and dspsize control the size that is scaled from,
4138 * which should always be the user's requested size.
4140 I915_WRITE(DSPSIZE(plane),
4141 ((mode->vdisplay - 1) << 16) |
4142 (mode->hdisplay - 1));
4143 I915_WRITE(DSPPOS(plane), 0);
4144 I915_WRITE(PIPESRC(pipe),
4145 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4147 I915_WRITE(PIPECONF(pipe), pipeconf);
4148 POSTING_READ(PIPECONF(pipe));
4149 intel_enable_pipe(dev_priv, pipe, false);
4151 intel_wait_for_vblank(dev, pipe);
4153 I915_WRITE(DSPCNTR(plane), dspcntr);
4154 POSTING_READ(DSPCNTR(plane));
4156 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4158 intel_update_watermarks(dev);
4164 * Initialize reference clocks when the driver loads
4166 void ironlake_init_pch_refclk(struct drm_device *dev)
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 struct drm_mode_config *mode_config = &dev->mode_config;
4170 struct intel_encoder *encoder;
4172 bool has_lvds = false;
4173 bool has_cpu_edp = false;
4174 bool has_pch_edp = false;
4175 bool has_panel = false;
4176 bool has_ck505 = false;
4177 bool can_ssc = false;
4179 /* We need to take the global config into account */
4180 list_for_each_entry(encoder, &mode_config->encoder_list,
4182 switch (encoder->type) {
4183 case INTEL_OUTPUT_LVDS:
4187 case INTEL_OUTPUT_EDP:
4189 if (intel_encoder_is_pch_edp(&encoder->base))
4197 if (HAS_PCH_IBX(dev)) {
4198 has_ck505 = dev_priv->display_clock_mode;
4199 can_ssc = has_ck505;
4205 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4206 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4209 /* Ironlake: try to setup display ref clock before DPLL
4210 * enabling. This is only under driver's control after
4211 * PCH B stepping, previous chipset stepping should be
4212 * ignoring this setting.
4214 temp = I915_READ(PCH_DREF_CONTROL);
4215 /* Always enable nonspread source */
4216 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4219 temp |= DREF_NONSPREAD_CK505_ENABLE;
4221 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4224 temp &= ~DREF_SSC_SOURCE_MASK;
4225 temp |= DREF_SSC_SOURCE_ENABLE;
4227 /* SSC must be turned on before enabling the CPU output */
4228 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4229 DRM_DEBUG_KMS("Using SSC on panel\n");
4230 temp |= DREF_SSC1_ENABLE;
4232 temp &= ~DREF_SSC1_ENABLE;
4234 /* Get SSC going before enabling the outputs */
4235 I915_WRITE(PCH_DREF_CONTROL, temp);
4236 POSTING_READ(PCH_DREF_CONTROL);
4239 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4241 /* Enable CPU source on CPU attached eDP */
4243 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4244 DRM_DEBUG_KMS("Using SSC on eDP\n");
4245 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4248 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4250 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4252 I915_WRITE(PCH_DREF_CONTROL, temp);
4253 POSTING_READ(PCH_DREF_CONTROL);
4256 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4258 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4260 /* Turn off CPU output */
4261 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4263 I915_WRITE(PCH_DREF_CONTROL, temp);
4264 POSTING_READ(PCH_DREF_CONTROL);
4267 /* Turn off the SSC source */
4268 temp &= ~DREF_SSC_SOURCE_MASK;
4269 temp |= DREF_SSC_SOURCE_DISABLE;
4272 temp &= ~ DREF_SSC1_ENABLE;
4274 I915_WRITE(PCH_DREF_CONTROL, temp);
4275 POSTING_READ(PCH_DREF_CONTROL);
4280 static int ironlake_get_refclk(struct drm_crtc *crtc)
4282 struct drm_device *dev = crtc->dev;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_encoder *encoder;
4285 struct drm_mode_config *mode_config = &dev->mode_config;
4286 struct intel_encoder *edp_encoder = NULL;
4287 int num_connectors = 0;
4288 bool is_lvds = false;
4290 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4291 if (encoder->base.crtc != crtc)
4294 switch (encoder->type) {
4295 case INTEL_OUTPUT_LVDS:
4298 case INTEL_OUTPUT_EDP:
4299 edp_encoder = encoder;
4305 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4306 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4307 dev_priv->lvds_ssc_freq);
4308 return dev_priv->lvds_ssc_freq * 1000;
4314 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4315 struct drm_display_mode *mode,
4316 struct drm_display_mode *adjusted_mode,
4318 struct drm_framebuffer *old_fb)
4320 struct drm_device *dev = crtc->dev;
4321 struct drm_i915_private *dev_priv = dev->dev_private;
4322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4323 int pipe = intel_crtc->pipe;
4324 int plane = intel_crtc->plane;
4325 int refclk, num_connectors = 0;
4326 intel_clock_t clock, reduced_clock;
4327 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4328 bool ok, has_reduced_clock = false, is_sdvo = false;
4329 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4330 struct drm_mode_config *mode_config = &dev->mode_config;
4331 struct intel_encoder *encoder, *edp_encoder = NULL;
4332 const intel_limit_t *limit;
4334 struct fdi_m_n m_n = {0};
4336 int target_clock, pixel_multiplier, lane, link_bw, factor;
4337 unsigned int pipe_bpp;
4339 bool is_cpu_edp = false, is_pch_edp = false;
4341 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4342 if (encoder->base.crtc != crtc)
4345 switch (encoder->type) {
4346 case INTEL_OUTPUT_LVDS:
4349 case INTEL_OUTPUT_SDVO:
4350 case INTEL_OUTPUT_HDMI:
4352 if (encoder->needs_tv_clock)
4355 case INTEL_OUTPUT_TVOUT:
4358 case INTEL_OUTPUT_ANALOG:
4361 case INTEL_OUTPUT_DISPLAYPORT:
4364 case INTEL_OUTPUT_EDP:
4366 if (intel_encoder_is_pch_edp(&encoder->base))
4370 edp_encoder = encoder;
4377 refclk = ironlake_get_refclk(crtc);
4380 * Returns a set of divisors for the desired target clock with the given
4381 * refclk, or FALSE. The returned values represent the clock equation:
4382 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4384 limit = intel_limit(crtc, refclk);
4385 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4388 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4392 /* Ensure that the cursor is valid for the new mode before changing... */
4393 intel_crtc_update_cursor(crtc, true);
4395 if (is_lvds && dev_priv->lvds_downclock_avail) {
4397 * Ensure we match the reduced clock's P to the target clock.
4398 * If the clocks don't match, we can't switch the display clock
4399 * by using the FP0/FP1. In such case we will disable the LVDS
4400 * downclock feature.
4402 has_reduced_clock = limit->find_pll(limit, crtc,
4403 dev_priv->lvds_downclock,
4409 if (is_sdvo && is_tv)
4410 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4414 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4416 /* CPU eDP doesn't require FDI link, so just set DP M/N
4417 according to current link config */
4419 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4421 /* FDI is a binary signal running at ~2.7GHz, encoding
4422 * each output octet as 10 bits. The actual frequency
4423 * is stored as a divider into a 100MHz clock, and the
4424 * mode pixel clock is stored in units of 1KHz.
4425 * Hence the bw of each lane in terms of the mode signal
4428 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4431 /* [e]DP over FDI requires target mode clock instead of link clock. */
4433 target_clock = intel_edp_target_clock(edp_encoder, mode);
4435 target_clock = mode->clock;
4437 target_clock = adjusted_mode->clock;
4439 /* determine panel color depth */
4440 temp = I915_READ(PIPECONF(pipe));
4441 temp &= ~PIPE_BPC_MASK;
4442 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4457 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4464 intel_crtc->bpp = pipe_bpp;
4465 I915_WRITE(PIPECONF(pipe), temp);
4469 * Account for spread spectrum to avoid
4470 * oversubscribing the link. Max center spread
4471 * is 2.5%; use 5% for safety's sake.
4473 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4474 lane = bps / (link_bw * 8) + 1;
4477 intel_crtc->fdi_lanes = lane;
4479 if (pixel_multiplier > 1)
4480 link_bw *= pixel_multiplier;
4481 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4484 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4485 if (has_reduced_clock)
4486 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4489 /* Enable autotuning of the PLL clock (if permissible) */
4492 if ((intel_panel_use_ssc(dev_priv) &&
4493 dev_priv->lvds_ssc_freq == 100) ||
4494 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4496 } else if (is_sdvo && is_tv)
4499 if (clock.m < factor * clock.n)
4505 dpll |= DPLLB_MODE_LVDS;
4507 dpll |= DPLLB_MODE_DAC_SERIAL;
4509 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4510 if (pixel_multiplier > 1) {
4511 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4513 dpll |= DPLL_DVO_HIGH_SPEED;
4515 if (is_dp && !is_cpu_edp)
4516 dpll |= DPLL_DVO_HIGH_SPEED;
4518 /* compute bitmask from p1 value */
4519 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4521 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4538 if (is_sdvo && is_tv)
4539 dpll |= PLL_REF_INPUT_TVCLKINBC;
4541 /* XXX: just matching BIOS for now */
4542 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4544 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4545 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4547 dpll |= PLL_REF_INPUT_DREFCLK;
4549 /* setup pipeconf */
4550 pipeconf = I915_READ(PIPECONF(pipe));
4552 /* Set up the display plane register */
4553 dspcntr = DISPPLANE_GAMMA_ENABLE;
4555 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4556 drm_mode_debug_printmodeline(mode);
4558 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4559 * pre-Haswell/LPT generation */
4560 if (HAS_PCH_LPT(dev)) {
4561 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4563 } else if (!is_cpu_edp) {
4564 struct intel_pch_pll *pll;
4566 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4568 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4573 intel_put_pch_pll(intel_crtc);
4575 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4576 * This is an exception to the general rule that mode_set doesn't turn
4580 temp = I915_READ(PCH_LVDS);
4581 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4582 if (HAS_PCH_CPT(dev)) {
4583 temp &= ~PORT_TRANS_SEL_MASK;
4584 temp |= PORT_TRANS_SEL_CPT(pipe);
4587 temp |= LVDS_PIPEB_SELECT;
4589 temp &= ~LVDS_PIPEB_SELECT;
4592 /* set the corresponsding LVDS_BORDER bit */
4593 temp |= dev_priv->lvds_border_bits;
4594 /* Set the B0-B3 data pairs corresponding to whether we're going to
4595 * set the DPLLs for dual-channel mode or not.
4598 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4600 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4602 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4603 * appropriately here, but we need to look more thoroughly into how
4604 * panels behave in the two modes.
4606 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4607 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4608 temp |= LVDS_HSYNC_POLARITY;
4609 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4610 temp |= LVDS_VSYNC_POLARITY;
4611 I915_WRITE(PCH_LVDS, temp);
4614 pipeconf &= ~PIPECONF_DITHER_EN;
4615 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4616 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4617 pipeconf |= PIPECONF_DITHER_EN;
4618 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4620 if (is_dp && !is_cpu_edp) {
4621 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4623 /* For non-DP output, clear any trans DP clock recovery setting.*/
4624 I915_WRITE(TRANSDATA_M1(pipe), 0);
4625 I915_WRITE(TRANSDATA_N1(pipe), 0);
4626 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4627 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4630 if (intel_crtc->pch_pll) {
4631 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4633 /* Wait for the clocks to stabilize. */
4634 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4637 /* The pixel multiplier can only be updated once the
4638 * DPLL is enabled and the clocks are stable.
4640 * So write it again.
4642 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4645 intel_crtc->lowfreq_avail = false;
4646 if (intel_crtc->pch_pll) {
4647 if (is_lvds && has_reduced_clock && i915_powersave) {
4648 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4649 intel_crtc->lowfreq_avail = true;
4651 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4655 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4656 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4657 pipeconf |= PIPECONF_INTERLACED_ILK;
4658 /* the chip adds 2 halflines automatically */
4659 adjusted_mode->crtc_vtotal -= 1;
4660 adjusted_mode->crtc_vblank_end -= 1;
4661 I915_WRITE(VSYNCSHIFT(pipe),
4662 adjusted_mode->crtc_hsync_start
4663 - adjusted_mode->crtc_htotal/2);
4665 pipeconf |= PIPECONF_PROGRESSIVE;
4666 I915_WRITE(VSYNCSHIFT(pipe), 0);
4669 I915_WRITE(HTOTAL(pipe),
4670 (adjusted_mode->crtc_hdisplay - 1) |
4671 ((adjusted_mode->crtc_htotal - 1) << 16));
4672 I915_WRITE(HBLANK(pipe),
4673 (adjusted_mode->crtc_hblank_start - 1) |
4674 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4675 I915_WRITE(HSYNC(pipe),
4676 (adjusted_mode->crtc_hsync_start - 1) |
4677 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4679 I915_WRITE(VTOTAL(pipe),
4680 (adjusted_mode->crtc_vdisplay - 1) |
4681 ((adjusted_mode->crtc_vtotal - 1) << 16));
4682 I915_WRITE(VBLANK(pipe),
4683 (adjusted_mode->crtc_vblank_start - 1) |
4684 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4685 I915_WRITE(VSYNC(pipe),
4686 (adjusted_mode->crtc_vsync_start - 1) |
4687 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4689 /* pipesrc controls the size that is scaled from, which should
4690 * always be the user's requested size.
4692 I915_WRITE(PIPESRC(pipe),
4693 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4695 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4696 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4697 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4698 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4701 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4703 I915_WRITE(PIPECONF(pipe), pipeconf);
4704 POSTING_READ(PIPECONF(pipe));
4706 intel_wait_for_vblank(dev, pipe);
4708 I915_WRITE(DSPCNTR(plane), dspcntr);
4709 POSTING_READ(DSPCNTR(plane));
4711 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4713 intel_update_watermarks(dev);
4715 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4720 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4721 struct drm_display_mode *mode,
4722 struct drm_display_mode *adjusted_mode,
4724 struct drm_framebuffer *old_fb)
4726 struct drm_device *dev = crtc->dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729 int pipe = intel_crtc->pipe;
4732 drm_vblank_pre_modeset(dev, pipe);
4734 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4736 drm_vblank_post_modeset(dev, pipe);
4739 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4741 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4746 static bool intel_eld_uptodate(struct drm_connector *connector,
4747 int reg_eldv, uint32_t bits_eldv,
4748 int reg_elda, uint32_t bits_elda,
4751 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4752 uint8_t *eld = connector->eld;
4755 i = I915_READ(reg_eldv);
4764 i = I915_READ(reg_elda);
4766 I915_WRITE(reg_elda, i);
4768 for (i = 0; i < eld[2]; i++)
4769 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4775 static void g4x_write_eld(struct drm_connector *connector,
4776 struct drm_crtc *crtc)
4778 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4779 uint8_t *eld = connector->eld;
4784 i = I915_READ(G4X_AUD_VID_DID);
4786 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4787 eldv = G4X_ELDV_DEVCL_DEVBLC;
4789 eldv = G4X_ELDV_DEVCTG;
4791 if (intel_eld_uptodate(connector,
4792 G4X_AUD_CNTL_ST, eldv,
4793 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4794 G4X_HDMIW_HDMIEDID))
4797 i = I915_READ(G4X_AUD_CNTL_ST);
4798 i &= ~(eldv | G4X_ELD_ADDR);
4799 len = (i >> 9) & 0x1f; /* ELD buffer size */
4800 I915_WRITE(G4X_AUD_CNTL_ST, i);
4805 len = min_t(uint8_t, eld[2], len);
4806 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4807 for (i = 0; i < len; i++)
4808 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4810 i = I915_READ(G4X_AUD_CNTL_ST);
4812 I915_WRITE(G4X_AUD_CNTL_ST, i);
4815 static void ironlake_write_eld(struct drm_connector *connector,
4816 struct drm_crtc *crtc)
4818 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4819 uint8_t *eld = connector->eld;
4828 if (HAS_PCH_IBX(connector->dev)) {
4829 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4830 aud_config = IBX_AUD_CONFIG_A;
4831 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4832 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4834 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4835 aud_config = CPT_AUD_CONFIG_A;
4836 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4837 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4840 i = to_intel_crtc(crtc)->pipe;
4841 hdmiw_hdmiedid += i * 0x100;
4842 aud_cntl_st += i * 0x100;
4843 aud_config += i * 0x100;
4845 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4847 i = I915_READ(aud_cntl_st);
4848 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4850 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4851 /* operate blindly on all ports */
4852 eldv = IBX_ELD_VALIDB;
4853 eldv |= IBX_ELD_VALIDB << 4;
4854 eldv |= IBX_ELD_VALIDB << 8;
4856 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4857 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4860 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4861 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4862 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4863 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4865 I915_WRITE(aud_config, 0);
4867 if (intel_eld_uptodate(connector,
4868 aud_cntrl_st2, eldv,
4869 aud_cntl_st, IBX_ELD_ADDRESS,
4873 i = I915_READ(aud_cntrl_st2);
4875 I915_WRITE(aud_cntrl_st2, i);
4880 i = I915_READ(aud_cntl_st);
4881 i &= ~IBX_ELD_ADDRESS;
4882 I915_WRITE(aud_cntl_st, i);
4884 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4885 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4886 for (i = 0; i < len; i++)
4887 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4889 i = I915_READ(aud_cntrl_st2);
4891 I915_WRITE(aud_cntrl_st2, i);
4894 void intel_write_eld(struct drm_encoder *encoder,
4895 struct drm_display_mode *mode)
4897 struct drm_crtc *crtc = encoder->crtc;
4898 struct drm_connector *connector;
4899 struct drm_device *dev = encoder->dev;
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4902 connector = drm_select_eld(encoder, mode);
4906 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4908 drm_get_connector_name(connector),
4909 connector->encoder->base.id,
4910 drm_get_encoder_name(connector->encoder));
4912 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4914 if (dev_priv->display.write_eld)
4915 dev_priv->display.write_eld(connector, crtc);
4918 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4919 void intel_crtc_load_lut(struct drm_crtc *crtc)
4921 struct drm_device *dev = crtc->dev;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4924 int palreg = PALETTE(intel_crtc->pipe);
4927 /* The clocks have to be on to load the palette. */
4928 if (!crtc->enabled || !intel_crtc->active)
4931 /* use legacy palette for Ironlake */
4932 if (HAS_PCH_SPLIT(dev))
4933 palreg = LGC_PALETTE(intel_crtc->pipe);
4935 for (i = 0; i < 256; i++) {
4936 I915_WRITE(palreg + 4 * i,
4937 (intel_crtc->lut_r[i] << 16) |
4938 (intel_crtc->lut_g[i] << 8) |
4939 intel_crtc->lut_b[i]);
4943 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948 bool visible = base != 0;
4951 if (intel_crtc->cursor_visible == visible)
4954 cntl = I915_READ(_CURACNTR);
4956 /* On these chipsets we can only modify the base whilst
4957 * the cursor is disabled.
4959 I915_WRITE(_CURABASE, base);
4961 cntl &= ~(CURSOR_FORMAT_MASK);
4962 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4963 cntl |= CURSOR_ENABLE |
4964 CURSOR_GAMMA_ENABLE |
4967 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4968 I915_WRITE(_CURACNTR, cntl);
4970 intel_crtc->cursor_visible = visible;
4973 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4975 struct drm_device *dev = crtc->dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978 int pipe = intel_crtc->pipe;
4979 bool visible = base != 0;
4981 if (intel_crtc->cursor_visible != visible) {
4982 uint32_t cntl = I915_READ(CURCNTR(pipe));
4984 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4985 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4986 cntl |= pipe << 28; /* Connect to correct pipe */
4988 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4989 cntl |= CURSOR_MODE_DISABLE;
4991 I915_WRITE(CURCNTR(pipe), cntl);
4993 intel_crtc->cursor_visible = visible;
4995 /* and commit changes on next vblank */
4996 I915_WRITE(CURBASE(pipe), base);
4999 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5001 struct drm_device *dev = crtc->dev;
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004 int pipe = intel_crtc->pipe;
5005 bool visible = base != 0;
5007 if (intel_crtc->cursor_visible != visible) {
5008 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5010 cntl &= ~CURSOR_MODE;
5011 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5013 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5014 cntl |= CURSOR_MODE_DISABLE;
5016 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5018 intel_crtc->cursor_visible = visible;
5020 /* and commit changes on next vblank */
5021 I915_WRITE(CURBASE_IVB(pipe), base);
5024 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5025 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5028 struct drm_device *dev = crtc->dev;
5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031 int pipe = intel_crtc->pipe;
5032 int x = intel_crtc->cursor_x;
5033 int y = intel_crtc->cursor_y;
5039 if (on && crtc->enabled && crtc->fb) {
5040 base = intel_crtc->cursor_addr;
5041 if (x > (int) crtc->fb->width)
5044 if (y > (int) crtc->fb->height)
5050 if (x + intel_crtc->cursor_width < 0)
5053 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5056 pos |= x << CURSOR_X_SHIFT;
5059 if (y + intel_crtc->cursor_height < 0)
5062 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5065 pos |= y << CURSOR_Y_SHIFT;
5067 visible = base != 0;
5068 if (!visible && !intel_crtc->cursor_visible)
5071 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5072 I915_WRITE(CURPOS_IVB(pipe), pos);
5073 ivb_update_cursor(crtc, base);
5075 I915_WRITE(CURPOS(pipe), pos);
5076 if (IS_845G(dev) || IS_I865G(dev))
5077 i845_update_cursor(crtc, base);
5079 i9xx_update_cursor(crtc, base);
5083 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5084 struct drm_file *file,
5086 uint32_t width, uint32_t height)
5088 struct drm_device *dev = crtc->dev;
5089 struct drm_i915_private *dev_priv = dev->dev_private;
5090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5091 struct drm_i915_gem_object *obj;
5095 DRM_DEBUG_KMS("\n");
5097 /* if we want to turn off the cursor ignore width and height */
5099 DRM_DEBUG_KMS("cursor off\n");
5102 mutex_lock(&dev->struct_mutex);
5106 /* Currently we only support 64x64 cursors */
5107 if (width != 64 || height != 64) {
5108 DRM_ERROR("we currently only support 64x64 cursors\n");
5112 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5113 if (&obj->base == NULL)
5116 if (obj->base.size < width * height * 4) {
5117 DRM_ERROR("buffer is to small\n");
5122 /* we only need to pin inside GTT if cursor is non-phy */
5123 mutex_lock(&dev->struct_mutex);
5124 if (!dev_priv->info->cursor_needs_physical) {
5125 if (obj->tiling_mode) {
5126 DRM_ERROR("cursor cannot be tiled\n");
5131 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5133 DRM_ERROR("failed to move cursor bo into the GTT\n");
5137 ret = i915_gem_object_put_fence(obj);
5139 DRM_ERROR("failed to release fence for cursor");
5143 addr = obj->gtt_offset;
5145 int align = IS_I830(dev) ? 16 * 1024 : 256;
5146 ret = i915_gem_attach_phys_object(dev, obj,
5147 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5150 DRM_ERROR("failed to attach phys object\n");
5153 addr = obj->phys_obj->handle->busaddr;
5157 I915_WRITE(CURSIZE, (height << 12) | width);
5160 if (intel_crtc->cursor_bo) {
5161 if (dev_priv->info->cursor_needs_physical) {
5162 if (intel_crtc->cursor_bo != obj)
5163 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5165 i915_gem_object_unpin(intel_crtc->cursor_bo);
5166 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5169 mutex_unlock(&dev->struct_mutex);
5171 intel_crtc->cursor_addr = addr;
5172 intel_crtc->cursor_bo = obj;
5173 intel_crtc->cursor_width = width;
5174 intel_crtc->cursor_height = height;
5176 intel_crtc_update_cursor(crtc, true);
5180 i915_gem_object_unpin(obj);
5182 mutex_unlock(&dev->struct_mutex);
5184 drm_gem_object_unreference_unlocked(&obj->base);
5188 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192 intel_crtc->cursor_x = x;
5193 intel_crtc->cursor_y = y;
5195 intel_crtc_update_cursor(crtc, true);
5200 /** Sets the color ramps on behalf of RandR */
5201 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5202 u16 blue, int regno)
5204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206 intel_crtc->lut_r[regno] = red >> 8;
5207 intel_crtc->lut_g[regno] = green >> 8;
5208 intel_crtc->lut_b[regno] = blue >> 8;
5211 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5212 u16 *blue, int regno)
5214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216 *red = intel_crtc->lut_r[regno] << 8;
5217 *green = intel_crtc->lut_g[regno] << 8;
5218 *blue = intel_crtc->lut_b[regno] << 8;
5221 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5222 u16 *blue, uint32_t start, uint32_t size)
5224 int end = (start + size > 256) ? 256 : start + size, i;
5225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5227 for (i = start; i < end; i++) {
5228 intel_crtc->lut_r[i] = red[i] >> 8;
5229 intel_crtc->lut_g[i] = green[i] >> 8;
5230 intel_crtc->lut_b[i] = blue[i] >> 8;
5233 intel_crtc_load_lut(crtc);
5237 * Get a pipe with a simple mode set on it for doing load-based monitor
5240 * It will be up to the load-detect code to adjust the pipe as appropriate for
5241 * its requirements. The pipe will be connected to no other encoders.
5243 * Currently this code will only succeed if there is a pipe with no encoders
5244 * configured for it. In the future, it could choose to temporarily disable
5245 * some outputs to free up a pipe for its use.
5247 * \return crtc, or NULL if no pipes are available.
5250 /* VESA 640x480x72Hz mode to set on the pipe */
5251 static struct drm_display_mode load_detect_mode = {
5252 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5253 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5256 static struct drm_framebuffer *
5257 intel_framebuffer_create(struct drm_device *dev,
5258 struct drm_mode_fb_cmd2 *mode_cmd,
5259 struct drm_i915_gem_object *obj)
5261 struct intel_framebuffer *intel_fb;
5264 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5266 drm_gem_object_unreference_unlocked(&obj->base);
5267 return ERR_PTR(-ENOMEM);
5270 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5272 drm_gem_object_unreference_unlocked(&obj->base);
5274 return ERR_PTR(ret);
5277 return &intel_fb->base;
5281 intel_framebuffer_pitch_for_width(int width, int bpp)
5283 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5284 return ALIGN(pitch, 64);
5288 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5290 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5291 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5294 static struct drm_framebuffer *
5295 intel_framebuffer_create_for_mode(struct drm_device *dev,
5296 struct drm_display_mode *mode,
5299 struct drm_i915_gem_object *obj;
5300 struct drm_mode_fb_cmd2 mode_cmd;
5302 obj = i915_gem_alloc_object(dev,
5303 intel_framebuffer_size_for_mode(mode, bpp));
5305 return ERR_PTR(-ENOMEM);
5307 mode_cmd.width = mode->hdisplay;
5308 mode_cmd.height = mode->vdisplay;
5309 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5311 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5313 return intel_framebuffer_create(dev, &mode_cmd, obj);
5316 static struct drm_framebuffer *
5317 mode_fits_in_fbdev(struct drm_device *dev,
5318 struct drm_display_mode *mode)
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 struct drm_i915_gem_object *obj;
5322 struct drm_framebuffer *fb;
5324 if (dev_priv->fbdev == NULL)
5327 obj = dev_priv->fbdev->ifb.obj;
5331 fb = &dev_priv->fbdev->ifb.base;
5332 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5333 fb->bits_per_pixel))
5336 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5342 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5343 struct drm_connector *connector,
5344 struct drm_display_mode *mode,
5345 struct intel_load_detect_pipe *old)
5347 struct intel_crtc *intel_crtc;
5348 struct drm_crtc *possible_crtc;
5349 struct drm_encoder *encoder = &intel_encoder->base;
5350 struct drm_crtc *crtc = NULL;
5351 struct drm_device *dev = encoder->dev;
5352 struct drm_framebuffer *old_fb;
5355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5356 connector->base.id, drm_get_connector_name(connector),
5357 encoder->base.id, drm_get_encoder_name(encoder));
5360 * Algorithm gets a little messy:
5362 * - if the connector already has an assigned crtc, use it (but make
5363 * sure it's on first)
5365 * - try to find the first unused crtc that can drive this connector,
5366 * and use that if we find one
5369 /* See if we already have a CRTC for this connector */
5370 if (encoder->crtc) {
5371 crtc = encoder->crtc;
5373 intel_crtc = to_intel_crtc(crtc);
5374 old->dpms_mode = intel_crtc->dpms_mode;
5375 old->load_detect_temp = false;
5377 /* Make sure the crtc and connector are running */
5378 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5379 struct drm_encoder_helper_funcs *encoder_funcs;
5380 struct drm_crtc_helper_funcs *crtc_funcs;
5382 crtc_funcs = crtc->helper_private;
5383 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5385 encoder_funcs = encoder->helper_private;
5386 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5392 /* Find an unused one (if possible) */
5393 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5395 if (!(encoder->possible_crtcs & (1 << i)))
5397 if (!possible_crtc->enabled) {
5398 crtc = possible_crtc;
5404 * If we didn't find an unused CRTC, don't use any.
5407 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5411 encoder->crtc = crtc;
5412 connector->encoder = encoder;
5414 intel_crtc = to_intel_crtc(crtc);
5415 old->dpms_mode = intel_crtc->dpms_mode;
5416 old->load_detect_temp = true;
5417 old->release_fb = NULL;
5420 mode = &load_detect_mode;
5424 /* We need a framebuffer large enough to accommodate all accesses
5425 * that the plane may generate whilst we perform load detection.
5426 * We can not rely on the fbcon either being present (we get called
5427 * during its initialisation to detect all boot displays, or it may
5428 * not even exist) or that it is large enough to satisfy the
5431 crtc->fb = mode_fits_in_fbdev(dev, mode);
5432 if (crtc->fb == NULL) {
5433 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5434 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5435 old->release_fb = crtc->fb;
5437 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5438 if (IS_ERR(crtc->fb)) {
5439 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5444 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5445 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5446 if (old->release_fb)
5447 old->release_fb->funcs->destroy(old->release_fb);
5452 /* let the connector get through one full cycle before testing */
5453 intel_wait_for_vblank(dev, intel_crtc->pipe);
5458 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5459 struct drm_connector *connector,
5460 struct intel_load_detect_pipe *old)
5462 struct drm_encoder *encoder = &intel_encoder->base;
5463 struct drm_device *dev = encoder->dev;
5464 struct drm_crtc *crtc = encoder->crtc;
5465 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5466 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5469 connector->base.id, drm_get_connector_name(connector),
5470 encoder->base.id, drm_get_encoder_name(encoder));
5472 if (old->load_detect_temp) {
5473 connector->encoder = NULL;
5474 drm_helper_disable_unused_functions(dev);
5476 if (old->release_fb)
5477 old->release_fb->funcs->destroy(old->release_fb);
5482 /* Switch crtc and encoder back off if necessary */
5483 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5484 encoder_funcs->dpms(encoder, old->dpms_mode);
5485 crtc_funcs->dpms(crtc, old->dpms_mode);
5489 /* Returns the clock of the currently programmed mode of the given pipe. */
5490 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5492 struct drm_i915_private *dev_priv = dev->dev_private;
5493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5494 int pipe = intel_crtc->pipe;
5495 u32 dpll = I915_READ(DPLL(pipe));
5497 intel_clock_t clock;
5499 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5500 fp = I915_READ(FP0(pipe));
5502 fp = I915_READ(FP1(pipe));
5504 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5505 if (IS_PINEVIEW(dev)) {
5506 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5507 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5509 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5510 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5513 if (!IS_GEN2(dev)) {
5514 if (IS_PINEVIEW(dev))
5515 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5516 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5518 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5519 DPLL_FPA01_P1_POST_DIV_SHIFT);
5521 switch (dpll & DPLL_MODE_MASK) {
5522 case DPLLB_MODE_DAC_SERIAL:
5523 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5526 case DPLLB_MODE_LVDS:
5527 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5531 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5532 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5536 /* XXX: Handle the 100Mhz refclk */
5537 intel_clock(dev, 96000, &clock);
5539 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5542 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5543 DPLL_FPA01_P1_POST_DIV_SHIFT);
5546 if ((dpll & PLL_REF_INPUT_MASK) ==
5547 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5548 /* XXX: might not be 66MHz */
5549 intel_clock(dev, 66000, &clock);
5551 intel_clock(dev, 48000, &clock);
5553 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5556 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5557 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5559 if (dpll & PLL_P2_DIVIDE_BY_4)
5564 intel_clock(dev, 48000, &clock);
5568 /* XXX: It would be nice to validate the clocks, but we can't reuse
5569 * i830PllIsValid() because it relies on the xf86_config connector
5570 * configuration being accurate, which it isn't necessarily.
5576 /** Returns the currently programmed mode of the given pipe. */
5577 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5578 struct drm_crtc *crtc)
5580 struct drm_i915_private *dev_priv = dev->dev_private;
5581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5582 int pipe = intel_crtc->pipe;
5583 struct drm_display_mode *mode;
5584 int htot = I915_READ(HTOTAL(pipe));
5585 int hsync = I915_READ(HSYNC(pipe));
5586 int vtot = I915_READ(VTOTAL(pipe));
5587 int vsync = I915_READ(VSYNC(pipe));
5589 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5593 mode->clock = intel_crtc_clock_get(dev, crtc);
5594 mode->hdisplay = (htot & 0xffff) + 1;
5595 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5596 mode->hsync_start = (hsync & 0xffff) + 1;
5597 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5598 mode->vdisplay = (vtot & 0xffff) + 1;
5599 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5600 mode->vsync_start = (vsync & 0xffff) + 1;
5601 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5603 drm_mode_set_name(mode);
5608 #define GPU_IDLE_TIMEOUT 500 /* ms */
5610 /* When this timer fires, we've been idle for awhile */
5611 static void intel_gpu_idle_timer(unsigned long arg)
5613 struct drm_device *dev = (struct drm_device *)arg;
5614 drm_i915_private_t *dev_priv = dev->dev_private;
5616 if (!list_empty(&dev_priv->mm.active_list)) {
5617 /* Still processing requests, so just re-arm the timer. */
5618 mod_timer(&dev_priv->idle_timer, jiffies +
5619 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5623 dev_priv->busy = false;
5624 queue_work(dev_priv->wq, &dev_priv->idle_work);
5627 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5629 static void intel_crtc_idle_timer(unsigned long arg)
5631 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5632 struct drm_crtc *crtc = &intel_crtc->base;
5633 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5634 struct intel_framebuffer *intel_fb;
5636 intel_fb = to_intel_framebuffer(crtc->fb);
5637 if (intel_fb && intel_fb->obj->active) {
5638 /* The framebuffer is still being accessed by the GPU. */
5639 mod_timer(&intel_crtc->idle_timer, jiffies +
5640 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5644 intel_crtc->busy = false;
5645 queue_work(dev_priv->wq, &dev_priv->idle_work);
5648 static void intel_increase_pllclock(struct drm_crtc *crtc)
5650 struct drm_device *dev = crtc->dev;
5651 drm_i915_private_t *dev_priv = dev->dev_private;
5652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5653 int pipe = intel_crtc->pipe;
5654 int dpll_reg = DPLL(pipe);
5657 if (HAS_PCH_SPLIT(dev))
5660 if (!dev_priv->lvds_downclock_avail)
5663 dpll = I915_READ(dpll_reg);
5664 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5665 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5667 assert_panel_unlocked(dev_priv, pipe);
5669 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5670 I915_WRITE(dpll_reg, dpll);
5671 intel_wait_for_vblank(dev, pipe);
5673 dpll = I915_READ(dpll_reg);
5674 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5675 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5678 /* Schedule downclock */
5679 mod_timer(&intel_crtc->idle_timer, jiffies +
5680 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5683 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5685 struct drm_device *dev = crtc->dev;
5686 drm_i915_private_t *dev_priv = dev->dev_private;
5687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5689 if (HAS_PCH_SPLIT(dev))
5692 if (!dev_priv->lvds_downclock_avail)
5696 * Since this is called by a timer, we should never get here in
5699 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5700 int pipe = intel_crtc->pipe;
5701 int dpll_reg = DPLL(pipe);
5704 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5706 assert_panel_unlocked(dev_priv, pipe);
5708 dpll = I915_READ(dpll_reg);
5709 dpll |= DISPLAY_RATE_SELECT_FPA1;
5710 I915_WRITE(dpll_reg, dpll);
5711 intel_wait_for_vblank(dev, pipe);
5712 dpll = I915_READ(dpll_reg);
5713 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5714 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5720 * intel_idle_update - adjust clocks for idleness
5721 * @work: work struct
5723 * Either the GPU or display (or both) went idle. Check the busy status
5724 * here and adjust the CRTC and GPU clocks as necessary.
5726 static void intel_idle_update(struct work_struct *work)
5728 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5730 struct drm_device *dev = dev_priv->dev;
5731 struct drm_crtc *crtc;
5732 struct intel_crtc *intel_crtc;
5734 if (!i915_powersave)
5737 mutex_lock(&dev->struct_mutex);
5739 i915_update_gfx_val(dev_priv);
5741 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5742 /* Skip inactive CRTCs */
5746 intel_crtc = to_intel_crtc(crtc);
5747 if (!intel_crtc->busy)
5748 intel_decrease_pllclock(crtc);
5752 mutex_unlock(&dev->struct_mutex);
5756 * intel_mark_busy - mark the GPU and possibly the display busy
5758 * @obj: object we're operating on
5760 * Callers can use this function to indicate that the GPU is busy processing
5761 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5762 * buffer), we'll also mark the display as busy, so we know to increase its
5765 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5767 drm_i915_private_t *dev_priv = dev->dev_private;
5768 struct drm_crtc *crtc = NULL;
5769 struct intel_framebuffer *intel_fb;
5770 struct intel_crtc *intel_crtc;
5772 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5775 if (!dev_priv->busy) {
5776 intel_sanitize_pm(dev);
5777 dev_priv->busy = true;
5779 mod_timer(&dev_priv->idle_timer, jiffies +
5780 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5785 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5789 intel_crtc = to_intel_crtc(crtc);
5790 intel_fb = to_intel_framebuffer(crtc->fb);
5791 if (intel_fb->obj == obj) {
5792 if (!intel_crtc->busy) {
5793 /* Non-busy -> busy, upclock */
5794 intel_increase_pllclock(crtc);
5795 intel_crtc->busy = true;
5797 /* Busy -> busy, put off timer */
5798 mod_timer(&intel_crtc->idle_timer, jiffies +
5799 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5805 static void intel_crtc_destroy(struct drm_crtc *crtc)
5807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5808 struct drm_device *dev = crtc->dev;
5809 struct intel_unpin_work *work;
5810 unsigned long flags;
5812 spin_lock_irqsave(&dev->event_lock, flags);
5813 work = intel_crtc->unpin_work;
5814 intel_crtc->unpin_work = NULL;
5815 spin_unlock_irqrestore(&dev->event_lock, flags);
5818 cancel_work_sync(&work->work);
5822 drm_crtc_cleanup(crtc);
5827 static void intel_unpin_work_fn(struct work_struct *__work)
5829 struct intel_unpin_work *work =
5830 container_of(__work, struct intel_unpin_work, work);
5832 mutex_lock(&work->dev->struct_mutex);
5833 intel_unpin_fb_obj(work->old_fb_obj);
5834 drm_gem_object_unreference(&work->pending_flip_obj->base);
5835 drm_gem_object_unreference(&work->old_fb_obj->base);
5837 intel_update_fbc(work->dev);
5838 mutex_unlock(&work->dev->struct_mutex);
5842 static void do_intel_finish_page_flip(struct drm_device *dev,
5843 struct drm_crtc *crtc)
5845 drm_i915_private_t *dev_priv = dev->dev_private;
5846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5847 struct intel_unpin_work *work;
5848 struct drm_i915_gem_object *obj;
5849 struct drm_pending_vblank_event *e;
5850 struct timeval tnow, tvbl;
5851 unsigned long flags;
5853 /* Ignore early vblank irqs */
5854 if (intel_crtc == NULL)
5857 do_gettimeofday(&tnow);
5859 spin_lock_irqsave(&dev->event_lock, flags);
5860 work = intel_crtc->unpin_work;
5861 if (work == NULL || !work->pending) {
5862 spin_unlock_irqrestore(&dev->event_lock, flags);
5866 intel_crtc->unpin_work = NULL;
5870 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5872 /* Called before vblank count and timestamps have
5873 * been updated for the vblank interval of flip
5874 * completion? Need to increment vblank count and
5875 * add one videorefresh duration to returned timestamp
5876 * to account for this. We assume this happened if we
5877 * get called over 0.9 frame durations after the last
5878 * timestamped vblank.
5880 * This calculation can not be used with vrefresh rates
5881 * below 5Hz (10Hz to be on the safe side) without
5882 * promoting to 64 integers.
5884 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5885 9 * crtc->framedur_ns) {
5886 e->event.sequence++;
5887 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5891 e->event.tv_sec = tvbl.tv_sec;
5892 e->event.tv_usec = tvbl.tv_usec;
5894 list_add_tail(&e->base.link,
5895 &e->base.file_priv->event_list);
5896 wake_up_interruptible(&e->base.file_priv->event_wait);
5899 drm_vblank_put(dev, intel_crtc->pipe);
5901 spin_unlock_irqrestore(&dev->event_lock, flags);
5903 obj = work->old_fb_obj;
5905 atomic_clear_mask(1 << intel_crtc->plane,
5906 &obj->pending_flip.counter);
5907 if (atomic_read(&obj->pending_flip) == 0)
5908 wake_up(&dev_priv->pending_flip_queue);
5910 schedule_work(&work->work);
5912 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5915 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5917 drm_i915_private_t *dev_priv = dev->dev_private;
5918 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5920 do_intel_finish_page_flip(dev, crtc);
5923 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5925 drm_i915_private_t *dev_priv = dev->dev_private;
5926 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5928 do_intel_finish_page_flip(dev, crtc);
5931 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5933 drm_i915_private_t *dev_priv = dev->dev_private;
5934 struct intel_crtc *intel_crtc =
5935 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5936 unsigned long flags;
5938 spin_lock_irqsave(&dev->event_lock, flags);
5939 if (intel_crtc->unpin_work) {
5940 if ((++intel_crtc->unpin_work->pending) > 1)
5941 DRM_ERROR("Prepared flip multiple times\n");
5943 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5945 spin_unlock_irqrestore(&dev->event_lock, flags);
5948 static int intel_gen2_queue_flip(struct drm_device *dev,
5949 struct drm_crtc *crtc,
5950 struct drm_framebuffer *fb,
5951 struct drm_i915_gem_object *obj)
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5955 unsigned long offset;
5957 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5960 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5964 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5965 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5967 ret = intel_ring_begin(ring, 6);
5971 /* Can't queue multiple flips, so wait for the previous
5972 * one to finish before executing the next.
5974 if (intel_crtc->plane)
5975 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5977 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5978 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5979 intel_ring_emit(ring, MI_NOOP);
5980 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5981 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5982 intel_ring_emit(ring, fb->pitches[0]);
5983 intel_ring_emit(ring, obj->gtt_offset + offset);
5984 intel_ring_emit(ring, 0); /* aux display base address, unused */
5985 intel_ring_advance(ring);
5989 intel_unpin_fb_obj(obj);
5994 static int intel_gen3_queue_flip(struct drm_device *dev,
5995 struct drm_crtc *crtc,
5996 struct drm_framebuffer *fb,
5997 struct drm_i915_gem_object *obj)
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001 unsigned long offset;
6003 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6006 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6010 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6011 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6013 ret = intel_ring_begin(ring, 6);
6017 if (intel_crtc->plane)
6018 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6020 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6021 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6022 intel_ring_emit(ring, MI_NOOP);
6023 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6024 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6025 intel_ring_emit(ring, fb->pitches[0]);
6026 intel_ring_emit(ring, obj->gtt_offset + offset);
6027 intel_ring_emit(ring, MI_NOOP);
6029 intel_ring_advance(ring);
6033 intel_unpin_fb_obj(obj);
6038 static int intel_gen4_queue_flip(struct drm_device *dev,
6039 struct drm_crtc *crtc,
6040 struct drm_framebuffer *fb,
6041 struct drm_i915_gem_object *obj)
6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 uint32_t pf, pipesrc;
6046 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6049 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6053 ret = intel_ring_begin(ring, 4);
6057 /* i965+ uses the linear or tiled offsets from the
6058 * Display Registers (which do not change across a page-flip)
6059 * so we need only reprogram the base address.
6061 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6062 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6063 intel_ring_emit(ring, fb->pitches[0]);
6064 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
6066 /* XXX Enabling the panel-fitter across page-flip is so far
6067 * untested on non-native modes, so ignore it for now.
6068 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6071 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6072 intel_ring_emit(ring, pf | pipesrc);
6073 intel_ring_advance(ring);
6077 intel_unpin_fb_obj(obj);
6082 static int intel_gen6_queue_flip(struct drm_device *dev,
6083 struct drm_crtc *crtc,
6084 struct drm_framebuffer *fb,
6085 struct drm_i915_gem_object *obj)
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6089 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6090 uint32_t pf, pipesrc;
6093 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6097 ret = intel_ring_begin(ring, 4);
6101 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6103 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6104 intel_ring_emit(ring, obj->gtt_offset);
6106 /* Contrary to the suggestions in the documentation,
6107 * "Enable Panel Fitter" does not seem to be required when page
6108 * flipping with a non-native mode, and worse causes a normal
6110 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6113 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6114 intel_ring_emit(ring, pf | pipesrc);
6115 intel_ring_advance(ring);
6119 intel_unpin_fb_obj(obj);
6125 * On gen7 we currently use the blit ring because (in early silicon at least)
6126 * the render ring doesn't give us interrpts for page flip completion, which
6127 * means clients will hang after the first flip is queued. Fortunately the
6128 * blit ring generates interrupts properly, so use it instead.
6130 static int intel_gen7_queue_flip(struct drm_device *dev,
6131 struct drm_crtc *crtc,
6132 struct drm_framebuffer *fb,
6133 struct drm_i915_gem_object *obj)
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6137 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6138 uint32_t plane_bit = 0;
6141 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6145 switch(intel_crtc->plane) {
6147 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6150 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6153 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6156 WARN_ONCE(1, "unknown plane in flip command\n");
6161 ret = intel_ring_begin(ring, 4);
6165 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6166 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6167 intel_ring_emit(ring, (obj->gtt_offset));
6168 intel_ring_emit(ring, (MI_NOOP));
6169 intel_ring_advance(ring);
6173 intel_unpin_fb_obj(obj);
6178 static int intel_default_queue_flip(struct drm_device *dev,
6179 struct drm_crtc *crtc,
6180 struct drm_framebuffer *fb,
6181 struct drm_i915_gem_object *obj)
6186 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6187 struct drm_framebuffer *fb,
6188 struct drm_pending_vblank_event *event)
6190 struct drm_device *dev = crtc->dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 struct intel_framebuffer *intel_fb;
6193 struct drm_i915_gem_object *obj;
6194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6195 struct intel_unpin_work *work;
6196 unsigned long flags;
6199 work = kzalloc(sizeof *work, GFP_KERNEL);
6203 work->event = event;
6204 work->dev = crtc->dev;
6205 intel_fb = to_intel_framebuffer(crtc->fb);
6206 work->old_fb_obj = intel_fb->obj;
6207 INIT_WORK(&work->work, intel_unpin_work_fn);
6209 ret = drm_vblank_get(dev, intel_crtc->pipe);
6213 /* We borrow the event spin lock for protecting unpin_work */
6214 spin_lock_irqsave(&dev->event_lock, flags);
6215 if (intel_crtc->unpin_work) {
6216 spin_unlock_irqrestore(&dev->event_lock, flags);
6218 drm_vblank_put(dev, intel_crtc->pipe);
6220 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6223 intel_crtc->unpin_work = work;
6224 spin_unlock_irqrestore(&dev->event_lock, flags);
6226 intel_fb = to_intel_framebuffer(fb);
6227 obj = intel_fb->obj;
6229 mutex_lock(&dev->struct_mutex);
6231 /* Reference the objects for the scheduled work. */
6232 drm_gem_object_reference(&work->old_fb_obj->base);
6233 drm_gem_object_reference(&obj->base);
6237 work->pending_flip_obj = obj;
6239 work->enable_stall_check = true;
6241 /* Block clients from rendering to the new back buffer until
6242 * the flip occurs and the object is no longer visible.
6244 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6246 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6248 goto cleanup_pending;
6250 intel_disable_fbc(dev);
6251 intel_mark_busy(dev, obj);
6252 mutex_unlock(&dev->struct_mutex);
6254 trace_i915_flip_request(intel_crtc->plane, obj);
6259 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6260 drm_gem_object_unreference(&work->old_fb_obj->base);
6261 drm_gem_object_unreference(&obj->base);
6262 mutex_unlock(&dev->struct_mutex);
6264 spin_lock_irqsave(&dev->event_lock, flags);
6265 intel_crtc->unpin_work = NULL;
6266 spin_unlock_irqrestore(&dev->event_lock, flags);
6268 drm_vblank_put(dev, intel_crtc->pipe);
6275 static void intel_sanitize_modesetting(struct drm_device *dev,
6276 int pipe, int plane)
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6282 /* Clear any frame start delays used for debugging left by the BIOS */
6285 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6288 if (HAS_PCH_SPLIT(dev))
6291 /* Who knows what state these registers were left in by the BIOS or
6294 * If we leave the registers in a conflicting state (e.g. with the
6295 * display plane reading from the other pipe than the one we intend
6296 * to use) then when we attempt to teardown the active mode, we will
6297 * not disable the pipes and planes in the correct order -- leaving
6298 * a plane reading from a disabled pipe and possibly leading to
6299 * undefined behaviour.
6302 reg = DSPCNTR(plane);
6303 val = I915_READ(reg);
6305 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6307 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6310 /* This display plane is active and attached to the other CPU pipe. */
6313 /* Disable the plane and wait for it to stop reading from the pipe. */
6314 intel_disable_plane(dev_priv, plane, pipe);
6315 intel_disable_pipe(dev_priv, pipe);
6318 static void intel_crtc_reset(struct drm_crtc *crtc)
6320 struct drm_device *dev = crtc->dev;
6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6323 /* Reset flags back to the 'unknown' status so that they
6324 * will be correctly set on the initial modeset.
6326 intel_crtc->dpms_mode = -1;
6328 /* We need to fix up any BIOS configuration that conflicts with
6331 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6334 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6335 .dpms = intel_crtc_dpms,
6336 .mode_fixup = intel_crtc_mode_fixup,
6337 .mode_set = intel_crtc_mode_set,
6338 .mode_set_base = intel_pipe_set_base,
6339 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6340 .load_lut = intel_crtc_load_lut,
6341 .disable = intel_crtc_disable,
6344 static const struct drm_crtc_funcs intel_crtc_funcs = {
6345 .reset = intel_crtc_reset,
6346 .cursor_set = intel_crtc_cursor_set,
6347 .cursor_move = intel_crtc_cursor_move,
6348 .gamma_set = intel_crtc_gamma_set,
6349 .set_config = drm_crtc_helper_set_config,
6350 .destroy = intel_crtc_destroy,
6351 .page_flip = intel_crtc_page_flip,
6354 static void intel_pch_pll_init(struct drm_device *dev)
6356 drm_i915_private_t *dev_priv = dev->dev_private;
6359 if (dev_priv->num_pch_pll == 0) {
6360 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6364 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6365 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6366 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6367 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6371 static void intel_crtc_init(struct drm_device *dev, int pipe)
6373 drm_i915_private_t *dev_priv = dev->dev_private;
6374 struct intel_crtc *intel_crtc;
6377 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6378 if (intel_crtc == NULL)
6381 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6383 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6384 for (i = 0; i < 256; i++) {
6385 intel_crtc->lut_r[i] = i;
6386 intel_crtc->lut_g[i] = i;
6387 intel_crtc->lut_b[i] = i;
6390 /* Swap pipes & planes for FBC on pre-965 */
6391 intel_crtc->pipe = pipe;
6392 intel_crtc->plane = pipe;
6393 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6394 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6395 intel_crtc->plane = !pipe;
6398 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6399 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6400 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6401 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6403 intel_crtc_reset(&intel_crtc->base);
6404 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6405 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6407 if (HAS_PCH_SPLIT(dev)) {
6408 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6409 intel_helper_funcs.commit = ironlake_crtc_commit;
6411 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6412 intel_helper_funcs.commit = i9xx_crtc_commit;
6415 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6417 intel_crtc->busy = false;
6419 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6420 (unsigned long)intel_crtc);
6423 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6424 struct drm_file *file)
6426 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6427 struct drm_mode_object *drmmode_obj;
6428 struct intel_crtc *crtc;
6430 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6433 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6434 DRM_MODE_OBJECT_CRTC);
6437 DRM_ERROR("no such CRTC id\n");
6441 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6442 pipe_from_crtc_id->pipe = crtc->pipe;
6447 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6449 struct intel_encoder *encoder;
6453 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6454 if (type_mask & encoder->clone_mask)
6455 index_mask |= (1 << entry);
6462 static bool has_edp_a(struct drm_device *dev)
6464 struct drm_i915_private *dev_priv = dev->dev_private;
6466 if (!IS_MOBILE(dev))
6469 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6473 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6479 static void intel_setup_outputs(struct drm_device *dev)
6481 struct drm_i915_private *dev_priv = dev->dev_private;
6482 struct intel_encoder *encoder;
6483 bool dpd_is_edp = false;
6486 has_lvds = intel_lvds_init(dev);
6487 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6488 /* disable the panel fitter on everything but LVDS */
6489 I915_WRITE(PFIT_CONTROL, 0);
6492 if (HAS_PCH_SPLIT(dev)) {
6493 dpd_is_edp = intel_dpd_is_edp(dev);
6496 intel_dp_init(dev, DP_A);
6498 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6499 intel_dp_init(dev, PCH_DP_D);
6502 intel_crt_init(dev);
6504 if (IS_HASWELL(dev)) {
6507 /* Haswell uses DDI functions to detect digital outputs */
6508 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6509 /* DDI A only supports eDP */
6511 intel_ddi_init(dev, PORT_A);
6513 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6515 found = I915_READ(SFUSE_STRAP);
6517 if (found & SFUSE_STRAP_DDIB_DETECTED)
6518 intel_ddi_init(dev, PORT_B);
6519 if (found & SFUSE_STRAP_DDIC_DETECTED)
6520 intel_ddi_init(dev, PORT_C);
6521 if (found & SFUSE_STRAP_DDID_DETECTED)
6522 intel_ddi_init(dev, PORT_D);
6523 } else if (HAS_PCH_SPLIT(dev)) {
6526 if (I915_READ(HDMIB) & PORT_DETECTED) {
6527 /* PCH SDVOB multiplex with HDMIB */
6528 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6530 intel_hdmi_init(dev, HDMIB);
6531 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6532 intel_dp_init(dev, PCH_DP_B);
6535 if (I915_READ(HDMIC) & PORT_DETECTED)
6536 intel_hdmi_init(dev, HDMIC);
6538 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6539 intel_hdmi_init(dev, HDMID);
6541 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6542 intel_dp_init(dev, PCH_DP_C);
6544 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6545 intel_dp_init(dev, PCH_DP_D);
6547 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6550 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6551 DRM_DEBUG_KMS("probing SDVOB\n");
6552 found = intel_sdvo_init(dev, SDVOB, true);
6553 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6554 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6555 intel_hdmi_init(dev, SDVOB);
6558 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6559 DRM_DEBUG_KMS("probing DP_B\n");
6560 intel_dp_init(dev, DP_B);
6564 /* Before G4X SDVOC doesn't have its own detect register */
6566 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6567 DRM_DEBUG_KMS("probing SDVOC\n");
6568 found = intel_sdvo_init(dev, SDVOC, false);
6571 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6573 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6574 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6575 intel_hdmi_init(dev, SDVOC);
6577 if (SUPPORTS_INTEGRATED_DP(dev)) {
6578 DRM_DEBUG_KMS("probing DP_C\n");
6579 intel_dp_init(dev, DP_C);
6583 if (SUPPORTS_INTEGRATED_DP(dev) &&
6584 (I915_READ(DP_D) & DP_DETECTED)) {
6585 DRM_DEBUG_KMS("probing DP_D\n");
6586 intel_dp_init(dev, DP_D);
6588 } else if (IS_GEN2(dev))
6589 intel_dvo_init(dev);
6591 if (SUPPORTS_TV(dev))
6594 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6595 encoder->base.possible_crtcs = encoder->crtc_mask;
6596 encoder->base.possible_clones =
6597 intel_encoder_clones(dev, encoder->clone_mask);
6600 /* disable all the possible outputs/crtcs before entering KMS mode */
6601 drm_helper_disable_unused_functions(dev);
6603 if (HAS_PCH_SPLIT(dev))
6604 ironlake_init_pch_refclk(dev);
6607 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6609 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6611 drm_framebuffer_cleanup(fb);
6612 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6617 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6618 struct drm_file *file,
6619 unsigned int *handle)
6621 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6622 struct drm_i915_gem_object *obj = intel_fb->obj;
6624 return drm_gem_handle_create(file, &obj->base, handle);
6627 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6628 .destroy = intel_user_framebuffer_destroy,
6629 .create_handle = intel_user_framebuffer_create_handle,
6632 int intel_framebuffer_init(struct drm_device *dev,
6633 struct intel_framebuffer *intel_fb,
6634 struct drm_mode_fb_cmd2 *mode_cmd,
6635 struct drm_i915_gem_object *obj)
6639 if (obj->tiling_mode == I915_TILING_Y)
6642 if (mode_cmd->pitches[0] & 63)
6645 switch (mode_cmd->pixel_format) {
6646 case DRM_FORMAT_RGB332:
6647 case DRM_FORMAT_RGB565:
6648 case DRM_FORMAT_XRGB8888:
6649 case DRM_FORMAT_XBGR8888:
6650 case DRM_FORMAT_ARGB8888:
6651 case DRM_FORMAT_XRGB2101010:
6652 case DRM_FORMAT_ARGB2101010:
6653 /* RGB formats are common across chipsets */
6655 case DRM_FORMAT_YUYV:
6656 case DRM_FORMAT_UYVY:
6657 case DRM_FORMAT_YVYU:
6658 case DRM_FORMAT_VYUY:
6661 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6662 mode_cmd->pixel_format);
6666 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6668 DRM_ERROR("framebuffer init failed %d\n", ret);
6672 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6673 intel_fb->obj = obj;
6677 static struct drm_framebuffer *
6678 intel_user_framebuffer_create(struct drm_device *dev,
6679 struct drm_file *filp,
6680 struct drm_mode_fb_cmd2 *mode_cmd)
6682 struct drm_i915_gem_object *obj;
6684 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6685 mode_cmd->handles[0]));
6686 if (&obj->base == NULL)
6687 return ERR_PTR(-ENOENT);
6689 return intel_framebuffer_create(dev, mode_cmd, obj);
6692 static const struct drm_mode_config_funcs intel_mode_funcs = {
6693 .fb_create = intel_user_framebuffer_create,
6694 .output_poll_changed = intel_fb_output_poll_changed,
6697 /* Set up chip specific display functions */
6698 static void intel_init_display(struct drm_device *dev)
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6702 /* We always want a DPMS function */
6703 if (HAS_PCH_SPLIT(dev)) {
6704 dev_priv->display.dpms = ironlake_crtc_dpms;
6705 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6706 dev_priv->display.off = ironlake_crtc_off;
6707 dev_priv->display.update_plane = ironlake_update_plane;
6709 dev_priv->display.dpms = i9xx_crtc_dpms;
6710 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6711 dev_priv->display.off = i9xx_crtc_off;
6712 dev_priv->display.update_plane = i9xx_update_plane;
6715 /* Returns the core display clock speed */
6716 if (IS_VALLEYVIEW(dev))
6717 dev_priv->display.get_display_clock_speed =
6718 valleyview_get_display_clock_speed;
6719 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6720 dev_priv->display.get_display_clock_speed =
6721 i945_get_display_clock_speed;
6722 else if (IS_I915G(dev))
6723 dev_priv->display.get_display_clock_speed =
6724 i915_get_display_clock_speed;
6725 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6726 dev_priv->display.get_display_clock_speed =
6727 i9xx_misc_get_display_clock_speed;
6728 else if (IS_I915GM(dev))
6729 dev_priv->display.get_display_clock_speed =
6730 i915gm_get_display_clock_speed;
6731 else if (IS_I865G(dev))
6732 dev_priv->display.get_display_clock_speed =
6733 i865_get_display_clock_speed;
6734 else if (IS_I85X(dev))
6735 dev_priv->display.get_display_clock_speed =
6736 i855_get_display_clock_speed;
6738 dev_priv->display.get_display_clock_speed =
6739 i830_get_display_clock_speed;
6741 if (HAS_PCH_SPLIT(dev)) {
6743 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6744 dev_priv->display.write_eld = ironlake_write_eld;
6745 } else if (IS_GEN6(dev)) {
6746 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6747 dev_priv->display.write_eld = ironlake_write_eld;
6748 } else if (IS_IVYBRIDGE(dev)) {
6749 /* FIXME: detect B0+ stepping and use auto training */
6750 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6751 dev_priv->display.write_eld = ironlake_write_eld;
6752 } else if (IS_HASWELL(dev)) {
6753 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6754 dev_priv->display.write_eld = ironlake_write_eld;
6756 dev_priv->display.update_wm = NULL;
6757 } else if (IS_VALLEYVIEW(dev)) {
6758 dev_priv->display.force_wake_get = vlv_force_wake_get;
6759 dev_priv->display.force_wake_put = vlv_force_wake_put;
6760 } else if (IS_G4X(dev)) {
6761 dev_priv->display.write_eld = g4x_write_eld;
6764 /* Default just returns -ENODEV to indicate unsupported */
6765 dev_priv->display.queue_flip = intel_default_queue_flip;
6767 switch (INTEL_INFO(dev)->gen) {
6769 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6773 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6778 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6782 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6785 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6791 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6792 * resume, or other times. This quirk makes sure that's the case for
6795 static void quirk_pipea_force(struct drm_device *dev)
6797 struct drm_i915_private *dev_priv = dev->dev_private;
6799 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6800 DRM_INFO("applying pipe a force quirk\n");
6804 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6806 static void quirk_ssc_force_disable(struct drm_device *dev)
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6810 DRM_INFO("applying lvds SSC disable quirk\n");
6814 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6817 static void quirk_invert_brightness(struct drm_device *dev)
6819 struct drm_i915_private *dev_priv = dev->dev_private;
6820 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6821 DRM_INFO("applying inverted panel brightness quirk\n");
6824 struct intel_quirk {
6826 int subsystem_vendor;
6827 int subsystem_device;
6828 void (*hook)(struct drm_device *dev);
6831 static struct intel_quirk intel_quirks[] = {
6832 /* HP Mini needs pipe A force quirk (LP: #322104) */
6833 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6835 /* Thinkpad R31 needs pipe A force quirk */
6836 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6837 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6838 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6840 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6841 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6842 /* ThinkPad X40 needs pipe A force quirk */
6844 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6845 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6847 /* 855 & before need to leave pipe A & dpll A up */
6848 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6849 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6851 /* Lenovo U160 cannot use SSC on LVDS */
6852 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6854 /* Sony Vaio Y cannot use SSC on LVDS */
6855 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6857 /* Acer Aspire 5734Z must invert backlight brightness */
6858 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6861 static void intel_init_quirks(struct drm_device *dev)
6863 struct pci_dev *d = dev->pdev;
6866 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6867 struct intel_quirk *q = &intel_quirks[i];
6869 if (d->device == q->device &&
6870 (d->subsystem_vendor == q->subsystem_vendor ||
6871 q->subsystem_vendor == PCI_ANY_ID) &&
6872 (d->subsystem_device == q->subsystem_device ||
6873 q->subsystem_device == PCI_ANY_ID))
6878 /* Disable the VGA plane that we never use */
6879 static void i915_disable_vga(struct drm_device *dev)
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6885 if (HAS_PCH_SPLIT(dev))
6886 vga_reg = CPU_VGACNTRL;
6890 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6891 outb(SR01, VGA_SR_INDEX);
6892 sr1 = inb(VGA_SR_DATA);
6893 outb(sr1 | 1<<5, VGA_SR_DATA);
6894 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6897 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6898 POSTING_READ(vga_reg);
6901 static void ivb_pch_pwm_override(struct drm_device *dev)
6903 struct drm_i915_private *dev_priv = dev->dev_private;
6906 * IVB has CPU eDP backlight regs too, set things up to let the
6907 * PCH regs control the backlight
6909 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6910 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6911 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6914 void intel_modeset_init_hw(struct drm_device *dev)
6916 struct drm_i915_private *dev_priv = dev->dev_private;
6918 intel_init_clock_gating(dev);
6920 if (IS_IRONLAKE_M(dev)) {
6921 ironlake_enable_drps(dev);
6922 ironlake_enable_rc6(dev);
6923 intel_init_emon(dev);
6926 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6927 gen6_enable_rps(dev_priv);
6928 gen6_update_ring_freq(dev_priv);
6931 if (IS_IVYBRIDGE(dev))
6932 ivb_pch_pwm_override(dev);
6935 void intel_modeset_init(struct drm_device *dev)
6937 struct drm_i915_private *dev_priv = dev->dev_private;
6940 drm_mode_config_init(dev);
6942 dev->mode_config.min_width = 0;
6943 dev->mode_config.min_height = 0;
6945 dev->mode_config.preferred_depth = 24;
6946 dev->mode_config.prefer_shadow = 1;
6948 dev->mode_config.funcs = &intel_mode_funcs;
6950 intel_init_quirks(dev);
6954 intel_prepare_ddi(dev);
6956 intel_init_display(dev);
6959 dev->mode_config.max_width = 2048;
6960 dev->mode_config.max_height = 2048;
6961 } else if (IS_GEN3(dev)) {
6962 dev->mode_config.max_width = 4096;
6963 dev->mode_config.max_height = 4096;
6965 dev->mode_config.max_width = 8192;
6966 dev->mode_config.max_height = 8192;
6968 dev->mode_config.fb_base = dev->agp->base;
6970 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6971 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6973 for (i = 0; i < dev_priv->num_pipe; i++) {
6974 intel_crtc_init(dev, i);
6975 ret = intel_plane_init(dev, i);
6977 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6980 intel_pch_pll_init(dev);
6982 /* Just disable it once at startup */
6983 i915_disable_vga(dev);
6984 intel_setup_outputs(dev);
6986 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6987 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6988 (unsigned long)dev);
6991 void intel_modeset_gem_init(struct drm_device *dev)
6993 intel_modeset_init_hw(dev);
6995 intel_setup_overlay(dev);
6998 void intel_modeset_cleanup(struct drm_device *dev)
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7001 struct drm_crtc *crtc;
7002 struct intel_crtc *intel_crtc;
7004 drm_kms_helper_poll_fini(dev);
7005 mutex_lock(&dev->struct_mutex);
7007 intel_unregister_dsm_handler();
7010 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7011 /* Skip inactive CRTCs */
7015 intel_crtc = to_intel_crtc(crtc);
7016 intel_increase_pllclock(crtc);
7019 intel_disable_fbc(dev);
7021 if (IS_IRONLAKE_M(dev))
7022 ironlake_disable_drps(dev);
7023 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
7024 gen6_disable_rps(dev);
7026 if (IS_IRONLAKE_M(dev))
7027 ironlake_disable_rc6(dev);
7029 if (IS_VALLEYVIEW(dev))
7032 mutex_unlock(&dev->struct_mutex);
7034 /* Disable the irq before mode object teardown, for the irq might
7035 * enqueue unpin/hotplug work. */
7036 drm_irq_uninstall(dev);
7037 cancel_work_sync(&dev_priv->hotplug_work);
7038 cancel_work_sync(&dev_priv->rps_work);
7040 /* flush any delayed tasks or pending work */
7041 flush_scheduled_work();
7043 /* Shut off idle work before the crtcs get freed. */
7044 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7045 intel_crtc = to_intel_crtc(crtc);
7046 del_timer_sync(&intel_crtc->idle_timer);
7048 del_timer_sync(&dev_priv->idle_timer);
7049 cancel_work_sync(&dev_priv->idle_work);
7051 drm_mode_config_cleanup(dev);
7055 * Return which encoder is currently attached for connector.
7057 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7059 return &intel_attached_encoder(connector)->base;
7062 void intel_connector_attach_encoder(struct intel_connector *connector,
7063 struct intel_encoder *encoder)
7065 connector->encoder = encoder;
7066 drm_mode_connector_attach_encoder(&connector->base,
7071 * set vga decode state - true == enable VGA decode
7073 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7075 struct drm_i915_private *dev_priv = dev->dev_private;
7078 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7080 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7082 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7083 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7087 #ifdef CONFIG_DEBUG_FS
7088 #include <linux/seq_file.h>
7090 struct intel_display_error_state {
7091 struct intel_cursor_error_state {
7098 struct intel_pipe_error_state {
7110 struct intel_plane_error_state {
7121 struct intel_display_error_state *
7122 intel_display_capture_error_state(struct drm_device *dev)
7124 drm_i915_private_t *dev_priv = dev->dev_private;
7125 struct intel_display_error_state *error;
7128 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7132 for (i = 0; i < 2; i++) {
7133 error->cursor[i].control = I915_READ(CURCNTR(i));
7134 error->cursor[i].position = I915_READ(CURPOS(i));
7135 error->cursor[i].base = I915_READ(CURBASE(i));
7137 error->plane[i].control = I915_READ(DSPCNTR(i));
7138 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7139 error->plane[i].size = I915_READ(DSPSIZE(i));
7140 error->plane[i].pos = I915_READ(DSPPOS(i));
7141 error->plane[i].addr = I915_READ(DSPADDR(i));
7142 if (INTEL_INFO(dev)->gen >= 4) {
7143 error->plane[i].surface = I915_READ(DSPSURF(i));
7144 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7147 error->pipe[i].conf = I915_READ(PIPECONF(i));
7148 error->pipe[i].source = I915_READ(PIPESRC(i));
7149 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7150 error->pipe[i].hblank = I915_READ(HBLANK(i));
7151 error->pipe[i].hsync = I915_READ(HSYNC(i));
7152 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7153 error->pipe[i].vblank = I915_READ(VBLANK(i));
7154 error->pipe[i].vsync = I915_READ(VSYNC(i));
7161 intel_display_print_error_state(struct seq_file *m,
7162 struct drm_device *dev,
7163 struct intel_display_error_state *error)
7167 for (i = 0; i < 2; i++) {
7168 seq_printf(m, "Pipe [%d]:\n", i);
7169 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7170 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7171 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7172 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7173 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7174 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7175 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7176 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7178 seq_printf(m, "Plane [%d]:\n", i);
7179 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7180 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7181 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7182 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7183 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7184 if (INTEL_INFO(dev)->gen >= 4) {
7185 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7186 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7189 seq_printf(m, "Cursor [%d]:\n", i);
7190 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7191 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7192 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);