drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  89
  90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  91                                 struct intel_crtc_state *pipe_config);
  92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  93                                    struct intel_crtc_state *pipe_config);
  94
  95 static int intel_framebuffer_init(struct drm_device *dev,
  96                                   struct intel_framebuffer *ifb,
  97                                   struct drm_mode_fb_cmd2 *mode_cmd,
  98                                   struct drm_i915_gem_object *obj);
  99 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 114         struct intel_crtc_state *crtc_state);
 115 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 116                            int num_connectors);
 117 static void skylake_pfit_enable(struct intel_crtc *crtc);
 118 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 119 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 120 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 121
 122 typedef struct {
 123         int     min, max;
 124 } intel_range_t;
 125
 126 typedef struct {
 127         int     dot_limit;
 128         int     p2_slow, p2_fast;
 129 } intel_p2_t;
 130
 131 typedef struct intel_limit intel_limit_t;
 132 struct intel_limit {
 133         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 134         intel_p2_t          p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 152                                   const char *name, u32 reg)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         if (dev_priv->hpll_freq == 0)
 158                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 171 }
 172
 173 int
 174 intel_pch_rawclk(struct drm_device *dev)
 175 {
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177
 178         WARN_ON(!HAS_PCH_SPLIT(dev));
 179
 180         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 181 }
 182
 183 /* hrawclock is 1/4 the FSB frequency */
 184 int intel_hrawclk(struct drm_device *dev)
 185 {
 186         struct drm_i915_private *dev_priv = dev->dev_private;
 187         uint32_t clkcfg;
 188
 189         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 190         if (IS_VALLEYVIEW(dev))
 191                 return 200;
 192
 193         clkcfg = I915_READ(CLKCFG);
 194         switch (clkcfg & CLKCFG_FSB_MASK) {
 195         case CLKCFG_FSB_400:
 196                 return 100;
 197         case CLKCFG_FSB_533:
 198                 return 133;
 199         case CLKCFG_FSB_667:
 200                 return 166;
 201         case CLKCFG_FSB_800:
 202                 return 200;
 203         case CLKCFG_FSB_1067:
 204                 return 266;
 205         case CLKCFG_FSB_1333:
 206                 return 333;
 207         /* these two are just a guess; one of them might be right */
 208         case CLKCFG_FSB_1600:
 209         case CLKCFG_FSB_1600_ALT:
 210                 return 400;
 211         default:
 212                 return 133;
 213         }
 214 }
 215
 216 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 217 {
 218         if (!IS_VALLEYVIEW(dev_priv))
 219                 return;
 220
 221         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 222                                                       CCK_CZ_CLOCK_CONTROL);
 223
 224         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 225 }
 226
 227 static inline u32 /* units of 100MHz */
 228 intel_fdi_link_freq(struct drm_device *dev)
 229 {
 230         if (IS_GEN5(dev)) {
 231                 struct drm_i915_private *dev_priv = dev->dev_private;
 232                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 233         } else
 234                 return 27;
 235 }
 236
 237 static const intel_limit_t intel_limits_i8xx_dac = {
 238         .dot = { .min = 25000, .max = 350000 },
 239         .vco = { .min = 908000, .max = 1512000 },
 240         .n = { .min = 2, .max = 16 },
 241         .m = { .min = 96, .max = 140 },
 242         .m1 = { .min = 18, .max = 26 },
 243         .m2 = { .min = 6, .max = 16 },
 244         .p = { .min = 4, .max = 128 },
 245         .p1 = { .min = 2, .max = 33 },
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 4, .p2_fast = 2 },
 248 };
 249
 250 static const intel_limit_t intel_limits_i8xx_dvo = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 908000, .max = 1512000 },
 253         .n = { .min = 2, .max = 16 },
 254         .m = { .min = 96, .max = 140 },
 255         .m1 = { .min = 18, .max = 26 },
 256         .m2 = { .min = 6, .max = 16 },
 257         .p = { .min = 4, .max = 128 },
 258         .p1 = { .min = 2, .max = 33 },
 259         .p2 = { .dot_limit = 165000,
 260                 .p2_slow = 4, .p2_fast = 4 },
 261 };
 262
 263 static const intel_limit_t intel_limits_i8xx_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 1, .max = 6 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 14, .p2_fast = 7 },
 274 };
 275
 276 static const intel_limit_t intel_limits_i9xx_sdvo = {
 277         .dot = { .min = 20000, .max = 400000 },
 278         .vco = { .min = 1400000, .max = 2800000 },
 279         .n = { .min = 1, .max = 6 },
 280         .m = { .min = 70, .max = 120 },
 281         .m1 = { .min = 8, .max = 18 },
 282         .m2 = { .min = 3, .max = 7 },
 283         .p = { .min = 5, .max = 80 },
 284         .p1 = { .min = 1, .max = 8 },
 285         .p2 = { .dot_limit = 200000,
 286                 .p2_slow = 10, .p2_fast = 5 },
 287 };
 288
 289 static const intel_limit_t intel_limits_i9xx_lvds = {
 290         .dot = { .min = 20000, .max = 400000 },
 291         .vco = { .min = 1400000, .max = 2800000 },
 292         .n = { .min = 1, .max = 6 },
 293         .m = { .min = 70, .max = 120 },
 294         .m1 = { .min = 8, .max = 18 },
 295         .m2 = { .min = 3, .max = 7 },
 296         .p = { .min = 7, .max = 98 },
 297         .p1 = { .min = 1, .max = 8 },
 298         .p2 = { .dot_limit = 112000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302
 303 static const intel_limit_t intel_limits_g4x_sdvo = {
 304         .dot = { .min = 25000, .max = 270000 },
 305         .vco = { .min = 1750000, .max = 3500000},
 306         .n = { .min = 1, .max = 4 },
 307         .m = { .min = 104, .max = 138 },
 308         .m1 = { .min = 17, .max = 23 },
 309         .m2 = { .min = 5, .max = 11 },
 310         .p = { .min = 10, .max = 30 },
 311         .p1 = { .min = 1, .max = 3},
 312         .p2 = { .dot_limit = 270000,
 313                 .p2_slow = 10,
 314                 .p2_fast = 10
 315         },
 316 };
 317
 318 static const intel_limit_t intel_limits_g4x_hdmi = {
 319         .dot = { .min = 22000, .max = 400000 },
 320         .vco = { .min = 1750000, .max = 3500000},
 321         .n = { .min = 1, .max = 4 },
 322         .m = { .min = 104, .max = 138 },
 323         .m1 = { .min = 16, .max = 23 },
 324         .m2 = { .min = 5, .max = 11 },
 325         .p = { .min = 5, .max = 80 },
 326         .p1 = { .min = 1, .max = 8},
 327         .p2 = { .dot_limit = 165000,
 328                 .p2_slow = 10, .p2_fast = 5 },
 329 };
 330
 331 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 332         .dot = { .min = 20000, .max = 115000 },
 333         .vco = { .min = 1750000, .max = 3500000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 104, .max = 138 },
 336         .m1 = { .min = 17, .max = 23 },
 337         .m2 = { .min = 5, .max = 11 },
 338         .p = { .min = 28, .max = 112 },
 339         .p1 = { .min = 2, .max = 8 },
 340         .p2 = { .dot_limit = 0,
 341                 .p2_slow = 14, .p2_fast = 14
 342         },
 343 };
 344
 345 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 346         .dot = { .min = 80000, .max = 224000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 14, .max = 42 },
 353         .p1 = { .min = 2, .max = 6 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 7, .p2_fast = 7
 356         },
 357 };
 358
 359 static const intel_limit_t intel_limits_pineview_sdvo = {
 360         .dot = { .min = 20000, .max = 400000},
 361         .vco = { .min = 1700000, .max = 3500000 },
 362         /* Pineview's Ncounter is a ring counter */
 363         .n = { .min = 3, .max = 6 },
 364         .m = { .min = 2, .max = 256 },
 365         /* Pineview only has one combined m divider, which we treat as m2. */
 366         .m1 = { .min = 0, .max = 0 },
 367         .m2 = { .min = 0, .max = 254 },
 368         .p = { .min = 5, .max = 80 },
 369         .p1 = { .min = 1, .max = 8 },
 370         .p2 = { .dot_limit = 200000,
 371                 .p2_slow = 10, .p2_fast = 5 },
 372 };
 373
 374 static const intel_limit_t intel_limits_pineview_lvds = {
 375         .dot = { .min = 20000, .max = 400000 },
 376         .vco = { .min = 1700000, .max = 3500000 },
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         .m1 = { .min = 0, .max = 0 },
 380         .m2 = { .min = 0, .max = 254 },
 381         .p = { .min = 7, .max = 112 },
 382         .p1 = { .min = 1, .max = 8 },
 383         .p2 = { .dot_limit = 112000,
 384                 .p2_slow = 14, .p2_fast = 14 },
 385 };
 386
 387 /* Ironlake / Sandybridge
 388  *
 389  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 390  * the range value for them is (actual_value - 2).
 391  */
 392 static const intel_limit_t intel_limits_ironlake_dac = {
 393         .dot = { .min = 25000, .max = 350000 },
 394         .vco = { .min = 1760000, .max = 3510000 },
 395         .n = { .min = 1, .max = 5 },
 396         .m = { .min = 79, .max = 127 },
 397         .m1 = { .min = 12, .max = 22 },
 398         .m2 = { .min = 5, .max = 9 },
 399         .p = { .min = 5, .max = 80 },
 400         .p1 = { .min = 1, .max = 8 },
 401         .p2 = { .dot_limit = 225000,
 402                 .p2_slow = 10, .p2_fast = 5 },
 403 };
 404
 405 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 406         .dot = { .min = 25000, .max = 350000 },
 407         .vco = { .min = 1760000, .max = 3510000 },
 408         .n = { .min = 1, .max = 3 },
 409         .m = { .min = 79, .max = 118 },
 410         .m1 = { .min = 12, .max = 22 },
 411         .m2 = { .min = 5, .max = 9 },
 412         .p = { .min = 28, .max = 112 },
 413         .p1 = { .min = 2, .max = 8 },
 414         .p2 = { .dot_limit = 225000,
 415                 .p2_slow = 14, .p2_fast = 14 },
 416 };
 417
 418 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 3 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 14, .max = 56 },
 426         .p1 = { .min = 2, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 7, .p2_fast = 7 },
 429 };
 430
 431 /* LVDS 100mhz refclk limits. */
 432 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 2 },
 436         .m = { .min = 79, .max = 126 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 28, .max = 112 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 14, .p2_fast = 14 },
 443 };
 444
 445 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 446         .dot = { .min = 25000, .max = 350000 },
 447         .vco = { .min = 1760000, .max = 3510000 },
 448         .n = { .min = 1, .max = 3 },
 449         .m = { .min = 79, .max = 126 },
 450         .m1 = { .min = 12, .max = 22 },
 451         .m2 = { .min = 5, .max = 9 },
 452         .p = { .min = 14, .max = 42 },
 453         .p1 = { .min = 2, .max = 6 },
 454         .p2 = { .dot_limit = 225000,
 455                 .p2_slow = 7, .p2_fast = 7 },
 456 };
 457
 458 static const intel_limit_t intel_limits_vlv = {
 459          /*
 460           * These are the data rate limits (measured in fast clocks)
 461           * since those are the strictest limits we have. The fast
 462           * clock and actual rate limits are more relaxed, so checking
 463           * them would make no difference.
 464           */
 465         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 466         .vco = { .min = 4000000, .max = 6000000 },
 467         .n = { .min = 1, .max = 7 },
 468         .m1 = { .min = 2, .max = 3 },
 469         .m2 = { .min = 11, .max = 156 },
 470         .p1 = { .min = 2, .max = 3 },
 471         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 472 };
 473
 474 static const intel_limit_t intel_limits_chv = {
 475         /*
 476          * These are the data rate limits (measured in fast clocks)
 477          * since those are the strictest limits we have.  The fast
 478          * clock and actual rate limits are more relaxed, so checking
 479          * them would make no difference.
 480          */
 481         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 482         .vco = { .min = 4800000, .max = 6480000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 486         .p1 = { .min = 2, .max = 4 },
 487         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 488 };
 489
 490 static const intel_limit_t intel_limits_bxt = {
 491         /* FIXME: find real dot limits */
 492         .dot = { .min = 0, .max = INT_MAX },
 493         .vco = { .min = 4800000, .max = 6700000 },
 494         .n = { .min = 1, .max = 1 },
 495         .m1 = { .min = 2, .max = 2 },
 496         /* FIXME: find real m2 limits */
 497         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 498         .p1 = { .min = 2, .max = 4 },
 499         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 500 };
 501
 502 static bool
 503 needs_modeset(struct drm_crtc_state *state)
 504 {
 505         return drm_atomic_crtc_needs_modeset(state);
 506 }
 507
 508 /**
 509  * Returns whether any output on the specified pipe is of the specified type
 510  */
 511 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 512 {
 513         struct drm_device *dev = crtc->base.dev;
 514         struct intel_encoder *encoder;
 515
 516         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 517                 if (encoder->type == type)
 518                         return true;
 519
 520         return false;
 521 }
 522
 523 /**
 524  * Returns whether any output on the specified pipe will have the specified
 525  * type after a staged modeset is complete, i.e., the same as
 526  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 527  * encoder->crtc.
 528  */
 529 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 530                                       int type)
 531 {
 532         struct drm_atomic_state *state = crtc_state->base.state;
 533         struct drm_connector *connector;
 534         struct drm_connector_state *connector_state;
 535         struct intel_encoder *encoder;
 536         int i, num_connectors = 0;
 537
 538         for_each_connector_in_state(state, connector, connector_state, i) {
 539                 if (connector_state->crtc != crtc_state->base.crtc)
 540                         continue;
 541
 542                 num_connectors++;
 543
 544                 encoder = to_intel_encoder(connector_state->best_encoder);
 545                 if (encoder->type == type)
 546                         return true;
 547         }
 548
 549         WARN_ON(num_connectors == 0);
 550
 551         return false;
 552 }
 553
 554 static const intel_limit_t *
 555 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 556 {
 557         struct drm_device *dev = crtc_state->base.crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 561                 if (intel_is_dual_link_lvds(dev)) {
 562                         if (refclk == 100000)
 563                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 564                         else
 565                                 limit = &intel_limits_ironlake_dual_lvds;
 566                 } else {
 567                         if (refclk == 100000)
 568                                 limit = &intel_limits_ironlake_single_lvds_100m;
 569                         else
 570                                 limit = &intel_limits_ironlake_single_lvds;
 571                 }
 572         } else
 573                 limit = &intel_limits_ironlake_dac;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *
 579 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 580 {
 581         struct drm_device *dev = crtc_state->base.crtc->dev;
 582         const intel_limit_t *limit;
 583
 584         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 585                 if (intel_is_dual_link_lvds(dev))
 586                         limit = &intel_limits_g4x_dual_channel_lvds;
 587                 else
 588                         limit = &intel_limits_g4x_single_channel_lvds;
 589         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 590                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 591                 limit = &intel_limits_g4x_hdmi;
 592         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 593                 limit = &intel_limits_g4x_sdvo;
 594         } else /* The option is for other outputs */
 595                 limit = &intel_limits_i9xx_sdvo;
 596
 597         return limit;
 598 }
 599
 600 static const intel_limit_t *
 601 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 602 {
 603         struct drm_device *dev = crtc_state->base.crtc->dev;
 604         const intel_limit_t *limit;
 605
 606         if (IS_BROXTON(dev))
 607                 limit = &intel_limits_bxt;
 608         else if (HAS_PCH_SPLIT(dev))
 609                 limit = intel_ironlake_limit(crtc_state, refclk);
 610         else if (IS_G4X(dev)) {
 611                 limit = intel_g4x_limit(crtc_state);
 612         } else if (IS_PINEVIEW(dev)) {
 613                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 614                         limit = &intel_limits_pineview_lvds;
 615                 else
 616                         limit = &intel_limits_pineview_sdvo;
 617         } else if (IS_CHERRYVIEW(dev)) {
 618                 limit = &intel_limits_chv;
 619         } else if (IS_VALLEYVIEW(dev)) {
 620                 limit = &intel_limits_vlv;
 621         } else if (!IS_GEN2(dev)) {
 622                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 623                         limit = &intel_limits_i9xx_lvds;
 624                 else
 625                         limit = &intel_limits_i9xx_sdvo;
 626         } else {
 627                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 628                         limit = &intel_limits_i8xx_lvds;
 629                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 630                         limit = &intel_limits_i8xx_dvo;
 631                 else
 632                         limit = &intel_limits_i8xx_dac;
 633         }
 634         return limit;
 635 }
 636
 637 /*
 638  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 639  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 640  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 641  * The helpers' return value is the rate of the clock that is fed to the
 642  * display engine's pipe which can be the above fast dot clock rate or a
 643  * divided-down version of it.
 644  */
 645 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 646 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 647 {
 648         clock->m = clock->m2 + 2;
 649         clock->p = clock->p1 * clock->p2;
 650         if (WARN_ON(clock->n == 0 || clock->p == 0))
 651                 return 0;
 652         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 653         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 654
 655         return clock->dot;
 656 }
 657
 658 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 659 {
 660         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 661 }
 662
 663 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 664 {
 665         clock->m = i9xx_dpll_compute_m(clock);
 666         clock->p = clock->p1 * clock->p2;
 667         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 668                 return 0;
 669         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 670         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 671
 672         return clock->dot;
 673 }
 674
 675 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 676 {
 677         clock->m = clock->m1 * clock->m2;
 678         clock->p = clock->p1 * clock->p2;
 679         if (WARN_ON(clock->n == 0 || clock->p == 0))
 680                 return 0;
 681         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 682         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 683
 684         return clock->dot / 5;
 685 }
 686
 687 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 688 {
 689         clock->m = clock->m1 * clock->m2;
 690         clock->p = clock->p1 * clock->p2;
 691         if (WARN_ON(clock->n == 0 || clock->p == 0))
 692                 return 0;
 693         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 694                         clock->n << 22);
 695         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 696
 697         return clock->dot / 5;
 698 }
 699
 700 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 701 /**
 702  * Returns whether the given set of divisors are valid for a given refclk with
 703  * the given connectors.
 704  */
 705
 706 static bool intel_PLL_is_valid(struct drm_device *dev,
 707                                const intel_limit_t *limit,
 708                                const intel_clock_t *clock)
 709 {
 710         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 711                 INTELPllInvalid("n out of range\n");
 712         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 713                 INTELPllInvalid("p1 out of range\n");
 714         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 715                 INTELPllInvalid("m2 out of range\n");
 716         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 717                 INTELPllInvalid("m1 out of range\n");
 718
 719         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 720                 if (clock->m1 <= clock->m2)
 721                         INTELPllInvalid("m1 <= m2\n");
 722
 723         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 724                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 725                         INTELPllInvalid("p out of range\n");
 726                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 727                         INTELPllInvalid("m out of range\n");
 728         }
 729
 730         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 731                 INTELPllInvalid("vco out of range\n");
 732         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 733          * connector, etc., rather than just a single range.
 734          */
 735         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 736                 INTELPllInvalid("dot out of range\n");
 737
 738         return true;
 739 }
 740
 741 static int
 742 i9xx_select_p2_div(const intel_limit_t *limit,
 743                    const struct intel_crtc_state *crtc_state,
 744                    int target)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747
 748         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 749                 /*
 750                  * For LVDS just rely on its current settings for dual-channel.
 751                  * We haven't figured out how to reliably set up different
 752                  * single/dual channel state, if we even can.
 753                  */
 754                 if (intel_is_dual_link_lvds(dev))
 755                         return limit->p2.p2_fast;
 756                 else
 757                         return limit->p2.p2_slow;
 758         } else {
 759                 if (target < limit->p2.dot_limit)
 760                         return limit->p2.p2_slow;
 761                 else
 762                         return limit->p2.p2_fast;
 763         }
 764 }
 765
 766 static bool
 767 i9xx_find_best_dpll(const intel_limit_t *limit,
 768                     struct intel_crtc_state *crtc_state,
 769                     int target, int refclk, intel_clock_t *match_clock,
 770                     intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->base.crtc->dev;
 773         intel_clock_t clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         if (clock.m2 >= clock.m1)
 785                                 break;
 786                         for (clock.n = limit->n.min;
 787                              clock.n <= limit->n.max; clock.n++) {
 788                                 for (clock.p1 = limit->p1.min;
 789                                         clock.p1 <= limit->p1.max; clock.p1++) {
 790                                         int this_err;
 791
 792                                         i9xx_calc_dpll_params(refclk, &clock);
 793                                         if (!intel_PLL_is_valid(dev, limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 static bool
 814 pnv_find_best_dpll(const intel_limit_t *limit,
 815                    struct intel_crtc_state *crtc_state,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc_state->base.crtc->dev;
 820         intel_clock_t clock;
 821         int err = target;
 822
 823         memset(best_clock, 0, sizeof(*best_clock));
 824
 825         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 826
 827         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 828              clock.m1++) {
 829                 for (clock.m2 = limit->m2.min;
 830                      clock.m2 <= limit->m2.max; clock.m2++) {
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         pnv_calc_dpll_params(refclk, &clock);
 838                                         if (!intel_PLL_is_valid(dev, limit,
 839                                                                 &clock))
 840                                                 continue;
 841                                         if (match_clock &&
 842                                             clock.p != match_clock->p)
 843                                                 continue;
 844
 845                                         this_err = abs(clock.dot - target);
 846                                         if (this_err < err) {
 847                                                 *best_clock = clock;
 848                                                 err = this_err;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854
 855         return (err != target);
 856 }
 857
 858 static bool
 859 g4x_find_best_dpll(const intel_limit_t *limit,
 860                    struct intel_crtc_state *crtc_state,
 861                    int target, int refclk, intel_clock_t *match_clock,
 862                    intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc_state->base.crtc->dev;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found = false;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870
 871         memset(best_clock, 0, sizeof(*best_clock));
 872
 873         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 874
 875         max_n = limit->n.max;
 876         /* based on hardware requirement, prefer smaller n to precision */
 877         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 878                 /* based on hardware requirement, prefere larger m1,m2 */
 879                 for (clock.m1 = limit->m1.max;
 880                      clock.m1 >= limit->m1.min; clock.m1--) {
 881                         for (clock.m2 = limit->m2.max;
 882                              clock.m2 >= limit->m2.min; clock.m2--) {
 883                                 for (clock.p1 = limit->p1.max;
 884                                      clock.p1 >= limit->p1.min; clock.p1--) {
 885                                         int this_err;
 886
 887                                         i9xx_calc_dpll_params(refclk, &clock);
 888                                         if (!intel_PLL_is_valid(dev, limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         this_err = abs(clock.dot - target);
 893                                         if (this_err < err_most) {
 894                                                 *best_clock = clock;
 895                                                 err_most = this_err;
 896                                                 max_n = clock.n;
 897                                                 found = true;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903         return found;
 904 }
 905
 906 /*
 907  * Check if the calculated PLL configuration is more optimal compared to the
 908  * best configuration and error found so far. Return the calculated error.
 909  */
 910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 911                                const intel_clock_t *calculated_clock,
 912                                const intel_clock_t *best_clock,
 913                                unsigned int best_error_ppm,
 914                                unsigned int *error_ppm)
 915 {
 916         /*
 917          * For CHV ignore the error and consider only the P value.
 918          * Prefer a bigger P value based on HW requirements.
 919          */
 920         if (IS_CHERRYVIEW(dev)) {
 921                 *error_ppm = 0;
 922
 923                 return calculated_clock->p > best_clock->p;
 924         }
 925
 926         if (WARN_ON_ONCE(!target_freq))
 927                 return false;
 928
 929         *error_ppm = div_u64(1000000ULL *
 930                                 abs(target_freq - calculated_clock->dot),
 931                              target_freq);
 932         /*
 933          * Prefer a better P value over a better (smaller) error if the error
 934          * is small. Ensure this preference for future configurations too by
 935          * setting the error to 0.
 936          */
 937         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 938                 *error_ppm = 0;
 939
 940                 return true;
 941         }
 942
 943         return *error_ppm + 10 < best_error_ppm;
 944 }
 945
 946 static bool
 947 vlv_find_best_dpll(const intel_limit_t *limit,
 948                    struct intel_crtc_state *crtc_state,
 949                    int target, int refclk, intel_clock_t *match_clock,
 950                    intel_clock_t *best_clock)
 951 {
 952         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 953         struct drm_device *dev = crtc->base.dev;
 954         intel_clock_t clock;
 955         unsigned int bestppm = 1000000;
 956         /* min update 19.2 MHz */
 957         int max_n = min(limit->n.max, refclk / 19200);
 958         bool found = false;
 959
 960         target *= 5; /* fast clock */
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963
 964         /* based on hardware requirement, prefer smaller n to precision */
 965         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 966                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 967                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 968                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 969                                 clock.p = clock.p1 * clock.p2;
 970                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 971                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 972                                         unsigned int ppm;
 973
 974                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 975                                                                      refclk * clock.m1);
 976
 977                                         vlv_calc_dpll_params(refclk, &clock);
 978
 979                                         if (!intel_PLL_is_valid(dev, limit,
 980                                                                 &clock))
 981                                                 continue;
 982
 983                                         if (!vlv_PLL_is_optimal(dev, target,
 984                                                                 &clock,
 985                                                                 best_clock,
 986                                                                 bestppm, &ppm))
 987                                                 continue;
 988
 989                                         *best_clock = clock;
 990                                         bestppm = ppm;
 991                                         found = true;
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return found;
 998 }
 999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002                    struct intel_crtc_state *crtc_state,
1003                    int target, int refclk, intel_clock_t *match_clock,
1004                    intel_clock_t *best_clock)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007         struct drm_device *dev = crtc->base.dev;
1008         unsigned int best_error_ppm;
1009         intel_clock_t clock;
1010         uint64_t m2;
1011         int found = false;
1012
1013         memset(best_clock, 0, sizeof(*best_clock));
1014         best_error_ppm = 1000000;
1015
1016         /*
1017          * Based on hardware doc, the n always set to 1, and m1 always
1018          * set to 2.  If requires to support 200Mhz refclk, we need to
1019          * revisit this because n may not 1 anymore.
1020          */
1021         clock.n = 1, clock.m1 = 2;
1022         target *= 5;    /* fast clock */
1023
1024         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025                 for (clock.p2 = limit->p2.p2_fast;
1026                                 clock.p2 >= limit->p2.p2_slow;
1027                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028                         unsigned int error_ppm;
1029
1030                         clock.p = clock.p1 * clock.p2;
1031
1032                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033                                         clock.n) << 22, refclk * clock.m1);
1034
1035                         if (m2 > INT_MAX/clock.m1)
1036                                 continue;
1037
1038                         clock.m2 = m2;
1039
1040                         chv_calc_dpll_params(refclk, &clock);
1041
1042                         if (!intel_PLL_is_valid(dev, limit, &clock))
1043                                 continue;
1044
1045                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046                                                 best_error_ppm, &error_ppm))
1047                                 continue;
1048
1049                         *best_clock = clock;
1050                         best_error_ppm = error_ppm;
1051                         found = true;
1052                 }
1053         }
1054
1055         return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059                         intel_clock_t *best_clock)
1060 {
1061         int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064                                   target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071         /* Be paranoid as we can arrive here with only partial
1072          * state retrieved from the hardware during setup.
1073          *
1074          * We can ditch the adjusted_mode.crtc_clock check as soon
1075          * as Haswell has gained clock readout/fastboot support.
1076          *
1077          * We can ditch the crtc->primary->fb check as soon as we can
1078          * properly reconstruct framebuffers.
1079          *
1080          * FIXME: The intel_crtc->active here should be switched to
1081          * crtc->state->active once we have proper CRTC states wired up
1082          * for atomic.
1083          */
1084         return intel_crtc->active && crtc->primary->state->fb &&
1085                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089                                              enum pipe pipe)
1090 {
1091         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094         return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         i915_reg_t reg = PIPEDSL(pipe);
1101         u32 line1, line2;
1102         u32 line_mask;
1103
1104         if (IS_GEN2(dev))
1105                 line_mask = DSL_LINEMASK_GEN2;
1106         else
1107                 line_mask = DSL_LINEMASK_GEN3;
1108
1109         line1 = I915_READ(reg) & line_mask;
1110         msleep(5);
1111         line2 = I915_READ(reg) & line_mask;
1112
1113         return line1 == line2;
1114 }
1115
1116 /*
1117  * intel_wait_for_pipe_off - wait for pipe to turn off
1118  * @crtc: crtc whose pipe to wait for
1119  *
1120  * After disabling a pipe, we can't wait for vblank in the usual way,
1121  * spinning on the vblank interrupt status bit, since we won't actually
1122  * see an interrupt when the pipe is disabled.
1123  *
1124  * On Gen4 and above:
1125  *   wait for the pipe register state bit to turn off
1126  *
1127  * Otherwise:
1128  *   wait for the display line value to settle (it usually
1129  *   ends up stopping at the start of the next frame).
1130  *
1131  */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134         struct drm_device *dev = crtc->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137         enum pipe pipe = crtc->pipe;
1138
1139         if (INTEL_INFO(dev)->gen >= 4) {
1140                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142                 /* Wait for the Pipe State to go off */
1143                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144                              100))
1145                         WARN(1, "pipe_off wait timed out\n");
1146         } else {
1147                 /* Wait for the display line to settle */
1148                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149                         WARN(1, "pipe_off wait timed out\n");
1150         }
1151 }
1152
1153 static const char *state_string(bool enabled)
1154 {
1155         return enabled ? "on" : "off";
1156 }
1157
1158 /* Only for pre-ILK configs */
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160                 enum pipe pipe, bool state)
1161 {
1162         u32 val;
1163         bool cur_state;
1164
1165         val = I915_READ(DPLL(pipe));
1166         cur_state = !!(val & DPLL_VCO_ENABLE);
1167         I915_STATE_WARN(cur_state != state,
1168              "PLL state assertion failure (expected %s, current %s)\n",
1169              state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175         u32 val;
1176         bool cur_state;
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180         mutex_unlock(&dev_priv->sb_lock);
1181
1182         cur_state = val & DSI_PLL_VCO_EN;
1183         I915_STATE_WARN(cur_state != state,
1184              "DSI PLL state assertion failure (expected %s, current %s)\n",
1185              state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195         if (crtc->config->shared_dpll < 0)
1196                 return NULL;
1197
1198         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203                         struct intel_shared_dpll *pll,
1204                         bool state)
1205 {
1206         bool cur_state;
1207         struct intel_dpll_hw_state hw_state;
1208
1209         if (WARN (!pll,
1210                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1211                 return;
1212
1213         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214         I915_STATE_WARN(cur_state != state,
1215              "%s assertion failure (expected %s, current %s)\n",
1216              pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220                           enum pipe pipe, bool state)
1221 {
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         if (HAS_DDI(dev_priv->dev)) {
1227                 /* DDI does not have a specific FDI_TX register */
1228                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1229                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1230         } else {
1231                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1232                 cur_state = !!(val & FDI_TX_ENABLE);
1233         }
1234         I915_STATE_WARN(cur_state != state,
1235              "FDI TX state assertion failure (expected %s, current %s)\n",
1236              state_string(state), state_string(cur_state));
1237 }
1238 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1239 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1240
1241 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1242                           enum pipe pipe, bool state)
1243 {
1244         u32 val;
1245         bool cur_state;
1246
1247         val = I915_READ(FDI_RX_CTL(pipe));
1248         cur_state = !!(val & FDI_RX_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX state assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1254 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1255
1256 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1257                                       enum pipe pipe)
1258 {
1259         u32 val;
1260
1261         /* ILK FDI PLL is always enabled */
1262         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1263                 return;
1264
1265         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1266         if (HAS_DDI(dev_priv->dev))
1267                 return;
1268
1269         val = I915_READ(FDI_TX_CTL(pipe));
1270         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 }
1272
1273 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1274                        enum pipe pipe, bool state)
1275 {
1276         u32 val;
1277         bool cur_state;
1278
1279         val = I915_READ(FDI_RX_CTL(pipe));
1280         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1281         I915_STATE_WARN(cur_state != state,
1282              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1283              state_string(state), state_string(cur_state));
1284 }
1285
1286 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1287                            enum pipe pipe)
1288 {
1289         struct drm_device *dev = dev_priv->dev;
1290         i915_reg_t pp_reg;
1291         u32 val;
1292         enum pipe panel_pipe = PIPE_A;
1293         bool locked = true;
1294
1295         if (WARN_ON(HAS_DDI(dev)))
1296                 return;
1297
1298         if (HAS_PCH_SPLIT(dev)) {
1299                 u32 port_sel;
1300
1301                 pp_reg = PCH_PP_CONTROL;
1302                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1303
1304                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1305                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1306                         panel_pipe = PIPE_B;
1307                 /* XXX: else fix for eDP */
1308         } else if (IS_VALLEYVIEW(dev)) {
1309                 /* presumably write lock depends on pipe, not port select */
1310                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1311                 panel_pipe = pipe;
1312         } else {
1313                 pp_reg = PP_CONTROL;
1314                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1315                         panel_pipe = PIPE_B;
1316         }
1317
1318         val = I915_READ(pp_reg);
1319         if (!(val & PANEL_POWER_ON) ||
1320             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1321                 locked = false;
1322
1323         I915_STATE_WARN(panel_pipe == pipe && locked,
1324              "panel assertion failure, pipe %c regs locked\n",
1325              pipe_name(pipe));
1326 }
1327
1328 static void assert_cursor(struct drm_i915_private *dev_priv,
1329                           enum pipe pipe, bool state)
1330 {
1331         struct drm_device *dev = dev_priv->dev;
1332         bool cur_state;
1333
1334         if (IS_845G(dev) || IS_I865G(dev))
1335                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1336         else
1337                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1338
1339         I915_STATE_WARN(cur_state != state,
1340              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1341              pipe_name(pipe), state_string(state), state_string(cur_state));
1342 }
1343 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1344 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1345
1346 void assert_pipe(struct drm_i915_private *dev_priv,
1347                  enum pipe pipe, bool state)
1348 {
1349         bool cur_state;
1350         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1351                                                                       pipe);
1352
1353         /* if we need the pipe quirk it must be always on */
1354         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1355             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1356                 state = true;
1357
1358         if (!intel_display_power_is_enabled(dev_priv,
1359                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1360                 cur_state = false;
1361         } else {
1362                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1363                 cur_state = !!(val & PIPECONF_ENABLE);
1364         }
1365
1366         I915_STATE_WARN(cur_state != state,
1367              "pipe %c assertion failure (expected %s, current %s)\n",
1368              pipe_name(pipe), state_string(state), state_string(cur_state));
1369 }
1370
1371 static void assert_plane(struct drm_i915_private *dev_priv,
1372                          enum plane plane, bool state)
1373 {
1374         u32 val;
1375         bool cur_state;
1376
1377         val = I915_READ(DSPCNTR(plane));
1378         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1379         I915_STATE_WARN(cur_state != state,
1380              "plane %c assertion failure (expected %s, current %s)\n",
1381              plane_name(plane), state_string(state), state_string(cur_state));
1382 }
1383
1384 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1385 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1386
1387 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1388                                    enum pipe pipe)
1389 {
1390         struct drm_device *dev = dev_priv->dev;
1391         int i;
1392
1393         /* Primary planes are fixed to pipes on gen4+ */
1394         if (INTEL_INFO(dev)->gen >= 4) {
1395                 u32 val = I915_READ(DSPCNTR(pipe));
1396                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1397                      "plane %c assertion failure, should be disabled but not\n",
1398                      plane_name(pipe));
1399                 return;
1400         }
1401
1402         /* Need to check both planes against the pipe */
1403         for_each_pipe(dev_priv, i) {
1404                 u32 val = I915_READ(DSPCNTR(i));
1405                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1406                         DISPPLANE_SEL_PIPE_SHIFT;
1407                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1408                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1409                      plane_name(i), pipe_name(pipe));
1410         }
1411 }
1412
1413 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1414                                     enum pipe pipe)
1415 {
1416         struct drm_device *dev = dev_priv->dev;
1417         int sprite;
1418
1419         if (INTEL_INFO(dev)->gen >= 9) {
1420                 for_each_sprite(dev_priv, pipe, sprite) {
1421                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1422                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1423                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1424                              sprite, pipe_name(pipe));
1425                 }
1426         } else if (IS_VALLEYVIEW(dev)) {
1427                 for_each_sprite(dev_priv, pipe, sprite) {
1428                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1429                         I915_STATE_WARN(val & SP_ENABLE,
1430                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                              sprite_name(pipe, sprite), pipe_name(pipe));
1432                 }
1433         } else if (INTEL_INFO(dev)->gen >= 7) {
1434                 u32 val = I915_READ(SPRCTL(pipe));
1435                 I915_STATE_WARN(val & SPRITE_ENABLE,
1436                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1437                      plane_name(pipe), pipe_name(pipe));
1438         } else if (INTEL_INFO(dev)->gen >= 5) {
1439                 u32 val = I915_READ(DVSCNTR(pipe));
1440                 I915_STATE_WARN(val & DVS_ENABLE,
1441                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442                      plane_name(pipe), pipe_name(pipe));
1443         }
1444 }
1445
1446 static void assert_vblank_disabled(struct drm_crtc *crtc)
1447 {
1448         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1449                 drm_crtc_vblank_put(crtc);
1450 }
1451
1452 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1453 {
1454         u32 val;
1455         bool enabled;
1456
1457         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1458
1459         val = I915_READ(PCH_DREF_CONTROL);
1460         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1461                             DREF_SUPERSPREAD_SOURCE_MASK));
1462         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1463 }
1464
1465 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1466                                            enum pipe pipe)
1467 {
1468         u32 val;
1469         bool enabled;
1470
1471         val = I915_READ(PCH_TRANSCONF(pipe));
1472         enabled = !!(val & TRANS_ENABLE);
1473         I915_STATE_WARN(enabled,
1474              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1475              pipe_name(pipe));
1476 }
1477
1478 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1479                             enum pipe pipe, u32 port_sel, u32 val)
1480 {
1481         if ((val & DP_PORT_EN) == 0)
1482                 return false;
1483
1484         if (HAS_PCH_CPT(dev_priv->dev)) {
1485                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1486                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487                         return false;
1488         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1489                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1490                         return false;
1491         } else {
1492                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1493                         return false;
1494         }
1495         return true;
1496 }
1497
1498 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1499                               enum pipe pipe, u32 val)
1500 {
1501         if ((val & SDVO_ENABLE) == 0)
1502                 return false;
1503
1504         if (HAS_PCH_CPT(dev_priv->dev)) {
1505                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1506                         return false;
1507         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1508                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & LVDS_PORT_EN) == 0)
1521                 return false;
1522
1523         if (HAS_PCH_CPT(dev_priv->dev)) {
1524                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1525                         return false;
1526         } else {
1527                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1528                         return false;
1529         }
1530         return true;
1531 }
1532
1533 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1534                               enum pipe pipe, u32 val)
1535 {
1536         if ((val & ADPA_DAC_ENABLE) == 0)
1537                 return false;
1538         if (HAS_PCH_CPT(dev_priv->dev)) {
1539                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1540                         return false;
1541         } else {
1542                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1543                         return false;
1544         }
1545         return true;
1546 }
1547
1548 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549                                    enum pipe pipe, i915_reg_t reg,
1550                                    u32 port_sel)
1551 {
1552         u32 val = I915_READ(reg);
1553         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1554              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1555              i915_mmio_reg_offset(reg), pipe_name(pipe));
1556
1557         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1558              && (val & DP_PIPEB_SELECT),
1559              "IBX PCH dp port still using transcoder B\n");
1560 }
1561
1562 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1563                                      enum pipe pipe, i915_reg_t reg)
1564 {
1565         u32 val = I915_READ(reg);
1566         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1567              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1568              i915_mmio_reg_offset(reg), pipe_name(pipe));
1569
1570         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1571              && (val & SDVO_PIPE_B_SELECT),
1572              "IBX PCH hdmi port still using transcoder B\n");
1573 }
1574
1575 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1576                                       enum pipe pipe)
1577 {
1578         u32 val;
1579
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1581         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1582         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1583
1584         val = I915_READ(PCH_ADPA);
1585         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1586              "PCH VGA enabled on transcoder %c, should be disabled\n",
1587              pipe_name(pipe));
1588
1589         val = I915_READ(PCH_LVDS);
1590         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1591              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592              pipe_name(pipe));
1593
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1595         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1596         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 }
1598
1599 static void vlv_enable_pll(struct intel_crtc *crtc,
1600                            const struct intel_crtc_state *pipe_config)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         i915_reg_t reg = DPLL(crtc->pipe);
1605         u32 dpll = pipe_config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev_priv->dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         I915_WRITE(reg, dpll);
1617         POSTING_READ(reg);
1618         udelay(150);
1619
1620         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1621                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1622
1623         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1624         POSTING_READ(DPLL_MD(crtc->pipe));
1625
1626         /* We do this three times for luck */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150); /* wait for warmup */
1633         I915_WRITE(reg, dpll);
1634         POSTING_READ(reg);
1635         udelay(150); /* wait for warmup */
1636 }
1637
1638 static void chv_enable_pll(struct intel_crtc *crtc,
1639                            const struct intel_crtc_state *pipe_config)
1640 {
1641         struct drm_device *dev = crtc->base.dev;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643         int pipe = crtc->pipe;
1644         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1645         u32 tmp;
1646
1647         assert_pipe_disabled(dev_priv, crtc->pipe);
1648
1649         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1650
1651         mutex_lock(&dev_priv->sb_lock);
1652
1653         /* Enable back the 10bit clock to display controller */
1654         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1655         tmp |= DPIO_DCLKP_EN;
1656         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1657
1658         mutex_unlock(&dev_priv->sb_lock);
1659
1660         /*
1661          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1662          */
1663         udelay(1);
1664
1665         /* Enable PLL */
1666         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1667
1668         /* Check PLL is locked */
1669         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1670                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1671
1672         /* not sure when this should be written */
1673         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1674         POSTING_READ(DPLL_MD(pipe));
1675 }
1676
1677 static int intel_num_dvo_pipes(struct drm_device *dev)
1678 {
1679         struct intel_crtc *crtc;
1680         int count = 0;
1681
1682         for_each_intel_crtc(dev, crtc)
1683                 count += crtc->base.state->active &&
1684                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1685
1686         return count;
1687 }
1688
1689 static void i9xx_enable_pll(struct intel_crtc *crtc)
1690 {
1691         struct drm_device *dev = crtc->base.dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         i915_reg_t reg = DPLL(crtc->pipe);
1694         u32 dpll = crtc->config->dpll_hw_state.dpll;
1695
1696         assert_pipe_disabled(dev_priv, crtc->pipe);
1697
1698         /* No really, not for ILK+ */
1699         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1700
1701         /* PLL is protected by panel, make sure we can write it */
1702         if (IS_MOBILE(dev) && !IS_I830(dev))
1703                 assert_panel_unlocked(dev_priv, crtc->pipe);
1704
1705         /* Enable DVO 2x clock on both PLLs if necessary */
1706         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1707                 /*
1708                  * It appears to be important that we don't enable this
1709                  * for the current pipe before otherwise configuring the
1710                  * PLL. No idea how this should be handled if multiple
1711                  * DVO outputs are enabled simultaneosly.
1712                  */
1713                 dpll |= DPLL_DVO_2X_MODE;
1714                 I915_WRITE(DPLL(!crtc->pipe),
1715                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1716         }
1717
1718         /*
1719          * Apparently we need to have VGA mode enabled prior to changing
1720          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1721          * dividers, even though the register value does change.
1722          */
1723         I915_WRITE(reg, 0);
1724
1725         I915_WRITE(reg, dpll);
1726
1727         /* Wait for the clocks to stabilize. */
1728         POSTING_READ(reg);
1729         udelay(150);
1730
1731         if (INTEL_INFO(dev)->gen >= 4) {
1732                 I915_WRITE(DPLL_MD(crtc->pipe),
1733                            crtc->config->dpll_hw_state.dpll_md);
1734         } else {
1735                 /* The pixel multiplier can only be updated once the
1736                  * DPLL is enabled and the clocks are stable.
1737                  *
1738                  * So write it again.
1739                  */
1740                 I915_WRITE(reg, dpll);
1741         }
1742
1743         /* We do this three times for luck */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750         I915_WRITE(reg, dpll);
1751         POSTING_READ(reg);
1752         udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756  * i9xx_disable_pll - disable a PLL
1757  * @dev_priv: i915 private structure
1758  * @pipe: pipe PLL to disable
1759  *
1760  * Disable the PLL for @pipe, making sure the pipe is off first.
1761  *
1762  * Note!  This is for pre-ILK only.
1763  */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766         struct drm_device *dev = crtc->base.dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         enum pipe pipe = crtc->pipe;
1769
1770         /* Disable DVO 2x clock on both PLLs if necessary */
1771         if (IS_I830(dev) &&
1772             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773             !intel_num_dvo_pipes(dev)) {
1774                 I915_WRITE(DPLL(PIPE_B),
1775                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776                 I915_WRITE(DPLL(PIPE_A),
1777                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778         }
1779
1780         /* Don't disable pipe or pipe PLLs if needed */
1781         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783                 return;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1789         POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794         u32 val;
1795
1796         /* Make sure the pipe isn't still relying on us */
1797         assert_pipe_disabled(dev_priv, pipe);
1798
1799         /*
1800          * Leave integrated clock source and reference clock enabled for pipe B.
1801          * The latter is needed for VGA hotplug / manual detection.
1802          */
1803         val = DPLL_VGA_MODE_DIS;
1804         if (pipe == PIPE_B)
1805                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1806         I915_WRITE(DPLL(pipe), val);
1807         POSTING_READ(DPLL(pipe));
1808
1809 }
1810
1811 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1814         u32 val;
1815
1816         /* Make sure the pipe isn't still relying on us */
1817         assert_pipe_disabled(dev_priv, pipe);
1818
1819         /* Set PLL en = 0 */
1820         val = DPLL_SSC_REF_CLK_CHV |
1821                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1822         if (pipe != PIPE_A)
1823                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824         I915_WRITE(DPLL(pipe), val);
1825         POSTING_READ(DPLL(pipe));
1826
1827         mutex_lock(&dev_priv->sb_lock);
1828
1829         /* Disable 10bit clock to display controller */
1830         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831         val &= ~DPIO_DCLKP_EN;
1832         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
1834         mutex_unlock(&dev_priv->sb_lock);
1835 }
1836
1837 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1838                          struct intel_digital_port *dport,
1839                          unsigned int expected_mask)
1840 {
1841         u32 port_mask;
1842         i915_reg_t dpll_reg;
1843
1844         switch (dport->port) {
1845         case PORT_B:
1846                 port_mask = DPLL_PORTB_READY_MASK;
1847                 dpll_reg = DPLL(0);
1848                 break;
1849         case PORT_C:
1850                 port_mask = DPLL_PORTC_READY_MASK;
1851                 dpll_reg = DPLL(0);
1852                 expected_mask <<= 4;
1853                 break;
1854         case PORT_D:
1855                 port_mask = DPLL_PORTD_READY_MASK;
1856                 dpll_reg = DPIO_PHY_STATUS;
1857                 break;
1858         default:
1859                 BUG();
1860         }
1861
1862         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1863                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1864                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1865 }
1866
1867 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1868 {
1869         struct drm_device *dev = crtc->base.dev;
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1872
1873         if (WARN_ON(pll == NULL))
1874                 return;
1875
1876         WARN_ON(!pll->config.crtc_mask);
1877         if (pll->active == 0) {
1878                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1879                 WARN_ON(pll->on);
1880                 assert_shared_dpll_disabled(dev_priv, pll);
1881
1882                 pll->mode_set(dev_priv, pll);
1883         }
1884 }
1885
1886 /**
1887  * intel_enable_shared_dpll - enable PCH PLL
1888  * @dev_priv: i915 private structure
1889  * @pipe: pipe PLL to enable
1890  *
1891  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1892  * drives the transcoder clock.
1893  */
1894 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1895 {
1896         struct drm_device *dev = crtc->base.dev;
1897         struct drm_i915_private *dev_priv = dev->dev_private;
1898         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1899
1900         if (WARN_ON(pll == NULL))
1901                 return;
1902
1903         if (WARN_ON(pll->config.crtc_mask == 0))
1904                 return;
1905
1906         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1907                       pll->name, pll->active, pll->on,
1908                       crtc->base.base.id);
1909
1910         if (pll->active++) {
1911                 WARN_ON(!pll->on);
1912                 assert_shared_dpll_enabled(dev_priv, pll);
1913                 return;
1914         }
1915         WARN_ON(pll->on);
1916
1917         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1918
1919         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1920         pll->enable(dev_priv, pll);
1921         pll->on = true;
1922 }
1923
1924 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1925 {
1926         struct drm_device *dev = crtc->base.dev;
1927         struct drm_i915_private *dev_priv = dev->dev_private;
1928         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1929
1930         /* PCH only available on ILK+ */
1931         if (INTEL_INFO(dev)->gen < 5)
1932                 return;
1933
1934         if (pll == NULL)
1935                 return;
1936
1937         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1938                 return;
1939
1940         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1941                       pll->name, pll->active, pll->on,
1942                       crtc->base.base.id);
1943
1944         if (WARN_ON(pll->active == 0)) {
1945                 assert_shared_dpll_disabled(dev_priv, pll);
1946                 return;
1947         }
1948
1949         assert_shared_dpll_enabled(dev_priv, pll);
1950         WARN_ON(!pll->on);
1951         if (--pll->active)
1952                 return;
1953
1954         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1955         pll->disable(dev_priv, pll);
1956         pll->on = false;
1957
1958         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1959 }
1960
1961 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1962                                            enum pipe pipe)
1963 {
1964         struct drm_device *dev = dev_priv->dev;
1965         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1967         i915_reg_t reg;
1968         uint32_t val, pipeconf_val;
1969
1970         /* PCH only available on ILK+ */
1971         BUG_ON(!HAS_PCH_SPLIT(dev));
1972
1973         /* Make sure PCH DPLL is enabled */
1974         assert_shared_dpll_enabled(dev_priv,
1975                                    intel_crtc_to_shared_dpll(intel_crtc));
1976
1977         /* FDI must be feeding us bits for PCH ports */
1978         assert_fdi_tx_enabled(dev_priv, pipe);
1979         assert_fdi_rx_enabled(dev_priv, pipe);
1980
1981         if (HAS_PCH_CPT(dev)) {
1982                 /* Workaround: Set the timing override bit before enabling the
1983                  * pch transcoder. */
1984                 reg = TRANS_CHICKEN2(pipe);
1985                 val = I915_READ(reg);
1986                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1987                 I915_WRITE(reg, val);
1988         }
1989
1990         reg = PCH_TRANSCONF(pipe);
1991         val = I915_READ(reg);
1992         pipeconf_val = I915_READ(PIPECONF(pipe));
1993
1994         if (HAS_PCH_IBX(dev_priv->dev)) {
1995                 /*
1996                  * Make the BPC in transcoder be consistent with
1997                  * that in pipeconf reg. For HDMI we must use 8bpc
1998                  * here for both 8bpc and 12bpc.
1999                  */
2000                 val &= ~PIPECONF_BPC_MASK;
2001                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2002                         val |= PIPECONF_8BPC;
2003                 else
2004                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2005         }
2006
2007         val &= ~TRANS_INTERLACE_MASK;
2008         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2009                 if (HAS_PCH_IBX(dev_priv->dev) &&
2010                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2011                         val |= TRANS_LEGACY_INTERLACED_ILK;
2012                 else
2013                         val |= TRANS_INTERLACED;
2014         else
2015                 val |= TRANS_PROGRESSIVE;
2016
2017         I915_WRITE(reg, val | TRANS_ENABLE);
2018         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2019                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2020 }
2021
2022 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2023                                       enum transcoder cpu_transcoder)
2024 {
2025         u32 val, pipeconf_val;
2026
2027         /* PCH only available on ILK+ */
2028         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2029
2030         /* FDI must be feeding us bits for PCH ports */
2031         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2032         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2033
2034         /* Workaround: set timing override bit. */
2035         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2036         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2037         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2038
2039         val = TRANS_ENABLE;
2040         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2041
2042         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2043             PIPECONF_INTERLACED_ILK)
2044                 val |= TRANS_INTERLACED;
2045         else
2046                 val |= TRANS_PROGRESSIVE;
2047
2048         I915_WRITE(LPT_TRANSCONF, val);
2049         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2050                 DRM_ERROR("Failed to enable PCH transcoder\n");
2051 }
2052
2053 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2054                                             enum pipe pipe)
2055 {
2056         struct drm_device *dev = dev_priv->dev;
2057         i915_reg_t reg;
2058         uint32_t val;
2059
2060         /* FDI relies on the transcoder */
2061         assert_fdi_tx_disabled(dev_priv, pipe);
2062         assert_fdi_rx_disabled(dev_priv, pipe);
2063
2064         /* Ports must be off as well */
2065         assert_pch_ports_disabled(dev_priv, pipe);
2066
2067         reg = PCH_TRANSCONF(pipe);
2068         val = I915_READ(reg);
2069         val &= ~TRANS_ENABLE;
2070         I915_WRITE(reg, val);
2071         /* wait for PCH transcoder off, transcoder state */
2072         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2073                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2074
2075         if (HAS_PCH_CPT(dev)) {
2076                 /* Workaround: Clear the timing override chicken bit again. */
2077                 reg = TRANS_CHICKEN2(pipe);
2078                 val = I915_READ(reg);
2079                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2080                 I915_WRITE(reg, val);
2081         }
2082 }
2083
2084 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2085 {
2086         u32 val;
2087
2088         val = I915_READ(LPT_TRANSCONF);
2089         val &= ~TRANS_ENABLE;
2090         I915_WRITE(LPT_TRANSCONF, val);
2091         /* wait for PCH transcoder off, transcoder state */
2092         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2093                 DRM_ERROR("Failed to disable PCH transcoder\n");
2094
2095         /* Workaround: clear timing override bit. */
2096         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2097         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2098         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2099 }
2100
2101 /**
2102  * intel_enable_pipe - enable a pipe, asserting requirements
2103  * @crtc: crtc responsible for the pipe
2104  *
2105  * Enable @crtc's pipe, making sure that various hardware specific requirements
2106  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2107  */
2108 static void intel_enable_pipe(struct intel_crtc *crtc)
2109 {
2110         struct drm_device *dev = crtc->base.dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         enum pipe pipe = crtc->pipe;
2113         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2114         enum pipe pch_transcoder;
2115         i915_reg_t reg;
2116         u32 val;
2117
2118         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2119
2120         assert_planes_disabled(dev_priv, pipe);
2121         assert_cursor_disabled(dev_priv, pipe);
2122         assert_sprites_disabled(dev_priv, pipe);
2123
2124         if (HAS_PCH_LPT(dev_priv->dev))
2125                 pch_transcoder = TRANSCODER_A;
2126         else
2127                 pch_transcoder = pipe;
2128
2129         /*
2130          * A pipe without a PLL won't actually be able to drive bits from
2131          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2132          * need the check.
2133          */
2134         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135                 if (crtc->config->has_dsi_encoder)
2136                         assert_dsi_pll_enabled(dev_priv);
2137                 else
2138                         assert_pll_enabled(dev_priv, pipe);
2139         else {
2140                 if (crtc->config->has_pch_encoder) {
2141                         /* if driving the PCH, we need FDI enabled */
2142                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143                         assert_fdi_tx_pll_enabled(dev_priv,
2144                                                   (enum pipe) cpu_transcoder);
2145                 }
2146                 /* FIXME: assert CPU port conditions for SNB+ */
2147         }
2148
2149         reg = PIPECONF(cpu_transcoder);
2150         val = I915_READ(reg);
2151         if (val & PIPECONF_ENABLE) {
2152                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154                 return;
2155         }
2156
2157         I915_WRITE(reg, val | PIPECONF_ENABLE);
2158         POSTING_READ(reg);
2159 }
2160
2161 /**
2162  * intel_disable_pipe - disable a pipe, asserting requirements
2163  * @crtc: crtc whose pipes is to be disabled
2164  *
2165  * Disable the pipe of @crtc, making sure that various hardware
2166  * specific requirements are met, if applicable, e.g. plane
2167  * disabled, panel fitter off, etc.
2168  *
2169  * Will wait until the pipe has shut down before returning.
2170  */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175         enum pipe pipe = crtc->pipe;
2176         i915_reg_t reg;
2177         u32 val;
2178
2179         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180
2181         /*
2182          * Make sure planes won't keep trying to pump pixels to us,
2183          * or we might hang the display.
2184          */
2185         assert_planes_disabled(dev_priv, pipe);
2186         assert_cursor_disabled(dev_priv, pipe);
2187         assert_sprites_disabled(dev_priv, pipe);
2188
2189         reg = PIPECONF(cpu_transcoder);
2190         val = I915_READ(reg);
2191         if ((val & PIPECONF_ENABLE) == 0)
2192                 return;
2193
2194         /*
2195          * Double wide has implications for planes
2196          * so best keep it disabled when not needed.
2197          */
2198         if (crtc->config->double_wide)
2199                 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201         /* Don't disable pipe or pipe PLLs if needed */
2202         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204                 val &= ~PIPECONF_ENABLE;
2205
2206         I915_WRITE(reg, val);
2207         if ((val & PIPECONF_ENABLE) == 0)
2208                 intel_wait_for_pipe_off(crtc);
2209 }
2210
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215                 return true;
2216 #endif
2217         return false;
2218 }
2219
2220 unsigned int
2221 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2222                   uint64_t fb_format_modifier, unsigned int plane)
2223 {
2224         unsigned int tile_height;
2225         uint32_t pixel_bytes;
2226
2227         switch (fb_format_modifier) {
2228         case DRM_FORMAT_MOD_NONE:
2229                 tile_height = 1;
2230                 break;
2231         case I915_FORMAT_MOD_X_TILED:
2232                 tile_height = IS_GEN2(dev) ? 16 : 8;
2233                 break;
2234         case I915_FORMAT_MOD_Y_TILED:
2235                 tile_height = 32;
2236                 break;
2237         case I915_FORMAT_MOD_Yf_TILED:
2238                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2239                 switch (pixel_bytes) {
2240                 default:
2241                 case 1:
2242                         tile_height = 64;
2243                         break;
2244                 case 2:
2245                 case 4:
2246                         tile_height = 32;
2247                         break;
2248                 case 8:
2249                         tile_height = 16;
2250                         break;
2251                 case 16:
2252                         WARN_ONCE(1,
2253                                   "128-bit pixels are not supported for display!");
2254                         tile_height = 16;
2255                         break;
2256                 }
2257                 break;
2258         default:
2259                 MISSING_CASE(fb_format_modifier);
2260                 tile_height = 1;
2261                 break;
2262         }
2263
2264         return tile_height;
2265 }
2266
2267 unsigned int
2268 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2269                       uint32_t pixel_format, uint64_t fb_format_modifier)
2270 {
2271         return ALIGN(height, intel_tile_height(dev, pixel_format,
2272                                                fb_format_modifier, 0));
2273 }
2274
2275 static void
2276 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2277                         const struct drm_plane_state *plane_state)
2278 {
2279         struct intel_rotation_info *info = &view->params.rotation_info;
2280         unsigned int tile_height, tile_pitch;
2281
2282         *view = i915_ggtt_view_normal;
2283
2284         if (!plane_state)
2285                 return;
2286
2287         if (!intel_rotation_90_or_270(plane_state->rotation))
2288                 return;
2289
2290         *view = i915_ggtt_view_rotated;
2291
2292         info->height = fb->height;
2293         info->pixel_format = fb->pixel_format;
2294         info->pitch = fb->pitches[0];
2295         info->uv_offset = fb->offsets[1];
2296         info->fb_modifier = fb->modifier[0];
2297
2298         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2299                                         fb->modifier[0], 0);
2300         tile_pitch = PAGE_SIZE / tile_height;
2301         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2302         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2303         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2304
2305         if (info->pixel_format == DRM_FORMAT_NV12) {
2306                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2307                                                 fb->modifier[0], 1);
2308                 tile_pitch = PAGE_SIZE / tile_height;
2309                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2310                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2311                                                      tile_height);
2312                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2313                                 PAGE_SIZE;
2314         }
2315 }
2316
2317 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2318 {
2319         if (INTEL_INFO(dev_priv)->gen >= 9)
2320                 return 256 * 1024;
2321         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322                  IS_VALLEYVIEW(dev_priv))
2323                 return 128 * 1024;
2324         else if (INTEL_INFO(dev_priv)->gen >= 4)
2325                 return 4 * 1024;
2326         else
2327                 return 0;
2328 }
2329
2330 int
2331 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332                            struct drm_framebuffer *fb,
2333                            const struct drm_plane_state *plane_state)
2334 {
2335         struct drm_device *dev = fb->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2338         struct i915_ggtt_view view;
2339         u32 alignment;
2340         int ret;
2341
2342         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343
2344         switch (fb->modifier[0]) {
2345         case DRM_FORMAT_MOD_NONE:
2346                 alignment = intel_linear_alignment(dev_priv);
2347                 break;
2348         case I915_FORMAT_MOD_X_TILED:
2349                 if (INTEL_INFO(dev)->gen >= 9)
2350                         alignment = 256 * 1024;
2351                 else {
2352                         /* pin() will align the object as required by fence */
2353                         alignment = 0;
2354                 }
2355                 break;
2356         case I915_FORMAT_MOD_Y_TILED:
2357         case I915_FORMAT_MOD_Yf_TILED:
2358                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2359                           "Y tiling bo slipped through, driver bug!\n"))
2360                         return -EINVAL;
2361                 alignment = 1 * 1024 * 1024;
2362                 break;
2363         default:
2364                 MISSING_CASE(fb->modifier[0]);
2365                 return -EINVAL;
2366         }
2367
2368         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2369
2370         /* Note that the w/a also requires 64 PTE of padding following the
2371          * bo. We currently fill all unused PTE with the shadow page and so
2372          * we should always have valid PTE following the scanout preventing
2373          * the VT-d warning.
2374          */
2375         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2376                 alignment = 256 * 1024;
2377
2378         /*
2379          * Global gtt pte registers are special registers which actually forward
2380          * writes to a chunk of system memory. Which means that there is no risk
2381          * that the register values disappear as soon as we call
2382          * intel_runtime_pm_put(), so it is correct to wrap only the
2383          * pin/unpin/fence and not more.
2384          */
2385         intel_runtime_pm_get(dev_priv);
2386
2387         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2388                                                    &view);
2389         if (ret)
2390                 goto err_pm;
2391
2392         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393          * fence, whereas 965+ only requires a fence if using
2394          * framebuffer compression.  For simplicity, we always install
2395          * a fence as the cost is not that onerous.
2396          */
2397         if (view.type == I915_GGTT_VIEW_NORMAL) {
2398                 ret = i915_gem_object_get_fence(obj);
2399                 if (ret == -EDEADLK) {
2400                         /*
2401                          * -EDEADLK means there are no free fences
2402                          * no pending flips.
2403                          *
2404                          * This is propagated to atomic, but it uses
2405                          * -EDEADLK to force a locking recovery, so
2406                          * change the returned error to -EBUSY.
2407                          */
2408                         ret = -EBUSY;
2409                         goto err_unpin;
2410                 } else if (ret)
2411                         goto err_unpin;
2412
2413                 i915_gem_object_pin_fence(obj);
2414         }
2415
2416         intel_runtime_pm_put(dev_priv);
2417         return 0;
2418
2419 err_unpin:
2420         i915_gem_object_unpin_from_display_plane(obj, &view);
2421 err_pm:
2422         intel_runtime_pm_put(dev_priv);
2423         return ret;
2424 }
2425
2426 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2427                                const struct drm_plane_state *plane_state)
2428 {
2429         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2430         struct i915_ggtt_view view;
2431
2432         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2433
2434         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2435
2436         if (view.type == I915_GGTT_VIEW_NORMAL)
2437                 i915_gem_object_unpin_fence(obj);
2438
2439         i915_gem_object_unpin_from_display_plane(obj, &view);
2440 }
2441
2442 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2443  * is assumed to be a power-of-two. */
2444 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2445                                              int *x, int *y,
2446                                              unsigned int tiling_mode,
2447                                              unsigned int cpp,
2448                                              unsigned int pitch)
2449 {
2450         if (tiling_mode != I915_TILING_NONE) {
2451                 unsigned int tile_rows, tiles;
2452
2453                 tile_rows = *y / 8;
2454                 *y %= 8;
2455
2456                 tiles = *x / (512/cpp);
2457                 *x %= 512/cpp;
2458
2459                 return tile_rows * pitch * 8 + tiles * 4096;
2460         } else {
2461                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2462                 unsigned int offset;
2463
2464                 offset = *y * pitch + *x * cpp;
2465                 *y = (offset & alignment) / pitch;
2466                 *x = ((offset & alignment) - *y * pitch) / cpp;
2467                 return offset & ~alignment;
2468         }
2469 }
2470
2471 static int i9xx_format_to_fourcc(int format)
2472 {
2473         switch (format) {
2474         case DISPPLANE_8BPP:
2475                 return DRM_FORMAT_C8;
2476         case DISPPLANE_BGRX555:
2477                 return DRM_FORMAT_XRGB1555;
2478         case DISPPLANE_BGRX565:
2479                 return DRM_FORMAT_RGB565;
2480         default:
2481         case DISPPLANE_BGRX888:
2482                 return DRM_FORMAT_XRGB8888;
2483         case DISPPLANE_RGBX888:
2484                 return DRM_FORMAT_XBGR8888;
2485         case DISPPLANE_BGRX101010:
2486                 return DRM_FORMAT_XRGB2101010;
2487         case DISPPLANE_RGBX101010:
2488                 return DRM_FORMAT_XBGR2101010;
2489         }
2490 }
2491
2492 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2493 {
2494         switch (format) {
2495         case PLANE_CTL_FORMAT_RGB_565:
2496                 return DRM_FORMAT_RGB565;
2497         default:
2498         case PLANE_CTL_FORMAT_XRGB_8888:
2499                 if (rgb_order) {
2500                         if (alpha)
2501                                 return DRM_FORMAT_ABGR8888;
2502                         else
2503                                 return DRM_FORMAT_XBGR8888;
2504                 } else {
2505                         if (alpha)
2506                                 return DRM_FORMAT_ARGB8888;
2507                         else
2508                                 return DRM_FORMAT_XRGB8888;
2509                 }
2510         case PLANE_CTL_FORMAT_XRGB_2101010:
2511                 if (rgb_order)
2512                         return DRM_FORMAT_XBGR2101010;
2513                 else
2514                         return DRM_FORMAT_XRGB2101010;
2515         }
2516 }
2517
2518 static bool
2519 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2520                               struct intel_initial_plane_config *plane_config)
2521 {
2522         struct drm_device *dev = crtc->base.dev;
2523         struct drm_i915_private *dev_priv = to_i915(dev);
2524         struct drm_i915_gem_object *obj = NULL;
2525         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526         struct drm_framebuffer *fb = &plane_config->fb->base;
2527         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529                                     PAGE_SIZE);
2530
2531         size_aligned -= base_aligned;
2532
2533         if (plane_config->size == 0)
2534                 return false;
2535
2536         /* If the FB is too big, just don't use it since fbdev is not very
2537          * important and we should probably use that space with FBC or other
2538          * features. */
2539         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2540                 return false;
2541
2542         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2543                                                              base_aligned,
2544                                                              base_aligned,
2545                                                              size_aligned);
2546         if (!obj)
2547                 return false;
2548
2549         obj->tiling_mode = plane_config->tiling;
2550         if (obj->tiling_mode == I915_TILING_X)
2551                 obj->stride = fb->pitches[0];
2552
2553         mode_cmd.pixel_format = fb->pixel_format;
2554         mode_cmd.width = fb->width;
2555         mode_cmd.height = fb->height;
2556         mode_cmd.pitches[0] = fb->pitches[0];
2557         mode_cmd.modifier[0] = fb->modifier[0];
2558         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2559
2560         mutex_lock(&dev->struct_mutex);
2561         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2562                                    &mode_cmd, obj)) {
2563                 DRM_DEBUG_KMS("intel fb init failed\n");
2564                 goto out_unref_obj;
2565         }
2566         mutex_unlock(&dev->struct_mutex);
2567
2568         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2569         return true;
2570
2571 out_unref_obj:
2572         drm_gem_object_unreference(&obj->base);
2573         mutex_unlock(&dev->struct_mutex);
2574         return false;
2575 }
2576
2577 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2578 static void
2579 update_state_fb(struct drm_plane *plane)
2580 {
2581         if (plane->fb == plane->state->fb)
2582                 return;
2583
2584         if (plane->state->fb)
2585                 drm_framebuffer_unreference(plane->state->fb);
2586         plane->state->fb = plane->fb;
2587         if (plane->state->fb)
2588                 drm_framebuffer_reference(plane->state->fb);
2589 }
2590
2591 static void
2592 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2593                              struct intel_initial_plane_config *plane_config)
2594 {
2595         struct drm_device *dev = intel_crtc->base.dev;
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct drm_crtc *c;
2598         struct intel_crtc *i;
2599         struct drm_i915_gem_object *obj;
2600         struct drm_plane *primary = intel_crtc->base.primary;
2601         struct drm_plane_state *plane_state = primary->state;
2602         struct drm_framebuffer *fb;
2603
2604         if (!plane_config->fb)
2605                 return;
2606
2607         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608                 fb = &plane_config->fb->base;
2609                 goto valid_fb;
2610         }
2611
2612         kfree(plane_config->fb);
2613
2614         /*
2615          * Failed to alloc the obj, check to see if we should share
2616          * an fb with another CRTC instead
2617          */
2618         for_each_crtc(dev, c) {
2619                 i = to_intel_crtc(c);
2620
2621                 if (c == &intel_crtc->base)
2622                         continue;
2623
2624                 if (!i->active)
2625                         continue;
2626
2627                 fb = c->primary->fb;
2628                 if (!fb)
2629                         continue;
2630
2631                 obj = intel_fb_obj(fb);
2632                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633                         drm_framebuffer_reference(fb);
2634                         goto valid_fb;
2635                 }
2636         }
2637
2638         return;
2639
2640 valid_fb:
2641         plane_state->src_x = 0;
2642         plane_state->src_y = 0;
2643         plane_state->src_w = fb->width << 16;
2644         plane_state->src_h = fb->height << 16;
2645
2646         plane_state->crtc_x = 0;
2647         plane_state->crtc_y = 0;
2648         plane_state->crtc_w = fb->width;
2649         plane_state->crtc_h = fb->height;
2650
2651         obj = intel_fb_obj(fb);
2652         if (obj->tiling_mode != I915_TILING_NONE)
2653                 dev_priv->preserve_bios_swizzle = true;
2654
2655         drm_framebuffer_reference(fb);
2656         primary->fb = primary->state->fb = fb;
2657         primary->crtc = primary->state->crtc = &intel_crtc->base;
2658         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2659         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2660 }
2661
2662 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2663                                       struct drm_framebuffer *fb,
2664                                       int x, int y)
2665 {
2666         struct drm_device *dev = crtc->dev;
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2669         struct drm_plane *primary = crtc->primary;
2670         bool visible = to_intel_plane_state(primary->state)->visible;
2671         struct drm_i915_gem_object *obj;
2672         int plane = intel_crtc->plane;
2673         unsigned long linear_offset;
2674         u32 dspcntr;
2675         i915_reg_t reg = DSPCNTR(plane);
2676         int pixel_size;
2677
2678         if (!visible || !fb) {
2679                 I915_WRITE(reg, 0);
2680                 if (INTEL_INFO(dev)->gen >= 4)
2681                         I915_WRITE(DSPSURF(plane), 0);
2682                 else
2683                         I915_WRITE(DSPADDR(plane), 0);
2684                 POSTING_READ(reg);
2685                 return;
2686         }
2687
2688         obj = intel_fb_obj(fb);
2689         if (WARN_ON(obj == NULL))
2690                 return;
2691
2692         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2693
2694         dspcntr = DISPPLANE_GAMMA_ENABLE;
2695
2696         dspcntr |= DISPLAY_PLANE_ENABLE;
2697
2698         if (INTEL_INFO(dev)->gen < 4) {
2699                 if (intel_crtc->pipe == PIPE_B)
2700                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2701
2702                 /* pipesrc and dspsize control the size that is scaled from,
2703                  * which should always be the user's requested size.
2704                  */
2705                 I915_WRITE(DSPSIZE(plane),
2706                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2707                            (intel_crtc->config->pipe_src_w - 1));
2708                 I915_WRITE(DSPPOS(plane), 0);
2709         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2710                 I915_WRITE(PRIMSIZE(plane),
2711                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2712                            (intel_crtc->config->pipe_src_w - 1));
2713                 I915_WRITE(PRIMPOS(plane), 0);
2714                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2715         }
2716
2717         switch (fb->pixel_format) {
2718         case DRM_FORMAT_C8:
2719                 dspcntr |= DISPPLANE_8BPP;
2720                 break;
2721         case DRM_FORMAT_XRGB1555:
2722                 dspcntr |= DISPPLANE_BGRX555;
2723                 break;
2724         case DRM_FORMAT_RGB565:
2725                 dspcntr |= DISPPLANE_BGRX565;
2726                 break;
2727         case DRM_FORMAT_XRGB8888:
2728                 dspcntr |= DISPPLANE_BGRX888;
2729                 break;
2730         case DRM_FORMAT_XBGR8888:
2731                 dspcntr |= DISPPLANE_RGBX888;
2732                 break;
2733         case DRM_FORMAT_XRGB2101010:
2734                 dspcntr |= DISPPLANE_BGRX101010;
2735                 break;
2736         case DRM_FORMAT_XBGR2101010:
2737                 dspcntr |= DISPPLANE_RGBX101010;
2738                 break;
2739         default:
2740                 BUG();
2741         }
2742
2743         if (INTEL_INFO(dev)->gen >= 4 &&
2744             obj->tiling_mode != I915_TILING_NONE)
2745                 dspcntr |= DISPPLANE_TILED;
2746
2747         if (IS_G4X(dev))
2748                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2749
2750         linear_offset = y * fb->pitches[0] + x * pixel_size;
2751
2752         if (INTEL_INFO(dev)->gen >= 4) {
2753                 intel_crtc->dspaddr_offset =
2754                         intel_gen4_compute_page_offset(dev_priv,
2755                                                        &x, &y, obj->tiling_mode,
2756                                                        pixel_size,
2757                                                        fb->pitches[0]);
2758                 linear_offset -= intel_crtc->dspaddr_offset;
2759         } else {
2760                 intel_crtc->dspaddr_offset = linear_offset;
2761         }
2762
2763         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2764                 dspcntr |= DISPPLANE_ROTATE_180;
2765
2766                 x += (intel_crtc->config->pipe_src_w - 1);
2767                 y += (intel_crtc->config->pipe_src_h - 1);
2768
2769                 /* Finding the last pixel of the last line of the display
2770                 data and adding to linear_offset*/
2771                 linear_offset +=
2772                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2773                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2774         }
2775
2776         intel_crtc->adjusted_x = x;
2777         intel_crtc->adjusted_y = y;
2778
2779         I915_WRITE(reg, dspcntr);
2780
2781         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2782         if (INTEL_INFO(dev)->gen >= 4) {
2783                 I915_WRITE(DSPSURF(plane),
2784                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2785                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2786                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2787         } else
2788                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2789         POSTING_READ(reg);
2790 }
2791
2792 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793                                           struct drm_framebuffer *fb,
2794                                           int x, int y)
2795 {
2796         struct drm_device *dev = crtc->dev;
2797         struct drm_i915_private *dev_priv = dev->dev_private;
2798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799         struct drm_plane *primary = crtc->primary;
2800         bool visible = to_intel_plane_state(primary->state)->visible;
2801         struct drm_i915_gem_object *obj;
2802         int plane = intel_crtc->plane;
2803         unsigned long linear_offset;
2804         u32 dspcntr;
2805         i915_reg_t reg = DSPCNTR(plane);
2806         int pixel_size;
2807
2808         if (!visible || !fb) {
2809                 I915_WRITE(reg, 0);
2810                 I915_WRITE(DSPSURF(plane), 0);
2811                 POSTING_READ(reg);
2812                 return;
2813         }
2814
2815         obj = intel_fb_obj(fb);
2816         if (WARN_ON(obj == NULL))
2817                 return;
2818
2819         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2820
2821         dspcntr = DISPPLANE_GAMMA_ENABLE;
2822
2823         dspcntr |= DISPLAY_PLANE_ENABLE;
2824
2825         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2826                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2827
2828         switch (fb->pixel_format) {
2829         case DRM_FORMAT_C8:
2830                 dspcntr |= DISPPLANE_8BPP;
2831                 break;
2832         case DRM_FORMAT_RGB565:
2833                 dspcntr |= DISPPLANE_BGRX565;
2834                 break;
2835         case DRM_FORMAT_XRGB8888:
2836                 dspcntr |= DISPPLANE_BGRX888;
2837                 break;
2838         case DRM_FORMAT_XBGR8888:
2839                 dspcntr |= DISPPLANE_RGBX888;
2840                 break;
2841         case DRM_FORMAT_XRGB2101010:
2842                 dspcntr |= DISPPLANE_BGRX101010;
2843                 break;
2844         case DRM_FORMAT_XBGR2101010:
2845                 dspcntr |= DISPPLANE_RGBX101010;
2846                 break;
2847         default:
2848                 BUG();
2849         }
2850
2851         if (obj->tiling_mode != I915_TILING_NONE)
2852                 dspcntr |= DISPPLANE_TILED;
2853
2854         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2855                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2856
2857         linear_offset = y * fb->pitches[0] + x * pixel_size;
2858         intel_crtc->dspaddr_offset =
2859                 intel_gen4_compute_page_offset(dev_priv,
2860                                                &x, &y, obj->tiling_mode,
2861                                                pixel_size,
2862                                                fb->pitches[0]);
2863         linear_offset -= intel_crtc->dspaddr_offset;
2864         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2865                 dspcntr |= DISPPLANE_ROTATE_180;
2866
2867                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2868                         x += (intel_crtc->config->pipe_src_w - 1);
2869                         y += (intel_crtc->config->pipe_src_h - 1);
2870
2871                         /* Finding the last pixel of the last line of the display
2872                         data and adding to linear_offset*/
2873                         linear_offset +=
2874                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2875                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2876                 }
2877         }
2878
2879         intel_crtc->adjusted_x = x;
2880         intel_crtc->adjusted_y = y;
2881
2882         I915_WRITE(reg, dspcntr);
2883
2884         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2885         I915_WRITE(DSPSURF(plane),
2886                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2887         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2888                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2889         } else {
2890                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2891                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2892         }
2893         POSTING_READ(reg);
2894 }
2895
2896 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2897                               uint32_t pixel_format)
2898 {
2899         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2900
2901         /*
2902          * The stride is either expressed as a multiple of 64 bytes
2903          * chunks for linear buffers or in number of tiles for tiled
2904          * buffers.
2905          */
2906         switch (fb_modifier) {
2907         case DRM_FORMAT_MOD_NONE:
2908                 return 64;
2909         case I915_FORMAT_MOD_X_TILED:
2910                 if (INTEL_INFO(dev)->gen == 2)
2911                         return 128;
2912                 return 512;
2913         case I915_FORMAT_MOD_Y_TILED:
2914                 /* No need to check for old gens and Y tiling since this is
2915                  * about the display engine and those will be blocked before
2916                  * we get here.
2917                  */
2918                 return 128;
2919         case I915_FORMAT_MOD_Yf_TILED:
2920                 if (bits_per_pixel == 8)
2921                         return 64;
2922                 else
2923                         return 128;
2924         default:
2925                 MISSING_CASE(fb_modifier);
2926                 return 64;
2927         }
2928 }
2929
2930 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2931                            struct drm_i915_gem_object *obj,
2932                            unsigned int plane)
2933 {
2934         struct i915_ggtt_view view;
2935         struct i915_vma *vma;
2936         u64 offset;
2937
2938         intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2939                                 intel_plane->base.state);
2940
2941         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2942         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2943                 view.type))
2944                 return -1;
2945
2946         offset = vma->node.start;
2947
2948         if (plane == 1) {
2949                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2950                           PAGE_SIZE;
2951         }
2952
2953         WARN_ON(upper_32_bits(offset));
2954
2955         return lower_32_bits(offset);
2956 }
2957
2958 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2959 {
2960         struct drm_device *dev = intel_crtc->base.dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962
2963         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2964         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2965         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2966 }
2967
2968 /*
2969  * This function detaches (aka. unbinds) unused scalers in hardware
2970  */
2971 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2972 {
2973         struct intel_crtc_scaler_state *scaler_state;
2974         int i;
2975
2976         scaler_state = &intel_crtc->config->scaler_state;
2977
2978         /* loop through and disable scalers that aren't in use */
2979         for (i = 0; i < intel_crtc->num_scalers; i++) {
2980                 if (!scaler_state->scalers[i].in_use)
2981                         skl_detach_scaler(intel_crtc, i);
2982         }
2983 }
2984
2985 u32 skl_plane_ctl_format(uint32_t pixel_format)
2986 {
2987         switch (pixel_format) {
2988         case DRM_FORMAT_C8:
2989                 return PLANE_CTL_FORMAT_INDEXED;
2990         case DRM_FORMAT_RGB565:
2991                 return PLANE_CTL_FORMAT_RGB_565;
2992         case DRM_FORMAT_XBGR8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2994         case DRM_FORMAT_XRGB8888:
2995                 return PLANE_CTL_FORMAT_XRGB_8888;
2996         /*
2997          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2998          * to be already pre-multiplied. We need to add a knob (or a different
2999          * DRM_FORMAT) for user-space to configure that.
3000          */
3001         case DRM_FORMAT_ABGR8888:
3002                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3003                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3004         case DRM_FORMAT_ARGB8888:
3005                 return PLANE_CTL_FORMAT_XRGB_8888 |
3006                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3007         case DRM_FORMAT_XRGB2101010:
3008                 return PLANE_CTL_FORMAT_XRGB_2101010;
3009         case DRM_FORMAT_XBGR2101010:
3010                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3011         case DRM_FORMAT_YUYV:
3012                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3013         case DRM_FORMAT_YVYU:
3014                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3015         case DRM_FORMAT_UYVY:
3016                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3017         case DRM_FORMAT_VYUY:
3018                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3019         default:
3020                 MISSING_CASE(pixel_format);
3021         }
3022
3023         return 0;
3024 }
3025
3026 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3027 {
3028         switch (fb_modifier) {
3029         case DRM_FORMAT_MOD_NONE:
3030                 break;
3031         case I915_FORMAT_MOD_X_TILED:
3032                 return PLANE_CTL_TILED_X;
3033         case I915_FORMAT_MOD_Y_TILED:
3034                 return PLANE_CTL_TILED_Y;
3035         case I915_FORMAT_MOD_Yf_TILED:
3036                 return PLANE_CTL_TILED_YF;
3037         default:
3038                 MISSING_CASE(fb_modifier);
3039         }
3040
3041         return 0;
3042 }
3043
3044 u32 skl_plane_ctl_rotation(unsigned int rotation)
3045 {
3046         switch (rotation) {
3047         case BIT(DRM_ROTATE_0):
3048                 break;
3049         /*
3050          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3051          * while i915 HW rotation is clockwise, thats why this swapping.
3052          */
3053         case BIT(DRM_ROTATE_90):
3054                 return PLANE_CTL_ROTATE_270;
3055         case BIT(DRM_ROTATE_180):
3056                 return PLANE_CTL_ROTATE_180;
3057         case BIT(DRM_ROTATE_270):
3058                 return PLANE_CTL_ROTATE_90;
3059         default:
3060                 MISSING_CASE(rotation);
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3067                                          struct drm_framebuffer *fb,
3068                                          int x, int y)
3069 {
3070         struct drm_device *dev = crtc->dev;
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073         struct drm_plane *plane = crtc->primary;
3074         bool visible = to_intel_plane_state(plane->state)->visible;
3075         struct drm_i915_gem_object *obj;
3076         int pipe = intel_crtc->pipe;
3077         u32 plane_ctl, stride_div, stride;
3078         u32 tile_height, plane_offset, plane_size;
3079         unsigned int rotation;
3080         int x_offset, y_offset;
3081         u32 surf_addr;
3082         struct intel_crtc_state *crtc_state = intel_crtc->config;
3083         struct intel_plane_state *plane_state;
3084         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3085         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3086         int scaler_id = -1;
3087
3088         plane_state = to_intel_plane_state(plane->state);
3089
3090         if (!visible || !fb) {
3091                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3092                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3093                 POSTING_READ(PLANE_CTL(pipe, 0));
3094                 return;
3095         }
3096
3097         plane_ctl = PLANE_CTL_ENABLE |
3098                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3099                     PLANE_CTL_PIPE_CSC_ENABLE;
3100
3101         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3102         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3103         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3104
3105         rotation = plane->state->rotation;
3106         plane_ctl |= skl_plane_ctl_rotation(rotation);
3107
3108         obj = intel_fb_obj(fb);
3109         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3110                                                fb->pixel_format);
3111         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3112
3113         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3114
3115         scaler_id = plane_state->scaler_id;
3116         src_x = plane_state->src.x1 >> 16;
3117         src_y = plane_state->src.y1 >> 16;
3118         src_w = drm_rect_width(&plane_state->src) >> 16;
3119         src_h = drm_rect_height(&plane_state->src) >> 16;
3120         dst_x = plane_state->dst.x1;
3121         dst_y = plane_state->dst.y1;
3122         dst_w = drm_rect_width(&plane_state->dst);
3123         dst_h = drm_rect_height(&plane_state->dst);
3124
3125         WARN_ON(x != src_x || y != src_y);
3126
3127         if (intel_rotation_90_or_270(rotation)) {
3128                 /* stride = Surface height in tiles */
3129                 tile_height = intel_tile_height(dev, fb->pixel_format,
3130                                                 fb->modifier[0], 0);
3131                 stride = DIV_ROUND_UP(fb->height, tile_height);
3132                 x_offset = stride * tile_height - y - src_h;
3133                 y_offset = x;
3134                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3135         } else {
3136                 stride = fb->pitches[0] / stride_div;
3137                 x_offset = x;
3138                 y_offset = y;
3139                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3140         }
3141         plane_offset = y_offset << 16 | x_offset;
3142
3143         intel_crtc->adjusted_x = x_offset;
3144         intel_crtc->adjusted_y = y_offset;
3145
3146         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3147         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3148         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3149         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3150
3151         if (scaler_id >= 0) {
3152                 uint32_t ps_ctrl = 0;
3153
3154                 WARN_ON(!dst_w || !dst_h);
3155                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3156                         crtc_state->scaler_state.scalers[scaler_id].mode;
3157                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3158                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3159                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3160                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3161                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3162         } else {
3163                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3164         }
3165
3166         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3167
3168         POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174                            int x, int y, enum mode_set_atomic state)
3175 {
3176         struct drm_device *dev = crtc->dev;
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178
3179         if (dev_priv->fbc.deactivate)
3180                 dev_priv->fbc.deactivate(dev_priv);
3181
3182         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3183
3184         return 0;
3185 }
3186
3187 static void intel_complete_page_flips(struct drm_device *dev)
3188 {
3189         struct drm_crtc *crtc;
3190
3191         for_each_crtc(dev, crtc) {
3192                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193                 enum plane plane = intel_crtc->plane;
3194
3195                 intel_prepare_page_flip(dev, plane);
3196                 intel_finish_page_flip_plane(dev, plane);
3197         }
3198 }
3199
3200 static void intel_update_primary_planes(struct drm_device *dev)
3201 {
3202         struct drm_crtc *crtc;
3203
3204         for_each_crtc(dev, crtc) {
3205                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3206                 struct intel_plane_state *plane_state;
3207
3208                 drm_modeset_lock_crtc(crtc, &plane->base);
3209                 plane_state = to_intel_plane_state(plane->base.state);
3210
3211                 if (crtc->state->active && plane_state->base.fb)
3212                         plane->commit_plane(&plane->base, plane_state);
3213
3214                 drm_modeset_unlock_crtc(crtc);
3215         }
3216 }
3217
3218 void intel_prepare_reset(struct drm_device *dev)
3219 {
3220         /* no reset support for gen2 */
3221         if (IS_GEN2(dev))
3222                 return;
3223
3224         /* reset doesn't touch the display */
3225         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3226                 return;
3227
3228         drm_modeset_lock_all(dev);
3229         /*
3230          * Disabling the crtcs gracefully seems nicer. Also the
3231          * g33 docs say we should at least disable all the planes.
3232          */
3233         intel_display_suspend(dev);
3234 }
3235
3236 void intel_finish_reset(struct drm_device *dev)
3237 {
3238         struct drm_i915_private *dev_priv = to_i915(dev);
3239
3240         /*
3241          * Flips in the rings will be nuked by the reset,
3242          * so complete all pending flips so that user space
3243          * will get its events and not get stuck.
3244          */
3245         intel_complete_page_flips(dev);
3246
3247         /* no reset support for gen2 */
3248         if (IS_GEN2(dev))
3249                 return;
3250
3251         /* reset doesn't touch the display */
3252         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3253                 /*
3254                  * Flips in the rings have been nuked by the reset,
3255                  * so update the base address of all primary
3256                  * planes to the the last fb to make sure we're
3257                  * showing the correct fb after a reset.
3258                  *
3259                  * FIXME: Atomic will make this obsolete since we won't schedule
3260                  * CS-based flips (which might get lost in gpu resets) any more.
3261                  */
3262                 intel_update_primary_planes(dev);
3263                 return;
3264         }
3265
3266         /*
3267          * The display has been reset as well,
3268          * so need a full re-initialization.
3269          */
3270         intel_runtime_pm_disable_interrupts(dev_priv);
3271         intel_runtime_pm_enable_interrupts(dev_priv);
3272
3273         intel_modeset_init_hw(dev);
3274
3275         spin_lock_irq(&dev_priv->irq_lock);
3276         if (dev_priv->display.hpd_irq_setup)
3277                 dev_priv->display.hpd_irq_setup(dev);
3278         spin_unlock_irq(&dev_priv->irq_lock);
3279
3280         intel_display_resume(dev);
3281
3282         intel_hpd_init(dev_priv);
3283
3284         drm_modeset_unlock_all(dev);
3285 }
3286
3287 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3288 {
3289         struct drm_device *dev = crtc->dev;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292         bool pending;
3293
3294         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3295             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3296                 return false;
3297
3298         spin_lock_irq(&dev->event_lock);
3299         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3300         spin_unlock_irq(&dev->event_lock);
3301
3302         return pending;
3303 }
3304
3305 static void intel_update_pipe_config(struct intel_crtc *crtc,
3306                                      struct intel_crtc_state *old_crtc_state)
3307 {
3308         struct drm_device *dev = crtc->base.dev;
3309         struct drm_i915_private *dev_priv = dev->dev_private;
3310         struct intel_crtc_state *pipe_config =
3311                 to_intel_crtc_state(crtc->base.state);
3312
3313         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3314         crtc->base.mode = crtc->base.state->mode;
3315
3316         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3317                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3318                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3319
3320         if (HAS_DDI(dev))
3321                 intel_set_pipe_csc(&crtc->base);
3322
3323         /*
3324          * Update pipe size and adjust fitter if needed: the reason for this is
3325          * that in compute_mode_changes we check the native mode (not the pfit
3326          * mode) to see if we can flip rather than do a full mode set. In the
3327          * fastboot case, we'll flip, but if we don't update the pipesrc and
3328          * pfit state, we'll end up with a big fb scanned out into the wrong
3329          * sized surface.
3330          */
3331
3332         I915_WRITE(PIPESRC(crtc->pipe),
3333                    ((pipe_config->pipe_src_w - 1) << 16) |
3334                    (pipe_config->pipe_src_h - 1));
3335
3336         /* on skylake this is done by detaching scalers */
3337         if (INTEL_INFO(dev)->gen >= 9) {
3338                 skl_detach_scalers(crtc);
3339
3340                 if (pipe_config->pch_pfit.enabled)
3341                         skylake_pfit_enable(crtc);
3342         } else if (HAS_PCH_SPLIT(dev)) {
3343                 if (pipe_config->pch_pfit.enabled)
3344                         ironlake_pfit_enable(crtc);
3345                 else if (old_crtc_state->pch_pfit.enabled)
3346                         ironlake_pfit_disable(crtc, true);
3347         }
3348 }
3349
3350 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355         int pipe = intel_crtc->pipe;
3356         i915_reg_t reg;
3357         u32 temp;
3358
3359         /* enable normal train */
3360         reg = FDI_TX_CTL(pipe);
3361         temp = I915_READ(reg);
3362         if (IS_IVYBRIDGE(dev)) {
3363                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3364                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3365         } else {
3366                 temp &= ~FDI_LINK_TRAIN_NONE;
3367                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3368         }
3369         I915_WRITE(reg, temp);
3370
3371         reg = FDI_RX_CTL(pipe);
3372         temp = I915_READ(reg);
3373         if (HAS_PCH_CPT(dev)) {
3374                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3376         } else {
3377                 temp &= ~FDI_LINK_TRAIN_NONE;
3378                 temp |= FDI_LINK_TRAIN_NONE;
3379         }
3380         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3381
3382         /* wait one idle pattern time */
3383         POSTING_READ(reg);
3384         udelay(1000);
3385
3386         /* IVB wants error correction enabled */
3387         if (IS_IVYBRIDGE(dev))
3388                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3389                            FDI_FE_ERRC_ENABLE);
3390 }
3391
3392 /* The FDI link training functions for ILK/Ibexpeak. */
3393 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3394 {
3395         struct drm_device *dev = crtc->dev;
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398         int pipe = intel_crtc->pipe;
3399         i915_reg_t reg;
3400         u32 temp, tries;
3401
3402         /* FDI needs bits from pipe first */
3403         assert_pipe_enabled(dev_priv, pipe);
3404
3405         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406            for train result */
3407         reg = FDI_RX_IMR(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_RX_SYMBOL_LOCK;
3410         temp &= ~FDI_RX_BIT_LOCK;
3411         I915_WRITE(reg, temp);
3412         I915_READ(reg);
3413         udelay(150);
3414
3415         /* enable CPU FDI TX and PCH FDI RX */
3416         reg = FDI_TX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420         temp &= ~FDI_LINK_TRAIN_NONE;
3421         temp |= FDI_LINK_TRAIN_PATTERN_1;
3422         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423
3424         reg = FDI_RX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         temp &= ~FDI_LINK_TRAIN_NONE;
3427         temp |= FDI_LINK_TRAIN_PATTERN_1;
3428         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430         POSTING_READ(reg);
3431         udelay(150);
3432
3433         /* Ironlake workaround, enable clock pointer after FDI enable*/
3434         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436                    FDI_RX_PHASE_SYNC_POINTER_EN);
3437
3438         reg = FDI_RX_IIR(pipe);
3439         for (tries = 0; tries < 5; tries++) {
3440                 temp = I915_READ(reg);
3441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443                 if ((temp & FDI_RX_BIT_LOCK)) {
3444                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3445                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                         break;
3447                 }
3448         }
3449         if (tries == 5)
3450                 DRM_ERROR("FDI train 1 fail!\n");
3451
3452         /* Train 2 */
3453         reg = FDI_TX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         I915_WRITE(reg, temp);
3458
3459         reg = FDI_RX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~FDI_LINK_TRAIN_NONE;
3462         temp |= FDI_LINK_TRAIN_PATTERN_2;
3463         I915_WRITE(reg, temp);
3464
3465         POSTING_READ(reg);
3466         udelay(150);
3467
3468         reg = FDI_RX_IIR(pipe);
3469         for (tries = 0; tries < 5; tries++) {
3470                 temp = I915_READ(reg);
3471                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473                 if (temp & FDI_RX_SYMBOL_LOCK) {
3474                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3476                         break;
3477                 }
3478         }
3479         if (tries == 5)
3480                 DRM_ERROR("FDI train 2 fail!\n");
3481
3482         DRM_DEBUG_KMS("FDI train done\n");
3483
3484 }
3485
3486 static const int snb_b_fdi_train_param[] = {
3487         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491 };
3492
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499         int pipe = intel_crtc->pipe;
3500         i915_reg_t reg;
3501         u32 temp, i, retry;
3502
3503         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3504            for train result */
3505         reg = FDI_RX_IMR(pipe);
3506         temp = I915_READ(reg);
3507         temp &= ~FDI_RX_SYMBOL_LOCK;
3508         temp &= ~FDI_RX_BIT_LOCK;
3509         I915_WRITE(reg, temp);
3510
3511         POSTING_READ(reg);
3512         udelay(150);
3513
3514         /* enable CPU FDI TX and PCH FDI RX */
3515         reg = FDI_TX_CTL(pipe);
3516         temp = I915_READ(reg);
3517         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3518         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3519         temp &= ~FDI_LINK_TRAIN_NONE;
3520         temp |= FDI_LINK_TRAIN_PATTERN_1;
3521         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522         /* SNB-B */
3523         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3524         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3525
3526         I915_WRITE(FDI_RX_MISC(pipe),
3527                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3528
3529         reg = FDI_RX_CTL(pipe);
3530         temp = I915_READ(reg);
3531         if (HAS_PCH_CPT(dev)) {
3532                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3533                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3534         } else {
3535                 temp &= ~FDI_LINK_TRAIN_NONE;
3536                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3537         }
3538         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3539
3540         POSTING_READ(reg);
3541         udelay(150);
3542
3543         for (i = 0; i < 4; i++) {
3544                 reg = FDI_TX_CTL(pipe);
3545                 temp = I915_READ(reg);
3546                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3547                 temp |= snb_b_fdi_train_param[i];
3548                 I915_WRITE(reg, temp);
3549
3550                 POSTING_READ(reg);
3551                 udelay(500);
3552
3553                 for (retry = 0; retry < 5; retry++) {
3554                         reg = FDI_RX_IIR(pipe);
3555                         temp = I915_READ(reg);
3556                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3557                         if (temp & FDI_RX_BIT_LOCK) {
3558                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3559                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3560                                 break;
3561                         }
3562                         udelay(50);
3563                 }
3564                 if (retry < 5)
3565                         break;
3566         }
3567         if (i == 4)
3568                 DRM_ERROR("FDI train 1 fail!\n");
3569
3570         /* Train 2 */
3571         reg = FDI_TX_CTL(pipe);
3572         temp = I915_READ(reg);
3573         temp &= ~FDI_LINK_TRAIN_NONE;
3574         temp |= FDI_LINK_TRAIN_PATTERN_2;
3575         if (IS_GEN6(dev)) {
3576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577                 /* SNB-B */
3578                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3579         }
3580         I915_WRITE(reg, temp);
3581
3582         reg = FDI_RX_CTL(pipe);
3583         temp = I915_READ(reg);
3584         if (HAS_PCH_CPT(dev)) {
3585                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3586                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3587         } else {
3588                 temp &= ~FDI_LINK_TRAIN_NONE;
3589                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3590         }
3591         I915_WRITE(reg, temp);
3592
3593         POSTING_READ(reg);
3594         udelay(150);
3595
3596         for (i = 0; i < 4; i++) {
3597                 reg = FDI_TX_CTL(pipe);
3598                 temp = I915_READ(reg);
3599                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3600                 temp |= snb_b_fdi_train_param[i];
3601                 I915_WRITE(reg, temp);
3602
3603                 POSTING_READ(reg);
3604                 udelay(500);
3605
3606                 for (retry = 0; retry < 5; retry++) {
3607                         reg = FDI_RX_IIR(pipe);
3608                         temp = I915_READ(reg);
3609                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3610                         if (temp & FDI_RX_SYMBOL_LOCK) {
3611                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3612                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3613                                 break;
3614                         }
3615                         udelay(50);
3616                 }
3617                 if (retry < 5)
3618                         break;
3619         }
3620         if (i == 4)
3621                 DRM_ERROR("FDI train 2 fail!\n");
3622
3623         DRM_DEBUG_KMS("FDI train done.\n");
3624 }
3625
3626 /* Manual link training for Ivy Bridge A0 parts */
3627 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3628 {
3629         struct drm_device *dev = crtc->dev;
3630         struct drm_i915_private *dev_priv = dev->dev_private;
3631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632         int pipe = intel_crtc->pipe;
3633         i915_reg_t reg;
3634         u32 temp, i, j;
3635
3636         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3637            for train result */
3638         reg = FDI_RX_IMR(pipe);
3639         temp = I915_READ(reg);
3640         temp &= ~FDI_RX_SYMBOL_LOCK;
3641         temp &= ~FDI_RX_BIT_LOCK;
3642         I915_WRITE(reg, temp);
3643
3644         POSTING_READ(reg);
3645         udelay(150);
3646
3647         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3648                       I915_READ(FDI_RX_IIR(pipe)));
3649
3650         /* Try each vswing and preemphasis setting twice before moving on */
3651         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3652                 /* disable first in case we need to retry */
3653                 reg = FDI_TX_CTL(pipe);
3654                 temp = I915_READ(reg);
3655                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3656                 temp &= ~FDI_TX_ENABLE;
3657                 I915_WRITE(reg, temp);
3658
3659                 reg = FDI_RX_CTL(pipe);
3660                 temp = I915_READ(reg);
3661                 temp &= ~FDI_LINK_TRAIN_AUTO;
3662                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3663                 temp &= ~FDI_RX_ENABLE;
3664                 I915_WRITE(reg, temp);
3665
3666                 /* enable CPU FDI TX and PCH FDI RX */
3667                 reg = FDI_TX_CTL(pipe);
3668                 temp = I915_READ(reg);
3669                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3670                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3671                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3672                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3673                 temp |= snb_b_fdi_train_param[j/2];
3674                 temp |= FDI_COMPOSITE_SYNC;
3675                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3676
3677                 I915_WRITE(FDI_RX_MISC(pipe),
3678                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3679
3680                 reg = FDI_RX_CTL(pipe);
3681                 temp = I915_READ(reg);
3682                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3683                 temp |= FDI_COMPOSITE_SYNC;
3684                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3685
3686                 POSTING_READ(reg);
3687                 udelay(1); /* should be 0.5us */
3688
3689                 for (i = 0; i < 4; i++) {
3690                         reg = FDI_RX_IIR(pipe);
3691                         temp = I915_READ(reg);
3692                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3693
3694                         if (temp & FDI_RX_BIT_LOCK ||
3695                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3696                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3697                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3698                                               i);
3699                                 break;
3700                         }
3701                         udelay(1); /* should be 0.5us */
3702                 }
3703                 if (i == 4) {
3704                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3705                         continue;
3706                 }
3707
3708                 /* Train 2 */
3709                 reg = FDI_TX_CTL(pipe);
3710                 temp = I915_READ(reg);
3711                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3712                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3713                 I915_WRITE(reg, temp);
3714
3715                 reg = FDI_RX_CTL(pipe);
3716                 temp = I915_READ(reg);
3717                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3718                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3719                 I915_WRITE(reg, temp);
3720
3721                 POSTING_READ(reg);
3722                 udelay(2); /* should be 1.5us */
3723
3724                 for (i = 0; i < 4; i++) {
3725                         reg = FDI_RX_IIR(pipe);
3726                         temp = I915_READ(reg);
3727                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3728
3729                         if (temp & FDI_RX_SYMBOL_LOCK ||
3730                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3731                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3732                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3733                                               i);
3734                                 goto train_done;
3735                         }
3736                         udelay(2); /* should be 1.5us */
3737                 }
3738                 if (i == 4)
3739                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3740         }
3741
3742 train_done:
3743         DRM_DEBUG_KMS("FDI train done.\n");
3744 }
3745
3746 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3747 {
3748         struct drm_device *dev = intel_crtc->base.dev;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         int pipe = intel_crtc->pipe;
3751         i915_reg_t reg;
3752         u32 temp;
3753
3754         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3755         reg = FDI_RX_CTL(pipe);
3756         temp = I915_READ(reg);
3757         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3758         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3759         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3760         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3761
3762         POSTING_READ(reg);
3763         udelay(200);
3764
3765         /* Switch from Rawclk to PCDclk */
3766         temp = I915_READ(reg);
3767         I915_WRITE(reg, temp | FDI_PCDCLK);
3768
3769         POSTING_READ(reg);
3770         udelay(200);
3771
3772         /* Enable CPU FDI TX PLL, always on for Ironlake */
3773         reg = FDI_TX_CTL(pipe);
3774         temp = I915_READ(reg);
3775         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3776                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3777
3778                 POSTING_READ(reg);
3779                 udelay(100);
3780         }
3781 }
3782
3783 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3784 {
3785         struct drm_device *dev = intel_crtc->base.dev;
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787         int pipe = intel_crtc->pipe;
3788         i915_reg_t reg;
3789         u32 temp;
3790
3791         /* Switch from PCDclk to Rawclk */
3792         reg = FDI_RX_CTL(pipe);
3793         temp = I915_READ(reg);
3794         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3795
3796         /* Disable CPU FDI TX PLL */
3797         reg = FDI_TX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3800
3801         POSTING_READ(reg);
3802         udelay(100);
3803
3804         reg = FDI_RX_CTL(pipe);
3805         temp = I915_READ(reg);
3806         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3807
3808         /* Wait for the clocks to turn off. */
3809         POSTING_READ(reg);
3810         udelay(100);
3811 }
3812
3813 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3814 {
3815         struct drm_device *dev = crtc->dev;
3816         struct drm_i915_private *dev_priv = dev->dev_private;
3817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3818         int pipe = intel_crtc->pipe;
3819         i915_reg_t reg;
3820         u32 temp;
3821
3822         /* disable CPU FDI tx and PCH FDI rx */
3823         reg = FDI_TX_CTL(pipe);
3824         temp = I915_READ(reg);
3825         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3826         POSTING_READ(reg);
3827
3828         reg = FDI_RX_CTL(pipe);
3829         temp = I915_READ(reg);
3830         temp &= ~(0x7 << 16);
3831         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3832         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3833
3834         POSTING_READ(reg);
3835         udelay(100);
3836
3837         /* Ironlake workaround, disable clock pointer after downing FDI */
3838         if (HAS_PCH_IBX(dev))
3839                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3840
3841         /* still set train pattern 1 */
3842         reg = FDI_TX_CTL(pipe);
3843         temp = I915_READ(reg);
3844         temp &= ~FDI_LINK_TRAIN_NONE;
3845         temp |= FDI_LINK_TRAIN_PATTERN_1;
3846         I915_WRITE(reg, temp);
3847
3848         reg = FDI_RX_CTL(pipe);
3849         temp = I915_READ(reg);
3850         if (HAS_PCH_CPT(dev)) {
3851                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3852                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3853         } else {
3854                 temp &= ~FDI_LINK_TRAIN_NONE;
3855                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3856         }
3857         /* BPC in FDI rx is consistent with that in PIPECONF */
3858         temp &= ~(0x07 << 16);
3859         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3860         I915_WRITE(reg, temp);
3861
3862         POSTING_READ(reg);
3863         udelay(100);
3864 }
3865
3866 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3867 {
3868         struct intel_crtc *crtc;
3869
3870         /* Note that we don't need to be called with mode_config.lock here
3871          * as our list of CRTC objects is static for the lifetime of the
3872          * device and so cannot disappear as we iterate. Similarly, we can
3873          * happily treat the predicates as racy, atomic checks as userspace
3874          * cannot claim and pin a new fb without at least acquring the
3875          * struct_mutex and so serialising with us.
3876          */
3877         for_each_intel_crtc(dev, crtc) {
3878                 if (atomic_read(&crtc->unpin_work_count) == 0)
3879                         continue;
3880
3881                 if (crtc->unpin_work)
3882                         intel_wait_for_vblank(dev, crtc->pipe);
3883
3884                 return true;
3885         }
3886
3887         return false;
3888 }
3889
3890 static void page_flip_completed(struct intel_crtc *intel_crtc)
3891 {
3892         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3893         struct intel_unpin_work *work = intel_crtc->unpin_work;
3894
3895         /* ensure that the unpin work is consistent wrt ->pending. */
3896         smp_rmb();
3897         intel_crtc->unpin_work = NULL;
3898
3899         if (work->event)
3900                 drm_send_vblank_event(intel_crtc->base.dev,
3901                                       intel_crtc->pipe,
3902                                       work->event);
3903
3904         drm_crtc_vblank_put(&intel_crtc->base);
3905
3906         wake_up_all(&dev_priv->pending_flip_queue);
3907         queue_work(dev_priv->wq, &work->work);
3908
3909         trace_i915_flip_complete(intel_crtc->plane,
3910                                  work->pending_flip_obj);
3911 }
3912
3913 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3914 {
3915         struct drm_device *dev = crtc->dev;
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         long ret;
3918
3919         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3920
3921         ret = wait_event_interruptible_timeout(
3922                                         dev_priv->pending_flip_queue,
3923                                         !intel_crtc_has_pending_flip(crtc),
3924                                         60*HZ);
3925
3926         if (ret < 0)
3927                 return ret;
3928
3929         if (ret == 0) {
3930                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931
3932                 spin_lock_irq(&dev->event_lock);
3933                 if (intel_crtc->unpin_work) {
3934                         WARN_ONCE(1, "Removing stuck page flip\n");
3935                         page_flip_completed(intel_crtc);
3936                 }
3937                 spin_unlock_irq(&dev->event_lock);
3938         }
3939
3940         return 0;
3941 }
3942
3943 /* Program iCLKIP clock to the desired frequency */
3944 static void lpt_program_iclkip(struct drm_crtc *crtc)
3945 {
3946         struct drm_device *dev = crtc->dev;
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3949         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3950         u32 temp;
3951
3952         mutex_lock(&dev_priv->sb_lock);
3953
3954         /* It is necessary to ungate the pixclk gate prior to programming
3955          * the divisors, and gate it back when it is done.
3956          */
3957         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3958
3959         /* Disable SSCCTL */
3960         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3961                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3962                                 SBI_SSCCTL_DISABLE,
3963                         SBI_ICLK);
3964
3965         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3966         if (clock == 20000) {
3967                 auxdiv = 1;
3968                 divsel = 0x41;
3969                 phaseinc = 0x20;
3970         } else {
3971                 /* The iCLK virtual clock root frequency is in MHz,
3972                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3973                  * divisors, it is necessary to divide one by another, so we
3974                  * convert the virtual clock precision to KHz here for higher
3975                  * precision.
3976                  */
3977                 u32 iclk_virtual_root_freq = 172800 * 1000;
3978                 u32 iclk_pi_range = 64;
3979                 u32 desired_divisor, msb_divisor_value, pi_value;
3980
3981                 desired_divisor = (iclk_virtual_root_freq / clock);
3982                 msb_divisor_value = desired_divisor / iclk_pi_range;
3983                 pi_value = desired_divisor % iclk_pi_range;
3984
3985                 auxdiv = 0;
3986                 divsel = msb_divisor_value - 2;
3987                 phaseinc = pi_value;
3988         }
3989
3990         /* This should not happen with any sane values */
3991         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3992                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3993         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3994                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3995
3996         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3997                         clock,
3998                         auxdiv,
3999                         divsel,
4000                         phasedir,
4001                         phaseinc);
4002
4003         /* Program SSCDIVINTPHASE6 */
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4006         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4007         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4008         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4009         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4010         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4011         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4012
4013         /* Program SSCAUXDIV */
4014         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4015         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4016         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4017         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4018
4019         /* Enable modulator and associated divider */
4020         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4021         temp &= ~SBI_SSCCTL_DISABLE;
4022         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4023
4024         /* Wait for initialization time */
4025         udelay(24);
4026
4027         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4028
4029         mutex_unlock(&dev_priv->sb_lock);
4030 }
4031
4032 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4033                                                 enum pipe pch_transcoder)
4034 {
4035         struct drm_device *dev = crtc->base.dev;
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4038
4039         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4040                    I915_READ(HTOTAL(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4042                    I915_READ(HBLANK(cpu_transcoder)));
4043         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4044                    I915_READ(HSYNC(cpu_transcoder)));
4045
4046         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4047                    I915_READ(VTOTAL(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4049                    I915_READ(VBLANK(cpu_transcoder)));
4050         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4051                    I915_READ(VSYNC(cpu_transcoder)));
4052         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4053                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4054 }
4055
4056 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4057 {
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059         uint32_t temp;
4060
4061         temp = I915_READ(SOUTH_CHICKEN1);
4062         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4063                 return;
4064
4065         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4066         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4067
4068         temp &= ~FDI_BC_BIFURCATION_SELECT;
4069         if (enable)
4070                 temp |= FDI_BC_BIFURCATION_SELECT;
4071
4072         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4073         I915_WRITE(SOUTH_CHICKEN1, temp);
4074         POSTING_READ(SOUTH_CHICKEN1);
4075 }
4076
4077 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4078 {
4079         struct drm_device *dev = intel_crtc->base.dev;
4080
4081         switch (intel_crtc->pipe) {
4082         case PIPE_A:
4083                 break;
4084         case PIPE_B:
4085                 if (intel_crtc->config->fdi_lanes > 2)
4086                         cpt_set_fdi_bc_bifurcation(dev, false);
4087                 else
4088                         cpt_set_fdi_bc_bifurcation(dev, true);
4089
4090                 break;
4091         case PIPE_C:
4092                 cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094                 break;
4095         default:
4096                 BUG();
4097         }
4098 }
4099
4100 /* Return which DP Port should be selected for Transcoder DP control */
4101 static enum port
4102 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4103 {
4104         struct drm_device *dev = crtc->dev;
4105         struct intel_encoder *encoder;
4106
4107         for_each_encoder_on_crtc(dev, crtc, encoder) {
4108                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4109                     encoder->type == INTEL_OUTPUT_EDP)
4110                         return enc_to_dig_port(&encoder->base)->port;
4111         }
4112
4113         return -1;
4114 }
4115
4116 /*
4117  * Enable PCH resources required for PCH ports:
4118  *   - PCH PLLs
4119  *   - FDI training & RX/TX
4120  *   - update transcoder timings
4121  *   - DP transcoding bits
4122  *   - transcoder
4123  */
4124 static void ironlake_pch_enable(struct drm_crtc *crtc)
4125 {
4126         struct drm_device *dev = crtc->dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129         int pipe = intel_crtc->pipe;
4130         u32 temp;
4131
4132         assert_pch_transcoder_disabled(dev_priv, pipe);
4133
4134         if (IS_IVYBRIDGE(dev))
4135                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4136
4137         /* Write the TU size bits before fdi link training, so that error
4138          * detection works. */
4139         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4140                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4141
4142         /*
4143          * Sometimes spurious CPU pipe underruns happen during FDI
4144          * training, at least with VGA+HDMI cloning. Suppress them.
4145          */
4146         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4147
4148         /* For PCH output, training FDI link */
4149         dev_priv->display.fdi_link_train(crtc);
4150
4151         /* We need to program the right clock selection before writing the pixel
4152          * mutliplier into the DPLL. */
4153         if (HAS_PCH_CPT(dev)) {
4154                 u32 sel;
4155
4156                 temp = I915_READ(PCH_DPLL_SEL);
4157                 temp |= TRANS_DPLL_ENABLE(pipe);
4158                 sel = TRANS_DPLLB_SEL(pipe);
4159                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4160                         temp |= sel;
4161                 else
4162                         temp &= ~sel;
4163                 I915_WRITE(PCH_DPLL_SEL, temp);
4164         }
4165
4166         /* XXX: pch pll's can be enabled any time before we enable the PCH
4167          * transcoder, and we actually should do this to not upset any PCH
4168          * transcoder that already use the clock when we share it.
4169          *
4170          * Note that enable_shared_dpll tries to do the right thing, but
4171          * get_shared_dpll unconditionally resets the pll - we need that to have
4172          * the right LVDS enable sequence. */
4173         intel_enable_shared_dpll(intel_crtc);
4174
4175         /* set transcoder timing, panel must allow it */
4176         assert_panel_unlocked(dev_priv, pipe);
4177         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4178
4179         intel_fdi_normal_train(crtc);
4180
4181         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4182
4183         /* For PCH DP, enable TRANS_DP_CTL */
4184         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4185                 const struct drm_display_mode *adjusted_mode =
4186                         &intel_crtc->config->base.adjusted_mode;
4187                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4188                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4189                 temp = I915_READ(reg);
4190                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4191                           TRANS_DP_SYNC_MASK |
4192                           TRANS_DP_BPC_MASK);
4193                 temp |= TRANS_DP_OUTPUT_ENABLE;
4194                 temp |= bpc << 9; /* same format but at 11:9 */
4195
4196                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4197                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4198                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4199                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4200
4201                 switch (intel_trans_dp_port_sel(crtc)) {
4202                 case PORT_B:
4203                         temp |= TRANS_DP_PORT_SEL_B;
4204                         break;
4205                 case PORT_C:
4206                         temp |= TRANS_DP_PORT_SEL_C;
4207                         break;
4208                 case PORT_D:
4209                         temp |= TRANS_DP_PORT_SEL_D;
4210                         break;
4211                 default:
4212                         BUG();
4213                 }
4214
4215                 I915_WRITE(reg, temp);
4216         }
4217
4218         ironlake_enable_pch_transcoder(dev_priv, pipe);
4219 }
4220
4221 static void lpt_pch_enable(struct drm_crtc *crtc)
4222 {
4223         struct drm_device *dev = crtc->dev;
4224         struct drm_i915_private *dev_priv = dev->dev_private;
4225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4226         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4227
4228         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4229
4230         lpt_program_iclkip(crtc);
4231
4232         /* Set transcoder timing. */
4233         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4234
4235         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4236 }
4237
4238 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4239                                                 struct intel_crtc_state *crtc_state)
4240 {
4241         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4242         struct intel_shared_dpll *pll;
4243         struct intel_shared_dpll_config *shared_dpll;
4244         enum intel_dpll_id i;
4245         int max = dev_priv->num_shared_dpll;
4246
4247         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4248
4249         if (HAS_PCH_IBX(dev_priv->dev)) {
4250                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4251                 i = (enum intel_dpll_id) crtc->pipe;
4252                 pll = &dev_priv->shared_dplls[i];
4253
4254                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4255                               crtc->base.base.id, pll->name);
4256
4257                 WARN_ON(shared_dpll[i].crtc_mask);
4258
4259                 goto found;
4260         }
4261
4262         if (IS_BROXTON(dev_priv->dev)) {
4263                 /* PLL is attached to port in bxt */
4264                 struct intel_encoder *encoder;
4265                 struct intel_digital_port *intel_dig_port;
4266
4267                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4268                 if (WARN_ON(!encoder))
4269                         return NULL;
4270
4271                 intel_dig_port = enc_to_dig_port(&encoder->base);
4272                 /* 1:1 mapping between ports and PLLs */
4273                 i = (enum intel_dpll_id)intel_dig_port->port;
4274                 pll = &dev_priv->shared_dplls[i];
4275                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4276                         crtc->base.base.id, pll->name);
4277                 WARN_ON(shared_dpll[i].crtc_mask);
4278
4279                 goto found;
4280         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4281                 /* Do not consider SPLL */
4282                 max = 2;
4283
4284         for (i = 0; i < max; i++) {
4285                 pll = &dev_priv->shared_dplls[i];
4286
4287                 /* Only want to check enabled timings first */
4288                 if (shared_dpll[i].crtc_mask == 0)
4289                         continue;
4290
4291                 if (memcmp(&crtc_state->dpll_hw_state,
4292                            &shared_dpll[i].hw_state,
4293                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4294                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4295                                       crtc->base.base.id, pll->name,
4296                                       shared_dpll[i].crtc_mask,
4297                                       pll->active);
4298                         goto found;
4299                 }
4300         }
4301
4302         /* Ok no matching timings, maybe there's a free one? */
4303         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4304                 pll = &dev_priv->shared_dplls[i];
4305                 if (shared_dpll[i].crtc_mask == 0) {
4306                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4307                                       crtc->base.base.id, pll->name);
4308                         goto found;
4309                 }
4310         }
4311
4312         return NULL;
4313
4314 found:
4315         if (shared_dpll[i].crtc_mask == 0)
4316                 shared_dpll[i].hw_state =
4317                         crtc_state->dpll_hw_state;
4318
4319         crtc_state->shared_dpll = i;
4320         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4321                          pipe_name(crtc->pipe));
4322
4323         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4324
4325         return pll;
4326 }
4327
4328 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4329 {
4330         struct drm_i915_private *dev_priv = to_i915(state->dev);
4331         struct intel_shared_dpll_config *shared_dpll;
4332         struct intel_shared_dpll *pll;
4333         enum intel_dpll_id i;
4334
4335         if (!to_intel_atomic_state(state)->dpll_set)
4336                 return;
4337
4338         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4339         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4340                 pll = &dev_priv->shared_dplls[i];
4341                 pll->config = shared_dpll[i];
4342         }
4343 }
4344
4345 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4346 {
4347         struct drm_i915_private *dev_priv = dev->dev_private;
4348         i915_reg_t dslreg = PIPEDSL(pipe);
4349         u32 temp;
4350
4351         temp = I915_READ(dslreg);
4352         udelay(500);
4353         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4354                 if (wait_for(I915_READ(dslreg) != temp, 5))
4355                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4356         }
4357 }
4358
4359 static int
4360 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4361                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4362                   int src_w, int src_h, int dst_w, int dst_h)
4363 {
4364         struct intel_crtc_scaler_state *scaler_state =
4365                 &crtc_state->scaler_state;
4366         struct intel_crtc *intel_crtc =
4367                 to_intel_crtc(crtc_state->base.crtc);
4368         int need_scaling;
4369
4370         need_scaling = intel_rotation_90_or_270(rotation) ?
4371                 (src_h != dst_w || src_w != dst_h):
4372                 (src_w != dst_w || src_h != dst_h);
4373
4374         /*
4375          * if plane is being disabled or scaler is no more required or force detach
4376          *  - free scaler binded to this plane/crtc
4377          *  - in order to do this, update crtc->scaler_usage
4378          *
4379          * Here scaler state in crtc_state is set free so that
4380          * scaler can be assigned to other user. Actual register
4381          * update to free the scaler is done in plane/panel-fit programming.
4382          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4383          */
4384         if (force_detach || !need_scaling) {
4385                 if (*scaler_id >= 0) {
4386                         scaler_state->scaler_users &= ~(1 << scaler_user);
4387                         scaler_state->scalers[*scaler_id].in_use = 0;
4388
4389                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4390                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4391                                 intel_crtc->pipe, scaler_user, *scaler_id,
4392                                 scaler_state->scaler_users);
4393                         *scaler_id = -1;
4394                 }
4395                 return 0;
4396         }
4397
4398         /* range checks */
4399         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4400                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4401
4402                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4403                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4404                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4405                         "size is out of scaler range\n",
4406                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4407                 return -EINVAL;
4408         }
4409
4410         /* mark this plane as a scaler user in crtc_state */
4411         scaler_state->scaler_users |= (1 << scaler_user);
4412         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4413                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4414                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4415                 scaler_state->scaler_users);
4416
4417         return 0;
4418 }
4419
4420 /**
4421  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4422  *
4423  * @state: crtc's scaler state
4424  *
4425  * Return
4426  *     0 - scaler_usage updated successfully
4427  *    error - requested scaling cannot be supported or other error condition
4428  */
4429 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4430 {
4431         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4432         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4433
4434         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4435                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4436
4437         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4438                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4439                 state->pipe_src_w, state->pipe_src_h,
4440                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4441 }
4442
4443 /**
4444  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4445  *
4446  * @state: crtc's scaler state
4447  * @plane_state: atomic plane state to update
4448  *
4449  * Return
4450  *     0 - scaler_usage updated successfully
4451  *    error - requested scaling cannot be supported or other error condition
4452  */
4453 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4454                                    struct intel_plane_state *plane_state)
4455 {
4456
4457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4458         struct intel_plane *intel_plane =
4459                 to_intel_plane(plane_state->base.plane);
4460         struct drm_framebuffer *fb = plane_state->base.fb;
4461         int ret;
4462
4463         bool force_detach = !fb || !plane_state->visible;
4464
4465         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4466                       intel_plane->base.base.id, intel_crtc->pipe,
4467                       drm_plane_index(&intel_plane->base));
4468
4469         ret = skl_update_scaler(crtc_state, force_detach,
4470                                 drm_plane_index(&intel_plane->base),
4471                                 &plane_state->scaler_id,
4472                                 plane_state->base.rotation,
4473                                 drm_rect_width(&plane_state->src) >> 16,
4474                                 drm_rect_height(&plane_state->src) >> 16,
4475                                 drm_rect_width(&plane_state->dst),
4476                                 drm_rect_height(&plane_state->dst));
4477
4478         if (ret || plane_state->scaler_id < 0)
4479                 return ret;
4480
4481         /* check colorkey */
4482         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4483                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4484                               intel_plane->base.base.id);
4485                 return -EINVAL;
4486         }
4487
4488         /* Check src format */
4489         switch (fb->pixel_format) {
4490         case DRM_FORMAT_RGB565:
4491         case DRM_FORMAT_XBGR8888:
4492         case DRM_FORMAT_XRGB8888:
4493         case DRM_FORMAT_ABGR8888:
4494         case DRM_FORMAT_ARGB8888:
4495         case DRM_FORMAT_XRGB2101010:
4496         case DRM_FORMAT_XBGR2101010:
4497         case DRM_FORMAT_YUYV:
4498         case DRM_FORMAT_YVYU:
4499         case DRM_FORMAT_UYVY:
4500         case DRM_FORMAT_VYUY:
4501                 break;
4502         default:
4503                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4504                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4505                 return -EINVAL;
4506         }
4507
4508         return 0;
4509 }
4510
4511 static void skylake_scaler_disable(struct intel_crtc *crtc)
4512 {
4513         int i;
4514
4515         for (i = 0; i < crtc->num_scalers; i++)
4516                 skl_detach_scaler(crtc, i);
4517 }
4518
4519 static void skylake_pfit_enable(struct intel_crtc *crtc)
4520 {
4521         struct drm_device *dev = crtc->base.dev;
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         int pipe = crtc->pipe;
4524         struct intel_crtc_scaler_state *scaler_state =
4525                 &crtc->config->scaler_state;
4526
4527         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4528
4529         if (crtc->config->pch_pfit.enabled) {
4530                 int id;
4531
4532                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4533                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4534                         return;
4535                 }
4536
4537                 id = scaler_state->scaler_id;
4538                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4539                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4540                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4541                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4542
4543                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4544         }
4545 }
4546
4547 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4548 {
4549         struct drm_device *dev = crtc->base.dev;
4550         struct drm_i915_private *dev_priv = dev->dev_private;
4551         int pipe = crtc->pipe;
4552
4553         if (crtc->config->pch_pfit.enabled) {
4554                 /* Force use of hard-coded filter coefficients
4555                  * as some pre-programmed values are broken,
4556                  * e.g. x201.
4557                  */
4558                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4559                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4560                                                  PF_PIPE_SEL_IVB(pipe));
4561                 else
4562                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4563                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4564                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4565         }
4566 }
4567
4568 void hsw_enable_ips(struct intel_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572
4573         if (!crtc->config->ips_enabled)
4574                 return;
4575
4576         /* We can only enable IPS after we enable a plane and wait for a vblank */
4577         intel_wait_for_vblank(dev, crtc->pipe);
4578
4579         assert_plane_enabled(dev_priv, crtc->plane);
4580         if (IS_BROADWELL(dev)) {
4581                 mutex_lock(&dev_priv->rps.hw_lock);
4582                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4583                 mutex_unlock(&dev_priv->rps.hw_lock);
4584                 /* Quoting Art Runyan: "its not safe to expect any particular
4585                  * value in IPS_CTL bit 31 after enabling IPS through the
4586                  * mailbox." Moreover, the mailbox may return a bogus state,
4587                  * so we need to just enable it and continue on.
4588                  */
4589         } else {
4590                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4591                 /* The bit only becomes 1 in the next vblank, so this wait here
4592                  * is essentially intel_wait_for_vblank. If we don't have this
4593                  * and don't wait for vblanks until the end of crtc_enable, then
4594                  * the HW state readout code will complain that the expected
4595                  * IPS_CTL value is not the one we read. */
4596                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4597                         DRM_ERROR("Timed out waiting for IPS enable\n");
4598         }
4599 }
4600
4601 void hsw_disable_ips(struct intel_crtc *crtc)
4602 {
4603         struct drm_device *dev = crtc->base.dev;
4604         struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606         if (!crtc->config->ips_enabled)
4607                 return;
4608
4609         assert_plane_enabled(dev_priv, crtc->plane);
4610         if (IS_BROADWELL(dev)) {
4611                 mutex_lock(&dev_priv->rps.hw_lock);
4612                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4613                 mutex_unlock(&dev_priv->rps.hw_lock);
4614                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4615                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4616                         DRM_ERROR("Timed out waiting for IPS disable\n");
4617         } else {
4618                 I915_WRITE(IPS_CTL, 0);
4619                 POSTING_READ(IPS_CTL);
4620         }
4621
4622         /* We need to wait for a vblank before we can disable the plane. */
4623         intel_wait_for_vblank(dev, crtc->pipe);
4624 }
4625
4626 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4627 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4628 {
4629         struct drm_device *dev = crtc->dev;
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632         enum pipe pipe = intel_crtc->pipe;
4633         int i;
4634         bool reenable_ips = false;
4635
4636         /* The clocks have to be on to load the palette. */
4637         if (!crtc->state->active)
4638                 return;
4639
4640         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4641                 if (intel_crtc->config->has_dsi_encoder)
4642                         assert_dsi_pll_enabled(dev_priv);
4643                 else
4644                         assert_pll_enabled(dev_priv, pipe);
4645         }
4646
4647         /* Workaround : Do not read or write the pipe palette/gamma data while
4648          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4649          */
4650         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4651             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4652              GAMMA_MODE_MODE_SPLIT)) {
4653                 hsw_disable_ips(intel_crtc);
4654                 reenable_ips = true;
4655         }
4656
4657         for (i = 0; i < 256; i++) {
4658                 i915_reg_t palreg;
4659
4660                 if (HAS_GMCH_DISPLAY(dev))
4661                         palreg = PALETTE(pipe, i);
4662                 else
4663                         palreg = LGC_PALETTE(pipe, i);
4664
4665                 I915_WRITE(palreg,
4666                            (intel_crtc->lut_r[i] << 16) |
4667                            (intel_crtc->lut_g[i] << 8) |
4668                            intel_crtc->lut_b[i]);
4669         }
4670
4671         if (reenable_ips)
4672                 hsw_enable_ips(intel_crtc);
4673 }
4674
4675 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4676 {
4677         if (intel_crtc->overlay) {
4678                 struct drm_device *dev = intel_crtc->base.dev;
4679                 struct drm_i915_private *dev_priv = dev->dev_private;
4680
4681                 mutex_lock(&dev->struct_mutex);
4682                 dev_priv->mm.interruptible = false;
4683                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4684                 dev_priv->mm.interruptible = true;
4685                 mutex_unlock(&dev->struct_mutex);
4686         }
4687
4688         /* Let userspace switch the overlay on again. In most cases userspace
4689          * has to recompute where to put it anyway.
4690          */
4691 }
4692
4693 /**
4694  * intel_post_enable_primary - Perform operations after enabling primary plane
4695  * @crtc: the CRTC whose primary plane was just enabled
4696  *
4697  * Performs potentially sleeping operations that must be done after the primary
4698  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4699  * called due to an explicit primary plane update, or due to an implicit
4700  * re-enable that is caused when a sprite plane is updated to no longer
4701  * completely hide the primary plane.
4702  */
4703 static void
4704 intel_post_enable_primary(struct drm_crtc *crtc)
4705 {
4706         struct drm_device *dev = crtc->dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         int pipe = intel_crtc->pipe;
4710
4711         /*
4712          * BDW signals flip done immediately if the plane
4713          * is disabled, even if the plane enable is already
4714          * armed to occur at the next vblank :(
4715          */
4716         if (IS_BROADWELL(dev))
4717                 intel_wait_for_vblank(dev, pipe);
4718
4719         /*
4720          * FIXME IPS should be fine as long as one plane is
4721          * enabled, but in practice it seems to have problems
4722          * when going from primary only to sprite only and vice
4723          * versa.
4724          */
4725         hsw_enable_ips(intel_crtc);
4726
4727         /*
4728          * Gen2 reports pipe underruns whenever all planes are disabled.
4729          * So don't enable underrun reporting before at least some planes
4730          * are enabled.
4731          * FIXME: Need to fix the logic to work when we turn off all planes
4732          * but leave the pipe running.
4733          */
4734         if (IS_GEN2(dev))
4735                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4736
4737         /* Underruns don't always raise interrupts, so check manually. */
4738         intel_check_cpu_fifo_underruns(dev_priv);
4739         intel_check_pch_fifo_underruns(dev_priv);
4740 }
4741
4742 /**
4743  * intel_pre_disable_primary - Perform operations before disabling primary plane
4744  * @crtc: the CRTC whose primary plane is to be disabled
4745  *
4746  * Performs potentially sleeping operations that must be done before the
4747  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4748  * be called due to an explicit primary plane update, or due to an implicit
4749  * disable that is caused when a sprite plane completely hides the primary
4750  * plane.
4751  */
4752 static void
4753 intel_pre_disable_primary(struct drm_crtc *crtc)
4754 {
4755         struct drm_device *dev = crtc->dev;
4756         struct drm_i915_private *dev_priv = dev->dev_private;
4757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4758         int pipe = intel_crtc->pipe;
4759
4760         /*
4761          * Gen2 reports pipe underruns whenever all planes are disabled.
4762          * So diasble underrun reporting before all the planes get disabled.
4763          * FIXME: Need to fix the logic to work when we turn off all planes
4764          * but leave the pipe running.
4765          */
4766         if (IS_GEN2(dev))
4767                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4768
4769         /*
4770          * Vblank time updates from the shadow to live plane control register
4771          * are blocked if the memory self-refresh mode is active at that
4772          * moment. So to make sure the plane gets truly disabled, disable
4773          * first the self-refresh mode. The self-refresh enable bit in turn
4774          * will be checked/applied by the HW only at the next frame start
4775          * event which is after the vblank start event, so we need to have a
4776          * wait-for-vblank between disabling the plane and the pipe.
4777          */
4778         if (HAS_GMCH_DISPLAY(dev)) {
4779                 intel_set_memory_cxsr(dev_priv, false);
4780                 dev_priv->wm.vlv.cxsr = false;
4781                 intel_wait_for_vblank(dev, pipe);
4782         }
4783
4784         /*
4785          * FIXME IPS should be fine as long as one plane is
4786          * enabled, but in practice it seems to have problems
4787          * when going from primary only to sprite only and vice
4788          * versa.
4789          */
4790         hsw_disable_ips(intel_crtc);
4791 }
4792
4793 static void intel_post_plane_update(struct intel_crtc *crtc)
4794 {
4795         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4796         struct drm_device *dev = crtc->base.dev;
4797
4798         if (atomic->wait_vblank)
4799                 intel_wait_for_vblank(dev, crtc->pipe);
4800
4801         intel_frontbuffer_flip(dev, atomic->fb_bits);
4802
4803         if (atomic->disable_cxsr)
4804                 crtc->wm.cxsr_allowed = true;
4805
4806         if (crtc->atomic.update_wm_post)
4807                 intel_update_watermarks(&crtc->base);
4808
4809         if (atomic->update_fbc)
4810                 intel_fbc_update(crtc);
4811
4812         if (atomic->post_enable_primary)
4813                 intel_post_enable_primary(&crtc->base);
4814
4815         memset(atomic, 0, sizeof(*atomic));
4816 }
4817
4818 static void intel_pre_plane_update(struct intel_crtc *crtc)
4819 {
4820         struct drm_device *dev = crtc->base.dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4823
4824         if (atomic->disable_fbc)
4825                 intel_fbc_deactivate(crtc);
4826
4827         if (crtc->atomic.disable_ips)
4828                 hsw_disable_ips(crtc);
4829
4830         if (atomic->pre_disable_primary)
4831                 intel_pre_disable_primary(&crtc->base);
4832
4833         if (atomic->disable_cxsr) {
4834                 crtc->wm.cxsr_allowed = false;
4835                 intel_set_memory_cxsr(dev_priv, false);
4836         }
4837 }
4838
4839 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4840 {
4841         struct drm_device *dev = crtc->dev;
4842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4843         struct drm_plane *p;
4844         int pipe = intel_crtc->pipe;
4845
4846         intel_crtc_dpms_overlay_disable(intel_crtc);
4847
4848         drm_for_each_plane_mask(p, dev, plane_mask)
4849                 to_intel_plane(p)->disable_plane(p, crtc);
4850
4851         /*
4852          * FIXME: Once we grow proper nuclear flip support out of this we need
4853          * to compute the mask of flip planes precisely. For the time being
4854          * consider this a flip to a NULL plane.
4855          */
4856         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4857 }
4858
4859 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4860 {
4861         struct drm_device *dev = crtc->dev;
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4864         struct intel_encoder *encoder;
4865         int pipe = intel_crtc->pipe;
4866
4867         if (WARN_ON(intel_crtc->active))
4868                 return;
4869
4870         if (intel_crtc->config->has_pch_encoder)
4871                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4872
4873         if (intel_crtc->config->has_pch_encoder)
4874                 intel_prepare_shared_dpll(intel_crtc);
4875
4876         if (intel_crtc->config->has_dp_encoder)
4877                 intel_dp_set_m_n(intel_crtc, M1_N1);
4878
4879         intel_set_pipe_timings(intel_crtc);
4880
4881         if (intel_crtc->config->has_pch_encoder) {
4882                 intel_cpu_transcoder_set_m_n(intel_crtc,
4883                                      &intel_crtc->config->fdi_m_n, NULL);
4884         }
4885
4886         ironlake_set_pipeconf(crtc);
4887
4888         intel_crtc->active = true;
4889
4890         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4891
4892         for_each_encoder_on_crtc(dev, crtc, encoder)
4893                 if (encoder->pre_enable)
4894                         encoder->pre_enable(encoder);
4895
4896         if (intel_crtc->config->has_pch_encoder) {
4897                 /* Note: FDI PLL enabling _must_ be done before we enable the
4898                  * cpu pipes, hence this is separate from all the other fdi/pch
4899                  * enabling. */
4900                 ironlake_fdi_pll_enable(intel_crtc);
4901         } else {
4902                 assert_fdi_tx_disabled(dev_priv, pipe);
4903                 assert_fdi_rx_disabled(dev_priv, pipe);
4904         }
4905
4906         ironlake_pfit_enable(intel_crtc);
4907
4908         /*
4909          * On ILK+ LUT must be loaded before the pipe is running but with
4910          * clocks enabled
4911          */
4912         intel_crtc_load_lut(crtc);
4913
4914         intel_update_watermarks(crtc);
4915         intel_enable_pipe(intel_crtc);
4916
4917         if (intel_crtc->config->has_pch_encoder)
4918                 ironlake_pch_enable(crtc);
4919
4920         assert_vblank_disabled(crtc);
4921         drm_crtc_vblank_on(crtc);
4922
4923         for_each_encoder_on_crtc(dev, crtc, encoder)
4924                 encoder->enable(encoder);
4925
4926         if (HAS_PCH_CPT(dev))
4927                 cpt_verify_modeset(dev, intel_crtc->pipe);
4928
4929         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4930         if (intel_crtc->config->has_pch_encoder)
4931                 intel_wait_for_vblank(dev, pipe);
4932         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4933
4934         intel_fbc_enable(intel_crtc);
4935 }
4936
4937 /* IPS only exists on ULT machines and is tied to pipe A. */
4938 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4939 {
4940         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4941 }
4942
4943 static void haswell_crtc_enable(struct drm_crtc *crtc)
4944 {
4945         struct drm_device *dev = crtc->dev;
4946         struct drm_i915_private *dev_priv = dev->dev_private;
4947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948         struct intel_encoder *encoder;
4949         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4950         struct intel_crtc_state *pipe_config =
4951                 to_intel_crtc_state(crtc->state);
4952
4953         if (WARN_ON(intel_crtc->active))
4954                 return;
4955
4956         if (intel_crtc->config->has_pch_encoder)
4957                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4958                                                       false);
4959
4960         if (intel_crtc_to_shared_dpll(intel_crtc))
4961                 intel_enable_shared_dpll(intel_crtc);
4962
4963         if (intel_crtc->config->has_dp_encoder)
4964                 intel_dp_set_m_n(intel_crtc, M1_N1);
4965
4966         intel_set_pipe_timings(intel_crtc);
4967
4968         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4969                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4970                            intel_crtc->config->pixel_multiplier - 1);
4971         }
4972
4973         if (intel_crtc->config->has_pch_encoder) {
4974                 intel_cpu_transcoder_set_m_n(intel_crtc,
4975                                      &intel_crtc->config->fdi_m_n, NULL);
4976         }
4977
4978         haswell_set_pipeconf(crtc);
4979
4980         intel_set_pipe_csc(crtc);
4981
4982         intel_crtc->active = true;
4983
4984         if (intel_crtc->config->has_pch_encoder)
4985                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4986         else
4987                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988
4989         for_each_encoder_on_crtc(dev, crtc, encoder) {
4990                 if (encoder->pre_enable)
4991                         encoder->pre_enable(encoder);
4992         }
4993
4994         if (intel_crtc->config->has_pch_encoder)
4995                 dev_priv->display.fdi_link_train(crtc);
4996
4997         if (!intel_crtc->config->has_dsi_encoder)
4998                 intel_ddi_enable_pipe_clock(intel_crtc);
4999
5000         if (INTEL_INFO(dev)->gen >= 9)
5001                 skylake_pfit_enable(intel_crtc);
5002         else
5003                 ironlake_pfit_enable(intel_crtc);
5004
5005         /*
5006          * On ILK+ LUT must be loaded before the pipe is running but with
5007          * clocks enabled
5008          */
5009         intel_crtc_load_lut(crtc);
5010
5011         intel_ddi_set_pipe_settings(crtc);
5012         if (!intel_crtc->config->has_dsi_encoder)
5013                 intel_ddi_enable_transcoder_func(crtc);
5014
5015         intel_update_watermarks(crtc);
5016         intel_enable_pipe(intel_crtc);
5017
5018         if (intel_crtc->config->has_pch_encoder)
5019                 lpt_pch_enable(crtc);
5020
5021         if (intel_crtc->config->dp_encoder_is_mst)
5022                 intel_ddi_set_vc_payload_alloc(crtc, true);
5023
5024         assert_vblank_disabled(crtc);
5025         drm_crtc_vblank_on(crtc);
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder) {
5028                 encoder->enable(encoder);
5029                 intel_opregion_notify_encoder(encoder, true);
5030         }
5031
5032         if (intel_crtc->config->has_pch_encoder) {
5033                 intel_wait_for_vblank(dev, pipe);
5034                 intel_wait_for_vblank(dev, pipe);
5035                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5036                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5037                                                       true);
5038         }
5039
5040         /* If we change the relative order between pipe/planes enabling, we need
5041          * to change the workaround. */
5042         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5043         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5044                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5045                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5046         }
5047
5048         intel_fbc_enable(intel_crtc);
5049 }
5050
5051 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5052 {
5053         struct drm_device *dev = crtc->base.dev;
5054         struct drm_i915_private *dev_priv = dev->dev_private;
5055         int pipe = crtc->pipe;
5056
5057         /* To avoid upsetting the power well on haswell only disable the pfit if
5058          * it's in use. The hw state code will make sure we get this right. */
5059         if (force || crtc->config->pch_pfit.enabled) {
5060                 I915_WRITE(PF_CTL(pipe), 0);
5061                 I915_WRITE(PF_WIN_POS(pipe), 0);
5062                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5063         }
5064 }
5065
5066 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5067 {
5068         struct drm_device *dev = crtc->dev;
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071         struct intel_encoder *encoder;
5072         int pipe = intel_crtc->pipe;
5073
5074         if (intel_crtc->config->has_pch_encoder)
5075                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5076
5077         for_each_encoder_on_crtc(dev, crtc, encoder)
5078                 encoder->disable(encoder);
5079
5080         drm_crtc_vblank_off(crtc);
5081         assert_vblank_disabled(crtc);
5082
5083         /*
5084          * Sometimes spurious CPU pipe underruns happen when the
5085          * pipe is already disabled, but FDI RX/TX is still enabled.
5086          * Happens at least with VGA+HDMI cloning. Suppress them.
5087          */
5088         if (intel_crtc->config->has_pch_encoder)
5089                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5090
5091         intel_disable_pipe(intel_crtc);
5092
5093         ironlake_pfit_disable(intel_crtc, false);
5094
5095         if (intel_crtc->config->has_pch_encoder) {
5096                 ironlake_fdi_disable(crtc);
5097                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5098         }
5099
5100         for_each_encoder_on_crtc(dev, crtc, encoder)
5101                 if (encoder->post_disable)
5102                         encoder->post_disable(encoder);
5103
5104         if (intel_crtc->config->has_pch_encoder) {
5105                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5106
5107                 if (HAS_PCH_CPT(dev)) {
5108                         i915_reg_t reg;
5109                         u32 temp;
5110
5111                         /* disable TRANS_DP_CTL */
5112                         reg = TRANS_DP_CTL(pipe);
5113                         temp = I915_READ(reg);
5114                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5115                                   TRANS_DP_PORT_SEL_MASK);
5116                         temp |= TRANS_DP_PORT_SEL_NONE;
5117                         I915_WRITE(reg, temp);
5118
5119                         /* disable DPLL_SEL */
5120                         temp = I915_READ(PCH_DPLL_SEL);
5121                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5122                         I915_WRITE(PCH_DPLL_SEL, temp);
5123                 }
5124
5125                 ironlake_fdi_pll_disable(intel_crtc);
5126         }
5127
5128         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5129
5130         intel_fbc_disable_crtc(intel_crtc);
5131 }
5132
5133 static void haswell_crtc_disable(struct drm_crtc *crtc)
5134 {
5135         struct drm_device *dev = crtc->dev;
5136         struct drm_i915_private *dev_priv = dev->dev_private;
5137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5138         struct intel_encoder *encoder;
5139         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5140
5141         if (intel_crtc->config->has_pch_encoder)
5142                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5143                                                       false);
5144
5145         for_each_encoder_on_crtc(dev, crtc, encoder) {
5146                 intel_opregion_notify_encoder(encoder, false);
5147                 encoder->disable(encoder);
5148         }
5149
5150         drm_crtc_vblank_off(crtc);
5151         assert_vblank_disabled(crtc);
5152
5153         intel_disable_pipe(intel_crtc);
5154
5155         if (intel_crtc->config->dp_encoder_is_mst)
5156                 intel_ddi_set_vc_payload_alloc(crtc, false);
5157
5158         if (!intel_crtc->config->has_dsi_encoder)
5159                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5160
5161         if (INTEL_INFO(dev)->gen >= 9)
5162                 skylake_scaler_disable(intel_crtc);
5163         else
5164                 ironlake_pfit_disable(intel_crtc, false);
5165
5166         if (!intel_crtc->config->has_dsi_encoder)
5167                 intel_ddi_disable_pipe_clock(intel_crtc);
5168
5169         if (intel_crtc->config->has_pch_encoder) {
5170                 lpt_disable_pch_transcoder(dev_priv);
5171                 intel_ddi_fdi_disable(crtc);
5172         }
5173
5174         for_each_encoder_on_crtc(dev, crtc, encoder)
5175                 if (encoder->post_disable)
5176                         encoder->post_disable(encoder);
5177
5178         if (intel_crtc->config->has_pch_encoder)
5179                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5180                                                       true);
5181
5182         intel_fbc_disable_crtc(intel_crtc);
5183 }
5184
5185 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5186 {
5187         struct drm_device *dev = crtc->base.dev;
5188         struct drm_i915_private *dev_priv = dev->dev_private;
5189         struct intel_crtc_state *pipe_config = crtc->config;
5190
5191         if (!pipe_config->gmch_pfit.control)
5192                 return;
5193
5194         /*
5195          * The panel fitter should only be adjusted whilst the pipe is disabled,
5196          * according to register description and PRM.
5197          */
5198         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5199         assert_pipe_disabled(dev_priv, crtc->pipe);
5200
5201         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5202         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5203
5204         /* Border color in case we don't scale up to the full screen. Black by
5205          * default, change to something else for debugging. */
5206         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5207 }
5208
5209 static enum intel_display_power_domain port_to_power_domain(enum port port)
5210 {
5211         switch (port) {
5212         case PORT_A:
5213                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5214         case PORT_B:
5215                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5216         case PORT_C:
5217                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5218         case PORT_D:
5219                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5220         case PORT_E:
5221                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5222         default:
5223                 MISSING_CASE(port);
5224                 return POWER_DOMAIN_PORT_OTHER;
5225         }
5226 }
5227
5228 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5229 {
5230         switch (port) {
5231         case PORT_A:
5232                 return POWER_DOMAIN_AUX_A;
5233         case PORT_B:
5234                 return POWER_DOMAIN_AUX_B;
5235         case PORT_C:
5236                 return POWER_DOMAIN_AUX_C;
5237         case PORT_D:
5238                 return POWER_DOMAIN_AUX_D;
5239         case PORT_E:
5240                 /* FIXME: Check VBT for actual wiring of PORT E */
5241                 return POWER_DOMAIN_AUX_D;
5242         default:
5243                 MISSING_CASE(port);
5244                 return POWER_DOMAIN_AUX_A;
5245         }
5246 }
5247
5248 enum intel_display_power_domain
5249 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5250 {
5251         struct drm_device *dev = intel_encoder->base.dev;
5252         struct intel_digital_port *intel_dig_port;
5253
5254         switch (intel_encoder->type) {
5255         case INTEL_OUTPUT_UNKNOWN:
5256                 /* Only DDI platforms should ever use this output type */
5257                 WARN_ON_ONCE(!HAS_DDI(dev));
5258         case INTEL_OUTPUT_DISPLAYPORT:
5259         case INTEL_OUTPUT_HDMI:
5260         case INTEL_OUTPUT_EDP:
5261                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5262                 return port_to_power_domain(intel_dig_port->port);
5263         case INTEL_OUTPUT_DP_MST:
5264                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5265                 return port_to_power_domain(intel_dig_port->port);
5266         case INTEL_OUTPUT_ANALOG:
5267                 return POWER_DOMAIN_PORT_CRT;
5268         case INTEL_OUTPUT_DSI:
5269                 return POWER_DOMAIN_PORT_DSI;
5270         default:
5271                 return POWER_DOMAIN_PORT_OTHER;
5272         }
5273 }
5274
5275 enum intel_display_power_domain
5276 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5277 {
5278         struct drm_device *dev = intel_encoder->base.dev;
5279         struct intel_digital_port *intel_dig_port;
5280
5281         switch (intel_encoder->type) {
5282         case INTEL_OUTPUT_UNKNOWN:
5283         case INTEL_OUTPUT_HDMI:
5284                 /*
5285                  * Only DDI platforms should ever use these output types.
5286                  * We can get here after the HDMI detect code has already set
5287                  * the type of the shared encoder. Since we can't be sure
5288                  * what's the status of the given connectors, play safe and
5289                  * run the DP detection too.
5290                  */
5291                 WARN_ON_ONCE(!HAS_DDI(dev));
5292         case INTEL_OUTPUT_DISPLAYPORT:
5293         case INTEL_OUTPUT_EDP:
5294                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5295                 return port_to_aux_power_domain(intel_dig_port->port);
5296         case INTEL_OUTPUT_DP_MST:
5297                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5298                 return port_to_aux_power_domain(intel_dig_port->port);
5299         default:
5300                 MISSING_CASE(intel_encoder->type);
5301                 return POWER_DOMAIN_AUX_A;
5302         }
5303 }
5304
5305 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5306 {
5307         struct drm_device *dev = crtc->dev;
5308         struct intel_encoder *intel_encoder;
5309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5310         enum pipe pipe = intel_crtc->pipe;
5311         unsigned long mask;
5312         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5313
5314         if (!crtc->state->active)
5315                 return 0;
5316
5317         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5318         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5319         if (intel_crtc->config->pch_pfit.enabled ||
5320             intel_crtc->config->pch_pfit.force_thru)
5321                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5322
5323         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5324                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5325
5326         return mask;
5327 }
5328
5329 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5330 {
5331         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5333         enum intel_display_power_domain domain;
5334         unsigned long domains, new_domains, old_domains;
5335
5336         old_domains = intel_crtc->enabled_power_domains;
5337         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5338
5339         domains = new_domains & ~old_domains;
5340
5341         for_each_power_domain(domain, domains)
5342                 intel_display_power_get(dev_priv, domain);
5343
5344         return old_domains & ~new_domains;
5345 }
5346
5347 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5348                                       unsigned long domains)
5349 {
5350         enum intel_display_power_domain domain;
5351
5352         for_each_power_domain(domain, domains)
5353                 intel_display_power_put(dev_priv, domain);
5354 }
5355
5356 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5357 {
5358         struct drm_device *dev = state->dev;
5359         struct drm_i915_private *dev_priv = dev->dev_private;
5360         unsigned long put_domains[I915_MAX_PIPES] = {};
5361         struct drm_crtc_state *crtc_state;
5362         struct drm_crtc *crtc;
5363         int i;
5364
5365         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5366                 if (needs_modeset(crtc->state))
5367                         put_domains[to_intel_crtc(crtc)->pipe] =
5368                                 modeset_get_crtc_power_domains(crtc);
5369         }
5370
5371         if (dev_priv->display.modeset_commit_cdclk) {
5372                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5373
5374                 if (cdclk != dev_priv->cdclk_freq &&
5375                     !WARN_ON(!state->allow_modeset))
5376                         dev_priv->display.modeset_commit_cdclk(state);
5377         }
5378
5379         for (i = 0; i < I915_MAX_PIPES; i++)
5380                 if (put_domains[i])
5381                         modeset_put_power_domains(dev_priv, put_domains[i]);
5382 }
5383
5384 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5385 {
5386         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5387
5388         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5389             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5390                 return max_cdclk_freq;
5391         else if (IS_CHERRYVIEW(dev_priv))
5392                 return max_cdclk_freq*95/100;
5393         else if (INTEL_INFO(dev_priv)->gen < 4)
5394                 return 2*max_cdclk_freq*90/100;
5395         else
5396                 return max_cdclk_freq*90/100;
5397 }
5398
5399 static void intel_update_max_cdclk(struct drm_device *dev)
5400 {
5401         struct drm_i915_private *dev_priv = dev->dev_private;
5402
5403         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5404                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5405
5406                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5407                         dev_priv->max_cdclk_freq = 675000;
5408                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5409                         dev_priv->max_cdclk_freq = 540000;
5410                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5411                         dev_priv->max_cdclk_freq = 450000;
5412                 else
5413                         dev_priv->max_cdclk_freq = 337500;
5414         } else if (IS_BROADWELL(dev))  {
5415                 /*
5416                  * FIXME with extra cooling we can allow
5417                  * 540 MHz for ULX and 675 Mhz for ULT.
5418                  * How can we know if extra cooling is
5419                  * available? PCI ID, VTB, something else?
5420                  */
5421                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5422                         dev_priv->max_cdclk_freq = 450000;
5423                 else if (IS_BDW_ULX(dev))
5424                         dev_priv->max_cdclk_freq = 450000;
5425                 else if (IS_BDW_ULT(dev))
5426                         dev_priv->max_cdclk_freq = 540000;
5427                 else
5428                         dev_priv->max_cdclk_freq = 675000;
5429         } else if (IS_CHERRYVIEW(dev)) {
5430                 dev_priv->max_cdclk_freq = 320000;
5431         } else if (IS_VALLEYVIEW(dev)) {
5432                 dev_priv->max_cdclk_freq = 400000;
5433         } else {
5434                 /* otherwise assume cdclk is fixed */
5435                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5436         }
5437
5438         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5439
5440         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5441                          dev_priv->max_cdclk_freq);
5442
5443         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5444                          dev_priv->max_dotclk_freq);
5445 }
5446
5447 static void intel_update_cdclk(struct drm_device *dev)
5448 {
5449         struct drm_i915_private *dev_priv = dev->dev_private;
5450
5451         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5452         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5453                          dev_priv->cdclk_freq);
5454
5455         /*
5456          * Program the gmbus_freq based on the cdclk frequency.
5457          * BSpec erroneously claims we should aim for 4MHz, but
5458          * in fact 1MHz is the correct frequency.
5459          */
5460         if (IS_VALLEYVIEW(dev)) {
5461                 /*
5462                  * Program the gmbus_freq based on the cdclk frequency.
5463                  * BSpec erroneously claims we should aim for 4MHz, but
5464                  * in fact 1MHz is the correct frequency.
5465                  */
5466                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5467         }
5468
5469         if (dev_priv->max_cdclk_freq == 0)
5470                 intel_update_max_cdclk(dev);
5471 }
5472
5473 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5474 {
5475         struct drm_i915_private *dev_priv = dev->dev_private;
5476         uint32_t divider;
5477         uint32_t ratio;
5478         uint32_t current_freq;
5479         int ret;
5480
5481         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5482         switch (frequency) {
5483         case 144000:
5484                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5485                 ratio = BXT_DE_PLL_RATIO(60);
5486                 break;
5487         case 288000:
5488                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5489                 ratio = BXT_DE_PLL_RATIO(60);
5490                 break;
5491         case 384000:
5492                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5493                 ratio = BXT_DE_PLL_RATIO(60);
5494                 break;
5495         case 576000:
5496                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5497                 ratio = BXT_DE_PLL_RATIO(60);
5498                 break;
5499         case 624000:
5500                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5501                 ratio = BXT_DE_PLL_RATIO(65);
5502                 break;
5503         case 19200:
5504                 /*
5505                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5506                  * to suppress GCC warning.
5507                  */
5508                 ratio = 0;
5509                 divider = 0;
5510                 break;
5511         default:
5512                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5513
5514                 return;
5515         }
5516
5517         mutex_lock(&dev_priv->rps.hw_lock);
5518         /* Inform power controller of upcoming frequency change */
5519         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5520                                       0x80000000);
5521         mutex_unlock(&dev_priv->rps.hw_lock);
5522
5523         if (ret) {
5524                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5525                           ret, frequency);
5526                 return;
5527         }
5528
5529         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5530         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5531         current_freq = current_freq * 500 + 1000;
5532
5533         /*
5534          * DE PLL has to be disabled when
5535          * - setting to 19.2MHz (bypass, PLL isn't used)
5536          * - before setting to 624MHz (PLL needs toggling)
5537          * - before setting to any frequency from 624MHz (PLL needs toggling)
5538          */
5539         if (frequency == 19200 || frequency == 624000 ||
5540             current_freq == 624000) {
5541                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5542                 /* Timeout 200us */
5543                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5544                              1))
5545                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5546         }
5547
5548         if (frequency != 19200) {
5549                 uint32_t val;
5550
5551                 val = I915_READ(BXT_DE_PLL_CTL);
5552                 val &= ~BXT_DE_PLL_RATIO_MASK;
5553                 val |= ratio;
5554                 I915_WRITE(BXT_DE_PLL_CTL, val);
5555
5556                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5557                 /* Timeout 200us */
5558                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5559                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5560
5561                 val = I915_READ(CDCLK_CTL);
5562                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5563                 val |= divider;
5564                 /*
5565                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5566                  * enable otherwise.
5567                  */
5568                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5569                 if (frequency >= 500000)
5570                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5571
5572                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5573                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5574                 val |= (frequency - 1000) / 500;
5575                 I915_WRITE(CDCLK_CTL, val);
5576         }
5577
5578         mutex_lock(&dev_priv->rps.hw_lock);
5579         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5580                                       DIV_ROUND_UP(frequency, 25000));
5581         mutex_unlock(&dev_priv->rps.hw_lock);
5582
5583         if (ret) {
5584                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5585                           ret, frequency);
5586                 return;
5587         }
5588
5589         intel_update_cdclk(dev);
5590 }
5591
5592 void broxton_init_cdclk(struct drm_device *dev)
5593 {
5594         struct drm_i915_private *dev_priv = dev->dev_private;
5595         uint32_t val;
5596
5597         /*
5598          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5599          * or else the reset will hang because there is no PCH to respond.
5600          * Move the handshake programming to initialization sequence.
5601          * Previously was left up to BIOS.
5602          */
5603         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5604         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5605         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5606
5607         /* Enable PG1 for cdclk */
5608         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5609
5610         /* check if cd clock is enabled */
5611         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5612                 DRM_DEBUG_KMS("Display already initialized\n");
5613                 return;
5614         }
5615
5616         /*
5617          * FIXME:
5618          * - The initial CDCLK needs to be read from VBT.
5619          *   Need to make this change after VBT has changes for BXT.
5620          * - check if setting the max (or any) cdclk freq is really necessary
5621          *   here, it belongs to modeset time
5622          */
5623         broxton_set_cdclk(dev, 624000);
5624
5625         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5626         POSTING_READ(DBUF_CTL);
5627
5628         udelay(10);
5629
5630         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5631                 DRM_ERROR("DBuf power enable timeout!\n");
5632 }
5633
5634 void broxton_uninit_cdclk(struct drm_device *dev)
5635 {
5636         struct drm_i915_private *dev_priv = dev->dev_private;
5637
5638         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5639         POSTING_READ(DBUF_CTL);
5640
5641         udelay(10);
5642
5643         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5644                 DRM_ERROR("DBuf power disable timeout!\n");
5645
5646         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5647         broxton_set_cdclk(dev, 19200);
5648
5649         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5650 }
5651
5652 static const struct skl_cdclk_entry {
5653         unsigned int freq;
5654         unsigned int vco;
5655 } skl_cdclk_frequencies[] = {
5656         { .freq = 308570, .vco = 8640 },
5657         { .freq = 337500, .vco = 8100 },
5658         { .freq = 432000, .vco = 8640 },
5659         { .freq = 450000, .vco = 8100 },
5660         { .freq = 540000, .vco = 8100 },
5661         { .freq = 617140, .vco = 8640 },
5662         { .freq = 675000, .vco = 8100 },
5663 };
5664
5665 static unsigned int skl_cdclk_decimal(unsigned int freq)
5666 {
5667         return (freq - 1000) / 500;
5668 }
5669
5670 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5671 {
5672         unsigned int i;
5673
5674         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5675                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5676
5677                 if (e->freq == freq)
5678                         return e->vco;
5679         }
5680
5681         return 8100;
5682 }
5683
5684 static void
5685 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5686 {
5687         unsigned int min_freq;
5688         u32 val;
5689
5690         /* select the minimum CDCLK before enabling DPLL 0 */
5691         val = I915_READ(CDCLK_CTL);
5692         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5693         val |= CDCLK_FREQ_337_308;
5694
5695         if (required_vco == 8640)
5696                 min_freq = 308570;
5697         else
5698                 min_freq = 337500;
5699
5700         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5701
5702         I915_WRITE(CDCLK_CTL, val);
5703         POSTING_READ(CDCLK_CTL);
5704
5705         /*
5706          * We always enable DPLL0 with the lowest link rate possible, but still
5707          * taking into account the VCO required to operate the eDP panel at the
5708          * desired frequency. The usual DP link rates operate with a VCO of
5709          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5710          * The modeset code is responsible for the selection of the exact link
5711          * rate later on, with the constraint of choosing a frequency that
5712          * works with required_vco.
5713          */
5714         val = I915_READ(DPLL_CTRL1);
5715
5716         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5717                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5718         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5719         if (required_vco == 8640)
5720                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5721                                             SKL_DPLL0);
5722         else
5723                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5724                                             SKL_DPLL0);
5725
5726         I915_WRITE(DPLL_CTRL1, val);
5727         POSTING_READ(DPLL_CTRL1);
5728
5729         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5730
5731         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5732                 DRM_ERROR("DPLL0 not locked\n");
5733 }
5734
5735 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5736 {
5737         int ret;
5738         u32 val;
5739
5740         /* inform PCU we want to change CDCLK */
5741         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5742         mutex_lock(&dev_priv->rps.hw_lock);
5743         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5744         mutex_unlock(&dev_priv->rps.hw_lock);
5745
5746         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5747 }
5748
5749 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5750 {
5751         unsigned int i;
5752
5753         for (i = 0; i < 15; i++) {
5754                 if (skl_cdclk_pcu_ready(dev_priv))
5755                         return true;
5756                 udelay(10);
5757         }
5758
5759         return false;
5760 }
5761
5762 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5763 {
5764         struct drm_device *dev = dev_priv->dev;
5765         u32 freq_select, pcu_ack;
5766
5767         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5768
5769         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5770                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5771                 return;
5772         }
5773
5774         /* set CDCLK_CTL */
5775         switch(freq) {
5776         case 450000:
5777         case 432000:
5778                 freq_select = CDCLK_FREQ_450_432;
5779                 pcu_ack = 1;
5780                 break;
5781         case 540000:
5782                 freq_select = CDCLK_FREQ_540;
5783                 pcu_ack = 2;
5784                 break;
5785         case 308570:
5786         case 337500:
5787         default:
5788                 freq_select = CDCLK_FREQ_337_308;
5789                 pcu_ack = 0;
5790                 break;
5791         case 617140:
5792         case 675000:
5793                 freq_select = CDCLK_FREQ_675_617;
5794                 pcu_ack = 3;
5795                 break;
5796         }
5797
5798         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5799         POSTING_READ(CDCLK_CTL);
5800
5801         /* inform PCU of the change */
5802         mutex_lock(&dev_priv->rps.hw_lock);
5803         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5804         mutex_unlock(&dev_priv->rps.hw_lock);
5805
5806         intel_update_cdclk(dev);
5807 }
5808
5809 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5810 {
5811         /* disable DBUF power */
5812         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5813         POSTING_READ(DBUF_CTL);
5814
5815         udelay(10);
5816
5817         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5818                 DRM_ERROR("DBuf power disable timeout\n");
5819
5820         /* disable DPLL0 */
5821         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5822         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5823                 DRM_ERROR("Couldn't disable DPLL0\n");
5824 }
5825
5826 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5827 {
5828         unsigned int required_vco;
5829
5830         /* DPLL0 not enabled (happens on early BIOS versions) */
5831         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5832                 /* enable DPLL0 */
5833                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5834                 skl_dpll0_enable(dev_priv, required_vco);
5835         }
5836
5837         /* set CDCLK to the frequency the BIOS chose */
5838         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5839
5840         /* enable DBUF power */
5841         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5842         POSTING_READ(DBUF_CTL);
5843
5844         udelay(10);
5845
5846         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5847                 DRM_ERROR("DBuf power enable timeout\n");
5848 }
5849
5850 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5851 {
5852         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5853         uint32_t cdctl = I915_READ(CDCLK_CTL);
5854         int freq = dev_priv->skl_boot_cdclk;
5855
5856         /*
5857          * check if the pre-os intialized the display
5858          * There is SWF18 scratchpad register defined which is set by the
5859          * pre-os which can be used by the OS drivers to check the status
5860          */
5861         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5862                 goto sanitize;
5863
5864         /* Is PLL enabled and locked ? */
5865         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5866                 goto sanitize;
5867
5868         /* DPLL okay; verify the cdclock
5869          *
5870          * Noticed in some instances that the freq selection is correct but
5871          * decimal part is programmed wrong from BIOS where pre-os does not
5872          * enable display. Verify the same as well.
5873          */
5874         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5875                 /* All well; nothing to sanitize */
5876                 return false;
5877 sanitize:
5878         /*
5879          * As of now initialize with max cdclk till
5880          * we get dynamic cdclk support
5881          * */
5882         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5883         skl_init_cdclk(dev_priv);
5884
5885         /* we did have to sanitize */
5886         return true;
5887 }
5888
5889 /* Adjust CDclk dividers to allow high res or save power if possible */
5890 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5891 {
5892         struct drm_i915_private *dev_priv = dev->dev_private;
5893         u32 val, cmd;
5894
5895         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5896                                         != dev_priv->cdclk_freq);
5897
5898         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5899                 cmd = 2;
5900         else if (cdclk == 266667)
5901                 cmd = 1;
5902         else
5903                 cmd = 0;
5904
5905         mutex_lock(&dev_priv->rps.hw_lock);
5906         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5907         val &= ~DSPFREQGUAR_MASK;
5908         val |= (cmd << DSPFREQGUAR_SHIFT);
5909         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5910         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5911                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5912                      50)) {
5913                 DRM_ERROR("timed out waiting for CDclk change\n");
5914         }
5915         mutex_unlock(&dev_priv->rps.hw_lock);
5916
5917         mutex_lock(&dev_priv->sb_lock);
5918
5919         if (cdclk == 400000) {
5920                 u32 divider;
5921
5922                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5923
5924                 /* adjust cdclk divider */
5925                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5926                 val &= ~CCK_FREQUENCY_VALUES;
5927                 val |= divider;
5928                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5929
5930                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5931                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5932                              50))
5933                         DRM_ERROR("timed out waiting for CDclk change\n");
5934         }
5935
5936         /* adjust self-refresh exit latency value */
5937         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5938         val &= ~0x7f;
5939
5940         /*
5941          * For high bandwidth configs, we set a higher latency in the bunit
5942          * so that the core display fetch happens in time to avoid underruns.
5943          */
5944         if (cdclk == 400000)
5945                 val |= 4500 / 250; /* 4.5 usec */
5946         else
5947                 val |= 3000 / 250; /* 3.0 usec */
5948         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5949
5950         mutex_unlock(&dev_priv->sb_lock);
5951
5952         intel_update_cdclk(dev);
5953 }
5954
5955 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5956 {
5957         struct drm_i915_private *dev_priv = dev->dev_private;
5958         u32 val, cmd;
5959
5960         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5961                                                 != dev_priv->cdclk_freq);
5962
5963         switch (cdclk) {
5964         case 333333:
5965         case 320000:
5966         case 266667:
5967         case 200000:
5968                 break;
5969         default:
5970                 MISSING_CASE(cdclk);
5971                 return;
5972         }
5973
5974         /*
5975          * Specs are full of misinformation, but testing on actual
5976          * hardware has shown that we just need to write the desired
5977          * CCK divider into the Punit register.
5978          */
5979         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5980
5981         mutex_lock(&dev_priv->rps.hw_lock);
5982         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5983         val &= ~DSPFREQGUAR_MASK_CHV;
5984         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5985         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5986         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5987                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5988                      50)) {
5989                 DRM_ERROR("timed out waiting for CDclk change\n");
5990         }
5991         mutex_unlock(&dev_priv->rps.hw_lock);
5992
5993         intel_update_cdclk(dev);
5994 }
5995
5996 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5997                                  int max_pixclk)
5998 {
5999         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6000         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6001
6002         /*
6003          * Really only a few cases to deal with, as only 4 CDclks are supported:
6004          *   200MHz
6005          *   267MHz
6006          *   320/333MHz (depends on HPLL freq)
6007          *   400MHz (VLV only)
6008          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6009          * of the lower bin and adjust if needed.
6010          *
6011          * We seem to get an unstable or solid color picture at 200MHz.
6012          * Not sure what's wrong. For now use 200MHz only when all pipes
6013          * are off.
6014          */
6015         if (!IS_CHERRYVIEW(dev_priv) &&
6016             max_pixclk > freq_320*limit/100)
6017                 return 400000;
6018         else if (max_pixclk > 266667*limit/100)
6019                 return freq_320;
6020         else if (max_pixclk > 0)
6021                 return 266667;
6022         else
6023                 return 200000;
6024 }
6025
6026 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6027                               int max_pixclk)
6028 {
6029         /*
6030          * FIXME:
6031          * - remove the guardband, it's not needed on BXT
6032          * - set 19.2MHz bypass frequency if there are no active pipes
6033          */
6034         if (max_pixclk > 576000*9/10)
6035                 return 624000;
6036         else if (max_pixclk > 384000*9/10)
6037                 return 576000;
6038         else if (max_pixclk > 288000*9/10)
6039                 return 384000;
6040         else if (max_pixclk > 144000*9/10)
6041                 return 288000;
6042         else
6043                 return 144000;
6044 }
6045
6046 /* Compute the max pixel clock for new configuration. Uses atomic state if
6047  * that's non-NULL, look at current state otherwise. */
6048 static int intel_mode_max_pixclk(struct drm_device *dev,
6049                                  struct drm_atomic_state *state)
6050 {
6051         struct intel_crtc *intel_crtc;
6052         struct intel_crtc_state *crtc_state;
6053         int max_pixclk = 0;
6054
6055         for_each_intel_crtc(dev, intel_crtc) {
6056                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6057                 if (IS_ERR(crtc_state))
6058                         return PTR_ERR(crtc_state);
6059
6060                 if (!crtc_state->base.enable)
6061                         continue;
6062
6063                 max_pixclk = max(max_pixclk,
6064                                  crtc_state->base.adjusted_mode.crtc_clock);
6065         }
6066
6067         return max_pixclk;
6068 }
6069
6070 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6071 {
6072         struct drm_device *dev = state->dev;
6073         struct drm_i915_private *dev_priv = dev->dev_private;
6074         int max_pixclk = intel_mode_max_pixclk(dev, state);
6075
6076         if (max_pixclk < 0)
6077                 return max_pixclk;
6078
6079         to_intel_atomic_state(state)->cdclk =
6080                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6081
6082         return 0;
6083 }
6084
6085 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6086 {
6087         struct drm_device *dev = state->dev;
6088         struct drm_i915_private *dev_priv = dev->dev_private;
6089         int max_pixclk = intel_mode_max_pixclk(dev, state);
6090
6091         if (max_pixclk < 0)
6092                 return max_pixclk;
6093
6094         to_intel_atomic_state(state)->cdclk =
6095                 broxton_calc_cdclk(dev_priv, max_pixclk);
6096
6097         return 0;
6098 }
6099
6100 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6101 {
6102         unsigned int credits, default_credits;
6103
6104         if (IS_CHERRYVIEW(dev_priv))
6105                 default_credits = PFI_CREDIT(12);
6106         else
6107                 default_credits = PFI_CREDIT(8);
6108
6109         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6110                 /* CHV suggested value is 31 or 63 */
6111                 if (IS_CHERRYVIEW(dev_priv))
6112                         credits = PFI_CREDIT_63;
6113                 else
6114                         credits = PFI_CREDIT(15);
6115         } else {
6116                 credits = default_credits;
6117         }
6118
6119         /*
6120          * WA - write default credits before re-programming
6121          * FIXME: should we also set the resend bit here?
6122          */
6123         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6124                    default_credits);
6125
6126         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6127                    credits | PFI_CREDIT_RESEND);
6128
6129         /*
6130          * FIXME is this guaranteed to clear
6131          * immediately or should we poll for it?
6132          */
6133         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6134 }
6135
6136 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6137 {
6138         struct drm_device *dev = old_state->dev;
6139         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6140         struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142         /*
6143          * FIXME: We can end up here with all power domains off, yet
6144          * with a CDCLK frequency other than the minimum. To account
6145          * for this take the PIPE-A power domain, which covers the HW
6146          * blocks needed for the following programming. This can be
6147          * removed once it's guaranteed that we get here either with
6148          * the minimum CDCLK set, or the required power domains
6149          * enabled.
6150          */
6151         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6152
6153         if (IS_CHERRYVIEW(dev))
6154                 cherryview_set_cdclk(dev, req_cdclk);
6155         else
6156                 valleyview_set_cdclk(dev, req_cdclk);
6157
6158         vlv_program_pfi_credits(dev_priv);
6159
6160         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6161 }
6162
6163 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6164 {
6165         struct drm_device *dev = crtc->dev;
6166         struct drm_i915_private *dev_priv = to_i915(dev);
6167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6168         struct intel_encoder *encoder;
6169         int pipe = intel_crtc->pipe;
6170
6171         if (WARN_ON(intel_crtc->active))
6172                 return;
6173
6174         if (intel_crtc->config->has_dp_encoder)
6175                 intel_dp_set_m_n(intel_crtc, M1_N1);
6176
6177         intel_set_pipe_timings(intel_crtc);
6178
6179         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6180                 struct drm_i915_private *dev_priv = dev->dev_private;
6181
6182                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6183                 I915_WRITE(CHV_CANVAS(pipe), 0);
6184         }
6185
6186         i9xx_set_pipeconf(intel_crtc);
6187
6188         intel_crtc->active = true;
6189
6190         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6191
6192         for_each_encoder_on_crtc(dev, crtc, encoder)
6193                 if (encoder->pre_pll_enable)
6194                         encoder->pre_pll_enable(encoder);
6195
6196         if (!intel_crtc->config->has_dsi_encoder) {
6197                 if (IS_CHERRYVIEW(dev)) {
6198                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6199                         chv_enable_pll(intel_crtc, intel_crtc->config);
6200                 } else {
6201                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6202                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6203                 }
6204         }
6205
6206         for_each_encoder_on_crtc(dev, crtc, encoder)
6207                 if (encoder->pre_enable)
6208                         encoder->pre_enable(encoder);
6209
6210         i9xx_pfit_enable(intel_crtc);
6211
6212         intel_crtc_load_lut(crtc);
6213
6214         intel_enable_pipe(intel_crtc);
6215
6216         assert_vblank_disabled(crtc);
6217         drm_crtc_vblank_on(crtc);
6218
6219         for_each_encoder_on_crtc(dev, crtc, encoder)
6220                 encoder->enable(encoder);
6221 }
6222
6223 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6224 {
6225         struct drm_device *dev = crtc->base.dev;
6226         struct drm_i915_private *dev_priv = dev->dev_private;
6227
6228         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6229         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6230 }
6231
6232 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6233 {
6234         struct drm_device *dev = crtc->dev;
6235         struct drm_i915_private *dev_priv = to_i915(dev);
6236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237         struct intel_encoder *encoder;
6238         int pipe = intel_crtc->pipe;
6239
6240         if (WARN_ON(intel_crtc->active))
6241                 return;
6242
6243         i9xx_set_pll_dividers(intel_crtc);
6244
6245         if (intel_crtc->config->has_dp_encoder)
6246                 intel_dp_set_m_n(intel_crtc, M1_N1);
6247
6248         intel_set_pipe_timings(intel_crtc);
6249
6250         i9xx_set_pipeconf(intel_crtc);
6251
6252         intel_crtc->active = true;
6253
6254         if (!IS_GEN2(dev))
6255                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6256
6257         for_each_encoder_on_crtc(dev, crtc, encoder)
6258                 if (encoder->pre_enable)
6259                         encoder->pre_enable(encoder);
6260
6261         i9xx_enable_pll(intel_crtc);
6262
6263         i9xx_pfit_enable(intel_crtc);
6264
6265         intel_crtc_load_lut(crtc);
6266
6267         intel_update_watermarks(crtc);
6268         intel_enable_pipe(intel_crtc);
6269
6270         assert_vblank_disabled(crtc);
6271         drm_crtc_vblank_on(crtc);
6272
6273         for_each_encoder_on_crtc(dev, crtc, encoder)
6274                 encoder->enable(encoder);
6275
6276         intel_fbc_enable(intel_crtc);
6277 }
6278
6279 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6280 {
6281         struct drm_device *dev = crtc->base.dev;
6282         struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284         if (!crtc->config->gmch_pfit.control)
6285                 return;
6286
6287         assert_pipe_disabled(dev_priv, crtc->pipe);
6288
6289         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6290                          I915_READ(PFIT_CONTROL));
6291         I915_WRITE(PFIT_CONTROL, 0);
6292 }
6293
6294 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6295 {
6296         struct drm_device *dev = crtc->dev;
6297         struct drm_i915_private *dev_priv = dev->dev_private;
6298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299         struct intel_encoder *encoder;
6300         int pipe = intel_crtc->pipe;
6301
6302         /*
6303          * On gen2 planes are double buffered but the pipe isn't, so we must
6304          * wait for planes to fully turn off before disabling the pipe.
6305          * We also need to wait on all gmch platforms because of the
6306          * self-refresh mode constraint explained above.
6307          */
6308         intel_wait_for_vblank(dev, pipe);
6309
6310         for_each_encoder_on_crtc(dev, crtc, encoder)
6311                 encoder->disable(encoder);
6312
6313         drm_crtc_vblank_off(crtc);
6314         assert_vblank_disabled(crtc);
6315
6316         intel_disable_pipe(intel_crtc);
6317
6318         i9xx_pfit_disable(intel_crtc);
6319
6320         for_each_encoder_on_crtc(dev, crtc, encoder)
6321                 if (encoder->post_disable)
6322                         encoder->post_disable(encoder);
6323
6324         if (!intel_crtc->config->has_dsi_encoder) {
6325                 if (IS_CHERRYVIEW(dev))
6326                         chv_disable_pll(dev_priv, pipe);
6327                 else if (IS_VALLEYVIEW(dev))
6328                         vlv_disable_pll(dev_priv, pipe);
6329                 else
6330                         i9xx_disable_pll(intel_crtc);
6331         }
6332
6333         for_each_encoder_on_crtc(dev, crtc, encoder)
6334                 if (encoder->post_pll_disable)
6335                         encoder->post_pll_disable(encoder);
6336
6337         if (!IS_GEN2(dev))
6338                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6339
6340         intel_fbc_disable_crtc(intel_crtc);
6341 }
6342
6343 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6344 {
6345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6346         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6347         enum intel_display_power_domain domain;
6348         unsigned long domains;
6349
6350         if (!intel_crtc->active)
6351                 return;
6352
6353         if (to_intel_plane_state(crtc->primary->state)->visible) {
6354                 WARN_ON(intel_crtc->unpin_work);
6355
6356                 intel_pre_disable_primary(crtc);
6357         }
6358
6359         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6360         dev_priv->display.crtc_disable(crtc);
6361         intel_crtc->active = false;
6362         intel_update_watermarks(crtc);
6363         intel_disable_shared_dpll(intel_crtc);
6364
6365         domains = intel_crtc->enabled_power_domains;
6366         for_each_power_domain(domain, domains)
6367                 intel_display_power_put(dev_priv, domain);
6368         intel_crtc->enabled_power_domains = 0;
6369 }
6370
6371 /*
6372  * turn all crtc's off, but do not adjust state
6373  * This has to be paired with a call to intel_modeset_setup_hw_state.
6374  */
6375 int intel_display_suspend(struct drm_device *dev)
6376 {
6377         struct drm_mode_config *config = &dev->mode_config;
6378         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6379         struct drm_atomic_state *state;
6380         struct drm_crtc *crtc;
6381         unsigned crtc_mask = 0;
6382         int ret = 0;
6383
6384         if (WARN_ON(!ctx))
6385                 return 0;
6386
6387         lockdep_assert_held(&ctx->ww_ctx);
6388         state = drm_atomic_state_alloc(dev);
6389         if (WARN_ON(!state))
6390                 return -ENOMEM;
6391
6392         state->acquire_ctx = ctx;
6393         state->allow_modeset = true;
6394
6395         for_each_crtc(dev, crtc) {
6396                 struct drm_crtc_state *crtc_state =
6397                         drm_atomic_get_crtc_state(state, crtc);
6398
6399                 ret = PTR_ERR_OR_ZERO(crtc_state);
6400                 if (ret)
6401                         goto free;
6402
6403                 if (!crtc_state->active)
6404                         continue;
6405
6406                 crtc_state->active = false;
6407                 crtc_mask |= 1 << drm_crtc_index(crtc);
6408         }
6409
6410         if (crtc_mask) {
6411                 ret = drm_atomic_commit(state);
6412
6413                 if (!ret) {
6414                         for_each_crtc(dev, crtc)
6415                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6416                                         crtc->state->active = true;
6417
6418                         return ret;
6419                 }
6420         }
6421
6422 free:
6423         if (ret)
6424                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6425         drm_atomic_state_free(state);
6426         return ret;
6427 }
6428
6429 void intel_encoder_destroy(struct drm_encoder *encoder)
6430 {
6431         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6432
6433         drm_encoder_cleanup(encoder);
6434         kfree(intel_encoder);
6435 }
6436
6437 /* Cross check the actual hw state with our own modeset state tracking (and it's
6438  * internal consistency). */
6439 static void intel_connector_check_state(struct intel_connector *connector)
6440 {
6441         struct drm_crtc *crtc = connector->base.state->crtc;
6442
6443         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6444                       connector->base.base.id,
6445                       connector->base.name);
6446
6447         if (connector->get_hw_state(connector)) {
6448                 struct intel_encoder *encoder = connector->encoder;
6449                 struct drm_connector_state *conn_state = connector->base.state;
6450
6451                 I915_STATE_WARN(!crtc,
6452                          "connector enabled without attached crtc\n");
6453
6454                 if (!crtc)
6455                         return;
6456
6457                 I915_STATE_WARN(!crtc->state->active,
6458                       "connector is active, but attached crtc isn't\n");
6459
6460                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6461                         return;
6462
6463                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6464                         "atomic encoder doesn't match attached encoder\n");
6465
6466                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6467                         "attached encoder crtc differs from connector crtc\n");
6468         } else {
6469                 I915_STATE_WARN(crtc && crtc->state->active,
6470                         "attached crtc is active, but connector isn't\n");
6471                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6472                         "best encoder set without crtc!\n");
6473         }
6474 }
6475
6476 int intel_connector_init(struct intel_connector *connector)
6477 {
6478         struct drm_connector_state *connector_state;
6479
6480         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6481         if (!connector_state)
6482                 return -ENOMEM;
6483
6484         connector->base.state = connector_state;
6485         return 0;
6486 }
6487
6488 struct intel_connector *intel_connector_alloc(void)
6489 {
6490         struct intel_connector *connector;
6491
6492         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6493         if (!connector)
6494                 return NULL;
6495
6496         if (intel_connector_init(connector) < 0) {
6497                 kfree(connector);
6498                 return NULL;
6499         }
6500
6501         return connector;
6502 }
6503
6504 /* Simple connector->get_hw_state implementation for encoders that support only
6505  * one connector and no cloning and hence the encoder state determines the state
6506  * of the connector. */
6507 bool intel_connector_get_hw_state(struct intel_connector *connector)
6508 {
6509         enum pipe pipe = 0;
6510         struct intel_encoder *encoder = connector->encoder;
6511
6512         return encoder->get_hw_state(encoder, &pipe);
6513 }
6514
6515 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6516 {
6517         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6518                 return crtc_state->fdi_lanes;
6519
6520         return 0;
6521 }
6522
6523 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6524                                      struct intel_crtc_state *pipe_config)
6525 {
6526         struct drm_atomic_state *state = pipe_config->base.state;
6527         struct intel_crtc *other_crtc;
6528         struct intel_crtc_state *other_crtc_state;
6529
6530         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6531                       pipe_name(pipe), pipe_config->fdi_lanes);
6532         if (pipe_config->fdi_lanes > 4) {
6533                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6534                               pipe_name(pipe), pipe_config->fdi_lanes);
6535                 return -EINVAL;
6536         }
6537
6538         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6539                 if (pipe_config->fdi_lanes > 2) {
6540                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6541                                       pipe_config->fdi_lanes);
6542                         return -EINVAL;
6543                 } else {
6544                         return 0;
6545                 }
6546         }
6547
6548         if (INTEL_INFO(dev)->num_pipes == 2)
6549                 return 0;
6550
6551         /* Ivybridge 3 pipe is really complicated */
6552         switch (pipe) {
6553         case PIPE_A:
6554                 return 0;
6555         case PIPE_B:
6556                 if (pipe_config->fdi_lanes <= 2)
6557                         return 0;
6558
6559                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6560                 other_crtc_state =
6561                         intel_atomic_get_crtc_state(state, other_crtc);
6562                 if (IS_ERR(other_crtc_state))
6563                         return PTR_ERR(other_crtc_state);
6564
6565                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6566                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6567                                       pipe_name(pipe), pipe_config->fdi_lanes);
6568                         return -EINVAL;
6569                 }
6570                 return 0;
6571         case PIPE_C:
6572                 if (pipe_config->fdi_lanes > 2) {
6573                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6574                                       pipe_name(pipe), pipe_config->fdi_lanes);
6575                         return -EINVAL;
6576                 }
6577
6578                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6579                 other_crtc_state =
6580                         intel_atomic_get_crtc_state(state, other_crtc);
6581                 if (IS_ERR(other_crtc_state))
6582                         return PTR_ERR(other_crtc_state);
6583
6584                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6585                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6586                         return -EINVAL;
6587                 }
6588                 return 0;
6589         default:
6590                 BUG();
6591         }
6592 }
6593
6594 #define RETRY 1
6595 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6596                                        struct intel_crtc_state *pipe_config)
6597 {
6598         struct drm_device *dev = intel_crtc->base.dev;
6599         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6600         int lane, link_bw, fdi_dotclock, ret;
6601         bool needs_recompute = false;
6602
6603 retry:
6604         /* FDI is a binary signal running at ~2.7GHz, encoding
6605          * each output octet as 10 bits. The actual frequency
6606          * is stored as a divider into a 100MHz clock, and the
6607          * mode pixel clock is stored in units of 1KHz.
6608          * Hence the bw of each lane in terms of the mode signal
6609          * is:
6610          */
6611         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6612
6613         fdi_dotclock = adjusted_mode->crtc_clock;
6614
6615         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6616                                            pipe_config->pipe_bpp);
6617
6618         pipe_config->fdi_lanes = lane;
6619
6620         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6621                                link_bw, &pipe_config->fdi_m_n);
6622
6623         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6624                                        intel_crtc->pipe, pipe_config);
6625         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6626                 pipe_config->pipe_bpp -= 2*3;
6627                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6628                               pipe_config->pipe_bpp);
6629                 needs_recompute = true;
6630                 pipe_config->bw_constrained = true;
6631
6632                 goto retry;
6633         }
6634
6635         if (needs_recompute)
6636                 return RETRY;
6637
6638         return ret;
6639 }
6640
6641 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6642                                      struct intel_crtc_state *pipe_config)
6643 {
6644         if (pipe_config->pipe_bpp > 24)
6645                 return false;
6646
6647         /* HSW can handle pixel rate up to cdclk? */
6648         if (IS_HASWELL(dev_priv->dev))
6649                 return true;
6650
6651         /*
6652          * We compare against max which means we must take
6653          * the increased cdclk requirement into account when
6654          * calculating the new cdclk.
6655          *
6656          * Should measure whether using a lower cdclk w/o IPS
6657          */
6658         return ilk_pipe_pixel_rate(pipe_config) <=
6659                 dev_priv->max_cdclk_freq * 95 / 100;
6660 }
6661
6662 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6663                                    struct intel_crtc_state *pipe_config)
6664 {
6665         struct drm_device *dev = crtc->base.dev;
6666         struct drm_i915_private *dev_priv = dev->dev_private;
6667
6668         pipe_config->ips_enabled = i915.enable_ips &&
6669                 hsw_crtc_supports_ips(crtc) &&
6670                 pipe_config_supports_ips(dev_priv, pipe_config);
6671 }
6672
6673 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6674 {
6675         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6676
6677         /* GDG double wide on either pipe, otherwise pipe A only */
6678         return INTEL_INFO(dev_priv)->gen < 4 &&
6679                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6680 }
6681
6682 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6683                                      struct intel_crtc_state *pipe_config)
6684 {
6685         struct drm_device *dev = crtc->base.dev;
6686         struct drm_i915_private *dev_priv = dev->dev_private;
6687         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6688
6689         /* FIXME should check pixel clock limits on all platforms */
6690         if (INTEL_INFO(dev)->gen < 4) {
6691                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6692
6693                 /*
6694                  * Enable double wide mode when the dot clock
6695                  * is > 90% of the (display) core speed.
6696                  */
6697                 if (intel_crtc_supports_double_wide(crtc) &&
6698                     adjusted_mode->crtc_clock > clock_limit) {
6699                         clock_limit *= 2;
6700                         pipe_config->double_wide = true;
6701                 }
6702
6703                 if (adjusted_mode->crtc_clock > clock_limit) {
6704                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6705                                       adjusted_mode->crtc_clock, clock_limit,
6706                                       yesno(pipe_config->double_wide));
6707                         return -EINVAL;
6708                 }
6709         }
6710
6711         /*
6712          * Pipe horizontal size must be even in:
6713          * - DVO ganged mode
6714          * - LVDS dual channel mode
6715          * - Double wide pipe
6716          */
6717         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6718              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6719                 pipe_config->pipe_src_w &= ~1;
6720
6721         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6722          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6723          */
6724         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6725                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6726                 return -EINVAL;
6727
6728         if (HAS_IPS(dev))
6729                 hsw_compute_ips_config(crtc, pipe_config);
6730
6731         if (pipe_config->has_pch_encoder)
6732                 return ironlake_fdi_compute_config(crtc, pipe_config);
6733
6734         return 0;
6735 }
6736
6737 static int skylake_get_display_clock_speed(struct drm_device *dev)
6738 {
6739         struct drm_i915_private *dev_priv = to_i915(dev);
6740         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6741         uint32_t cdctl = I915_READ(CDCLK_CTL);
6742         uint32_t linkrate;
6743
6744         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6745                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6746
6747         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6748                 return 540000;
6749
6750         linkrate = (I915_READ(DPLL_CTRL1) &
6751                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6752
6753         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6754             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6755                 /* vco 8640 */
6756                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6757                 case CDCLK_FREQ_450_432:
6758                         return 432000;
6759                 case CDCLK_FREQ_337_308:
6760                         return 308570;
6761                 case CDCLK_FREQ_675_617:
6762                         return 617140;
6763                 default:
6764                         WARN(1, "Unknown cd freq selection\n");
6765                 }
6766         } else {
6767                 /* vco 8100 */
6768                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6769                 case CDCLK_FREQ_450_432:
6770                         return 450000;
6771                 case CDCLK_FREQ_337_308:
6772                         return 337500;
6773                 case CDCLK_FREQ_675_617:
6774                         return 675000;
6775                 default:
6776                         WARN(1, "Unknown cd freq selection\n");
6777                 }
6778         }
6779
6780         /* error case, do as if DPLL0 isn't enabled */
6781         return 24000;
6782 }
6783
6784 static int broxton_get_display_clock_speed(struct drm_device *dev)
6785 {
6786         struct drm_i915_private *dev_priv = to_i915(dev);
6787         uint32_t cdctl = I915_READ(CDCLK_CTL);
6788         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6789         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6790         int cdclk;
6791
6792         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6793                 return 19200;
6794
6795         cdclk = 19200 * pll_ratio / 2;
6796
6797         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6798         case BXT_CDCLK_CD2X_DIV_SEL_1:
6799                 return cdclk;  /* 576MHz or 624MHz */
6800         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6801                 return cdclk * 2 / 3; /* 384MHz */
6802         case BXT_CDCLK_CD2X_DIV_SEL_2:
6803                 return cdclk / 2; /* 288MHz */
6804         case BXT_CDCLK_CD2X_DIV_SEL_4:
6805                 return cdclk / 4; /* 144MHz */
6806         }
6807
6808         /* error case, do as if DE PLL isn't enabled */
6809         return 19200;
6810 }
6811
6812 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6813 {
6814         struct drm_i915_private *dev_priv = dev->dev_private;
6815         uint32_t lcpll = I915_READ(LCPLL_CTL);
6816         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6817
6818         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6819                 return 800000;
6820         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6821                 return 450000;
6822         else if (freq == LCPLL_CLK_FREQ_450)
6823                 return 450000;
6824         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6825                 return 540000;
6826         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6827                 return 337500;
6828         else
6829                 return 675000;
6830 }
6831
6832 static int haswell_get_display_clock_speed(struct drm_device *dev)
6833 {
6834         struct drm_i915_private *dev_priv = dev->dev_private;
6835         uint32_t lcpll = I915_READ(LCPLL_CTL);
6836         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6837
6838         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6839                 return 800000;
6840         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6841                 return 450000;
6842         else if (freq == LCPLL_CLK_FREQ_450)
6843                 return 450000;
6844         else if (IS_HSW_ULT(dev))
6845                 return 337500;
6846         else
6847                 return 540000;
6848 }
6849
6850 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6851 {
6852         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6853                                       CCK_DISPLAY_CLOCK_CONTROL);
6854 }
6855
6856 static int ilk_get_display_clock_speed(struct drm_device *dev)
6857 {
6858         return 450000;
6859 }
6860
6861 static int i945_get_display_clock_speed(struct drm_device *dev)
6862 {
6863         return 400000;
6864 }
6865
6866 static int i915_get_display_clock_speed(struct drm_device *dev)
6867 {
6868         return 333333;
6869 }
6870
6871 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6872 {
6873         return 200000;
6874 }
6875
6876 static int pnv_get_display_clock_speed(struct drm_device *dev)
6877 {
6878         u16 gcfgc = 0;
6879
6880         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6881
6882         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6883         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6884                 return 266667;
6885         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6886                 return 333333;
6887         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6888                 return 444444;
6889         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6890                 return 200000;
6891         default:
6892                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6893         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6894                 return 133333;
6895         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6896                 return 166667;
6897         }
6898 }
6899
6900 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6901 {
6902         u16 gcfgc = 0;
6903
6904         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6905
6906         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6907                 return 133333;
6908         else {
6909                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6910                 case GC_DISPLAY_CLOCK_333_MHZ:
6911                         return 333333;
6912                 default:
6913                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6914                         return 190000;
6915                 }
6916         }
6917 }
6918
6919 static int i865_get_display_clock_speed(struct drm_device *dev)
6920 {
6921         return 266667;
6922 }
6923
6924 static int i85x_get_display_clock_speed(struct drm_device *dev)
6925 {
6926         u16 hpllcc = 0;
6927
6928         /*
6929          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6930          * encoding is different :(
6931          * FIXME is this the right way to detect 852GM/852GMV?
6932          */
6933         if (dev->pdev->revision == 0x1)
6934                 return 133333;
6935
6936         pci_bus_read_config_word(dev->pdev->bus,
6937                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6938
6939         /* Assume that the hardware is in the high speed state.  This
6940          * should be the default.
6941          */
6942         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6943         case GC_CLOCK_133_200:
6944         case GC_CLOCK_133_200_2:
6945         case GC_CLOCK_100_200:
6946                 return 200000;
6947         case GC_CLOCK_166_250:
6948                 return 250000;
6949         case GC_CLOCK_100_133:
6950                 return 133333;
6951         case GC_CLOCK_133_266:
6952         case GC_CLOCK_133_266_2:
6953         case GC_CLOCK_166_266:
6954                 return 266667;
6955         }
6956
6957         /* Shouldn't happen */
6958         return 0;
6959 }
6960
6961 static int i830_get_display_clock_speed(struct drm_device *dev)
6962 {
6963         return 133333;
6964 }
6965
6966 static unsigned int intel_hpll_vco(struct drm_device *dev)
6967 {
6968         struct drm_i915_private *dev_priv = dev->dev_private;
6969         static const unsigned int blb_vco[8] = {
6970                 [0] = 3200000,
6971                 [1] = 4000000,
6972                 [2] = 5333333,
6973                 [3] = 4800000,
6974                 [4] = 6400000,
6975         };
6976         static const unsigned int pnv_vco[8] = {
6977                 [0] = 3200000,
6978                 [1] = 4000000,
6979                 [2] = 5333333,
6980                 [3] = 4800000,
6981                 [4] = 2666667,
6982         };
6983         static const unsigned int cl_vco[8] = {
6984                 [0] = 3200000,
6985                 [1] = 4000000,
6986                 [2] = 5333333,
6987                 [3] = 6400000,
6988                 [4] = 3333333,
6989                 [5] = 3566667,
6990                 [6] = 4266667,
6991         };
6992         static const unsigned int elk_vco[8] = {
6993                 [0] = 3200000,
6994                 [1] = 4000000,
6995                 [2] = 5333333,
6996                 [3] = 4800000,
6997         };
6998         static const unsigned int ctg_vco[8] = {
6999                 [0] = 3200000,
7000                 [1] = 4000000,
7001                 [2] = 5333333,
7002                 [3] = 6400000,
7003                 [4] = 2666667,
7004                 [5] = 4266667,
7005         };
7006         const unsigned int *vco_table;
7007         unsigned int vco;
7008         uint8_t tmp = 0;
7009
7010         /* FIXME other chipsets? */
7011         if (IS_GM45(dev))
7012                 vco_table = ctg_vco;
7013         else if (IS_G4X(dev))
7014                 vco_table = elk_vco;
7015         else if (IS_CRESTLINE(dev))
7016                 vco_table = cl_vco;
7017         else if (IS_PINEVIEW(dev))
7018                 vco_table = pnv_vco;
7019         else if (IS_G33(dev))
7020                 vco_table = blb_vco;
7021         else
7022                 return 0;
7023
7024         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7025
7026         vco = vco_table[tmp & 0x7];
7027         if (vco == 0)
7028                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7029         else
7030                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7031
7032         return vco;
7033 }
7034
7035 static int gm45_get_display_clock_speed(struct drm_device *dev)
7036 {
7037         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7038         uint16_t tmp = 0;
7039
7040         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7041
7042         cdclk_sel = (tmp >> 12) & 0x1;
7043
7044         switch (vco) {
7045         case 2666667:
7046         case 4000000:
7047         case 5333333:
7048                 return cdclk_sel ? 333333 : 222222;
7049         case 3200000:
7050                 return cdclk_sel ? 320000 : 228571;
7051         default:
7052                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7053                 return 222222;
7054         }
7055 }
7056
7057 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7058 {
7059         static const uint8_t div_3200[] = { 16, 10,  8 };
7060         static const uint8_t div_4000[] = { 20, 12, 10 };
7061         static const uint8_t div_5333[] = { 24, 16, 14 };
7062         const uint8_t *div_table;
7063         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7064         uint16_t tmp = 0;
7065
7066         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7067
7068         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7069
7070         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7071                 goto fail;
7072
7073         switch (vco) {
7074         case 3200000:
7075                 div_table = div_3200;
7076                 break;
7077         case 4000000:
7078                 div_table = div_4000;
7079                 break;
7080         case 5333333:
7081                 div_table = div_5333;
7082                 break;
7083         default:
7084                 goto fail;
7085         }
7086
7087         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7088
7089 fail:
7090         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7091         return 200000;
7092 }
7093
7094 static int g33_get_display_clock_speed(struct drm_device *dev)
7095 {
7096         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7097         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7098         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7099         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7100         const uint8_t *div_table;
7101         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7102         uint16_t tmp = 0;
7103
7104         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7105
7106         cdclk_sel = (tmp >> 4) & 0x7;
7107
7108         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7109                 goto fail;
7110
7111         switch (vco) {
7112         case 3200000:
7113                 div_table = div_3200;
7114                 break;
7115         case 4000000:
7116                 div_table = div_4000;
7117                 break;
7118         case 4800000:
7119                 div_table = div_4800;
7120                 break;
7121         case 5333333:
7122                 div_table = div_5333;
7123                 break;
7124         default:
7125                 goto fail;
7126         }
7127
7128         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7129
7130 fail:
7131         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7132         return 190476;
7133 }
7134
7135 static void
7136 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7137 {
7138         while (*num > DATA_LINK_M_N_MASK ||
7139                *den > DATA_LINK_M_N_MASK) {
7140                 *num >>= 1;
7141                 *den >>= 1;
7142         }
7143 }
7144
7145 static void compute_m_n(unsigned int m, unsigned int n,
7146                         uint32_t *ret_m, uint32_t *ret_n)
7147 {
7148         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7149         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7150         intel_reduce_m_n_ratio(ret_m, ret_n);
7151 }
7152
7153 void
7154 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7155                        int pixel_clock, int link_clock,
7156                        struct intel_link_m_n *m_n)
7157 {
7158         m_n->tu = 64;
7159
7160         compute_m_n(bits_per_pixel * pixel_clock,
7161                     link_clock * nlanes * 8,
7162                     &m_n->gmch_m, &m_n->gmch_n);
7163
7164         compute_m_n(pixel_clock, link_clock,
7165                     &m_n->link_m, &m_n->link_n);
7166 }
7167
7168 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7169 {
7170         if (i915.panel_use_ssc >= 0)
7171                 return i915.panel_use_ssc != 0;
7172         return dev_priv->vbt.lvds_use_ssc
7173                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7174 }
7175
7176 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7177                            int num_connectors)
7178 {
7179         struct drm_device *dev = crtc_state->base.crtc->dev;
7180         struct drm_i915_private *dev_priv = dev->dev_private;
7181         int refclk;
7182
7183         WARN_ON(!crtc_state->base.state);
7184
7185         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7186                 refclk = 100000;
7187         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7188             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7189                 refclk = dev_priv->vbt.lvds_ssc_freq;
7190                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7191         } else if (!IS_GEN2(dev)) {
7192                 refclk = 96000;
7193         } else {
7194                 refclk = 48000;
7195         }
7196
7197         return refclk;
7198 }
7199
7200 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7201 {
7202         return (1 << dpll->n) << 16 | dpll->m2;
7203 }
7204
7205 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7206 {
7207         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7208 }
7209
7210 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7211                                      struct intel_crtc_state *crtc_state,
7212                                      intel_clock_t *reduced_clock)
7213 {
7214         struct drm_device *dev = crtc->base.dev;
7215         u32 fp, fp2 = 0;
7216
7217         if (IS_PINEVIEW(dev)) {
7218                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7219                 if (reduced_clock)
7220                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7221         } else {
7222                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7223                 if (reduced_clock)
7224                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7225         }
7226
7227         crtc_state->dpll_hw_state.fp0 = fp;
7228
7229         crtc->lowfreq_avail = false;
7230         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7231             reduced_clock) {
7232                 crtc_state->dpll_hw_state.fp1 = fp2;
7233                 crtc->lowfreq_avail = true;
7234         } else {
7235                 crtc_state->dpll_hw_state.fp1 = fp;
7236         }
7237 }
7238
7239 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7240                 pipe)
7241 {
7242         u32 reg_val;
7243
7244         /*
7245          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7246          * and set it to a reasonable value instead.
7247          */
7248         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7249         reg_val &= 0xffffff00;
7250         reg_val |= 0x00000030;
7251         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7252
7253         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7254         reg_val &= 0x8cffffff;
7255         reg_val = 0x8c000000;
7256         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7257
7258         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7259         reg_val &= 0xffffff00;
7260         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7261
7262         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7263         reg_val &= 0x00ffffff;
7264         reg_val |= 0xb0000000;
7265         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7266 }
7267
7268 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7269                                          struct intel_link_m_n *m_n)
7270 {
7271         struct drm_device *dev = crtc->base.dev;
7272         struct drm_i915_private *dev_priv = dev->dev_private;
7273         int pipe = crtc->pipe;
7274
7275         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7276         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7277         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7278         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7279 }
7280
7281 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7282                                          struct intel_link_m_n *m_n,
7283                                          struct intel_link_m_n *m2_n2)
7284 {
7285         struct drm_device *dev = crtc->base.dev;
7286         struct drm_i915_private *dev_priv = dev->dev_private;
7287         int pipe = crtc->pipe;
7288         enum transcoder transcoder = crtc->config->cpu_transcoder;
7289
7290         if (INTEL_INFO(dev)->gen >= 5) {
7291                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7292                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7293                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7294                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7295                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7296                  * for gen < 8) and if DRRS is supported (to make sure the
7297                  * registers are not unnecessarily accessed).
7298                  */
7299                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7300                         crtc->config->has_drrs) {
7301                         I915_WRITE(PIPE_DATA_M2(transcoder),
7302                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7303                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7304                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7305                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7306                 }
7307         } else {
7308                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7309                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7310                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7311                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7312         }
7313 }
7314
7315 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7316 {
7317         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7318
7319         if (m_n == M1_N1) {
7320                 dp_m_n = &crtc->config->dp_m_n;
7321                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7322         } else if (m_n == M2_N2) {
7323
7324                 /*
7325                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7326                  * needs to be programmed into M1_N1.
7327                  */
7328                 dp_m_n = &crtc->config->dp_m2_n2;
7329         } else {
7330                 DRM_ERROR("Unsupported divider value\n");
7331                 return;
7332         }
7333
7334         if (crtc->config->has_pch_encoder)
7335                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7336         else
7337                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7338 }
7339
7340 static void vlv_compute_dpll(struct intel_crtc *crtc,
7341                              struct intel_crtc_state *pipe_config)
7342 {
7343         u32 dpll, dpll_md;
7344
7345         /*
7346          * Enable DPIO clock input. We should never disable the reference
7347          * clock for pipe B, since VGA hotplug / manual detection depends
7348          * on it.
7349          */
7350         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7351                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7352         /* We should never disable this, set it here for state tracking */
7353         if (crtc->pipe == PIPE_B)
7354                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7355         dpll |= DPLL_VCO_ENABLE;
7356         pipe_config->dpll_hw_state.dpll = dpll;
7357
7358         dpll_md = (pipe_config->pixel_multiplier - 1)
7359                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7360         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7361 }
7362
7363 static void vlv_prepare_pll(struct intel_crtc *crtc,
7364                             const struct intel_crtc_state *pipe_config)
7365 {
7366         struct drm_device *dev = crtc->base.dev;
7367         struct drm_i915_private *dev_priv = dev->dev_private;
7368         int pipe = crtc->pipe;
7369         u32 mdiv;
7370         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7371         u32 coreclk, reg_val;
7372
7373         mutex_lock(&dev_priv->sb_lock);
7374
7375         bestn = pipe_config->dpll.n;
7376         bestm1 = pipe_config->dpll.m1;
7377         bestm2 = pipe_config->dpll.m2;
7378         bestp1 = pipe_config->dpll.p1;
7379         bestp2 = pipe_config->dpll.p2;
7380
7381         /* See eDP HDMI DPIO driver vbios notes doc */
7382
7383         /* PLL B needs special handling */
7384         if (pipe == PIPE_B)
7385                 vlv_pllb_recal_opamp(dev_priv, pipe);
7386
7387         /* Set up Tx target for periodic Rcomp update */
7388         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7389
7390         /* Disable target IRef on PLL */
7391         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7392         reg_val &= 0x00ffffff;
7393         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7394
7395         /* Disable fast lock */
7396         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7397
7398         /* Set idtafcrecal before PLL is enabled */
7399         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7400         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7401         mdiv |= ((bestn << DPIO_N_SHIFT));
7402         mdiv |= (1 << DPIO_K_SHIFT);
7403
7404         /*
7405          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7406          * but we don't support that).
7407          * Note: don't use the DAC post divider as it seems unstable.
7408          */
7409         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7410         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7411
7412         mdiv |= DPIO_ENABLE_CALIBRATION;
7413         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7414
7415         /* Set HBR and RBR LPF coefficients */
7416         if (pipe_config->port_clock == 162000 ||
7417             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7418             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7419                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7420                                  0x009f0003);
7421         else
7422                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7423                                  0x00d0000f);
7424
7425         if (pipe_config->has_dp_encoder) {
7426                 /* Use SSC source */
7427                 if (pipe == PIPE_A)
7428                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7429                                          0x0df40000);
7430                 else
7431                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7432                                          0x0df70000);
7433         } else { /* HDMI or VGA */
7434                 /* Use bend source */
7435                 if (pipe == PIPE_A)
7436                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7437                                          0x0df70000);
7438                 else
7439                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7440                                          0x0df40000);
7441         }
7442
7443         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7444         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7445         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7446             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7447                 coreclk |= 0x01000000;
7448         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7449
7450         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7451         mutex_unlock(&dev_priv->sb_lock);
7452 }
7453
7454 static void chv_compute_dpll(struct intel_crtc *crtc,
7455                              struct intel_crtc_state *pipe_config)
7456 {
7457         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7458                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7459                 DPLL_VCO_ENABLE;
7460         if (crtc->pipe != PIPE_A)
7461                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7462
7463         pipe_config->dpll_hw_state.dpll_md =
7464                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7465 }
7466
7467 static void chv_prepare_pll(struct intel_crtc *crtc,
7468                             const struct intel_crtc_state *pipe_config)
7469 {
7470         struct drm_device *dev = crtc->base.dev;
7471         struct drm_i915_private *dev_priv = dev->dev_private;
7472         int pipe = crtc->pipe;
7473         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7474         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7475         u32 loopfilter, tribuf_calcntr;
7476         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7477         u32 dpio_val;
7478         int vco;
7479
7480         bestn = pipe_config->dpll.n;
7481         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7482         bestm1 = pipe_config->dpll.m1;
7483         bestm2 = pipe_config->dpll.m2 >> 22;
7484         bestp1 = pipe_config->dpll.p1;
7485         bestp2 = pipe_config->dpll.p2;
7486         vco = pipe_config->dpll.vco;
7487         dpio_val = 0;
7488         loopfilter = 0;
7489
7490         /*
7491          * Enable Refclk and SSC
7492          */
7493         I915_WRITE(dpll_reg,
7494                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7495
7496         mutex_lock(&dev_priv->sb_lock);
7497
7498         /* p1 and p2 divider */
7499         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7500                         5 << DPIO_CHV_S1_DIV_SHIFT |
7501                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7502                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7503                         1 << DPIO_CHV_K_DIV_SHIFT);
7504
7505         /* Feedback post-divider - m2 */
7506         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7507
7508         /* Feedback refclk divider - n and m1 */
7509         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7510                         DPIO_CHV_M1_DIV_BY_2 |
7511                         1 << DPIO_CHV_N_DIV_SHIFT);
7512
7513         /* M2 fraction division */
7514         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7515
7516         /* M2 fraction division enable */
7517         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7518         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7519         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7520         if (bestm2_frac)
7521                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7522         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7523
7524         /* Program digital lock detect threshold */
7525         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7526         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7527                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7528         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7529         if (!bestm2_frac)
7530                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7531         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7532
7533         /* Loop filter */
7534         if (vco == 5400000) {
7535                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7536                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7537                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7538                 tribuf_calcntr = 0x9;
7539         } else if (vco <= 6200000) {
7540                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7541                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7542                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7543                 tribuf_calcntr = 0x9;
7544         } else if (vco <= 6480000) {
7545                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7546                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7547                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7548                 tribuf_calcntr = 0x8;
7549         } else {
7550                 /* Not supported. Apply the same limits as in the max case */
7551                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7552                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7553                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7554                 tribuf_calcntr = 0;
7555         }
7556         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7557
7558         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7559         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7560         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7561         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7562
7563         /* AFC Recal */
7564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7565                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7566                         DPIO_AFC_RECAL);
7567
7568         mutex_unlock(&dev_priv->sb_lock);
7569 }
7570
7571 /**
7572  * vlv_force_pll_on - forcibly enable just the PLL
7573  * @dev_priv: i915 private structure
7574  * @pipe: pipe PLL to enable
7575  * @dpll: PLL configuration
7576  *
7577  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7578  * in cases where we need the PLL enabled even when @pipe is not going to
7579  * be enabled.
7580  */
7581 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7582                       const struct dpll *dpll)
7583 {
7584         struct intel_crtc *crtc =
7585                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7586         struct intel_crtc_state pipe_config = {
7587                 .base.crtc = &crtc->base,
7588                 .pixel_multiplier = 1,
7589                 .dpll = *dpll,
7590         };
7591
7592         if (IS_CHERRYVIEW(dev)) {
7593                 chv_compute_dpll(crtc, &pipe_config);
7594                 chv_prepare_pll(crtc, &pipe_config);
7595                 chv_enable_pll(crtc, &pipe_config);
7596         } else {
7597                 vlv_compute_dpll(crtc, &pipe_config);
7598                 vlv_prepare_pll(crtc, &pipe_config);
7599                 vlv_enable_pll(crtc, &pipe_config);
7600         }
7601 }
7602
7603 /**
7604  * vlv_force_pll_off - forcibly disable just the PLL
7605  * @dev_priv: i915 private structure
7606  * @pipe: pipe PLL to disable
7607  *
7608  * Disable the PLL for @pipe. To be used in cases where we need
7609  * the PLL enabled even when @pipe is not going to be enabled.
7610  */
7611 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7612 {
7613         if (IS_CHERRYVIEW(dev))
7614                 chv_disable_pll(to_i915(dev), pipe);
7615         else
7616                 vlv_disable_pll(to_i915(dev), pipe);
7617 }
7618
7619 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7620                               struct intel_crtc_state *crtc_state,
7621                               intel_clock_t *reduced_clock,
7622                               int num_connectors)
7623 {
7624         struct drm_device *dev = crtc->base.dev;
7625         struct drm_i915_private *dev_priv = dev->dev_private;
7626         u32 dpll;
7627         bool is_sdvo;
7628         struct dpll *clock = &crtc_state->dpll;
7629
7630         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7631
7632         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7633                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7634
7635         dpll = DPLL_VGA_MODE_DIS;
7636
7637         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7638                 dpll |= DPLLB_MODE_LVDS;
7639         else
7640                 dpll |= DPLLB_MODE_DAC_SERIAL;
7641
7642         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7643                 dpll |= (crtc_state->pixel_multiplier - 1)
7644                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7645         }
7646
7647         if (is_sdvo)
7648                 dpll |= DPLL_SDVO_HIGH_SPEED;
7649
7650         if (crtc_state->has_dp_encoder)
7651                 dpll |= DPLL_SDVO_HIGH_SPEED;
7652
7653         /* compute bitmask from p1 value */
7654         if (IS_PINEVIEW(dev))
7655                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7656         else {
7657                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7658                 if (IS_G4X(dev) && reduced_clock)
7659                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7660         }
7661         switch (clock->p2) {
7662         case 5:
7663                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7664                 break;
7665         case 7:
7666                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7667                 break;
7668         case 10:
7669                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7670                 break;
7671         case 14:
7672                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7673                 break;
7674         }
7675         if (INTEL_INFO(dev)->gen >= 4)
7676                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7677
7678         if (crtc_state->sdvo_tv_clock)
7679                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7680         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7681                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7682                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7683         else
7684                 dpll |= PLL_REF_INPUT_DREFCLK;
7685
7686         dpll |= DPLL_VCO_ENABLE;
7687         crtc_state->dpll_hw_state.dpll = dpll;
7688
7689         if (INTEL_INFO(dev)->gen >= 4) {
7690                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7691                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7692                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7693         }
7694 }
7695
7696 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7697                               struct intel_crtc_state *crtc_state,
7698                               intel_clock_t *reduced_clock,
7699                               int num_connectors)
7700 {
7701         struct drm_device *dev = crtc->base.dev;
7702         struct drm_i915_private *dev_priv = dev->dev_private;
7703         u32 dpll;
7704         struct dpll *clock = &crtc_state->dpll;
7705
7706         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7707
7708         dpll = DPLL_VGA_MODE_DIS;
7709
7710         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7711                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7712         } else {
7713                 if (clock->p1 == 2)
7714                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7715                 else
7716                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7717                 if (clock->p2 == 4)
7718                         dpll |= PLL_P2_DIVIDE_BY_4;
7719         }
7720
7721         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7722                 dpll |= DPLL_DVO_2X_MODE;
7723
7724         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7725                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7726                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7727         else
7728                 dpll |= PLL_REF_INPUT_DREFCLK;
7729
7730         dpll |= DPLL_VCO_ENABLE;
7731         crtc_state->dpll_hw_state.dpll = dpll;
7732 }
7733
7734 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7735 {
7736         struct drm_device *dev = intel_crtc->base.dev;
7737         struct drm_i915_private *dev_priv = dev->dev_private;
7738         enum pipe pipe = intel_crtc->pipe;
7739         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7740         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7741         uint32_t crtc_vtotal, crtc_vblank_end;
7742         int vsyncshift = 0;
7743
7744         /* We need to be careful not to changed the adjusted mode, for otherwise
7745          * the hw state checker will get angry at the mismatch. */
7746         crtc_vtotal = adjusted_mode->crtc_vtotal;
7747         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7748
7749         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7750                 /* the chip adds 2 halflines automatically */
7751                 crtc_vtotal -= 1;
7752                 crtc_vblank_end -= 1;
7753
7754                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7755                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7756                 else
7757                         vsyncshift = adjusted_mode->crtc_hsync_start -
7758                                 adjusted_mode->crtc_htotal / 2;
7759                 if (vsyncshift < 0)
7760                         vsyncshift += adjusted_mode->crtc_htotal;
7761         }
7762
7763         if (INTEL_INFO(dev)->gen > 3)
7764                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7765
7766         I915_WRITE(HTOTAL(cpu_transcoder),
7767                    (adjusted_mode->crtc_hdisplay - 1) |
7768                    ((adjusted_mode->crtc_htotal - 1) << 16));
7769         I915_WRITE(HBLANK(cpu_transcoder),
7770                    (adjusted_mode->crtc_hblank_start - 1) |
7771                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7772         I915_WRITE(HSYNC(cpu_transcoder),
7773                    (adjusted_mode->crtc_hsync_start - 1) |
7774                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7775
7776         I915_WRITE(VTOTAL(cpu_transcoder),
7777                    (adjusted_mode->crtc_vdisplay - 1) |
7778                    ((crtc_vtotal - 1) << 16));
7779         I915_WRITE(VBLANK(cpu_transcoder),
7780                    (adjusted_mode->crtc_vblank_start - 1) |
7781                    ((crtc_vblank_end - 1) << 16));
7782         I915_WRITE(VSYNC(cpu_transcoder),
7783                    (adjusted_mode->crtc_vsync_start - 1) |
7784                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7785
7786         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7787          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7788          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7789          * bits. */
7790         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7791             (pipe == PIPE_B || pipe == PIPE_C))
7792                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7793
7794         /* pipesrc controls the size that is scaled from, which should
7795          * always be the user's requested size.
7796          */
7797         I915_WRITE(PIPESRC(pipe),
7798                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7799                    (intel_crtc->config->pipe_src_h - 1));
7800 }
7801
7802 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7803                                    struct intel_crtc_state *pipe_config)
7804 {
7805         struct drm_device *dev = crtc->base.dev;
7806         struct drm_i915_private *dev_priv = dev->dev_private;
7807         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7808         uint32_t tmp;
7809
7810         tmp = I915_READ(HTOTAL(cpu_transcoder));
7811         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7812         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7813         tmp = I915_READ(HBLANK(cpu_transcoder));
7814         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7815         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7816         tmp = I915_READ(HSYNC(cpu_transcoder));
7817         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7818         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7819
7820         tmp = I915_READ(VTOTAL(cpu_transcoder));
7821         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7822         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7823         tmp = I915_READ(VBLANK(cpu_transcoder));
7824         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7825         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7826         tmp = I915_READ(VSYNC(cpu_transcoder));
7827         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7828         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7829
7830         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7831                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7832                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7833                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7834         }
7835
7836         tmp = I915_READ(PIPESRC(crtc->pipe));
7837         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7838         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7839
7840         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7841         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7842 }
7843
7844 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7845                                  struct intel_crtc_state *pipe_config)
7846 {
7847         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7848         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7849         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7850         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7851
7852         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7853         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7854         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7855         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7856
7857         mode->flags = pipe_config->base.adjusted_mode.flags;
7858         mode->type = DRM_MODE_TYPE_DRIVER;
7859
7860         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7861         mode->flags |= pipe_config->base.adjusted_mode.flags;
7862
7863         mode->hsync = drm_mode_hsync(mode);
7864         mode->vrefresh = drm_mode_vrefresh(mode);
7865         drm_mode_set_name(mode);
7866 }
7867
7868 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7869 {
7870         struct drm_device *dev = intel_crtc->base.dev;
7871         struct drm_i915_private *dev_priv = dev->dev_private;
7872         uint32_t pipeconf;
7873
7874         pipeconf = 0;
7875
7876         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7877             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7878                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7879
7880         if (intel_crtc->config->double_wide)
7881                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7882
7883         /* only g4x and later have fancy bpc/dither controls */
7884         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7885                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7886                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7887                         pipeconf |= PIPECONF_DITHER_EN |
7888                                     PIPECONF_DITHER_TYPE_SP;
7889
7890                 switch (intel_crtc->config->pipe_bpp) {
7891                 case 18:
7892                         pipeconf |= PIPECONF_6BPC;
7893                         break;
7894                 case 24:
7895                         pipeconf |= PIPECONF_8BPC;
7896                         break;
7897                 case 30:
7898                         pipeconf |= PIPECONF_10BPC;
7899                         break;
7900                 default:
7901                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7902                         BUG();
7903                 }
7904         }
7905
7906         if (HAS_PIPE_CXSR(dev)) {
7907                 if (intel_crtc->lowfreq_avail) {
7908                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7909                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7910                 } else {
7911                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7912                 }
7913         }
7914
7915         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7916                 if (INTEL_INFO(dev)->gen < 4 ||
7917                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7918                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7919                 else
7920                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7921         } else
7922                 pipeconf |= PIPECONF_PROGRESSIVE;
7923
7924         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7925                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7926
7927         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7928         POSTING_READ(PIPECONF(intel_crtc->pipe));
7929 }
7930
7931 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7932                                    struct intel_crtc_state *crtc_state)
7933 {
7934         struct drm_device *dev = crtc->base.dev;
7935         struct drm_i915_private *dev_priv = dev->dev_private;
7936         int refclk, num_connectors = 0;
7937         intel_clock_t clock;
7938         bool ok;
7939         const intel_limit_t *limit;
7940         struct drm_atomic_state *state = crtc_state->base.state;
7941         struct drm_connector *connector;
7942         struct drm_connector_state *connector_state;
7943         int i;
7944
7945         memset(&crtc_state->dpll_hw_state, 0,
7946                sizeof(crtc_state->dpll_hw_state));
7947
7948         if (crtc_state->has_dsi_encoder)
7949                 return 0;
7950
7951         for_each_connector_in_state(state, connector, connector_state, i) {
7952                 if (connector_state->crtc == &crtc->base)
7953                         num_connectors++;
7954         }
7955
7956         if (!crtc_state->clock_set) {
7957                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7958
7959                 /*
7960                  * Returns a set of divisors for the desired target clock with
7961                  * the given refclk, or FALSE.  The returned values represent
7962                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7963                  * 2) / p1 / p2.
7964                  */
7965                 limit = intel_limit(crtc_state, refclk);
7966                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7967                                                  crtc_state->port_clock,
7968                                                  refclk, NULL, &clock);
7969                 if (!ok) {
7970                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7971                         return -EINVAL;
7972                 }
7973
7974                 /* Compat-code for transition, will disappear. */
7975                 crtc_state->dpll.n = clock.n;
7976                 crtc_state->dpll.m1 = clock.m1;
7977                 crtc_state->dpll.m2 = clock.m2;
7978                 crtc_state->dpll.p1 = clock.p1;
7979                 crtc_state->dpll.p2 = clock.p2;
7980         }
7981
7982         if (IS_GEN2(dev)) {
7983                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7984                                   num_connectors);
7985         } else if (IS_CHERRYVIEW(dev)) {
7986                 chv_compute_dpll(crtc, crtc_state);
7987         } else if (IS_VALLEYVIEW(dev)) {
7988                 vlv_compute_dpll(crtc, crtc_state);
7989         } else {
7990                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7991                                   num_connectors);
7992         }
7993
7994         return 0;
7995 }
7996
7997 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7998                                  struct intel_crtc_state *pipe_config)
7999 {
8000         struct drm_device *dev = crtc->base.dev;
8001         struct drm_i915_private *dev_priv = dev->dev_private;
8002         uint32_t tmp;
8003
8004         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8005                 return;
8006
8007         tmp = I915_READ(PFIT_CONTROL);
8008         if (!(tmp & PFIT_ENABLE))
8009                 return;
8010
8011         /* Check whether the pfit is attached to our pipe. */
8012         if (INTEL_INFO(dev)->gen < 4) {
8013                 if (crtc->pipe != PIPE_B)
8014                         return;
8015         } else {
8016                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8017                         return;
8018         }
8019
8020         pipe_config->gmch_pfit.control = tmp;
8021         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8022         if (INTEL_INFO(dev)->gen < 5)
8023                 pipe_config->gmch_pfit.lvds_border_bits =
8024                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8025 }
8026
8027 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8028                                struct intel_crtc_state *pipe_config)
8029 {
8030         struct drm_device *dev = crtc->base.dev;
8031         struct drm_i915_private *dev_priv = dev->dev_private;
8032         int pipe = pipe_config->cpu_transcoder;
8033         intel_clock_t clock;
8034         u32 mdiv;
8035         int refclk = 100000;
8036
8037         /* In case of MIPI DPLL will not even be used */
8038         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8039                 return;
8040
8041         mutex_lock(&dev_priv->sb_lock);
8042         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8043         mutex_unlock(&dev_priv->sb_lock);
8044
8045         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8046         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8047         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8048         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8049         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8050
8051         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8052 }
8053
8054 static void
8055 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8056                               struct intel_initial_plane_config *plane_config)
8057 {
8058         struct drm_device *dev = crtc->base.dev;
8059         struct drm_i915_private *dev_priv = dev->dev_private;
8060         u32 val, base, offset;
8061         int pipe = crtc->pipe, plane = crtc->plane;
8062         int fourcc, pixel_format;
8063         unsigned int aligned_height;
8064         struct drm_framebuffer *fb;
8065         struct intel_framebuffer *intel_fb;
8066
8067         val = I915_READ(DSPCNTR(plane));
8068         if (!(val & DISPLAY_PLANE_ENABLE))
8069                 return;
8070
8071         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8072         if (!intel_fb) {
8073                 DRM_DEBUG_KMS("failed to alloc fb\n");
8074                 return;
8075         }
8076
8077         fb = &intel_fb->base;
8078
8079         if (INTEL_INFO(dev)->gen >= 4) {
8080                 if (val & DISPPLANE_TILED) {
8081                         plane_config->tiling = I915_TILING_X;
8082                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8083                 }
8084         }
8085
8086         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8087         fourcc = i9xx_format_to_fourcc(pixel_format);
8088         fb->pixel_format = fourcc;
8089         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8090
8091         if (INTEL_INFO(dev)->gen >= 4) {
8092                 if (plane_config->tiling)
8093                         offset = I915_READ(DSPTILEOFF(plane));
8094                 else
8095                         offset = I915_READ(DSPLINOFF(plane));
8096                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8097         } else {
8098                 base = I915_READ(DSPADDR(plane));
8099         }
8100         plane_config->base = base;
8101
8102         val = I915_READ(PIPESRC(pipe));
8103         fb->width = ((val >> 16) & 0xfff) + 1;
8104         fb->height = ((val >> 0) & 0xfff) + 1;
8105
8106         val = I915_READ(DSPSTRIDE(pipe));
8107         fb->pitches[0] = val & 0xffffffc0;
8108
8109         aligned_height = intel_fb_align_height(dev, fb->height,
8110                                                fb->pixel_format,
8111                                                fb->modifier[0]);
8112
8113         plane_config->size = fb->pitches[0] * aligned_height;
8114
8115         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8116                       pipe_name(pipe), plane, fb->width, fb->height,
8117                       fb->bits_per_pixel, base, fb->pitches[0],
8118                       plane_config->size);
8119
8120         plane_config->fb = intel_fb;
8121 }
8122
8123 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8124                                struct intel_crtc_state *pipe_config)
8125 {
8126         struct drm_device *dev = crtc->base.dev;
8127         struct drm_i915_private *dev_priv = dev->dev_private;
8128         int pipe = pipe_config->cpu_transcoder;
8129         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8130         intel_clock_t clock;
8131         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8132         int refclk = 100000;
8133
8134         mutex_lock(&dev_priv->sb_lock);
8135         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8136         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8137         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8138         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8139         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8140         mutex_unlock(&dev_priv->sb_lock);
8141
8142         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8143         clock.m2 = (pll_dw0 & 0xff) << 22;
8144         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8145                 clock.m2 |= pll_dw2 & 0x3fffff;
8146         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8147         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8148         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8149
8150         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8151 }
8152
8153 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8154                                  struct intel_crtc_state *pipe_config)
8155 {
8156         struct drm_device *dev = crtc->base.dev;
8157         struct drm_i915_private *dev_priv = dev->dev_private;
8158         uint32_t tmp;
8159
8160         if (!intel_display_power_is_enabled(dev_priv,
8161                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8162                 return false;
8163
8164         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8165         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8166
8167         tmp = I915_READ(PIPECONF(crtc->pipe));
8168         if (!(tmp & PIPECONF_ENABLE))
8169                 return false;
8170
8171         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8172                 switch (tmp & PIPECONF_BPC_MASK) {
8173                 case PIPECONF_6BPC:
8174                         pipe_config->pipe_bpp = 18;
8175                         break;
8176                 case PIPECONF_8BPC:
8177                         pipe_config->pipe_bpp = 24;
8178                         break;
8179                 case PIPECONF_10BPC:
8180                         pipe_config->pipe_bpp = 30;
8181                         break;
8182                 default:
8183                         break;
8184                 }
8185         }
8186
8187         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8188                 pipe_config->limited_color_range = true;
8189
8190         if (INTEL_INFO(dev)->gen < 4)
8191                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8192
8193         intel_get_pipe_timings(crtc, pipe_config);
8194
8195         i9xx_get_pfit_config(crtc, pipe_config);
8196
8197         if (INTEL_INFO(dev)->gen >= 4) {
8198                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8199                 pipe_config->pixel_multiplier =
8200                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8201                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8202                 pipe_config->dpll_hw_state.dpll_md = tmp;
8203         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8204                 tmp = I915_READ(DPLL(crtc->pipe));
8205                 pipe_config->pixel_multiplier =
8206                         ((tmp & SDVO_MULTIPLIER_MASK)
8207                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8208         } else {
8209                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8210                  * port and will be fixed up in the encoder->get_config
8211                  * function. */
8212                 pipe_config->pixel_multiplier = 1;
8213         }
8214         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8215         if (!IS_VALLEYVIEW(dev)) {
8216                 /*
8217                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8218                  * on 830. Filter it out here so that we don't
8219                  * report errors due to that.
8220                  */
8221                 if (IS_I830(dev))
8222                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8223
8224                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8225                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8226         } else {
8227                 /* Mask out read-only status bits. */
8228                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8229                                                      DPLL_PORTC_READY_MASK |
8230                                                      DPLL_PORTB_READY_MASK);
8231         }
8232
8233         if (IS_CHERRYVIEW(dev))
8234                 chv_crtc_clock_get(crtc, pipe_config);
8235         else if (IS_VALLEYVIEW(dev))
8236                 vlv_crtc_clock_get(crtc, pipe_config);
8237         else
8238                 i9xx_crtc_clock_get(crtc, pipe_config);
8239
8240         /*
8241          * Normally the dotclock is filled in by the encoder .get_config()
8242          * but in case the pipe is enabled w/o any ports we need a sane
8243          * default.
8244          */
8245         pipe_config->base.adjusted_mode.crtc_clock =
8246                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8247
8248         return true;
8249 }
8250
8251 static void ironlake_init_pch_refclk(struct drm_device *dev)
8252 {
8253         struct drm_i915_private *dev_priv = dev->dev_private;
8254         struct intel_encoder *encoder;
8255         u32 val, final;
8256         bool has_lvds = false;
8257         bool has_cpu_edp = false;
8258         bool has_panel = false;
8259         bool has_ck505 = false;
8260         bool can_ssc = false;
8261
8262         /* We need to take the global config into account */
8263         for_each_intel_encoder(dev, encoder) {
8264                 switch (encoder->type) {
8265                 case INTEL_OUTPUT_LVDS:
8266                         has_panel = true;
8267                         has_lvds = true;
8268                         break;
8269                 case INTEL_OUTPUT_EDP:
8270                         has_panel = true;
8271                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8272                                 has_cpu_edp = true;
8273                         break;
8274                 default:
8275                         break;
8276                 }
8277         }
8278
8279         if (HAS_PCH_IBX(dev)) {
8280                 has_ck505 = dev_priv->vbt.display_clock_mode;
8281                 can_ssc = has_ck505;
8282         } else {
8283                 has_ck505 = false;
8284                 can_ssc = true;
8285         }
8286
8287         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8288                       has_panel, has_lvds, has_ck505);
8289
8290         /* Ironlake: try to setup display ref clock before DPLL
8291          * enabling. This is only under driver's control after
8292          * PCH B stepping, previous chipset stepping should be
8293          * ignoring this setting.
8294          */
8295         val = I915_READ(PCH_DREF_CONTROL);
8296
8297         /* As we must carefully and slowly disable/enable each source in turn,
8298          * compute the final state we want first and check if we need to
8299          * make any changes at all.
8300          */
8301         final = val;
8302         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8303         if (has_ck505)
8304                 final |= DREF_NONSPREAD_CK505_ENABLE;
8305         else
8306                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8307
8308         final &= ~DREF_SSC_SOURCE_MASK;
8309         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8310         final &= ~DREF_SSC1_ENABLE;
8311
8312         if (has_panel) {
8313                 final |= DREF_SSC_SOURCE_ENABLE;
8314
8315                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8316                         final |= DREF_SSC1_ENABLE;
8317
8318                 if (has_cpu_edp) {
8319                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8320                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8321                         else
8322                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8323                 } else
8324                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8325         } else {
8326                 final |= DREF_SSC_SOURCE_DISABLE;
8327                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8328         }
8329
8330         if (final == val)
8331                 return;
8332
8333         /* Always enable nonspread source */
8334         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8335
8336         if (has_ck505)
8337                 val |= DREF_NONSPREAD_CK505_ENABLE;
8338         else
8339                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8340
8341         if (has_panel) {
8342                 val &= ~DREF_SSC_SOURCE_MASK;
8343                 val |= DREF_SSC_SOURCE_ENABLE;
8344
8345                 /* SSC must be turned on before enabling the CPU output  */
8346                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8347                         DRM_DEBUG_KMS("Using SSC on panel\n");
8348                         val |= DREF_SSC1_ENABLE;
8349                 } else
8350                         val &= ~DREF_SSC1_ENABLE;
8351
8352                 /* Get SSC going before enabling the outputs */
8353                 I915_WRITE(PCH_DREF_CONTROL, val);
8354                 POSTING_READ(PCH_DREF_CONTROL);
8355                 udelay(200);
8356
8357                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8358
8359                 /* Enable CPU source on CPU attached eDP */
8360                 if (has_cpu_edp) {
8361                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8362                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8363                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8364                         } else
8365                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8366                 } else
8367                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8368
8369                 I915_WRITE(PCH_DREF_CONTROL, val);
8370                 POSTING_READ(PCH_DREF_CONTROL);
8371                 udelay(200);
8372         } else {
8373                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8374
8375                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8376
8377                 /* Turn off CPU output */
8378                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8379
8380                 I915_WRITE(PCH_DREF_CONTROL, val);
8381                 POSTING_READ(PCH_DREF_CONTROL);
8382                 udelay(200);
8383
8384                 /* Turn off the SSC source */
8385                 val &= ~DREF_SSC_SOURCE_MASK;
8386                 val |= DREF_SSC_SOURCE_DISABLE;
8387
8388                 /* Turn off SSC1 */
8389                 val &= ~DREF_SSC1_ENABLE;
8390
8391                 I915_WRITE(PCH_DREF_CONTROL, val);
8392                 POSTING_READ(PCH_DREF_CONTROL);
8393                 udelay(200);
8394         }
8395
8396         BUG_ON(val != final);
8397 }
8398
8399 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8400 {
8401         uint32_t tmp;
8402
8403         tmp = I915_READ(SOUTH_CHICKEN2);
8404         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8405         I915_WRITE(SOUTH_CHICKEN2, tmp);
8406
8407         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8408                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8409                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8410
8411         tmp = I915_READ(SOUTH_CHICKEN2);
8412         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8413         I915_WRITE(SOUTH_CHICKEN2, tmp);
8414
8415         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8416                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8417                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8418 }
8419
8420 /* WaMPhyProgramming:hsw */
8421 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8422 {
8423         uint32_t tmp;
8424
8425         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8426         tmp &= ~(0xFF << 24);
8427         tmp |= (0x12 << 24);
8428         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8429
8430         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8431         tmp |= (1 << 11);
8432         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8433
8434         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8435         tmp |= (1 << 11);
8436         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8439         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8440         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8441
8442         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8443         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8444         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8445
8446         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8447         tmp &= ~(7 << 13);
8448         tmp |= (5 << 13);
8449         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8450
8451         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8452         tmp &= ~(7 << 13);
8453         tmp |= (5 << 13);
8454         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8455
8456         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8457         tmp &= ~0xFF;
8458         tmp |= 0x1C;
8459         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8460
8461         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8462         tmp &= ~0xFF;
8463         tmp |= 0x1C;
8464         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8465
8466         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8467         tmp &= ~(0xFF << 16);
8468         tmp |= (0x1C << 16);
8469         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8470
8471         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8472         tmp &= ~(0xFF << 16);
8473         tmp |= (0x1C << 16);
8474         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8475
8476         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8477         tmp |= (1 << 27);
8478         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8479
8480         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8481         tmp |= (1 << 27);
8482         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8483
8484         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8485         tmp &= ~(0xF << 28);
8486         tmp |= (4 << 28);
8487         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8488
8489         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8490         tmp &= ~(0xF << 28);
8491         tmp |= (4 << 28);
8492         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8493 }
8494
8495 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8496  * Programming" based on the parameters passed:
8497  * - Sequence to enable CLKOUT_DP
8498  * - Sequence to enable CLKOUT_DP without spread
8499  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8500  */
8501 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8502                                  bool with_fdi)
8503 {
8504         struct drm_i915_private *dev_priv = dev->dev_private;
8505         uint32_t reg, tmp;
8506
8507         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8508                 with_spread = true;
8509         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8510                 with_fdi = false;
8511
8512         mutex_lock(&dev_priv->sb_lock);
8513
8514         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8515         tmp &= ~SBI_SSCCTL_DISABLE;
8516         tmp |= SBI_SSCCTL_PATHALT;
8517         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8518
8519         udelay(24);
8520
8521         if (with_spread) {
8522                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8523                 tmp &= ~SBI_SSCCTL_PATHALT;
8524                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8525
8526                 if (with_fdi) {
8527                         lpt_reset_fdi_mphy(dev_priv);
8528                         lpt_program_fdi_mphy(dev_priv);
8529                 }
8530         }
8531
8532         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8533         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8534         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8535         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8536
8537         mutex_unlock(&dev_priv->sb_lock);
8538 }
8539
8540 /* Sequence to disable CLKOUT_DP */
8541 static void lpt_disable_clkout_dp(struct drm_device *dev)
8542 {
8543         struct drm_i915_private *dev_priv = dev->dev_private;
8544         uint32_t reg, tmp;
8545
8546         mutex_lock(&dev_priv->sb_lock);
8547
8548         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8549         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8550         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8551         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8552
8553         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8554         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8555                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8556                         tmp |= SBI_SSCCTL_PATHALT;
8557                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8558                         udelay(32);
8559                 }
8560                 tmp |= SBI_SSCCTL_DISABLE;
8561                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8562         }
8563
8564         mutex_unlock(&dev_priv->sb_lock);
8565 }
8566
8567 static void lpt_init_pch_refclk(struct drm_device *dev)
8568 {
8569         struct intel_encoder *encoder;
8570         bool has_vga = false;
8571
8572         for_each_intel_encoder(dev, encoder) {
8573                 switch (encoder->type) {
8574                 case INTEL_OUTPUT_ANALOG:
8575                         has_vga = true;
8576                         break;
8577                 default:
8578                         break;
8579                 }
8580         }
8581
8582         if (has_vga)
8583                 lpt_enable_clkout_dp(dev, true, true);
8584         else
8585                 lpt_disable_clkout_dp(dev);
8586 }
8587
8588 /*
8589  * Initialize reference clocks when the driver loads
8590  */
8591 void intel_init_pch_refclk(struct drm_device *dev)
8592 {
8593         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8594                 ironlake_init_pch_refclk(dev);
8595         else if (HAS_PCH_LPT(dev))
8596                 lpt_init_pch_refclk(dev);
8597 }
8598
8599 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8600 {
8601         struct drm_device *dev = crtc_state->base.crtc->dev;
8602         struct drm_i915_private *dev_priv = dev->dev_private;
8603         struct drm_atomic_state *state = crtc_state->base.state;
8604         struct drm_connector *connector;
8605         struct drm_connector_state *connector_state;
8606         struct intel_encoder *encoder;
8607         int num_connectors = 0, i;
8608         bool is_lvds = false;
8609
8610         for_each_connector_in_state(state, connector, connector_state, i) {
8611                 if (connector_state->crtc != crtc_state->base.crtc)
8612                         continue;
8613
8614                 encoder = to_intel_encoder(connector_state->best_encoder);
8615
8616                 switch (encoder->type) {
8617                 case INTEL_OUTPUT_LVDS:
8618                         is_lvds = true;
8619                         break;
8620                 default:
8621                         break;
8622                 }
8623                 num_connectors++;
8624         }
8625
8626         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8627                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8628                               dev_priv->vbt.lvds_ssc_freq);
8629                 return dev_priv->vbt.lvds_ssc_freq;
8630         }
8631
8632         return 120000;
8633 }
8634
8635 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8636 {
8637         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8639         int pipe = intel_crtc->pipe;
8640         uint32_t val;
8641
8642         val = 0;
8643
8644         switch (intel_crtc->config->pipe_bpp) {
8645         case 18:
8646                 val |= PIPECONF_6BPC;
8647                 break;
8648         case 24:
8649                 val |= PIPECONF_8BPC;
8650                 break;
8651         case 30:
8652                 val |= PIPECONF_10BPC;
8653                 break;
8654         case 36:
8655                 val |= PIPECONF_12BPC;
8656                 break;
8657         default:
8658                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8659                 BUG();
8660         }
8661
8662         if (intel_crtc->config->dither)
8663                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8664
8665         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8666                 val |= PIPECONF_INTERLACED_ILK;
8667         else
8668                 val |= PIPECONF_PROGRESSIVE;
8669
8670         if (intel_crtc->config->limited_color_range)
8671                 val |= PIPECONF_COLOR_RANGE_SELECT;
8672
8673         I915_WRITE(PIPECONF(pipe), val);
8674         POSTING_READ(PIPECONF(pipe));
8675 }
8676
8677 /*
8678  * Set up the pipe CSC unit.
8679  *
8680  * Currently only full range RGB to limited range RGB conversion
8681  * is supported, but eventually this should handle various
8682  * RGB<->YCbCr scenarios as well.
8683  */
8684 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8685 {
8686         struct drm_device *dev = crtc->dev;
8687         struct drm_i915_private *dev_priv = dev->dev_private;
8688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8689         int pipe = intel_crtc->pipe;
8690         uint16_t coeff = 0x7800; /* 1.0 */
8691
8692         /*
8693          * TODO: Check what kind of values actually come out of the pipe
8694          * with these coeff/postoff values and adjust to get the best
8695          * accuracy. Perhaps we even need to take the bpc value into
8696          * consideration.
8697          */
8698
8699         if (intel_crtc->config->limited_color_range)
8700                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8701
8702         /*
8703          * GY/GU and RY/RU should be the other way around according
8704          * to BSpec, but reality doesn't agree. Just set them up in
8705          * a way that results in the correct picture.
8706          */
8707         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8708         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8709
8710         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8711         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8712
8713         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8714         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8715
8716         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8717         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8718         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8719
8720         if (INTEL_INFO(dev)->gen > 6) {
8721                 uint16_t postoff = 0;
8722
8723                 if (intel_crtc->config->limited_color_range)
8724                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8725
8726                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8727                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8728                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8729
8730                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8731         } else {
8732                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8733
8734                 if (intel_crtc->config->limited_color_range)
8735                         mode |= CSC_BLACK_SCREEN_OFFSET;
8736
8737                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8738         }
8739 }
8740
8741 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8742 {
8743         struct drm_device *dev = crtc->dev;
8744         struct drm_i915_private *dev_priv = dev->dev_private;
8745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8746         enum pipe pipe = intel_crtc->pipe;
8747         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8748         uint32_t val;
8749
8750         val = 0;
8751
8752         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8753                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8754
8755         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8756                 val |= PIPECONF_INTERLACED_ILK;
8757         else
8758                 val |= PIPECONF_PROGRESSIVE;
8759
8760         I915_WRITE(PIPECONF(cpu_transcoder), val);
8761         POSTING_READ(PIPECONF(cpu_transcoder));
8762
8763         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8764         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8765
8766         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8767                 val = 0;
8768
8769                 switch (intel_crtc->config->pipe_bpp) {
8770                 case 18:
8771                         val |= PIPEMISC_DITHER_6_BPC;
8772                         break;
8773                 case 24:
8774                         val |= PIPEMISC_DITHER_8_BPC;
8775                         break;
8776                 case 30:
8777                         val |= PIPEMISC_DITHER_10_BPC;
8778                         break;
8779                 case 36:
8780                         val |= PIPEMISC_DITHER_12_BPC;
8781                         break;
8782                 default:
8783                         /* Case prevented by pipe_config_set_bpp. */
8784                         BUG();
8785                 }
8786
8787                 if (intel_crtc->config->dither)
8788                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8789
8790                 I915_WRITE(PIPEMISC(pipe), val);
8791         }
8792 }
8793
8794 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8795                                     struct intel_crtc_state *crtc_state,
8796                                     intel_clock_t *clock,
8797                                     bool *has_reduced_clock,
8798                                     intel_clock_t *reduced_clock)
8799 {
8800         struct drm_device *dev = crtc->dev;
8801         struct drm_i915_private *dev_priv = dev->dev_private;
8802         int refclk;
8803         const intel_limit_t *limit;
8804         bool ret;
8805
8806         refclk = ironlake_get_refclk(crtc_state);
8807
8808         /*
8809          * Returns a set of divisors for the desired target clock with the given
8810          * refclk, or FALSE.  The returned values represent the clock equation:
8811          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8812          */
8813         limit = intel_limit(crtc_state, refclk);
8814         ret = dev_priv->display.find_dpll(limit, crtc_state,
8815                                           crtc_state->port_clock,
8816                                           refclk, NULL, clock);
8817         if (!ret)
8818                 return false;
8819
8820         return true;
8821 }
8822
8823 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8824 {
8825         /*
8826          * Account for spread spectrum to avoid
8827          * oversubscribing the link. Max center spread
8828          * is 2.5%; use 5% for safety's sake.
8829          */
8830         u32 bps = target_clock * bpp * 21 / 20;
8831         return DIV_ROUND_UP(bps, link_bw * 8);
8832 }
8833
8834 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8835 {
8836         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8837 }
8838
8839 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8840                                       struct intel_crtc_state *crtc_state,
8841                                       u32 *fp,
8842                                       intel_clock_t *reduced_clock, u32 *fp2)
8843 {
8844         struct drm_crtc *crtc = &intel_crtc->base;
8845         struct drm_device *dev = crtc->dev;
8846         struct drm_i915_private *dev_priv = dev->dev_private;
8847         struct drm_atomic_state *state = crtc_state->base.state;
8848         struct drm_connector *connector;
8849         struct drm_connector_state *connector_state;
8850         struct intel_encoder *encoder;
8851         uint32_t dpll;
8852         int factor, num_connectors = 0, i;
8853         bool is_lvds = false, is_sdvo = false;
8854
8855         for_each_connector_in_state(state, connector, connector_state, i) {
8856                 if (connector_state->crtc != crtc_state->base.crtc)
8857                         continue;
8858
8859                 encoder = to_intel_encoder(connector_state->best_encoder);
8860
8861                 switch (encoder->type) {
8862                 case INTEL_OUTPUT_LVDS:
8863                         is_lvds = true;
8864                         break;
8865                 case INTEL_OUTPUT_SDVO:
8866                 case INTEL_OUTPUT_HDMI:
8867                         is_sdvo = true;
8868                         break;
8869                 default:
8870                         break;
8871                 }
8872
8873                 num_connectors++;
8874         }
8875
8876         /* Enable autotuning of the PLL clock (if permissible) */
8877         factor = 21;
8878         if (is_lvds) {
8879                 if ((intel_panel_use_ssc(dev_priv) &&
8880                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8881                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8882                         factor = 25;
8883         } else if (crtc_state->sdvo_tv_clock)
8884                 factor = 20;
8885
8886         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8887                 *fp |= FP_CB_TUNE;
8888
8889         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8890                 *fp2 |= FP_CB_TUNE;
8891
8892         dpll = 0;
8893
8894         if (is_lvds)
8895                 dpll |= DPLLB_MODE_LVDS;
8896         else
8897                 dpll |= DPLLB_MODE_DAC_SERIAL;
8898
8899         dpll |= (crtc_state->pixel_multiplier - 1)
8900                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8901
8902         if (is_sdvo)
8903                 dpll |= DPLL_SDVO_HIGH_SPEED;
8904         if (crtc_state->has_dp_encoder)
8905                 dpll |= DPLL_SDVO_HIGH_SPEED;
8906
8907         /* compute bitmask from p1 value */
8908         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8909         /* also FPA1 */
8910         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8911
8912         switch (crtc_state->dpll.p2) {
8913         case 5:
8914                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8915                 break;
8916         case 7:
8917                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8918                 break;
8919         case 10:
8920                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8921                 break;
8922         case 14:
8923                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8924                 break;
8925         }
8926
8927         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8928                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8929         else
8930                 dpll |= PLL_REF_INPUT_DREFCLK;
8931
8932         return dpll | DPLL_VCO_ENABLE;
8933 }
8934
8935 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8936                                        struct intel_crtc_state *crtc_state)
8937 {
8938         struct drm_device *dev = crtc->base.dev;
8939         intel_clock_t clock, reduced_clock;
8940         u32 dpll = 0, fp = 0, fp2 = 0;
8941         bool ok, has_reduced_clock = false;
8942         bool is_lvds = false;
8943         struct intel_shared_dpll *pll;
8944
8945         memset(&crtc_state->dpll_hw_state, 0,
8946                sizeof(crtc_state->dpll_hw_state));
8947
8948         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8949
8950         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8951              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8952
8953         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8954                                      &has_reduced_clock, &reduced_clock);
8955         if (!ok && !crtc_state->clock_set) {
8956                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8957                 return -EINVAL;
8958         }
8959         /* Compat-code for transition, will disappear. */
8960         if (!crtc_state->clock_set) {
8961                 crtc_state->dpll.n = clock.n;
8962                 crtc_state->dpll.m1 = clock.m1;
8963                 crtc_state->dpll.m2 = clock.m2;
8964                 crtc_state->dpll.p1 = clock.p1;
8965                 crtc_state->dpll.p2 = clock.p2;
8966         }
8967
8968         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8969         if (crtc_state->has_pch_encoder) {
8970                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8971                 if (has_reduced_clock)
8972                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8973
8974                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8975                                              &fp, &reduced_clock,
8976                                              has_reduced_clock ? &fp2 : NULL);
8977
8978                 crtc_state->dpll_hw_state.dpll = dpll;
8979                 crtc_state->dpll_hw_state.fp0 = fp;
8980                 if (has_reduced_clock)
8981                         crtc_state->dpll_hw_state.fp1 = fp2;
8982                 else
8983                         crtc_state->dpll_hw_state.fp1 = fp;
8984
8985                 pll = intel_get_shared_dpll(crtc, crtc_state);
8986                 if (pll == NULL) {
8987                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8988                                          pipe_name(crtc->pipe));
8989                         return -EINVAL;
8990                 }
8991         }
8992
8993         if (is_lvds && has_reduced_clock)
8994                 crtc->lowfreq_avail = true;
8995         else
8996                 crtc->lowfreq_avail = false;
8997
8998         return 0;
8999 }
9000
9001 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9002                                          struct intel_link_m_n *m_n)
9003 {
9004         struct drm_device *dev = crtc->base.dev;
9005         struct drm_i915_private *dev_priv = dev->dev_private;
9006         enum pipe pipe = crtc->pipe;
9007
9008         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9009         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9010         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9011                 & ~TU_SIZE_MASK;
9012         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9013         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9014                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9015 }
9016
9017 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9018                                          enum transcoder transcoder,
9019                                          struct intel_link_m_n *m_n,
9020                                          struct intel_link_m_n *m2_n2)
9021 {
9022         struct drm_device *dev = crtc->base.dev;
9023         struct drm_i915_private *dev_priv = dev->dev_private;
9024         enum pipe pipe = crtc->pipe;
9025
9026         if (INTEL_INFO(dev)->gen >= 5) {
9027                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9028                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9029                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9030                         & ~TU_SIZE_MASK;
9031                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9032                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9033                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9034                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9035                  * gen < 8) and if DRRS is supported (to make sure the
9036                  * registers are not unnecessarily read).
9037                  */
9038                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9039                         crtc->config->has_drrs) {
9040                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9041                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9042                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9043                                         & ~TU_SIZE_MASK;
9044                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9045                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9046                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9047                 }
9048         } else {
9049                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9050                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9051                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9052                         & ~TU_SIZE_MASK;
9053                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9054                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9055                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9056         }
9057 }
9058
9059 void intel_dp_get_m_n(struct intel_crtc *crtc,
9060                       struct intel_crtc_state *pipe_config)
9061 {
9062         if (pipe_config->has_pch_encoder)
9063                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9064         else
9065                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9066                                              &pipe_config->dp_m_n,
9067                                              &pipe_config->dp_m2_n2);
9068 }
9069
9070 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9071                                         struct intel_crtc_state *pipe_config)
9072 {
9073         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9074                                      &pipe_config->fdi_m_n, NULL);
9075 }
9076
9077 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9078                                     struct intel_crtc_state *pipe_config)
9079 {
9080         struct drm_device *dev = crtc->base.dev;
9081         struct drm_i915_private *dev_priv = dev->dev_private;
9082         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9083         uint32_t ps_ctrl = 0;
9084         int id = -1;
9085         int i;
9086
9087         /* find scaler attached to this pipe */
9088         for (i = 0; i < crtc->num_scalers; i++) {
9089                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9090                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9091                         id = i;
9092                         pipe_config->pch_pfit.enabled = true;
9093                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9094                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9095                         break;
9096                 }
9097         }
9098
9099         scaler_state->scaler_id = id;
9100         if (id >= 0) {
9101                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9102         } else {
9103                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9104         }
9105 }
9106
9107 static void
9108 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9109                                  struct intel_initial_plane_config *plane_config)
9110 {
9111         struct drm_device *dev = crtc->base.dev;
9112         struct drm_i915_private *dev_priv = dev->dev_private;
9113         u32 val, base, offset, stride_mult, tiling;
9114         int pipe = crtc->pipe;
9115         int fourcc, pixel_format;
9116         unsigned int aligned_height;
9117         struct drm_framebuffer *fb;
9118         struct intel_framebuffer *intel_fb;
9119
9120         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9121         if (!intel_fb) {
9122                 DRM_DEBUG_KMS("failed to alloc fb\n");
9123                 return;
9124         }
9125
9126         fb = &intel_fb->base;
9127
9128         val = I915_READ(PLANE_CTL(pipe, 0));
9129         if (!(val & PLANE_CTL_ENABLE))
9130                 goto error;
9131
9132         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9133         fourcc = skl_format_to_fourcc(pixel_format,
9134                                       val & PLANE_CTL_ORDER_RGBX,
9135                                       val & PLANE_CTL_ALPHA_MASK);
9136         fb->pixel_format = fourcc;
9137         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9138
9139         tiling = val & PLANE_CTL_TILED_MASK;
9140         switch (tiling) {
9141         case PLANE_CTL_TILED_LINEAR:
9142                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9143                 break;
9144         case PLANE_CTL_TILED_X:
9145                 plane_config->tiling = I915_TILING_X;
9146                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9147                 break;
9148         case PLANE_CTL_TILED_Y:
9149                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9150                 break;
9151         case PLANE_CTL_TILED_YF:
9152                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9153                 break;
9154         default:
9155                 MISSING_CASE(tiling);
9156                 goto error;
9157         }
9158
9159         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9160         plane_config->base = base;
9161
9162         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9163
9164         val = I915_READ(PLANE_SIZE(pipe, 0));
9165         fb->height = ((val >> 16) & 0xfff) + 1;
9166         fb->width = ((val >> 0) & 0x1fff) + 1;
9167
9168         val = I915_READ(PLANE_STRIDE(pipe, 0));
9169         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9170                                                 fb->pixel_format);
9171         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9172
9173         aligned_height = intel_fb_align_height(dev, fb->height,
9174                                                fb->pixel_format,
9175                                                fb->modifier[0]);
9176
9177         plane_config->size = fb->pitches[0] * aligned_height;
9178
9179         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9180                       pipe_name(pipe), fb->width, fb->height,
9181                       fb->bits_per_pixel, base, fb->pitches[0],
9182                       plane_config->size);
9183
9184         plane_config->fb = intel_fb;
9185         return;
9186
9187 error:
9188         kfree(fb);
9189 }
9190
9191 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9192                                      struct intel_crtc_state *pipe_config)
9193 {
9194         struct drm_device *dev = crtc->base.dev;
9195         struct drm_i915_private *dev_priv = dev->dev_private;
9196         uint32_t tmp;
9197
9198         tmp = I915_READ(PF_CTL(crtc->pipe));
9199
9200         if (tmp & PF_ENABLE) {
9201                 pipe_config->pch_pfit.enabled = true;
9202                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9203                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9204
9205                 /* We currently do not free assignements of panel fitters on
9206                  * ivb/hsw (since we don't use the higher upscaling modes which
9207                  * differentiates them) so just WARN about this case for now. */
9208                 if (IS_GEN7(dev)) {
9209                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9210                                 PF_PIPE_SEL_IVB(crtc->pipe));
9211                 }
9212         }
9213 }
9214
9215 static void
9216 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9217                                   struct intel_initial_plane_config *plane_config)
9218 {
9219         struct drm_device *dev = crtc->base.dev;
9220         struct drm_i915_private *dev_priv = dev->dev_private;
9221         u32 val, base, offset;
9222         int pipe = crtc->pipe;
9223         int fourcc, pixel_format;
9224         unsigned int aligned_height;
9225         struct drm_framebuffer *fb;
9226         struct intel_framebuffer *intel_fb;
9227
9228         val = I915_READ(DSPCNTR(pipe));
9229         if (!(val & DISPLAY_PLANE_ENABLE))
9230                 return;
9231
9232         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9233         if (!intel_fb) {
9234                 DRM_DEBUG_KMS("failed to alloc fb\n");
9235                 return;
9236         }
9237
9238         fb = &intel_fb->base;
9239
9240         if (INTEL_INFO(dev)->gen >= 4) {
9241                 if (val & DISPPLANE_TILED) {
9242                         plane_config->tiling = I915_TILING_X;
9243                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9244                 }
9245         }
9246
9247         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9248         fourcc = i9xx_format_to_fourcc(pixel_format);
9249         fb->pixel_format = fourcc;
9250         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9251
9252         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9253         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9254                 offset = I915_READ(DSPOFFSET(pipe));
9255         } else {
9256                 if (plane_config->tiling)
9257                         offset = I915_READ(DSPTILEOFF(pipe));
9258                 else
9259                         offset = I915_READ(DSPLINOFF(pipe));
9260         }
9261         plane_config->base = base;
9262
9263         val = I915_READ(PIPESRC(pipe));
9264         fb->width = ((val >> 16) & 0xfff) + 1;
9265         fb->height = ((val >> 0) & 0xfff) + 1;
9266
9267         val = I915_READ(DSPSTRIDE(pipe));
9268         fb->pitches[0] = val & 0xffffffc0;
9269
9270         aligned_height = intel_fb_align_height(dev, fb->height,
9271                                                fb->pixel_format,
9272                                                fb->modifier[0]);
9273
9274         plane_config->size = fb->pitches[0] * aligned_height;
9275
9276         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9277                       pipe_name(pipe), fb->width, fb->height,
9278                       fb->bits_per_pixel, base, fb->pitches[0],
9279                       plane_config->size);
9280
9281         plane_config->fb = intel_fb;
9282 }
9283
9284 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9285                                      struct intel_crtc_state *pipe_config)
9286 {
9287         struct drm_device *dev = crtc->base.dev;
9288         struct drm_i915_private *dev_priv = dev->dev_private;
9289         uint32_t tmp;
9290
9291         if (!intel_display_power_is_enabled(dev_priv,
9292                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9293                 return false;
9294
9295         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9296         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9297
9298         tmp = I915_READ(PIPECONF(crtc->pipe));
9299         if (!(tmp & PIPECONF_ENABLE))
9300                 return false;
9301
9302         switch (tmp & PIPECONF_BPC_MASK) {
9303         case PIPECONF_6BPC:
9304                 pipe_config->pipe_bpp = 18;
9305                 break;
9306         case PIPECONF_8BPC:
9307                 pipe_config->pipe_bpp = 24;
9308                 break;
9309         case PIPECONF_10BPC:
9310                 pipe_config->pipe_bpp = 30;
9311                 break;
9312         case PIPECONF_12BPC:
9313                 pipe_config->pipe_bpp = 36;
9314                 break;
9315         default:
9316                 break;
9317         }
9318
9319         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9320                 pipe_config->limited_color_range = true;
9321
9322         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9323                 struct intel_shared_dpll *pll;
9324
9325                 pipe_config->has_pch_encoder = true;
9326
9327                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9328                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9329                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9330
9331                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9332
9333                 if (HAS_PCH_IBX(dev_priv->dev)) {
9334                         pipe_config->shared_dpll =
9335                                 (enum intel_dpll_id) crtc->pipe;
9336                 } else {
9337                         tmp = I915_READ(PCH_DPLL_SEL);
9338                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9339                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9340                         else
9341                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9342                 }
9343
9344                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9345
9346                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9347                                            &pipe_config->dpll_hw_state));
9348
9349                 tmp = pipe_config->dpll_hw_state.dpll;
9350                 pipe_config->pixel_multiplier =
9351                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9352                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9353
9354                 ironlake_pch_clock_get(crtc, pipe_config);
9355         } else {
9356                 pipe_config->pixel_multiplier = 1;
9357         }
9358
9359         intel_get_pipe_timings(crtc, pipe_config);
9360
9361         ironlake_get_pfit_config(crtc, pipe_config);
9362
9363         return true;
9364 }
9365
9366 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9367 {
9368         struct drm_device *dev = dev_priv->dev;
9369         struct intel_crtc *crtc;
9370
9371         for_each_intel_crtc(dev, crtc)
9372                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9373                      pipe_name(crtc->pipe));
9374
9375         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9376         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9377         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9378         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9379         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9380         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9381              "CPU PWM1 enabled\n");
9382         if (IS_HASWELL(dev))
9383                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9384                      "CPU PWM2 enabled\n");
9385         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9386              "PCH PWM1 enabled\n");
9387         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9388              "Utility pin enabled\n");
9389         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9390
9391         /*
9392          * In theory we can still leave IRQs enabled, as long as only the HPD
9393          * interrupts remain enabled. We used to check for that, but since it's
9394          * gen-specific and since we only disable LCPLL after we fully disable
9395          * the interrupts, the check below should be enough.
9396          */
9397         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9398 }
9399
9400 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9401 {
9402         struct drm_device *dev = dev_priv->dev;
9403
9404         if (IS_HASWELL(dev))
9405                 return I915_READ(D_COMP_HSW);
9406         else
9407                 return I915_READ(D_COMP_BDW);
9408 }
9409
9410 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9411 {
9412         struct drm_device *dev = dev_priv->dev;
9413
9414         if (IS_HASWELL(dev)) {
9415                 mutex_lock(&dev_priv->rps.hw_lock);
9416                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9417                                             val))
9418                         DRM_ERROR("Failed to write to D_COMP\n");
9419                 mutex_unlock(&dev_priv->rps.hw_lock);
9420         } else {
9421                 I915_WRITE(D_COMP_BDW, val);
9422                 POSTING_READ(D_COMP_BDW);
9423         }
9424 }
9425
9426 /*
9427  * This function implements pieces of two sequences from BSpec:
9428  * - Sequence for display software to disable LCPLL
9429  * - Sequence for display software to allow package C8+
9430  * The steps implemented here are just the steps that actually touch the LCPLL
9431  * register. Callers should take care of disabling all the display engine
9432  * functions, doing the mode unset, fixing interrupts, etc.
9433  */
9434 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9435                               bool switch_to_fclk, bool allow_power_down)
9436 {
9437         uint32_t val;
9438
9439         assert_can_disable_lcpll(dev_priv);
9440
9441         val = I915_READ(LCPLL_CTL);
9442
9443         if (switch_to_fclk) {
9444                 val |= LCPLL_CD_SOURCE_FCLK;
9445                 I915_WRITE(LCPLL_CTL, val);
9446
9447                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9448                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9449                         DRM_ERROR("Switching to FCLK failed\n");
9450
9451                 val = I915_READ(LCPLL_CTL);
9452         }
9453
9454         val |= LCPLL_PLL_DISABLE;
9455         I915_WRITE(LCPLL_CTL, val);
9456         POSTING_READ(LCPLL_CTL);
9457
9458         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9459                 DRM_ERROR("LCPLL still locked\n");
9460
9461         val = hsw_read_dcomp(dev_priv);
9462         val |= D_COMP_COMP_DISABLE;
9463         hsw_write_dcomp(dev_priv, val);
9464         ndelay(100);
9465
9466         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9467                      1))
9468                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9469
9470         if (allow_power_down) {
9471                 val = I915_READ(LCPLL_CTL);
9472                 val |= LCPLL_POWER_DOWN_ALLOW;
9473                 I915_WRITE(LCPLL_CTL, val);
9474                 POSTING_READ(LCPLL_CTL);
9475         }
9476 }
9477
9478 /*
9479  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9480  * source.
9481  */
9482 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9483 {
9484         uint32_t val;
9485
9486         val = I915_READ(LCPLL_CTL);
9487
9488         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9489                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9490                 return;
9491
9492         /*
9493          * Make sure we're not on PC8 state before disabling PC8, otherwise
9494          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9495          */
9496         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9497
9498         if (val & LCPLL_POWER_DOWN_ALLOW) {
9499                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9500                 I915_WRITE(LCPLL_CTL, val);
9501                 POSTING_READ(LCPLL_CTL);
9502         }
9503
9504         val = hsw_read_dcomp(dev_priv);
9505         val |= D_COMP_COMP_FORCE;
9506         val &= ~D_COMP_COMP_DISABLE;
9507         hsw_write_dcomp(dev_priv, val);
9508
9509         val = I915_READ(LCPLL_CTL);
9510         val &= ~LCPLL_PLL_DISABLE;
9511         I915_WRITE(LCPLL_CTL, val);
9512
9513         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9514                 DRM_ERROR("LCPLL not locked yet\n");
9515
9516         if (val & LCPLL_CD_SOURCE_FCLK) {
9517                 val = I915_READ(LCPLL_CTL);
9518                 val &= ~LCPLL_CD_SOURCE_FCLK;
9519                 I915_WRITE(LCPLL_CTL, val);
9520
9521                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9522                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9523                         DRM_ERROR("Switching back to LCPLL failed\n");
9524         }
9525
9526         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9527         intel_update_cdclk(dev_priv->dev);
9528 }
9529
9530 /*
9531  * Package states C8 and deeper are really deep PC states that can only be
9532  * reached when all the devices on the system allow it, so even if the graphics
9533  * device allows PC8+, it doesn't mean the system will actually get to these
9534  * states. Our driver only allows PC8+ when going into runtime PM.
9535  *
9536  * The requirements for PC8+ are that all the outputs are disabled, the power
9537  * well is disabled and most interrupts are disabled, and these are also
9538  * requirements for runtime PM. When these conditions are met, we manually do
9539  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9540  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9541  * hang the machine.
9542  *
9543  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9544  * the state of some registers, so when we come back from PC8+ we need to
9545  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9546  * need to take care of the registers kept by RC6. Notice that this happens even
9547  * if we don't put the device in PCI D3 state (which is what currently happens
9548  * because of the runtime PM support).
9549  *
9550  * For more, read "Display Sequences for Package C8" on the hardware
9551  * documentation.
9552  */
9553 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9554 {
9555         struct drm_device *dev = dev_priv->dev;
9556         uint32_t val;
9557
9558         DRM_DEBUG_KMS("Enabling package C8+\n");
9559
9560         if (HAS_PCH_LPT_LP(dev)) {
9561                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9562                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9563                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9564         }
9565
9566         lpt_disable_clkout_dp(dev);
9567         hsw_disable_lcpll(dev_priv, true, true);
9568 }
9569
9570 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9571 {
9572         struct drm_device *dev = dev_priv->dev;
9573         uint32_t val;
9574
9575         DRM_DEBUG_KMS("Disabling package C8+\n");
9576
9577         hsw_restore_lcpll(dev_priv);
9578         lpt_init_pch_refclk(dev);
9579
9580         if (HAS_PCH_LPT_LP(dev)) {
9581                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9582                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9583                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9584         }
9585
9586         intel_prepare_ddi(dev);
9587 }
9588
9589 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9590 {
9591         struct drm_device *dev = old_state->dev;
9592         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9593
9594         broxton_set_cdclk(dev, req_cdclk);
9595 }
9596
9597 /* compute the max rate for new configuration */
9598 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9599 {
9600         struct intel_crtc *intel_crtc;
9601         struct intel_crtc_state *crtc_state;
9602         int max_pixel_rate = 0;
9603
9604         for_each_intel_crtc(state->dev, intel_crtc) {
9605                 int pixel_rate;
9606
9607                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9608                 if (IS_ERR(crtc_state))
9609                         return PTR_ERR(crtc_state);
9610
9611                 if (!crtc_state->base.enable)
9612                         continue;
9613
9614                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9615
9616                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9617                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9618                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9619
9620                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9621         }
9622
9623         return max_pixel_rate;
9624 }
9625
9626 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9627 {
9628         struct drm_i915_private *dev_priv = dev->dev_private;
9629         uint32_t val, data;
9630         int ret;
9631
9632         if (WARN((I915_READ(LCPLL_CTL) &
9633                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9634                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9635                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9636                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9637                  "trying to change cdclk frequency with cdclk not enabled\n"))
9638                 return;
9639
9640         mutex_lock(&dev_priv->rps.hw_lock);
9641         ret = sandybridge_pcode_write(dev_priv,
9642                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9643         mutex_unlock(&dev_priv->rps.hw_lock);
9644         if (ret) {
9645                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9646                 return;
9647         }
9648
9649         val = I915_READ(LCPLL_CTL);
9650         val |= LCPLL_CD_SOURCE_FCLK;
9651         I915_WRITE(LCPLL_CTL, val);
9652
9653         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9654                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9655                 DRM_ERROR("Switching to FCLK failed\n");
9656
9657         val = I915_READ(LCPLL_CTL);
9658         val &= ~LCPLL_CLK_FREQ_MASK;
9659
9660         switch (cdclk) {
9661         case 450000:
9662                 val |= LCPLL_CLK_FREQ_450;
9663                 data = 0;
9664                 break;
9665         case 540000:
9666                 val |= LCPLL_CLK_FREQ_54O_BDW;
9667                 data = 1;
9668                 break;
9669         case 337500:
9670                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9671                 data = 2;
9672                 break;
9673         case 675000:
9674                 val |= LCPLL_CLK_FREQ_675_BDW;
9675                 data = 3;
9676                 break;
9677         default:
9678                 WARN(1, "invalid cdclk frequency\n");
9679                 return;
9680         }
9681
9682         I915_WRITE(LCPLL_CTL, val);
9683
9684         val = I915_READ(LCPLL_CTL);
9685         val &= ~LCPLL_CD_SOURCE_FCLK;
9686         I915_WRITE(LCPLL_CTL, val);
9687
9688         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9689                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9690                 DRM_ERROR("Switching back to LCPLL failed\n");
9691
9692         mutex_lock(&dev_priv->rps.hw_lock);
9693         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9694         mutex_unlock(&dev_priv->rps.hw_lock);
9695
9696         intel_update_cdclk(dev);
9697
9698         WARN(cdclk != dev_priv->cdclk_freq,
9699              "cdclk requested %d kHz but got %d kHz\n",
9700              cdclk, dev_priv->cdclk_freq);
9701 }
9702
9703 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9704 {
9705         struct drm_i915_private *dev_priv = to_i915(state->dev);
9706         int max_pixclk = ilk_max_pixel_rate(state);
9707         int cdclk;
9708
9709         /*
9710          * FIXME should also account for plane ratio
9711          * once 64bpp pixel formats are supported.
9712          */
9713         if (max_pixclk > 540000)
9714                 cdclk = 675000;
9715         else if (max_pixclk > 450000)
9716                 cdclk = 540000;
9717         else if (max_pixclk > 337500)
9718                 cdclk = 450000;
9719         else
9720                 cdclk = 337500;
9721
9722         if (cdclk > dev_priv->max_cdclk_freq) {
9723                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9724                               cdclk, dev_priv->max_cdclk_freq);
9725                 return -EINVAL;
9726         }
9727
9728         to_intel_atomic_state(state)->cdclk = cdclk;
9729
9730         return 0;
9731 }
9732
9733 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9734 {
9735         struct drm_device *dev = old_state->dev;
9736         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9737
9738         broadwell_set_cdclk(dev, req_cdclk);
9739 }
9740
9741 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9742                                       struct intel_crtc_state *crtc_state)
9743 {
9744         if (!intel_ddi_pll_select(crtc, crtc_state))
9745                 return -EINVAL;
9746
9747         crtc->lowfreq_avail = false;
9748
9749         return 0;
9750 }
9751
9752 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9753                                 enum port port,
9754                                 struct intel_crtc_state *pipe_config)
9755 {
9756         switch (port) {
9757         case PORT_A:
9758                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9759                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9760                 break;
9761         case PORT_B:
9762                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9763                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9764                 break;
9765         case PORT_C:
9766                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9767                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9768                 break;
9769         default:
9770                 DRM_ERROR("Incorrect port type\n");
9771         }
9772 }
9773
9774 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9775                                 enum port port,
9776                                 struct intel_crtc_state *pipe_config)
9777 {
9778         u32 temp, dpll_ctl1;
9779
9780         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9781         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9782
9783         switch (pipe_config->ddi_pll_sel) {
9784         case SKL_DPLL0:
9785                 /*
9786                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9787                  * of the shared DPLL framework and thus needs to be read out
9788                  * separately
9789                  */
9790                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9791                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9792                 break;
9793         case SKL_DPLL1:
9794                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9795                 break;
9796         case SKL_DPLL2:
9797                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9798                 break;
9799         case SKL_DPLL3:
9800                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9801                 break;
9802         }
9803 }
9804
9805 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9806                                 enum port port,
9807                                 struct intel_crtc_state *pipe_config)
9808 {
9809         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9810
9811         switch (pipe_config->ddi_pll_sel) {
9812         case PORT_CLK_SEL_WRPLL1:
9813                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9814                 break;
9815         case PORT_CLK_SEL_WRPLL2:
9816                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9817                 break;
9818         case PORT_CLK_SEL_SPLL:
9819                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9820                 break;
9821         }
9822 }
9823
9824 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9825                                        struct intel_crtc_state *pipe_config)
9826 {
9827         struct drm_device *dev = crtc->base.dev;
9828         struct drm_i915_private *dev_priv = dev->dev_private;
9829         struct intel_shared_dpll *pll;
9830         enum port port;
9831         uint32_t tmp;
9832
9833         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9834
9835         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9836
9837         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9838                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9839         else if (IS_BROXTON(dev))
9840                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9841         else
9842                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9843
9844         if (pipe_config->shared_dpll >= 0) {
9845                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9846
9847                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9848                                            &pipe_config->dpll_hw_state));
9849         }
9850
9851         /*
9852          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9853          * DDI E. So just check whether this pipe is wired to DDI E and whether
9854          * the PCH transcoder is on.
9855          */
9856         if (INTEL_INFO(dev)->gen < 9 &&
9857             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9858                 pipe_config->has_pch_encoder = true;
9859
9860                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9861                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9862                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9863
9864                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9865         }
9866 }
9867
9868 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9869                                     struct intel_crtc_state *pipe_config)
9870 {
9871         struct drm_device *dev = crtc->base.dev;
9872         struct drm_i915_private *dev_priv = dev->dev_private;
9873         enum intel_display_power_domain pfit_domain;
9874         uint32_t tmp;
9875
9876         if (!intel_display_power_is_enabled(dev_priv,
9877                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9878                 return false;
9879
9880         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9881         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9882
9883         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9884         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9885                 enum pipe trans_edp_pipe;
9886                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9887                 default:
9888                         WARN(1, "unknown pipe linked to edp transcoder\n");
9889                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9890                 case TRANS_DDI_EDP_INPUT_A_ON:
9891                         trans_edp_pipe = PIPE_A;
9892                         break;
9893                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9894                         trans_edp_pipe = PIPE_B;
9895                         break;
9896                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9897                         trans_edp_pipe = PIPE_C;
9898                         break;
9899                 }
9900
9901                 if (trans_edp_pipe == crtc->pipe)
9902                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9903         }
9904
9905         if (!intel_display_power_is_enabled(dev_priv,
9906                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9907                 return false;
9908
9909         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9910         if (!(tmp & PIPECONF_ENABLE))
9911                 return false;
9912
9913         haswell_get_ddi_port_state(crtc, pipe_config);
9914
9915         intel_get_pipe_timings(crtc, pipe_config);
9916
9917         if (INTEL_INFO(dev)->gen >= 9) {
9918                 skl_init_scalers(dev, crtc, pipe_config);
9919         }
9920
9921         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9922
9923         if (INTEL_INFO(dev)->gen >= 9) {
9924                 pipe_config->scaler_state.scaler_id = -1;
9925                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9926         }
9927
9928         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9929                 if (INTEL_INFO(dev)->gen >= 9)
9930                         skylake_get_pfit_config(crtc, pipe_config);
9931                 else
9932                         ironlake_get_pfit_config(crtc, pipe_config);
9933         }
9934
9935         if (IS_HASWELL(dev))
9936                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9937                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9938
9939         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9940                 pipe_config->pixel_multiplier =
9941                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9942         } else {
9943                 pipe_config->pixel_multiplier = 1;
9944         }
9945
9946         return true;
9947 }
9948
9949 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9950 {
9951         struct drm_device *dev = crtc->dev;
9952         struct drm_i915_private *dev_priv = dev->dev_private;
9953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9954         uint32_t cntl = 0, size = 0;
9955
9956         if (base) {
9957                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9958                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9959                 unsigned int stride = roundup_pow_of_two(width) * 4;
9960
9961                 switch (stride) {
9962                 default:
9963                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9964                                   width, stride);
9965                         stride = 256;
9966                         /* fallthrough */
9967                 case 256:
9968                 case 512:
9969                 case 1024:
9970                 case 2048:
9971                         break;
9972                 }
9973
9974                 cntl |= CURSOR_ENABLE |
9975                         CURSOR_GAMMA_ENABLE |
9976                         CURSOR_FORMAT_ARGB |
9977                         CURSOR_STRIDE(stride);
9978
9979                 size = (height << 12) | width;
9980         }
9981
9982         if (intel_crtc->cursor_cntl != 0 &&
9983             (intel_crtc->cursor_base != base ||
9984              intel_crtc->cursor_size != size ||
9985              intel_crtc->cursor_cntl != cntl)) {
9986                 /* On these chipsets we can only modify the base/size/stride
9987                  * whilst the cursor is disabled.
9988                  */
9989                 I915_WRITE(CURCNTR(PIPE_A), 0);
9990                 POSTING_READ(CURCNTR(PIPE_A));
9991                 intel_crtc->cursor_cntl = 0;
9992         }
9993
9994         if (intel_crtc->cursor_base != base) {
9995                 I915_WRITE(CURBASE(PIPE_A), base);
9996                 intel_crtc->cursor_base = base;
9997         }
9998
9999         if (intel_crtc->cursor_size != size) {
10000                 I915_WRITE(CURSIZE, size);
10001                 intel_crtc->cursor_size = size;
10002         }
10003
10004         if (intel_crtc->cursor_cntl != cntl) {
10005                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10006                 POSTING_READ(CURCNTR(PIPE_A));
10007                 intel_crtc->cursor_cntl = cntl;
10008         }
10009 }
10010
10011 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10012 {
10013         struct drm_device *dev = crtc->dev;
10014         struct drm_i915_private *dev_priv = dev->dev_private;
10015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10016         int pipe = intel_crtc->pipe;
10017         uint32_t cntl;
10018
10019         cntl = 0;
10020         if (base) {
10021                 cntl = MCURSOR_GAMMA_ENABLE;
10022                 switch (intel_crtc->base.cursor->state->crtc_w) {
10023                         case 64:
10024                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10025                                 break;
10026                         case 128:
10027                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10028                                 break;
10029                         case 256:
10030                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10031                                 break;
10032                         default:
10033                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10034                                 return;
10035                 }
10036                 cntl |= pipe << 28; /* Connect to correct pipe */
10037
10038                 if (HAS_DDI(dev))
10039                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10040         }
10041
10042         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10043                 cntl |= CURSOR_ROTATE_180;
10044
10045         if (intel_crtc->cursor_cntl != cntl) {
10046                 I915_WRITE(CURCNTR(pipe), cntl);
10047                 POSTING_READ(CURCNTR(pipe));
10048                 intel_crtc->cursor_cntl = cntl;
10049         }
10050
10051         /* and commit changes on next vblank */
10052         I915_WRITE(CURBASE(pipe), base);
10053         POSTING_READ(CURBASE(pipe));
10054
10055         intel_crtc->cursor_base = base;
10056 }
10057
10058 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10059 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10060                                      bool on)
10061 {
10062         struct drm_device *dev = crtc->dev;
10063         struct drm_i915_private *dev_priv = dev->dev_private;
10064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10065         int pipe = intel_crtc->pipe;
10066         struct drm_plane_state *cursor_state = crtc->cursor->state;
10067         int x = cursor_state->crtc_x;
10068         int y = cursor_state->crtc_y;
10069         u32 base = 0, pos = 0;
10070
10071         if (on)
10072                 base = intel_crtc->cursor_addr;
10073
10074         if (x >= intel_crtc->config->pipe_src_w)
10075                 base = 0;
10076
10077         if (y >= intel_crtc->config->pipe_src_h)
10078                 base = 0;
10079
10080         if (x < 0) {
10081                 if (x + cursor_state->crtc_w <= 0)
10082                         base = 0;
10083
10084                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10085                 x = -x;
10086         }
10087         pos |= x << CURSOR_X_SHIFT;
10088
10089         if (y < 0) {
10090                 if (y + cursor_state->crtc_h <= 0)
10091                         base = 0;
10092
10093                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10094                 y = -y;
10095         }
10096         pos |= y << CURSOR_Y_SHIFT;
10097
10098         if (base == 0 && intel_crtc->cursor_base == 0)
10099                 return;
10100
10101         I915_WRITE(CURPOS(pipe), pos);
10102
10103         /* ILK+ do this automagically */
10104         if (HAS_GMCH_DISPLAY(dev) &&
10105             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10106                 base += (cursor_state->crtc_h *
10107                          cursor_state->crtc_w - 1) * 4;
10108         }
10109
10110         if (IS_845G(dev) || IS_I865G(dev))
10111                 i845_update_cursor(crtc, base);
10112         else
10113                 i9xx_update_cursor(crtc, base);
10114 }
10115
10116 static bool cursor_size_ok(struct drm_device *dev,
10117                            uint32_t width, uint32_t height)
10118 {
10119         if (width == 0 || height == 0)
10120                 return false;
10121
10122         /*
10123          * 845g/865g are special in that they are only limited by
10124          * the width of their cursors, the height is arbitrary up to
10125          * the precision of the register. Everything else requires
10126          * square cursors, limited to a few power-of-two sizes.
10127          */
10128         if (IS_845G(dev) || IS_I865G(dev)) {
10129                 if ((width & 63) != 0)
10130                         return false;
10131
10132                 if (width > (IS_845G(dev) ? 64 : 512))
10133                         return false;
10134
10135                 if (height > 1023)
10136                         return false;
10137         } else {
10138                 switch (width | height) {
10139                 case 256:
10140                 case 128:
10141                         if (IS_GEN2(dev))
10142                                 return false;
10143                 case 64:
10144                         break;
10145                 default:
10146                         return false;
10147                 }
10148         }
10149
10150         return true;
10151 }
10152
10153 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10154                                  u16 *blue, uint32_t start, uint32_t size)
10155 {
10156         int end = (start + size > 256) ? 256 : start + size, i;
10157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10158
10159         for (i = start; i < end; i++) {
10160                 intel_crtc->lut_r[i] = red[i] >> 8;
10161                 intel_crtc->lut_g[i] = green[i] >> 8;
10162                 intel_crtc->lut_b[i] = blue[i] >> 8;
10163         }
10164
10165         intel_crtc_load_lut(crtc);
10166 }
10167
10168 /* VESA 640x480x72Hz mode to set on the pipe */
10169 static struct drm_display_mode load_detect_mode = {
10170         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10171                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10172 };
10173
10174 struct drm_framebuffer *
10175 __intel_framebuffer_create(struct drm_device *dev,
10176                            struct drm_mode_fb_cmd2 *mode_cmd,
10177                            struct drm_i915_gem_object *obj)
10178 {
10179         struct intel_framebuffer *intel_fb;
10180         int ret;
10181
10182         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10183         if (!intel_fb)
10184                 return ERR_PTR(-ENOMEM);
10185
10186         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10187         if (ret)
10188                 goto err;
10189
10190         return &intel_fb->base;
10191
10192 err:
10193         kfree(intel_fb);
10194         return ERR_PTR(ret);
10195 }
10196
10197 static struct drm_framebuffer *
10198 intel_framebuffer_create(struct drm_device *dev,
10199                          struct drm_mode_fb_cmd2 *mode_cmd,
10200                          struct drm_i915_gem_object *obj)
10201 {
10202         struct drm_framebuffer *fb;
10203         int ret;
10204
10205         ret = i915_mutex_lock_interruptible(dev);
10206         if (ret)
10207                 return ERR_PTR(ret);
10208         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10209         mutex_unlock(&dev->struct_mutex);
10210
10211         return fb;
10212 }
10213
10214 static u32
10215 intel_framebuffer_pitch_for_width(int width, int bpp)
10216 {
10217         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10218         return ALIGN(pitch, 64);
10219 }
10220
10221 static u32
10222 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10223 {
10224         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10225         return PAGE_ALIGN(pitch * mode->vdisplay);
10226 }
10227
10228 static struct drm_framebuffer *
10229 intel_framebuffer_create_for_mode(struct drm_device *dev,
10230                                   struct drm_display_mode *mode,
10231                                   int depth, int bpp)
10232 {
10233         struct drm_framebuffer *fb;
10234         struct drm_i915_gem_object *obj;
10235         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10236
10237         obj = i915_gem_alloc_object(dev,
10238                                     intel_framebuffer_size_for_mode(mode, bpp));
10239         if (obj == NULL)
10240                 return ERR_PTR(-ENOMEM);
10241
10242         mode_cmd.width = mode->hdisplay;
10243         mode_cmd.height = mode->vdisplay;
10244         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10245                                                                 bpp);
10246         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10247
10248         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10249         if (IS_ERR(fb))
10250                 drm_gem_object_unreference_unlocked(&obj->base);
10251
10252         return fb;
10253 }
10254
10255 static struct drm_framebuffer *
10256 mode_fits_in_fbdev(struct drm_device *dev,
10257                    struct drm_display_mode *mode)
10258 {
10259 #ifdef CONFIG_DRM_FBDEV_EMULATION
10260         struct drm_i915_private *dev_priv = dev->dev_private;
10261         struct drm_i915_gem_object *obj;
10262         struct drm_framebuffer *fb;
10263
10264         if (!dev_priv->fbdev)
10265                 return NULL;
10266
10267         if (!dev_priv->fbdev->fb)
10268                 return NULL;
10269
10270         obj = dev_priv->fbdev->fb->obj;
10271         BUG_ON(!obj);
10272
10273         fb = &dev_priv->fbdev->fb->base;
10274         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10275                                                                fb->bits_per_pixel))
10276                 return NULL;
10277
10278         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10279                 return NULL;
10280
10281         return fb;
10282 #else
10283         return NULL;
10284 #endif
10285 }
10286
10287 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10288                                            struct drm_crtc *crtc,
10289                                            struct drm_display_mode *mode,
10290                                            struct drm_framebuffer *fb,
10291                                            int x, int y)
10292 {
10293         struct drm_plane_state *plane_state;
10294         int hdisplay, vdisplay;
10295         int ret;
10296
10297         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10298         if (IS_ERR(plane_state))
10299                 return PTR_ERR(plane_state);
10300
10301         if (mode)
10302                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10303         else
10304                 hdisplay = vdisplay = 0;
10305
10306         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10307         if (ret)
10308                 return ret;
10309         drm_atomic_set_fb_for_plane(plane_state, fb);
10310         plane_state->crtc_x = 0;
10311         plane_state->crtc_y = 0;
10312         plane_state->crtc_w = hdisplay;
10313         plane_state->crtc_h = vdisplay;
10314         plane_state->src_x = x << 16;
10315         plane_state->src_y = y << 16;
10316         plane_state->src_w = hdisplay << 16;
10317         plane_state->src_h = vdisplay << 16;
10318
10319         return 0;
10320 }
10321
10322 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10323                                 struct drm_display_mode *mode,
10324                                 struct intel_load_detect_pipe *old,
10325                                 struct drm_modeset_acquire_ctx *ctx)
10326 {
10327         struct intel_crtc *intel_crtc;
10328         struct intel_encoder *intel_encoder =
10329                 intel_attached_encoder(connector);
10330         struct drm_crtc *possible_crtc;
10331         struct drm_encoder *encoder = &intel_encoder->base;
10332         struct drm_crtc *crtc = NULL;
10333         struct drm_device *dev = encoder->dev;
10334         struct drm_framebuffer *fb;
10335         struct drm_mode_config *config = &dev->mode_config;
10336         struct drm_atomic_state *state = NULL;
10337         struct drm_connector_state *connector_state;
10338         struct intel_crtc_state *crtc_state;
10339         int ret, i = -1;
10340
10341         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10342                       connector->base.id, connector->name,
10343                       encoder->base.id, encoder->name);
10344
10345 retry:
10346         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10347         if (ret)
10348                 goto fail;
10349
10350         /*
10351          * Algorithm gets a little messy:
10352          *
10353          *   - if the connector already has an assigned crtc, use it (but make
10354          *     sure it's on first)
10355          *
10356          *   - try to find the first unused crtc that can drive this connector,
10357          *     and use that if we find one
10358          */
10359
10360         /* See if we already have a CRTC for this connector */
10361         if (encoder->crtc) {
10362                 crtc = encoder->crtc;
10363
10364                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10365                 if (ret)
10366                         goto fail;
10367                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10368                 if (ret)
10369                         goto fail;
10370
10371                 old->dpms_mode = connector->dpms;
10372                 old->load_detect_temp = false;
10373
10374                 /* Make sure the crtc and connector are running */
10375                 if (connector->dpms != DRM_MODE_DPMS_ON)
10376                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10377
10378                 return true;
10379         }
10380
10381         /* Find an unused one (if possible) */
10382         for_each_crtc(dev, possible_crtc) {
10383                 i++;
10384                 if (!(encoder->possible_crtcs & (1 << i)))
10385                         continue;
10386                 if (possible_crtc->state->enable)
10387                         continue;
10388
10389                 crtc = possible_crtc;
10390                 break;
10391         }
10392
10393         /*
10394          * If we didn't find an unused CRTC, don't use any.
10395          */
10396         if (!crtc) {
10397                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10398                 goto fail;
10399         }
10400
10401         ret = drm_modeset_lock(&crtc->mutex, ctx);
10402         if (ret)
10403                 goto fail;
10404         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10405         if (ret)
10406                 goto fail;
10407
10408         intel_crtc = to_intel_crtc(crtc);
10409         old->dpms_mode = connector->dpms;
10410         old->load_detect_temp = true;
10411         old->release_fb = NULL;
10412
10413         state = drm_atomic_state_alloc(dev);
10414         if (!state)
10415                 return false;
10416
10417         state->acquire_ctx = ctx;
10418
10419         connector_state = drm_atomic_get_connector_state(state, connector);
10420         if (IS_ERR(connector_state)) {
10421                 ret = PTR_ERR(connector_state);
10422                 goto fail;
10423         }
10424
10425         connector_state->crtc = crtc;
10426         connector_state->best_encoder = &intel_encoder->base;
10427
10428         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10429         if (IS_ERR(crtc_state)) {
10430                 ret = PTR_ERR(crtc_state);
10431                 goto fail;
10432         }
10433
10434         crtc_state->base.active = crtc_state->base.enable = true;
10435
10436         if (!mode)
10437                 mode = &load_detect_mode;
10438
10439         /* We need a framebuffer large enough to accommodate all accesses
10440          * that the plane may generate whilst we perform load detection.
10441          * We can not rely on the fbcon either being present (we get called
10442          * during its initialisation to detect all boot displays, or it may
10443          * not even exist) or that it is large enough to satisfy the
10444          * requested mode.
10445          */
10446         fb = mode_fits_in_fbdev(dev, mode);
10447         if (fb == NULL) {
10448                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10449                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10450                 old->release_fb = fb;
10451         } else
10452                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10453         if (IS_ERR(fb)) {
10454                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10455                 goto fail;
10456         }
10457
10458         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10459         if (ret)
10460                 goto fail;
10461
10462         drm_mode_copy(&crtc_state->base.mode, mode);
10463
10464         if (drm_atomic_commit(state)) {
10465                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10466                 if (old->release_fb)
10467                         old->release_fb->funcs->destroy(old->release_fb);
10468                 goto fail;
10469         }
10470         crtc->primary->crtc = crtc;
10471
10472         /* let the connector get through one full cycle before testing */
10473         intel_wait_for_vblank(dev, intel_crtc->pipe);
10474         return true;
10475
10476 fail:
10477         drm_atomic_state_free(state);
10478         state = NULL;
10479
10480         if (ret == -EDEADLK) {
10481                 drm_modeset_backoff(ctx);
10482                 goto retry;
10483         }
10484
10485         return false;
10486 }
10487
10488 void intel_release_load_detect_pipe(struct drm_connector *connector,
10489                                     struct intel_load_detect_pipe *old,
10490                                     struct drm_modeset_acquire_ctx *ctx)
10491 {
10492         struct drm_device *dev = connector->dev;
10493         struct intel_encoder *intel_encoder =
10494                 intel_attached_encoder(connector);
10495         struct drm_encoder *encoder = &intel_encoder->base;
10496         struct drm_crtc *crtc = encoder->crtc;
10497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10498         struct drm_atomic_state *state;
10499         struct drm_connector_state *connector_state;
10500         struct intel_crtc_state *crtc_state;
10501         int ret;
10502
10503         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10504                       connector->base.id, connector->name,
10505                       encoder->base.id, encoder->name);
10506
10507         if (old->load_detect_temp) {
10508                 state = drm_atomic_state_alloc(dev);
10509                 if (!state)
10510                         goto fail;
10511
10512                 state->acquire_ctx = ctx;
10513
10514                 connector_state = drm_atomic_get_connector_state(state, connector);
10515                 if (IS_ERR(connector_state))
10516                         goto fail;
10517
10518                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10519                 if (IS_ERR(crtc_state))
10520                         goto fail;
10521
10522                 connector_state->best_encoder = NULL;
10523                 connector_state->crtc = NULL;
10524
10525                 crtc_state->base.enable = crtc_state->base.active = false;
10526
10527                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10528                                                       0, 0);
10529                 if (ret)
10530                         goto fail;
10531
10532                 ret = drm_atomic_commit(state);
10533                 if (ret)
10534                         goto fail;
10535
10536                 if (old->release_fb) {
10537                         drm_framebuffer_unregister_private(old->release_fb);
10538                         drm_framebuffer_unreference(old->release_fb);
10539                 }
10540
10541                 return;
10542         }
10543
10544         /* Switch crtc and encoder back off if necessary */
10545         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10546                 connector->funcs->dpms(connector, old->dpms_mode);
10547
10548         return;
10549 fail:
10550         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10551         drm_atomic_state_free(state);
10552 }
10553
10554 static int i9xx_pll_refclk(struct drm_device *dev,
10555                            const struct intel_crtc_state *pipe_config)
10556 {
10557         struct drm_i915_private *dev_priv = dev->dev_private;
10558         u32 dpll = pipe_config->dpll_hw_state.dpll;
10559
10560         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10561                 return dev_priv->vbt.lvds_ssc_freq;
10562         else if (HAS_PCH_SPLIT(dev))
10563                 return 120000;
10564         else if (!IS_GEN2(dev))
10565                 return 96000;
10566         else
10567                 return 48000;
10568 }
10569
10570 /* Returns the clock of the currently programmed mode of the given pipe. */
10571 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10572                                 struct intel_crtc_state *pipe_config)
10573 {
10574         struct drm_device *dev = crtc->base.dev;
10575         struct drm_i915_private *dev_priv = dev->dev_private;
10576         int pipe = pipe_config->cpu_transcoder;
10577         u32 dpll = pipe_config->dpll_hw_state.dpll;
10578         u32 fp;
10579         intel_clock_t clock;
10580         int port_clock;
10581         int refclk = i9xx_pll_refclk(dev, pipe_config);
10582
10583         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10584                 fp = pipe_config->dpll_hw_state.fp0;
10585         else
10586                 fp = pipe_config->dpll_hw_state.fp1;
10587
10588         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10589         if (IS_PINEVIEW(dev)) {
10590                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10591                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10592         } else {
10593                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10594                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10595         }
10596
10597         if (!IS_GEN2(dev)) {
10598                 if (IS_PINEVIEW(dev))
10599                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10600                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10601                 else
10602                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10603                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10604
10605                 switch (dpll & DPLL_MODE_MASK) {
10606                 case DPLLB_MODE_DAC_SERIAL:
10607                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10608                                 5 : 10;
10609                         break;
10610                 case DPLLB_MODE_LVDS:
10611                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10612                                 7 : 14;
10613                         break;
10614                 default:
10615                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10616                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10617                         return;
10618                 }
10619
10620                 if (IS_PINEVIEW(dev))
10621                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10622                 else
10623                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10624         } else {
10625                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10626                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10627
10628                 if (is_lvds) {
10629                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10630                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10631
10632                         if (lvds & LVDS_CLKB_POWER_UP)
10633                                 clock.p2 = 7;
10634                         else
10635                                 clock.p2 = 14;
10636                 } else {
10637                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10638                                 clock.p1 = 2;
10639                         else {
10640                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10641                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10642                         }
10643                         if (dpll & PLL_P2_DIVIDE_BY_4)
10644                                 clock.p2 = 4;
10645                         else
10646                                 clock.p2 = 2;
10647                 }
10648
10649                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10650         }
10651
10652         /*
10653          * This value includes pixel_multiplier. We will use
10654          * port_clock to compute adjusted_mode.crtc_clock in the
10655          * encoder's get_config() function.
10656          */
10657         pipe_config->port_clock = port_clock;
10658 }
10659
10660 int intel_dotclock_calculate(int link_freq,
10661                              const struct intel_link_m_n *m_n)
10662 {
10663         /*
10664          * The calculation for the data clock is:
10665          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10666          * But we want to avoid losing precison if possible, so:
10667          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10668          *
10669          * and the link clock is simpler:
10670          * link_clock = (m * link_clock) / n
10671          */
10672
10673         if (!m_n->link_n)
10674                 return 0;
10675
10676         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10677 }
10678
10679 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10680                                    struct intel_crtc_state *pipe_config)
10681 {
10682         struct drm_device *dev = crtc->base.dev;
10683
10684         /* read out port_clock from the DPLL */
10685         i9xx_crtc_clock_get(crtc, pipe_config);
10686
10687         /*
10688          * This value does not include pixel_multiplier.
10689          * We will check that port_clock and adjusted_mode.crtc_clock
10690          * agree once we know their relationship in the encoder's
10691          * get_config() function.
10692          */
10693         pipe_config->base.adjusted_mode.crtc_clock =
10694                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10695                                          &pipe_config->fdi_m_n);
10696 }
10697
10698 /** Returns the currently programmed mode of the given pipe. */
10699 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10700                                              struct drm_crtc *crtc)
10701 {
10702         struct drm_i915_private *dev_priv = dev->dev_private;
10703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10704         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10705         struct drm_display_mode *mode;
10706         struct intel_crtc_state pipe_config;
10707         int htot = I915_READ(HTOTAL(cpu_transcoder));
10708         int hsync = I915_READ(HSYNC(cpu_transcoder));
10709         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10710         int vsync = I915_READ(VSYNC(cpu_transcoder));
10711         enum pipe pipe = intel_crtc->pipe;
10712
10713         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10714         if (!mode)
10715                 return NULL;
10716
10717         /*
10718          * Construct a pipe_config sufficient for getting the clock info
10719          * back out of crtc_clock_get.
10720          *
10721          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10722          * to use a real value here instead.
10723          */
10724         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10725         pipe_config.pixel_multiplier = 1;
10726         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10727         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10728         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10729         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10730
10731         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10732         mode->hdisplay = (htot & 0xffff) + 1;
10733         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10734         mode->hsync_start = (hsync & 0xffff) + 1;
10735         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10736         mode->vdisplay = (vtot & 0xffff) + 1;
10737         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10738         mode->vsync_start = (vsync & 0xffff) + 1;
10739         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10740
10741         drm_mode_set_name(mode);
10742
10743         return mode;
10744 }
10745
10746 void intel_mark_busy(struct drm_device *dev)
10747 {
10748         struct drm_i915_private *dev_priv = dev->dev_private;
10749
10750         if (dev_priv->mm.busy)
10751                 return;
10752
10753         intel_runtime_pm_get(dev_priv);
10754         i915_update_gfx_val(dev_priv);
10755         if (INTEL_INFO(dev)->gen >= 6)
10756                 gen6_rps_busy(dev_priv);
10757         dev_priv->mm.busy = true;
10758 }
10759
10760 void intel_mark_idle(struct drm_device *dev)
10761 {
10762         struct drm_i915_private *dev_priv = dev->dev_private;
10763
10764         if (!dev_priv->mm.busy)
10765                 return;
10766
10767         dev_priv->mm.busy = false;
10768
10769         if (INTEL_INFO(dev)->gen >= 6)
10770                 gen6_rps_idle(dev->dev_private);
10771
10772         intel_runtime_pm_put(dev_priv);
10773 }
10774
10775 static void intel_crtc_destroy(struct drm_crtc *crtc)
10776 {
10777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10778         struct drm_device *dev = crtc->dev;
10779         struct intel_unpin_work *work;
10780
10781         spin_lock_irq(&dev->event_lock);
10782         work = intel_crtc->unpin_work;
10783         intel_crtc->unpin_work = NULL;
10784         spin_unlock_irq(&dev->event_lock);
10785
10786         if (work) {
10787                 cancel_work_sync(&work->work);
10788                 kfree(work);
10789         }
10790
10791         drm_crtc_cleanup(crtc);
10792
10793         kfree(intel_crtc);
10794 }
10795
10796 static void intel_unpin_work_fn(struct work_struct *__work)
10797 {
10798         struct intel_unpin_work *work =
10799                 container_of(__work, struct intel_unpin_work, work);
10800         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10801         struct drm_device *dev = crtc->base.dev;
10802         struct drm_plane *primary = crtc->base.primary;
10803
10804         mutex_lock(&dev->struct_mutex);
10805         intel_unpin_fb_obj(work->old_fb, primary->state);
10806         drm_gem_object_unreference(&work->pending_flip_obj->base);
10807
10808         if (work->flip_queued_req)
10809                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10810         mutex_unlock(&dev->struct_mutex);
10811
10812         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10813         drm_framebuffer_unreference(work->old_fb);
10814
10815         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10816         atomic_dec(&crtc->unpin_work_count);
10817
10818         kfree(work);
10819 }
10820
10821 static void do_intel_finish_page_flip(struct drm_device *dev,
10822                                       struct drm_crtc *crtc)
10823 {
10824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10825         struct intel_unpin_work *work;
10826         unsigned long flags;
10827
10828         /* Ignore early vblank irqs */
10829         if (intel_crtc == NULL)
10830                 return;
10831
10832         /*
10833          * This is called both by irq handlers and the reset code (to complete
10834          * lost pageflips) so needs the full irqsave spinlocks.
10835          */
10836         spin_lock_irqsave(&dev->event_lock, flags);
10837         work = intel_crtc->unpin_work;
10838
10839         /* Ensure we don't miss a work->pending update ... */
10840         smp_rmb();
10841
10842         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10843                 spin_unlock_irqrestore(&dev->event_lock, flags);
10844                 return;
10845         }
10846
10847         page_flip_completed(intel_crtc);
10848
10849         spin_unlock_irqrestore(&dev->event_lock, flags);
10850 }
10851
10852 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10853 {
10854         struct drm_i915_private *dev_priv = dev->dev_private;
10855         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10856
10857         do_intel_finish_page_flip(dev, crtc);
10858 }
10859
10860 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10861 {
10862         struct drm_i915_private *dev_priv = dev->dev_private;
10863         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10864
10865         do_intel_finish_page_flip(dev, crtc);
10866 }
10867
10868 /* Is 'a' after or equal to 'b'? */
10869 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10870 {
10871         return !((a - b) & 0x80000000);
10872 }
10873
10874 static bool page_flip_finished(struct intel_crtc *crtc)
10875 {
10876         struct drm_device *dev = crtc->base.dev;
10877         struct drm_i915_private *dev_priv = dev->dev_private;
10878
10879         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10880             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10881                 return true;
10882
10883         /*
10884          * The relevant registers doen't exist on pre-ctg.
10885          * As the flip done interrupt doesn't trigger for mmio
10886          * flips on gmch platforms, a flip count check isn't
10887          * really needed there. But since ctg has the registers,
10888          * include it in the check anyway.
10889          */
10890         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10891                 return true;
10892
10893         /*
10894          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10895          * used the same base address. In that case the mmio flip might
10896          * have completed, but the CS hasn't even executed the flip yet.
10897          *
10898          * A flip count check isn't enough as the CS might have updated
10899          * the base address just after start of vblank, but before we
10900          * managed to process the interrupt. This means we'd complete the
10901          * CS flip too soon.
10902          *
10903          * Combining both checks should get us a good enough result. It may
10904          * still happen that the CS flip has been executed, but has not
10905          * yet actually completed. But in case the base address is the same
10906          * anyway, we don't really care.
10907          */
10908         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10909                 crtc->unpin_work->gtt_offset &&
10910                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10911                                     crtc->unpin_work->flip_count);
10912 }
10913
10914 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10915 {
10916         struct drm_i915_private *dev_priv = dev->dev_private;
10917         struct intel_crtc *intel_crtc =
10918                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10919         unsigned long flags;
10920
10921
10922         /*
10923          * This is called both by irq handlers and the reset code (to complete
10924          * lost pageflips) so needs the full irqsave spinlocks.
10925          *
10926          * NB: An MMIO update of the plane base pointer will also
10927          * generate a page-flip completion irq, i.e. every modeset
10928          * is also accompanied by a spurious intel_prepare_page_flip().
10929          */
10930         spin_lock_irqsave(&dev->event_lock, flags);
10931         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10932                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10933         spin_unlock_irqrestore(&dev->event_lock, flags);
10934 }
10935
10936 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10937 {
10938         /* Ensure that the work item is consistent when activating it ... */
10939         smp_wmb();
10940         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10941         /* and that it is marked active as soon as the irq could fire. */
10942         smp_wmb();
10943 }
10944
10945 static int intel_gen2_queue_flip(struct drm_device *dev,
10946                                  struct drm_crtc *crtc,
10947                                  struct drm_framebuffer *fb,
10948                                  struct drm_i915_gem_object *obj,
10949                                  struct drm_i915_gem_request *req,
10950                                  uint32_t flags)
10951 {
10952         struct intel_engine_cs *ring = req->ring;
10953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10954         u32 flip_mask;
10955         int ret;
10956
10957         ret = intel_ring_begin(req, 6);
10958         if (ret)
10959                 return ret;
10960
10961         /* Can't queue multiple flips, so wait for the previous
10962          * one to finish before executing the next.
10963          */
10964         if (intel_crtc->plane)
10965                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10966         else
10967                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10968         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10969         intel_ring_emit(ring, MI_NOOP);
10970         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10971                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10972         intel_ring_emit(ring, fb->pitches[0]);
10973         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10974         intel_ring_emit(ring, 0); /* aux display base address, unused */
10975
10976         intel_mark_page_flip_active(intel_crtc->unpin_work);
10977         return 0;
10978 }
10979
10980 static int intel_gen3_queue_flip(struct drm_device *dev,
10981                                  struct drm_crtc *crtc,
10982                                  struct drm_framebuffer *fb,
10983                                  struct drm_i915_gem_object *obj,
10984                                  struct drm_i915_gem_request *req,
10985                                  uint32_t flags)
10986 {
10987         struct intel_engine_cs *ring = req->ring;
10988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10989         u32 flip_mask;
10990         int ret;
10991
10992         ret = intel_ring_begin(req, 6);
10993         if (ret)
10994                 return ret;
10995
10996         if (intel_crtc->plane)
10997                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10998         else
10999                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11000         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11001         intel_ring_emit(ring, MI_NOOP);
11002         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11003                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11004         intel_ring_emit(ring, fb->pitches[0]);
11005         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11006         intel_ring_emit(ring, MI_NOOP);
11007
11008         intel_mark_page_flip_active(intel_crtc->unpin_work);
11009         return 0;
11010 }
11011
11012 static int intel_gen4_queue_flip(struct drm_device *dev,
11013                                  struct drm_crtc *crtc,
11014                                  struct drm_framebuffer *fb,
11015                                  struct drm_i915_gem_object *obj,
11016                                  struct drm_i915_gem_request *req,
11017                                  uint32_t flags)
11018 {
11019         struct intel_engine_cs *ring = req->ring;
11020         struct drm_i915_private *dev_priv = dev->dev_private;
11021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11022         uint32_t pf, pipesrc;
11023         int ret;
11024
11025         ret = intel_ring_begin(req, 4);
11026         if (ret)
11027                 return ret;
11028
11029         /* i965+ uses the linear or tiled offsets from the
11030          * Display Registers (which do not change across a page-flip)
11031          * so we need only reprogram the base address.
11032          */
11033         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11034                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11035         intel_ring_emit(ring, fb->pitches[0]);
11036         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11037                         obj->tiling_mode);
11038
11039         /* XXX Enabling the panel-fitter across page-flip is so far
11040          * untested on non-native modes, so ignore it for now.
11041          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11042          */
11043         pf = 0;
11044         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11045         intel_ring_emit(ring, pf | pipesrc);
11046
11047         intel_mark_page_flip_active(intel_crtc->unpin_work);
11048         return 0;
11049 }
11050
11051 static int intel_gen6_queue_flip(struct drm_device *dev,
11052                                  struct drm_crtc *crtc,
11053                                  struct drm_framebuffer *fb,
11054                                  struct drm_i915_gem_object *obj,
11055                                  struct drm_i915_gem_request *req,
11056                                  uint32_t flags)
11057 {
11058         struct intel_engine_cs *ring = req->ring;
11059         struct drm_i915_private *dev_priv = dev->dev_private;
11060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11061         uint32_t pf, pipesrc;
11062         int ret;
11063
11064         ret = intel_ring_begin(req, 4);
11065         if (ret)
11066                 return ret;
11067
11068         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11069                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11070         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11071         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11072
11073         /* Contrary to the suggestions in the documentation,
11074          * "Enable Panel Fitter" does not seem to be required when page
11075          * flipping with a non-native mode, and worse causes a normal
11076          * modeset to fail.
11077          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11078          */
11079         pf = 0;
11080         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11081         intel_ring_emit(ring, pf | pipesrc);
11082
11083         intel_mark_page_flip_active(intel_crtc->unpin_work);
11084         return 0;
11085 }
11086
11087 static int intel_gen7_queue_flip(struct drm_device *dev,
11088                                  struct drm_crtc *crtc,
11089                                  struct drm_framebuffer *fb,
11090                                  struct drm_i915_gem_object *obj,
11091                                  struct drm_i915_gem_request *req,
11092                                  uint32_t flags)
11093 {
11094         struct intel_engine_cs *ring = req->ring;
11095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11096         uint32_t plane_bit = 0;
11097         int len, ret;
11098
11099         switch (intel_crtc->plane) {
11100         case PLANE_A:
11101                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11102                 break;
11103         case PLANE_B:
11104                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11105                 break;
11106         case PLANE_C:
11107                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11108                 break;
11109         default:
11110                 WARN_ONCE(1, "unknown plane in flip command\n");
11111                 return -ENODEV;
11112         }
11113
11114         len = 4;
11115         if (ring->id == RCS) {
11116                 len += 6;
11117                 /*
11118                  * On Gen 8, SRM is now taking an extra dword to accommodate
11119                  * 48bits addresses, and we need a NOOP for the batch size to
11120                  * stay even.
11121                  */
11122                 if (IS_GEN8(dev))
11123                         len += 2;
11124         }
11125
11126         /*
11127          * BSpec MI_DISPLAY_FLIP for IVB:
11128          * "The full packet must be contained within the same cache line."
11129          *
11130          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11131          * cacheline, if we ever start emitting more commands before
11132          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11133          * then do the cacheline alignment, and finally emit the
11134          * MI_DISPLAY_FLIP.
11135          */
11136         ret = intel_ring_cacheline_align(req);
11137         if (ret)
11138                 return ret;
11139
11140         ret = intel_ring_begin(req, len);
11141         if (ret)
11142                 return ret;
11143
11144         /* Unmask the flip-done completion message. Note that the bspec says that
11145          * we should do this for both the BCS and RCS, and that we must not unmask
11146          * more than one flip event at any time (or ensure that one flip message
11147          * can be sent by waiting for flip-done prior to queueing new flips).
11148          * Experimentation says that BCS works despite DERRMR masking all
11149          * flip-done completion events and that unmasking all planes at once
11150          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11151          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11152          */
11153         if (ring->id == RCS) {
11154                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11155                 intel_ring_emit_reg(ring, DERRMR);
11156                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11157                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11158                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11159                 if (IS_GEN8(dev))
11160                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11161                                               MI_SRM_LRM_GLOBAL_GTT);
11162                 else
11163                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11164                                               MI_SRM_LRM_GLOBAL_GTT);
11165                 intel_ring_emit_reg(ring, DERRMR);
11166                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11167                 if (IS_GEN8(dev)) {
11168                         intel_ring_emit(ring, 0);
11169                         intel_ring_emit(ring, MI_NOOP);
11170                 }
11171         }
11172
11173         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11174         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11175         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11176         intel_ring_emit(ring, (MI_NOOP));
11177
11178         intel_mark_page_flip_active(intel_crtc->unpin_work);
11179         return 0;
11180 }
11181
11182 static bool use_mmio_flip(struct intel_engine_cs *ring,
11183                           struct drm_i915_gem_object *obj)
11184 {
11185         /*
11186          * This is not being used for older platforms, because
11187          * non-availability of flip done interrupt forces us to use
11188          * CS flips. Older platforms derive flip done using some clever
11189          * tricks involving the flip_pending status bits and vblank irqs.
11190          * So using MMIO flips there would disrupt this mechanism.
11191          */
11192
11193         if (ring == NULL)
11194                 return true;
11195
11196         if (INTEL_INFO(ring->dev)->gen < 5)
11197                 return false;
11198
11199         if (i915.use_mmio_flip < 0)
11200                 return false;
11201         else if (i915.use_mmio_flip > 0)
11202                 return true;
11203         else if (i915.enable_execlists)
11204                 return true;
11205         else if (obj->base.dma_buf &&
11206                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11207                                                        false))
11208                 return true;
11209         else
11210                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11211 }
11212
11213 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11214                              unsigned int rotation,
11215                              struct intel_unpin_work *work)
11216 {
11217         struct drm_device *dev = intel_crtc->base.dev;
11218         struct drm_i915_private *dev_priv = dev->dev_private;
11219         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11220         const enum pipe pipe = intel_crtc->pipe;
11221         u32 ctl, stride, tile_height;
11222
11223         ctl = I915_READ(PLANE_CTL(pipe, 0));
11224         ctl &= ~PLANE_CTL_TILED_MASK;
11225         switch (fb->modifier[0]) {
11226         case DRM_FORMAT_MOD_NONE:
11227                 break;
11228         case I915_FORMAT_MOD_X_TILED:
11229                 ctl |= PLANE_CTL_TILED_X;
11230                 break;
11231         case I915_FORMAT_MOD_Y_TILED:
11232                 ctl |= PLANE_CTL_TILED_Y;
11233                 break;
11234         case I915_FORMAT_MOD_Yf_TILED:
11235                 ctl |= PLANE_CTL_TILED_YF;
11236                 break;
11237         default:
11238                 MISSING_CASE(fb->modifier[0]);
11239         }
11240
11241         /*
11242          * The stride is either expressed as a multiple of 64 bytes chunks for
11243          * linear buffers or in number of tiles for tiled buffers.
11244          */
11245         if (intel_rotation_90_or_270(rotation)) {
11246                 /* stride = Surface height in tiles */
11247                 tile_height = intel_tile_height(dev, fb->pixel_format,
11248                                                 fb->modifier[0], 0);
11249                 stride = DIV_ROUND_UP(fb->height, tile_height);
11250         } else {
11251                 stride = fb->pitches[0] /
11252                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11253                                                           fb->pixel_format);
11254         }
11255
11256         /*
11257          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11258          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11259          */
11260         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11261         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11262
11263         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11264         POSTING_READ(PLANE_SURF(pipe, 0));
11265 }
11266
11267 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11268                              struct intel_unpin_work *work)
11269 {
11270         struct drm_device *dev = intel_crtc->base.dev;
11271         struct drm_i915_private *dev_priv = dev->dev_private;
11272         struct intel_framebuffer *intel_fb =
11273                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11274         struct drm_i915_gem_object *obj = intel_fb->obj;
11275         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11276         u32 dspcntr;
11277
11278         dspcntr = I915_READ(reg);
11279
11280         if (obj->tiling_mode != I915_TILING_NONE)
11281                 dspcntr |= DISPPLANE_TILED;
11282         else
11283                 dspcntr &= ~DISPPLANE_TILED;
11284
11285         I915_WRITE(reg, dspcntr);
11286
11287         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11288         POSTING_READ(DSPSURF(intel_crtc->plane));
11289 }
11290
11291 /*
11292  * XXX: This is the temporary way to update the plane registers until we get
11293  * around to using the usual plane update functions for MMIO flips
11294  */
11295 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11296 {
11297         struct intel_crtc *crtc = mmio_flip->crtc;
11298         struct intel_unpin_work *work;
11299
11300         spin_lock_irq(&crtc->base.dev->event_lock);
11301         work = crtc->unpin_work;
11302         spin_unlock_irq(&crtc->base.dev->event_lock);
11303         if (work == NULL)
11304                 return;
11305
11306         intel_mark_page_flip_active(work);
11307
11308         intel_pipe_update_start(crtc);
11309
11310         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11311                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11312         else
11313                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11314                 ilk_do_mmio_flip(crtc, work);
11315
11316         intel_pipe_update_end(crtc);
11317 }
11318
11319 static void intel_mmio_flip_work_func(struct work_struct *work)
11320 {
11321         struct intel_mmio_flip *mmio_flip =
11322                 container_of(work, struct intel_mmio_flip, work);
11323         struct intel_framebuffer *intel_fb =
11324                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11325         struct drm_i915_gem_object *obj = intel_fb->obj;
11326
11327         if (mmio_flip->req) {
11328                 WARN_ON(__i915_wait_request(mmio_flip->req,
11329                                             mmio_flip->crtc->reset_counter,
11330                                             false, NULL,
11331                                             &mmio_flip->i915->rps.mmioflips));
11332                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11333         }
11334
11335         /* For framebuffer backed by dmabuf, wait for fence */
11336         if (obj->base.dma_buf)
11337                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11338                                                             false, false,
11339                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11340
11341         intel_do_mmio_flip(mmio_flip);
11342         kfree(mmio_flip);
11343 }
11344
11345 static int intel_queue_mmio_flip(struct drm_device *dev,
11346                                  struct drm_crtc *crtc,
11347                                  struct drm_i915_gem_object *obj)
11348 {
11349         struct intel_mmio_flip *mmio_flip;
11350
11351         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11352         if (mmio_flip == NULL)
11353                 return -ENOMEM;
11354
11355         mmio_flip->i915 = to_i915(dev);
11356         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11357         mmio_flip->crtc = to_intel_crtc(crtc);
11358         mmio_flip->rotation = crtc->primary->state->rotation;
11359
11360         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11361         schedule_work(&mmio_flip->work);
11362
11363         return 0;
11364 }
11365
11366 static int intel_default_queue_flip(struct drm_device *dev,
11367                                     struct drm_crtc *crtc,
11368                                     struct drm_framebuffer *fb,
11369                                     struct drm_i915_gem_object *obj,
11370                                     struct drm_i915_gem_request *req,
11371                                     uint32_t flags)
11372 {
11373         return -ENODEV;
11374 }
11375
11376 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11377                                          struct drm_crtc *crtc)
11378 {
11379         struct drm_i915_private *dev_priv = dev->dev_private;
11380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11381         struct intel_unpin_work *work = intel_crtc->unpin_work;
11382         u32 addr;
11383
11384         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11385                 return true;
11386
11387         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11388                 return false;
11389
11390         if (!work->enable_stall_check)
11391                 return false;
11392
11393         if (work->flip_ready_vblank == 0) {
11394                 if (work->flip_queued_req &&
11395                     !i915_gem_request_completed(work->flip_queued_req, true))
11396                         return false;
11397
11398                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11399         }
11400
11401         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11402                 return false;
11403
11404         /* Potential stall - if we see that the flip has happened,
11405          * assume a missed interrupt. */
11406         if (INTEL_INFO(dev)->gen >= 4)
11407                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11408         else
11409                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11410
11411         /* There is a potential issue here with a false positive after a flip
11412          * to the same address. We could address this by checking for a
11413          * non-incrementing frame counter.
11414          */
11415         return addr == work->gtt_offset;
11416 }
11417
11418 void intel_check_page_flip(struct drm_device *dev, int pipe)
11419 {
11420         struct drm_i915_private *dev_priv = dev->dev_private;
11421         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11423         struct intel_unpin_work *work;
11424
11425         WARN_ON(!in_interrupt());
11426
11427         if (crtc == NULL)
11428                 return;
11429
11430         spin_lock(&dev->event_lock);
11431         work = intel_crtc->unpin_work;
11432         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11433                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11434                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11435                 page_flip_completed(intel_crtc);
11436                 work = NULL;
11437         }
11438         if (work != NULL &&
11439             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11440                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11441         spin_unlock(&dev->event_lock);
11442 }
11443
11444 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11445                                 struct drm_framebuffer *fb,
11446                                 struct drm_pending_vblank_event *event,
11447                                 uint32_t page_flip_flags)
11448 {
11449         struct drm_device *dev = crtc->dev;
11450         struct drm_i915_private *dev_priv = dev->dev_private;
11451         struct drm_framebuffer *old_fb = crtc->primary->fb;
11452         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11454         struct drm_plane *primary = crtc->primary;
11455         enum pipe pipe = intel_crtc->pipe;
11456         struct intel_unpin_work *work;
11457         struct intel_engine_cs *ring;
11458         bool mmio_flip;
11459         struct drm_i915_gem_request *request = NULL;
11460         int ret;
11461
11462         /*
11463          * drm_mode_page_flip_ioctl() should already catch this, but double
11464          * check to be safe.  In the future we may enable pageflipping from
11465          * a disabled primary plane.
11466          */
11467         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11468                 return -EBUSY;
11469
11470         /* Can't change pixel format via MI display flips. */
11471         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11472                 return -EINVAL;
11473
11474         /*
11475          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11476          * Note that pitch changes could also affect these register.
11477          */
11478         if (INTEL_INFO(dev)->gen > 3 &&
11479             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11480              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11481                 return -EINVAL;
11482
11483         if (i915_terminally_wedged(&dev_priv->gpu_error))
11484                 goto out_hang;
11485
11486         work = kzalloc(sizeof(*work), GFP_KERNEL);
11487         if (work == NULL)
11488                 return -ENOMEM;
11489
11490         work->event = event;
11491         work->crtc = crtc;
11492         work->old_fb = old_fb;
11493         INIT_WORK(&work->work, intel_unpin_work_fn);
11494
11495         ret = drm_crtc_vblank_get(crtc);
11496         if (ret)
11497                 goto free_work;
11498
11499         /* We borrow the event spin lock for protecting unpin_work */
11500         spin_lock_irq(&dev->event_lock);
11501         if (intel_crtc->unpin_work) {
11502                 /* Before declaring the flip queue wedged, check if
11503                  * the hardware completed the operation behind our backs.
11504                  */
11505                 if (__intel_pageflip_stall_check(dev, crtc)) {
11506                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11507                         page_flip_completed(intel_crtc);
11508                 } else {
11509                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11510                         spin_unlock_irq(&dev->event_lock);
11511
11512                         drm_crtc_vblank_put(crtc);
11513                         kfree(work);
11514                         return -EBUSY;
11515                 }
11516         }
11517         intel_crtc->unpin_work = work;
11518         spin_unlock_irq(&dev->event_lock);
11519
11520         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11521                 flush_workqueue(dev_priv->wq);
11522
11523         /* Reference the objects for the scheduled work. */
11524         drm_framebuffer_reference(work->old_fb);
11525         drm_gem_object_reference(&obj->base);
11526
11527         crtc->primary->fb = fb;
11528         update_state_fb(crtc->primary);
11529
11530         work->pending_flip_obj = obj;
11531
11532         ret = i915_mutex_lock_interruptible(dev);
11533         if (ret)
11534                 goto cleanup;
11535
11536         atomic_inc(&intel_crtc->unpin_work_count);
11537         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11538
11539         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11540                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11541
11542         if (IS_VALLEYVIEW(dev)) {
11543                 ring = &dev_priv->ring[BCS];
11544                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11545                         /* vlv: DISPLAY_FLIP fails to change tiling */
11546                         ring = NULL;
11547         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11548                 ring = &dev_priv->ring[BCS];
11549         } else if (INTEL_INFO(dev)->gen >= 7) {
11550                 ring = i915_gem_request_get_ring(obj->last_write_req);
11551                 if (ring == NULL || ring->id != RCS)
11552                         ring = &dev_priv->ring[BCS];
11553         } else {
11554                 ring = &dev_priv->ring[RCS];
11555         }
11556
11557         mmio_flip = use_mmio_flip(ring, obj);
11558
11559         /* When using CS flips, we want to emit semaphores between rings.
11560          * However, when using mmio flips we will create a task to do the
11561          * synchronisation, so all we want here is to pin the framebuffer
11562          * into the display plane and skip any waits.
11563          */
11564         if (!mmio_flip) {
11565                 ret = i915_gem_object_sync(obj, ring, &request);
11566                 if (ret)
11567                         goto cleanup_pending;
11568         }
11569
11570         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11571                                          crtc->primary->state);
11572         if (ret)
11573                 goto cleanup_pending;
11574
11575         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11576                                                   obj, 0);
11577         work->gtt_offset += intel_crtc->dspaddr_offset;
11578
11579         if (mmio_flip) {
11580                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11581                 if (ret)
11582                         goto cleanup_unpin;
11583
11584                 i915_gem_request_assign(&work->flip_queued_req,
11585                                         obj->last_write_req);
11586         } else {
11587                 if (!request) {
11588                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11589                         if (ret)
11590                                 goto cleanup_unpin;
11591                 }
11592
11593                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11594                                                    page_flip_flags);
11595                 if (ret)
11596                         goto cleanup_unpin;
11597
11598                 i915_gem_request_assign(&work->flip_queued_req, request);
11599         }
11600
11601         if (request)
11602                 i915_add_request_no_flush(request);
11603
11604         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11605         work->enable_stall_check = true;
11606
11607         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11608                           to_intel_plane(primary)->frontbuffer_bit);
11609         mutex_unlock(&dev->struct_mutex);
11610
11611         intel_fbc_deactivate(intel_crtc);
11612         intel_frontbuffer_flip_prepare(dev,
11613                                        to_intel_plane(primary)->frontbuffer_bit);
11614
11615         trace_i915_flip_request(intel_crtc->plane, obj);
11616
11617         return 0;
11618
11619 cleanup_unpin:
11620         intel_unpin_fb_obj(fb, crtc->primary->state);
11621 cleanup_pending:
11622         if (request)
11623                 i915_gem_request_cancel(request);
11624         atomic_dec(&intel_crtc->unpin_work_count);
11625         mutex_unlock(&dev->struct_mutex);
11626 cleanup:
11627         crtc->primary->fb = old_fb;
11628         update_state_fb(crtc->primary);
11629
11630         drm_gem_object_unreference_unlocked(&obj->base);
11631         drm_framebuffer_unreference(work->old_fb);
11632
11633         spin_lock_irq(&dev->event_lock);
11634         intel_crtc->unpin_work = NULL;
11635         spin_unlock_irq(&dev->event_lock);
11636
11637         drm_crtc_vblank_put(crtc);
11638 free_work:
11639         kfree(work);
11640
11641         if (ret == -EIO) {
11642                 struct drm_atomic_state *state;
11643                 struct drm_plane_state *plane_state;
11644
11645 out_hang:
11646                 state = drm_atomic_state_alloc(dev);
11647                 if (!state)
11648                         return -ENOMEM;
11649                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11650
11651 retry:
11652                 plane_state = drm_atomic_get_plane_state(state, primary);
11653                 ret = PTR_ERR_OR_ZERO(plane_state);
11654                 if (!ret) {
11655                         drm_atomic_set_fb_for_plane(plane_state, fb);
11656
11657                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11658                         if (!ret)
11659                                 ret = drm_atomic_commit(state);
11660                 }
11661
11662                 if (ret == -EDEADLK) {
11663                         drm_modeset_backoff(state->acquire_ctx);
11664                         drm_atomic_state_clear(state);
11665                         goto retry;
11666                 }
11667
11668                 if (ret)
11669                         drm_atomic_state_free(state);
11670
11671                 if (ret == 0 && event) {
11672                         spin_lock_irq(&dev->event_lock);
11673                         drm_send_vblank_event(dev, pipe, event);
11674                         spin_unlock_irq(&dev->event_lock);
11675                 }
11676         }
11677         return ret;
11678 }
11679
11680
11681 /**
11682  * intel_wm_need_update - Check whether watermarks need updating
11683  * @plane: drm plane
11684  * @state: new plane state
11685  *
11686  * Check current plane state versus the new one to determine whether
11687  * watermarks need to be recalculated.
11688  *
11689  * Returns true or false.
11690  */
11691 static bool intel_wm_need_update(struct drm_plane *plane,
11692                                  struct drm_plane_state *state)
11693 {
11694         struct intel_plane_state *new = to_intel_plane_state(state);
11695         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11696
11697         /* Update watermarks on tiling or size changes. */
11698         if (!plane->state->fb || !state->fb ||
11699             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11700             plane->state->rotation != state->rotation ||
11701             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11702             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11703             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11704             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11705                 return true;
11706
11707         return false;
11708 }
11709
11710 static bool needs_scaling(struct intel_plane_state *state)
11711 {
11712         int src_w = drm_rect_width(&state->src) >> 16;
11713         int src_h = drm_rect_height(&state->src) >> 16;
11714         int dst_w = drm_rect_width(&state->dst);
11715         int dst_h = drm_rect_height(&state->dst);
11716
11717         return (src_w != dst_w || src_h != dst_h);
11718 }
11719
11720 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11721                                     struct drm_plane_state *plane_state)
11722 {
11723         struct drm_crtc *crtc = crtc_state->crtc;
11724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11725         struct drm_plane *plane = plane_state->plane;
11726         struct drm_device *dev = crtc->dev;
11727         struct drm_i915_private *dev_priv = dev->dev_private;
11728         struct intel_plane_state *old_plane_state =
11729                 to_intel_plane_state(plane->state);
11730         int idx = intel_crtc->base.base.id, ret;
11731         int i = drm_plane_index(plane);
11732         bool mode_changed = needs_modeset(crtc_state);
11733         bool was_crtc_enabled = crtc->state->active;
11734         bool is_crtc_enabled = crtc_state->active;
11735         bool turn_off, turn_on, visible, was_visible;
11736         struct drm_framebuffer *fb = plane_state->fb;
11737
11738         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11739             plane->type != DRM_PLANE_TYPE_CURSOR) {
11740                 ret = skl_update_scaler_plane(
11741                         to_intel_crtc_state(crtc_state),
11742                         to_intel_plane_state(plane_state));
11743                 if (ret)
11744                         return ret;
11745         }
11746
11747         was_visible = old_plane_state->visible;
11748         visible = to_intel_plane_state(plane_state)->visible;
11749
11750         if (!was_crtc_enabled && WARN_ON(was_visible))
11751                 was_visible = false;
11752
11753         if (!is_crtc_enabled && WARN_ON(visible))
11754                 visible = false;
11755
11756         if (!was_visible && !visible)
11757                 return 0;
11758
11759         turn_off = was_visible && (!visible || mode_changed);
11760         turn_on = visible && (!was_visible || mode_changed);
11761
11762         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11763                          plane->base.id, fb ? fb->base.id : -1);
11764
11765         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11766                          plane->base.id, was_visible, visible,
11767                          turn_off, turn_on, mode_changed);
11768
11769         if (turn_on) {
11770                 intel_crtc->atomic.update_wm_pre = true;
11771                 /* must disable cxsr around plane enable/disable */
11772                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11773                         intel_crtc->atomic.disable_cxsr = true;
11774                         /* to potentially re-enable cxsr */
11775                         intel_crtc->atomic.wait_vblank = true;
11776                         intel_crtc->atomic.update_wm_post = true;
11777                 }
11778         } else if (turn_off) {
11779                 intel_crtc->atomic.update_wm_post = true;
11780                 /* must disable cxsr around plane enable/disable */
11781                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11782                         if (is_crtc_enabled)
11783                                 intel_crtc->atomic.wait_vblank = true;
11784                         intel_crtc->atomic.disable_cxsr = true;
11785                 }
11786         } else if (intel_wm_need_update(plane, plane_state)) {
11787                 intel_crtc->atomic.update_wm_pre = true;
11788         }
11789
11790         if (visible || was_visible)
11791                 intel_crtc->atomic.fb_bits |=
11792                         to_intel_plane(plane)->frontbuffer_bit;
11793
11794         switch (plane->type) {
11795         case DRM_PLANE_TYPE_PRIMARY:
11796                 intel_crtc->atomic.pre_disable_primary = turn_off;
11797                 intel_crtc->atomic.post_enable_primary = turn_on;
11798
11799                 if (turn_off) {
11800                         /*
11801                          * FIXME: Actually if we will still have any other
11802                          * plane enabled on the pipe we could let IPS enabled
11803                          * still, but for now lets consider that when we make
11804                          * primary invisible by setting DSPCNTR to 0 on
11805                          * update_primary_plane function IPS needs to be
11806                          * disable.
11807                          */
11808                         intel_crtc->atomic.disable_ips = true;
11809
11810                         intel_crtc->atomic.disable_fbc = true;
11811                 }
11812
11813                 /*
11814                  * FBC does not work on some platforms for rotated
11815                  * planes, so disable it when rotation is not 0 and
11816                  * update it when rotation is set back to 0.
11817                  *
11818                  * FIXME: This is redundant with the fbc update done in
11819                  * the primary plane enable function except that that
11820                  * one is done too late. We eventually need to unify
11821                  * this.
11822                  */
11823
11824                 if (visible &&
11825                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11826                     dev_priv->fbc.crtc == intel_crtc &&
11827                     plane_state->rotation != BIT(DRM_ROTATE_0))
11828                         intel_crtc->atomic.disable_fbc = true;
11829
11830                 /*
11831                  * BDW signals flip done immediately if the plane
11832                  * is disabled, even if the plane enable is already
11833                  * armed to occur at the next vblank :(
11834                  */
11835                 if (turn_on && IS_BROADWELL(dev))
11836                         intel_crtc->atomic.wait_vblank = true;
11837
11838                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11839                 break;
11840         case DRM_PLANE_TYPE_CURSOR:
11841                 break;
11842         case DRM_PLANE_TYPE_OVERLAY:
11843                 /*
11844                  * WaCxSRDisabledForSpriteScaling:ivb
11845                  *
11846                  * cstate->update_wm was already set above, so this flag will
11847                  * take effect when we commit and program watermarks.
11848                  */
11849                 if (IS_IVYBRIDGE(dev) &&
11850                     needs_scaling(to_intel_plane_state(plane_state)) &&
11851                     !needs_scaling(old_plane_state)) {
11852                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11853                 } else if (turn_off && !mode_changed) {
11854                         intel_crtc->atomic.wait_vblank = true;
11855                         intel_crtc->atomic.update_sprite_watermarks |=
11856                                 1 << i;
11857                 }
11858
11859                 break;
11860         }
11861         return 0;
11862 }
11863
11864 static bool encoders_cloneable(const struct intel_encoder *a,
11865                                const struct intel_encoder *b)
11866 {
11867         /* masks could be asymmetric, so check both ways */
11868         return a == b || (a->cloneable & (1 << b->type) &&
11869                           b->cloneable & (1 << a->type));
11870 }
11871
11872 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11873                                          struct intel_crtc *crtc,
11874                                          struct intel_encoder *encoder)
11875 {
11876         struct intel_encoder *source_encoder;
11877         struct drm_connector *connector;
11878         struct drm_connector_state *connector_state;
11879         int i;
11880
11881         for_each_connector_in_state(state, connector, connector_state, i) {
11882                 if (connector_state->crtc != &crtc->base)
11883                         continue;
11884
11885                 source_encoder =
11886                         to_intel_encoder(connector_state->best_encoder);
11887                 if (!encoders_cloneable(encoder, source_encoder))
11888                         return false;
11889         }
11890
11891         return true;
11892 }
11893
11894 static bool check_encoder_cloning(struct drm_atomic_state *state,
11895                                   struct intel_crtc *crtc)
11896 {
11897         struct intel_encoder *encoder;
11898         struct drm_connector *connector;
11899         struct drm_connector_state *connector_state;
11900         int i;
11901
11902         for_each_connector_in_state(state, connector, connector_state, i) {
11903                 if (connector_state->crtc != &crtc->base)
11904                         continue;
11905
11906                 encoder = to_intel_encoder(connector_state->best_encoder);
11907                 if (!check_single_encoder_cloning(state, crtc, encoder))
11908                         return false;
11909         }
11910
11911         return true;
11912 }
11913
11914 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11915                                    struct drm_crtc_state *crtc_state)
11916 {
11917         struct drm_device *dev = crtc->dev;
11918         struct drm_i915_private *dev_priv = dev->dev_private;
11919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11920         struct intel_crtc_state *pipe_config =
11921                 to_intel_crtc_state(crtc_state);
11922         struct drm_atomic_state *state = crtc_state->state;
11923         int ret;
11924         bool mode_changed = needs_modeset(crtc_state);
11925
11926         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11927                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11928                 return -EINVAL;
11929         }
11930
11931         if (mode_changed && !crtc_state->active)
11932                 intel_crtc->atomic.update_wm_post = true;
11933
11934         if (mode_changed && crtc_state->enable &&
11935             dev_priv->display.crtc_compute_clock &&
11936             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11937                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11938                                                            pipe_config);
11939                 if (ret)
11940                         return ret;
11941         }
11942
11943         ret = 0;
11944         if (dev_priv->display.compute_pipe_wm) {
11945                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11946                 if (ret)
11947                         return ret;
11948         }
11949
11950         if (INTEL_INFO(dev)->gen >= 9) {
11951                 if (mode_changed)
11952                         ret = skl_update_scaler_crtc(pipe_config);
11953
11954                 if (!ret)
11955                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11956                                                          pipe_config);
11957         }
11958
11959         return ret;
11960 }
11961
11962 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11963         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11964         .load_lut = intel_crtc_load_lut,
11965         .atomic_begin = intel_begin_crtc_commit,
11966         .atomic_flush = intel_finish_crtc_commit,
11967         .atomic_check = intel_crtc_atomic_check,
11968 };
11969
11970 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11971 {
11972         struct intel_connector *connector;
11973
11974         for_each_intel_connector(dev, connector) {
11975                 if (connector->base.encoder) {
11976                         connector->base.state->best_encoder =
11977                                 connector->base.encoder;
11978                         connector->base.state->crtc =
11979                                 connector->base.encoder->crtc;
11980                 } else {
11981                         connector->base.state->best_encoder = NULL;
11982                         connector->base.state->crtc = NULL;
11983                 }
11984         }
11985 }
11986
11987 static void
11988 connected_sink_compute_bpp(struct intel_connector *connector,
11989                            struct intel_crtc_state *pipe_config)
11990 {
11991         int bpp = pipe_config->pipe_bpp;
11992
11993         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11994                 connector->base.base.id,
11995                 connector->base.name);
11996
11997         /* Don't use an invalid EDID bpc value */
11998         if (connector->base.display_info.bpc &&
11999             connector->base.display_info.bpc * 3 < bpp) {
12000                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12001                               bpp, connector->base.display_info.bpc*3);
12002                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12003         }
12004
12005         /* Clamp bpp to 8 on screens without EDID 1.4 */
12006         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12007                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12008                               bpp);
12009                 pipe_config->pipe_bpp = 24;
12010         }
12011 }
12012
12013 static int
12014 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12015                           struct intel_crtc_state *pipe_config)
12016 {
12017         struct drm_device *dev = crtc->base.dev;
12018         struct drm_atomic_state *state;
12019         struct drm_connector *connector;
12020         struct drm_connector_state *connector_state;
12021         int bpp, i;
12022
12023         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12024                 bpp = 10*3;
12025         else if (INTEL_INFO(dev)->gen >= 5)
12026                 bpp = 12*3;
12027         else
12028                 bpp = 8*3;
12029
12030
12031         pipe_config->pipe_bpp = bpp;
12032
12033         state = pipe_config->base.state;
12034
12035         /* Clamp display bpp to EDID value */
12036         for_each_connector_in_state(state, connector, connector_state, i) {
12037                 if (connector_state->crtc != &crtc->base)
12038                         continue;
12039
12040                 connected_sink_compute_bpp(to_intel_connector(connector),
12041                                            pipe_config);
12042         }
12043
12044         return bpp;
12045 }
12046
12047 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12048 {
12049         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12050                         "type: 0x%x flags: 0x%x\n",
12051                 mode->crtc_clock,
12052                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12053                 mode->crtc_hsync_end, mode->crtc_htotal,
12054                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12055                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12056 }
12057
12058 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12059                                    struct intel_crtc_state *pipe_config,
12060                                    const char *context)
12061 {
12062         struct drm_device *dev = crtc->base.dev;
12063         struct drm_plane *plane;
12064         struct intel_plane *intel_plane;
12065         struct intel_plane_state *state;
12066         struct drm_framebuffer *fb;
12067
12068         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12069                       context, pipe_config, pipe_name(crtc->pipe));
12070
12071         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12072         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12073                       pipe_config->pipe_bpp, pipe_config->dither);
12074         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12075                       pipe_config->has_pch_encoder,
12076                       pipe_config->fdi_lanes,
12077                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12078                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12079                       pipe_config->fdi_m_n.tu);
12080         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12081                       pipe_config->has_dp_encoder,
12082                       pipe_config->lane_count,
12083                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12084                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12085                       pipe_config->dp_m_n.tu);
12086
12087         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12088                       pipe_config->has_dp_encoder,
12089                       pipe_config->lane_count,
12090                       pipe_config->dp_m2_n2.gmch_m,
12091                       pipe_config->dp_m2_n2.gmch_n,
12092                       pipe_config->dp_m2_n2.link_m,
12093                       pipe_config->dp_m2_n2.link_n,
12094                       pipe_config->dp_m2_n2.tu);
12095
12096         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12097                       pipe_config->has_audio,
12098                       pipe_config->has_infoframe);
12099
12100         DRM_DEBUG_KMS("requested mode:\n");
12101         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12102         DRM_DEBUG_KMS("adjusted mode:\n");
12103         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12104         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12105         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12106         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12107                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12108         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12109                       crtc->num_scalers,
12110                       pipe_config->scaler_state.scaler_users,
12111                       pipe_config->scaler_state.scaler_id);
12112         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12113                       pipe_config->gmch_pfit.control,
12114                       pipe_config->gmch_pfit.pgm_ratios,
12115                       pipe_config->gmch_pfit.lvds_border_bits);
12116         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12117                       pipe_config->pch_pfit.pos,
12118                       pipe_config->pch_pfit.size,
12119                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12120         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12121         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12122
12123         if (IS_BROXTON(dev)) {
12124                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12125                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12126                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12127                               pipe_config->ddi_pll_sel,
12128                               pipe_config->dpll_hw_state.ebb0,
12129                               pipe_config->dpll_hw_state.ebb4,
12130                               pipe_config->dpll_hw_state.pll0,
12131                               pipe_config->dpll_hw_state.pll1,
12132                               pipe_config->dpll_hw_state.pll2,
12133                               pipe_config->dpll_hw_state.pll3,
12134                               pipe_config->dpll_hw_state.pll6,
12135                               pipe_config->dpll_hw_state.pll8,
12136                               pipe_config->dpll_hw_state.pll9,
12137                               pipe_config->dpll_hw_state.pll10,
12138                               pipe_config->dpll_hw_state.pcsdw12);
12139         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12140                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12141                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12142                               pipe_config->ddi_pll_sel,
12143                               pipe_config->dpll_hw_state.ctrl1,
12144                               pipe_config->dpll_hw_state.cfgcr1,
12145                               pipe_config->dpll_hw_state.cfgcr2);
12146         } else if (HAS_DDI(dev)) {
12147                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12148                               pipe_config->ddi_pll_sel,
12149                               pipe_config->dpll_hw_state.wrpll,
12150                               pipe_config->dpll_hw_state.spll);
12151         } else {
12152                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12153                               "fp0: 0x%x, fp1: 0x%x\n",
12154                               pipe_config->dpll_hw_state.dpll,
12155                               pipe_config->dpll_hw_state.dpll_md,
12156                               pipe_config->dpll_hw_state.fp0,
12157                               pipe_config->dpll_hw_state.fp1);
12158         }
12159
12160         DRM_DEBUG_KMS("planes on this crtc\n");
12161         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12162                 intel_plane = to_intel_plane(plane);
12163                 if (intel_plane->pipe != crtc->pipe)
12164                         continue;
12165
12166                 state = to_intel_plane_state(plane->state);
12167                 fb = state->base.fb;
12168                 if (!fb) {
12169                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12170                                 "disabled, scaler_id = %d\n",
12171                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12172                                 plane->base.id, intel_plane->pipe,
12173                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12174                                 drm_plane_index(plane), state->scaler_id);
12175                         continue;
12176                 }
12177
12178                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12179                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12180                         plane->base.id, intel_plane->pipe,
12181                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12182                         drm_plane_index(plane));
12183                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12184                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12185                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12186                         state->scaler_id,
12187                         state->src.x1 >> 16, state->src.y1 >> 16,
12188                         drm_rect_width(&state->src) >> 16,
12189                         drm_rect_height(&state->src) >> 16,
12190                         state->dst.x1, state->dst.y1,
12191                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12192         }
12193 }
12194
12195 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12196 {
12197         struct drm_device *dev = state->dev;
12198         struct intel_encoder *encoder;
12199         struct drm_connector *connector;
12200         struct drm_connector_state *connector_state;
12201         unsigned int used_ports = 0;
12202         int i;
12203
12204         /*
12205          * Walk the connector list instead of the encoder
12206          * list to detect the problem on ddi platforms
12207          * where there's just one encoder per digital port.
12208          */
12209         for_each_connector_in_state(state, connector, connector_state, i) {
12210                 if (!connector_state->best_encoder)
12211                         continue;
12212
12213                 encoder = to_intel_encoder(connector_state->best_encoder);
12214
12215                 WARN_ON(!connector_state->crtc);
12216
12217                 switch (encoder->type) {
12218                         unsigned int port_mask;
12219                 case INTEL_OUTPUT_UNKNOWN:
12220                         if (WARN_ON(!HAS_DDI(dev)))
12221                                 break;
12222                 case INTEL_OUTPUT_DISPLAYPORT:
12223                 case INTEL_OUTPUT_HDMI:
12224                 case INTEL_OUTPUT_EDP:
12225                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12226
12227                         /* the same port mustn't appear more than once */
12228                         if (used_ports & port_mask)
12229                                 return false;
12230
12231                         used_ports |= port_mask;
12232                 default:
12233                         break;
12234                 }
12235         }
12236
12237         return true;
12238 }
12239
12240 static void
12241 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12242 {
12243         struct drm_crtc_state tmp_state;
12244         struct intel_crtc_scaler_state scaler_state;
12245         struct intel_dpll_hw_state dpll_hw_state;
12246         enum intel_dpll_id shared_dpll;
12247         uint32_t ddi_pll_sel;
12248         bool force_thru;
12249
12250         /* FIXME: before the switch to atomic started, a new pipe_config was
12251          * kzalloc'd. Code that depends on any field being zero should be
12252          * fixed, so that the crtc_state can be safely duplicated. For now,
12253          * only fields that are know to not cause problems are preserved. */
12254
12255         tmp_state = crtc_state->base;
12256         scaler_state = crtc_state->scaler_state;
12257         shared_dpll = crtc_state->shared_dpll;
12258         dpll_hw_state = crtc_state->dpll_hw_state;
12259         ddi_pll_sel = crtc_state->ddi_pll_sel;
12260         force_thru = crtc_state->pch_pfit.force_thru;
12261
12262         memset(crtc_state, 0, sizeof *crtc_state);
12263
12264         crtc_state->base = tmp_state;
12265         crtc_state->scaler_state = scaler_state;
12266         crtc_state->shared_dpll = shared_dpll;
12267         crtc_state->dpll_hw_state = dpll_hw_state;
12268         crtc_state->ddi_pll_sel = ddi_pll_sel;
12269         crtc_state->pch_pfit.force_thru = force_thru;
12270 }
12271
12272 static int
12273 intel_modeset_pipe_config(struct drm_crtc *crtc,
12274                           struct intel_crtc_state *pipe_config)
12275 {
12276         struct drm_atomic_state *state = pipe_config->base.state;
12277         struct intel_encoder *encoder;
12278         struct drm_connector *connector;
12279         struct drm_connector_state *connector_state;
12280         int base_bpp, ret = -EINVAL;
12281         int i;
12282         bool retry = true;
12283
12284         clear_intel_crtc_state(pipe_config);
12285
12286         pipe_config->cpu_transcoder =
12287                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12288
12289         /*
12290          * Sanitize sync polarity flags based on requested ones. If neither
12291          * positive or negative polarity is requested, treat this as meaning
12292          * negative polarity.
12293          */
12294         if (!(pipe_config->base.adjusted_mode.flags &
12295               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12296                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12297
12298         if (!(pipe_config->base.adjusted_mode.flags &
12299               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12300                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12301
12302         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12303                                              pipe_config);
12304         if (base_bpp < 0)
12305                 goto fail;
12306
12307         /*
12308          * Determine the real pipe dimensions. Note that stereo modes can
12309          * increase the actual pipe size due to the frame doubling and
12310          * insertion of additional space for blanks between the frame. This
12311          * is stored in the crtc timings. We use the requested mode to do this
12312          * computation to clearly distinguish it from the adjusted mode, which
12313          * can be changed by the connectors in the below retry loop.
12314          */
12315         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12316                                &pipe_config->pipe_src_w,
12317                                &pipe_config->pipe_src_h);
12318
12319 encoder_retry:
12320         /* Ensure the port clock defaults are reset when retrying. */
12321         pipe_config->port_clock = 0;
12322         pipe_config->pixel_multiplier = 1;
12323
12324         /* Fill in default crtc timings, allow encoders to overwrite them. */
12325         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12326                               CRTC_STEREO_DOUBLE);
12327
12328         /* Pass our mode to the connectors and the CRTC to give them a chance to
12329          * adjust it according to limitations or connector properties, and also
12330          * a chance to reject the mode entirely.
12331          */
12332         for_each_connector_in_state(state, connector, connector_state, i) {
12333                 if (connector_state->crtc != crtc)
12334                         continue;
12335
12336                 encoder = to_intel_encoder(connector_state->best_encoder);
12337
12338                 if (!(encoder->compute_config(encoder, pipe_config))) {
12339                         DRM_DEBUG_KMS("Encoder config failure\n");
12340                         goto fail;
12341                 }
12342         }
12343
12344         /* Set default port clock if not overwritten by the encoder. Needs to be
12345          * done afterwards in case the encoder adjusts the mode. */
12346         if (!pipe_config->port_clock)
12347                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12348                         * pipe_config->pixel_multiplier;
12349
12350         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12351         if (ret < 0) {
12352                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12353                 goto fail;
12354         }
12355
12356         if (ret == RETRY) {
12357                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12358                         ret = -EINVAL;
12359                         goto fail;
12360                 }
12361
12362                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12363                 retry = false;
12364                 goto encoder_retry;
12365         }
12366
12367         /* Dithering seems to not pass-through bits correctly when it should, so
12368          * only enable it on 6bpc panels. */
12369         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12370         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12371                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12372
12373 fail:
12374         return ret;
12375 }
12376
12377 static void
12378 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12379 {
12380         struct drm_crtc *crtc;
12381         struct drm_crtc_state *crtc_state;
12382         int i;
12383
12384         /* Double check state. */
12385         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12386                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12387
12388                 /* Update hwmode for vblank functions */
12389                 if (crtc->state->active)
12390                         crtc->hwmode = crtc->state->adjusted_mode;
12391                 else
12392                         crtc->hwmode.crtc_clock = 0;
12393
12394                 /*
12395                  * Update legacy state to satisfy fbc code. This can
12396                  * be removed when fbc uses the atomic state.
12397                  */
12398                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12399                         struct drm_plane_state *plane_state = crtc->primary->state;
12400
12401                         crtc->primary->fb = plane_state->fb;
12402                         crtc->x = plane_state->src_x >> 16;
12403                         crtc->y = plane_state->src_y >> 16;
12404                 }
12405         }
12406 }
12407
12408 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12409 {
12410         int diff;
12411
12412         if (clock1 == clock2)
12413                 return true;
12414
12415         if (!clock1 || !clock2)
12416                 return false;
12417
12418         diff = abs(clock1 - clock2);
12419
12420         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12421                 return true;
12422
12423         return false;
12424 }
12425
12426 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12427         list_for_each_entry((intel_crtc), \
12428                             &(dev)->mode_config.crtc_list, \
12429                             base.head) \
12430                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12431
12432 static bool
12433 intel_compare_m_n(unsigned int m, unsigned int n,
12434                   unsigned int m2, unsigned int n2,
12435                   bool exact)
12436 {
12437         if (m == m2 && n == n2)
12438                 return true;
12439
12440         if (exact || !m || !n || !m2 || !n2)
12441                 return false;
12442
12443         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12444
12445         if (m > m2) {
12446                 while (m > m2) {
12447                         m2 <<= 1;
12448                         n2 <<= 1;
12449                 }
12450         } else if (m < m2) {
12451                 while (m < m2) {
12452                         m <<= 1;
12453                         n <<= 1;
12454                 }
12455         }
12456
12457         return m == m2 && n == n2;
12458 }
12459
12460 static bool
12461 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12462                        struct intel_link_m_n *m2_n2,
12463                        bool adjust)
12464 {
12465         if (m_n->tu == m2_n2->tu &&
12466             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12467                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12468             intel_compare_m_n(m_n->link_m, m_n->link_n,
12469                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12470                 if (adjust)
12471                         *m2_n2 = *m_n;
12472
12473                 return true;
12474         }
12475
12476         return false;
12477 }
12478
12479 static bool
12480 intel_pipe_config_compare(struct drm_device *dev,
12481                           struct intel_crtc_state *current_config,
12482                           struct intel_crtc_state *pipe_config,
12483                           bool adjust)
12484 {
12485         bool ret = true;
12486
12487 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12488         do { \
12489                 if (!adjust) \
12490                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12491                 else \
12492                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12493         } while (0)
12494
12495 #define PIPE_CONF_CHECK_X(name) \
12496         if (current_config->name != pipe_config->name) { \
12497                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12498                           "(expected 0x%08x, found 0x%08x)\n", \
12499                           current_config->name, \
12500                           pipe_config->name); \
12501                 ret = false; \
12502         }
12503
12504 #define PIPE_CONF_CHECK_I(name) \
12505         if (current_config->name != pipe_config->name) { \
12506                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12507                           "(expected %i, found %i)\n", \
12508                           current_config->name, \
12509                           pipe_config->name); \
12510                 ret = false; \
12511         }
12512
12513 #define PIPE_CONF_CHECK_M_N(name) \
12514         if (!intel_compare_link_m_n(&current_config->name, \
12515                                     &pipe_config->name,\
12516                                     adjust)) { \
12517                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12518                           "(expected tu %i gmch %i/%i link %i/%i, " \
12519                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12520                           current_config->name.tu, \
12521                           current_config->name.gmch_m, \
12522                           current_config->name.gmch_n, \
12523                           current_config->name.link_m, \
12524                           current_config->name.link_n, \
12525                           pipe_config->name.tu, \
12526                           pipe_config->name.gmch_m, \
12527                           pipe_config->name.gmch_n, \
12528                           pipe_config->name.link_m, \
12529                           pipe_config->name.link_n); \
12530                 ret = false; \
12531         }
12532
12533 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12534         if (!intel_compare_link_m_n(&current_config->name, \
12535                                     &pipe_config->name, adjust) && \
12536             !intel_compare_link_m_n(&current_config->alt_name, \
12537                                     &pipe_config->name, adjust)) { \
12538                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12539                           "(expected tu %i gmch %i/%i link %i/%i, " \
12540                           "or tu %i gmch %i/%i link %i/%i, " \
12541                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12542                           current_config->name.tu, \
12543                           current_config->name.gmch_m, \
12544                           current_config->name.gmch_n, \
12545                           current_config->name.link_m, \
12546                           current_config->name.link_n, \
12547                           current_config->alt_name.tu, \
12548                           current_config->alt_name.gmch_m, \
12549                           current_config->alt_name.gmch_n, \
12550                           current_config->alt_name.link_m, \
12551                           current_config->alt_name.link_n, \
12552                           pipe_config->name.tu, \
12553                           pipe_config->name.gmch_m, \
12554                           pipe_config->name.gmch_n, \
12555                           pipe_config->name.link_m, \
12556                           pipe_config->name.link_n); \
12557                 ret = false; \
12558         }
12559
12560 /* This is required for BDW+ where there is only one set of registers for
12561  * switching between high and low RR.
12562  * This macro can be used whenever a comparison has to be made between one
12563  * hw state and multiple sw state variables.
12564  */
12565 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12566         if ((current_config->name != pipe_config->name) && \
12567                 (current_config->alt_name != pipe_config->name)) { \
12568                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12569                                   "(expected %i or %i, found %i)\n", \
12570                                   current_config->name, \
12571                                   current_config->alt_name, \
12572                                   pipe_config->name); \
12573                         ret = false; \
12574         }
12575
12576 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12577         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12578                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12579                           "(expected %i, found %i)\n", \
12580                           current_config->name & (mask), \
12581                           pipe_config->name & (mask)); \
12582                 ret = false; \
12583         }
12584
12585 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12586         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12587                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12588                           "(expected %i, found %i)\n", \
12589                           current_config->name, \
12590                           pipe_config->name); \
12591                 ret = false; \
12592         }
12593
12594 #define PIPE_CONF_QUIRK(quirk)  \
12595         ((current_config->quirks | pipe_config->quirks) & (quirk))
12596
12597         PIPE_CONF_CHECK_I(cpu_transcoder);
12598
12599         PIPE_CONF_CHECK_I(has_pch_encoder);
12600         PIPE_CONF_CHECK_I(fdi_lanes);
12601         PIPE_CONF_CHECK_M_N(fdi_m_n);
12602
12603         PIPE_CONF_CHECK_I(has_dp_encoder);
12604         PIPE_CONF_CHECK_I(lane_count);
12605
12606         if (INTEL_INFO(dev)->gen < 8) {
12607                 PIPE_CONF_CHECK_M_N(dp_m_n);
12608
12609                 if (current_config->has_drrs)
12610                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12611         } else
12612                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12613
12614         PIPE_CONF_CHECK_I(has_dsi_encoder);
12615
12616         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12617         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12618         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12619         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12620         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12621         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12622
12623         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12624         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12625         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12626         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12627         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12628         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12629
12630         PIPE_CONF_CHECK_I(pixel_multiplier);
12631         PIPE_CONF_CHECK_I(has_hdmi_sink);
12632         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12633             IS_VALLEYVIEW(dev))
12634                 PIPE_CONF_CHECK_I(limited_color_range);
12635         PIPE_CONF_CHECK_I(has_infoframe);
12636
12637         PIPE_CONF_CHECK_I(has_audio);
12638
12639         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12640                               DRM_MODE_FLAG_INTERLACE);
12641
12642         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12643                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12644                                       DRM_MODE_FLAG_PHSYNC);
12645                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12646                                       DRM_MODE_FLAG_NHSYNC);
12647                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12648                                       DRM_MODE_FLAG_PVSYNC);
12649                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12650                                       DRM_MODE_FLAG_NVSYNC);
12651         }
12652
12653         PIPE_CONF_CHECK_X(gmch_pfit.control);
12654         /* pfit ratios are autocomputed by the hw on gen4+ */
12655         if (INTEL_INFO(dev)->gen < 4)
12656                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12657         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12658
12659         if (!adjust) {
12660                 PIPE_CONF_CHECK_I(pipe_src_w);
12661                 PIPE_CONF_CHECK_I(pipe_src_h);
12662
12663                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12664                 if (current_config->pch_pfit.enabled) {
12665                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12666                         PIPE_CONF_CHECK_X(pch_pfit.size);
12667                 }
12668
12669                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12670         }
12671
12672         /* BDW+ don't expose a synchronous way to read the state */
12673         if (IS_HASWELL(dev))
12674                 PIPE_CONF_CHECK_I(ips_enabled);
12675
12676         PIPE_CONF_CHECK_I(double_wide);
12677
12678         PIPE_CONF_CHECK_X(ddi_pll_sel);
12679
12680         PIPE_CONF_CHECK_I(shared_dpll);
12681         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12682         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12683         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12684         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12685         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12686         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12687         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12688         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12689         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12690
12691         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12692                 PIPE_CONF_CHECK_I(pipe_bpp);
12693
12694         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12695         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12696
12697 #undef PIPE_CONF_CHECK_X
12698 #undef PIPE_CONF_CHECK_I
12699 #undef PIPE_CONF_CHECK_I_ALT
12700 #undef PIPE_CONF_CHECK_FLAGS
12701 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12702 #undef PIPE_CONF_QUIRK
12703 #undef INTEL_ERR_OR_DBG_KMS
12704
12705         return ret;
12706 }
12707
12708 static void check_wm_state(struct drm_device *dev)
12709 {
12710         struct drm_i915_private *dev_priv = dev->dev_private;
12711         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12712         struct intel_crtc *intel_crtc;
12713         int plane;
12714
12715         if (INTEL_INFO(dev)->gen < 9)
12716                 return;
12717
12718         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12719         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12720
12721         for_each_intel_crtc(dev, intel_crtc) {
12722                 struct skl_ddb_entry *hw_entry, *sw_entry;
12723                 const enum pipe pipe = intel_crtc->pipe;
12724
12725                 if (!intel_crtc->active)
12726                         continue;
12727
12728                 /* planes */
12729                 for_each_plane(dev_priv, pipe, plane) {
12730                         hw_entry = &hw_ddb.plane[pipe][plane];
12731                         sw_entry = &sw_ddb->plane[pipe][plane];
12732
12733                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12734                                 continue;
12735
12736                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12737                                   "(expected (%u,%u), found (%u,%u))\n",
12738                                   pipe_name(pipe), plane + 1,
12739                                   sw_entry->start, sw_entry->end,
12740                                   hw_entry->start, hw_entry->end);
12741                 }
12742
12743                 /* cursor */
12744                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12745                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12746
12747                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12748                         continue;
12749
12750                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12751                           "(expected (%u,%u), found (%u,%u))\n",
12752                           pipe_name(pipe),
12753                           sw_entry->start, sw_entry->end,
12754                           hw_entry->start, hw_entry->end);
12755         }
12756 }
12757
12758 static void
12759 check_connector_state(struct drm_device *dev,
12760                       struct drm_atomic_state *old_state)
12761 {
12762         struct drm_connector_state *old_conn_state;
12763         struct drm_connector *connector;
12764         int i;
12765
12766         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12767                 struct drm_encoder *encoder = connector->encoder;
12768                 struct drm_connector_state *state = connector->state;
12769
12770                 /* This also checks the encoder/connector hw state with the
12771                  * ->get_hw_state callbacks. */
12772                 intel_connector_check_state(to_intel_connector(connector));
12773
12774                 I915_STATE_WARN(state->best_encoder != encoder,
12775                      "connector's atomic encoder doesn't match legacy encoder\n");
12776         }
12777 }
12778
12779 static void
12780 check_encoder_state(struct drm_device *dev)
12781 {
12782         struct intel_encoder *encoder;
12783         struct intel_connector *connector;
12784
12785         for_each_intel_encoder(dev, encoder) {
12786                 bool enabled = false;
12787                 enum pipe pipe;
12788
12789                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12790                               encoder->base.base.id,
12791                               encoder->base.name);
12792
12793                 for_each_intel_connector(dev, connector) {
12794                         if (connector->base.state->best_encoder != &encoder->base)
12795                                 continue;
12796                         enabled = true;
12797
12798                         I915_STATE_WARN(connector->base.state->crtc !=
12799                                         encoder->base.crtc,
12800                              "connector's crtc doesn't match encoder crtc\n");
12801                 }
12802
12803                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12804                      "encoder's enabled state mismatch "
12805                      "(expected %i, found %i)\n",
12806                      !!encoder->base.crtc, enabled);
12807
12808                 if (!encoder->base.crtc) {
12809                         bool active;
12810
12811                         active = encoder->get_hw_state(encoder, &pipe);
12812                         I915_STATE_WARN(active,
12813                              "encoder detached but still enabled on pipe %c.\n",
12814                              pipe_name(pipe));
12815                 }
12816         }
12817 }
12818
12819 static void
12820 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12821 {
12822         struct drm_i915_private *dev_priv = dev->dev_private;
12823         struct intel_encoder *encoder;
12824         struct drm_crtc_state *old_crtc_state;
12825         struct drm_crtc *crtc;
12826         int i;
12827
12828         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12829                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12830                 struct intel_crtc_state *pipe_config, *sw_config;
12831                 bool active;
12832
12833                 if (!needs_modeset(crtc->state) &&
12834                     !to_intel_crtc_state(crtc->state)->update_pipe)
12835                         continue;
12836
12837                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12838                 pipe_config = to_intel_crtc_state(old_crtc_state);
12839                 memset(pipe_config, 0, sizeof(*pipe_config));
12840                 pipe_config->base.crtc = crtc;
12841                 pipe_config->base.state = old_state;
12842
12843                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12844                               crtc->base.id);
12845
12846                 active = dev_priv->display.get_pipe_config(intel_crtc,
12847                                                            pipe_config);
12848
12849                 /* hw state is inconsistent with the pipe quirk */
12850                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12851                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12852                         active = crtc->state->active;
12853
12854                 I915_STATE_WARN(crtc->state->active != active,
12855                      "crtc active state doesn't match with hw state "
12856                      "(expected %i, found %i)\n", crtc->state->active, active);
12857
12858                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12859                      "transitional active state does not match atomic hw state "
12860                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12861
12862                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12863                         enum pipe pipe;
12864
12865                         active = encoder->get_hw_state(encoder, &pipe);
12866                         I915_STATE_WARN(active != crtc->state->active,
12867                                 "[ENCODER:%i] active %i with crtc active %i\n",
12868                                 encoder->base.base.id, active, crtc->state->active);
12869
12870                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12871                                         "Encoder connected to wrong pipe %c\n",
12872                                         pipe_name(pipe));
12873
12874                         if (active)
12875                                 encoder->get_config(encoder, pipe_config);
12876                 }
12877
12878                 if (!crtc->state->active)
12879                         continue;
12880
12881                 sw_config = to_intel_crtc_state(crtc->state);
12882                 if (!intel_pipe_config_compare(dev, sw_config,
12883                                                pipe_config, false)) {
12884                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12885                         intel_dump_pipe_config(intel_crtc, pipe_config,
12886                                                "[hw state]");
12887                         intel_dump_pipe_config(intel_crtc, sw_config,
12888                                                "[sw state]");
12889                 }
12890         }
12891 }
12892
12893 static void
12894 check_shared_dpll_state(struct drm_device *dev)
12895 {
12896         struct drm_i915_private *dev_priv = dev->dev_private;
12897         struct intel_crtc *crtc;
12898         struct intel_dpll_hw_state dpll_hw_state;
12899         int i;
12900
12901         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12902                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12903                 int enabled_crtcs = 0, active_crtcs = 0;
12904                 bool active;
12905
12906                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12907
12908                 DRM_DEBUG_KMS("%s\n", pll->name);
12909
12910                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12911
12912                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12913                      "more active pll users than references: %i vs %i\n",
12914                      pll->active, hweight32(pll->config.crtc_mask));
12915                 I915_STATE_WARN(pll->active && !pll->on,
12916                      "pll in active use but not on in sw tracking\n");
12917                 I915_STATE_WARN(pll->on && !pll->active,
12918                      "pll in on but not on in use in sw tracking\n");
12919                 I915_STATE_WARN(pll->on != active,
12920                      "pll on state mismatch (expected %i, found %i)\n",
12921                      pll->on, active);
12922
12923                 for_each_intel_crtc(dev, crtc) {
12924                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12925                                 enabled_crtcs++;
12926                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12927                                 active_crtcs++;
12928                 }
12929                 I915_STATE_WARN(pll->active != active_crtcs,
12930                      "pll active crtcs mismatch (expected %i, found %i)\n",
12931                      pll->active, active_crtcs);
12932                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12933                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12934                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12935
12936                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12937                                        sizeof(dpll_hw_state)),
12938                      "pll hw state mismatch\n");
12939         }
12940 }
12941
12942 static void
12943 intel_modeset_check_state(struct drm_device *dev,
12944                           struct drm_atomic_state *old_state)
12945 {
12946         check_wm_state(dev);
12947         check_connector_state(dev, old_state);
12948         check_encoder_state(dev);
12949         check_crtc_state(dev, old_state);
12950         check_shared_dpll_state(dev);
12951 }
12952
12953 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12954                                      int dotclock)
12955 {
12956         /*
12957          * FDI already provided one idea for the dotclock.
12958          * Yell if the encoder disagrees.
12959          */
12960         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12961              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12962              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12963 }
12964
12965 static void update_scanline_offset(struct intel_crtc *crtc)
12966 {
12967         struct drm_device *dev = crtc->base.dev;
12968
12969         /*
12970          * The scanline counter increments at the leading edge of hsync.
12971          *
12972          * On most platforms it starts counting from vtotal-1 on the
12973          * first active line. That means the scanline counter value is
12974          * always one less than what we would expect. Ie. just after
12975          * start of vblank, which also occurs at start of hsync (on the
12976          * last active line), the scanline counter will read vblank_start-1.
12977          *
12978          * On gen2 the scanline counter starts counting from 1 instead
12979          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12980          * to keep the value positive), instead of adding one.
12981          *
12982          * On HSW+ the behaviour of the scanline counter depends on the output
12983          * type. For DP ports it behaves like most other platforms, but on HDMI
12984          * there's an extra 1 line difference. So we need to add two instead of
12985          * one to the value.
12986          */
12987         if (IS_GEN2(dev)) {
12988                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12989                 int vtotal;
12990
12991                 vtotal = adjusted_mode->crtc_vtotal;
12992                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12993                         vtotal /= 2;
12994
12995                 crtc->scanline_offset = vtotal - 1;
12996         } else if (HAS_DDI(dev) &&
12997                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12998                 crtc->scanline_offset = 2;
12999         } else
13000                 crtc->scanline_offset = 1;
13001 }
13002
13003 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13004 {
13005         struct drm_device *dev = state->dev;
13006         struct drm_i915_private *dev_priv = to_i915(dev);
13007         struct intel_shared_dpll_config *shared_dpll = NULL;
13008         struct intel_crtc *intel_crtc;
13009         struct intel_crtc_state *intel_crtc_state;
13010         struct drm_crtc *crtc;
13011         struct drm_crtc_state *crtc_state;
13012         int i;
13013
13014         if (!dev_priv->display.crtc_compute_clock)
13015                 return;
13016
13017         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13018                 int dpll;
13019
13020                 intel_crtc = to_intel_crtc(crtc);
13021                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13022                 dpll = intel_crtc_state->shared_dpll;
13023
13024                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13025                         continue;
13026
13027                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13028
13029                 if (!shared_dpll)
13030                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13031
13032                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13033         }
13034 }
13035
13036 /*
13037  * This implements the workaround described in the "notes" section of the mode
13038  * set sequence documentation. When going from no pipes or single pipe to
13039  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13040  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13041  */
13042 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13043 {
13044         struct drm_crtc_state *crtc_state;
13045         struct intel_crtc *intel_crtc;
13046         struct drm_crtc *crtc;
13047         struct intel_crtc_state *first_crtc_state = NULL;
13048         struct intel_crtc_state *other_crtc_state = NULL;
13049         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13050         int i;
13051
13052         /* look at all crtc's that are going to be enabled in during modeset */
13053         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13054                 intel_crtc = to_intel_crtc(crtc);
13055
13056                 if (!crtc_state->active || !needs_modeset(crtc_state))
13057                         continue;
13058
13059                 if (first_crtc_state) {
13060                         other_crtc_state = to_intel_crtc_state(crtc_state);
13061                         break;
13062                 } else {
13063                         first_crtc_state = to_intel_crtc_state(crtc_state);
13064                         first_pipe = intel_crtc->pipe;
13065                 }
13066         }
13067
13068         /* No workaround needed? */
13069         if (!first_crtc_state)
13070                 return 0;
13071
13072         /* w/a possibly needed, check how many crtc's are already enabled. */
13073         for_each_intel_crtc(state->dev, intel_crtc) {
13074                 struct intel_crtc_state *pipe_config;
13075
13076                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13077                 if (IS_ERR(pipe_config))
13078                         return PTR_ERR(pipe_config);
13079
13080                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13081
13082                 if (!pipe_config->base.active ||
13083                     needs_modeset(&pipe_config->base))
13084                         continue;
13085
13086                 /* 2 or more enabled crtcs means no need for w/a */
13087                 if (enabled_pipe != INVALID_PIPE)
13088                         return 0;
13089
13090                 enabled_pipe = intel_crtc->pipe;
13091         }
13092
13093         if (enabled_pipe != INVALID_PIPE)
13094                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13095         else if (other_crtc_state)
13096                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13097
13098         return 0;
13099 }
13100
13101 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13102 {
13103         struct drm_crtc *crtc;
13104         struct drm_crtc_state *crtc_state;
13105         int ret = 0;
13106
13107         /* add all active pipes to the state */
13108         for_each_crtc(state->dev, crtc) {
13109                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13110                 if (IS_ERR(crtc_state))
13111                         return PTR_ERR(crtc_state);
13112
13113                 if (!crtc_state->active || needs_modeset(crtc_state))
13114                         continue;
13115
13116                 crtc_state->mode_changed = true;
13117
13118                 ret = drm_atomic_add_affected_connectors(state, crtc);
13119                 if (ret)
13120                         break;
13121
13122                 ret = drm_atomic_add_affected_planes(state, crtc);
13123                 if (ret)
13124                         break;
13125         }
13126
13127         return ret;
13128 }
13129
13130 static int intel_modeset_checks(struct drm_atomic_state *state)
13131 {
13132         struct drm_device *dev = state->dev;
13133         struct drm_i915_private *dev_priv = dev->dev_private;
13134         int ret;
13135
13136         if (!check_digital_port_conflicts(state)) {
13137                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13138                 return -EINVAL;
13139         }
13140
13141         /*
13142          * See if the config requires any additional preparation, e.g.
13143          * to adjust global state with pipes off.  We need to do this
13144          * here so we can get the modeset_pipe updated config for the new
13145          * mode set on this crtc.  For other crtcs we need to use the
13146          * adjusted_mode bits in the crtc directly.
13147          */
13148         if (dev_priv->display.modeset_calc_cdclk) {
13149                 unsigned int cdclk;
13150
13151                 ret = dev_priv->display.modeset_calc_cdclk(state);
13152
13153                 cdclk = to_intel_atomic_state(state)->cdclk;
13154                 if (!ret && cdclk != dev_priv->cdclk_freq)
13155                         ret = intel_modeset_all_pipes(state);
13156
13157                 if (ret < 0)
13158                         return ret;
13159         } else
13160                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13161
13162         intel_modeset_clear_plls(state);
13163
13164         if (IS_HASWELL(dev))
13165                 return haswell_mode_set_planes_workaround(state);
13166
13167         return 0;
13168 }
13169
13170 /*
13171  * Handle calculation of various watermark data at the end of the atomic check
13172  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13173  * handlers to ensure that all derived state has been updated.
13174  */
13175 static void calc_watermark_data(struct drm_atomic_state *state)
13176 {
13177         struct drm_device *dev = state->dev;
13178         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13179         struct drm_crtc *crtc;
13180         struct drm_crtc_state *cstate;
13181         struct drm_plane *plane;
13182         struct drm_plane_state *pstate;
13183
13184         /*
13185          * Calculate watermark configuration details now that derived
13186          * plane/crtc state is all properly updated.
13187          */
13188         drm_for_each_crtc(crtc, dev) {
13189                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13190                         crtc->state;
13191
13192                 if (cstate->active)
13193                         intel_state->wm_config.num_pipes_active++;
13194         }
13195         drm_for_each_legacy_plane(plane, dev) {
13196                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13197                         plane->state;
13198
13199                 if (!to_intel_plane_state(pstate)->visible)
13200                         continue;
13201
13202                 intel_state->wm_config.sprites_enabled = true;
13203                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13204                     pstate->crtc_h != pstate->src_h >> 16)
13205                         intel_state->wm_config.sprites_scaled = true;
13206         }
13207 }
13208
13209 /**
13210  * intel_atomic_check - validate state object
13211  * @dev: drm device
13212  * @state: state to validate
13213  */
13214 static int intel_atomic_check(struct drm_device *dev,
13215                               struct drm_atomic_state *state)
13216 {
13217         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13218         struct drm_crtc *crtc;
13219         struct drm_crtc_state *crtc_state;
13220         int ret, i;
13221         bool any_ms = false;
13222
13223         ret = drm_atomic_helper_check_modeset(dev, state);
13224         if (ret)
13225                 return ret;
13226
13227         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13228                 struct intel_crtc_state *pipe_config =
13229                         to_intel_crtc_state(crtc_state);
13230
13231                 memset(&to_intel_crtc(crtc)->atomic, 0,
13232                        sizeof(struct intel_crtc_atomic_commit));
13233
13234                 /* Catch I915_MODE_FLAG_INHERITED */
13235                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13236                         crtc_state->mode_changed = true;
13237
13238                 if (!crtc_state->enable) {
13239                         if (needs_modeset(crtc_state))
13240                                 any_ms = true;
13241                         continue;
13242                 }
13243
13244                 if (!needs_modeset(crtc_state))
13245                         continue;
13246
13247                 /* FIXME: For only active_changed we shouldn't need to do any
13248                  * state recomputation at all. */
13249
13250                 ret = drm_atomic_add_affected_connectors(state, crtc);
13251                 if (ret)
13252                         return ret;
13253
13254                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13255                 if (ret)
13256                         return ret;
13257
13258                 if (i915.fastboot &&
13259                     intel_pipe_config_compare(state->dev,
13260                                         to_intel_crtc_state(crtc->state),
13261                                         pipe_config, true)) {
13262                         crtc_state->mode_changed = false;
13263                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13264                 }
13265
13266                 if (needs_modeset(crtc_state)) {
13267                         any_ms = true;
13268
13269                         ret = drm_atomic_add_affected_planes(state, crtc);
13270                         if (ret)
13271                                 return ret;
13272                 }
13273
13274                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13275                                        needs_modeset(crtc_state) ?
13276                                        "[modeset]" : "[fastset]");
13277         }
13278
13279         if (any_ms) {
13280                 ret = intel_modeset_checks(state);
13281
13282                 if (ret)
13283                         return ret;
13284         } else
13285                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13286
13287         ret = drm_atomic_helper_check_planes(state->dev, state);
13288         if (ret)
13289                 return ret;
13290
13291         calc_watermark_data(state);
13292
13293         return 0;
13294 }
13295
13296 static int intel_atomic_prepare_commit(struct drm_device *dev,
13297                                        struct drm_atomic_state *state,
13298                                        bool async)
13299 {
13300         struct drm_i915_private *dev_priv = dev->dev_private;
13301         struct drm_plane_state *plane_state;
13302         struct drm_crtc_state *crtc_state;
13303         struct drm_plane *plane;
13304         struct drm_crtc *crtc;
13305         int i, ret;
13306
13307         if (async) {
13308                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13309                 return -EINVAL;
13310         }
13311
13312         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13313                 ret = intel_crtc_wait_for_pending_flips(crtc);
13314                 if (ret)
13315                         return ret;
13316
13317                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13318                         flush_workqueue(dev_priv->wq);
13319         }
13320
13321         ret = mutex_lock_interruptible(&dev->struct_mutex);
13322         if (ret)
13323                 return ret;
13324
13325         ret = drm_atomic_helper_prepare_planes(dev, state);
13326         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13327                 u32 reset_counter;
13328
13329                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13330                 mutex_unlock(&dev->struct_mutex);
13331
13332                 for_each_plane_in_state(state, plane, plane_state, i) {
13333                         struct intel_plane_state *intel_plane_state =
13334                                 to_intel_plane_state(plane_state);
13335
13336                         if (!intel_plane_state->wait_req)
13337                                 continue;
13338
13339                         ret = __i915_wait_request(intel_plane_state->wait_req,
13340                                                   reset_counter, true,
13341                                                   NULL, NULL);
13342
13343                         /* Swallow -EIO errors to allow updates during hw lockup. */
13344                         if (ret == -EIO)
13345                                 ret = 0;
13346
13347                         if (ret)
13348                                 break;
13349                 }
13350
13351                 if (!ret)
13352                         return 0;
13353
13354                 mutex_lock(&dev->struct_mutex);
13355                 drm_atomic_helper_cleanup_planes(dev, state);
13356         }
13357
13358         mutex_unlock(&dev->struct_mutex);
13359         return ret;
13360 }
13361
13362 /**
13363  * intel_atomic_commit - commit validated state object
13364  * @dev: DRM device
13365  * @state: the top-level driver state object
13366  * @async: asynchronous commit
13367  *
13368  * This function commits a top-level state object that has been validated
13369  * with drm_atomic_helper_check().
13370  *
13371  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13372  * we can only handle plane-related operations and do not yet support
13373  * asynchronous commit.
13374  *
13375  * RETURNS
13376  * Zero for success or -errno.
13377  */
13378 static int intel_atomic_commit(struct drm_device *dev,
13379                                struct drm_atomic_state *state,
13380                                bool async)
13381 {
13382         struct drm_i915_private *dev_priv = dev->dev_private;
13383         struct drm_crtc_state *crtc_state;
13384         struct drm_crtc *crtc;
13385         int ret = 0;
13386         int i;
13387         bool any_ms = false;
13388
13389         ret = intel_atomic_prepare_commit(dev, state, async);
13390         if (ret) {
13391                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13392                 return ret;
13393         }
13394
13395         drm_atomic_helper_swap_state(dev, state);
13396         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13397
13398         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13399                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13400
13401                 if (!needs_modeset(crtc->state))
13402                         continue;
13403
13404                 any_ms = true;
13405                 intel_pre_plane_update(intel_crtc);
13406
13407                 if (crtc_state->active) {
13408                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13409                         dev_priv->display.crtc_disable(crtc);
13410                         intel_crtc->active = false;
13411                         intel_disable_shared_dpll(intel_crtc);
13412
13413                         /*
13414                          * Underruns don't always raise
13415                          * interrupts, so check manually.
13416                          */
13417                         intel_check_cpu_fifo_underruns(dev_priv);
13418                         intel_check_pch_fifo_underruns(dev_priv);
13419                 }
13420         }
13421
13422         /* Only after disabling all output pipelines that will be changed can we
13423          * update the the output configuration. */
13424         intel_modeset_update_crtc_state(state);
13425
13426         if (any_ms) {
13427                 intel_shared_dpll_commit(state);
13428
13429                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13430                 modeset_update_crtc_power_domains(state);
13431         }
13432
13433         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13434         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13435                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13436                 bool modeset = needs_modeset(crtc->state);
13437                 bool update_pipe = !modeset &&
13438                         to_intel_crtc_state(crtc->state)->update_pipe;
13439                 unsigned long put_domains = 0;
13440
13441                 if (modeset)
13442                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13443
13444                 if (modeset && crtc->state->active) {
13445                         update_scanline_offset(to_intel_crtc(crtc));
13446                         dev_priv->display.crtc_enable(crtc);
13447                 }
13448
13449                 if (update_pipe) {
13450                         put_domains = modeset_get_crtc_power_domains(crtc);
13451
13452                         /* make sure intel_modeset_check_state runs */
13453                         any_ms = true;
13454                 }
13455
13456                 if (!modeset)
13457                         intel_pre_plane_update(intel_crtc);
13458
13459                 if (crtc->state->active &&
13460                     (crtc->state->planes_changed || update_pipe))
13461                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13462
13463                 if (put_domains)
13464                         modeset_put_power_domains(dev_priv, put_domains);
13465
13466                 intel_post_plane_update(intel_crtc);
13467
13468                 if (modeset)
13469                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13470         }
13471
13472         /* FIXME: add subpixel order */
13473
13474         drm_atomic_helper_wait_for_vblanks(dev, state);
13475
13476         mutex_lock(&dev->struct_mutex);
13477         drm_atomic_helper_cleanup_planes(dev, state);
13478         mutex_unlock(&dev->struct_mutex);
13479
13480         if (any_ms)
13481                 intel_modeset_check_state(dev, state);
13482
13483         drm_atomic_state_free(state);
13484
13485         return 0;
13486 }
13487
13488 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13489 {
13490         struct drm_device *dev = crtc->dev;
13491         struct drm_atomic_state *state;
13492         struct drm_crtc_state *crtc_state;
13493         int ret;
13494
13495         state = drm_atomic_state_alloc(dev);
13496         if (!state) {
13497                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13498                               crtc->base.id);
13499                 return;
13500         }
13501
13502         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13503
13504 retry:
13505         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13506         ret = PTR_ERR_OR_ZERO(crtc_state);
13507         if (!ret) {
13508                 if (!crtc_state->active)
13509                         goto out;
13510
13511                 crtc_state->mode_changed = true;
13512                 ret = drm_atomic_commit(state);
13513         }
13514
13515         if (ret == -EDEADLK) {
13516                 drm_atomic_state_clear(state);
13517                 drm_modeset_backoff(state->acquire_ctx);
13518                 goto retry;
13519         }
13520
13521         if (ret)
13522 out:
13523                 drm_atomic_state_free(state);
13524 }
13525
13526 #undef for_each_intel_crtc_masked
13527
13528 static const struct drm_crtc_funcs intel_crtc_funcs = {
13529         .gamma_set = intel_crtc_gamma_set,
13530         .set_config = drm_atomic_helper_set_config,
13531         .destroy = intel_crtc_destroy,
13532         .page_flip = intel_crtc_page_flip,
13533         .atomic_duplicate_state = intel_crtc_duplicate_state,
13534         .atomic_destroy_state = intel_crtc_destroy_state,
13535 };
13536
13537 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13538                                       struct intel_shared_dpll *pll,
13539                                       struct intel_dpll_hw_state *hw_state)
13540 {
13541         uint32_t val;
13542
13543         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13544                 return false;
13545
13546         val = I915_READ(PCH_DPLL(pll->id));
13547         hw_state->dpll = val;
13548         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13549         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13550
13551         return val & DPLL_VCO_ENABLE;
13552 }
13553
13554 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13555                                   struct intel_shared_dpll *pll)
13556 {
13557         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13558         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13559 }
13560
13561 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13562                                 struct intel_shared_dpll *pll)
13563 {
13564         /* PCH refclock must be enabled first */
13565         ibx_assert_pch_refclk_enabled(dev_priv);
13566
13567         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13568
13569         /* Wait for the clocks to stabilize. */
13570         POSTING_READ(PCH_DPLL(pll->id));
13571         udelay(150);
13572
13573         /* The pixel multiplier can only be updated once the
13574          * DPLL is enabled and the clocks are stable.
13575          *
13576          * So write it again.
13577          */
13578         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13579         POSTING_READ(PCH_DPLL(pll->id));
13580         udelay(200);
13581 }
13582
13583 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13584                                  struct intel_shared_dpll *pll)
13585 {
13586         struct drm_device *dev = dev_priv->dev;
13587         struct intel_crtc *crtc;
13588
13589         /* Make sure no transcoder isn't still depending on us. */
13590         for_each_intel_crtc(dev, crtc) {
13591                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13592                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13593         }
13594
13595         I915_WRITE(PCH_DPLL(pll->id), 0);
13596         POSTING_READ(PCH_DPLL(pll->id));
13597         udelay(200);
13598 }
13599
13600 static char *ibx_pch_dpll_names[] = {
13601         "PCH DPLL A",
13602         "PCH DPLL B",
13603 };
13604
13605 static void ibx_pch_dpll_init(struct drm_device *dev)
13606 {
13607         struct drm_i915_private *dev_priv = dev->dev_private;
13608         int i;
13609
13610         dev_priv->num_shared_dpll = 2;
13611
13612         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13613                 dev_priv->shared_dplls[i].id = i;
13614                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13615                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13616                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13617                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13618                 dev_priv->shared_dplls[i].get_hw_state =
13619                         ibx_pch_dpll_get_hw_state;
13620         }
13621 }
13622
13623 static void intel_shared_dpll_init(struct drm_device *dev)
13624 {
13625         struct drm_i915_private *dev_priv = dev->dev_private;
13626
13627         if (HAS_DDI(dev))
13628                 intel_ddi_pll_init(dev);
13629         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13630                 ibx_pch_dpll_init(dev);
13631         else
13632                 dev_priv->num_shared_dpll = 0;
13633
13634         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13635 }
13636
13637 /**
13638  * intel_prepare_plane_fb - Prepare fb for usage on plane
13639  * @plane: drm plane to prepare for
13640  * @fb: framebuffer to prepare for presentation
13641  *
13642  * Prepares a framebuffer for usage on a display plane.  Generally this
13643  * involves pinning the underlying object and updating the frontbuffer tracking
13644  * bits.  Some older platforms need special physical address handling for
13645  * cursor planes.
13646  *
13647  * Must be called with struct_mutex held.
13648  *
13649  * Returns 0 on success, negative error code on failure.
13650  */
13651 int
13652 intel_prepare_plane_fb(struct drm_plane *plane,
13653                        const struct drm_plane_state *new_state)
13654 {
13655         struct drm_device *dev = plane->dev;
13656         struct drm_framebuffer *fb = new_state->fb;
13657         struct intel_plane *intel_plane = to_intel_plane(plane);
13658         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13659         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13660         int ret = 0;
13661
13662         if (!obj && !old_obj)
13663                 return 0;
13664
13665         if (old_obj) {
13666                 struct drm_crtc_state *crtc_state =
13667                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13668
13669                 /* Big Hammer, we also need to ensure that any pending
13670                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13671                  * current scanout is retired before unpinning the old
13672                  * framebuffer. Note that we rely on userspace rendering
13673                  * into the buffer attached to the pipe they are waiting
13674                  * on. If not, userspace generates a GPU hang with IPEHR
13675                  * point to the MI_WAIT_FOR_EVENT.
13676                  *
13677                  * This should only fail upon a hung GPU, in which case we
13678                  * can safely continue.
13679                  */
13680                 if (needs_modeset(crtc_state))
13681                         ret = i915_gem_object_wait_rendering(old_obj, true);
13682
13683                 /* Swallow -EIO errors to allow updates during hw lockup. */
13684                 if (ret && ret != -EIO)
13685                         return ret;
13686         }
13687
13688         /* For framebuffer backed by dmabuf, wait for fence */
13689         if (obj && obj->base.dma_buf) {
13690                 ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13691                                                           false, true,
13692                                                           MAX_SCHEDULE_TIMEOUT);
13693                 if (ret == -ERESTARTSYS)
13694                         return ret;
13695
13696                 WARN_ON(ret < 0);
13697         }
13698
13699         if (!obj) {
13700                 ret = 0;
13701         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13702             INTEL_INFO(dev)->cursor_needs_physical) {
13703                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13704                 ret = i915_gem_object_attach_phys(obj, align);
13705                 if (ret)
13706                         DRM_DEBUG_KMS("failed to attach phys object\n");
13707         } else {
13708                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13709         }
13710
13711         if (ret == 0) {
13712                 if (obj) {
13713                         struct intel_plane_state *plane_state =
13714                                 to_intel_plane_state(new_state);
13715
13716                         i915_gem_request_assign(&plane_state->wait_req,
13717                                                 obj->last_write_req);
13718                 }
13719
13720                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13721         }
13722
13723         return ret;
13724 }
13725
13726 /**
13727  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13728  * @plane: drm plane to clean up for
13729  * @fb: old framebuffer that was on plane
13730  *
13731  * Cleans up a framebuffer that has just been removed from a plane.
13732  *
13733  * Must be called with struct_mutex held.
13734  */
13735 void
13736 intel_cleanup_plane_fb(struct drm_plane *plane,
13737                        const struct drm_plane_state *old_state)
13738 {
13739         struct drm_device *dev = plane->dev;
13740         struct intel_plane *intel_plane = to_intel_plane(plane);
13741         struct intel_plane_state *old_intel_state;
13742         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13743         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13744
13745         old_intel_state = to_intel_plane_state(old_state);
13746
13747         if (!obj && !old_obj)
13748                 return;
13749
13750         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13751             !INTEL_INFO(dev)->cursor_needs_physical))
13752                 intel_unpin_fb_obj(old_state->fb, old_state);
13753
13754         /* prepare_fb aborted? */
13755         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13756             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13757                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13758
13759         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13760
13761 }
13762
13763 int
13764 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13765 {
13766         int max_scale;
13767         struct drm_device *dev;
13768         struct drm_i915_private *dev_priv;
13769         int crtc_clock, cdclk;
13770
13771         if (!intel_crtc || !crtc_state)
13772                 return DRM_PLANE_HELPER_NO_SCALING;
13773
13774         dev = intel_crtc->base.dev;
13775         dev_priv = dev->dev_private;
13776         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13777         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13778
13779         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13780                 return DRM_PLANE_HELPER_NO_SCALING;
13781
13782         /*
13783          * skl max scale is lower of:
13784          *    close to 3 but not 3, -1 is for that purpose
13785          *            or
13786          *    cdclk/crtc_clock
13787          */
13788         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13789
13790         return max_scale;
13791 }
13792
13793 static int
13794 intel_check_primary_plane(struct drm_plane *plane,
13795                           struct intel_crtc_state *crtc_state,
13796                           struct intel_plane_state *state)
13797 {
13798         struct drm_crtc *crtc = state->base.crtc;
13799         struct drm_framebuffer *fb = state->base.fb;
13800         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13801         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13802         bool can_position = false;
13803
13804         /* use scaler when colorkey is not required */
13805         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13806             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13807                 min_scale = 1;
13808                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13809                 can_position = true;
13810         }
13811
13812         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13813                                              &state->dst, &state->clip,
13814                                              min_scale, max_scale,
13815                                              can_position, true,
13816                                              &state->visible);
13817 }
13818
13819 static void
13820 intel_commit_primary_plane(struct drm_plane *plane,
13821                            struct intel_plane_state *state)
13822 {
13823         struct drm_crtc *crtc = state->base.crtc;
13824         struct drm_framebuffer *fb = state->base.fb;
13825         struct drm_device *dev = plane->dev;
13826         struct drm_i915_private *dev_priv = dev->dev_private;
13827
13828         crtc = crtc ? crtc : plane->crtc;
13829
13830         dev_priv->display.update_primary_plane(crtc, fb,
13831                                                state->src.x1 >> 16,
13832                                                state->src.y1 >> 16);
13833 }
13834
13835 static void
13836 intel_disable_primary_plane(struct drm_plane *plane,
13837                             struct drm_crtc *crtc)
13838 {
13839         struct drm_device *dev = plane->dev;
13840         struct drm_i915_private *dev_priv = dev->dev_private;
13841
13842         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13843 }
13844
13845 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13846                                     struct drm_crtc_state *old_crtc_state)
13847 {
13848         struct drm_device *dev = crtc->dev;
13849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13850         struct intel_crtc_state *old_intel_state =
13851                 to_intel_crtc_state(old_crtc_state);
13852         bool modeset = needs_modeset(crtc->state);
13853
13854         if (intel_crtc->atomic.update_wm_pre)
13855                 intel_update_watermarks(crtc);
13856
13857         /* Perform vblank evasion around commit operation */
13858         intel_pipe_update_start(intel_crtc);
13859
13860         if (modeset)
13861                 return;
13862
13863         if (to_intel_crtc_state(crtc->state)->update_pipe)
13864                 intel_update_pipe_config(intel_crtc, old_intel_state);
13865         else if (INTEL_INFO(dev)->gen >= 9)
13866                 skl_detach_scalers(intel_crtc);
13867 }
13868
13869 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13870                                      struct drm_crtc_state *old_crtc_state)
13871 {
13872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13873
13874         intel_pipe_update_end(intel_crtc);
13875 }
13876
13877 /**
13878  * intel_plane_destroy - destroy a plane
13879  * @plane: plane to destroy
13880  *
13881  * Common destruction function for all types of planes (primary, cursor,
13882  * sprite).
13883  */
13884 void intel_plane_destroy(struct drm_plane *plane)
13885 {
13886         struct intel_plane *intel_plane = to_intel_plane(plane);
13887         drm_plane_cleanup(plane);
13888         kfree(intel_plane);
13889 }
13890
13891 const struct drm_plane_funcs intel_plane_funcs = {
13892         .update_plane = drm_atomic_helper_update_plane,
13893         .disable_plane = drm_atomic_helper_disable_plane,
13894         .destroy = intel_plane_destroy,
13895         .set_property = drm_atomic_helper_plane_set_property,
13896         .atomic_get_property = intel_plane_atomic_get_property,
13897         .atomic_set_property = intel_plane_atomic_set_property,
13898         .atomic_duplicate_state = intel_plane_duplicate_state,
13899         .atomic_destroy_state = intel_plane_destroy_state,
13900
13901 };
13902
13903 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13904                                                     int pipe)
13905 {
13906         struct intel_plane *primary;
13907         struct intel_plane_state *state;
13908         const uint32_t *intel_primary_formats;
13909         unsigned int num_formats;
13910
13911         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13912         if (primary == NULL)
13913                 return NULL;
13914
13915         state = intel_create_plane_state(&primary->base);
13916         if (!state) {
13917                 kfree(primary);
13918                 return NULL;
13919         }
13920         primary->base.state = &state->base;
13921
13922         primary->can_scale = false;
13923         primary->max_downscale = 1;
13924         if (INTEL_INFO(dev)->gen >= 9) {
13925                 primary->can_scale = true;
13926                 state->scaler_id = -1;
13927         }
13928         primary->pipe = pipe;
13929         primary->plane = pipe;
13930         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13931         primary->check_plane = intel_check_primary_plane;
13932         primary->commit_plane = intel_commit_primary_plane;
13933         primary->disable_plane = intel_disable_primary_plane;
13934         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13935                 primary->plane = !pipe;
13936
13937         if (INTEL_INFO(dev)->gen >= 9) {
13938                 intel_primary_formats = skl_primary_formats;
13939                 num_formats = ARRAY_SIZE(skl_primary_formats);
13940         } else if (INTEL_INFO(dev)->gen >= 4) {
13941                 intel_primary_formats = i965_primary_formats;
13942                 num_formats = ARRAY_SIZE(i965_primary_formats);
13943         } else {
13944                 intel_primary_formats = i8xx_primary_formats;
13945                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13946         }
13947
13948         drm_universal_plane_init(dev, &primary->base, 0,
13949                                  &intel_plane_funcs,
13950                                  intel_primary_formats, num_formats,
13951                                  DRM_PLANE_TYPE_PRIMARY, NULL);
13952
13953         if (INTEL_INFO(dev)->gen >= 4)
13954                 intel_create_rotation_property(dev, primary);
13955
13956         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13957
13958         return &primary->base;
13959 }
13960
13961 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13962 {
13963         if (!dev->mode_config.rotation_property) {
13964                 unsigned long flags = BIT(DRM_ROTATE_0) |
13965                         BIT(DRM_ROTATE_180);
13966
13967                 if (INTEL_INFO(dev)->gen >= 9)
13968                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13969
13970                 dev->mode_config.rotation_property =
13971                         drm_mode_create_rotation_property(dev, flags);
13972         }
13973         if (dev->mode_config.rotation_property)
13974                 drm_object_attach_property(&plane->base.base,
13975                                 dev->mode_config.rotation_property,
13976                                 plane->base.state->rotation);
13977 }
13978
13979 static int
13980 intel_check_cursor_plane(struct drm_plane *plane,
13981                          struct intel_crtc_state *crtc_state,
13982                          struct intel_plane_state *state)
13983 {
13984         struct drm_crtc *crtc = crtc_state->base.crtc;
13985         struct drm_framebuffer *fb = state->base.fb;
13986         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13987         unsigned stride;
13988         int ret;
13989
13990         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13991                                             &state->dst, &state->clip,
13992                                             DRM_PLANE_HELPER_NO_SCALING,
13993                                             DRM_PLANE_HELPER_NO_SCALING,
13994                                             true, true, &state->visible);
13995         if (ret)
13996                 return ret;
13997
13998         /* if we want to turn off the cursor ignore width and height */
13999         if (!obj)
14000                 return 0;
14001
14002         /* Check for which cursor types we support */
14003         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14004                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14005                           state->base.crtc_w, state->base.crtc_h);
14006                 return -EINVAL;
14007         }
14008
14009         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14010         if (obj->base.size < stride * state->base.crtc_h) {
14011                 DRM_DEBUG_KMS("buffer is too small\n");
14012                 return -ENOMEM;
14013         }
14014
14015         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14016                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14017                 return -EINVAL;
14018         }
14019
14020         return 0;
14021 }
14022
14023 static void
14024 intel_disable_cursor_plane(struct drm_plane *plane,
14025                            struct drm_crtc *crtc)
14026 {
14027         intel_crtc_update_cursor(crtc, false);
14028 }
14029
14030 static void
14031 intel_commit_cursor_plane(struct drm_plane *plane,
14032                           struct intel_plane_state *state)
14033 {
14034         struct drm_crtc *crtc = state->base.crtc;
14035         struct drm_device *dev = plane->dev;
14036         struct intel_crtc *intel_crtc;
14037         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14038         uint32_t addr;
14039
14040         crtc = crtc ? crtc : plane->crtc;
14041         intel_crtc = to_intel_crtc(crtc);
14042
14043         if (intel_crtc->cursor_bo == obj)
14044                 goto update;
14045
14046         if (!obj)
14047                 addr = 0;
14048         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14049                 addr = i915_gem_obj_ggtt_offset(obj);
14050         else
14051                 addr = obj->phys_handle->busaddr;
14052
14053         intel_crtc->cursor_addr = addr;
14054         intel_crtc->cursor_bo = obj;
14055
14056 update:
14057         intel_crtc_update_cursor(crtc, state->visible);
14058 }
14059
14060 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14061                                                    int pipe)
14062 {
14063         struct intel_plane *cursor;
14064         struct intel_plane_state *state;
14065
14066         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14067         if (cursor == NULL)
14068                 return NULL;
14069
14070         state = intel_create_plane_state(&cursor->base);
14071         if (!state) {
14072                 kfree(cursor);
14073                 return NULL;
14074         }
14075         cursor->base.state = &state->base;
14076
14077         cursor->can_scale = false;
14078         cursor->max_downscale = 1;
14079         cursor->pipe = pipe;
14080         cursor->plane = pipe;
14081         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14082         cursor->check_plane = intel_check_cursor_plane;
14083         cursor->commit_plane = intel_commit_cursor_plane;
14084         cursor->disable_plane = intel_disable_cursor_plane;
14085
14086         drm_universal_plane_init(dev, &cursor->base, 0,
14087                                  &intel_plane_funcs,
14088                                  intel_cursor_formats,
14089                                  ARRAY_SIZE(intel_cursor_formats),
14090                                  DRM_PLANE_TYPE_CURSOR, NULL);
14091
14092         if (INTEL_INFO(dev)->gen >= 4) {
14093                 if (!dev->mode_config.rotation_property)
14094                         dev->mode_config.rotation_property =
14095                                 drm_mode_create_rotation_property(dev,
14096                                                         BIT(DRM_ROTATE_0) |
14097                                                         BIT(DRM_ROTATE_180));
14098                 if (dev->mode_config.rotation_property)
14099                         drm_object_attach_property(&cursor->base.base,
14100                                 dev->mode_config.rotation_property,
14101                                 state->base.rotation);
14102         }
14103
14104         if (INTEL_INFO(dev)->gen >=9)
14105                 state->scaler_id = -1;
14106
14107         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14108
14109         return &cursor->base;
14110 }
14111
14112 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14113         struct intel_crtc_state *crtc_state)
14114 {
14115         int i;
14116         struct intel_scaler *intel_scaler;
14117         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14118
14119         for (i = 0; i < intel_crtc->num_scalers; i++) {
14120                 intel_scaler = &scaler_state->scalers[i];
14121                 intel_scaler->in_use = 0;
14122                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14123         }
14124
14125         scaler_state->scaler_id = -1;
14126 }
14127
14128 static void intel_crtc_init(struct drm_device *dev, int pipe)
14129 {
14130         struct drm_i915_private *dev_priv = dev->dev_private;
14131         struct intel_crtc *intel_crtc;
14132         struct intel_crtc_state *crtc_state = NULL;
14133         struct drm_plane *primary = NULL;
14134         struct drm_plane *cursor = NULL;
14135         int i, ret;
14136
14137         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14138         if (intel_crtc == NULL)
14139                 return;
14140
14141         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14142         if (!crtc_state)
14143                 goto fail;
14144         intel_crtc->config = crtc_state;
14145         intel_crtc->base.state = &crtc_state->base;
14146         crtc_state->base.crtc = &intel_crtc->base;
14147
14148         /* initialize shared scalers */
14149         if (INTEL_INFO(dev)->gen >= 9) {
14150                 if (pipe == PIPE_C)
14151                         intel_crtc->num_scalers = 1;
14152                 else
14153                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14154
14155                 skl_init_scalers(dev, intel_crtc, crtc_state);
14156         }
14157
14158         primary = intel_primary_plane_create(dev, pipe);
14159         if (!primary)
14160                 goto fail;
14161
14162         cursor = intel_cursor_plane_create(dev, pipe);
14163         if (!cursor)
14164                 goto fail;
14165
14166         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14167                                         cursor, &intel_crtc_funcs, NULL);
14168         if (ret)
14169                 goto fail;
14170
14171         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14172         for (i = 0; i < 256; i++) {
14173                 intel_crtc->lut_r[i] = i;
14174                 intel_crtc->lut_g[i] = i;
14175                 intel_crtc->lut_b[i] = i;
14176         }
14177
14178         /*
14179          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14180          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14181          */
14182         intel_crtc->pipe = pipe;
14183         intel_crtc->plane = pipe;
14184         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14185                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14186                 intel_crtc->plane = !pipe;
14187         }
14188
14189         intel_crtc->cursor_base = ~0;
14190         intel_crtc->cursor_cntl = ~0;
14191         intel_crtc->cursor_size = ~0;
14192
14193         intel_crtc->wm.cxsr_allowed = true;
14194
14195         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14196                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14197         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14198         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14199
14200         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14201
14202         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14203         return;
14204
14205 fail:
14206         if (primary)
14207                 drm_plane_cleanup(primary);
14208         if (cursor)
14209                 drm_plane_cleanup(cursor);
14210         kfree(crtc_state);
14211         kfree(intel_crtc);
14212 }
14213
14214 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14215 {
14216         struct drm_encoder *encoder = connector->base.encoder;
14217         struct drm_device *dev = connector->base.dev;
14218
14219         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14220
14221         if (!encoder || WARN_ON(!encoder->crtc))
14222                 return INVALID_PIPE;
14223
14224         return to_intel_crtc(encoder->crtc)->pipe;
14225 }
14226
14227 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14228                                 struct drm_file *file)
14229 {
14230         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14231         struct drm_crtc *drmmode_crtc;
14232         struct intel_crtc *crtc;
14233
14234         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14235
14236         if (!drmmode_crtc) {
14237                 DRM_ERROR("no such CRTC id\n");
14238                 return -ENOENT;
14239         }
14240
14241         crtc = to_intel_crtc(drmmode_crtc);
14242         pipe_from_crtc_id->pipe = crtc->pipe;
14243
14244         return 0;
14245 }
14246
14247 static int intel_encoder_clones(struct intel_encoder *encoder)
14248 {
14249         struct drm_device *dev = encoder->base.dev;
14250         struct intel_encoder *source_encoder;
14251         int index_mask = 0;
14252         int entry = 0;
14253
14254         for_each_intel_encoder(dev, source_encoder) {
14255                 if (encoders_cloneable(encoder, source_encoder))
14256                         index_mask |= (1 << entry);
14257
14258                 entry++;
14259         }
14260
14261         return index_mask;
14262 }
14263
14264 static bool has_edp_a(struct drm_device *dev)
14265 {
14266         struct drm_i915_private *dev_priv = dev->dev_private;
14267
14268         if (!IS_MOBILE(dev))
14269                 return false;
14270
14271         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14272                 return false;
14273
14274         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14275                 return false;
14276
14277         return true;
14278 }
14279
14280 static bool intel_crt_present(struct drm_device *dev)
14281 {
14282         struct drm_i915_private *dev_priv = dev->dev_private;
14283
14284         if (INTEL_INFO(dev)->gen >= 9)
14285                 return false;
14286
14287         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14288                 return false;
14289
14290         if (IS_CHERRYVIEW(dev))
14291                 return false;
14292
14293         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14294                 return false;
14295
14296         /* DDI E can't be used if DDI A requires 4 lanes */
14297         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14298                 return false;
14299
14300         if (!dev_priv->vbt.int_crt_support)
14301                 return false;
14302
14303         return true;
14304 }
14305
14306 static void intel_setup_outputs(struct drm_device *dev)
14307 {
14308         struct drm_i915_private *dev_priv = dev->dev_private;
14309         struct intel_encoder *encoder;
14310         bool dpd_is_edp = false;
14311
14312         intel_lvds_init(dev);
14313
14314         if (intel_crt_present(dev))
14315                 intel_crt_init(dev);
14316
14317         if (IS_BROXTON(dev)) {
14318                 /*
14319                  * FIXME: Broxton doesn't support port detection via the
14320                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14321                  * detect the ports.
14322                  */
14323                 intel_ddi_init(dev, PORT_A);
14324                 intel_ddi_init(dev, PORT_B);
14325                 intel_ddi_init(dev, PORT_C);
14326         } else if (HAS_DDI(dev)) {
14327                 int found;
14328
14329                 /*
14330                  * Haswell uses DDI functions to detect digital outputs.
14331                  * On SKL pre-D0 the strap isn't connected, so we assume
14332                  * it's there.
14333                  */
14334                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14335                 /* WaIgnoreDDIAStrap: skl */
14336                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14337                         intel_ddi_init(dev, PORT_A);
14338
14339                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14340                  * register */
14341                 found = I915_READ(SFUSE_STRAP);
14342
14343                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14344                         intel_ddi_init(dev, PORT_B);
14345                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14346                         intel_ddi_init(dev, PORT_C);
14347                 if (found & SFUSE_STRAP_DDID_DETECTED)
14348                         intel_ddi_init(dev, PORT_D);
14349                 /*
14350                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14351                  */
14352                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14353                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14354                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14355                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14356                         intel_ddi_init(dev, PORT_E);
14357
14358         } else if (HAS_PCH_SPLIT(dev)) {
14359                 int found;
14360                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14361
14362                 if (has_edp_a(dev))
14363                         intel_dp_init(dev, DP_A, PORT_A);
14364
14365                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14366                         /* PCH SDVOB multiplex with HDMIB */
14367                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14368                         if (!found)
14369                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14370                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14371                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14372                 }
14373
14374                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14375                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14376
14377                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14378                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14379
14380                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14381                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14382
14383                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14384                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14385         } else if (IS_VALLEYVIEW(dev)) {
14386                 /*
14387                  * The DP_DETECTED bit is the latched state of the DDC
14388                  * SDA pin at boot. However since eDP doesn't require DDC
14389                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14390                  * eDP ports may have been muxed to an alternate function.
14391                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14392                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14393                  * detect eDP ports.
14394                  */
14395                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14396                     !intel_dp_is_edp(dev, PORT_B))
14397                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14398                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14399                     intel_dp_is_edp(dev, PORT_B))
14400                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14401
14402                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14403                     !intel_dp_is_edp(dev, PORT_C))
14404                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14405                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14406                     intel_dp_is_edp(dev, PORT_C))
14407                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14408
14409                 if (IS_CHERRYVIEW(dev)) {
14410                         /* eDP not supported on port D, so don't check VBT */
14411                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14412                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14413                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14414                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14415                 }
14416
14417                 intel_dsi_init(dev);
14418         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14419                 bool found = false;
14420
14421                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14422                         DRM_DEBUG_KMS("probing SDVOB\n");
14423                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14424                         if (!found && IS_G4X(dev)) {
14425                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14426                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14427                         }
14428
14429                         if (!found && IS_G4X(dev))
14430                                 intel_dp_init(dev, DP_B, PORT_B);
14431                 }
14432
14433                 /* Before G4X SDVOC doesn't have its own detect register */
14434
14435                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14436                         DRM_DEBUG_KMS("probing SDVOC\n");
14437                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14438                 }
14439
14440                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14441
14442                         if (IS_G4X(dev)) {
14443                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14444                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14445                         }
14446                         if (IS_G4X(dev))
14447                                 intel_dp_init(dev, DP_C, PORT_C);
14448                 }
14449
14450                 if (IS_G4X(dev) &&
14451                     (I915_READ(DP_D) & DP_DETECTED))
14452                         intel_dp_init(dev, DP_D, PORT_D);
14453         } else if (IS_GEN2(dev))
14454                 intel_dvo_init(dev);
14455
14456         if (SUPPORTS_TV(dev))
14457                 intel_tv_init(dev);
14458
14459         intel_psr_init(dev);
14460
14461         for_each_intel_encoder(dev, encoder) {
14462                 encoder->base.possible_crtcs = encoder->crtc_mask;
14463                 encoder->base.possible_clones =
14464                         intel_encoder_clones(encoder);
14465         }
14466
14467         intel_init_pch_refclk(dev);
14468
14469         drm_helper_move_panel_connectors_to_head(dev);
14470 }
14471
14472 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14473 {
14474         struct drm_device *dev = fb->dev;
14475         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14476
14477         drm_framebuffer_cleanup(fb);
14478         mutex_lock(&dev->struct_mutex);
14479         WARN_ON(!intel_fb->obj->framebuffer_references--);
14480         drm_gem_object_unreference(&intel_fb->obj->base);
14481         mutex_unlock(&dev->struct_mutex);
14482         kfree(intel_fb);
14483 }
14484
14485 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14486                                                 struct drm_file *file,
14487                                                 unsigned int *handle)
14488 {
14489         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14490         struct drm_i915_gem_object *obj = intel_fb->obj;
14491
14492         if (obj->userptr.mm) {
14493                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14494                 return -EINVAL;
14495         }
14496
14497         return drm_gem_handle_create(file, &obj->base, handle);
14498 }
14499
14500 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14501                                         struct drm_file *file,
14502                                         unsigned flags, unsigned color,
14503                                         struct drm_clip_rect *clips,
14504                                         unsigned num_clips)
14505 {
14506         struct drm_device *dev = fb->dev;
14507         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14508         struct drm_i915_gem_object *obj = intel_fb->obj;
14509
14510         mutex_lock(&dev->struct_mutex);
14511         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14512         mutex_unlock(&dev->struct_mutex);
14513
14514         return 0;
14515 }
14516
14517 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14518         .destroy = intel_user_framebuffer_destroy,
14519         .create_handle = intel_user_framebuffer_create_handle,
14520         .dirty = intel_user_framebuffer_dirty,
14521 };
14522
14523 static
14524 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14525                          uint32_t pixel_format)
14526 {
14527         u32 gen = INTEL_INFO(dev)->gen;
14528
14529         if (gen >= 9) {
14530                 /* "The stride in bytes must not exceed the of the size of 8K
14531                  *  pixels and 32K bytes."
14532                  */
14533                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14534         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14535                 return 32*1024;
14536         } else if (gen >= 4) {
14537                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14538                         return 16*1024;
14539                 else
14540                         return 32*1024;
14541         } else if (gen >= 3) {
14542                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14543                         return 8*1024;
14544                 else
14545                         return 16*1024;
14546         } else {
14547                 /* XXX DSPC is limited to 4k tiled */
14548                 return 8*1024;
14549         }
14550 }
14551
14552 static int intel_framebuffer_init(struct drm_device *dev,
14553                                   struct intel_framebuffer *intel_fb,
14554                                   struct drm_mode_fb_cmd2 *mode_cmd,
14555                                   struct drm_i915_gem_object *obj)
14556 {
14557         unsigned int aligned_height;
14558         int ret;
14559         u32 pitch_limit, stride_alignment;
14560
14561         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14562
14563         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14564                 /* Enforce that fb modifier and tiling mode match, but only for
14565                  * X-tiled. This is needed for FBC. */
14566                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14567                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14568                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14569                         return -EINVAL;
14570                 }
14571         } else {
14572                 if (obj->tiling_mode == I915_TILING_X)
14573                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14574                 else if (obj->tiling_mode == I915_TILING_Y) {
14575                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14576                         return -EINVAL;
14577                 }
14578         }
14579
14580         /* Passed in modifier sanity checking. */
14581         switch (mode_cmd->modifier[0]) {
14582         case I915_FORMAT_MOD_Y_TILED:
14583         case I915_FORMAT_MOD_Yf_TILED:
14584                 if (INTEL_INFO(dev)->gen < 9) {
14585                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14586                                   mode_cmd->modifier[0]);
14587                         return -EINVAL;
14588                 }
14589         case DRM_FORMAT_MOD_NONE:
14590         case I915_FORMAT_MOD_X_TILED:
14591                 break;
14592         default:
14593                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14594                           mode_cmd->modifier[0]);
14595                 return -EINVAL;
14596         }
14597
14598         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14599                                                      mode_cmd->pixel_format);
14600         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14601                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14602                           mode_cmd->pitches[0], stride_alignment);
14603                 return -EINVAL;
14604         }
14605
14606         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14607                                            mode_cmd->pixel_format);
14608         if (mode_cmd->pitches[0] > pitch_limit) {
14609                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14610                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14611                           "tiled" : "linear",
14612                           mode_cmd->pitches[0], pitch_limit);
14613                 return -EINVAL;
14614         }
14615
14616         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14617             mode_cmd->pitches[0] != obj->stride) {
14618                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14619                           mode_cmd->pitches[0], obj->stride);
14620                 return -EINVAL;
14621         }
14622
14623         /* Reject formats not supported by any plane early. */
14624         switch (mode_cmd->pixel_format) {
14625         case DRM_FORMAT_C8:
14626         case DRM_FORMAT_RGB565:
14627         case DRM_FORMAT_XRGB8888:
14628         case DRM_FORMAT_ARGB8888:
14629                 break;
14630         case DRM_FORMAT_XRGB1555:
14631                 if (INTEL_INFO(dev)->gen > 3) {
14632                         DRM_DEBUG("unsupported pixel format: %s\n",
14633                                   drm_get_format_name(mode_cmd->pixel_format));
14634                         return -EINVAL;
14635                 }
14636                 break;
14637         case DRM_FORMAT_ABGR8888:
14638                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14639                         DRM_DEBUG("unsupported pixel format: %s\n",
14640                                   drm_get_format_name(mode_cmd->pixel_format));
14641                         return -EINVAL;
14642                 }
14643                 break;
14644         case DRM_FORMAT_XBGR8888:
14645         case DRM_FORMAT_XRGB2101010:
14646         case DRM_FORMAT_XBGR2101010:
14647                 if (INTEL_INFO(dev)->gen < 4) {
14648                         DRM_DEBUG("unsupported pixel format: %s\n",
14649                                   drm_get_format_name(mode_cmd->pixel_format));
14650                         return -EINVAL;
14651                 }
14652                 break;
14653         case DRM_FORMAT_ABGR2101010:
14654                 if (!IS_VALLEYVIEW(dev)) {
14655                         DRM_DEBUG("unsupported pixel format: %s\n",
14656                                   drm_get_format_name(mode_cmd->pixel_format));
14657                         return -EINVAL;
14658                 }
14659                 break;
14660         case DRM_FORMAT_YUYV:
14661         case DRM_FORMAT_UYVY:
14662         case DRM_FORMAT_YVYU:
14663         case DRM_FORMAT_VYUY:
14664                 if (INTEL_INFO(dev)->gen < 5) {
14665                         DRM_DEBUG("unsupported pixel format: %s\n",
14666                                   drm_get_format_name(mode_cmd->pixel_format));
14667                         return -EINVAL;
14668                 }
14669                 break;
14670         default:
14671                 DRM_DEBUG("unsupported pixel format: %s\n",
14672                           drm_get_format_name(mode_cmd->pixel_format));
14673                 return -EINVAL;
14674         }
14675
14676         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14677         if (mode_cmd->offsets[0] != 0)
14678                 return -EINVAL;
14679
14680         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14681                                                mode_cmd->pixel_format,
14682                                                mode_cmd->modifier[0]);
14683         /* FIXME drm helper for size checks (especially planar formats)? */
14684         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14685                 return -EINVAL;
14686
14687         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14688         intel_fb->obj = obj;
14689         intel_fb->obj->framebuffer_references++;
14690
14691         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14692         if (ret) {
14693                 DRM_ERROR("framebuffer init failed %d\n", ret);
14694                 return ret;
14695         }
14696
14697         return 0;
14698 }
14699
14700 static struct drm_framebuffer *
14701 intel_user_framebuffer_create(struct drm_device *dev,
14702                               struct drm_file *filp,
14703                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14704 {
14705         struct drm_framebuffer *fb;
14706         struct drm_i915_gem_object *obj;
14707         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14708
14709         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14710                                                 mode_cmd.handles[0]));
14711         if (&obj->base == NULL)
14712                 return ERR_PTR(-ENOENT);
14713
14714         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14715         if (IS_ERR(fb))
14716                 drm_gem_object_unreference_unlocked(&obj->base);
14717
14718         return fb;
14719 }
14720
14721 #ifndef CONFIG_DRM_FBDEV_EMULATION
14722 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14723 {
14724 }
14725 #endif
14726
14727 static const struct drm_mode_config_funcs intel_mode_funcs = {
14728         .fb_create = intel_user_framebuffer_create,
14729         .output_poll_changed = intel_fbdev_output_poll_changed,
14730         .atomic_check = intel_atomic_check,
14731         .atomic_commit = intel_atomic_commit,
14732         .atomic_state_alloc = intel_atomic_state_alloc,
14733         .atomic_state_clear = intel_atomic_state_clear,
14734 };
14735
14736 /* Set up chip specific display functions */
14737 static void intel_init_display(struct drm_device *dev)
14738 {
14739         struct drm_i915_private *dev_priv = dev->dev_private;
14740
14741         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14742                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14743         else if (IS_CHERRYVIEW(dev))
14744                 dev_priv->display.find_dpll = chv_find_best_dpll;
14745         else if (IS_VALLEYVIEW(dev))
14746                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14747         else if (IS_PINEVIEW(dev))
14748                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14749         else
14750                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14751
14752         if (INTEL_INFO(dev)->gen >= 9) {
14753                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14754                 dev_priv->display.get_initial_plane_config =
14755                         skylake_get_initial_plane_config;
14756                 dev_priv->display.crtc_compute_clock =
14757                         haswell_crtc_compute_clock;
14758                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14759                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14760                 dev_priv->display.update_primary_plane =
14761                         skylake_update_primary_plane;
14762         } else if (HAS_DDI(dev)) {
14763                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14764                 dev_priv->display.get_initial_plane_config =
14765                         ironlake_get_initial_plane_config;
14766                 dev_priv->display.crtc_compute_clock =
14767                         haswell_crtc_compute_clock;
14768                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14769                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14770                 dev_priv->display.update_primary_plane =
14771                         ironlake_update_primary_plane;
14772         } else if (HAS_PCH_SPLIT(dev)) {
14773                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14774                 dev_priv->display.get_initial_plane_config =
14775                         ironlake_get_initial_plane_config;
14776                 dev_priv->display.crtc_compute_clock =
14777                         ironlake_crtc_compute_clock;
14778                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14779                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14780                 dev_priv->display.update_primary_plane =
14781                         ironlake_update_primary_plane;
14782         } else if (IS_VALLEYVIEW(dev)) {
14783                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14784                 dev_priv->display.get_initial_plane_config =
14785                         i9xx_get_initial_plane_config;
14786                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14787                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14788                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14789                 dev_priv->display.update_primary_plane =
14790                         i9xx_update_primary_plane;
14791         } else {
14792                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14793                 dev_priv->display.get_initial_plane_config =
14794                         i9xx_get_initial_plane_config;
14795                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14796                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14797                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14798                 dev_priv->display.update_primary_plane =
14799                         i9xx_update_primary_plane;
14800         }
14801
14802         /* Returns the core display clock speed */
14803         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14804                 dev_priv->display.get_display_clock_speed =
14805                         skylake_get_display_clock_speed;
14806         else if (IS_BROXTON(dev))
14807                 dev_priv->display.get_display_clock_speed =
14808                         broxton_get_display_clock_speed;
14809         else if (IS_BROADWELL(dev))
14810                 dev_priv->display.get_display_clock_speed =
14811                         broadwell_get_display_clock_speed;
14812         else if (IS_HASWELL(dev))
14813                 dev_priv->display.get_display_clock_speed =
14814                         haswell_get_display_clock_speed;
14815         else if (IS_VALLEYVIEW(dev))
14816                 dev_priv->display.get_display_clock_speed =
14817                         valleyview_get_display_clock_speed;
14818         else if (IS_GEN5(dev))
14819                 dev_priv->display.get_display_clock_speed =
14820                         ilk_get_display_clock_speed;
14821         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14822                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14823                 dev_priv->display.get_display_clock_speed =
14824                         i945_get_display_clock_speed;
14825         else if (IS_GM45(dev))
14826                 dev_priv->display.get_display_clock_speed =
14827                         gm45_get_display_clock_speed;
14828         else if (IS_CRESTLINE(dev))
14829                 dev_priv->display.get_display_clock_speed =
14830                         i965gm_get_display_clock_speed;
14831         else if (IS_PINEVIEW(dev))
14832                 dev_priv->display.get_display_clock_speed =
14833                         pnv_get_display_clock_speed;
14834         else if (IS_G33(dev) || IS_G4X(dev))
14835                 dev_priv->display.get_display_clock_speed =
14836                         g33_get_display_clock_speed;
14837         else if (IS_I915G(dev))
14838                 dev_priv->display.get_display_clock_speed =
14839                         i915_get_display_clock_speed;
14840         else if (IS_I945GM(dev) || IS_845G(dev))
14841                 dev_priv->display.get_display_clock_speed =
14842                         i9xx_misc_get_display_clock_speed;
14843         else if (IS_I915GM(dev))
14844                 dev_priv->display.get_display_clock_speed =
14845                         i915gm_get_display_clock_speed;
14846         else if (IS_I865G(dev))
14847                 dev_priv->display.get_display_clock_speed =
14848                         i865_get_display_clock_speed;
14849         else if (IS_I85X(dev))
14850                 dev_priv->display.get_display_clock_speed =
14851                         i85x_get_display_clock_speed;
14852         else { /* 830 */
14853                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14854                 dev_priv->display.get_display_clock_speed =
14855                         i830_get_display_clock_speed;
14856         }
14857
14858         if (IS_GEN5(dev)) {
14859                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14860         } else if (IS_GEN6(dev)) {
14861                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14862         } else if (IS_IVYBRIDGE(dev)) {
14863                 /* FIXME: detect B0+ stepping and use auto training */
14864                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14865         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14866                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14867                 if (IS_BROADWELL(dev)) {
14868                         dev_priv->display.modeset_commit_cdclk =
14869                                 broadwell_modeset_commit_cdclk;
14870                         dev_priv->display.modeset_calc_cdclk =
14871                                 broadwell_modeset_calc_cdclk;
14872                 }
14873         } else if (IS_VALLEYVIEW(dev)) {
14874                 dev_priv->display.modeset_commit_cdclk =
14875                         valleyview_modeset_commit_cdclk;
14876                 dev_priv->display.modeset_calc_cdclk =
14877                         valleyview_modeset_calc_cdclk;
14878         } else if (IS_BROXTON(dev)) {
14879                 dev_priv->display.modeset_commit_cdclk =
14880                         broxton_modeset_commit_cdclk;
14881                 dev_priv->display.modeset_calc_cdclk =
14882                         broxton_modeset_calc_cdclk;
14883         }
14884
14885         switch (INTEL_INFO(dev)->gen) {
14886         case 2:
14887                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14888                 break;
14889
14890         case 3:
14891                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14892                 break;
14893
14894         case 4:
14895         case 5:
14896                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14897                 break;
14898
14899         case 6:
14900                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14901                 break;
14902         case 7:
14903         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14904                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14905                 break;
14906         case 9:
14907                 /* Drop through - unsupported since execlist only. */
14908         default:
14909                 /* Default just returns -ENODEV to indicate unsupported */
14910                 dev_priv->display.queue_flip = intel_default_queue_flip;
14911         }
14912
14913         mutex_init(&dev_priv->pps_mutex);
14914 }
14915
14916 /*
14917  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14918  * resume, or other times.  This quirk makes sure that's the case for
14919  * affected systems.
14920  */
14921 static void quirk_pipea_force(struct drm_device *dev)
14922 {
14923         struct drm_i915_private *dev_priv = dev->dev_private;
14924
14925         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14926         DRM_INFO("applying pipe a force quirk\n");
14927 }
14928
14929 static void quirk_pipeb_force(struct drm_device *dev)
14930 {
14931         struct drm_i915_private *dev_priv = dev->dev_private;
14932
14933         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14934         DRM_INFO("applying pipe b force quirk\n");
14935 }
14936
14937 /*
14938  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14939  */
14940 static void quirk_ssc_force_disable(struct drm_device *dev)
14941 {
14942         struct drm_i915_private *dev_priv = dev->dev_private;
14943         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14944         DRM_INFO("applying lvds SSC disable quirk\n");
14945 }
14946
14947 /*
14948  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14949  * brightness value
14950  */
14951 static void quirk_invert_brightness(struct drm_device *dev)
14952 {
14953         struct drm_i915_private *dev_priv = dev->dev_private;
14954         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14955         DRM_INFO("applying inverted panel brightness quirk\n");
14956 }
14957
14958 /* Some VBT's incorrectly indicate no backlight is present */
14959 static void quirk_backlight_present(struct drm_device *dev)
14960 {
14961         struct drm_i915_private *dev_priv = dev->dev_private;
14962         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14963         DRM_INFO("applying backlight present quirk\n");
14964 }
14965
14966 struct intel_quirk {
14967         int device;
14968         int subsystem_vendor;
14969         int subsystem_device;
14970         void (*hook)(struct drm_device *dev);
14971 };
14972
14973 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14974 struct intel_dmi_quirk {
14975         void (*hook)(struct drm_device *dev);
14976         const struct dmi_system_id (*dmi_id_list)[];
14977 };
14978
14979 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14980 {
14981         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14982         return 1;
14983 }
14984
14985 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14986         {
14987                 .dmi_id_list = &(const struct dmi_system_id[]) {
14988                         {
14989                                 .callback = intel_dmi_reverse_brightness,
14990                                 .ident = "NCR Corporation",
14991                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14992                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14993                                 },
14994                         },
14995                         { }  /* terminating entry */
14996                 },
14997                 .hook = quirk_invert_brightness,
14998         },
14999 };
15000
15001 static struct intel_quirk intel_quirks[] = {
15002         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15003         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15004
15005         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15006         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15007
15008         /* 830 needs to leave pipe A & dpll A up */
15009         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15010
15011         /* 830 needs to leave pipe B & dpll B up */
15012         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15013
15014         /* Lenovo U160 cannot use SSC on LVDS */
15015         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15016
15017         /* Sony Vaio Y cannot use SSC on LVDS */
15018         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15019
15020         /* Acer Aspire 5734Z must invert backlight brightness */
15021         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15022
15023         /* Acer/eMachines G725 */
15024         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15025
15026         /* Acer/eMachines e725 */
15027         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15028
15029         /* Acer/Packard Bell NCL20 */
15030         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15031
15032         /* Acer Aspire 4736Z */
15033         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15034
15035         /* Acer Aspire 5336 */
15036         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15037
15038         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15039         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15040
15041         /* Acer C720 Chromebook (Core i3 4005U) */
15042         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15043
15044         /* Apple Macbook 2,1 (Core 2 T7400) */
15045         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15046
15047         /* Apple Macbook 4,1 */
15048         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15049
15050         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15051         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15052
15053         /* HP Chromebook 14 (Celeron 2955U) */
15054         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15055
15056         /* Dell Chromebook 11 */
15057         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15058
15059         /* Dell Chromebook 11 (2015 version) */
15060         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15061 };
15062
15063 static void intel_init_quirks(struct drm_device *dev)
15064 {
15065         struct pci_dev *d = dev->pdev;
15066         int i;
15067
15068         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15069                 struct intel_quirk *q = &intel_quirks[i];
15070
15071                 if (d->device == q->device &&
15072                     (d->subsystem_vendor == q->subsystem_vendor ||
15073                      q->subsystem_vendor == PCI_ANY_ID) &&
15074                     (d->subsystem_device == q->subsystem_device ||
15075                      q->subsystem_device == PCI_ANY_ID))
15076                         q->hook(dev);
15077         }
15078         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15079                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15080                         intel_dmi_quirks[i].hook(dev);
15081         }
15082 }
15083
15084 /* Disable the VGA plane that we never use */
15085 static void i915_disable_vga(struct drm_device *dev)
15086 {
15087         struct drm_i915_private *dev_priv = dev->dev_private;
15088         u8 sr1;
15089         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15090
15091         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15092         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15093         outb(SR01, VGA_SR_INDEX);
15094         sr1 = inb(VGA_SR_DATA);
15095         outb(sr1 | 1<<5, VGA_SR_DATA);
15096         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15097         udelay(300);
15098
15099         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15100         POSTING_READ(vga_reg);
15101 }
15102
15103 void intel_modeset_init_hw(struct drm_device *dev)
15104 {
15105         intel_update_cdclk(dev);
15106         intel_prepare_ddi(dev);
15107         intel_init_clock_gating(dev);
15108         intel_enable_gt_powersave(dev);
15109 }
15110
15111 void intel_modeset_init(struct drm_device *dev)
15112 {
15113         struct drm_i915_private *dev_priv = dev->dev_private;
15114         int sprite, ret;
15115         enum pipe pipe;
15116         struct intel_crtc *crtc;
15117
15118         drm_mode_config_init(dev);
15119
15120         dev->mode_config.min_width = 0;
15121         dev->mode_config.min_height = 0;
15122
15123         dev->mode_config.preferred_depth = 24;
15124         dev->mode_config.prefer_shadow = 1;
15125
15126         dev->mode_config.allow_fb_modifiers = true;
15127
15128         dev->mode_config.funcs = &intel_mode_funcs;
15129
15130         intel_init_quirks(dev);
15131
15132         intel_init_pm(dev);
15133
15134         if (INTEL_INFO(dev)->num_pipes == 0)
15135                 return;
15136
15137         /*
15138          * There may be no VBT; and if the BIOS enabled SSC we can
15139          * just keep using it to avoid unnecessary flicker.  Whereas if the
15140          * BIOS isn't using it, don't assume it will work even if the VBT
15141          * indicates as much.
15142          */
15143         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15144                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15145                                             DREF_SSC1_ENABLE);
15146
15147                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15148                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15149                                      bios_lvds_use_ssc ? "en" : "dis",
15150                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15151                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15152                 }
15153         }
15154
15155         intel_init_display(dev);
15156         intel_init_audio(dev);
15157
15158         if (IS_GEN2(dev)) {
15159                 dev->mode_config.max_width = 2048;
15160                 dev->mode_config.max_height = 2048;
15161         } else if (IS_GEN3(dev)) {
15162                 dev->mode_config.max_width = 4096;
15163                 dev->mode_config.max_height = 4096;
15164         } else {
15165                 dev->mode_config.max_width = 8192;
15166                 dev->mode_config.max_height = 8192;
15167         }
15168
15169         if (IS_845G(dev) || IS_I865G(dev)) {
15170                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15171                 dev->mode_config.cursor_height = 1023;
15172         } else if (IS_GEN2(dev)) {
15173                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15174                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15175         } else {
15176                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15177                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15178         }
15179
15180         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15181
15182         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15183                       INTEL_INFO(dev)->num_pipes,
15184                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15185
15186         for_each_pipe(dev_priv, pipe) {
15187                 intel_crtc_init(dev, pipe);
15188                 for_each_sprite(dev_priv, pipe, sprite) {
15189                         ret = intel_plane_init(dev, pipe, sprite);
15190                         if (ret)
15191                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15192                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15193                 }
15194         }
15195
15196         intel_update_czclk(dev_priv);
15197         intel_update_cdclk(dev);
15198
15199         intel_shared_dpll_init(dev);
15200
15201         /* Just disable it once at startup */
15202         i915_disable_vga(dev);
15203         intel_setup_outputs(dev);
15204
15205         drm_modeset_lock_all(dev);
15206         intel_modeset_setup_hw_state(dev);
15207         drm_modeset_unlock_all(dev);
15208
15209         for_each_intel_crtc(dev, crtc) {
15210                 struct intel_initial_plane_config plane_config = {};
15211
15212                 if (!crtc->active)
15213                         continue;
15214
15215                 /*
15216                  * Note that reserving the BIOS fb up front prevents us
15217                  * from stuffing other stolen allocations like the ring
15218                  * on top.  This prevents some ugliness at boot time, and
15219                  * can even allow for smooth boot transitions if the BIOS
15220                  * fb is large enough for the active pipe configuration.
15221                  */
15222                 dev_priv->display.get_initial_plane_config(crtc,
15223                                                            &plane_config);
15224
15225                 /*
15226                  * If the fb is shared between multiple heads, we'll
15227                  * just get the first one.
15228                  */
15229                 intel_find_initial_plane_obj(crtc, &plane_config);
15230         }
15231 }
15232
15233 static void intel_enable_pipe_a(struct drm_device *dev)
15234 {
15235         struct intel_connector *connector;
15236         struct drm_connector *crt = NULL;
15237         struct intel_load_detect_pipe load_detect_temp;
15238         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15239
15240         /* We can't just switch on the pipe A, we need to set things up with a
15241          * proper mode and output configuration. As a gross hack, enable pipe A
15242          * by enabling the load detect pipe once. */
15243         for_each_intel_connector(dev, connector) {
15244                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15245                         crt = &connector->base;
15246                         break;
15247                 }
15248         }
15249
15250         if (!crt)
15251                 return;
15252
15253         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15254                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15255 }
15256
15257 static bool
15258 intel_check_plane_mapping(struct intel_crtc *crtc)
15259 {
15260         struct drm_device *dev = crtc->base.dev;
15261         struct drm_i915_private *dev_priv = dev->dev_private;
15262         u32 val;
15263
15264         if (INTEL_INFO(dev)->num_pipes == 1)
15265                 return true;
15266
15267         val = I915_READ(DSPCNTR(!crtc->plane));
15268
15269         if ((val & DISPLAY_PLANE_ENABLE) &&
15270             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15271                 return false;
15272
15273         return true;
15274 }
15275
15276 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15277 {
15278         struct drm_device *dev = crtc->base.dev;
15279         struct intel_encoder *encoder;
15280
15281         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15282                 return true;
15283
15284         return false;
15285 }
15286
15287 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15288 {
15289         struct drm_device *dev = crtc->base.dev;
15290         struct drm_i915_private *dev_priv = dev->dev_private;
15291         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15292
15293         /* Clear any frame start delays used for debugging left by the BIOS */
15294         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15295
15296         /* restore vblank interrupts to correct state */
15297         drm_crtc_vblank_reset(&crtc->base);
15298         if (crtc->active) {
15299                 struct intel_plane *plane;
15300
15301                 drm_crtc_vblank_on(&crtc->base);
15302
15303                 /* Disable everything but the primary plane */
15304                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15305                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15306                                 continue;
15307
15308                         plane->disable_plane(&plane->base, &crtc->base);
15309                 }
15310         }
15311
15312         /* We need to sanitize the plane -> pipe mapping first because this will
15313          * disable the crtc (and hence change the state) if it is wrong. Note
15314          * that gen4+ has a fixed plane -> pipe mapping.  */
15315         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15316                 bool plane;
15317
15318                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15319                               crtc->base.base.id);
15320
15321                 /* Pipe has the wrong plane attached and the plane is active.
15322                  * Temporarily change the plane mapping and disable everything
15323                  * ...  */
15324                 plane = crtc->plane;
15325                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15326                 crtc->plane = !plane;
15327                 intel_crtc_disable_noatomic(&crtc->base);
15328                 crtc->plane = plane;
15329         }
15330
15331         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15332             crtc->pipe == PIPE_A && !crtc->active) {
15333                 /* BIOS forgot to enable pipe A, this mostly happens after
15334                  * resume. Force-enable the pipe to fix this, the update_dpms
15335                  * call below we restore the pipe to the right state, but leave
15336                  * the required bits on. */
15337                 intel_enable_pipe_a(dev);
15338         }
15339
15340         /* Adjust the state of the output pipe according to whether we
15341          * have active connectors/encoders. */
15342         if (!intel_crtc_has_encoders(crtc))
15343                 intel_crtc_disable_noatomic(&crtc->base);
15344
15345         if (crtc->active != crtc->base.state->active) {
15346                 struct intel_encoder *encoder;
15347
15348                 /* This can happen either due to bugs in the get_hw_state
15349                  * functions or because of calls to intel_crtc_disable_noatomic,
15350                  * or because the pipe is force-enabled due to the
15351                  * pipe A quirk. */
15352                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15353                               crtc->base.base.id,
15354                               crtc->base.state->enable ? "enabled" : "disabled",
15355                               crtc->active ? "enabled" : "disabled");
15356
15357                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15358                 crtc->base.state->active = crtc->active;
15359                 crtc->base.enabled = crtc->active;
15360
15361                 /* Because we only establish the connector -> encoder ->
15362                  * crtc links if something is active, this means the
15363                  * crtc is now deactivated. Break the links. connector
15364                  * -> encoder links are only establish when things are
15365                  *  actually up, hence no need to break them. */
15366                 WARN_ON(crtc->active);
15367
15368                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15369                         encoder->base.crtc = NULL;
15370         }
15371
15372         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15373                 /*
15374                  * We start out with underrun reporting disabled to avoid races.
15375                  * For correct bookkeeping mark this on active crtcs.
15376                  *
15377                  * Also on gmch platforms we dont have any hardware bits to
15378                  * disable the underrun reporting. Which means we need to start
15379                  * out with underrun reporting disabled also on inactive pipes,
15380                  * since otherwise we'll complain about the garbage we read when
15381                  * e.g. coming up after runtime pm.
15382                  *
15383                  * No protection against concurrent access is required - at
15384                  * worst a fifo underrun happens which also sets this to false.
15385                  */
15386                 crtc->cpu_fifo_underrun_disabled = true;
15387                 crtc->pch_fifo_underrun_disabled = true;
15388         }
15389 }
15390
15391 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15392 {
15393         struct intel_connector *connector;
15394         struct drm_device *dev = encoder->base.dev;
15395         bool active = false;
15396
15397         /* We need to check both for a crtc link (meaning that the
15398          * encoder is active and trying to read from a pipe) and the
15399          * pipe itself being active. */
15400         bool has_active_crtc = encoder->base.crtc &&
15401                 to_intel_crtc(encoder->base.crtc)->active;
15402
15403         for_each_intel_connector(dev, connector) {
15404                 if (connector->base.encoder != &encoder->base)
15405                         continue;
15406
15407                 active = true;
15408                 break;
15409         }
15410
15411         if (active && !has_active_crtc) {
15412                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15413                               encoder->base.base.id,
15414                               encoder->base.name);
15415
15416                 /* Connector is active, but has no active pipe. This is
15417                  * fallout from our resume register restoring. Disable
15418                  * the encoder manually again. */
15419                 if (encoder->base.crtc) {
15420                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15421                                       encoder->base.base.id,
15422                                       encoder->base.name);
15423                         encoder->disable(encoder);
15424                         if (encoder->post_disable)
15425                                 encoder->post_disable(encoder);
15426                 }
15427                 encoder->base.crtc = NULL;
15428
15429                 /* Inconsistent output/port/pipe state happens presumably due to
15430                  * a bug in one of the get_hw_state functions. Or someplace else
15431                  * in our code, like the register restore mess on resume. Clamp
15432                  * things to off as a safer default. */
15433                 for_each_intel_connector(dev, connector) {
15434                         if (connector->encoder != encoder)
15435                                 continue;
15436                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15437                         connector->base.encoder = NULL;
15438                 }
15439         }
15440         /* Enabled encoders without active connectors will be fixed in
15441          * the crtc fixup. */
15442 }
15443
15444 void i915_redisable_vga_power_on(struct drm_device *dev)
15445 {
15446         struct drm_i915_private *dev_priv = dev->dev_private;
15447         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15448
15449         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15450                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15451                 i915_disable_vga(dev);
15452         }
15453 }
15454
15455 void i915_redisable_vga(struct drm_device *dev)
15456 {
15457         struct drm_i915_private *dev_priv = dev->dev_private;
15458
15459         /* This function can be called both from intel_modeset_setup_hw_state or
15460          * at a very early point in our resume sequence, where the power well
15461          * structures are not yet restored. Since this function is at a very
15462          * paranoid "someone might have enabled VGA while we were not looking"
15463          * level, just check if the power well is enabled instead of trying to
15464          * follow the "don't touch the power well if we don't need it" policy
15465          * the rest of the driver uses. */
15466         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15467                 return;
15468
15469         i915_redisable_vga_power_on(dev);
15470 }
15471
15472 static bool primary_get_hw_state(struct intel_plane *plane)
15473 {
15474         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15475
15476         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15477 }
15478
15479 /* FIXME read out full plane state for all planes */
15480 static void readout_plane_state(struct intel_crtc *crtc)
15481 {
15482         struct drm_plane *primary = crtc->base.primary;
15483         struct intel_plane_state *plane_state =
15484                 to_intel_plane_state(primary->state);
15485
15486         plane_state->visible = crtc->active &&
15487                 primary_get_hw_state(to_intel_plane(primary));
15488
15489         if (plane_state->visible)
15490                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15491 }
15492
15493 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15494 {
15495         struct drm_i915_private *dev_priv = dev->dev_private;
15496         enum pipe pipe;
15497         struct intel_crtc *crtc;
15498         struct intel_encoder *encoder;
15499         struct intel_connector *connector;
15500         int i;
15501
15502         for_each_intel_crtc(dev, crtc) {
15503                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15504                 memset(crtc->config, 0, sizeof(*crtc->config));
15505                 crtc->config->base.crtc = &crtc->base;
15506
15507                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15508                                                                  crtc->config);
15509
15510                 crtc->base.state->active = crtc->active;
15511                 crtc->base.enabled = crtc->active;
15512
15513                 readout_plane_state(crtc);
15514
15515                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15516                               crtc->base.base.id,
15517                               crtc->active ? "enabled" : "disabled");
15518         }
15519
15520         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15521                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15522
15523                 pll->on = pll->get_hw_state(dev_priv, pll,
15524                                             &pll->config.hw_state);
15525                 pll->active = 0;
15526                 pll->config.crtc_mask = 0;
15527                 for_each_intel_crtc(dev, crtc) {
15528                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15529                                 pll->active++;
15530                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15531                         }
15532                 }
15533
15534                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15535                               pll->name, pll->config.crtc_mask, pll->on);
15536
15537                 if (pll->config.crtc_mask)
15538                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15539         }
15540
15541         for_each_intel_encoder(dev, encoder) {
15542                 pipe = 0;
15543
15544                 if (encoder->get_hw_state(encoder, &pipe)) {
15545                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15546                         encoder->base.crtc = &crtc->base;
15547                         encoder->get_config(encoder, crtc->config);
15548                 } else {
15549                         encoder->base.crtc = NULL;
15550                 }
15551
15552                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15553                               encoder->base.base.id,
15554                               encoder->base.name,
15555                               encoder->base.crtc ? "enabled" : "disabled",
15556                               pipe_name(pipe));
15557         }
15558
15559         for_each_intel_connector(dev, connector) {
15560                 if (connector->get_hw_state(connector)) {
15561                         connector->base.dpms = DRM_MODE_DPMS_ON;
15562                         connector->base.encoder = &connector->encoder->base;
15563                 } else {
15564                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15565                         connector->base.encoder = NULL;
15566                 }
15567                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15568                               connector->base.base.id,
15569                               connector->base.name,
15570                               connector->base.encoder ? "enabled" : "disabled");
15571         }
15572
15573         for_each_intel_crtc(dev, crtc) {
15574                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15575
15576                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15577                 if (crtc->base.state->active) {
15578                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15579                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15580                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15581
15582                         /*
15583                          * The initial mode needs to be set in order to keep
15584                          * the atomic core happy. It wants a valid mode if the
15585                          * crtc's enabled, so we do the above call.
15586                          *
15587                          * At this point some state updated by the connectors
15588                          * in their ->detect() callback has not run yet, so
15589                          * no recalculation can be done yet.
15590                          *
15591                          * Even if we could do a recalculation and modeset
15592                          * right now it would cause a double modeset if
15593                          * fbdev or userspace chooses a different initial mode.
15594                          *
15595                          * If that happens, someone indicated they wanted a
15596                          * mode change, which means it's safe to do a full
15597                          * recalculation.
15598                          */
15599                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15600
15601                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15602                         update_scanline_offset(crtc);
15603                 }
15604         }
15605 }
15606
15607 /* Scan out the current hw modeset state,
15608  * and sanitizes it to the current state
15609  */
15610 static void
15611 intel_modeset_setup_hw_state(struct drm_device *dev)
15612 {
15613         struct drm_i915_private *dev_priv = dev->dev_private;
15614         enum pipe pipe;
15615         struct intel_crtc *crtc;
15616         struct intel_encoder *encoder;
15617         int i;
15618
15619         intel_modeset_readout_hw_state(dev);
15620
15621         /* HW state is read out, now we need to sanitize this mess. */
15622         for_each_intel_encoder(dev, encoder) {
15623                 intel_sanitize_encoder(encoder);
15624         }
15625
15626         for_each_pipe(dev_priv, pipe) {
15627                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15628                 intel_sanitize_crtc(crtc);
15629                 intel_dump_pipe_config(crtc, crtc->config,
15630                                        "[setup_hw_state]");
15631         }
15632
15633         intel_modeset_update_connector_atomic_state(dev);
15634
15635         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15636                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15637
15638                 if (!pll->on || pll->active)
15639                         continue;
15640
15641                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15642
15643                 pll->disable(dev_priv, pll);
15644                 pll->on = false;
15645         }
15646
15647         if (IS_VALLEYVIEW(dev))
15648                 vlv_wm_get_hw_state(dev);
15649         else if (IS_GEN9(dev))
15650                 skl_wm_get_hw_state(dev);
15651         else if (HAS_PCH_SPLIT(dev))
15652                 ilk_wm_get_hw_state(dev);
15653
15654         for_each_intel_crtc(dev, crtc) {
15655                 unsigned long put_domains;
15656
15657                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15658                 if (WARN_ON(put_domains))
15659                         modeset_put_power_domains(dev_priv, put_domains);
15660         }
15661         intel_display_set_init_power(dev_priv, false);
15662 }
15663
15664 void intel_display_resume(struct drm_device *dev)
15665 {
15666         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15667         struct intel_connector *conn;
15668         struct intel_plane *plane;
15669         struct drm_crtc *crtc;
15670         int ret;
15671
15672         if (!state)
15673                 return;
15674
15675         state->acquire_ctx = dev->mode_config.acquire_ctx;
15676
15677         /* preserve complete old state, including dpll */
15678         intel_atomic_get_shared_dpll_state(state);
15679
15680         for_each_crtc(dev, crtc) {
15681                 struct drm_crtc_state *crtc_state =
15682                         drm_atomic_get_crtc_state(state, crtc);
15683
15684                 ret = PTR_ERR_OR_ZERO(crtc_state);
15685                 if (ret)
15686                         goto err;
15687
15688                 /* force a restore */
15689                 crtc_state->mode_changed = true;
15690         }
15691
15692         for_each_intel_plane(dev, plane) {
15693                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15694                 if (ret)
15695                         goto err;
15696         }
15697
15698         for_each_intel_connector(dev, conn) {
15699                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15700                 if (ret)
15701                         goto err;
15702         }
15703
15704         intel_modeset_setup_hw_state(dev);
15705
15706         i915_redisable_vga(dev);
15707         ret = drm_atomic_commit(state);
15708         if (!ret)
15709                 return;
15710
15711 err:
15712         DRM_ERROR("Restoring old state failed with %i\n", ret);
15713         drm_atomic_state_free(state);
15714 }
15715
15716 void intel_modeset_gem_init(struct drm_device *dev)
15717 {
15718         struct drm_crtc *c;
15719         struct drm_i915_gem_object *obj;
15720         int ret;
15721
15722         mutex_lock(&dev->struct_mutex);
15723         intel_init_gt_powersave(dev);
15724         mutex_unlock(&dev->struct_mutex);
15725
15726         intel_modeset_init_hw(dev);
15727
15728         intel_setup_overlay(dev);
15729
15730         /*
15731          * Make sure any fbs we allocated at startup are properly
15732          * pinned & fenced.  When we do the allocation it's too early
15733          * for this.
15734          */
15735         for_each_crtc(dev, c) {
15736                 obj = intel_fb_obj(c->primary->fb);
15737                 if (obj == NULL)
15738                         continue;
15739
15740                 mutex_lock(&dev->struct_mutex);
15741                 ret = intel_pin_and_fence_fb_obj(c->primary,
15742                                                  c->primary->fb,
15743                                                  c->primary->state);
15744                 mutex_unlock(&dev->struct_mutex);
15745                 if (ret) {
15746                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15747                                   to_intel_crtc(c)->pipe);
15748                         drm_framebuffer_unreference(c->primary->fb);
15749                         c->primary->fb = NULL;
15750                         c->primary->crtc = c->primary->state->crtc = NULL;
15751                         update_state_fb(c->primary);
15752                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15753                 }
15754         }
15755
15756         intel_backlight_register(dev);
15757 }
15758
15759 void intel_connector_unregister(struct intel_connector *intel_connector)
15760 {
15761         struct drm_connector *connector = &intel_connector->base;
15762
15763         intel_panel_destroy_backlight(connector);
15764         drm_connector_unregister(connector);
15765 }
15766
15767 void intel_modeset_cleanup(struct drm_device *dev)
15768 {
15769         struct drm_i915_private *dev_priv = dev->dev_private;
15770         struct drm_connector *connector;
15771
15772         intel_disable_gt_powersave(dev);
15773
15774         intel_backlight_unregister(dev);
15775
15776         /*
15777          * Interrupts and polling as the first thing to avoid creating havoc.
15778          * Too much stuff here (turning of connectors, ...) would
15779          * experience fancy races otherwise.
15780          */
15781         intel_irq_uninstall(dev_priv);
15782
15783         /*
15784          * Due to the hpd irq storm handling the hotplug work can re-arm the
15785          * poll handlers. Hence disable polling after hpd handling is shut down.
15786          */
15787         drm_kms_helper_poll_fini(dev);
15788
15789         intel_unregister_dsm_handler();
15790
15791         intel_fbc_disable(dev_priv);
15792
15793         /* flush any delayed tasks or pending work */
15794         flush_scheduled_work();
15795
15796         /* destroy the backlight and sysfs files before encoders/connectors */
15797         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15798                 struct intel_connector *intel_connector;
15799
15800                 intel_connector = to_intel_connector(connector);
15801                 intel_connector->unregister(intel_connector);
15802         }
15803
15804         drm_mode_config_cleanup(dev);
15805
15806         intel_cleanup_overlay(dev);
15807
15808         mutex_lock(&dev->struct_mutex);
15809         intel_cleanup_gt_powersave(dev);
15810         mutex_unlock(&dev->struct_mutex);
15811 }
15812
15813 /*
15814  * Return which encoder is currently attached for connector.
15815  */
15816 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15817 {
15818         return &intel_attached_encoder(connector)->base;
15819 }
15820
15821 void intel_connector_attach_encoder(struct intel_connector *connector,
15822                                     struct intel_encoder *encoder)
15823 {
15824         connector->encoder = encoder;
15825         drm_mode_connector_attach_encoder(&connector->base,
15826                                           &encoder->base);
15827 }
15828
15829 /*
15830  * set vga decode state - true == enable VGA decode
15831  */
15832 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15833 {
15834         struct drm_i915_private *dev_priv = dev->dev_private;
15835         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15836         u16 gmch_ctrl;
15837
15838         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15839                 DRM_ERROR("failed to read control word\n");
15840                 return -EIO;
15841         }
15842
15843         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15844                 return 0;
15845
15846         if (state)
15847                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15848         else
15849                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15850
15851         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15852                 DRM_ERROR("failed to write control word\n");
15853                 return -EIO;
15854         }
15855
15856         return 0;
15857 }
15858
15859 struct intel_display_error_state {
15860
15861         u32 power_well_driver;
15862
15863         int num_transcoders;
15864
15865         struct intel_cursor_error_state {
15866                 u32 control;
15867                 u32 position;
15868                 u32 base;
15869                 u32 size;
15870         } cursor[I915_MAX_PIPES];
15871
15872         struct intel_pipe_error_state {
15873                 bool power_domain_on;
15874                 u32 source;
15875                 u32 stat;
15876         } pipe[I915_MAX_PIPES];
15877
15878         struct intel_plane_error_state {
15879                 u32 control;
15880                 u32 stride;
15881                 u32 size;
15882                 u32 pos;
15883                 u32 addr;
15884                 u32 surface;
15885                 u32 tile_offset;
15886         } plane[I915_MAX_PIPES];
15887
15888         struct intel_transcoder_error_state {
15889                 bool power_domain_on;
15890                 enum transcoder cpu_transcoder;
15891
15892                 u32 conf;
15893
15894                 u32 htotal;
15895                 u32 hblank;
15896                 u32 hsync;
15897                 u32 vtotal;
15898                 u32 vblank;
15899                 u32 vsync;
15900         } transcoder[4];
15901 };
15902
15903 struct intel_display_error_state *
15904 intel_display_capture_error_state(struct drm_device *dev)
15905 {
15906         struct drm_i915_private *dev_priv = dev->dev_private;
15907         struct intel_display_error_state *error;
15908         int transcoders[] = {
15909                 TRANSCODER_A,
15910                 TRANSCODER_B,
15911                 TRANSCODER_C,
15912                 TRANSCODER_EDP,
15913         };
15914         int i;
15915
15916         if (INTEL_INFO(dev)->num_pipes == 0)
15917                 return NULL;
15918
15919         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15920         if (error == NULL)
15921                 return NULL;
15922
15923         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15924                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15925
15926         for_each_pipe(dev_priv, i) {
15927                 error->pipe[i].power_domain_on =
15928                         __intel_display_power_is_enabled(dev_priv,
15929                                                          POWER_DOMAIN_PIPE(i));
15930                 if (!error->pipe[i].power_domain_on)
15931                         continue;
15932
15933                 error->cursor[i].control = I915_READ(CURCNTR(i));
15934                 error->cursor[i].position = I915_READ(CURPOS(i));
15935                 error->cursor[i].base = I915_READ(CURBASE(i));
15936
15937                 error->plane[i].control = I915_READ(DSPCNTR(i));
15938                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15939                 if (INTEL_INFO(dev)->gen <= 3) {
15940                         error->plane[i].size = I915_READ(DSPSIZE(i));
15941                         error->plane[i].pos = I915_READ(DSPPOS(i));
15942                 }
15943                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15944                         error->plane[i].addr = I915_READ(DSPADDR(i));
15945                 if (INTEL_INFO(dev)->gen >= 4) {
15946                         error->plane[i].surface = I915_READ(DSPSURF(i));
15947                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15948                 }
15949
15950                 error->pipe[i].source = I915_READ(PIPESRC(i));
15951
15952                 if (HAS_GMCH_DISPLAY(dev))
15953                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15954         }
15955
15956         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15957         if (HAS_DDI(dev_priv->dev))
15958                 error->num_transcoders++; /* Account for eDP. */
15959
15960         for (i = 0; i < error->num_transcoders; i++) {
15961                 enum transcoder cpu_transcoder = transcoders[i];
15962
15963                 error->transcoder[i].power_domain_on =
15964                         __intel_display_power_is_enabled(dev_priv,
15965                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15966                 if (!error->transcoder[i].power_domain_on)
15967                         continue;
15968
15969                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15970
15971                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15972                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15973                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15974                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15975                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15976                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15977                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15978         }
15979
15980         return error;
15981 }
15982
15983 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15984
15985 void
15986 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15987                                 struct drm_device *dev,
15988                                 struct intel_display_error_state *error)
15989 {
15990         struct drm_i915_private *dev_priv = dev->dev_private;
15991         int i;
15992
15993         if (!error)
15994                 return;
15995
15996         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15997         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15998                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15999                            error->power_well_driver);
16000         for_each_pipe(dev_priv, i) {
16001                 err_printf(m, "Pipe [%d]:\n", i);
16002                 err_printf(m, "  Power: %s\n",
16003                            error->pipe[i].power_domain_on ? "on" : "off");
16004                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16005                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16006
16007                 err_printf(m, "Plane [%d]:\n", i);
16008                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16009                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16010                 if (INTEL_INFO(dev)->gen <= 3) {
16011                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16012                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16013                 }
16014                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16015                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16016                 if (INTEL_INFO(dev)->gen >= 4) {
16017                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16018                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16019                 }
16020
16021                 err_printf(m, "Cursor [%d]:\n", i);
16022                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16023                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16024                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16025         }
16026
16027         for (i = 0; i < error->num_transcoders; i++) {
16028                 err_printf(m, "CPU transcoder: %c\n",
16029                            transcoder_name(error->transcoder[i].cpu_transcoder));
16030                 err_printf(m, "  Power: %s\n",
16031                            error->transcoder[i].power_domain_on ? "on" : "off");
16032                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16033                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16034                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16035                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16036                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16037                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16038                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16039         }
16040 }
16041
16042 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16043 {
16044         struct intel_crtc *crtc;
16045
16046         for_each_intel_crtc(dev, crtc) {
16047                 struct intel_unpin_work *work;
16048
16049                 spin_lock_irq(&dev->event_lock);
16050
16051                 work = crtc->unpin_work;
16052
16053                 if (work && work->event &&
16054                     work->event->base.file_priv == file) {
16055                         kfree(work->event);
16056                         work->event = NULL;
16057                 }
16058
16059                 spin_unlock_irq(&dev->event_lock);
16060         }
16061 }