drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 int reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         int pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486                         return false;
1487         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489                         return false;
1490         } else {
1491                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492                         return false;
1493         }
1494         return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498                               enum pipe pipe, u32 val)
1499 {
1500         if ((val & SDVO_ENABLE) == 0)
1501                 return false;
1502
1503         if (HAS_PCH_CPT(dev_priv->dev)) {
1504                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505                         return false;
1506         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508                         return false;
1509         } else {
1510                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511                         return false;
1512         }
1513         return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517                               enum pipe pipe, u32 val)
1518 {
1519         if ((val & LVDS_PORT_EN) == 0)
1520                 return false;
1521
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533                               enum pipe pipe, u32 val)
1534 {
1535         if ((val & ADPA_DAC_ENABLE) == 0)
1536                 return false;
1537         if (HAS_PCH_CPT(dev_priv->dev)) {
1538                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539                         return false;
1540         } else {
1541                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542                         return false;
1543         }
1544         return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548                                    enum pipe pipe, int reg, u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              reg, pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, int reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              reg, pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         int reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /* Wait for the clocks to stabilize. */
1717         POSTING_READ(reg);
1718         udelay(150);
1719
1720         if (INTEL_INFO(dev)->gen >= 4) {
1721                 I915_WRITE(DPLL_MD(crtc->pipe),
1722                            crtc->config->dpll_hw_state.dpll_md);
1723         } else {
1724                 /* The pixel multiplier can only be updated once the
1725                  * DPLL is enabled and the clocks are stable.
1726                  *
1727                  * So write it again.
1728                  */
1729                 I915_WRITE(reg, dpll);
1730         }
1731
1732         /* We do this three times for luck */
1733         I915_WRITE(reg, dpll);
1734         POSTING_READ(reg);
1735         udelay(150); /* wait for warmup */
1736         I915_WRITE(reg, dpll);
1737         POSTING_READ(reg);
1738         udelay(150); /* wait for warmup */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745  * i9xx_disable_pll - disable a PLL
1746  * @dev_priv: i915 private structure
1747  * @pipe: pipe PLL to disable
1748  *
1749  * Disable the PLL for @pipe, making sure the pipe is off first.
1750  *
1751  * Note!  This is for pre-ILK only.
1752  */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755         struct drm_device *dev = crtc->base.dev;
1756         struct drm_i915_private *dev_priv = dev->dev_private;
1757         enum pipe pipe = crtc->pipe;
1758
1759         /* Disable DVO 2x clock on both PLLs if necessary */
1760         if (IS_I830(dev) &&
1761             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762             !intel_num_dvo_pipes(dev)) {
1763                 I915_WRITE(DPLL(PIPE_B),
1764                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765                 I915_WRITE(DPLL(PIPE_A),
1766                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767         }
1768
1769         /* Don't disable pipe or pipe PLLs if needed */
1770         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772                 return;
1773
1774         /* Make sure the pipe isn't still relying on us */
1775         assert_pipe_disabled(dev_priv, pipe);
1776
1777         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778         POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783         u32 val;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         /*
1789          * Leave integrated clock source and reference clock enabled for pipe B.
1790          * The latter is needed for VGA hotplug / manual detection.
1791          */
1792         val = DPLL_VGA_MODE_DIS;
1793         if (pipe == PIPE_B)
1794                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795         I915_WRITE(DPLL(pipe), val);
1796         POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803         u32 val;
1804
1805         /* Make sure the pipe isn't still relying on us */
1806         assert_pipe_disabled(dev_priv, pipe);
1807
1808         /* Set PLL en = 0 */
1809         val = DPLL_SSC_REF_CLK_CHV |
1810                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811         if (pipe != PIPE_A)
1812                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813         I915_WRITE(DPLL(pipe), val);
1814         POSTING_READ(DPLL(pipe));
1815
1816         mutex_lock(&dev_priv->sb_lock);
1817
1818         /* Disable 10bit clock to display controller */
1819         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820         val &= ~DPIO_DCLKP_EN;
1821         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823         mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827                          struct intel_digital_port *dport,
1828                          unsigned int expected_mask)
1829 {
1830         u32 port_mask;
1831         int dpll_reg;
1832
1833         switch (dport->port) {
1834         case PORT_B:
1835                 port_mask = DPLL_PORTB_READY_MASK;
1836                 dpll_reg = DPLL(0);
1837                 break;
1838         case PORT_C:
1839                 port_mask = DPLL_PORTC_READY_MASK;
1840                 dpll_reg = DPLL(0);
1841                 expected_mask <<= 4;
1842                 break;
1843         case PORT_D:
1844                 port_mask = DPLL_PORTD_READY_MASK;
1845                 dpll_reg = DPIO_PHY_STATUS;
1846                 break;
1847         default:
1848                 BUG();
1849         }
1850
1851         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858         struct drm_device *dev = crtc->base.dev;
1859         struct drm_i915_private *dev_priv = dev->dev_private;
1860         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862         if (WARN_ON(pll == NULL))
1863                 return;
1864
1865         WARN_ON(!pll->config.crtc_mask);
1866         if (pll->active == 0) {
1867                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868                 WARN_ON(pll->on);
1869                 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871                 pll->mode_set(dev_priv, pll);
1872         }
1873 }
1874
1875 /**
1876  * intel_enable_shared_dpll - enable PCH PLL
1877  * @dev_priv: i915 private structure
1878  * @pipe: pipe PLL to enable
1879  *
1880  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881  * drives the transcoder clock.
1882  */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885         struct drm_device *dev = crtc->base.dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889         if (WARN_ON(pll == NULL))
1890                 return;
1891
1892         if (WARN_ON(pll->config.crtc_mask == 0))
1893                 return;
1894
1895         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896                       pll->name, pll->active, pll->on,
1897                       crtc->base.base.id);
1898
1899         if (pll->active++) {
1900                 WARN_ON(!pll->on);
1901                 assert_shared_dpll_enabled(dev_priv, pll);
1902                 return;
1903         }
1904         WARN_ON(pll->on);
1905
1906         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909         pll->enable(dev_priv, pll);
1910         pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915         struct drm_device *dev = crtc->base.dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919         /* PCH only available on ILK+ */
1920         if (INTEL_INFO(dev)->gen < 5)
1921                 return;
1922
1923         if (pll == NULL)
1924                 return;
1925
1926         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927                 return;
1928
1929         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930                       pll->name, pll->active, pll->on,
1931                       crtc->base.base.id);
1932
1933         if (WARN_ON(pll->active == 0)) {
1934                 assert_shared_dpll_disabled(dev_priv, pll);
1935                 return;
1936         }
1937
1938         assert_shared_dpll_enabled(dev_priv, pll);
1939         WARN_ON(!pll->on);
1940         if (--pll->active)
1941                 return;
1942
1943         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944         pll->disable(dev_priv, pll);
1945         pll->on = false;
1946
1947         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951                                            enum pipe pipe)
1952 {
1953         struct drm_device *dev = dev_priv->dev;
1954         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956         uint32_t reg, val, pipeconf_val;
1957
1958         /* PCH only available on ILK+ */
1959         BUG_ON(!HAS_PCH_SPLIT(dev));
1960
1961         /* Make sure PCH DPLL is enabled */
1962         assert_shared_dpll_enabled(dev_priv,
1963                                    intel_crtc_to_shared_dpll(intel_crtc));
1964
1965         /* FDI must be feeding us bits for PCH ports */
1966         assert_fdi_tx_enabled(dev_priv, pipe);
1967         assert_fdi_rx_enabled(dev_priv, pipe);
1968
1969         if (HAS_PCH_CPT(dev)) {
1970                 /* Workaround: Set the timing override bit before enabling the
1971                  * pch transcoder. */
1972                 reg = TRANS_CHICKEN2(pipe);
1973                 val = I915_READ(reg);
1974                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975                 I915_WRITE(reg, val);
1976         }
1977
1978         reg = PCH_TRANSCONF(pipe);
1979         val = I915_READ(reg);
1980         pipeconf_val = I915_READ(PIPECONF(pipe));
1981
1982         if (HAS_PCH_IBX(dev_priv->dev)) {
1983                 /*
1984                  * Make the BPC in transcoder be consistent with
1985                  * that in pipeconf reg. For HDMI we must use 8bpc
1986                  * here for both 8bpc and 12bpc.
1987                  */
1988                 val &= ~PIPECONF_BPC_MASK;
1989                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990                         val |= PIPECONF_8BPC;
1991                 else
1992                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1993         }
1994
1995         val &= ~TRANS_INTERLACE_MASK;
1996         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1997                 if (HAS_PCH_IBX(dev_priv->dev) &&
1998                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1999                         val |= TRANS_LEGACY_INTERLACED_ILK;
2000                 else
2001                         val |= TRANS_INTERLACED;
2002         else
2003                 val |= TRANS_PROGRESSIVE;
2004
2005         I915_WRITE(reg, val | TRANS_ENABLE);
2006         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2007                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2008 }
2009
2010 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2011                                       enum transcoder cpu_transcoder)
2012 {
2013         u32 val, pipeconf_val;
2014
2015         /* PCH only available on ILK+ */
2016         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2017
2018         /* FDI must be feeding us bits for PCH ports */
2019         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2020         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2021
2022         /* Workaround: set timing override bit. */
2023         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2024         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2025         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2026
2027         val = TRANS_ENABLE;
2028         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2029
2030         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031             PIPECONF_INTERLACED_ILK)
2032                 val |= TRANS_INTERLACED;
2033         else
2034                 val |= TRANS_PROGRESSIVE;
2035
2036         I915_WRITE(LPT_TRANSCONF, val);
2037         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2038                 DRM_ERROR("Failed to enable PCH transcoder\n");
2039 }
2040
2041 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042                                             enum pipe pipe)
2043 {
2044         struct drm_device *dev = dev_priv->dev;
2045         uint32_t reg, val;
2046
2047         /* FDI relies on the transcoder */
2048         assert_fdi_tx_disabled(dev_priv, pipe);
2049         assert_fdi_rx_disabled(dev_priv, pipe);
2050
2051         /* Ports must be off as well */
2052         assert_pch_ports_disabled(dev_priv, pipe);
2053
2054         reg = PCH_TRANSCONF(pipe);
2055         val = I915_READ(reg);
2056         val &= ~TRANS_ENABLE;
2057         I915_WRITE(reg, val);
2058         /* wait for PCH transcoder off, transcoder state */
2059         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2060                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2061
2062         if (!HAS_PCH_IBX(dev)) {
2063                 /* Workaround: Clear the timing override chicken bit again. */
2064                 reg = TRANS_CHICKEN2(pipe);
2065                 val = I915_READ(reg);
2066                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067                 I915_WRITE(reg, val);
2068         }
2069 }
2070
2071 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2072 {
2073         u32 val;
2074
2075         val = I915_READ(LPT_TRANSCONF);
2076         val &= ~TRANS_ENABLE;
2077         I915_WRITE(LPT_TRANSCONF, val);
2078         /* wait for PCH transcoder off, transcoder state */
2079         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2080                 DRM_ERROR("Failed to disable PCH transcoder\n");
2081
2082         /* Workaround: clear timing override bit. */
2083         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2084         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2086 }
2087
2088 /**
2089  * intel_enable_pipe - enable a pipe, asserting requirements
2090  * @crtc: crtc responsible for the pipe
2091  *
2092  * Enable @crtc's pipe, making sure that various hardware specific requirements
2093  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2094  */
2095 static void intel_enable_pipe(struct intel_crtc *crtc)
2096 {
2097         struct drm_device *dev = crtc->base.dev;
2098         struct drm_i915_private *dev_priv = dev->dev_private;
2099         enum pipe pipe = crtc->pipe;
2100         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2101                                                                       pipe);
2102         enum pipe pch_transcoder;
2103         int reg;
2104         u32 val;
2105
2106         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2107
2108         assert_planes_disabled(dev_priv, pipe);
2109         assert_cursor_disabled(dev_priv, pipe);
2110         assert_sprites_disabled(dev_priv, pipe);
2111
2112         if (HAS_PCH_LPT(dev_priv->dev))
2113                 pch_transcoder = TRANSCODER_A;
2114         else
2115                 pch_transcoder = pipe;
2116
2117         /*
2118          * A pipe without a PLL won't actually be able to drive bits from
2119          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2120          * need the check.
2121          */
2122         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2123                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2124                         assert_dsi_pll_enabled(dev_priv);
2125                 else
2126                         assert_pll_enabled(dev_priv, pipe);
2127         else {
2128                 if (crtc->config->has_pch_encoder) {
2129                         /* if driving the PCH, we need FDI enabled */
2130                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2131                         assert_fdi_tx_pll_enabled(dev_priv,
2132                                                   (enum pipe) cpu_transcoder);
2133                 }
2134                 /* FIXME: assert CPU port conditions for SNB+ */
2135         }
2136
2137         reg = PIPECONF(cpu_transcoder);
2138         val = I915_READ(reg);
2139         if (val & PIPECONF_ENABLE) {
2140                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2141                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2142                 return;
2143         }
2144
2145         I915_WRITE(reg, val | PIPECONF_ENABLE);
2146         POSTING_READ(reg);
2147 }
2148
2149 /**
2150  * intel_disable_pipe - disable a pipe, asserting requirements
2151  * @crtc: crtc whose pipes is to be disabled
2152  *
2153  * Disable the pipe of @crtc, making sure that various hardware
2154  * specific requirements are met, if applicable, e.g. plane
2155  * disabled, panel fitter off, etc.
2156  *
2157  * Will wait until the pipe has shut down before returning.
2158  */
2159 static void intel_disable_pipe(struct intel_crtc *crtc)
2160 {
2161         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2162         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2163         enum pipe pipe = crtc->pipe;
2164         int reg;
2165         u32 val;
2166
2167         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2168
2169         /*
2170          * Make sure planes won't keep trying to pump pixels to us,
2171          * or we might hang the display.
2172          */
2173         assert_planes_disabled(dev_priv, pipe);
2174         assert_cursor_disabled(dev_priv, pipe);
2175         assert_sprites_disabled(dev_priv, pipe);
2176
2177         reg = PIPECONF(cpu_transcoder);
2178         val = I915_READ(reg);
2179         if ((val & PIPECONF_ENABLE) == 0)
2180                 return;
2181
2182         /*
2183          * Double wide has implications for planes
2184          * so best keep it disabled when not needed.
2185          */
2186         if (crtc->config->double_wide)
2187                 val &= ~PIPECONF_DOUBLE_WIDE;
2188
2189         /* Don't disable pipe or pipe PLLs if needed */
2190         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2191             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2192                 val &= ~PIPECONF_ENABLE;
2193
2194         I915_WRITE(reg, val);
2195         if ((val & PIPECONF_ENABLE) == 0)
2196                 intel_wait_for_pipe_off(crtc);
2197 }
2198
2199 static bool need_vtd_wa(struct drm_device *dev)
2200 {
2201 #ifdef CONFIG_INTEL_IOMMU
2202         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2203                 return true;
2204 #endif
2205         return false;
2206 }
2207
2208 unsigned int
2209 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2210                   uint64_t fb_format_modifier, unsigned int plane)
2211 {
2212         unsigned int tile_height;
2213         uint32_t pixel_bytes;
2214
2215         switch (fb_format_modifier) {
2216         case DRM_FORMAT_MOD_NONE:
2217                 tile_height = 1;
2218                 break;
2219         case I915_FORMAT_MOD_X_TILED:
2220                 tile_height = IS_GEN2(dev) ? 16 : 8;
2221                 break;
2222         case I915_FORMAT_MOD_Y_TILED:
2223                 tile_height = 32;
2224                 break;
2225         case I915_FORMAT_MOD_Yf_TILED:
2226                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2227                 switch (pixel_bytes) {
2228                 default:
2229                 case 1:
2230                         tile_height = 64;
2231                         break;
2232                 case 2:
2233                 case 4:
2234                         tile_height = 32;
2235                         break;
2236                 case 8:
2237                         tile_height = 16;
2238                         break;
2239                 case 16:
2240                         WARN_ONCE(1,
2241                                   "128-bit pixels are not supported for display!");
2242                         tile_height = 16;
2243                         break;
2244                 }
2245                 break;
2246         default:
2247                 MISSING_CASE(fb_format_modifier);
2248                 tile_height = 1;
2249                 break;
2250         }
2251
2252         return tile_height;
2253 }
2254
2255 unsigned int
2256 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2257                       uint32_t pixel_format, uint64_t fb_format_modifier)
2258 {
2259         return ALIGN(height, intel_tile_height(dev, pixel_format,
2260                                                fb_format_modifier, 0));
2261 }
2262
2263 static int
2264 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2265                         const struct drm_plane_state *plane_state)
2266 {
2267         struct intel_rotation_info *info = &view->rotation_info;
2268         unsigned int tile_height, tile_pitch;
2269
2270         *view = i915_ggtt_view_normal;
2271
2272         if (!plane_state)
2273                 return 0;
2274
2275         if (!intel_rotation_90_or_270(plane_state->rotation))
2276                 return 0;
2277
2278         *view = i915_ggtt_view_rotated;
2279
2280         info->height = fb->height;
2281         info->pixel_format = fb->pixel_format;
2282         info->pitch = fb->pitches[0];
2283         info->uv_offset = fb->offsets[1];
2284         info->fb_modifier = fb->modifier[0];
2285
2286         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2287                                         fb->modifier[0], 0);
2288         tile_pitch = PAGE_SIZE / tile_height;
2289         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2290         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2291         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2292
2293         if (info->pixel_format == DRM_FORMAT_NV12) {
2294                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295                                                 fb->modifier[0], 1);
2296                 tile_pitch = PAGE_SIZE / tile_height;
2297                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2299                                                      tile_height);
2300                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2301                                 PAGE_SIZE;
2302         }
2303
2304         return 0;
2305 }
2306
2307 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2308 {
2309         if (INTEL_INFO(dev_priv)->gen >= 9)
2310                 return 256 * 1024;
2311         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2312                  IS_VALLEYVIEW(dev_priv))
2313                 return 128 * 1024;
2314         else if (INTEL_INFO(dev_priv)->gen >= 4)
2315                 return 4 * 1024;
2316         else
2317                 return 0;
2318 }
2319
2320 int
2321 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2322                            struct drm_framebuffer *fb,
2323                            const struct drm_plane_state *plane_state,
2324                            struct intel_engine_cs *pipelined,
2325                            struct drm_i915_gem_request **pipelined_request)
2326 {
2327         struct drm_device *dev = fb->dev;
2328         struct drm_i915_private *dev_priv = dev->dev_private;
2329         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2330         struct i915_ggtt_view view;
2331         u32 alignment;
2332         int ret;
2333
2334         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2335
2336         switch (fb->modifier[0]) {
2337         case DRM_FORMAT_MOD_NONE:
2338                 alignment = intel_linear_alignment(dev_priv);
2339                 break;
2340         case I915_FORMAT_MOD_X_TILED:
2341                 if (INTEL_INFO(dev)->gen >= 9)
2342                         alignment = 256 * 1024;
2343                 else {
2344                         /* pin() will align the object as required by fence */
2345                         alignment = 0;
2346                 }
2347                 break;
2348         case I915_FORMAT_MOD_Y_TILED:
2349         case I915_FORMAT_MOD_Yf_TILED:
2350                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2351                           "Y tiling bo slipped through, driver bug!\n"))
2352                         return -EINVAL;
2353                 alignment = 1 * 1024 * 1024;
2354                 break;
2355         default:
2356                 MISSING_CASE(fb->modifier[0]);
2357                 return -EINVAL;
2358         }
2359
2360         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2361         if (ret)
2362                 return ret;
2363
2364         /* Note that the w/a also requires 64 PTE of padding following the
2365          * bo. We currently fill all unused PTE with the shadow page and so
2366          * we should always have valid PTE following the scanout preventing
2367          * the VT-d warning.
2368          */
2369         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2370                 alignment = 256 * 1024;
2371
2372         /*
2373          * Global gtt pte registers are special registers which actually forward
2374          * writes to a chunk of system memory. Which means that there is no risk
2375          * that the register values disappear as soon as we call
2376          * intel_runtime_pm_put(), so it is correct to wrap only the
2377          * pin/unpin/fence and not more.
2378          */
2379         intel_runtime_pm_get(dev_priv);
2380
2381         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2382                                                    pipelined_request, &view);
2383         if (ret)
2384                 goto err_pm;
2385
2386         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2387          * fence, whereas 965+ only requires a fence if using
2388          * framebuffer compression.  For simplicity, we always install
2389          * a fence as the cost is not that onerous.
2390          */
2391         ret = i915_gem_object_get_fence(obj);
2392         if (ret == -EDEADLK) {
2393                 /*
2394                  * -EDEADLK means there are no free fences
2395                  * no pending flips.
2396                  *
2397                  * This is propagated to atomic, but it uses
2398                  * -EDEADLK to force a locking recovery, so
2399                  * change the returned error to -EBUSY.
2400                  */
2401                 ret = -EBUSY;
2402                 goto err_unpin;
2403         } else if (ret)
2404                 goto err_unpin;
2405
2406         i915_gem_object_pin_fence(obj);
2407
2408         intel_runtime_pm_put(dev_priv);
2409         return 0;
2410
2411 err_unpin:
2412         i915_gem_object_unpin_from_display_plane(obj, &view);
2413 err_pm:
2414         intel_runtime_pm_put(dev_priv);
2415         return ret;
2416 }
2417
2418 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2419                                const struct drm_plane_state *plane_state)
2420 {
2421         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2422         struct i915_ggtt_view view;
2423         int ret;
2424
2425         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2426
2427         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2428         WARN_ONCE(ret, "Couldn't get view from plane state!");
2429
2430         i915_gem_object_unpin_fence(obj);
2431         i915_gem_object_unpin_from_display_plane(obj, &view);
2432 }
2433
2434 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2435  * is assumed to be a power-of-two. */
2436 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2437                                              int *x, int *y,
2438                                              unsigned int tiling_mode,
2439                                              unsigned int cpp,
2440                                              unsigned int pitch)
2441 {
2442         if (tiling_mode != I915_TILING_NONE) {
2443                 unsigned int tile_rows, tiles;
2444
2445                 tile_rows = *y / 8;
2446                 *y %= 8;
2447
2448                 tiles = *x / (512/cpp);
2449                 *x %= 512/cpp;
2450
2451                 return tile_rows * pitch * 8 + tiles * 4096;
2452         } else {
2453                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2454                 unsigned int offset;
2455
2456                 offset = *y * pitch + *x * cpp;
2457                 *y = (offset & alignment) / pitch;
2458                 *x = ((offset & alignment) - *y * pitch) / cpp;
2459                 return offset & ~alignment;
2460         }
2461 }
2462
2463 static int i9xx_format_to_fourcc(int format)
2464 {
2465         switch (format) {
2466         case DISPPLANE_8BPP:
2467                 return DRM_FORMAT_C8;
2468         case DISPPLANE_BGRX555:
2469                 return DRM_FORMAT_XRGB1555;
2470         case DISPPLANE_BGRX565:
2471                 return DRM_FORMAT_RGB565;
2472         default:
2473         case DISPPLANE_BGRX888:
2474                 return DRM_FORMAT_XRGB8888;
2475         case DISPPLANE_RGBX888:
2476                 return DRM_FORMAT_XBGR8888;
2477         case DISPPLANE_BGRX101010:
2478                 return DRM_FORMAT_XRGB2101010;
2479         case DISPPLANE_RGBX101010:
2480                 return DRM_FORMAT_XBGR2101010;
2481         }
2482 }
2483
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485 {
2486         switch (format) {
2487         case PLANE_CTL_FORMAT_RGB_565:
2488                 return DRM_FORMAT_RGB565;
2489         default:
2490         case PLANE_CTL_FORMAT_XRGB_8888:
2491                 if (rgb_order) {
2492                         if (alpha)
2493                                 return DRM_FORMAT_ABGR8888;
2494                         else
2495                                 return DRM_FORMAT_XBGR8888;
2496                 } else {
2497                         if (alpha)
2498                                 return DRM_FORMAT_ARGB8888;
2499                         else
2500                                 return DRM_FORMAT_XRGB8888;
2501                 }
2502         case PLANE_CTL_FORMAT_XRGB_2101010:
2503                 if (rgb_order)
2504                         return DRM_FORMAT_XBGR2101010;
2505                 else
2506                         return DRM_FORMAT_XRGB2101010;
2507         }
2508 }
2509
2510 static bool
2511 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512                               struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = crtc->base.dev;
2515         struct drm_i915_private *dev_priv = to_i915(dev);
2516         struct drm_i915_gem_object *obj = NULL;
2517         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2518         struct drm_framebuffer *fb = &plane_config->fb->base;
2519         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2520         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2521                                     PAGE_SIZE);
2522
2523         size_aligned -= base_aligned;
2524
2525         if (plane_config->size == 0)
2526                 return false;
2527
2528         /* If the FB is too big, just don't use it since fbdev is not very
2529          * important and we should probably use that space with FBC or other
2530          * features. */
2531         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2532                 return false;
2533
2534         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2535                                                              base_aligned,
2536                                                              base_aligned,
2537                                                              size_aligned);
2538         if (!obj)
2539                 return false;
2540
2541         obj->tiling_mode = plane_config->tiling;
2542         if (obj->tiling_mode == I915_TILING_X)
2543                 obj->stride = fb->pitches[0];
2544
2545         mode_cmd.pixel_format = fb->pixel_format;
2546         mode_cmd.width = fb->width;
2547         mode_cmd.height = fb->height;
2548         mode_cmd.pitches[0] = fb->pitches[0];
2549         mode_cmd.modifier[0] = fb->modifier[0];
2550         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2551
2552         mutex_lock(&dev->struct_mutex);
2553         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2554                                    &mode_cmd, obj)) {
2555                 DRM_DEBUG_KMS("intel fb init failed\n");
2556                 goto out_unref_obj;
2557         }
2558         mutex_unlock(&dev->struct_mutex);
2559
2560         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2561         return true;
2562
2563 out_unref_obj:
2564         drm_gem_object_unreference(&obj->base);
2565         mutex_unlock(&dev->struct_mutex);
2566         return false;
2567 }
2568
2569 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2570 static void
2571 update_state_fb(struct drm_plane *plane)
2572 {
2573         if (plane->fb == plane->state->fb)
2574                 return;
2575
2576         if (plane->state->fb)
2577                 drm_framebuffer_unreference(plane->state->fb);
2578         plane->state->fb = plane->fb;
2579         if (plane->state->fb)
2580                 drm_framebuffer_reference(plane->state->fb);
2581 }
2582
2583 static void
2584 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2585                              struct intel_initial_plane_config *plane_config)
2586 {
2587         struct drm_device *dev = intel_crtc->base.dev;
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589         struct drm_crtc *c;
2590         struct intel_crtc *i;
2591         struct drm_i915_gem_object *obj;
2592         struct drm_plane *primary = intel_crtc->base.primary;
2593         struct drm_plane_state *plane_state = primary->state;
2594         struct drm_framebuffer *fb;
2595
2596         if (!plane_config->fb)
2597                 return;
2598
2599         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2600                 fb = &plane_config->fb->base;
2601                 goto valid_fb;
2602         }
2603
2604         kfree(plane_config->fb);
2605
2606         /*
2607          * Failed to alloc the obj, check to see if we should share
2608          * an fb with another CRTC instead
2609          */
2610         for_each_crtc(dev, c) {
2611                 i = to_intel_crtc(c);
2612
2613                 if (c == &intel_crtc->base)
2614                         continue;
2615
2616                 if (!i->active)
2617                         continue;
2618
2619                 fb = c->primary->fb;
2620                 if (!fb)
2621                         continue;
2622
2623                 obj = intel_fb_obj(fb);
2624                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2625                         drm_framebuffer_reference(fb);
2626                         goto valid_fb;
2627                 }
2628         }
2629
2630         return;
2631
2632 valid_fb:
2633         plane_state->src_x = plane_state->src_y = 0;
2634         plane_state->src_w = fb->width << 16;
2635         plane_state->src_h = fb->height << 16;
2636
2637         plane_state->crtc_x = plane_state->src_y = 0;
2638         plane_state->crtc_w = fb->width;
2639         plane_state->crtc_h = fb->height;
2640
2641         obj = intel_fb_obj(fb);
2642         if (obj->tiling_mode != I915_TILING_NONE)
2643                 dev_priv->preserve_bios_swizzle = true;
2644
2645         drm_framebuffer_reference(fb);
2646         primary->fb = primary->state->fb = fb;
2647         primary->crtc = primary->state->crtc = &intel_crtc->base;
2648         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2649         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2650 }
2651
2652 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653                                       struct drm_framebuffer *fb,
2654                                       int x, int y)
2655 {
2656         struct drm_device *dev = crtc->dev;
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2659         struct drm_plane *primary = crtc->primary;
2660         bool visible = to_intel_plane_state(primary->state)->visible;
2661         struct drm_i915_gem_object *obj;
2662         int plane = intel_crtc->plane;
2663         unsigned long linear_offset;
2664         u32 dspcntr;
2665         u32 reg = DSPCNTR(plane);
2666         int pixel_size;
2667
2668         if (!visible || !fb) {
2669                 I915_WRITE(reg, 0);
2670                 if (INTEL_INFO(dev)->gen >= 4)
2671                         I915_WRITE(DSPSURF(plane), 0);
2672                 else
2673                         I915_WRITE(DSPADDR(plane), 0);
2674                 POSTING_READ(reg);
2675                 return;
2676         }
2677
2678         obj = intel_fb_obj(fb);
2679         if (WARN_ON(obj == NULL))
2680                 return;
2681
2682         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
2684         dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
2686         dspcntr |= DISPLAY_PLANE_ENABLE;
2687
2688         if (INTEL_INFO(dev)->gen < 4) {
2689                 if (intel_crtc->pipe == PIPE_B)
2690                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692                 /* pipesrc and dspsize control the size that is scaled from,
2693                  * which should always be the user's requested size.
2694                  */
2695                 I915_WRITE(DSPSIZE(plane),
2696                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697                            (intel_crtc->config->pipe_src_w - 1));
2698                 I915_WRITE(DSPPOS(plane), 0);
2699         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700                 I915_WRITE(PRIMSIZE(plane),
2701                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702                            (intel_crtc->config->pipe_src_w - 1));
2703                 I915_WRITE(PRIMPOS(plane), 0);
2704                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2705         }
2706
2707         switch (fb->pixel_format) {
2708         case DRM_FORMAT_C8:
2709                 dspcntr |= DISPPLANE_8BPP;
2710                 break;
2711         case DRM_FORMAT_XRGB1555:
2712                 dspcntr |= DISPPLANE_BGRX555;
2713                 break;
2714         case DRM_FORMAT_RGB565:
2715                 dspcntr |= DISPPLANE_BGRX565;
2716                 break;
2717         case DRM_FORMAT_XRGB8888:
2718                 dspcntr |= DISPPLANE_BGRX888;
2719                 break;
2720         case DRM_FORMAT_XBGR8888:
2721                 dspcntr |= DISPPLANE_RGBX888;
2722                 break;
2723         case DRM_FORMAT_XRGB2101010:
2724                 dspcntr |= DISPPLANE_BGRX101010;
2725                 break;
2726         case DRM_FORMAT_XBGR2101010:
2727                 dspcntr |= DISPPLANE_RGBX101010;
2728                 break;
2729         default:
2730                 BUG();
2731         }
2732
2733         if (INTEL_INFO(dev)->gen >= 4 &&
2734             obj->tiling_mode != I915_TILING_NONE)
2735                 dspcntr |= DISPPLANE_TILED;
2736
2737         if (IS_G4X(dev))
2738                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
2740         linear_offset = y * fb->pitches[0] + x * pixel_size;
2741
2742         if (INTEL_INFO(dev)->gen >= 4) {
2743                 intel_crtc->dspaddr_offset =
2744                         intel_gen4_compute_page_offset(dev_priv,
2745                                                        &x, &y, obj->tiling_mode,
2746                                                        pixel_size,
2747                                                        fb->pitches[0]);
2748                 linear_offset -= intel_crtc->dspaddr_offset;
2749         } else {
2750                 intel_crtc->dspaddr_offset = linear_offset;
2751         }
2752
2753         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2754                 dspcntr |= DISPPLANE_ROTATE_180;
2755
2756                 x += (intel_crtc->config->pipe_src_w - 1);
2757                 y += (intel_crtc->config->pipe_src_h - 1);
2758
2759                 /* Finding the last pixel of the last line of the display
2760                 data and adding to linear_offset*/
2761                 linear_offset +=
2762                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2764         }
2765
2766         intel_crtc->adjusted_x = x;
2767         intel_crtc->adjusted_y = y;
2768
2769         I915_WRITE(reg, dspcntr);
2770
2771         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2772         if (INTEL_INFO(dev)->gen >= 4) {
2773                 I915_WRITE(DSPSURF(plane),
2774                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2775                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2776                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2777         } else
2778                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2779         POSTING_READ(reg);
2780 }
2781
2782 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783                                           struct drm_framebuffer *fb,
2784                                           int x, int y)
2785 {
2786         struct drm_device *dev = crtc->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789         struct drm_plane *primary = crtc->primary;
2790         bool visible = to_intel_plane_state(primary->state)->visible;
2791         struct drm_i915_gem_object *obj;
2792         int plane = intel_crtc->plane;
2793         unsigned long linear_offset;
2794         u32 dspcntr;
2795         u32 reg = DSPCNTR(plane);
2796         int pixel_size;
2797
2798         if (!visible || !fb) {
2799                 I915_WRITE(reg, 0);
2800                 I915_WRITE(DSPSURF(plane), 0);
2801                 POSTING_READ(reg);
2802                 return;
2803         }
2804
2805         obj = intel_fb_obj(fb);
2806         if (WARN_ON(obj == NULL))
2807                 return;
2808
2809         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
2811         dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
2813         dspcntr |= DISPLAY_PLANE_ENABLE;
2814
2815         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2817
2818         switch (fb->pixel_format) {
2819         case DRM_FORMAT_C8:
2820                 dspcntr |= DISPPLANE_8BPP;
2821                 break;
2822         case DRM_FORMAT_RGB565:
2823                 dspcntr |= DISPPLANE_BGRX565;
2824                 break;
2825         case DRM_FORMAT_XRGB8888:
2826                 dspcntr |= DISPPLANE_BGRX888;
2827                 break;
2828         case DRM_FORMAT_XBGR8888:
2829                 dspcntr |= DISPPLANE_RGBX888;
2830                 break;
2831         case DRM_FORMAT_XRGB2101010:
2832                 dspcntr |= DISPPLANE_BGRX101010;
2833                 break;
2834         case DRM_FORMAT_XBGR2101010:
2835                 dspcntr |= DISPPLANE_RGBX101010;
2836                 break;
2837         default:
2838                 BUG();
2839         }
2840
2841         if (obj->tiling_mode != I915_TILING_NONE)
2842                 dspcntr |= DISPPLANE_TILED;
2843
2844         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2845                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2846
2847         linear_offset = y * fb->pitches[0] + x * pixel_size;
2848         intel_crtc->dspaddr_offset =
2849                 intel_gen4_compute_page_offset(dev_priv,
2850                                                &x, &y, obj->tiling_mode,
2851                                                pixel_size,
2852                                                fb->pitches[0]);
2853         linear_offset -= intel_crtc->dspaddr_offset;
2854         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2855                 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2858                         x += (intel_crtc->config->pipe_src_w - 1);
2859                         y += (intel_crtc->config->pipe_src_h - 1);
2860
2861                         /* Finding the last pixel of the last line of the display
2862                         data and adding to linear_offset*/
2863                         linear_offset +=
2864                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2866                 }
2867         }
2868
2869         intel_crtc->adjusted_x = x;
2870         intel_crtc->adjusted_y = y;
2871
2872         I915_WRITE(reg, dspcntr);
2873
2874         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2875         I915_WRITE(DSPSURF(plane),
2876                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2877         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2878                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2879         } else {
2880                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2881                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2882         }
2883         POSTING_READ(reg);
2884 }
2885
2886 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2887                               uint32_t pixel_format)
2888 {
2889         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2890
2891         /*
2892          * The stride is either expressed as a multiple of 64 bytes
2893          * chunks for linear buffers or in number of tiles for tiled
2894          * buffers.
2895          */
2896         switch (fb_modifier) {
2897         case DRM_FORMAT_MOD_NONE:
2898                 return 64;
2899         case I915_FORMAT_MOD_X_TILED:
2900                 if (INTEL_INFO(dev)->gen == 2)
2901                         return 128;
2902                 return 512;
2903         case I915_FORMAT_MOD_Y_TILED:
2904                 /* No need to check for old gens and Y tiling since this is
2905                  * about the display engine and those will be blocked before
2906                  * we get here.
2907                  */
2908                 return 128;
2909         case I915_FORMAT_MOD_Yf_TILED:
2910                 if (bits_per_pixel == 8)
2911                         return 64;
2912                 else
2913                         return 128;
2914         default:
2915                 MISSING_CASE(fb_modifier);
2916                 return 64;
2917         }
2918 }
2919
2920 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2921                                      struct drm_i915_gem_object *obj,
2922                                      unsigned int plane)
2923 {
2924         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2925         struct i915_vma *vma;
2926         unsigned char *offset;
2927
2928         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2929                 view = &i915_ggtt_view_rotated;
2930
2931         vma = i915_gem_obj_to_ggtt_view(obj, view);
2932         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2933                 view->type))
2934                 return -1;
2935
2936         offset = (unsigned char *)vma->node.start;
2937
2938         if (plane == 1) {
2939                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2940                           PAGE_SIZE;
2941         }
2942
2943         return (unsigned long)offset;
2944 }
2945
2946 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2947 {
2948         struct drm_device *dev = intel_crtc->base.dev;
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2952         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2953         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2954 }
2955
2956 /*
2957  * This function detaches (aka. unbinds) unused scalers in hardware
2958  */
2959 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2960 {
2961         struct intel_crtc_scaler_state *scaler_state;
2962         int i;
2963
2964         scaler_state = &intel_crtc->config->scaler_state;
2965
2966         /* loop through and disable scalers that aren't in use */
2967         for (i = 0; i < intel_crtc->num_scalers; i++) {
2968                 if (!scaler_state->scalers[i].in_use)
2969                         skl_detach_scaler(intel_crtc, i);
2970         }
2971 }
2972
2973 u32 skl_plane_ctl_format(uint32_t pixel_format)
2974 {
2975         switch (pixel_format) {
2976         case DRM_FORMAT_C8:
2977                 return PLANE_CTL_FORMAT_INDEXED;
2978         case DRM_FORMAT_RGB565:
2979                 return PLANE_CTL_FORMAT_RGB_565;
2980         case DRM_FORMAT_XBGR8888:
2981                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2982         case DRM_FORMAT_XRGB8888:
2983                 return PLANE_CTL_FORMAT_XRGB_8888;
2984         /*
2985          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2986          * to be already pre-multiplied. We need to add a knob (or a different
2987          * DRM_FORMAT) for user-space to configure that.
2988          */
2989         case DRM_FORMAT_ABGR8888:
2990                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2991                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2992         case DRM_FORMAT_ARGB8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888 |
2994                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2995         case DRM_FORMAT_XRGB2101010:
2996                 return PLANE_CTL_FORMAT_XRGB_2101010;
2997         case DRM_FORMAT_XBGR2101010:
2998                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2999         case DRM_FORMAT_YUYV:
3000                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3001         case DRM_FORMAT_YVYU:
3002                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3003         case DRM_FORMAT_UYVY:
3004                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3005         case DRM_FORMAT_VYUY:
3006                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3007         default:
3008                 MISSING_CASE(pixel_format);
3009         }
3010
3011         return 0;
3012 }
3013
3014 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3015 {
3016         switch (fb_modifier) {
3017         case DRM_FORMAT_MOD_NONE:
3018                 break;
3019         case I915_FORMAT_MOD_X_TILED:
3020                 return PLANE_CTL_TILED_X;
3021         case I915_FORMAT_MOD_Y_TILED:
3022                 return PLANE_CTL_TILED_Y;
3023         case I915_FORMAT_MOD_Yf_TILED:
3024                 return PLANE_CTL_TILED_YF;
3025         default:
3026                 MISSING_CASE(fb_modifier);
3027         }
3028
3029         return 0;
3030 }
3031
3032 u32 skl_plane_ctl_rotation(unsigned int rotation)
3033 {
3034         switch (rotation) {
3035         case BIT(DRM_ROTATE_0):
3036                 break;
3037         /*
3038          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3039          * while i915 HW rotation is clockwise, thats why this swapping.
3040          */
3041         case BIT(DRM_ROTATE_90):
3042                 return PLANE_CTL_ROTATE_270;
3043         case BIT(DRM_ROTATE_180):
3044                 return PLANE_CTL_ROTATE_180;
3045         case BIT(DRM_ROTATE_270):
3046                 return PLANE_CTL_ROTATE_90;
3047         default:
3048                 MISSING_CASE(rotation);
3049         }
3050
3051         return 0;
3052 }
3053
3054 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3055                                          struct drm_framebuffer *fb,
3056                                          int x, int y)
3057 {
3058         struct drm_device *dev = crtc->dev;
3059         struct drm_i915_private *dev_priv = dev->dev_private;
3060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3061         struct drm_plane *plane = crtc->primary;
3062         bool visible = to_intel_plane_state(plane->state)->visible;
3063         struct drm_i915_gem_object *obj;
3064         int pipe = intel_crtc->pipe;
3065         u32 plane_ctl, stride_div, stride;
3066         u32 tile_height, plane_offset, plane_size;
3067         unsigned int rotation;
3068         int x_offset, y_offset;
3069         unsigned long surf_addr;
3070         struct intel_crtc_state *crtc_state = intel_crtc->config;
3071         struct intel_plane_state *plane_state;
3072         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3073         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3074         int scaler_id = -1;
3075
3076         plane_state = to_intel_plane_state(plane->state);
3077
3078         if (!visible || !fb) {
3079                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3080                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3081                 POSTING_READ(PLANE_CTL(pipe, 0));
3082                 return;
3083         }
3084
3085         plane_ctl = PLANE_CTL_ENABLE |
3086                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3087                     PLANE_CTL_PIPE_CSC_ENABLE;
3088
3089         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3090         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3091         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3092
3093         rotation = plane->state->rotation;
3094         plane_ctl |= skl_plane_ctl_rotation(rotation);
3095
3096         obj = intel_fb_obj(fb);
3097         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3098                                                fb->pixel_format);
3099         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3100
3101         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3102
3103         scaler_id = plane_state->scaler_id;
3104         src_x = plane_state->src.x1 >> 16;
3105         src_y = plane_state->src.y1 >> 16;
3106         src_w = drm_rect_width(&plane_state->src) >> 16;
3107         src_h = drm_rect_height(&plane_state->src) >> 16;
3108         dst_x = plane_state->dst.x1;
3109         dst_y = plane_state->dst.y1;
3110         dst_w = drm_rect_width(&plane_state->dst);
3111         dst_h = drm_rect_height(&plane_state->dst);
3112
3113         WARN_ON(x != src_x || y != src_y);
3114
3115         if (intel_rotation_90_or_270(rotation)) {
3116                 /* stride = Surface height in tiles */
3117                 tile_height = intel_tile_height(dev, fb->pixel_format,
3118                                                 fb->modifier[0], 0);
3119                 stride = DIV_ROUND_UP(fb->height, tile_height);
3120                 x_offset = stride * tile_height - y - src_h;
3121                 y_offset = x;
3122                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3123         } else {
3124                 stride = fb->pitches[0] / stride_div;
3125                 x_offset = x;
3126                 y_offset = y;
3127                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3128         }
3129         plane_offset = y_offset << 16 | x_offset;
3130
3131         intel_crtc->adjusted_x = x_offset;
3132         intel_crtc->adjusted_y = y_offset;
3133
3134         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3135         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3136         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3137         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3138
3139         if (scaler_id >= 0) {
3140                 uint32_t ps_ctrl = 0;
3141
3142                 WARN_ON(!dst_w || !dst_h);
3143                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3144                         crtc_state->scaler_state.scalers[scaler_id].mode;
3145                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3146                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3147                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3148                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3149                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3150         } else {
3151                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3152         }
3153
3154         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3155
3156         POSTING_READ(PLANE_SURF(pipe, 0));
3157 }
3158
3159 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3160 static int
3161 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3162                            int x, int y, enum mode_set_atomic state)
3163 {
3164         struct drm_device *dev = crtc->dev;
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166
3167         if (dev_priv->fbc.disable_fbc)
3168                 dev_priv->fbc.disable_fbc(dev_priv);
3169
3170         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3171
3172         return 0;
3173 }
3174
3175 static void intel_complete_page_flips(struct drm_device *dev)
3176 {
3177         struct drm_crtc *crtc;
3178
3179         for_each_crtc(dev, crtc) {
3180                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181                 enum plane plane = intel_crtc->plane;
3182
3183                 intel_prepare_page_flip(dev, plane);
3184                 intel_finish_page_flip_plane(dev, plane);
3185         }
3186 }
3187
3188 static void intel_update_primary_planes(struct drm_device *dev)
3189 {
3190         struct drm_crtc *crtc;
3191
3192         for_each_crtc(dev, crtc) {
3193                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3194                 struct intel_plane_state *plane_state;
3195
3196                 drm_modeset_lock_crtc(crtc, &plane->base);
3197                 plane_state = to_intel_plane_state(plane->base.state);
3198
3199                 if (crtc->state->active && plane_state->base.fb)
3200                         plane->commit_plane(&plane->base, plane_state);
3201
3202                 drm_modeset_unlock_crtc(crtc);
3203         }
3204 }
3205
3206 void intel_prepare_reset(struct drm_device *dev)
3207 {
3208         /* no reset support for gen2 */
3209         if (IS_GEN2(dev))
3210                 return;
3211
3212         /* reset doesn't touch the display */
3213         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3214                 return;
3215
3216         drm_modeset_lock_all(dev);
3217         /*
3218          * Disabling the crtcs gracefully seems nicer. Also the
3219          * g33 docs say we should at least disable all the planes.
3220          */
3221         intel_display_suspend(dev);
3222 }
3223
3224 void intel_finish_reset(struct drm_device *dev)
3225 {
3226         struct drm_i915_private *dev_priv = to_i915(dev);
3227
3228         /*
3229          * Flips in the rings will be nuked by the reset,
3230          * so complete all pending flips so that user space
3231          * will get its events and not get stuck.
3232          */
3233         intel_complete_page_flips(dev);
3234
3235         /* no reset support for gen2 */
3236         if (IS_GEN2(dev))
3237                 return;
3238
3239         /* reset doesn't touch the display */
3240         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3241                 /*
3242                  * Flips in the rings have been nuked by the reset,
3243                  * so update the base address of all primary
3244                  * planes to the the last fb to make sure we're
3245                  * showing the correct fb after a reset.
3246                  *
3247                  * FIXME: Atomic will make this obsolete since we won't schedule
3248                  * CS-based flips (which might get lost in gpu resets) any more.
3249                  */
3250                 intel_update_primary_planes(dev);
3251                 return;
3252         }
3253
3254         /*
3255          * The display has been reset as well,
3256          * so need a full re-initialization.
3257          */
3258         intel_runtime_pm_disable_interrupts(dev_priv);
3259         intel_runtime_pm_enable_interrupts(dev_priv);
3260
3261         intel_modeset_init_hw(dev);
3262
3263         spin_lock_irq(&dev_priv->irq_lock);
3264         if (dev_priv->display.hpd_irq_setup)
3265                 dev_priv->display.hpd_irq_setup(dev);
3266         spin_unlock_irq(&dev_priv->irq_lock);
3267
3268         intel_display_resume(dev);
3269
3270         intel_hpd_init(dev_priv);
3271
3272         drm_modeset_unlock_all(dev);
3273 }
3274
3275 static void
3276 intel_finish_fb(struct drm_framebuffer *old_fb)
3277 {
3278         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3279         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3280         bool was_interruptible = dev_priv->mm.interruptible;
3281         int ret;
3282
3283         /* Big Hammer, we also need to ensure that any pending
3284          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3285          * current scanout is retired before unpinning the old
3286          * framebuffer. Note that we rely on userspace rendering
3287          * into the buffer attached to the pipe they are waiting
3288          * on. If not, userspace generates a GPU hang with IPEHR
3289          * point to the MI_WAIT_FOR_EVENT.
3290          *
3291          * This should only fail upon a hung GPU, in which case we
3292          * can safely continue.
3293          */
3294         dev_priv->mm.interruptible = false;
3295         ret = i915_gem_object_wait_rendering(obj, true);
3296         dev_priv->mm.interruptible = was_interruptible;
3297
3298         WARN_ON(ret);
3299 }
3300
3301 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         bool pending;
3307
3308         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3309             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3310                 return false;
3311
3312         spin_lock_irq(&dev->event_lock);
3313         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3314         spin_unlock_irq(&dev->event_lock);
3315
3316         return pending;
3317 }
3318
3319 static void intel_update_pipe_config(struct intel_crtc *crtc,
3320                                      struct intel_crtc_state *old_crtc_state)
3321 {
3322         struct drm_device *dev = crtc->base.dev;
3323         struct drm_i915_private *dev_priv = dev->dev_private;
3324         struct intel_crtc_state *pipe_config =
3325                 to_intel_crtc_state(crtc->base.state);
3326
3327         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3328         crtc->base.mode = crtc->base.state->mode;
3329
3330         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3331                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3332                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3333
3334         if (HAS_DDI(dev))
3335                 intel_set_pipe_csc(&crtc->base);
3336
3337         /*
3338          * Update pipe size and adjust fitter if needed: the reason for this is
3339          * that in compute_mode_changes we check the native mode (not the pfit
3340          * mode) to see if we can flip rather than do a full mode set. In the
3341          * fastboot case, we'll flip, but if we don't update the pipesrc and
3342          * pfit state, we'll end up with a big fb scanned out into the wrong
3343          * sized surface.
3344          */
3345
3346         I915_WRITE(PIPESRC(crtc->pipe),
3347                    ((pipe_config->pipe_src_w - 1) << 16) |
3348                    (pipe_config->pipe_src_h - 1));
3349
3350         /* on skylake this is done by detaching scalers */
3351         if (INTEL_INFO(dev)->gen >= 9) {
3352                 skl_detach_scalers(crtc);
3353
3354                 if (pipe_config->pch_pfit.enabled)
3355                         skylake_pfit_enable(crtc);
3356         } else if (HAS_PCH_SPLIT(dev)) {
3357                 if (pipe_config->pch_pfit.enabled)
3358                         ironlake_pfit_enable(crtc);
3359                 else if (old_crtc_state->pch_pfit.enabled)
3360                         ironlake_pfit_disable(crtc, true);
3361         }
3362 }
3363
3364 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365 {
3366         struct drm_device *dev = crtc->dev;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369         int pipe = intel_crtc->pipe;
3370         u32 reg, temp;
3371
3372         /* enable normal train */
3373         reg = FDI_TX_CTL(pipe);
3374         temp = I915_READ(reg);
3375         if (IS_IVYBRIDGE(dev)) {
3376                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3378         } else {
3379                 temp &= ~FDI_LINK_TRAIN_NONE;
3380                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3381         }
3382         I915_WRITE(reg, temp);
3383
3384         reg = FDI_RX_CTL(pipe);
3385         temp = I915_READ(reg);
3386         if (HAS_PCH_CPT(dev)) {
3387                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389         } else {
3390                 temp &= ~FDI_LINK_TRAIN_NONE;
3391                 temp |= FDI_LINK_TRAIN_NONE;
3392         }
3393         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395         /* wait one idle pattern time */
3396         POSTING_READ(reg);
3397         udelay(1000);
3398
3399         /* IVB wants error correction enabled */
3400         if (IS_IVYBRIDGE(dev))
3401                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402                            FDI_FE_ERRC_ENABLE);
3403 }
3404
3405 /* The FDI link training functions for ILK/Ibexpeak. */
3406 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407 {
3408         struct drm_device *dev = crtc->dev;
3409         struct drm_i915_private *dev_priv = dev->dev_private;
3410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411         int pipe = intel_crtc->pipe;
3412         u32 reg, temp, tries;
3413
3414         /* FDI needs bits from pipe first */
3415         assert_pipe_enabled(dev_priv, pipe);
3416
3417         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418            for train result */
3419         reg = FDI_RX_IMR(pipe);
3420         temp = I915_READ(reg);
3421         temp &= ~FDI_RX_SYMBOL_LOCK;
3422         temp &= ~FDI_RX_BIT_LOCK;
3423         I915_WRITE(reg, temp);
3424         I915_READ(reg);
3425         udelay(150);
3426
3427         /* enable CPU FDI TX and PCH FDI RX */
3428         reg = FDI_TX_CTL(pipe);
3429         temp = I915_READ(reg);
3430         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3431         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3432         temp &= ~FDI_LINK_TRAIN_NONE;
3433         temp |= FDI_LINK_TRAIN_PATTERN_1;
3434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3435
3436         reg = FDI_RX_CTL(pipe);
3437         temp = I915_READ(reg);
3438         temp &= ~FDI_LINK_TRAIN_NONE;
3439         temp |= FDI_LINK_TRAIN_PATTERN_1;
3440         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442         POSTING_READ(reg);
3443         udelay(150);
3444
3445         /* Ironlake workaround, enable clock pointer after FDI enable*/
3446         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448                    FDI_RX_PHASE_SYNC_POINTER_EN);
3449
3450         reg = FDI_RX_IIR(pipe);
3451         for (tries = 0; tries < 5; tries++) {
3452                 temp = I915_READ(reg);
3453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455                 if ((temp & FDI_RX_BIT_LOCK)) {
3456                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3457                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3458                         break;
3459                 }
3460         }
3461         if (tries == 5)
3462                 DRM_ERROR("FDI train 1 fail!\n");
3463
3464         /* Train 2 */
3465         reg = FDI_TX_CTL(pipe);
3466         temp = I915_READ(reg);
3467         temp &= ~FDI_LINK_TRAIN_NONE;
3468         temp |= FDI_LINK_TRAIN_PATTERN_2;
3469         I915_WRITE(reg, temp);
3470
3471         reg = FDI_RX_CTL(pipe);
3472         temp = I915_READ(reg);
3473         temp &= ~FDI_LINK_TRAIN_NONE;
3474         temp |= FDI_LINK_TRAIN_PATTERN_2;
3475         I915_WRITE(reg, temp);
3476
3477         POSTING_READ(reg);
3478         udelay(150);
3479
3480         reg = FDI_RX_IIR(pipe);
3481         for (tries = 0; tries < 5; tries++) {
3482                 temp = I915_READ(reg);
3483                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485                 if (temp & FDI_RX_SYMBOL_LOCK) {
3486                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3488                         break;
3489                 }
3490         }
3491         if (tries == 5)
3492                 DRM_ERROR("FDI train 2 fail!\n");
3493
3494         DRM_DEBUG_KMS("FDI train done\n");
3495
3496 }
3497
3498 static const int snb_b_fdi_train_param[] = {
3499         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503 };
3504
3505 /* The FDI link training functions for SNB/Cougarpoint. */
3506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507 {
3508         struct drm_device *dev = crtc->dev;
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         int pipe = intel_crtc->pipe;
3512         u32 reg, temp, i, retry;
3513
3514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515            for train result */
3516         reg = FDI_RX_IMR(pipe);
3517         temp = I915_READ(reg);
3518         temp &= ~FDI_RX_SYMBOL_LOCK;
3519         temp &= ~FDI_RX_BIT_LOCK;
3520         I915_WRITE(reg, temp);
3521
3522         POSTING_READ(reg);
3523         udelay(150);
3524
3525         /* enable CPU FDI TX and PCH FDI RX */
3526         reg = FDI_TX_CTL(pipe);
3527         temp = I915_READ(reg);
3528         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3529         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3530         temp &= ~FDI_LINK_TRAIN_NONE;
3531         temp |= FDI_LINK_TRAIN_PATTERN_1;
3532         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533         /* SNB-B */
3534         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3535         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3536
3537         I915_WRITE(FDI_RX_MISC(pipe),
3538                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
3540         reg = FDI_RX_CTL(pipe);
3541         temp = I915_READ(reg);
3542         if (HAS_PCH_CPT(dev)) {
3543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545         } else {
3546                 temp &= ~FDI_LINK_TRAIN_NONE;
3547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548         }
3549         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551         POSTING_READ(reg);
3552         udelay(150);
3553
3554         for (i = 0; i < 4; i++) {
3555                 reg = FDI_TX_CTL(pipe);
3556                 temp = I915_READ(reg);
3557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558                 temp |= snb_b_fdi_train_param[i];
3559                 I915_WRITE(reg, temp);
3560
3561                 POSTING_READ(reg);
3562                 udelay(500);
3563
3564                 for (retry = 0; retry < 5; retry++) {
3565                         reg = FDI_RX_IIR(pipe);
3566                         temp = I915_READ(reg);
3567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568                         if (temp & FDI_RX_BIT_LOCK) {
3569                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571                                 break;
3572                         }
3573                         udelay(50);
3574                 }
3575                 if (retry < 5)
3576                         break;
3577         }
3578         if (i == 4)
3579                 DRM_ERROR("FDI train 1 fail!\n");
3580
3581         /* Train 2 */
3582         reg = FDI_TX_CTL(pipe);
3583         temp = I915_READ(reg);
3584         temp &= ~FDI_LINK_TRAIN_NONE;
3585         temp |= FDI_LINK_TRAIN_PATTERN_2;
3586         if (IS_GEN6(dev)) {
3587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588                 /* SNB-B */
3589                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590         }
3591         I915_WRITE(reg, temp);
3592
3593         reg = FDI_RX_CTL(pipe);
3594         temp = I915_READ(reg);
3595         if (HAS_PCH_CPT(dev)) {
3596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598         } else {
3599                 temp &= ~FDI_LINK_TRAIN_NONE;
3600                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601         }
3602         I915_WRITE(reg, temp);
3603
3604         POSTING_READ(reg);
3605         udelay(150);
3606
3607         for (i = 0; i < 4; i++) {
3608                 reg = FDI_TX_CTL(pipe);
3609                 temp = I915_READ(reg);
3610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611                 temp |= snb_b_fdi_train_param[i];
3612                 I915_WRITE(reg, temp);
3613
3614                 POSTING_READ(reg);
3615                 udelay(500);
3616
3617                 for (retry = 0; retry < 5; retry++) {
3618                         reg = FDI_RX_IIR(pipe);
3619                         temp = I915_READ(reg);
3620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621                         if (temp & FDI_RX_SYMBOL_LOCK) {
3622                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624                                 break;
3625                         }
3626                         udelay(50);
3627                 }
3628                 if (retry < 5)
3629                         break;
3630         }
3631         if (i == 4)
3632                 DRM_ERROR("FDI train 2 fail!\n");
3633
3634         DRM_DEBUG_KMS("FDI train done.\n");
3635 }
3636
3637 /* Manual link training for Ivy Bridge A0 parts */
3638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643         int pipe = intel_crtc->pipe;
3644         u32 reg, temp, i, j;
3645
3646         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647            for train result */
3648         reg = FDI_RX_IMR(pipe);
3649         temp = I915_READ(reg);
3650         temp &= ~FDI_RX_SYMBOL_LOCK;
3651         temp &= ~FDI_RX_BIT_LOCK;
3652         I915_WRITE(reg, temp);
3653
3654         POSTING_READ(reg);
3655         udelay(150);
3656
3657         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658                       I915_READ(FDI_RX_IIR(pipe)));
3659
3660         /* Try each vswing and preemphasis setting twice before moving on */
3661         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662                 /* disable first in case we need to retry */
3663                 reg = FDI_TX_CTL(pipe);
3664                 temp = I915_READ(reg);
3665                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666                 temp &= ~FDI_TX_ENABLE;
3667                 I915_WRITE(reg, temp);
3668
3669                 reg = FDI_RX_CTL(pipe);
3670                 temp = I915_READ(reg);
3671                 temp &= ~FDI_LINK_TRAIN_AUTO;
3672                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673                 temp &= ~FDI_RX_ENABLE;
3674                 I915_WRITE(reg, temp);
3675
3676                 /* enable CPU FDI TX and PCH FDI RX */
3677                 reg = FDI_TX_CTL(pipe);
3678                 temp = I915_READ(reg);
3679                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3680                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3682                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3683                 temp |= snb_b_fdi_train_param[j/2];
3684                 temp |= FDI_COMPOSITE_SYNC;
3685                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3686
3687                 I915_WRITE(FDI_RX_MISC(pipe),
3688                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3689
3690                 reg = FDI_RX_CTL(pipe);
3691                 temp = I915_READ(reg);
3692                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693                 temp |= FDI_COMPOSITE_SYNC;
3694                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3695
3696                 POSTING_READ(reg);
3697                 udelay(1); /* should be 0.5us */
3698
3699                 for (i = 0; i < 4; i++) {
3700                         reg = FDI_RX_IIR(pipe);
3701                         temp = I915_READ(reg);
3702                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3703
3704                         if (temp & FDI_RX_BIT_LOCK ||
3705                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708                                               i);
3709                                 break;
3710                         }
3711                         udelay(1); /* should be 0.5us */
3712                 }
3713                 if (i == 4) {
3714                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715                         continue;
3716                 }
3717
3718                 /* Train 2 */
3719                 reg = FDI_TX_CTL(pipe);
3720                 temp = I915_READ(reg);
3721                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723                 I915_WRITE(reg, temp);
3724
3725                 reg = FDI_RX_CTL(pipe);
3726                 temp = I915_READ(reg);
3727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3729                 I915_WRITE(reg, temp);
3730
3731                 POSTING_READ(reg);
3732                 udelay(2); /* should be 1.5us */
3733
3734                 for (i = 0; i < 4; i++) {
3735                         reg = FDI_RX_IIR(pipe);
3736                         temp = I915_READ(reg);
3737                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3738
3739                         if (temp & FDI_RX_SYMBOL_LOCK ||
3740                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743                                               i);
3744                                 goto train_done;
3745                         }
3746                         udelay(2); /* should be 1.5us */
3747                 }
3748                 if (i == 4)
3749                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3750         }
3751
3752 train_done:
3753         DRM_DEBUG_KMS("FDI train done.\n");
3754 }
3755
3756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3757 {
3758         struct drm_device *dev = intel_crtc->base.dev;
3759         struct drm_i915_private *dev_priv = dev->dev_private;
3760         int pipe = intel_crtc->pipe;
3761         u32 reg, temp;
3762
3763
3764         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3765         reg = FDI_RX_CTL(pipe);
3766         temp = I915_READ(reg);
3767         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3768         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3769         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3770         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772         POSTING_READ(reg);
3773         udelay(200);
3774
3775         /* Switch from Rawclk to PCDclk */
3776         temp = I915_READ(reg);
3777         I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779         POSTING_READ(reg);
3780         udelay(200);
3781
3782         /* Enable CPU FDI TX PLL, always on for Ironlake */
3783         reg = FDI_TX_CTL(pipe);
3784         temp = I915_READ(reg);
3785         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3787
3788                 POSTING_READ(reg);
3789                 udelay(100);
3790         }
3791 }
3792
3793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794 {
3795         struct drm_device *dev = intel_crtc->base.dev;
3796         struct drm_i915_private *dev_priv = dev->dev_private;
3797         int pipe = intel_crtc->pipe;
3798         u32 reg, temp;
3799
3800         /* Switch from PCDclk to Rawclk */
3801         reg = FDI_RX_CTL(pipe);
3802         temp = I915_READ(reg);
3803         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805         /* Disable CPU FDI TX PLL */
3806         reg = FDI_TX_CTL(pipe);
3807         temp = I915_READ(reg);
3808         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810         POSTING_READ(reg);
3811         udelay(100);
3812
3813         reg = FDI_RX_CTL(pipe);
3814         temp = I915_READ(reg);
3815         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817         /* Wait for the clocks to turn off. */
3818         POSTING_READ(reg);
3819         udelay(100);
3820 }
3821
3822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823 {
3824         struct drm_device *dev = crtc->dev;
3825         struct drm_i915_private *dev_priv = dev->dev_private;
3826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827         int pipe = intel_crtc->pipe;
3828         u32 reg, temp;
3829
3830         /* disable CPU FDI tx and PCH FDI rx */
3831         reg = FDI_TX_CTL(pipe);
3832         temp = I915_READ(reg);
3833         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834         POSTING_READ(reg);
3835
3836         reg = FDI_RX_CTL(pipe);
3837         temp = I915_READ(reg);
3838         temp &= ~(0x7 << 16);
3839         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3840         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842         POSTING_READ(reg);
3843         udelay(100);
3844
3845         /* Ironlake workaround, disable clock pointer after downing FDI */
3846         if (HAS_PCH_IBX(dev))
3847                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3848
3849         /* still set train pattern 1 */
3850         reg = FDI_TX_CTL(pipe);
3851         temp = I915_READ(reg);
3852         temp &= ~FDI_LINK_TRAIN_NONE;
3853         temp |= FDI_LINK_TRAIN_PATTERN_1;
3854         I915_WRITE(reg, temp);
3855
3856         reg = FDI_RX_CTL(pipe);
3857         temp = I915_READ(reg);
3858         if (HAS_PCH_CPT(dev)) {
3859                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861         } else {
3862                 temp &= ~FDI_LINK_TRAIN_NONE;
3863                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864         }
3865         /* BPC in FDI rx is consistent with that in PIPECONF */
3866         temp &= ~(0x07 << 16);
3867         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3868         I915_WRITE(reg, temp);
3869
3870         POSTING_READ(reg);
3871         udelay(100);
3872 }
3873
3874 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875 {
3876         struct intel_crtc *crtc;
3877
3878         /* Note that we don't need to be called with mode_config.lock here
3879          * as our list of CRTC objects is static for the lifetime of the
3880          * device and so cannot disappear as we iterate. Similarly, we can
3881          * happily treat the predicates as racy, atomic checks as userspace
3882          * cannot claim and pin a new fb without at least acquring the
3883          * struct_mutex and so serialising with us.
3884          */
3885         for_each_intel_crtc(dev, crtc) {
3886                 if (atomic_read(&crtc->unpin_work_count) == 0)
3887                         continue;
3888
3889                 if (crtc->unpin_work)
3890                         intel_wait_for_vblank(dev, crtc->pipe);
3891
3892                 return true;
3893         }
3894
3895         return false;
3896 }
3897
3898 static void page_flip_completed(struct intel_crtc *intel_crtc)
3899 {
3900         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901         struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903         /* ensure that the unpin work is consistent wrt ->pending. */
3904         smp_rmb();
3905         intel_crtc->unpin_work = NULL;
3906
3907         if (work->event)
3908                 drm_send_vblank_event(intel_crtc->base.dev,
3909                                       intel_crtc->pipe,
3910                                       work->event);
3911
3912         drm_crtc_vblank_put(&intel_crtc->base);
3913
3914         wake_up_all(&dev_priv->pending_flip_queue);
3915         queue_work(dev_priv->wq, &work->work);
3916
3917         trace_i915_flip_complete(intel_crtc->plane,
3918                                  work->pending_flip_obj);
3919 }
3920
3921 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3922 {
3923         struct drm_device *dev = crtc->dev;
3924         struct drm_i915_private *dev_priv = dev->dev_private;
3925
3926         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3927         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928                                        !intel_crtc_has_pending_flip(crtc),
3929                                        60*HZ) == 0)) {
3930                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931
3932                 spin_lock_irq(&dev->event_lock);
3933                 if (intel_crtc->unpin_work) {
3934                         WARN_ONCE(1, "Removing stuck page flip\n");
3935                         page_flip_completed(intel_crtc);
3936                 }
3937                 spin_unlock_irq(&dev->event_lock);
3938         }
3939
3940         if (crtc->primary->fb) {
3941                 mutex_lock(&dev->struct_mutex);
3942                 intel_finish_fb(crtc->primary->fb);
3943                 mutex_unlock(&dev->struct_mutex);
3944         }
3945 }
3946
3947 /* Program iCLKIP clock to the desired frequency */
3948 static void lpt_program_iclkip(struct drm_crtc *crtc)
3949 {
3950         struct drm_device *dev = crtc->dev;
3951         struct drm_i915_private *dev_priv = dev->dev_private;
3952         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3953         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954         u32 temp;
3955
3956         mutex_lock(&dev_priv->sb_lock);
3957
3958         /* It is necessary to ungate the pixclk gate prior to programming
3959          * the divisors, and gate it back when it is done.
3960          */
3961         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963         /* Disable SSCCTL */
3964         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3965                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966                                 SBI_SSCCTL_DISABLE,
3967                         SBI_ICLK);
3968
3969         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3970         if (clock == 20000) {
3971                 auxdiv = 1;
3972                 divsel = 0x41;
3973                 phaseinc = 0x20;
3974         } else {
3975                 /* The iCLK virtual clock root frequency is in MHz,
3976                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3977                  * divisors, it is necessary to divide one by another, so we
3978                  * convert the virtual clock precision to KHz here for higher
3979                  * precision.
3980                  */
3981                 u32 iclk_virtual_root_freq = 172800 * 1000;
3982                 u32 iclk_pi_range = 64;
3983                 u32 desired_divisor, msb_divisor_value, pi_value;
3984
3985                 desired_divisor = (iclk_virtual_root_freq / clock);
3986                 msb_divisor_value = desired_divisor / iclk_pi_range;
3987                 pi_value = desired_divisor % iclk_pi_range;
3988
3989                 auxdiv = 0;
3990                 divsel = msb_divisor_value - 2;
3991                 phaseinc = pi_value;
3992         }
3993
3994         /* This should not happen with any sane values */
3995         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4001                         clock,
4002                         auxdiv,
4003                         divsel,
4004                         phasedir,
4005                         phaseinc);
4006
4007         /* Program SSCDIVINTPHASE6 */
4008         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4009         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4015         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4016
4017         /* Program SSCAUXDIV */
4018         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4019         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4021         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4022
4023         /* Enable modulator and associated divider */
4024         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4025         temp &= ~SBI_SSCCTL_DISABLE;
4026         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4027
4028         /* Wait for initialization time */
4029         udelay(24);
4030
4031         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4032
4033         mutex_unlock(&dev_priv->sb_lock);
4034 }
4035
4036 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037                                                 enum pipe pch_transcoder)
4038 {
4039         struct drm_device *dev = crtc->base.dev;
4040         struct drm_i915_private *dev_priv = dev->dev_private;
4041         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4042
4043         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044                    I915_READ(HTOTAL(cpu_transcoder)));
4045         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046                    I915_READ(HBLANK(cpu_transcoder)));
4047         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048                    I915_READ(HSYNC(cpu_transcoder)));
4049
4050         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051                    I915_READ(VTOTAL(cpu_transcoder)));
4052         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053                    I915_READ(VBLANK(cpu_transcoder)));
4054         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055                    I915_READ(VSYNC(cpu_transcoder)));
4056         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058 }
4059
4060 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4061 {
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         uint32_t temp;
4064
4065         temp = I915_READ(SOUTH_CHICKEN1);
4066         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4067                 return;
4068
4069         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
4072         temp &= ~FDI_BC_BIFURCATION_SELECT;
4073         if (enable)
4074                 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4077         I915_WRITE(SOUTH_CHICKEN1, temp);
4078         POSTING_READ(SOUTH_CHICKEN1);
4079 }
4080
4081 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082 {
4083         struct drm_device *dev = intel_crtc->base.dev;
4084
4085         switch (intel_crtc->pipe) {
4086         case PIPE_A:
4087                 break;
4088         case PIPE_B:
4089                 if (intel_crtc->config->fdi_lanes > 2)
4090                         cpt_set_fdi_bc_bifurcation(dev, false);
4091                 else
4092                         cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094                 break;
4095         case PIPE_C:
4096                 cpt_set_fdi_bc_bifurcation(dev, true);
4097
4098                 break;
4099         default:
4100                 BUG();
4101         }
4102 }
4103
4104 /*
4105  * Enable PCH resources required for PCH ports:
4106  *   - PCH PLLs
4107  *   - FDI training & RX/TX
4108  *   - update transcoder timings
4109  *   - DP transcoding bits
4110  *   - transcoder
4111  */
4112 static void ironlake_pch_enable(struct drm_crtc *crtc)
4113 {
4114         struct drm_device *dev = crtc->dev;
4115         struct drm_i915_private *dev_priv = dev->dev_private;
4116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117         int pipe = intel_crtc->pipe;
4118         u32 reg, temp;
4119
4120         assert_pch_transcoder_disabled(dev_priv, pipe);
4121
4122         if (IS_IVYBRIDGE(dev))
4123                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
4125         /* Write the TU size bits before fdi link training, so that error
4126          * detection works. */
4127         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
4130         /* For PCH output, training FDI link */
4131         dev_priv->display.fdi_link_train(crtc);
4132
4133         /* We need to program the right clock selection before writing the pixel
4134          * mutliplier into the DPLL. */
4135         if (HAS_PCH_CPT(dev)) {
4136                 u32 sel;
4137
4138                 temp = I915_READ(PCH_DPLL_SEL);
4139                 temp |= TRANS_DPLL_ENABLE(pipe);
4140                 sel = TRANS_DPLLB_SEL(pipe);
4141                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4142                         temp |= sel;
4143                 else
4144                         temp &= ~sel;
4145                 I915_WRITE(PCH_DPLL_SEL, temp);
4146         }
4147
4148         /* XXX: pch pll's can be enabled any time before we enable the PCH
4149          * transcoder, and we actually should do this to not upset any PCH
4150          * transcoder that already use the clock when we share it.
4151          *
4152          * Note that enable_shared_dpll tries to do the right thing, but
4153          * get_shared_dpll unconditionally resets the pll - we need that to have
4154          * the right LVDS enable sequence. */
4155         intel_enable_shared_dpll(intel_crtc);
4156
4157         /* set transcoder timing, panel must allow it */
4158         assert_panel_unlocked(dev_priv, pipe);
4159         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4160
4161         intel_fdi_normal_train(crtc);
4162
4163         /* For PCH DP, enable TRANS_DP_CTL */
4164         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4165                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4166                 reg = TRANS_DP_CTL(pipe);
4167                 temp = I915_READ(reg);
4168                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4169                           TRANS_DP_SYNC_MASK |
4170                           TRANS_DP_BPC_MASK);
4171                 temp |= TRANS_DP_OUTPUT_ENABLE;
4172                 temp |= bpc << 9; /* same format but at 11:9 */
4173
4174                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4175                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4176                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4177                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4178
4179                 switch (intel_trans_dp_port_sel(crtc)) {
4180                 case PCH_DP_B:
4181                         temp |= TRANS_DP_PORT_SEL_B;
4182                         break;
4183                 case PCH_DP_C:
4184                         temp |= TRANS_DP_PORT_SEL_C;
4185                         break;
4186                 case PCH_DP_D:
4187                         temp |= TRANS_DP_PORT_SEL_D;
4188                         break;
4189                 default:
4190                         BUG();
4191                 }
4192
4193                 I915_WRITE(reg, temp);
4194         }
4195
4196         ironlake_enable_pch_transcoder(dev_priv, pipe);
4197 }
4198
4199 static void lpt_pch_enable(struct drm_crtc *crtc)
4200 {
4201         struct drm_device *dev = crtc->dev;
4202         struct drm_i915_private *dev_priv = dev->dev_private;
4203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4205
4206         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4207
4208         lpt_program_iclkip(crtc);
4209
4210         /* Set transcoder timing. */
4211         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4212
4213         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4214 }
4215
4216 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4217                                                 struct intel_crtc_state *crtc_state)
4218 {
4219         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4220         struct intel_shared_dpll *pll;
4221         struct intel_shared_dpll_config *shared_dpll;
4222         enum intel_dpll_id i;
4223
4224         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4225
4226         if (HAS_PCH_IBX(dev_priv->dev)) {
4227                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4228                 i = (enum intel_dpll_id) crtc->pipe;
4229                 pll = &dev_priv->shared_dplls[i];
4230
4231                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4232                               crtc->base.base.id, pll->name);
4233
4234                 WARN_ON(shared_dpll[i].crtc_mask);
4235
4236                 goto found;
4237         }
4238
4239         if (IS_BROXTON(dev_priv->dev)) {
4240                 /* PLL is attached to port in bxt */
4241                 struct intel_encoder *encoder;
4242                 struct intel_digital_port *intel_dig_port;
4243
4244                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4245                 if (WARN_ON(!encoder))
4246                         return NULL;
4247
4248                 intel_dig_port = enc_to_dig_port(&encoder->base);
4249                 /* 1:1 mapping between ports and PLLs */
4250                 i = (enum intel_dpll_id)intel_dig_port->port;
4251                 pll = &dev_priv->shared_dplls[i];
4252                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4253                         crtc->base.base.id, pll->name);
4254                 WARN_ON(shared_dpll[i].crtc_mask);
4255
4256                 goto found;
4257         }
4258
4259         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4260                 pll = &dev_priv->shared_dplls[i];
4261
4262                 /* Only want to check enabled timings first */
4263                 if (shared_dpll[i].crtc_mask == 0)
4264                         continue;
4265
4266                 if (memcmp(&crtc_state->dpll_hw_state,
4267                            &shared_dpll[i].hw_state,
4268                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4269                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4270                                       crtc->base.base.id, pll->name,
4271                                       shared_dpll[i].crtc_mask,
4272                                       pll->active);
4273                         goto found;
4274                 }
4275         }
4276
4277         /* Ok no matching timings, maybe there's a free one? */
4278         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4279                 pll = &dev_priv->shared_dplls[i];
4280                 if (shared_dpll[i].crtc_mask == 0) {
4281                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4282                                       crtc->base.base.id, pll->name);
4283                         goto found;
4284                 }
4285         }
4286
4287         return NULL;
4288
4289 found:
4290         if (shared_dpll[i].crtc_mask == 0)
4291                 shared_dpll[i].hw_state =
4292                         crtc_state->dpll_hw_state;
4293
4294         crtc_state->shared_dpll = i;
4295         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4296                          pipe_name(crtc->pipe));
4297
4298         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4299
4300         return pll;
4301 }
4302
4303 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4304 {
4305         struct drm_i915_private *dev_priv = to_i915(state->dev);
4306         struct intel_shared_dpll_config *shared_dpll;
4307         struct intel_shared_dpll *pll;
4308         enum intel_dpll_id i;
4309
4310         if (!to_intel_atomic_state(state)->dpll_set)
4311                 return;
4312
4313         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4314         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4315                 pll = &dev_priv->shared_dplls[i];
4316                 pll->config = shared_dpll[i];
4317         }
4318 }
4319
4320 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4321 {
4322         struct drm_i915_private *dev_priv = dev->dev_private;
4323         int dslreg = PIPEDSL(pipe);
4324         u32 temp;
4325
4326         temp = I915_READ(dslreg);
4327         udelay(500);
4328         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4329                 if (wait_for(I915_READ(dslreg) != temp, 5))
4330                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4331         }
4332 }
4333
4334 static int
4335 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4336                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4337                   int src_w, int src_h, int dst_w, int dst_h)
4338 {
4339         struct intel_crtc_scaler_state *scaler_state =
4340                 &crtc_state->scaler_state;
4341         struct intel_crtc *intel_crtc =
4342                 to_intel_crtc(crtc_state->base.crtc);
4343         int need_scaling;
4344
4345         need_scaling = intel_rotation_90_or_270(rotation) ?
4346                 (src_h != dst_w || src_w != dst_h):
4347                 (src_w != dst_w || src_h != dst_h);
4348
4349         /*
4350          * if plane is being disabled or scaler is no more required or force detach
4351          *  - free scaler binded to this plane/crtc
4352          *  - in order to do this, update crtc->scaler_usage
4353          *
4354          * Here scaler state in crtc_state is set free so that
4355          * scaler can be assigned to other user. Actual register
4356          * update to free the scaler is done in plane/panel-fit programming.
4357          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4358          */
4359         if (force_detach || !need_scaling) {
4360                 if (*scaler_id >= 0) {
4361                         scaler_state->scaler_users &= ~(1 << scaler_user);
4362                         scaler_state->scalers[*scaler_id].in_use = 0;
4363
4364                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4365                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4366                                 intel_crtc->pipe, scaler_user, *scaler_id,
4367                                 scaler_state->scaler_users);
4368                         *scaler_id = -1;
4369                 }
4370                 return 0;
4371         }
4372
4373         /* range checks */
4374         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4375                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4376
4377                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4378                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4379                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4380                         "size is out of scaler range\n",
4381                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4382                 return -EINVAL;
4383         }
4384
4385         /* mark this plane as a scaler user in crtc_state */
4386         scaler_state->scaler_users |= (1 << scaler_user);
4387         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4388                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4389                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4390                 scaler_state->scaler_users);
4391
4392         return 0;
4393 }
4394
4395 /**
4396  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4397  *
4398  * @state: crtc's scaler state
4399  *
4400  * Return
4401  *     0 - scaler_usage updated successfully
4402  *    error - requested scaling cannot be supported or other error condition
4403  */
4404 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4405 {
4406         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4407         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4408
4409         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4410                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4411
4412         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4413                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4414                 state->pipe_src_w, state->pipe_src_h,
4415                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4416 }
4417
4418 /**
4419  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4420  *
4421  * @state: crtc's scaler state
4422  * @plane_state: atomic plane state to update
4423  *
4424  * Return
4425  *     0 - scaler_usage updated successfully
4426  *    error - requested scaling cannot be supported or other error condition
4427  */
4428 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4429                                    struct intel_plane_state *plane_state)
4430 {
4431
4432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4433         struct intel_plane *intel_plane =
4434                 to_intel_plane(plane_state->base.plane);
4435         struct drm_framebuffer *fb = plane_state->base.fb;
4436         int ret;
4437
4438         bool force_detach = !fb || !plane_state->visible;
4439
4440         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4441                       intel_plane->base.base.id, intel_crtc->pipe,
4442                       drm_plane_index(&intel_plane->base));
4443
4444         ret = skl_update_scaler(crtc_state, force_detach,
4445                                 drm_plane_index(&intel_plane->base),
4446                                 &plane_state->scaler_id,
4447                                 plane_state->base.rotation,
4448                                 drm_rect_width(&plane_state->src) >> 16,
4449                                 drm_rect_height(&plane_state->src) >> 16,
4450                                 drm_rect_width(&plane_state->dst),
4451                                 drm_rect_height(&plane_state->dst));
4452
4453         if (ret || plane_state->scaler_id < 0)
4454                 return ret;
4455
4456         /* check colorkey */
4457         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4458                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4459                               intel_plane->base.base.id);
4460                 return -EINVAL;
4461         }
4462
4463         /* Check src format */
4464         switch (fb->pixel_format) {
4465         case DRM_FORMAT_RGB565:
4466         case DRM_FORMAT_XBGR8888:
4467         case DRM_FORMAT_XRGB8888:
4468         case DRM_FORMAT_ABGR8888:
4469         case DRM_FORMAT_ARGB8888:
4470         case DRM_FORMAT_XRGB2101010:
4471         case DRM_FORMAT_XBGR2101010:
4472         case DRM_FORMAT_YUYV:
4473         case DRM_FORMAT_YVYU:
4474         case DRM_FORMAT_UYVY:
4475         case DRM_FORMAT_VYUY:
4476                 break;
4477         default:
4478                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4479                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4480                 return -EINVAL;
4481         }
4482
4483         return 0;
4484 }
4485
4486 static void skylake_scaler_disable(struct intel_crtc *crtc)
4487 {
4488         int i;
4489
4490         for (i = 0; i < crtc->num_scalers; i++)
4491                 skl_detach_scaler(crtc, i);
4492 }
4493
4494 static void skylake_pfit_enable(struct intel_crtc *crtc)
4495 {
4496         struct drm_device *dev = crtc->base.dev;
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498         int pipe = crtc->pipe;
4499         struct intel_crtc_scaler_state *scaler_state =
4500                 &crtc->config->scaler_state;
4501
4502         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4503
4504         if (crtc->config->pch_pfit.enabled) {
4505                 int id;
4506
4507                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4508                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4509                         return;
4510                 }
4511
4512                 id = scaler_state->scaler_id;
4513                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4514                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4515                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4516                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4517
4518                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4519         }
4520 }
4521
4522 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4523 {
4524         struct drm_device *dev = crtc->base.dev;
4525         struct drm_i915_private *dev_priv = dev->dev_private;
4526         int pipe = crtc->pipe;
4527
4528         if (crtc->config->pch_pfit.enabled) {
4529                 /* Force use of hard-coded filter coefficients
4530                  * as some pre-programmed values are broken,
4531                  * e.g. x201.
4532                  */
4533                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4534                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4535                                                  PF_PIPE_SEL_IVB(pipe));
4536                 else
4537                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4538                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4539                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4540         }
4541 }
4542
4543 void hsw_enable_ips(struct intel_crtc *crtc)
4544 {
4545         struct drm_device *dev = crtc->base.dev;
4546         struct drm_i915_private *dev_priv = dev->dev_private;
4547
4548         if (!crtc->config->ips_enabled)
4549                 return;
4550
4551         /* We can only enable IPS after we enable a plane and wait for a vblank */
4552         intel_wait_for_vblank(dev, crtc->pipe);
4553
4554         assert_plane_enabled(dev_priv, crtc->plane);
4555         if (IS_BROADWELL(dev)) {
4556                 mutex_lock(&dev_priv->rps.hw_lock);
4557                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4558                 mutex_unlock(&dev_priv->rps.hw_lock);
4559                 /* Quoting Art Runyan: "its not safe to expect any particular
4560                  * value in IPS_CTL bit 31 after enabling IPS through the
4561                  * mailbox." Moreover, the mailbox may return a bogus state,
4562                  * so we need to just enable it and continue on.
4563                  */
4564         } else {
4565                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4566                 /* The bit only becomes 1 in the next vblank, so this wait here
4567                  * is essentially intel_wait_for_vblank. If we don't have this
4568                  * and don't wait for vblanks until the end of crtc_enable, then
4569                  * the HW state readout code will complain that the expected
4570                  * IPS_CTL value is not the one we read. */
4571                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4572                         DRM_ERROR("Timed out waiting for IPS enable\n");
4573         }
4574 }
4575
4576 void hsw_disable_ips(struct intel_crtc *crtc)
4577 {
4578         struct drm_device *dev = crtc->base.dev;
4579         struct drm_i915_private *dev_priv = dev->dev_private;
4580
4581         if (!crtc->config->ips_enabled)
4582                 return;
4583
4584         assert_plane_enabled(dev_priv, crtc->plane);
4585         if (IS_BROADWELL(dev)) {
4586                 mutex_lock(&dev_priv->rps.hw_lock);
4587                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4588                 mutex_unlock(&dev_priv->rps.hw_lock);
4589                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4590                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4591                         DRM_ERROR("Timed out waiting for IPS disable\n");
4592         } else {
4593                 I915_WRITE(IPS_CTL, 0);
4594                 POSTING_READ(IPS_CTL);
4595         }
4596
4597         /* We need to wait for a vblank before we can disable the plane. */
4598         intel_wait_for_vblank(dev, crtc->pipe);
4599 }
4600
4601 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4602 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4603 {
4604         struct drm_device *dev = crtc->dev;
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4607         enum pipe pipe = intel_crtc->pipe;
4608         int i;
4609         bool reenable_ips = false;
4610
4611         /* The clocks have to be on to load the palette. */
4612         if (!crtc->state->active)
4613                 return;
4614
4615         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4616                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4617                         assert_dsi_pll_enabled(dev_priv);
4618                 else
4619                         assert_pll_enabled(dev_priv, pipe);
4620         }
4621
4622         /* Workaround : Do not read or write the pipe palette/gamma data while
4623          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4624          */
4625         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4626             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4627              GAMMA_MODE_MODE_SPLIT)) {
4628                 hsw_disable_ips(intel_crtc);
4629                 reenable_ips = true;
4630         }
4631
4632         for (i = 0; i < 256; i++) {
4633                 u32 palreg;
4634
4635                 if (HAS_GMCH_DISPLAY(dev))
4636                         palreg = PALETTE(pipe, i);
4637                 else
4638                         palreg = LGC_PALETTE(pipe, i);
4639
4640                 I915_WRITE(palreg,
4641                            (intel_crtc->lut_r[i] << 16) |
4642                            (intel_crtc->lut_g[i] << 8) |
4643                            intel_crtc->lut_b[i]);
4644         }
4645
4646         if (reenable_ips)
4647                 hsw_enable_ips(intel_crtc);
4648 }
4649
4650 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4651 {
4652         if (intel_crtc->overlay) {
4653                 struct drm_device *dev = intel_crtc->base.dev;
4654                 struct drm_i915_private *dev_priv = dev->dev_private;
4655
4656                 mutex_lock(&dev->struct_mutex);
4657                 dev_priv->mm.interruptible = false;
4658                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4659                 dev_priv->mm.interruptible = true;
4660                 mutex_unlock(&dev->struct_mutex);
4661         }
4662
4663         /* Let userspace switch the overlay on again. In most cases userspace
4664          * has to recompute where to put it anyway.
4665          */
4666 }
4667
4668 /**
4669  * intel_post_enable_primary - Perform operations after enabling primary plane
4670  * @crtc: the CRTC whose primary plane was just enabled
4671  *
4672  * Performs potentially sleeping operations that must be done after the primary
4673  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4674  * called due to an explicit primary plane update, or due to an implicit
4675  * re-enable that is caused when a sprite plane is updated to no longer
4676  * completely hide the primary plane.
4677  */
4678 static void
4679 intel_post_enable_primary(struct drm_crtc *crtc)
4680 {
4681         struct drm_device *dev = crtc->dev;
4682         struct drm_i915_private *dev_priv = dev->dev_private;
4683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4684         int pipe = intel_crtc->pipe;
4685
4686         /*
4687          * BDW signals flip done immediately if the plane
4688          * is disabled, even if the plane enable is already
4689          * armed to occur at the next vblank :(
4690          */
4691         if (IS_BROADWELL(dev))
4692                 intel_wait_for_vblank(dev, pipe);
4693
4694         /*
4695          * FIXME IPS should be fine as long as one plane is
4696          * enabled, but in practice it seems to have problems
4697          * when going from primary only to sprite only and vice
4698          * versa.
4699          */
4700         hsw_enable_ips(intel_crtc);
4701
4702         /*
4703          * Gen2 reports pipe underruns whenever all planes are disabled.
4704          * So don't enable underrun reporting before at least some planes
4705          * are enabled.
4706          * FIXME: Need to fix the logic to work when we turn off all planes
4707          * but leave the pipe running.
4708          */
4709         if (IS_GEN2(dev))
4710                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4711
4712         /* Underruns don't raise interrupts, so check manually. */
4713         if (HAS_GMCH_DISPLAY(dev))
4714                 i9xx_check_fifo_underruns(dev_priv);
4715 }
4716
4717 /**
4718  * intel_pre_disable_primary - Perform operations before disabling primary plane
4719  * @crtc: the CRTC whose primary plane is to be disabled
4720  *
4721  * Performs potentially sleeping operations that must be done before the
4722  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4723  * be called due to an explicit primary plane update, or due to an implicit
4724  * disable that is caused when a sprite plane completely hides the primary
4725  * plane.
4726  */
4727 static void
4728 intel_pre_disable_primary(struct drm_crtc *crtc)
4729 {
4730         struct drm_device *dev = crtc->dev;
4731         struct drm_i915_private *dev_priv = dev->dev_private;
4732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733         int pipe = intel_crtc->pipe;
4734
4735         /*
4736          * Gen2 reports pipe underruns whenever all planes are disabled.
4737          * So diasble underrun reporting before all the planes get disabled.
4738          * FIXME: Need to fix the logic to work when we turn off all planes
4739          * but leave the pipe running.
4740          */
4741         if (IS_GEN2(dev))
4742                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4743
4744         /*
4745          * Vblank time updates from the shadow to live plane control register
4746          * are blocked if the memory self-refresh mode is active at that
4747          * moment. So to make sure the plane gets truly disabled, disable
4748          * first the self-refresh mode. The self-refresh enable bit in turn
4749          * will be checked/applied by the HW only at the next frame start
4750          * event which is after the vblank start event, so we need to have a
4751          * wait-for-vblank between disabling the plane and the pipe.
4752          */
4753         if (HAS_GMCH_DISPLAY(dev)) {
4754                 intel_set_memory_cxsr(dev_priv, false);
4755                 dev_priv->wm.vlv.cxsr = false;
4756                 intel_wait_for_vblank(dev, pipe);
4757         }
4758
4759         /*
4760          * FIXME IPS should be fine as long as one plane is
4761          * enabled, but in practice it seems to have problems
4762          * when going from primary only to sprite only and vice
4763          * versa.
4764          */
4765         hsw_disable_ips(intel_crtc);
4766 }
4767
4768 static void intel_post_plane_update(struct intel_crtc *crtc)
4769 {
4770         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4771         struct drm_device *dev = crtc->base.dev;
4772         struct drm_i915_private *dev_priv = dev->dev_private;
4773         struct drm_plane *plane;
4774
4775         if (atomic->wait_vblank)
4776                 intel_wait_for_vblank(dev, crtc->pipe);
4777
4778         intel_frontbuffer_flip(dev, atomic->fb_bits);
4779
4780         if (atomic->disable_cxsr)
4781                 crtc->wm.cxsr_allowed = true;
4782
4783         if (crtc->atomic.update_wm_post)
4784                 intel_update_watermarks(&crtc->base);
4785
4786         if (atomic->update_fbc)
4787                 intel_fbc_update(dev_priv);
4788
4789         if (atomic->post_enable_primary)
4790                 intel_post_enable_primary(&crtc->base);
4791
4792         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4793                 intel_update_sprite_watermarks(plane, &crtc->base,
4794                                                0, 0, 0, false, false);
4795
4796         memset(atomic, 0, sizeof(*atomic));
4797 }
4798
4799 static void intel_pre_plane_update(struct intel_crtc *crtc)
4800 {
4801         struct drm_device *dev = crtc->base.dev;
4802         struct drm_i915_private *dev_priv = dev->dev_private;
4803         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4804
4805         if (atomic->wait_for_flips)
4806                 intel_crtc_wait_for_pending_flips(&crtc->base);
4807
4808         if (atomic->disable_fbc)
4809                 intel_fbc_disable_crtc(crtc);
4810
4811         if (crtc->atomic.disable_ips)
4812                 hsw_disable_ips(crtc);
4813
4814         if (atomic->pre_disable_primary)
4815                 intel_pre_disable_primary(&crtc->base);
4816
4817         if (atomic->disable_cxsr) {
4818                 crtc->wm.cxsr_allowed = false;
4819                 intel_set_memory_cxsr(dev_priv, false);
4820         }
4821 }
4822
4823 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4824 {
4825         struct drm_device *dev = crtc->dev;
4826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4827         struct drm_plane *p;
4828         int pipe = intel_crtc->pipe;
4829
4830         intel_crtc_dpms_overlay_disable(intel_crtc);
4831
4832         drm_for_each_plane_mask(p, dev, plane_mask)
4833                 to_intel_plane(p)->disable_plane(p, crtc);
4834
4835         /*
4836          * FIXME: Once we grow proper nuclear flip support out of this we need
4837          * to compute the mask of flip planes precisely. For the time being
4838          * consider this a flip to a NULL plane.
4839          */
4840         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4841 }
4842
4843 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4844 {
4845         struct drm_device *dev = crtc->dev;
4846         struct drm_i915_private *dev_priv = dev->dev_private;
4847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848         struct intel_encoder *encoder;
4849         int pipe = intel_crtc->pipe;
4850
4851         if (WARN_ON(intel_crtc->active))
4852                 return;
4853
4854         if (intel_crtc->config->has_pch_encoder)
4855                 intel_prepare_shared_dpll(intel_crtc);
4856
4857         if (intel_crtc->config->has_dp_encoder)
4858                 intel_dp_set_m_n(intel_crtc, M1_N1);
4859
4860         intel_set_pipe_timings(intel_crtc);
4861
4862         if (intel_crtc->config->has_pch_encoder) {
4863                 intel_cpu_transcoder_set_m_n(intel_crtc,
4864                                      &intel_crtc->config->fdi_m_n, NULL);
4865         }
4866
4867         ironlake_set_pipeconf(crtc);
4868
4869         intel_crtc->active = true;
4870
4871         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4872         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4873
4874         for_each_encoder_on_crtc(dev, crtc, encoder)
4875                 if (encoder->pre_enable)
4876                         encoder->pre_enable(encoder);
4877
4878         if (intel_crtc->config->has_pch_encoder) {
4879                 /* Note: FDI PLL enabling _must_ be done before we enable the
4880                  * cpu pipes, hence this is separate from all the other fdi/pch
4881                  * enabling. */
4882                 ironlake_fdi_pll_enable(intel_crtc);
4883         } else {
4884                 assert_fdi_tx_disabled(dev_priv, pipe);
4885                 assert_fdi_rx_disabled(dev_priv, pipe);
4886         }
4887
4888         ironlake_pfit_enable(intel_crtc);
4889
4890         /*
4891          * On ILK+ LUT must be loaded before the pipe is running but with
4892          * clocks enabled
4893          */
4894         intel_crtc_load_lut(crtc);
4895
4896         intel_update_watermarks(crtc);
4897         intel_enable_pipe(intel_crtc);
4898
4899         if (intel_crtc->config->has_pch_encoder)
4900                 ironlake_pch_enable(crtc);
4901
4902         assert_vblank_disabled(crtc);
4903         drm_crtc_vblank_on(crtc);
4904
4905         for_each_encoder_on_crtc(dev, crtc, encoder)
4906                 encoder->enable(encoder);
4907
4908         if (HAS_PCH_CPT(dev))
4909                 cpt_verify_modeset(dev, intel_crtc->pipe);
4910 }
4911
4912 /* IPS only exists on ULT machines and is tied to pipe A. */
4913 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4914 {
4915         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4916 }
4917
4918 static void haswell_crtc_enable(struct drm_crtc *crtc)
4919 {
4920         struct drm_device *dev = crtc->dev;
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923         struct intel_encoder *encoder;
4924         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4925         struct intel_crtc_state *pipe_config =
4926                 to_intel_crtc_state(crtc->state);
4927         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4928
4929         if (WARN_ON(intel_crtc->active))
4930                 return;
4931
4932         if (intel_crtc_to_shared_dpll(intel_crtc))
4933                 intel_enable_shared_dpll(intel_crtc);
4934
4935         if (intel_crtc->config->has_dp_encoder)
4936                 intel_dp_set_m_n(intel_crtc, M1_N1);
4937
4938         intel_set_pipe_timings(intel_crtc);
4939
4940         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4941                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4942                            intel_crtc->config->pixel_multiplier - 1);
4943         }
4944
4945         if (intel_crtc->config->has_pch_encoder) {
4946                 intel_cpu_transcoder_set_m_n(intel_crtc,
4947                                      &intel_crtc->config->fdi_m_n, NULL);
4948         }
4949
4950         haswell_set_pipeconf(crtc);
4951
4952         intel_set_pipe_csc(crtc);
4953
4954         intel_crtc->active = true;
4955
4956         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957         for_each_encoder_on_crtc(dev, crtc, encoder) {
4958                 if (encoder->pre_pll_enable)
4959                         encoder->pre_pll_enable(encoder);
4960                 if (encoder->pre_enable)
4961                         encoder->pre_enable(encoder);
4962         }
4963
4964         if (intel_crtc->config->has_pch_encoder) {
4965                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4966                                                       true);
4967                 dev_priv->display.fdi_link_train(crtc);
4968         }
4969
4970         if (!is_dsi)
4971                 intel_ddi_enable_pipe_clock(intel_crtc);
4972
4973         if (INTEL_INFO(dev)->gen >= 9)
4974                 skylake_pfit_enable(intel_crtc);
4975         else
4976                 ironlake_pfit_enable(intel_crtc);
4977
4978         /*
4979          * On ILK+ LUT must be loaded before the pipe is running but with
4980          * clocks enabled
4981          */
4982         intel_crtc_load_lut(crtc);
4983
4984         intel_ddi_set_pipe_settings(crtc);
4985         if (!is_dsi)
4986                 intel_ddi_enable_transcoder_func(crtc);
4987
4988         intel_update_watermarks(crtc);
4989         intel_enable_pipe(intel_crtc);
4990
4991         if (intel_crtc->config->has_pch_encoder)
4992                 lpt_pch_enable(crtc);
4993
4994         if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
4995                 intel_ddi_set_vc_payload_alloc(crtc, true);
4996
4997         assert_vblank_disabled(crtc);
4998         drm_crtc_vblank_on(crtc);
4999
5000         for_each_encoder_on_crtc(dev, crtc, encoder) {
5001                 encoder->enable(encoder);
5002                 intel_opregion_notify_encoder(encoder, true);
5003         }
5004
5005         /* If we change the relative order between pipe/planes enabling, we need
5006          * to change the workaround. */
5007         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5008         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5009                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5010                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5011         }
5012 }
5013
5014 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5015 {
5016         struct drm_device *dev = crtc->base.dev;
5017         struct drm_i915_private *dev_priv = dev->dev_private;
5018         int pipe = crtc->pipe;
5019
5020         /* To avoid upsetting the power well on haswell only disable the pfit if
5021          * it's in use. The hw state code will make sure we get this right. */
5022         if (force || crtc->config->pch_pfit.enabled) {
5023                 I915_WRITE(PF_CTL(pipe), 0);
5024                 I915_WRITE(PF_WIN_POS(pipe), 0);
5025                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5026         }
5027 }
5028
5029 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5030 {
5031         struct drm_device *dev = crtc->dev;
5032         struct drm_i915_private *dev_priv = dev->dev_private;
5033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5034         struct intel_encoder *encoder;
5035         int pipe = intel_crtc->pipe;
5036         u32 reg, temp;
5037
5038         for_each_encoder_on_crtc(dev, crtc, encoder)
5039                 encoder->disable(encoder);
5040
5041         drm_crtc_vblank_off(crtc);
5042         assert_vblank_disabled(crtc);
5043
5044         if (intel_crtc->config->has_pch_encoder)
5045                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5046
5047         intel_disable_pipe(intel_crtc);
5048
5049         ironlake_pfit_disable(intel_crtc, false);
5050
5051         if (intel_crtc->config->has_pch_encoder)
5052                 ironlake_fdi_disable(crtc);
5053
5054         for_each_encoder_on_crtc(dev, crtc, encoder)
5055                 if (encoder->post_disable)
5056                         encoder->post_disable(encoder);
5057
5058         if (intel_crtc->config->has_pch_encoder) {
5059                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5060
5061                 if (HAS_PCH_CPT(dev)) {
5062                         /* disable TRANS_DP_CTL */
5063                         reg = TRANS_DP_CTL(pipe);
5064                         temp = I915_READ(reg);
5065                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5066                                   TRANS_DP_PORT_SEL_MASK);
5067                         temp |= TRANS_DP_PORT_SEL_NONE;
5068                         I915_WRITE(reg, temp);
5069
5070                         /* disable DPLL_SEL */
5071                         temp = I915_READ(PCH_DPLL_SEL);
5072                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5073                         I915_WRITE(PCH_DPLL_SEL, temp);
5074                 }
5075
5076                 ironlake_fdi_pll_disable(intel_crtc);
5077         }
5078 }
5079
5080 static void haswell_crtc_disable(struct drm_crtc *crtc)
5081 {
5082         struct drm_device *dev = crtc->dev;
5083         struct drm_i915_private *dev_priv = dev->dev_private;
5084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5085         struct intel_encoder *encoder;
5086         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5087         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5088
5089         for_each_encoder_on_crtc(dev, crtc, encoder) {
5090                 intel_opregion_notify_encoder(encoder, false);
5091                 encoder->disable(encoder);
5092         }
5093
5094         drm_crtc_vblank_off(crtc);
5095         assert_vblank_disabled(crtc);
5096
5097         if (intel_crtc->config->has_pch_encoder)
5098                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5099                                                       false);
5100         intel_disable_pipe(intel_crtc);
5101
5102         if (intel_crtc->config->dp_encoder_is_mst)
5103                 intel_ddi_set_vc_payload_alloc(crtc, false);
5104
5105         if (!is_dsi)
5106                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5107
5108         if (INTEL_INFO(dev)->gen >= 9)
5109                 skylake_scaler_disable(intel_crtc);
5110         else
5111                 ironlake_pfit_disable(intel_crtc, false);
5112
5113         if (!is_dsi)
5114                 intel_ddi_disable_pipe_clock(intel_crtc);
5115
5116         if (intel_crtc->config->has_pch_encoder) {
5117                 lpt_disable_pch_transcoder(dev_priv);
5118                 intel_ddi_fdi_disable(crtc);
5119         }
5120
5121         for_each_encoder_on_crtc(dev, crtc, encoder)
5122                 if (encoder->post_disable)
5123                         encoder->post_disable(encoder);
5124 }
5125
5126 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5127 {
5128         struct drm_device *dev = crtc->base.dev;
5129         struct drm_i915_private *dev_priv = dev->dev_private;
5130         struct intel_crtc_state *pipe_config = crtc->config;
5131
5132         if (!pipe_config->gmch_pfit.control)
5133                 return;
5134
5135         /*
5136          * The panel fitter should only be adjusted whilst the pipe is disabled,
5137          * according to register description and PRM.
5138          */
5139         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5140         assert_pipe_disabled(dev_priv, crtc->pipe);
5141
5142         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5143         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5144
5145         /* Border color in case we don't scale up to the full screen. Black by
5146          * default, change to something else for debugging. */
5147         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5148 }
5149
5150 static enum intel_display_power_domain port_to_power_domain(enum port port)
5151 {
5152         switch (port) {
5153         case PORT_A:
5154                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5155         case PORT_B:
5156                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5157         case PORT_C:
5158                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5159         case PORT_D:
5160                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5161         case PORT_E:
5162                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5163         default:
5164                 WARN_ON_ONCE(1);
5165                 return POWER_DOMAIN_PORT_OTHER;
5166         }
5167 }
5168
5169 #define for_each_power_domain(domain, mask)                             \
5170         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5171                 if ((1 << (domain)) & (mask))
5172
5173 enum intel_display_power_domain
5174 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5175 {
5176         struct drm_device *dev = intel_encoder->base.dev;
5177         struct intel_digital_port *intel_dig_port;
5178
5179         switch (intel_encoder->type) {
5180         case INTEL_OUTPUT_UNKNOWN:
5181                 /* Only DDI platforms should ever use this output type */
5182                 WARN_ON_ONCE(!HAS_DDI(dev));
5183         case INTEL_OUTPUT_DISPLAYPORT:
5184         case INTEL_OUTPUT_HDMI:
5185         case INTEL_OUTPUT_EDP:
5186                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5187                 return port_to_power_domain(intel_dig_port->port);
5188         case INTEL_OUTPUT_DP_MST:
5189                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5190                 return port_to_power_domain(intel_dig_port->port);
5191         case INTEL_OUTPUT_ANALOG:
5192                 return POWER_DOMAIN_PORT_CRT;
5193         case INTEL_OUTPUT_DSI:
5194                 return POWER_DOMAIN_PORT_DSI;
5195         default:
5196                 return POWER_DOMAIN_PORT_OTHER;
5197         }
5198 }
5199
5200 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5201 {
5202         struct drm_device *dev = crtc->dev;
5203         struct intel_encoder *intel_encoder;
5204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5205         enum pipe pipe = intel_crtc->pipe;
5206         unsigned long mask;
5207         enum transcoder transcoder;
5208
5209         if (!crtc->state->active)
5210                 return 0;
5211
5212         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5213
5214         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5215         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5216         if (intel_crtc->config->pch_pfit.enabled ||
5217             intel_crtc->config->pch_pfit.force_thru)
5218                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5219
5220         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5221                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5222
5223         return mask;
5224 }
5225
5226 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5227 {
5228         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5230         enum intel_display_power_domain domain;
5231         unsigned long domains, new_domains, old_domains;
5232
5233         old_domains = intel_crtc->enabled_power_domains;
5234         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5235
5236         domains = new_domains & ~old_domains;
5237
5238         for_each_power_domain(domain, domains)
5239                 intel_display_power_get(dev_priv, domain);
5240
5241         return old_domains & ~new_domains;
5242 }
5243
5244 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5245                                       unsigned long domains)
5246 {
5247         enum intel_display_power_domain domain;
5248
5249         for_each_power_domain(domain, domains)
5250                 intel_display_power_put(dev_priv, domain);
5251 }
5252
5253 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5254 {
5255         struct drm_device *dev = state->dev;
5256         struct drm_i915_private *dev_priv = dev->dev_private;
5257         unsigned long put_domains[I915_MAX_PIPES] = {};
5258         struct drm_crtc_state *crtc_state;
5259         struct drm_crtc *crtc;
5260         int i;
5261
5262         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5263                 if (needs_modeset(crtc->state))
5264                         put_domains[to_intel_crtc(crtc)->pipe] =
5265                                 modeset_get_crtc_power_domains(crtc);
5266         }
5267
5268         if (dev_priv->display.modeset_commit_cdclk) {
5269                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5270
5271                 if (cdclk != dev_priv->cdclk_freq &&
5272                     !WARN_ON(!state->allow_modeset))
5273                         dev_priv->display.modeset_commit_cdclk(state);
5274         }
5275
5276         for (i = 0; i < I915_MAX_PIPES; i++)
5277                 if (put_domains[i])
5278                         modeset_put_power_domains(dev_priv, put_domains[i]);
5279 }
5280
5281 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5282 {
5283         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5284
5285         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5286             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5287                 return max_cdclk_freq;
5288         else if (IS_CHERRYVIEW(dev_priv))
5289                 return max_cdclk_freq*95/100;
5290         else if (INTEL_INFO(dev_priv)->gen < 4)
5291                 return 2*max_cdclk_freq*90/100;
5292         else
5293                 return max_cdclk_freq*90/100;
5294 }
5295
5296 static void intel_update_max_cdclk(struct drm_device *dev)
5297 {
5298         struct drm_i915_private *dev_priv = dev->dev_private;
5299
5300         if (IS_SKYLAKE(dev)) {
5301                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5302
5303                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5304                         dev_priv->max_cdclk_freq = 675000;
5305                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5306                         dev_priv->max_cdclk_freq = 540000;
5307                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5308                         dev_priv->max_cdclk_freq = 450000;
5309                 else
5310                         dev_priv->max_cdclk_freq = 337500;
5311         } else if (IS_BROADWELL(dev))  {
5312                 /*
5313                  * FIXME with extra cooling we can allow
5314                  * 540 MHz for ULX and 675 Mhz for ULT.
5315                  * How can we know if extra cooling is
5316                  * available? PCI ID, VTB, something else?
5317                  */
5318                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5319                         dev_priv->max_cdclk_freq = 450000;
5320                 else if (IS_BDW_ULX(dev))
5321                         dev_priv->max_cdclk_freq = 450000;
5322                 else if (IS_BDW_ULT(dev))
5323                         dev_priv->max_cdclk_freq = 540000;
5324                 else
5325                         dev_priv->max_cdclk_freq = 675000;
5326         } else if (IS_CHERRYVIEW(dev)) {
5327                 dev_priv->max_cdclk_freq = 320000;
5328         } else if (IS_VALLEYVIEW(dev)) {
5329                 dev_priv->max_cdclk_freq = 400000;
5330         } else {
5331                 /* otherwise assume cdclk is fixed */
5332                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5333         }
5334
5335         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5336
5337         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5338                          dev_priv->max_cdclk_freq);
5339
5340         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5341                          dev_priv->max_dotclk_freq);
5342 }
5343
5344 static void intel_update_cdclk(struct drm_device *dev)
5345 {
5346         struct drm_i915_private *dev_priv = dev->dev_private;
5347
5348         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5349         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5350                          dev_priv->cdclk_freq);
5351
5352         /*
5353          * Program the gmbus_freq based on the cdclk frequency.
5354          * BSpec erroneously claims we should aim for 4MHz, but
5355          * in fact 1MHz is the correct frequency.
5356          */
5357         if (IS_VALLEYVIEW(dev)) {
5358                 /*
5359                  * Program the gmbus_freq based on the cdclk frequency.
5360                  * BSpec erroneously claims we should aim for 4MHz, but
5361                  * in fact 1MHz is the correct frequency.
5362                  */
5363                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5364         }
5365
5366         if (dev_priv->max_cdclk_freq == 0)
5367                 intel_update_max_cdclk(dev);
5368 }
5369
5370 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5371 {
5372         struct drm_i915_private *dev_priv = dev->dev_private;
5373         uint32_t divider;
5374         uint32_t ratio;
5375         uint32_t current_freq;
5376         int ret;
5377
5378         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5379         switch (frequency) {
5380         case 144000:
5381                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5382                 ratio = BXT_DE_PLL_RATIO(60);
5383                 break;
5384         case 288000:
5385                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5386                 ratio = BXT_DE_PLL_RATIO(60);
5387                 break;
5388         case 384000:
5389                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5390                 ratio = BXT_DE_PLL_RATIO(60);
5391                 break;
5392         case 576000:
5393                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394                 ratio = BXT_DE_PLL_RATIO(60);
5395                 break;
5396         case 624000:
5397                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5398                 ratio = BXT_DE_PLL_RATIO(65);
5399                 break;
5400         case 19200:
5401                 /*
5402                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5403                  * to suppress GCC warning.
5404                  */
5405                 ratio = 0;
5406                 divider = 0;
5407                 break;
5408         default:
5409                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5410
5411                 return;
5412         }
5413
5414         mutex_lock(&dev_priv->rps.hw_lock);
5415         /* Inform power controller of upcoming frequency change */
5416         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5417                                       0x80000000);
5418         mutex_unlock(&dev_priv->rps.hw_lock);
5419
5420         if (ret) {
5421                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5422                           ret, frequency);
5423                 return;
5424         }
5425
5426         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5427         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5428         current_freq = current_freq * 500 + 1000;
5429
5430         /*
5431          * DE PLL has to be disabled when
5432          * - setting to 19.2MHz (bypass, PLL isn't used)
5433          * - before setting to 624MHz (PLL needs toggling)
5434          * - before setting to any frequency from 624MHz (PLL needs toggling)
5435          */
5436         if (frequency == 19200 || frequency == 624000 ||
5437             current_freq == 624000) {
5438                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5439                 /* Timeout 200us */
5440                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5441                              1))
5442                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5443         }
5444
5445         if (frequency != 19200) {
5446                 uint32_t val;
5447
5448                 val = I915_READ(BXT_DE_PLL_CTL);
5449                 val &= ~BXT_DE_PLL_RATIO_MASK;
5450                 val |= ratio;
5451                 I915_WRITE(BXT_DE_PLL_CTL, val);
5452
5453                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5454                 /* Timeout 200us */
5455                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5456                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5457
5458                 val = I915_READ(CDCLK_CTL);
5459                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5460                 val |= divider;
5461                 /*
5462                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5463                  * enable otherwise.
5464                  */
5465                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5466                 if (frequency >= 500000)
5467                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5468
5469                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5470                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5471                 val |= (frequency - 1000) / 500;
5472                 I915_WRITE(CDCLK_CTL, val);
5473         }
5474
5475         mutex_lock(&dev_priv->rps.hw_lock);
5476         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5477                                       DIV_ROUND_UP(frequency, 25000));
5478         mutex_unlock(&dev_priv->rps.hw_lock);
5479
5480         if (ret) {
5481                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5482                           ret, frequency);
5483                 return;
5484         }
5485
5486         intel_update_cdclk(dev);
5487 }
5488
5489 void broxton_init_cdclk(struct drm_device *dev)
5490 {
5491         struct drm_i915_private *dev_priv = dev->dev_private;
5492         uint32_t val;
5493
5494         /*
5495          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5496          * or else the reset will hang because there is no PCH to respond.
5497          * Move the handshake programming to initialization sequence.
5498          * Previously was left up to BIOS.
5499          */
5500         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5501         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5502         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5503
5504         /* Enable PG1 for cdclk */
5505         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5506
5507         /* check if cd clock is enabled */
5508         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5509                 DRM_DEBUG_KMS("Display already initialized\n");
5510                 return;
5511         }
5512
5513         /*
5514          * FIXME:
5515          * - The initial CDCLK needs to be read from VBT.
5516          *   Need to make this change after VBT has changes for BXT.
5517          * - check if setting the max (or any) cdclk freq is really necessary
5518          *   here, it belongs to modeset time
5519          */
5520         broxton_set_cdclk(dev, 624000);
5521
5522         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5523         POSTING_READ(DBUF_CTL);
5524
5525         udelay(10);
5526
5527         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5528                 DRM_ERROR("DBuf power enable timeout!\n");
5529 }
5530
5531 void broxton_uninit_cdclk(struct drm_device *dev)
5532 {
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534
5535         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5536         POSTING_READ(DBUF_CTL);
5537
5538         udelay(10);
5539
5540         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5541                 DRM_ERROR("DBuf power disable timeout!\n");
5542
5543         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5544         broxton_set_cdclk(dev, 19200);
5545
5546         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5547 }
5548
5549 static const struct skl_cdclk_entry {
5550         unsigned int freq;
5551         unsigned int vco;
5552 } skl_cdclk_frequencies[] = {
5553         { .freq = 308570, .vco = 8640 },
5554         { .freq = 337500, .vco = 8100 },
5555         { .freq = 432000, .vco = 8640 },
5556         { .freq = 450000, .vco = 8100 },
5557         { .freq = 540000, .vco = 8100 },
5558         { .freq = 617140, .vco = 8640 },
5559         { .freq = 675000, .vco = 8100 },
5560 };
5561
5562 static unsigned int skl_cdclk_decimal(unsigned int freq)
5563 {
5564         return (freq - 1000) / 500;
5565 }
5566
5567 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5568 {
5569         unsigned int i;
5570
5571         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5572                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5573
5574                 if (e->freq == freq)
5575                         return e->vco;
5576         }
5577
5578         return 8100;
5579 }
5580
5581 static void
5582 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5583 {
5584         unsigned int min_freq;
5585         u32 val;
5586
5587         /* select the minimum CDCLK before enabling DPLL 0 */
5588         val = I915_READ(CDCLK_CTL);
5589         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5590         val |= CDCLK_FREQ_337_308;
5591
5592         if (required_vco == 8640)
5593                 min_freq = 308570;
5594         else
5595                 min_freq = 337500;
5596
5597         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5598
5599         I915_WRITE(CDCLK_CTL, val);
5600         POSTING_READ(CDCLK_CTL);
5601
5602         /*
5603          * We always enable DPLL0 with the lowest link rate possible, but still
5604          * taking into account the VCO required to operate the eDP panel at the
5605          * desired frequency. The usual DP link rates operate with a VCO of
5606          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5607          * The modeset code is responsible for the selection of the exact link
5608          * rate later on, with the constraint of choosing a frequency that
5609          * works with required_vco.
5610          */
5611         val = I915_READ(DPLL_CTRL1);
5612
5613         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5614                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5615         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5616         if (required_vco == 8640)
5617                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5618                                             SKL_DPLL0);
5619         else
5620                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5621                                             SKL_DPLL0);
5622
5623         I915_WRITE(DPLL_CTRL1, val);
5624         POSTING_READ(DPLL_CTRL1);
5625
5626         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5627
5628         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5629                 DRM_ERROR("DPLL0 not locked\n");
5630 }
5631
5632 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5633 {
5634         int ret;
5635         u32 val;
5636
5637         /* inform PCU we want to change CDCLK */
5638         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5639         mutex_lock(&dev_priv->rps.hw_lock);
5640         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5641         mutex_unlock(&dev_priv->rps.hw_lock);
5642
5643         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5644 }
5645
5646 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5647 {
5648         unsigned int i;
5649
5650         for (i = 0; i < 15; i++) {
5651                 if (skl_cdclk_pcu_ready(dev_priv))
5652                         return true;
5653                 udelay(10);
5654         }
5655
5656         return false;
5657 }
5658
5659 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5660 {
5661         struct drm_device *dev = dev_priv->dev;
5662         u32 freq_select, pcu_ack;
5663
5664         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5665
5666         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5667                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5668                 return;
5669         }
5670
5671         /* set CDCLK_CTL */
5672         switch(freq) {
5673         case 450000:
5674         case 432000:
5675                 freq_select = CDCLK_FREQ_450_432;
5676                 pcu_ack = 1;
5677                 break;
5678         case 540000:
5679                 freq_select = CDCLK_FREQ_540;
5680                 pcu_ack = 2;
5681                 break;
5682         case 308570:
5683         case 337500:
5684         default:
5685                 freq_select = CDCLK_FREQ_337_308;
5686                 pcu_ack = 0;
5687                 break;
5688         case 617140:
5689         case 675000:
5690                 freq_select = CDCLK_FREQ_675_617;
5691                 pcu_ack = 3;
5692                 break;
5693         }
5694
5695         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5696         POSTING_READ(CDCLK_CTL);
5697
5698         /* inform PCU of the change */
5699         mutex_lock(&dev_priv->rps.hw_lock);
5700         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5701         mutex_unlock(&dev_priv->rps.hw_lock);
5702
5703         intel_update_cdclk(dev);
5704 }
5705
5706 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5707 {
5708         /* disable DBUF power */
5709         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5710         POSTING_READ(DBUF_CTL);
5711
5712         udelay(10);
5713
5714         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5715                 DRM_ERROR("DBuf power disable timeout\n");
5716
5717         /*
5718          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5719          */
5720         if (dev_priv->csr.dmc_payload) {
5721                 /* disable DPLL0 */
5722                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5723                                         ~LCPLL_PLL_ENABLE);
5724                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5725                         DRM_ERROR("Couldn't disable DPLL0\n");
5726         }
5727
5728         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5729 }
5730
5731 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5732 {
5733         u32 val;
5734         unsigned int required_vco;
5735
5736         /* enable PCH reset handshake */
5737         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5738         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5739
5740         /* enable PG1 and Misc I/O */
5741         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5742
5743         /* DPLL0 not enabled (happens on early BIOS versions) */
5744         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5745                 /* enable DPLL0 */
5746                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5747                 skl_dpll0_enable(dev_priv, required_vco);
5748         }
5749
5750         /* set CDCLK to the frequency the BIOS chose */
5751         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5752
5753         /* enable DBUF power */
5754         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5755         POSTING_READ(DBUF_CTL);
5756
5757         udelay(10);
5758
5759         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5760                 DRM_ERROR("DBuf power enable timeout\n");
5761 }
5762
5763 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5764 {
5765         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5766         uint32_t cdctl = I915_READ(CDCLK_CTL);
5767         int freq = dev_priv->skl_boot_cdclk;
5768
5769         /* Is PLL enabled and locked ? */
5770         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5771                 goto sanitize;
5772
5773         /* DPLL okay; verify the cdclock
5774          *
5775          * Noticed in some instances that the freq selection is correct but
5776          * decimal part is programmed wrong from BIOS where pre-os does not
5777          * enable display. Verify the same as well.
5778          */
5779         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5780                 /* All well; nothing to sanitize */
5781                 return false;
5782 sanitize:
5783         /*
5784          * As of now initialize with max cdclk till
5785          * we get dynamic cdclk support
5786          * */
5787         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5788         skl_init_cdclk(dev_priv);
5789
5790         /* we did have to sanitize */
5791         return true;
5792 }
5793
5794 /* Adjust CDclk dividers to allow high res or save power if possible */
5795 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5796 {
5797         struct drm_i915_private *dev_priv = dev->dev_private;
5798         u32 val, cmd;
5799
5800         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5801                                         != dev_priv->cdclk_freq);
5802
5803         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5804                 cmd = 2;
5805         else if (cdclk == 266667)
5806                 cmd = 1;
5807         else
5808                 cmd = 0;
5809
5810         mutex_lock(&dev_priv->rps.hw_lock);
5811         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5812         val &= ~DSPFREQGUAR_MASK;
5813         val |= (cmd << DSPFREQGUAR_SHIFT);
5814         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5815         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5816                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5817                      50)) {
5818                 DRM_ERROR("timed out waiting for CDclk change\n");
5819         }
5820         mutex_unlock(&dev_priv->rps.hw_lock);
5821
5822         mutex_lock(&dev_priv->sb_lock);
5823
5824         if (cdclk == 400000) {
5825                 u32 divider;
5826
5827                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5828
5829                 /* adjust cdclk divider */
5830                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5831                 val &= ~CCK_FREQUENCY_VALUES;
5832                 val |= divider;
5833                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5834
5835                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5836                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5837                              50))
5838                         DRM_ERROR("timed out waiting for CDclk change\n");
5839         }
5840
5841         /* adjust self-refresh exit latency value */
5842         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5843         val &= ~0x7f;
5844
5845         /*
5846          * For high bandwidth configs, we set a higher latency in the bunit
5847          * so that the core display fetch happens in time to avoid underruns.
5848          */
5849         if (cdclk == 400000)
5850                 val |= 4500 / 250; /* 4.5 usec */
5851         else
5852                 val |= 3000 / 250; /* 3.0 usec */
5853         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5854
5855         mutex_unlock(&dev_priv->sb_lock);
5856
5857         intel_update_cdclk(dev);
5858 }
5859
5860 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5861 {
5862         struct drm_i915_private *dev_priv = dev->dev_private;
5863         u32 val, cmd;
5864
5865         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5866                                                 != dev_priv->cdclk_freq);
5867
5868         switch (cdclk) {
5869         case 333333:
5870         case 320000:
5871         case 266667:
5872         case 200000:
5873                 break;
5874         default:
5875                 MISSING_CASE(cdclk);
5876                 return;
5877         }
5878
5879         /*
5880          * Specs are full of misinformation, but testing on actual
5881          * hardware has shown that we just need to write the desired
5882          * CCK divider into the Punit register.
5883          */
5884         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5885
5886         mutex_lock(&dev_priv->rps.hw_lock);
5887         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5888         val &= ~DSPFREQGUAR_MASK_CHV;
5889         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5890         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5891         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5892                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5893                      50)) {
5894                 DRM_ERROR("timed out waiting for CDclk change\n");
5895         }
5896         mutex_unlock(&dev_priv->rps.hw_lock);
5897
5898         intel_update_cdclk(dev);
5899 }
5900
5901 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5902                                  int max_pixclk)
5903 {
5904         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5905         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5906
5907         /*
5908          * Really only a few cases to deal with, as only 4 CDclks are supported:
5909          *   200MHz
5910          *   267MHz
5911          *   320/333MHz (depends on HPLL freq)
5912          *   400MHz (VLV only)
5913          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5914          * of the lower bin and adjust if needed.
5915          *
5916          * We seem to get an unstable or solid color picture at 200MHz.
5917          * Not sure what's wrong. For now use 200MHz only when all pipes
5918          * are off.
5919          */
5920         if (!IS_CHERRYVIEW(dev_priv) &&
5921             max_pixclk > freq_320*limit/100)
5922                 return 400000;
5923         else if (max_pixclk > 266667*limit/100)
5924                 return freq_320;
5925         else if (max_pixclk > 0)
5926                 return 266667;
5927         else
5928                 return 200000;
5929 }
5930
5931 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5932                               int max_pixclk)
5933 {
5934         /*
5935          * FIXME:
5936          * - remove the guardband, it's not needed on BXT
5937          * - set 19.2MHz bypass frequency if there are no active pipes
5938          */
5939         if (max_pixclk > 576000*9/10)
5940                 return 624000;
5941         else if (max_pixclk > 384000*9/10)
5942                 return 576000;
5943         else if (max_pixclk > 288000*9/10)
5944                 return 384000;
5945         else if (max_pixclk > 144000*9/10)
5946                 return 288000;
5947         else
5948                 return 144000;
5949 }
5950
5951 /* Compute the max pixel clock for new configuration. Uses atomic state if
5952  * that's non-NULL, look at current state otherwise. */
5953 static int intel_mode_max_pixclk(struct drm_device *dev,
5954                                  struct drm_atomic_state *state)
5955 {
5956         struct intel_crtc *intel_crtc;
5957         struct intel_crtc_state *crtc_state;
5958         int max_pixclk = 0;
5959
5960         for_each_intel_crtc(dev, intel_crtc) {
5961                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5962                 if (IS_ERR(crtc_state))
5963                         return PTR_ERR(crtc_state);
5964
5965                 if (!crtc_state->base.enable)
5966                         continue;
5967
5968                 max_pixclk = max(max_pixclk,
5969                                  crtc_state->base.adjusted_mode.crtc_clock);
5970         }
5971
5972         return max_pixclk;
5973 }
5974
5975 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5976 {
5977         struct drm_device *dev = state->dev;
5978         struct drm_i915_private *dev_priv = dev->dev_private;
5979         int max_pixclk = intel_mode_max_pixclk(dev, state);
5980
5981         if (max_pixclk < 0)
5982                 return max_pixclk;
5983
5984         to_intel_atomic_state(state)->cdclk =
5985                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5986
5987         return 0;
5988 }
5989
5990 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5991 {
5992         struct drm_device *dev = state->dev;
5993         struct drm_i915_private *dev_priv = dev->dev_private;
5994         int max_pixclk = intel_mode_max_pixclk(dev, state);
5995
5996         if (max_pixclk < 0)
5997                 return max_pixclk;
5998
5999         to_intel_atomic_state(state)->cdclk =
6000                 broxton_calc_cdclk(dev_priv, max_pixclk);
6001
6002         return 0;
6003 }
6004
6005 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6006 {
6007         unsigned int credits, default_credits;
6008
6009         if (IS_CHERRYVIEW(dev_priv))
6010                 default_credits = PFI_CREDIT(12);
6011         else
6012                 default_credits = PFI_CREDIT(8);
6013
6014         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6015                 /* CHV suggested value is 31 or 63 */
6016                 if (IS_CHERRYVIEW(dev_priv))
6017                         credits = PFI_CREDIT_63;
6018                 else
6019                         credits = PFI_CREDIT(15);
6020         } else {
6021                 credits = default_credits;
6022         }
6023
6024         /*
6025          * WA - write default credits before re-programming
6026          * FIXME: should we also set the resend bit here?
6027          */
6028         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6029                    default_credits);
6030
6031         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6032                    credits | PFI_CREDIT_RESEND);
6033
6034         /*
6035          * FIXME is this guaranteed to clear
6036          * immediately or should we poll for it?
6037          */
6038         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6039 }
6040
6041 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6042 {
6043         struct drm_device *dev = old_state->dev;
6044         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6045         struct drm_i915_private *dev_priv = dev->dev_private;
6046
6047         /*
6048          * FIXME: We can end up here with all power domains off, yet
6049          * with a CDCLK frequency other than the minimum. To account
6050          * for this take the PIPE-A power domain, which covers the HW
6051          * blocks needed for the following programming. This can be
6052          * removed once it's guaranteed that we get here either with
6053          * the minimum CDCLK set, or the required power domains
6054          * enabled.
6055          */
6056         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6057
6058         if (IS_CHERRYVIEW(dev))
6059                 cherryview_set_cdclk(dev, req_cdclk);
6060         else
6061                 valleyview_set_cdclk(dev, req_cdclk);
6062
6063         vlv_program_pfi_credits(dev_priv);
6064
6065         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6066 }
6067
6068 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6069 {
6070         struct drm_device *dev = crtc->dev;
6071         struct drm_i915_private *dev_priv = to_i915(dev);
6072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6073         struct intel_encoder *encoder;
6074         int pipe = intel_crtc->pipe;
6075         bool is_dsi;
6076
6077         if (WARN_ON(intel_crtc->active))
6078                 return;
6079
6080         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6081
6082         if (intel_crtc->config->has_dp_encoder)
6083                 intel_dp_set_m_n(intel_crtc, M1_N1);
6084
6085         intel_set_pipe_timings(intel_crtc);
6086
6087         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6088                 struct drm_i915_private *dev_priv = dev->dev_private;
6089
6090                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6091                 I915_WRITE(CHV_CANVAS(pipe), 0);
6092         }
6093
6094         i9xx_set_pipeconf(intel_crtc);
6095
6096         intel_crtc->active = true;
6097
6098         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6099
6100         for_each_encoder_on_crtc(dev, crtc, encoder)
6101                 if (encoder->pre_pll_enable)
6102                         encoder->pre_pll_enable(encoder);
6103
6104         if (!is_dsi) {
6105                 if (IS_CHERRYVIEW(dev)) {
6106                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6107                         chv_enable_pll(intel_crtc, intel_crtc->config);
6108                 } else {
6109                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6110                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6111                 }
6112         }
6113
6114         for_each_encoder_on_crtc(dev, crtc, encoder)
6115                 if (encoder->pre_enable)
6116                         encoder->pre_enable(encoder);
6117
6118         i9xx_pfit_enable(intel_crtc);
6119
6120         intel_crtc_load_lut(crtc);
6121
6122         intel_enable_pipe(intel_crtc);
6123
6124         assert_vblank_disabled(crtc);
6125         drm_crtc_vblank_on(crtc);
6126
6127         for_each_encoder_on_crtc(dev, crtc, encoder)
6128                 encoder->enable(encoder);
6129 }
6130
6131 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6132 {
6133         struct drm_device *dev = crtc->base.dev;
6134         struct drm_i915_private *dev_priv = dev->dev_private;
6135
6136         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6137         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6138 }
6139
6140 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6141 {
6142         struct drm_device *dev = crtc->dev;
6143         struct drm_i915_private *dev_priv = to_i915(dev);
6144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6145         struct intel_encoder *encoder;
6146         int pipe = intel_crtc->pipe;
6147
6148         if (WARN_ON(intel_crtc->active))
6149                 return;
6150
6151         i9xx_set_pll_dividers(intel_crtc);
6152
6153         if (intel_crtc->config->has_dp_encoder)
6154                 intel_dp_set_m_n(intel_crtc, M1_N1);
6155
6156         intel_set_pipe_timings(intel_crtc);
6157
6158         i9xx_set_pipeconf(intel_crtc);
6159
6160         intel_crtc->active = true;
6161
6162         if (!IS_GEN2(dev))
6163                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6164
6165         for_each_encoder_on_crtc(dev, crtc, encoder)
6166                 if (encoder->pre_enable)
6167                         encoder->pre_enable(encoder);
6168
6169         i9xx_enable_pll(intel_crtc);
6170
6171         i9xx_pfit_enable(intel_crtc);
6172
6173         intel_crtc_load_lut(crtc);
6174
6175         intel_update_watermarks(crtc);
6176         intel_enable_pipe(intel_crtc);
6177
6178         assert_vblank_disabled(crtc);
6179         drm_crtc_vblank_on(crtc);
6180
6181         for_each_encoder_on_crtc(dev, crtc, encoder)
6182                 encoder->enable(encoder);
6183 }
6184
6185 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6186 {
6187         struct drm_device *dev = crtc->base.dev;
6188         struct drm_i915_private *dev_priv = dev->dev_private;
6189
6190         if (!crtc->config->gmch_pfit.control)
6191                 return;
6192
6193         assert_pipe_disabled(dev_priv, crtc->pipe);
6194
6195         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6196                          I915_READ(PFIT_CONTROL));
6197         I915_WRITE(PFIT_CONTROL, 0);
6198 }
6199
6200 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6201 {
6202         struct drm_device *dev = crtc->dev;
6203         struct drm_i915_private *dev_priv = dev->dev_private;
6204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6205         struct intel_encoder *encoder;
6206         int pipe = intel_crtc->pipe;
6207
6208         /*
6209          * On gen2 planes are double buffered but the pipe isn't, so we must
6210          * wait for planes to fully turn off before disabling the pipe.
6211          * We also need to wait on all gmch platforms because of the
6212          * self-refresh mode constraint explained above.
6213          */
6214         intel_wait_for_vblank(dev, pipe);
6215
6216         for_each_encoder_on_crtc(dev, crtc, encoder)
6217                 encoder->disable(encoder);
6218
6219         drm_crtc_vblank_off(crtc);
6220         assert_vblank_disabled(crtc);
6221
6222         intel_disable_pipe(intel_crtc);
6223
6224         i9xx_pfit_disable(intel_crtc);
6225
6226         for_each_encoder_on_crtc(dev, crtc, encoder)
6227                 if (encoder->post_disable)
6228                         encoder->post_disable(encoder);
6229
6230         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6231                 if (IS_CHERRYVIEW(dev))
6232                         chv_disable_pll(dev_priv, pipe);
6233                 else if (IS_VALLEYVIEW(dev))
6234                         vlv_disable_pll(dev_priv, pipe);
6235                 else
6236                         i9xx_disable_pll(intel_crtc);
6237         }
6238
6239         for_each_encoder_on_crtc(dev, crtc, encoder)
6240                 if (encoder->post_pll_disable)
6241                         encoder->post_pll_disable(encoder);
6242
6243         if (!IS_GEN2(dev))
6244                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6245 }
6246
6247 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6248 {
6249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6250         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6251         enum intel_display_power_domain domain;
6252         unsigned long domains;
6253
6254         if (!intel_crtc->active)
6255                 return;
6256
6257         if (to_intel_plane_state(crtc->primary->state)->visible) {
6258                 intel_crtc_wait_for_pending_flips(crtc);
6259                 intel_pre_disable_primary(crtc);
6260         }
6261
6262         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6263         dev_priv->display.crtc_disable(crtc);
6264         intel_crtc->active = false;
6265         intel_update_watermarks(crtc);
6266         intel_disable_shared_dpll(intel_crtc);
6267
6268         domains = intel_crtc->enabled_power_domains;
6269         for_each_power_domain(domain, domains)
6270                 intel_display_power_put(dev_priv, domain);
6271         intel_crtc->enabled_power_domains = 0;
6272 }
6273
6274 /*
6275  * turn all crtc's off, but do not adjust state
6276  * This has to be paired with a call to intel_modeset_setup_hw_state.
6277  */
6278 int intel_display_suspend(struct drm_device *dev)
6279 {
6280         struct drm_mode_config *config = &dev->mode_config;
6281         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6282         struct drm_atomic_state *state;
6283         struct drm_crtc *crtc;
6284         unsigned crtc_mask = 0;
6285         int ret = 0;
6286
6287         if (WARN_ON(!ctx))
6288                 return 0;
6289
6290         lockdep_assert_held(&ctx->ww_ctx);
6291         state = drm_atomic_state_alloc(dev);
6292         if (WARN_ON(!state))
6293                 return -ENOMEM;
6294
6295         state->acquire_ctx = ctx;
6296         state->allow_modeset = true;
6297
6298         for_each_crtc(dev, crtc) {
6299                 struct drm_crtc_state *crtc_state =
6300                         drm_atomic_get_crtc_state(state, crtc);
6301
6302                 ret = PTR_ERR_OR_ZERO(crtc_state);
6303                 if (ret)
6304                         goto free;
6305
6306                 if (!crtc_state->active)
6307                         continue;
6308
6309                 crtc_state->active = false;
6310                 crtc_mask |= 1 << drm_crtc_index(crtc);
6311         }
6312
6313         if (crtc_mask) {
6314                 ret = drm_atomic_commit(state);
6315
6316                 if (!ret) {
6317                         for_each_crtc(dev, crtc)
6318                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6319                                         crtc->state->active = true;
6320
6321                         return ret;
6322                 }
6323         }
6324
6325 free:
6326         if (ret)
6327                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6328         drm_atomic_state_free(state);
6329         return ret;
6330 }
6331
6332 void intel_encoder_destroy(struct drm_encoder *encoder)
6333 {
6334         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6335
6336         drm_encoder_cleanup(encoder);
6337         kfree(intel_encoder);
6338 }
6339
6340 /* Cross check the actual hw state with our own modeset state tracking (and it's
6341  * internal consistency). */
6342 static void intel_connector_check_state(struct intel_connector *connector)
6343 {
6344         struct drm_crtc *crtc = connector->base.state->crtc;
6345
6346         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6347                       connector->base.base.id,
6348                       connector->base.name);
6349
6350         if (connector->get_hw_state(connector)) {
6351                 struct intel_encoder *encoder = connector->encoder;
6352                 struct drm_connector_state *conn_state = connector->base.state;
6353
6354                 I915_STATE_WARN(!crtc,
6355                          "connector enabled without attached crtc\n");
6356
6357                 if (!crtc)
6358                         return;
6359
6360                 I915_STATE_WARN(!crtc->state->active,
6361                       "connector is active, but attached crtc isn't\n");
6362
6363                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6364                         return;
6365
6366                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6367                         "atomic encoder doesn't match attached encoder\n");
6368
6369                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6370                         "attached encoder crtc differs from connector crtc\n");
6371         } else {
6372                 I915_STATE_WARN(crtc && crtc->state->active,
6373                         "attached crtc is active, but connector isn't\n");
6374                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6375                         "best encoder set without crtc!\n");
6376         }
6377 }
6378
6379 int intel_connector_init(struct intel_connector *connector)
6380 {
6381         struct drm_connector_state *connector_state;
6382
6383         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6384         if (!connector_state)
6385                 return -ENOMEM;
6386
6387         connector->base.state = connector_state;
6388         return 0;
6389 }
6390
6391 struct intel_connector *intel_connector_alloc(void)
6392 {
6393         struct intel_connector *connector;
6394
6395         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6396         if (!connector)
6397                 return NULL;
6398
6399         if (intel_connector_init(connector) < 0) {
6400                 kfree(connector);
6401                 return NULL;
6402         }
6403
6404         return connector;
6405 }
6406
6407 /* Simple connector->get_hw_state implementation for encoders that support only
6408  * one connector and no cloning and hence the encoder state determines the state
6409  * of the connector. */
6410 bool intel_connector_get_hw_state(struct intel_connector *connector)
6411 {
6412         enum pipe pipe = 0;
6413         struct intel_encoder *encoder = connector->encoder;
6414
6415         return encoder->get_hw_state(encoder, &pipe);
6416 }
6417
6418 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6419 {
6420         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6421                 return crtc_state->fdi_lanes;
6422
6423         return 0;
6424 }
6425
6426 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6427                                      struct intel_crtc_state *pipe_config)
6428 {
6429         struct drm_atomic_state *state = pipe_config->base.state;
6430         struct intel_crtc *other_crtc;
6431         struct intel_crtc_state *other_crtc_state;
6432
6433         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6434                       pipe_name(pipe), pipe_config->fdi_lanes);
6435         if (pipe_config->fdi_lanes > 4) {
6436                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6437                               pipe_name(pipe), pipe_config->fdi_lanes);
6438                 return -EINVAL;
6439         }
6440
6441         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6442                 if (pipe_config->fdi_lanes > 2) {
6443                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6444                                       pipe_config->fdi_lanes);
6445                         return -EINVAL;
6446                 } else {
6447                         return 0;
6448                 }
6449         }
6450
6451         if (INTEL_INFO(dev)->num_pipes == 2)
6452                 return 0;
6453
6454         /* Ivybridge 3 pipe is really complicated */
6455         switch (pipe) {
6456         case PIPE_A:
6457                 return 0;
6458         case PIPE_B:
6459                 if (pipe_config->fdi_lanes <= 2)
6460                         return 0;
6461
6462                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6463                 other_crtc_state =
6464                         intel_atomic_get_crtc_state(state, other_crtc);
6465                 if (IS_ERR(other_crtc_state))
6466                         return PTR_ERR(other_crtc_state);
6467
6468                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6469                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6470                                       pipe_name(pipe), pipe_config->fdi_lanes);
6471                         return -EINVAL;
6472                 }
6473                 return 0;
6474         case PIPE_C:
6475                 if (pipe_config->fdi_lanes > 2) {
6476                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6477                                       pipe_name(pipe), pipe_config->fdi_lanes);
6478                         return -EINVAL;
6479                 }
6480
6481                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6482                 other_crtc_state =
6483                         intel_atomic_get_crtc_state(state, other_crtc);
6484                 if (IS_ERR(other_crtc_state))
6485                         return PTR_ERR(other_crtc_state);
6486
6487                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6488                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6489                         return -EINVAL;
6490                 }
6491                 return 0;
6492         default:
6493                 BUG();
6494         }
6495 }
6496
6497 #define RETRY 1
6498 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6499                                        struct intel_crtc_state *pipe_config)
6500 {
6501         struct drm_device *dev = intel_crtc->base.dev;
6502         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6503         int lane, link_bw, fdi_dotclock, ret;
6504         bool needs_recompute = false;
6505
6506 retry:
6507         /* FDI is a binary signal running at ~2.7GHz, encoding
6508          * each output octet as 10 bits. The actual frequency
6509          * is stored as a divider into a 100MHz clock, and the
6510          * mode pixel clock is stored in units of 1KHz.
6511          * Hence the bw of each lane in terms of the mode signal
6512          * is:
6513          */
6514         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6515
6516         fdi_dotclock = adjusted_mode->crtc_clock;
6517
6518         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6519                                            pipe_config->pipe_bpp);
6520
6521         pipe_config->fdi_lanes = lane;
6522
6523         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6524                                link_bw, &pipe_config->fdi_m_n);
6525
6526         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6527                                        intel_crtc->pipe, pipe_config);
6528         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6529                 pipe_config->pipe_bpp -= 2*3;
6530                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6531                               pipe_config->pipe_bpp);
6532                 needs_recompute = true;
6533                 pipe_config->bw_constrained = true;
6534
6535                 goto retry;
6536         }
6537
6538         if (needs_recompute)
6539                 return RETRY;
6540
6541         return ret;
6542 }
6543
6544 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6545                                      struct intel_crtc_state *pipe_config)
6546 {
6547         if (pipe_config->pipe_bpp > 24)
6548                 return false;
6549
6550         /* HSW can handle pixel rate up to cdclk? */
6551         if (IS_HASWELL(dev_priv->dev))
6552                 return true;
6553
6554         /*
6555          * We compare against max which means we must take
6556          * the increased cdclk requirement into account when
6557          * calculating the new cdclk.
6558          *
6559          * Should measure whether using a lower cdclk w/o IPS
6560          */
6561         return ilk_pipe_pixel_rate(pipe_config) <=
6562                 dev_priv->max_cdclk_freq * 95 / 100;
6563 }
6564
6565 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6566                                    struct intel_crtc_state *pipe_config)
6567 {
6568         struct drm_device *dev = crtc->base.dev;
6569         struct drm_i915_private *dev_priv = dev->dev_private;
6570
6571         pipe_config->ips_enabled = i915.enable_ips &&
6572                 hsw_crtc_supports_ips(crtc) &&
6573                 pipe_config_supports_ips(dev_priv, pipe_config);
6574 }
6575
6576 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6577                                      struct intel_crtc_state *pipe_config)
6578 {
6579         struct drm_device *dev = crtc->base.dev;
6580         struct drm_i915_private *dev_priv = dev->dev_private;
6581         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6582
6583         /* FIXME should check pixel clock limits on all platforms */
6584         if (INTEL_INFO(dev)->gen < 4) {
6585                 int clock_limit = dev_priv->max_cdclk_freq;
6586
6587                 /*
6588                  * Enable pixel doubling when the dot clock
6589                  * is > 90% of the (display) core speed.
6590                  *
6591                  * GDG double wide on either pipe,
6592                  * otherwise pipe A only.
6593                  */
6594                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6595                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6596                         clock_limit *= 2;
6597                         pipe_config->double_wide = true;
6598                 }
6599
6600                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6601                         return -EINVAL;
6602         }
6603
6604         /*
6605          * Pipe horizontal size must be even in:
6606          * - DVO ganged mode
6607          * - LVDS dual channel mode
6608          * - Double wide pipe
6609          */
6610         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6611              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6612                 pipe_config->pipe_src_w &= ~1;
6613
6614         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6615          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6616          */
6617         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6618                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6619                 return -EINVAL;
6620
6621         if (HAS_IPS(dev))
6622                 hsw_compute_ips_config(crtc, pipe_config);
6623
6624         if (pipe_config->has_pch_encoder)
6625                 return ironlake_fdi_compute_config(crtc, pipe_config);
6626
6627         return 0;
6628 }
6629
6630 static int skylake_get_display_clock_speed(struct drm_device *dev)
6631 {
6632         struct drm_i915_private *dev_priv = to_i915(dev);
6633         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6634         uint32_t cdctl = I915_READ(CDCLK_CTL);
6635         uint32_t linkrate;
6636
6637         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6638                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6639
6640         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6641                 return 540000;
6642
6643         linkrate = (I915_READ(DPLL_CTRL1) &
6644                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6645
6646         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6647             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6648                 /* vco 8640 */
6649                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6650                 case CDCLK_FREQ_450_432:
6651                         return 432000;
6652                 case CDCLK_FREQ_337_308:
6653                         return 308570;
6654                 case CDCLK_FREQ_675_617:
6655                         return 617140;
6656                 default:
6657                         WARN(1, "Unknown cd freq selection\n");
6658                 }
6659         } else {
6660                 /* vco 8100 */
6661                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6662                 case CDCLK_FREQ_450_432:
6663                         return 450000;
6664                 case CDCLK_FREQ_337_308:
6665                         return 337500;
6666                 case CDCLK_FREQ_675_617:
6667                         return 675000;
6668                 default:
6669                         WARN(1, "Unknown cd freq selection\n");
6670                 }
6671         }
6672
6673         /* error case, do as if DPLL0 isn't enabled */
6674         return 24000;
6675 }
6676
6677 static int broxton_get_display_clock_speed(struct drm_device *dev)
6678 {
6679         struct drm_i915_private *dev_priv = to_i915(dev);
6680         uint32_t cdctl = I915_READ(CDCLK_CTL);
6681         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6682         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6683         int cdclk;
6684
6685         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6686                 return 19200;
6687
6688         cdclk = 19200 * pll_ratio / 2;
6689
6690         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6691         case BXT_CDCLK_CD2X_DIV_SEL_1:
6692                 return cdclk;  /* 576MHz or 624MHz */
6693         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6694                 return cdclk * 2 / 3; /* 384MHz */
6695         case BXT_CDCLK_CD2X_DIV_SEL_2:
6696                 return cdclk / 2; /* 288MHz */
6697         case BXT_CDCLK_CD2X_DIV_SEL_4:
6698                 return cdclk / 4; /* 144MHz */
6699         }
6700
6701         /* error case, do as if DE PLL isn't enabled */
6702         return 19200;
6703 }
6704
6705 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6706 {
6707         struct drm_i915_private *dev_priv = dev->dev_private;
6708         uint32_t lcpll = I915_READ(LCPLL_CTL);
6709         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6710
6711         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6712                 return 800000;
6713         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6714                 return 450000;
6715         else if (freq == LCPLL_CLK_FREQ_450)
6716                 return 450000;
6717         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6718                 return 540000;
6719         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6720                 return 337500;
6721         else
6722                 return 675000;
6723 }
6724
6725 static int haswell_get_display_clock_speed(struct drm_device *dev)
6726 {
6727         struct drm_i915_private *dev_priv = dev->dev_private;
6728         uint32_t lcpll = I915_READ(LCPLL_CTL);
6729         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6730
6731         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6732                 return 800000;
6733         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6734                 return 450000;
6735         else if (freq == LCPLL_CLK_FREQ_450)
6736                 return 450000;
6737         else if (IS_HSW_ULT(dev))
6738                 return 337500;
6739         else
6740                 return 540000;
6741 }
6742
6743 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6744 {
6745         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6746                                       CCK_DISPLAY_CLOCK_CONTROL);
6747 }
6748
6749 static int ilk_get_display_clock_speed(struct drm_device *dev)
6750 {
6751         return 450000;
6752 }
6753
6754 static int i945_get_display_clock_speed(struct drm_device *dev)
6755 {
6756         return 400000;
6757 }
6758
6759 static int i915_get_display_clock_speed(struct drm_device *dev)
6760 {
6761         return 333333;
6762 }
6763
6764 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6765 {
6766         return 200000;
6767 }
6768
6769 static int pnv_get_display_clock_speed(struct drm_device *dev)
6770 {
6771         u16 gcfgc = 0;
6772
6773         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6774
6775         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6776         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6777                 return 266667;
6778         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6779                 return 333333;
6780         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6781                 return 444444;
6782         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6783                 return 200000;
6784         default:
6785                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6786         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6787                 return 133333;
6788         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6789                 return 166667;
6790         }
6791 }
6792
6793 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6794 {
6795         u16 gcfgc = 0;
6796
6797         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6798
6799         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6800                 return 133333;
6801         else {
6802                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6803                 case GC_DISPLAY_CLOCK_333_MHZ:
6804                         return 333333;
6805                 default:
6806                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6807                         return 190000;
6808                 }
6809         }
6810 }
6811
6812 static int i865_get_display_clock_speed(struct drm_device *dev)
6813 {
6814         return 266667;
6815 }
6816
6817 static int i85x_get_display_clock_speed(struct drm_device *dev)
6818 {
6819         u16 hpllcc = 0;
6820
6821         /*
6822          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6823          * encoding is different :(
6824          * FIXME is this the right way to detect 852GM/852GMV?
6825          */
6826         if (dev->pdev->revision == 0x1)
6827                 return 133333;
6828
6829         pci_bus_read_config_word(dev->pdev->bus,
6830                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6831
6832         /* Assume that the hardware is in the high speed state.  This
6833          * should be the default.
6834          */
6835         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6836         case GC_CLOCK_133_200:
6837         case GC_CLOCK_133_200_2:
6838         case GC_CLOCK_100_200:
6839                 return 200000;
6840         case GC_CLOCK_166_250:
6841                 return 250000;
6842         case GC_CLOCK_100_133:
6843                 return 133333;
6844         case GC_CLOCK_133_266:
6845         case GC_CLOCK_133_266_2:
6846         case GC_CLOCK_166_266:
6847                 return 266667;
6848         }
6849
6850         /* Shouldn't happen */
6851         return 0;
6852 }
6853
6854 static int i830_get_display_clock_speed(struct drm_device *dev)
6855 {
6856         return 133333;
6857 }
6858
6859 static unsigned int intel_hpll_vco(struct drm_device *dev)
6860 {
6861         struct drm_i915_private *dev_priv = dev->dev_private;
6862         static const unsigned int blb_vco[8] = {
6863                 [0] = 3200000,
6864                 [1] = 4000000,
6865                 [2] = 5333333,
6866                 [3] = 4800000,
6867                 [4] = 6400000,
6868         };
6869         static const unsigned int pnv_vco[8] = {
6870                 [0] = 3200000,
6871                 [1] = 4000000,
6872                 [2] = 5333333,
6873                 [3] = 4800000,
6874                 [4] = 2666667,
6875         };
6876         static const unsigned int cl_vco[8] = {
6877                 [0] = 3200000,
6878                 [1] = 4000000,
6879                 [2] = 5333333,
6880                 [3] = 6400000,
6881                 [4] = 3333333,
6882                 [5] = 3566667,
6883                 [6] = 4266667,
6884         };
6885         static const unsigned int elk_vco[8] = {
6886                 [0] = 3200000,
6887                 [1] = 4000000,
6888                 [2] = 5333333,
6889                 [3] = 4800000,
6890         };
6891         static const unsigned int ctg_vco[8] = {
6892                 [0] = 3200000,
6893                 [1] = 4000000,
6894                 [2] = 5333333,
6895                 [3] = 6400000,
6896                 [4] = 2666667,
6897                 [5] = 4266667,
6898         };
6899         const unsigned int *vco_table;
6900         unsigned int vco;
6901         uint8_t tmp = 0;
6902
6903         /* FIXME other chipsets? */
6904         if (IS_GM45(dev))
6905                 vco_table = ctg_vco;
6906         else if (IS_G4X(dev))
6907                 vco_table = elk_vco;
6908         else if (IS_CRESTLINE(dev))
6909                 vco_table = cl_vco;
6910         else if (IS_PINEVIEW(dev))
6911                 vco_table = pnv_vco;
6912         else if (IS_G33(dev))
6913                 vco_table = blb_vco;
6914         else
6915                 return 0;
6916
6917         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6918
6919         vco = vco_table[tmp & 0x7];
6920         if (vco == 0)
6921                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6922         else
6923                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6924
6925         return vco;
6926 }
6927
6928 static int gm45_get_display_clock_speed(struct drm_device *dev)
6929 {
6930         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6931         uint16_t tmp = 0;
6932
6933         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6934
6935         cdclk_sel = (tmp >> 12) & 0x1;
6936
6937         switch (vco) {
6938         case 2666667:
6939         case 4000000:
6940         case 5333333:
6941                 return cdclk_sel ? 333333 : 222222;
6942         case 3200000:
6943                 return cdclk_sel ? 320000 : 228571;
6944         default:
6945                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6946                 return 222222;
6947         }
6948 }
6949
6950 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6951 {
6952         static const uint8_t div_3200[] = { 16, 10,  8 };
6953         static const uint8_t div_4000[] = { 20, 12, 10 };
6954         static const uint8_t div_5333[] = { 24, 16, 14 };
6955         const uint8_t *div_table;
6956         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6957         uint16_t tmp = 0;
6958
6959         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6960
6961         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6962
6963         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6964                 goto fail;
6965
6966         switch (vco) {
6967         case 3200000:
6968                 div_table = div_3200;
6969                 break;
6970         case 4000000:
6971                 div_table = div_4000;
6972                 break;
6973         case 5333333:
6974                 div_table = div_5333;
6975                 break;
6976         default:
6977                 goto fail;
6978         }
6979
6980         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6981
6982 fail:
6983         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6984         return 200000;
6985 }
6986
6987 static int g33_get_display_clock_speed(struct drm_device *dev)
6988 {
6989         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6990         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6991         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6992         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6993         const uint8_t *div_table;
6994         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6995         uint16_t tmp = 0;
6996
6997         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6998
6999         cdclk_sel = (tmp >> 4) & 0x7;
7000
7001         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7002                 goto fail;
7003
7004         switch (vco) {
7005         case 3200000:
7006                 div_table = div_3200;
7007                 break;
7008         case 4000000:
7009                 div_table = div_4000;
7010                 break;
7011         case 4800000:
7012                 div_table = div_4800;
7013                 break;
7014         case 5333333:
7015                 div_table = div_5333;
7016                 break;
7017         default:
7018                 goto fail;
7019         }
7020
7021         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7022
7023 fail:
7024         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7025         return 190476;
7026 }
7027
7028 static void
7029 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7030 {
7031         while (*num > DATA_LINK_M_N_MASK ||
7032                *den > DATA_LINK_M_N_MASK) {
7033                 *num >>= 1;
7034                 *den >>= 1;
7035         }
7036 }
7037
7038 static void compute_m_n(unsigned int m, unsigned int n,
7039                         uint32_t *ret_m, uint32_t *ret_n)
7040 {
7041         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7042         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7043         intel_reduce_m_n_ratio(ret_m, ret_n);
7044 }
7045
7046 void
7047 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7048                        int pixel_clock, int link_clock,
7049                        struct intel_link_m_n *m_n)
7050 {
7051         m_n->tu = 64;
7052
7053         compute_m_n(bits_per_pixel * pixel_clock,
7054                     link_clock * nlanes * 8,
7055                     &m_n->gmch_m, &m_n->gmch_n);
7056
7057         compute_m_n(pixel_clock, link_clock,
7058                     &m_n->link_m, &m_n->link_n);
7059 }
7060
7061 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7062 {
7063         if (i915.panel_use_ssc >= 0)
7064                 return i915.panel_use_ssc != 0;
7065         return dev_priv->vbt.lvds_use_ssc
7066                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7067 }
7068
7069 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7070                            int num_connectors)
7071 {
7072         struct drm_device *dev = crtc_state->base.crtc->dev;
7073         struct drm_i915_private *dev_priv = dev->dev_private;
7074         int refclk;
7075
7076         WARN_ON(!crtc_state->base.state);
7077
7078         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7079                 refclk = 100000;
7080         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7081             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7082                 refclk = dev_priv->vbt.lvds_ssc_freq;
7083                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7084         } else if (!IS_GEN2(dev)) {
7085                 refclk = 96000;
7086         } else {
7087                 refclk = 48000;
7088         }
7089
7090         return refclk;
7091 }
7092
7093 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7094 {
7095         return (1 << dpll->n) << 16 | dpll->m2;
7096 }
7097
7098 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7099 {
7100         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7101 }
7102
7103 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7104                                      struct intel_crtc_state *crtc_state,
7105                                      intel_clock_t *reduced_clock)
7106 {
7107         struct drm_device *dev = crtc->base.dev;
7108         u32 fp, fp2 = 0;
7109
7110         if (IS_PINEVIEW(dev)) {
7111                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7112                 if (reduced_clock)
7113                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7114         } else {
7115                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7116                 if (reduced_clock)
7117                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7118         }
7119
7120         crtc_state->dpll_hw_state.fp0 = fp;
7121
7122         crtc->lowfreq_avail = false;
7123         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7124             reduced_clock) {
7125                 crtc_state->dpll_hw_state.fp1 = fp2;
7126                 crtc->lowfreq_avail = true;
7127         } else {
7128                 crtc_state->dpll_hw_state.fp1 = fp;
7129         }
7130 }
7131
7132 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7133                 pipe)
7134 {
7135         u32 reg_val;
7136
7137         /*
7138          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7139          * and set it to a reasonable value instead.
7140          */
7141         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7142         reg_val &= 0xffffff00;
7143         reg_val |= 0x00000030;
7144         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7145
7146         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7147         reg_val &= 0x8cffffff;
7148         reg_val = 0x8c000000;
7149         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7150
7151         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7152         reg_val &= 0xffffff00;
7153         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7154
7155         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7156         reg_val &= 0x00ffffff;
7157         reg_val |= 0xb0000000;
7158         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7159 }
7160
7161 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7162                                          struct intel_link_m_n *m_n)
7163 {
7164         struct drm_device *dev = crtc->base.dev;
7165         struct drm_i915_private *dev_priv = dev->dev_private;
7166         int pipe = crtc->pipe;
7167
7168         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7169         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7170         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7171         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7172 }
7173
7174 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7175                                          struct intel_link_m_n *m_n,
7176                                          struct intel_link_m_n *m2_n2)
7177 {
7178         struct drm_device *dev = crtc->base.dev;
7179         struct drm_i915_private *dev_priv = dev->dev_private;
7180         int pipe = crtc->pipe;
7181         enum transcoder transcoder = crtc->config->cpu_transcoder;
7182
7183         if (INTEL_INFO(dev)->gen >= 5) {
7184                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7185                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7186                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7187                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7188                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7189                  * for gen < 8) and if DRRS is supported (to make sure the
7190                  * registers are not unnecessarily accessed).
7191                  */
7192                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7193                         crtc->config->has_drrs) {
7194                         I915_WRITE(PIPE_DATA_M2(transcoder),
7195                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7196                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7197                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7198                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7199                 }
7200         } else {
7201                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7202                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7203                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7204                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7205         }
7206 }
7207
7208 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7209 {
7210         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7211
7212         if (m_n == M1_N1) {
7213                 dp_m_n = &crtc->config->dp_m_n;
7214                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7215         } else if (m_n == M2_N2) {
7216
7217                 /*
7218                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7219                  * needs to be programmed into M1_N1.
7220                  */
7221                 dp_m_n = &crtc->config->dp_m2_n2;
7222         } else {
7223                 DRM_ERROR("Unsupported divider value\n");
7224                 return;
7225         }
7226
7227         if (crtc->config->has_pch_encoder)
7228                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7229         else
7230                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7231 }
7232
7233 static void vlv_compute_dpll(struct intel_crtc *crtc,
7234                              struct intel_crtc_state *pipe_config)
7235 {
7236         u32 dpll, dpll_md;
7237
7238         /*
7239          * Enable DPIO clock input. We should never disable the reference
7240          * clock for pipe B, since VGA hotplug / manual detection depends
7241          * on it.
7242          */
7243         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7244                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7245         /* We should never disable this, set it here for state tracking */
7246         if (crtc->pipe == PIPE_B)
7247                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7248         dpll |= DPLL_VCO_ENABLE;
7249         pipe_config->dpll_hw_state.dpll = dpll;
7250
7251         dpll_md = (pipe_config->pixel_multiplier - 1)
7252                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7253         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7254 }
7255
7256 static void vlv_prepare_pll(struct intel_crtc *crtc,
7257                             const struct intel_crtc_state *pipe_config)
7258 {
7259         struct drm_device *dev = crtc->base.dev;
7260         struct drm_i915_private *dev_priv = dev->dev_private;
7261         int pipe = crtc->pipe;
7262         u32 mdiv;
7263         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7264         u32 coreclk, reg_val;
7265
7266         mutex_lock(&dev_priv->sb_lock);
7267
7268         bestn = pipe_config->dpll.n;
7269         bestm1 = pipe_config->dpll.m1;
7270         bestm2 = pipe_config->dpll.m2;
7271         bestp1 = pipe_config->dpll.p1;
7272         bestp2 = pipe_config->dpll.p2;
7273
7274         /* See eDP HDMI DPIO driver vbios notes doc */
7275
7276         /* PLL B needs special handling */
7277         if (pipe == PIPE_B)
7278                 vlv_pllb_recal_opamp(dev_priv, pipe);
7279
7280         /* Set up Tx target for periodic Rcomp update */
7281         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7282
7283         /* Disable target IRef on PLL */
7284         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7285         reg_val &= 0x00ffffff;
7286         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7287
7288         /* Disable fast lock */
7289         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7290
7291         /* Set idtafcrecal before PLL is enabled */
7292         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7293         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7294         mdiv |= ((bestn << DPIO_N_SHIFT));
7295         mdiv |= (1 << DPIO_K_SHIFT);
7296
7297         /*
7298          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7299          * but we don't support that).
7300          * Note: don't use the DAC post divider as it seems unstable.
7301          */
7302         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7303         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7304
7305         mdiv |= DPIO_ENABLE_CALIBRATION;
7306         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7307
7308         /* Set HBR and RBR LPF coefficients */
7309         if (pipe_config->port_clock == 162000 ||
7310             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7311             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7312                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7313                                  0x009f0003);
7314         else
7315                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7316                                  0x00d0000f);
7317
7318         if (pipe_config->has_dp_encoder) {
7319                 /* Use SSC source */
7320                 if (pipe == PIPE_A)
7321                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7322                                          0x0df40000);
7323                 else
7324                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7325                                          0x0df70000);
7326         } else { /* HDMI or VGA */
7327                 /* Use bend source */
7328                 if (pipe == PIPE_A)
7329                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7330                                          0x0df70000);
7331                 else
7332                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7333                                          0x0df40000);
7334         }
7335
7336         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7337         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7338         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7339             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7340                 coreclk |= 0x01000000;
7341         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7342
7343         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7344         mutex_unlock(&dev_priv->sb_lock);
7345 }
7346
7347 static void chv_compute_dpll(struct intel_crtc *crtc,
7348                              struct intel_crtc_state *pipe_config)
7349 {
7350         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7351                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7352                 DPLL_VCO_ENABLE;
7353         if (crtc->pipe != PIPE_A)
7354                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7355
7356         pipe_config->dpll_hw_state.dpll_md =
7357                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7358 }
7359
7360 static void chv_prepare_pll(struct intel_crtc *crtc,
7361                             const struct intel_crtc_state *pipe_config)
7362 {
7363         struct drm_device *dev = crtc->base.dev;
7364         struct drm_i915_private *dev_priv = dev->dev_private;
7365         int pipe = crtc->pipe;
7366         int dpll_reg = DPLL(crtc->pipe);
7367         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7368         u32 loopfilter, tribuf_calcntr;
7369         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7370         u32 dpio_val;
7371         int vco;
7372
7373         bestn = pipe_config->dpll.n;
7374         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7375         bestm1 = pipe_config->dpll.m1;
7376         bestm2 = pipe_config->dpll.m2 >> 22;
7377         bestp1 = pipe_config->dpll.p1;
7378         bestp2 = pipe_config->dpll.p2;
7379         vco = pipe_config->dpll.vco;
7380         dpio_val = 0;
7381         loopfilter = 0;
7382
7383         /*
7384          * Enable Refclk and SSC
7385          */
7386         I915_WRITE(dpll_reg,
7387                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7388
7389         mutex_lock(&dev_priv->sb_lock);
7390
7391         /* p1 and p2 divider */
7392         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7393                         5 << DPIO_CHV_S1_DIV_SHIFT |
7394                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7395                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7396                         1 << DPIO_CHV_K_DIV_SHIFT);
7397
7398         /* Feedback post-divider - m2 */
7399         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7400
7401         /* Feedback refclk divider - n and m1 */
7402         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7403                         DPIO_CHV_M1_DIV_BY_2 |
7404                         1 << DPIO_CHV_N_DIV_SHIFT);
7405
7406         /* M2 fraction division */
7407         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7408
7409         /* M2 fraction division enable */
7410         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7411         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7412         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7413         if (bestm2_frac)
7414                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7415         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7416
7417         /* Program digital lock detect threshold */
7418         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7419         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7420                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7421         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7422         if (!bestm2_frac)
7423                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7424         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7425
7426         /* Loop filter */
7427         if (vco == 5400000) {
7428                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7429                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7430                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7431                 tribuf_calcntr = 0x9;
7432         } else if (vco <= 6200000) {
7433                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7434                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7435                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7436                 tribuf_calcntr = 0x9;
7437         } else if (vco <= 6480000) {
7438                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7439                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7440                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7441                 tribuf_calcntr = 0x8;
7442         } else {
7443                 /* Not supported. Apply the same limits as in the max case */
7444                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7445                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7446                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7447                 tribuf_calcntr = 0;
7448         }
7449         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7450
7451         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7452         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7453         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7454         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7455
7456         /* AFC Recal */
7457         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7458                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7459                         DPIO_AFC_RECAL);
7460
7461         mutex_unlock(&dev_priv->sb_lock);
7462 }
7463
7464 /**
7465  * vlv_force_pll_on - forcibly enable just the PLL
7466  * @dev_priv: i915 private structure
7467  * @pipe: pipe PLL to enable
7468  * @dpll: PLL configuration
7469  *
7470  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7471  * in cases where we need the PLL enabled even when @pipe is not going to
7472  * be enabled.
7473  */
7474 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7475                       const struct dpll *dpll)
7476 {
7477         struct intel_crtc *crtc =
7478                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7479         struct intel_crtc_state pipe_config = {
7480                 .base.crtc = &crtc->base,
7481                 .pixel_multiplier = 1,
7482                 .dpll = *dpll,
7483         };
7484
7485         if (IS_CHERRYVIEW(dev)) {
7486                 chv_compute_dpll(crtc, &pipe_config);
7487                 chv_prepare_pll(crtc, &pipe_config);
7488                 chv_enable_pll(crtc, &pipe_config);
7489         } else {
7490                 vlv_compute_dpll(crtc, &pipe_config);
7491                 vlv_prepare_pll(crtc, &pipe_config);
7492                 vlv_enable_pll(crtc, &pipe_config);
7493         }
7494 }
7495
7496 /**
7497  * vlv_force_pll_off - forcibly disable just the PLL
7498  * @dev_priv: i915 private structure
7499  * @pipe: pipe PLL to disable
7500  *
7501  * Disable the PLL for @pipe. To be used in cases where we need
7502  * the PLL enabled even when @pipe is not going to be enabled.
7503  */
7504 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7505 {
7506         if (IS_CHERRYVIEW(dev))
7507                 chv_disable_pll(to_i915(dev), pipe);
7508         else
7509                 vlv_disable_pll(to_i915(dev), pipe);
7510 }
7511
7512 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7513                               struct intel_crtc_state *crtc_state,
7514                               intel_clock_t *reduced_clock,
7515                               int num_connectors)
7516 {
7517         struct drm_device *dev = crtc->base.dev;
7518         struct drm_i915_private *dev_priv = dev->dev_private;
7519         u32 dpll;
7520         bool is_sdvo;
7521         struct dpll *clock = &crtc_state->dpll;
7522
7523         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7524
7525         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7526                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7527
7528         dpll = DPLL_VGA_MODE_DIS;
7529
7530         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7531                 dpll |= DPLLB_MODE_LVDS;
7532         else
7533                 dpll |= DPLLB_MODE_DAC_SERIAL;
7534
7535         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7536                 dpll |= (crtc_state->pixel_multiplier - 1)
7537                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7538         }
7539
7540         if (is_sdvo)
7541                 dpll |= DPLL_SDVO_HIGH_SPEED;
7542
7543         if (crtc_state->has_dp_encoder)
7544                 dpll |= DPLL_SDVO_HIGH_SPEED;
7545
7546         /* compute bitmask from p1 value */
7547         if (IS_PINEVIEW(dev))
7548                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7549         else {
7550                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7551                 if (IS_G4X(dev) && reduced_clock)
7552                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7553         }
7554         switch (clock->p2) {
7555         case 5:
7556                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7557                 break;
7558         case 7:
7559                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7560                 break;
7561         case 10:
7562                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7563                 break;
7564         case 14:
7565                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7566                 break;
7567         }
7568         if (INTEL_INFO(dev)->gen >= 4)
7569                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7570
7571         if (crtc_state->sdvo_tv_clock)
7572                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7573         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7574                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7575                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7576         else
7577                 dpll |= PLL_REF_INPUT_DREFCLK;
7578
7579         dpll |= DPLL_VCO_ENABLE;
7580         crtc_state->dpll_hw_state.dpll = dpll;
7581
7582         if (INTEL_INFO(dev)->gen >= 4) {
7583                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7584                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7585                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7586         }
7587 }
7588
7589 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7590                               struct intel_crtc_state *crtc_state,
7591                               intel_clock_t *reduced_clock,
7592                               int num_connectors)
7593 {
7594         struct drm_device *dev = crtc->base.dev;
7595         struct drm_i915_private *dev_priv = dev->dev_private;
7596         u32 dpll;
7597         struct dpll *clock = &crtc_state->dpll;
7598
7599         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7600
7601         dpll = DPLL_VGA_MODE_DIS;
7602
7603         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7604                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7605         } else {
7606                 if (clock->p1 == 2)
7607                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7608                 else
7609                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7610                 if (clock->p2 == 4)
7611                         dpll |= PLL_P2_DIVIDE_BY_4;
7612         }
7613
7614         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7615                 dpll |= DPLL_DVO_2X_MODE;
7616
7617         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7618                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7619                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7620         else
7621                 dpll |= PLL_REF_INPUT_DREFCLK;
7622
7623         dpll |= DPLL_VCO_ENABLE;
7624         crtc_state->dpll_hw_state.dpll = dpll;
7625 }
7626
7627 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7628 {
7629         struct drm_device *dev = intel_crtc->base.dev;
7630         struct drm_i915_private *dev_priv = dev->dev_private;
7631         enum pipe pipe = intel_crtc->pipe;
7632         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7633         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7634         uint32_t crtc_vtotal, crtc_vblank_end;
7635         int vsyncshift = 0;
7636
7637         /* We need to be careful not to changed the adjusted mode, for otherwise
7638          * the hw state checker will get angry at the mismatch. */
7639         crtc_vtotal = adjusted_mode->crtc_vtotal;
7640         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7641
7642         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7643                 /* the chip adds 2 halflines automatically */
7644                 crtc_vtotal -= 1;
7645                 crtc_vblank_end -= 1;
7646
7647                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7648                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7649                 else
7650                         vsyncshift = adjusted_mode->crtc_hsync_start -
7651                                 adjusted_mode->crtc_htotal / 2;
7652                 if (vsyncshift < 0)
7653                         vsyncshift += adjusted_mode->crtc_htotal;
7654         }
7655
7656         if (INTEL_INFO(dev)->gen > 3)
7657                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7658
7659         I915_WRITE(HTOTAL(cpu_transcoder),
7660                    (adjusted_mode->crtc_hdisplay - 1) |
7661                    ((adjusted_mode->crtc_htotal - 1) << 16));
7662         I915_WRITE(HBLANK(cpu_transcoder),
7663                    (adjusted_mode->crtc_hblank_start - 1) |
7664                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7665         I915_WRITE(HSYNC(cpu_transcoder),
7666                    (adjusted_mode->crtc_hsync_start - 1) |
7667                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7668
7669         I915_WRITE(VTOTAL(cpu_transcoder),
7670                    (adjusted_mode->crtc_vdisplay - 1) |
7671                    ((crtc_vtotal - 1) << 16));
7672         I915_WRITE(VBLANK(cpu_transcoder),
7673                    (adjusted_mode->crtc_vblank_start - 1) |
7674                    ((crtc_vblank_end - 1) << 16));
7675         I915_WRITE(VSYNC(cpu_transcoder),
7676                    (adjusted_mode->crtc_vsync_start - 1) |
7677                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7678
7679         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7680          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7681          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7682          * bits. */
7683         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7684             (pipe == PIPE_B || pipe == PIPE_C))
7685                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7686
7687         /* pipesrc controls the size that is scaled from, which should
7688          * always be the user's requested size.
7689          */
7690         I915_WRITE(PIPESRC(pipe),
7691                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7692                    (intel_crtc->config->pipe_src_h - 1));
7693 }
7694
7695 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7696                                    struct intel_crtc_state *pipe_config)
7697 {
7698         struct drm_device *dev = crtc->base.dev;
7699         struct drm_i915_private *dev_priv = dev->dev_private;
7700         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7701         uint32_t tmp;
7702
7703         tmp = I915_READ(HTOTAL(cpu_transcoder));
7704         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7705         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7706         tmp = I915_READ(HBLANK(cpu_transcoder));
7707         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7708         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7709         tmp = I915_READ(HSYNC(cpu_transcoder));
7710         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7711         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7712
7713         tmp = I915_READ(VTOTAL(cpu_transcoder));
7714         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7715         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7716         tmp = I915_READ(VBLANK(cpu_transcoder));
7717         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7718         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7719         tmp = I915_READ(VSYNC(cpu_transcoder));
7720         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7721         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7722
7723         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7724                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7725                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7726                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7727         }
7728
7729         tmp = I915_READ(PIPESRC(crtc->pipe));
7730         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7731         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7732
7733         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7734         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7735 }
7736
7737 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7738                                  struct intel_crtc_state *pipe_config)
7739 {
7740         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7741         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7742         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7743         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7744
7745         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7746         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7747         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7748         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7749
7750         mode->flags = pipe_config->base.adjusted_mode.flags;
7751         mode->type = DRM_MODE_TYPE_DRIVER;
7752
7753         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7754         mode->flags |= pipe_config->base.adjusted_mode.flags;
7755
7756         mode->hsync = drm_mode_hsync(mode);
7757         mode->vrefresh = drm_mode_vrefresh(mode);
7758         drm_mode_set_name(mode);
7759 }
7760
7761 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7762 {
7763         struct drm_device *dev = intel_crtc->base.dev;
7764         struct drm_i915_private *dev_priv = dev->dev_private;
7765         uint32_t pipeconf;
7766
7767         pipeconf = 0;
7768
7769         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7770             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7771                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7772
7773         if (intel_crtc->config->double_wide)
7774                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7775
7776         /* only g4x and later have fancy bpc/dither controls */
7777         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7778                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7779                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7780                         pipeconf |= PIPECONF_DITHER_EN |
7781                                     PIPECONF_DITHER_TYPE_SP;
7782
7783                 switch (intel_crtc->config->pipe_bpp) {
7784                 case 18:
7785                         pipeconf |= PIPECONF_6BPC;
7786                         break;
7787                 case 24:
7788                         pipeconf |= PIPECONF_8BPC;
7789                         break;
7790                 case 30:
7791                         pipeconf |= PIPECONF_10BPC;
7792                         break;
7793                 default:
7794                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7795                         BUG();
7796                 }
7797         }
7798
7799         if (HAS_PIPE_CXSR(dev)) {
7800                 if (intel_crtc->lowfreq_avail) {
7801                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7802                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7803                 } else {
7804                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7805                 }
7806         }
7807
7808         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7809                 if (INTEL_INFO(dev)->gen < 4 ||
7810                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7811                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7812                 else
7813                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7814         } else
7815                 pipeconf |= PIPECONF_PROGRESSIVE;
7816
7817         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7818                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7819
7820         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7821         POSTING_READ(PIPECONF(intel_crtc->pipe));
7822 }
7823
7824 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7825                                    struct intel_crtc_state *crtc_state)
7826 {
7827         struct drm_device *dev = crtc->base.dev;
7828         struct drm_i915_private *dev_priv = dev->dev_private;
7829         int refclk, num_connectors = 0;
7830         intel_clock_t clock;
7831         bool ok;
7832         bool is_dsi = false;
7833         struct intel_encoder *encoder;
7834         const intel_limit_t *limit;
7835         struct drm_atomic_state *state = crtc_state->base.state;
7836         struct drm_connector *connector;
7837         struct drm_connector_state *connector_state;
7838         int i;
7839
7840         memset(&crtc_state->dpll_hw_state, 0,
7841                sizeof(crtc_state->dpll_hw_state));
7842
7843         for_each_connector_in_state(state, connector, connector_state, i) {
7844                 if (connector_state->crtc != &crtc->base)
7845                         continue;
7846
7847                 encoder = to_intel_encoder(connector_state->best_encoder);
7848
7849                 switch (encoder->type) {
7850                 case INTEL_OUTPUT_DSI:
7851                         is_dsi = true;
7852                         break;
7853                 default:
7854                         break;
7855                 }
7856
7857                 num_connectors++;
7858         }
7859
7860         if (is_dsi)
7861                 return 0;
7862
7863         if (!crtc_state->clock_set) {
7864                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7865
7866                 /*
7867                  * Returns a set of divisors for the desired target clock with
7868                  * the given refclk, or FALSE.  The returned values represent
7869                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7870                  * 2) / p1 / p2.
7871                  */
7872                 limit = intel_limit(crtc_state, refclk);
7873                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7874                                                  crtc_state->port_clock,
7875                                                  refclk, NULL, &clock);
7876                 if (!ok) {
7877                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7878                         return -EINVAL;
7879                 }
7880
7881                 /* Compat-code for transition, will disappear. */
7882                 crtc_state->dpll.n = clock.n;
7883                 crtc_state->dpll.m1 = clock.m1;
7884                 crtc_state->dpll.m2 = clock.m2;
7885                 crtc_state->dpll.p1 = clock.p1;
7886                 crtc_state->dpll.p2 = clock.p2;
7887         }
7888
7889         if (IS_GEN2(dev)) {
7890                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7891                                   num_connectors);
7892         } else if (IS_CHERRYVIEW(dev)) {
7893                 chv_compute_dpll(crtc, crtc_state);
7894         } else if (IS_VALLEYVIEW(dev)) {
7895                 vlv_compute_dpll(crtc, crtc_state);
7896         } else {
7897                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7898                                   num_connectors);
7899         }
7900
7901         return 0;
7902 }
7903
7904 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7905                                  struct intel_crtc_state *pipe_config)
7906 {
7907         struct drm_device *dev = crtc->base.dev;
7908         struct drm_i915_private *dev_priv = dev->dev_private;
7909         uint32_t tmp;
7910
7911         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7912                 return;
7913
7914         tmp = I915_READ(PFIT_CONTROL);
7915         if (!(tmp & PFIT_ENABLE))
7916                 return;
7917
7918         /* Check whether the pfit is attached to our pipe. */
7919         if (INTEL_INFO(dev)->gen < 4) {
7920                 if (crtc->pipe != PIPE_B)
7921                         return;
7922         } else {
7923                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7924                         return;
7925         }
7926
7927         pipe_config->gmch_pfit.control = tmp;
7928         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7929         if (INTEL_INFO(dev)->gen < 5)
7930                 pipe_config->gmch_pfit.lvds_border_bits =
7931                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7932 }
7933
7934 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7935                                struct intel_crtc_state *pipe_config)
7936 {
7937         struct drm_device *dev = crtc->base.dev;
7938         struct drm_i915_private *dev_priv = dev->dev_private;
7939         int pipe = pipe_config->cpu_transcoder;
7940         intel_clock_t clock;
7941         u32 mdiv;
7942         int refclk = 100000;
7943
7944         /* In case of MIPI DPLL will not even be used */
7945         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7946                 return;
7947
7948         mutex_lock(&dev_priv->sb_lock);
7949         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7950         mutex_unlock(&dev_priv->sb_lock);
7951
7952         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7953         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7954         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7955         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7956         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7957
7958         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7959 }
7960
7961 static void
7962 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7963                               struct intel_initial_plane_config *plane_config)
7964 {
7965         struct drm_device *dev = crtc->base.dev;
7966         struct drm_i915_private *dev_priv = dev->dev_private;
7967         u32 val, base, offset;
7968         int pipe = crtc->pipe, plane = crtc->plane;
7969         int fourcc, pixel_format;
7970         unsigned int aligned_height;
7971         struct drm_framebuffer *fb;
7972         struct intel_framebuffer *intel_fb;
7973
7974         val = I915_READ(DSPCNTR(plane));
7975         if (!(val & DISPLAY_PLANE_ENABLE))
7976                 return;
7977
7978         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7979         if (!intel_fb) {
7980                 DRM_DEBUG_KMS("failed to alloc fb\n");
7981                 return;
7982         }
7983
7984         fb = &intel_fb->base;
7985
7986         if (INTEL_INFO(dev)->gen >= 4) {
7987                 if (val & DISPPLANE_TILED) {
7988                         plane_config->tiling = I915_TILING_X;
7989                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7990                 }
7991         }
7992
7993         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7994         fourcc = i9xx_format_to_fourcc(pixel_format);
7995         fb->pixel_format = fourcc;
7996         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7997
7998         if (INTEL_INFO(dev)->gen >= 4) {
7999                 if (plane_config->tiling)
8000                         offset = I915_READ(DSPTILEOFF(plane));
8001                 else
8002                         offset = I915_READ(DSPLINOFF(plane));
8003                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8004         } else {
8005                 base = I915_READ(DSPADDR(plane));
8006         }
8007         plane_config->base = base;
8008
8009         val = I915_READ(PIPESRC(pipe));
8010         fb->width = ((val >> 16) & 0xfff) + 1;
8011         fb->height = ((val >> 0) & 0xfff) + 1;
8012
8013         val = I915_READ(DSPSTRIDE(pipe));
8014         fb->pitches[0] = val & 0xffffffc0;
8015
8016         aligned_height = intel_fb_align_height(dev, fb->height,
8017                                                fb->pixel_format,
8018                                                fb->modifier[0]);
8019
8020         plane_config->size = fb->pitches[0] * aligned_height;
8021
8022         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8023                       pipe_name(pipe), plane, fb->width, fb->height,
8024                       fb->bits_per_pixel, base, fb->pitches[0],
8025                       plane_config->size);
8026
8027         plane_config->fb = intel_fb;
8028 }
8029
8030 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8031                                struct intel_crtc_state *pipe_config)
8032 {
8033         struct drm_device *dev = crtc->base.dev;
8034         struct drm_i915_private *dev_priv = dev->dev_private;
8035         int pipe = pipe_config->cpu_transcoder;
8036         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8037         intel_clock_t clock;
8038         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8039         int refclk = 100000;
8040
8041         mutex_lock(&dev_priv->sb_lock);
8042         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8043         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8044         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8045         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8046         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8047         mutex_unlock(&dev_priv->sb_lock);
8048
8049         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8050         clock.m2 = (pll_dw0 & 0xff) << 22;
8051         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8052                 clock.m2 |= pll_dw2 & 0x3fffff;
8053         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8054         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8055         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8056
8057         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8058 }
8059
8060 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8061                                  struct intel_crtc_state *pipe_config)
8062 {
8063         struct drm_device *dev = crtc->base.dev;
8064         struct drm_i915_private *dev_priv = dev->dev_private;
8065         uint32_t tmp;
8066
8067         if (!intel_display_power_is_enabled(dev_priv,
8068                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8069                 return false;
8070
8071         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8072         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8073
8074         tmp = I915_READ(PIPECONF(crtc->pipe));
8075         if (!(tmp & PIPECONF_ENABLE))
8076                 return false;
8077
8078         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8079                 switch (tmp & PIPECONF_BPC_MASK) {
8080                 case PIPECONF_6BPC:
8081                         pipe_config->pipe_bpp = 18;
8082                         break;
8083                 case PIPECONF_8BPC:
8084                         pipe_config->pipe_bpp = 24;
8085                         break;
8086                 case PIPECONF_10BPC:
8087                         pipe_config->pipe_bpp = 30;
8088                         break;
8089                 default:
8090                         break;
8091                 }
8092         }
8093
8094         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8095                 pipe_config->limited_color_range = true;
8096
8097         if (INTEL_INFO(dev)->gen < 4)
8098                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8099
8100         intel_get_pipe_timings(crtc, pipe_config);
8101
8102         i9xx_get_pfit_config(crtc, pipe_config);
8103
8104         if (INTEL_INFO(dev)->gen >= 4) {
8105                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8106                 pipe_config->pixel_multiplier =
8107                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8108                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8109                 pipe_config->dpll_hw_state.dpll_md = tmp;
8110         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8111                 tmp = I915_READ(DPLL(crtc->pipe));
8112                 pipe_config->pixel_multiplier =
8113                         ((tmp & SDVO_MULTIPLIER_MASK)
8114                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8115         } else {
8116                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8117                  * port and will be fixed up in the encoder->get_config
8118                  * function. */
8119                 pipe_config->pixel_multiplier = 1;
8120         }
8121         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8122         if (!IS_VALLEYVIEW(dev)) {
8123                 /*
8124                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8125                  * on 830. Filter it out here so that we don't
8126                  * report errors due to that.
8127                  */
8128                 if (IS_I830(dev))
8129                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8130
8131                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8132                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8133         } else {
8134                 /* Mask out read-only status bits. */
8135                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8136                                                      DPLL_PORTC_READY_MASK |
8137                                                      DPLL_PORTB_READY_MASK);
8138         }
8139
8140         if (IS_CHERRYVIEW(dev))
8141                 chv_crtc_clock_get(crtc, pipe_config);
8142         else if (IS_VALLEYVIEW(dev))
8143                 vlv_crtc_clock_get(crtc, pipe_config);
8144         else
8145                 i9xx_crtc_clock_get(crtc, pipe_config);
8146
8147         /*
8148          * Normally the dotclock is filled in by the encoder .get_config()
8149          * but in case the pipe is enabled w/o any ports we need a sane
8150          * default.
8151          */
8152         pipe_config->base.adjusted_mode.crtc_clock =
8153                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8154
8155         return true;
8156 }
8157
8158 static void ironlake_init_pch_refclk(struct drm_device *dev)
8159 {
8160         struct drm_i915_private *dev_priv = dev->dev_private;
8161         struct intel_encoder *encoder;
8162         u32 val, final;
8163         bool has_lvds = false;
8164         bool has_cpu_edp = false;
8165         bool has_panel = false;
8166         bool has_ck505 = false;
8167         bool can_ssc = false;
8168
8169         /* We need to take the global config into account */
8170         for_each_intel_encoder(dev, encoder) {
8171                 switch (encoder->type) {
8172                 case INTEL_OUTPUT_LVDS:
8173                         has_panel = true;
8174                         has_lvds = true;
8175                         break;
8176                 case INTEL_OUTPUT_EDP:
8177                         has_panel = true;
8178                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8179                                 has_cpu_edp = true;
8180                         break;
8181                 default:
8182                         break;
8183                 }
8184         }
8185
8186         if (HAS_PCH_IBX(dev)) {
8187                 has_ck505 = dev_priv->vbt.display_clock_mode;
8188                 can_ssc = has_ck505;
8189         } else {
8190                 has_ck505 = false;
8191                 can_ssc = true;
8192         }
8193
8194         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8195                       has_panel, has_lvds, has_ck505);
8196
8197         /* Ironlake: try to setup display ref clock before DPLL
8198          * enabling. This is only under driver's control after
8199          * PCH B stepping, previous chipset stepping should be
8200          * ignoring this setting.
8201          */
8202         val = I915_READ(PCH_DREF_CONTROL);
8203
8204         /* As we must carefully and slowly disable/enable each source in turn,
8205          * compute the final state we want first and check if we need to
8206          * make any changes at all.
8207          */
8208         final = val;
8209         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8210         if (has_ck505)
8211                 final |= DREF_NONSPREAD_CK505_ENABLE;
8212         else
8213                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8214
8215         final &= ~DREF_SSC_SOURCE_MASK;
8216         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8217         final &= ~DREF_SSC1_ENABLE;
8218
8219         if (has_panel) {
8220                 final |= DREF_SSC_SOURCE_ENABLE;
8221
8222                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8223                         final |= DREF_SSC1_ENABLE;
8224
8225                 if (has_cpu_edp) {
8226                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8227                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8228                         else
8229                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8230                 } else
8231                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8232         } else {
8233                 final |= DREF_SSC_SOURCE_DISABLE;
8234                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8235         }
8236
8237         if (final == val)
8238                 return;
8239
8240         /* Always enable nonspread source */
8241         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8242
8243         if (has_ck505)
8244                 val |= DREF_NONSPREAD_CK505_ENABLE;
8245         else
8246                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8247
8248         if (has_panel) {
8249                 val &= ~DREF_SSC_SOURCE_MASK;
8250                 val |= DREF_SSC_SOURCE_ENABLE;
8251
8252                 /* SSC must be turned on before enabling the CPU output  */
8253                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8254                         DRM_DEBUG_KMS("Using SSC on panel\n");
8255                         val |= DREF_SSC1_ENABLE;
8256                 } else
8257                         val &= ~DREF_SSC1_ENABLE;
8258
8259                 /* Get SSC going before enabling the outputs */
8260                 I915_WRITE(PCH_DREF_CONTROL, val);
8261                 POSTING_READ(PCH_DREF_CONTROL);
8262                 udelay(200);
8263
8264                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8265
8266                 /* Enable CPU source on CPU attached eDP */
8267                 if (has_cpu_edp) {
8268                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8269                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8270                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8271                         } else
8272                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8273                 } else
8274                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8275
8276                 I915_WRITE(PCH_DREF_CONTROL, val);
8277                 POSTING_READ(PCH_DREF_CONTROL);
8278                 udelay(200);
8279         } else {
8280                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8281
8282                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8283
8284                 /* Turn off CPU output */
8285                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8286
8287                 I915_WRITE(PCH_DREF_CONTROL, val);
8288                 POSTING_READ(PCH_DREF_CONTROL);
8289                 udelay(200);
8290
8291                 /* Turn off the SSC source */
8292                 val &= ~DREF_SSC_SOURCE_MASK;
8293                 val |= DREF_SSC_SOURCE_DISABLE;
8294
8295                 /* Turn off SSC1 */
8296                 val &= ~DREF_SSC1_ENABLE;
8297
8298                 I915_WRITE(PCH_DREF_CONTROL, val);
8299                 POSTING_READ(PCH_DREF_CONTROL);
8300                 udelay(200);
8301         }
8302
8303         BUG_ON(val != final);
8304 }
8305
8306 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8307 {
8308         uint32_t tmp;
8309
8310         tmp = I915_READ(SOUTH_CHICKEN2);
8311         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8312         I915_WRITE(SOUTH_CHICKEN2, tmp);
8313
8314         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8315                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8316                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8317
8318         tmp = I915_READ(SOUTH_CHICKEN2);
8319         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8320         I915_WRITE(SOUTH_CHICKEN2, tmp);
8321
8322         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8323                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8324                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8325 }
8326
8327 /* WaMPhyProgramming:hsw */
8328 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8329 {
8330         uint32_t tmp;
8331
8332         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8333         tmp &= ~(0xFF << 24);
8334         tmp |= (0x12 << 24);
8335         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8336
8337         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8338         tmp |= (1 << 11);
8339         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8340
8341         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8342         tmp |= (1 << 11);
8343         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8344
8345         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8346         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8347         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8348
8349         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8350         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8351         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8352
8353         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8354         tmp &= ~(7 << 13);
8355         tmp |= (5 << 13);
8356         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8357
8358         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8359         tmp &= ~(7 << 13);
8360         tmp |= (5 << 13);
8361         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8362
8363         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8364         tmp &= ~0xFF;
8365         tmp |= 0x1C;
8366         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8367
8368         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8369         tmp &= ~0xFF;
8370         tmp |= 0x1C;
8371         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8372
8373         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8374         tmp &= ~(0xFF << 16);
8375         tmp |= (0x1C << 16);
8376         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8377
8378         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8379         tmp &= ~(0xFF << 16);
8380         tmp |= (0x1C << 16);
8381         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8382
8383         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8384         tmp |= (1 << 27);
8385         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8386
8387         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8388         tmp |= (1 << 27);
8389         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8390
8391         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8392         tmp &= ~(0xF << 28);
8393         tmp |= (4 << 28);
8394         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8395
8396         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8397         tmp &= ~(0xF << 28);
8398         tmp |= (4 << 28);
8399         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8400 }
8401
8402 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8403  * Programming" based on the parameters passed:
8404  * - Sequence to enable CLKOUT_DP
8405  * - Sequence to enable CLKOUT_DP without spread
8406  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8407  */
8408 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8409                                  bool with_fdi)
8410 {
8411         struct drm_i915_private *dev_priv = dev->dev_private;
8412         uint32_t reg, tmp;
8413
8414         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8415                 with_spread = true;
8416         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8417                 with_fdi = false;
8418
8419         mutex_lock(&dev_priv->sb_lock);
8420
8421         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8422         tmp &= ~SBI_SSCCTL_DISABLE;
8423         tmp |= SBI_SSCCTL_PATHALT;
8424         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8425
8426         udelay(24);
8427
8428         if (with_spread) {
8429                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8430                 tmp &= ~SBI_SSCCTL_PATHALT;
8431                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8432
8433                 if (with_fdi) {
8434                         lpt_reset_fdi_mphy(dev_priv);
8435                         lpt_program_fdi_mphy(dev_priv);
8436                 }
8437         }
8438
8439         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8440         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8441         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8442         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8443
8444         mutex_unlock(&dev_priv->sb_lock);
8445 }
8446
8447 /* Sequence to disable CLKOUT_DP */
8448 static void lpt_disable_clkout_dp(struct drm_device *dev)
8449 {
8450         struct drm_i915_private *dev_priv = dev->dev_private;
8451         uint32_t reg, tmp;
8452
8453         mutex_lock(&dev_priv->sb_lock);
8454
8455         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8456         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8457         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8458         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8459
8460         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8461         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8462                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8463                         tmp |= SBI_SSCCTL_PATHALT;
8464                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8465                         udelay(32);
8466                 }
8467                 tmp |= SBI_SSCCTL_DISABLE;
8468                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8469         }
8470
8471         mutex_unlock(&dev_priv->sb_lock);
8472 }
8473
8474 static void lpt_init_pch_refclk(struct drm_device *dev)
8475 {
8476         struct intel_encoder *encoder;
8477         bool has_vga = false;
8478
8479         for_each_intel_encoder(dev, encoder) {
8480                 switch (encoder->type) {
8481                 case INTEL_OUTPUT_ANALOG:
8482                         has_vga = true;
8483                         break;
8484                 default:
8485                         break;
8486                 }
8487         }
8488
8489         if (has_vga)
8490                 lpt_enable_clkout_dp(dev, true, true);
8491         else
8492                 lpt_disable_clkout_dp(dev);
8493 }
8494
8495 /*
8496  * Initialize reference clocks when the driver loads
8497  */
8498 void intel_init_pch_refclk(struct drm_device *dev)
8499 {
8500         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8501                 ironlake_init_pch_refclk(dev);
8502         else if (HAS_PCH_LPT(dev))
8503                 lpt_init_pch_refclk(dev);
8504 }
8505
8506 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8507 {
8508         struct drm_device *dev = crtc_state->base.crtc->dev;
8509         struct drm_i915_private *dev_priv = dev->dev_private;
8510         struct drm_atomic_state *state = crtc_state->base.state;
8511         struct drm_connector *connector;
8512         struct drm_connector_state *connector_state;
8513         struct intel_encoder *encoder;
8514         int num_connectors = 0, i;
8515         bool is_lvds = false;
8516
8517         for_each_connector_in_state(state, connector, connector_state, i) {
8518                 if (connector_state->crtc != crtc_state->base.crtc)
8519                         continue;
8520
8521                 encoder = to_intel_encoder(connector_state->best_encoder);
8522
8523                 switch (encoder->type) {
8524                 case INTEL_OUTPUT_LVDS:
8525                         is_lvds = true;
8526                         break;
8527                 default:
8528                         break;
8529                 }
8530                 num_connectors++;
8531         }
8532
8533         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8534                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8535                               dev_priv->vbt.lvds_ssc_freq);
8536                 return dev_priv->vbt.lvds_ssc_freq;
8537         }
8538
8539         return 120000;
8540 }
8541
8542 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8543 {
8544         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8546         int pipe = intel_crtc->pipe;
8547         uint32_t val;
8548
8549         val = 0;
8550
8551         switch (intel_crtc->config->pipe_bpp) {
8552         case 18:
8553                 val |= PIPECONF_6BPC;
8554                 break;
8555         case 24:
8556                 val |= PIPECONF_8BPC;
8557                 break;
8558         case 30:
8559                 val |= PIPECONF_10BPC;
8560                 break;
8561         case 36:
8562                 val |= PIPECONF_12BPC;
8563                 break;
8564         default:
8565                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8566                 BUG();
8567         }
8568
8569         if (intel_crtc->config->dither)
8570                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8571
8572         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8573                 val |= PIPECONF_INTERLACED_ILK;
8574         else
8575                 val |= PIPECONF_PROGRESSIVE;
8576
8577         if (intel_crtc->config->limited_color_range)
8578                 val |= PIPECONF_COLOR_RANGE_SELECT;
8579
8580         I915_WRITE(PIPECONF(pipe), val);
8581         POSTING_READ(PIPECONF(pipe));
8582 }
8583
8584 /*
8585  * Set up the pipe CSC unit.
8586  *
8587  * Currently only full range RGB to limited range RGB conversion
8588  * is supported, but eventually this should handle various
8589  * RGB<->YCbCr scenarios as well.
8590  */
8591 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8592 {
8593         struct drm_device *dev = crtc->dev;
8594         struct drm_i915_private *dev_priv = dev->dev_private;
8595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8596         int pipe = intel_crtc->pipe;
8597         uint16_t coeff = 0x7800; /* 1.0 */
8598
8599         /*
8600          * TODO: Check what kind of values actually come out of the pipe
8601          * with these coeff/postoff values and adjust to get the best
8602          * accuracy. Perhaps we even need to take the bpc value into
8603          * consideration.
8604          */
8605
8606         if (intel_crtc->config->limited_color_range)
8607                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8608
8609         /*
8610          * GY/GU and RY/RU should be the other way around according
8611          * to BSpec, but reality doesn't agree. Just set them up in
8612          * a way that results in the correct picture.
8613          */
8614         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8615         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8616
8617         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8618         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8619
8620         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8621         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8622
8623         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8624         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8625         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8626
8627         if (INTEL_INFO(dev)->gen > 6) {
8628                 uint16_t postoff = 0;
8629
8630                 if (intel_crtc->config->limited_color_range)
8631                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8632
8633                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8634                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8635                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8636
8637                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8638         } else {
8639                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8640
8641                 if (intel_crtc->config->limited_color_range)
8642                         mode |= CSC_BLACK_SCREEN_OFFSET;
8643
8644                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8645         }
8646 }
8647
8648 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8649 {
8650         struct drm_device *dev = crtc->dev;
8651         struct drm_i915_private *dev_priv = dev->dev_private;
8652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8653         enum pipe pipe = intel_crtc->pipe;
8654         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8655         uint32_t val;
8656
8657         val = 0;
8658
8659         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8660                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8661
8662         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8663                 val |= PIPECONF_INTERLACED_ILK;
8664         else
8665                 val |= PIPECONF_PROGRESSIVE;
8666
8667         I915_WRITE(PIPECONF(cpu_transcoder), val);
8668         POSTING_READ(PIPECONF(cpu_transcoder));
8669
8670         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8671         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8672
8673         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8674                 val = 0;
8675
8676                 switch (intel_crtc->config->pipe_bpp) {
8677                 case 18:
8678                         val |= PIPEMISC_DITHER_6_BPC;
8679                         break;
8680                 case 24:
8681                         val |= PIPEMISC_DITHER_8_BPC;
8682                         break;
8683                 case 30:
8684                         val |= PIPEMISC_DITHER_10_BPC;
8685                         break;
8686                 case 36:
8687                         val |= PIPEMISC_DITHER_12_BPC;
8688                         break;
8689                 default:
8690                         /* Case prevented by pipe_config_set_bpp. */
8691                         BUG();
8692                 }
8693
8694                 if (intel_crtc->config->dither)
8695                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8696
8697                 I915_WRITE(PIPEMISC(pipe), val);
8698         }
8699 }
8700
8701 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8702                                     struct intel_crtc_state *crtc_state,
8703                                     intel_clock_t *clock,
8704                                     bool *has_reduced_clock,
8705                                     intel_clock_t *reduced_clock)
8706 {
8707         struct drm_device *dev = crtc->dev;
8708         struct drm_i915_private *dev_priv = dev->dev_private;
8709         int refclk;
8710         const intel_limit_t *limit;
8711         bool ret;
8712
8713         refclk = ironlake_get_refclk(crtc_state);
8714
8715         /*
8716          * Returns a set of divisors for the desired target clock with the given
8717          * refclk, or FALSE.  The returned values represent the clock equation:
8718          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8719          */
8720         limit = intel_limit(crtc_state, refclk);
8721         ret = dev_priv->display.find_dpll(limit, crtc_state,
8722                                           crtc_state->port_clock,
8723                                           refclk, NULL, clock);
8724         if (!ret)
8725                 return false;
8726
8727         return true;
8728 }
8729
8730 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8731 {
8732         /*
8733          * Account for spread spectrum to avoid
8734          * oversubscribing the link. Max center spread
8735          * is 2.5%; use 5% for safety's sake.
8736          */
8737         u32 bps = target_clock * bpp * 21 / 20;
8738         return DIV_ROUND_UP(bps, link_bw * 8);
8739 }
8740
8741 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8742 {
8743         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8744 }
8745
8746 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8747                                       struct intel_crtc_state *crtc_state,
8748                                       u32 *fp,
8749                                       intel_clock_t *reduced_clock, u32 *fp2)
8750 {
8751         struct drm_crtc *crtc = &intel_crtc->base;
8752         struct drm_device *dev = crtc->dev;
8753         struct drm_i915_private *dev_priv = dev->dev_private;
8754         struct drm_atomic_state *state = crtc_state->base.state;
8755         struct drm_connector *connector;
8756         struct drm_connector_state *connector_state;
8757         struct intel_encoder *encoder;
8758         uint32_t dpll;
8759         int factor, num_connectors = 0, i;
8760         bool is_lvds = false, is_sdvo = false;
8761
8762         for_each_connector_in_state(state, connector, connector_state, i) {
8763                 if (connector_state->crtc != crtc_state->base.crtc)
8764                         continue;
8765
8766                 encoder = to_intel_encoder(connector_state->best_encoder);
8767
8768                 switch (encoder->type) {
8769                 case INTEL_OUTPUT_LVDS:
8770                         is_lvds = true;
8771                         break;
8772                 case INTEL_OUTPUT_SDVO:
8773                 case INTEL_OUTPUT_HDMI:
8774                         is_sdvo = true;
8775                         break;
8776                 default:
8777                         break;
8778                 }
8779
8780                 num_connectors++;
8781         }
8782
8783         /* Enable autotuning of the PLL clock (if permissible) */
8784         factor = 21;
8785         if (is_lvds) {
8786                 if ((intel_panel_use_ssc(dev_priv) &&
8787                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8788                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8789                         factor = 25;
8790         } else if (crtc_state->sdvo_tv_clock)
8791                 factor = 20;
8792
8793         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8794                 *fp |= FP_CB_TUNE;
8795
8796         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8797                 *fp2 |= FP_CB_TUNE;
8798
8799         dpll = 0;
8800
8801         if (is_lvds)
8802                 dpll |= DPLLB_MODE_LVDS;
8803         else
8804                 dpll |= DPLLB_MODE_DAC_SERIAL;
8805
8806         dpll |= (crtc_state->pixel_multiplier - 1)
8807                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8808
8809         if (is_sdvo)
8810                 dpll |= DPLL_SDVO_HIGH_SPEED;
8811         if (crtc_state->has_dp_encoder)
8812                 dpll |= DPLL_SDVO_HIGH_SPEED;
8813
8814         /* compute bitmask from p1 value */
8815         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8816         /* also FPA1 */
8817         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8818
8819         switch (crtc_state->dpll.p2) {
8820         case 5:
8821                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8822                 break;
8823         case 7:
8824                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8825                 break;
8826         case 10:
8827                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8828                 break;
8829         case 14:
8830                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8831                 break;
8832         }
8833
8834         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8835                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8836         else
8837                 dpll |= PLL_REF_INPUT_DREFCLK;
8838
8839         return dpll | DPLL_VCO_ENABLE;
8840 }
8841
8842 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8843                                        struct intel_crtc_state *crtc_state)
8844 {
8845         struct drm_device *dev = crtc->base.dev;
8846         intel_clock_t clock, reduced_clock;
8847         u32 dpll = 0, fp = 0, fp2 = 0;
8848         bool ok, has_reduced_clock = false;
8849         bool is_lvds = false;
8850         struct intel_shared_dpll *pll;
8851
8852         memset(&crtc_state->dpll_hw_state, 0,
8853                sizeof(crtc_state->dpll_hw_state));
8854
8855         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8856
8857         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8858              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8859
8860         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8861                                      &has_reduced_clock, &reduced_clock);
8862         if (!ok && !crtc_state->clock_set) {
8863                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8864                 return -EINVAL;
8865         }
8866         /* Compat-code for transition, will disappear. */
8867         if (!crtc_state->clock_set) {
8868                 crtc_state->dpll.n = clock.n;
8869                 crtc_state->dpll.m1 = clock.m1;
8870                 crtc_state->dpll.m2 = clock.m2;
8871                 crtc_state->dpll.p1 = clock.p1;
8872                 crtc_state->dpll.p2 = clock.p2;
8873         }
8874
8875         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8876         if (crtc_state->has_pch_encoder) {
8877                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8878                 if (has_reduced_clock)
8879                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8880
8881                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8882                                              &fp, &reduced_clock,
8883                                              has_reduced_clock ? &fp2 : NULL);
8884
8885                 crtc_state->dpll_hw_state.dpll = dpll;
8886                 crtc_state->dpll_hw_state.fp0 = fp;
8887                 if (has_reduced_clock)
8888                         crtc_state->dpll_hw_state.fp1 = fp2;
8889                 else
8890                         crtc_state->dpll_hw_state.fp1 = fp;
8891
8892                 pll = intel_get_shared_dpll(crtc, crtc_state);
8893                 if (pll == NULL) {
8894                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8895                                          pipe_name(crtc->pipe));
8896                         return -EINVAL;
8897                 }
8898         }
8899
8900         if (is_lvds && has_reduced_clock)
8901                 crtc->lowfreq_avail = true;
8902         else
8903                 crtc->lowfreq_avail = false;
8904
8905         return 0;
8906 }
8907
8908 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8909                                          struct intel_link_m_n *m_n)
8910 {
8911         struct drm_device *dev = crtc->base.dev;
8912         struct drm_i915_private *dev_priv = dev->dev_private;
8913         enum pipe pipe = crtc->pipe;
8914
8915         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8916         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8917         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8918                 & ~TU_SIZE_MASK;
8919         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8920         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8921                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8922 }
8923
8924 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8925                                          enum transcoder transcoder,
8926                                          struct intel_link_m_n *m_n,
8927                                          struct intel_link_m_n *m2_n2)
8928 {
8929         struct drm_device *dev = crtc->base.dev;
8930         struct drm_i915_private *dev_priv = dev->dev_private;
8931         enum pipe pipe = crtc->pipe;
8932
8933         if (INTEL_INFO(dev)->gen >= 5) {
8934                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8935                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8936                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8937                         & ~TU_SIZE_MASK;
8938                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8939                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8940                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8941                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8942                  * gen < 8) and if DRRS is supported (to make sure the
8943                  * registers are not unnecessarily read).
8944                  */
8945                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8946                         crtc->config->has_drrs) {
8947                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8948                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8949                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8950                                         & ~TU_SIZE_MASK;
8951                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8952                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8953                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8954                 }
8955         } else {
8956                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8957                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8958                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8959                         & ~TU_SIZE_MASK;
8960                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8961                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8962                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8963         }
8964 }
8965
8966 void intel_dp_get_m_n(struct intel_crtc *crtc,
8967                       struct intel_crtc_state *pipe_config)
8968 {
8969         if (pipe_config->has_pch_encoder)
8970                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8971         else
8972                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8973                                              &pipe_config->dp_m_n,
8974                                              &pipe_config->dp_m2_n2);
8975 }
8976
8977 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8978                                         struct intel_crtc_state *pipe_config)
8979 {
8980         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8981                                      &pipe_config->fdi_m_n, NULL);
8982 }
8983
8984 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8985                                     struct intel_crtc_state *pipe_config)
8986 {
8987         struct drm_device *dev = crtc->base.dev;
8988         struct drm_i915_private *dev_priv = dev->dev_private;
8989         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8990         uint32_t ps_ctrl = 0;
8991         int id = -1;
8992         int i;
8993
8994         /* find scaler attached to this pipe */
8995         for (i = 0; i < crtc->num_scalers; i++) {
8996                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8997                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8998                         id = i;
8999                         pipe_config->pch_pfit.enabled = true;
9000                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9001                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9002                         break;
9003                 }
9004         }
9005
9006         scaler_state->scaler_id = id;
9007         if (id >= 0) {
9008                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9009         } else {
9010                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9011         }
9012 }
9013
9014 static void
9015 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9016                                  struct intel_initial_plane_config *plane_config)
9017 {
9018         struct drm_device *dev = crtc->base.dev;
9019         struct drm_i915_private *dev_priv = dev->dev_private;
9020         u32 val, base, offset, stride_mult, tiling;
9021         int pipe = crtc->pipe;
9022         int fourcc, pixel_format;
9023         unsigned int aligned_height;
9024         struct drm_framebuffer *fb;
9025         struct intel_framebuffer *intel_fb;
9026
9027         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9028         if (!intel_fb) {
9029                 DRM_DEBUG_KMS("failed to alloc fb\n");
9030                 return;
9031         }
9032
9033         fb = &intel_fb->base;
9034
9035         val = I915_READ(PLANE_CTL(pipe, 0));
9036         if (!(val & PLANE_CTL_ENABLE))
9037                 goto error;
9038
9039         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9040         fourcc = skl_format_to_fourcc(pixel_format,
9041                                       val & PLANE_CTL_ORDER_RGBX,
9042                                       val & PLANE_CTL_ALPHA_MASK);
9043         fb->pixel_format = fourcc;
9044         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9045
9046         tiling = val & PLANE_CTL_TILED_MASK;
9047         switch (tiling) {
9048         case PLANE_CTL_TILED_LINEAR:
9049                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9050                 break;
9051         case PLANE_CTL_TILED_X:
9052                 plane_config->tiling = I915_TILING_X;
9053                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9054                 break;
9055         case PLANE_CTL_TILED_Y:
9056                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9057                 break;
9058         case PLANE_CTL_TILED_YF:
9059                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9060                 break;
9061         default:
9062                 MISSING_CASE(tiling);
9063                 goto error;
9064         }
9065
9066         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9067         plane_config->base = base;
9068
9069         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9070
9071         val = I915_READ(PLANE_SIZE(pipe, 0));
9072         fb->height = ((val >> 16) & 0xfff) + 1;
9073         fb->width = ((val >> 0) & 0x1fff) + 1;
9074
9075         val = I915_READ(PLANE_STRIDE(pipe, 0));
9076         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9077                                                 fb->pixel_format);
9078         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9079
9080         aligned_height = intel_fb_align_height(dev, fb->height,
9081                                                fb->pixel_format,
9082                                                fb->modifier[0]);
9083
9084         plane_config->size = fb->pitches[0] * aligned_height;
9085
9086         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9087                       pipe_name(pipe), fb->width, fb->height,
9088                       fb->bits_per_pixel, base, fb->pitches[0],
9089                       plane_config->size);
9090
9091         plane_config->fb = intel_fb;
9092         return;
9093
9094 error:
9095         kfree(fb);
9096 }
9097
9098 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9099                                      struct intel_crtc_state *pipe_config)
9100 {
9101         struct drm_device *dev = crtc->base.dev;
9102         struct drm_i915_private *dev_priv = dev->dev_private;
9103         uint32_t tmp;
9104
9105         tmp = I915_READ(PF_CTL(crtc->pipe));
9106
9107         if (tmp & PF_ENABLE) {
9108                 pipe_config->pch_pfit.enabled = true;
9109                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9110                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9111
9112                 /* We currently do not free assignements of panel fitters on
9113                  * ivb/hsw (since we don't use the higher upscaling modes which
9114                  * differentiates them) so just WARN about this case for now. */
9115                 if (IS_GEN7(dev)) {
9116                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9117                                 PF_PIPE_SEL_IVB(crtc->pipe));
9118                 }
9119         }
9120 }
9121
9122 static void
9123 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9124                                   struct intel_initial_plane_config *plane_config)
9125 {
9126         struct drm_device *dev = crtc->base.dev;
9127         struct drm_i915_private *dev_priv = dev->dev_private;
9128         u32 val, base, offset;
9129         int pipe = crtc->pipe;
9130         int fourcc, pixel_format;
9131         unsigned int aligned_height;
9132         struct drm_framebuffer *fb;
9133         struct intel_framebuffer *intel_fb;
9134
9135         val = I915_READ(DSPCNTR(pipe));
9136         if (!(val & DISPLAY_PLANE_ENABLE))
9137                 return;
9138
9139         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9140         if (!intel_fb) {
9141                 DRM_DEBUG_KMS("failed to alloc fb\n");
9142                 return;
9143         }
9144
9145         fb = &intel_fb->base;
9146
9147         if (INTEL_INFO(dev)->gen >= 4) {
9148                 if (val & DISPPLANE_TILED) {
9149                         plane_config->tiling = I915_TILING_X;
9150                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9151                 }
9152         }
9153
9154         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9155         fourcc = i9xx_format_to_fourcc(pixel_format);
9156         fb->pixel_format = fourcc;
9157         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9158
9159         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9160         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9161                 offset = I915_READ(DSPOFFSET(pipe));
9162         } else {
9163                 if (plane_config->tiling)
9164                         offset = I915_READ(DSPTILEOFF(pipe));
9165                 else
9166                         offset = I915_READ(DSPLINOFF(pipe));
9167         }
9168         plane_config->base = base;
9169
9170         val = I915_READ(PIPESRC(pipe));
9171         fb->width = ((val >> 16) & 0xfff) + 1;
9172         fb->height = ((val >> 0) & 0xfff) + 1;
9173
9174         val = I915_READ(DSPSTRIDE(pipe));
9175         fb->pitches[0] = val & 0xffffffc0;
9176
9177         aligned_height = intel_fb_align_height(dev, fb->height,
9178                                                fb->pixel_format,
9179                                                fb->modifier[0]);
9180
9181         plane_config->size = fb->pitches[0] * aligned_height;
9182
9183         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9184                       pipe_name(pipe), fb->width, fb->height,
9185                       fb->bits_per_pixel, base, fb->pitches[0],
9186                       plane_config->size);
9187
9188         plane_config->fb = intel_fb;
9189 }
9190
9191 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9192                                      struct intel_crtc_state *pipe_config)
9193 {
9194         struct drm_device *dev = crtc->base.dev;
9195         struct drm_i915_private *dev_priv = dev->dev_private;
9196         uint32_t tmp;
9197
9198         if (!intel_display_power_is_enabled(dev_priv,
9199                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9200                 return false;
9201
9202         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9203         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9204
9205         tmp = I915_READ(PIPECONF(crtc->pipe));
9206         if (!(tmp & PIPECONF_ENABLE))
9207                 return false;
9208
9209         switch (tmp & PIPECONF_BPC_MASK) {
9210         case PIPECONF_6BPC:
9211                 pipe_config->pipe_bpp = 18;
9212                 break;
9213         case PIPECONF_8BPC:
9214                 pipe_config->pipe_bpp = 24;
9215                 break;
9216         case PIPECONF_10BPC:
9217                 pipe_config->pipe_bpp = 30;
9218                 break;
9219         case PIPECONF_12BPC:
9220                 pipe_config->pipe_bpp = 36;
9221                 break;
9222         default:
9223                 break;
9224         }
9225
9226         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9227                 pipe_config->limited_color_range = true;
9228
9229         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9230                 struct intel_shared_dpll *pll;
9231
9232                 pipe_config->has_pch_encoder = true;
9233
9234                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9235                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9236                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9237
9238                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9239
9240                 if (HAS_PCH_IBX(dev_priv->dev)) {
9241                         pipe_config->shared_dpll =
9242                                 (enum intel_dpll_id) crtc->pipe;
9243                 } else {
9244                         tmp = I915_READ(PCH_DPLL_SEL);
9245                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9246                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9247                         else
9248                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9249                 }
9250
9251                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9252
9253                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9254                                            &pipe_config->dpll_hw_state));
9255
9256                 tmp = pipe_config->dpll_hw_state.dpll;
9257                 pipe_config->pixel_multiplier =
9258                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9259                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9260
9261                 ironlake_pch_clock_get(crtc, pipe_config);
9262         } else {
9263                 pipe_config->pixel_multiplier = 1;
9264         }
9265
9266         intel_get_pipe_timings(crtc, pipe_config);
9267
9268         ironlake_get_pfit_config(crtc, pipe_config);
9269
9270         return true;
9271 }
9272
9273 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9274 {
9275         struct drm_device *dev = dev_priv->dev;
9276         struct intel_crtc *crtc;
9277
9278         for_each_intel_crtc(dev, crtc)
9279                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9280                      pipe_name(crtc->pipe));
9281
9282         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9283         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9284         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9285         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9286         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9287         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9288              "CPU PWM1 enabled\n");
9289         if (IS_HASWELL(dev))
9290                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9291                      "CPU PWM2 enabled\n");
9292         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9293              "PCH PWM1 enabled\n");
9294         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9295              "Utility pin enabled\n");
9296         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9297
9298         /*
9299          * In theory we can still leave IRQs enabled, as long as only the HPD
9300          * interrupts remain enabled. We used to check for that, but since it's
9301          * gen-specific and since we only disable LCPLL after we fully disable
9302          * the interrupts, the check below should be enough.
9303          */
9304         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9305 }
9306
9307 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9308 {
9309         struct drm_device *dev = dev_priv->dev;
9310
9311         if (IS_HASWELL(dev))
9312                 return I915_READ(D_COMP_HSW);
9313         else
9314                 return I915_READ(D_COMP_BDW);
9315 }
9316
9317 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9318 {
9319         struct drm_device *dev = dev_priv->dev;
9320
9321         if (IS_HASWELL(dev)) {
9322                 mutex_lock(&dev_priv->rps.hw_lock);
9323                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9324                                             val))
9325                         DRM_ERROR("Failed to write to D_COMP\n");
9326                 mutex_unlock(&dev_priv->rps.hw_lock);
9327         } else {
9328                 I915_WRITE(D_COMP_BDW, val);
9329                 POSTING_READ(D_COMP_BDW);
9330         }
9331 }
9332
9333 /*
9334  * This function implements pieces of two sequences from BSpec:
9335  * - Sequence for display software to disable LCPLL
9336  * - Sequence for display software to allow package C8+
9337  * The steps implemented here are just the steps that actually touch the LCPLL
9338  * register. Callers should take care of disabling all the display engine
9339  * functions, doing the mode unset, fixing interrupts, etc.
9340  */
9341 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9342                               bool switch_to_fclk, bool allow_power_down)
9343 {
9344         uint32_t val;
9345
9346         assert_can_disable_lcpll(dev_priv);
9347
9348         val = I915_READ(LCPLL_CTL);
9349
9350         if (switch_to_fclk) {
9351                 val |= LCPLL_CD_SOURCE_FCLK;
9352                 I915_WRITE(LCPLL_CTL, val);
9353
9354                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9355                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9356                         DRM_ERROR("Switching to FCLK failed\n");
9357
9358                 val = I915_READ(LCPLL_CTL);
9359         }
9360
9361         val |= LCPLL_PLL_DISABLE;
9362         I915_WRITE(LCPLL_CTL, val);
9363         POSTING_READ(LCPLL_CTL);
9364
9365         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9366                 DRM_ERROR("LCPLL still locked\n");
9367
9368         val = hsw_read_dcomp(dev_priv);
9369         val |= D_COMP_COMP_DISABLE;
9370         hsw_write_dcomp(dev_priv, val);
9371         ndelay(100);
9372
9373         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9374                      1))
9375                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9376
9377         if (allow_power_down) {
9378                 val = I915_READ(LCPLL_CTL);
9379                 val |= LCPLL_POWER_DOWN_ALLOW;
9380                 I915_WRITE(LCPLL_CTL, val);
9381                 POSTING_READ(LCPLL_CTL);
9382         }
9383 }
9384
9385 /*
9386  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9387  * source.
9388  */
9389 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9390 {
9391         uint32_t val;
9392
9393         val = I915_READ(LCPLL_CTL);
9394
9395         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9396                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9397                 return;
9398
9399         /*
9400          * Make sure we're not on PC8 state before disabling PC8, otherwise
9401          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9402          */
9403         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9404
9405         if (val & LCPLL_POWER_DOWN_ALLOW) {
9406                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9407                 I915_WRITE(LCPLL_CTL, val);
9408                 POSTING_READ(LCPLL_CTL);
9409         }
9410
9411         val = hsw_read_dcomp(dev_priv);
9412         val |= D_COMP_COMP_FORCE;
9413         val &= ~D_COMP_COMP_DISABLE;
9414         hsw_write_dcomp(dev_priv, val);
9415
9416         val = I915_READ(LCPLL_CTL);
9417         val &= ~LCPLL_PLL_DISABLE;
9418         I915_WRITE(LCPLL_CTL, val);
9419
9420         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9421                 DRM_ERROR("LCPLL not locked yet\n");
9422
9423         if (val & LCPLL_CD_SOURCE_FCLK) {
9424                 val = I915_READ(LCPLL_CTL);
9425                 val &= ~LCPLL_CD_SOURCE_FCLK;
9426                 I915_WRITE(LCPLL_CTL, val);
9427
9428                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9429                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9430                         DRM_ERROR("Switching back to LCPLL failed\n");
9431         }
9432
9433         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9434         intel_update_cdclk(dev_priv->dev);
9435 }
9436
9437 /*
9438  * Package states C8 and deeper are really deep PC states that can only be
9439  * reached when all the devices on the system allow it, so even if the graphics
9440  * device allows PC8+, it doesn't mean the system will actually get to these
9441  * states. Our driver only allows PC8+ when going into runtime PM.
9442  *
9443  * The requirements for PC8+ are that all the outputs are disabled, the power
9444  * well is disabled and most interrupts are disabled, and these are also
9445  * requirements for runtime PM. When these conditions are met, we manually do
9446  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9447  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9448  * hang the machine.
9449  *
9450  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9451  * the state of some registers, so when we come back from PC8+ we need to
9452  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9453  * need to take care of the registers kept by RC6. Notice that this happens even
9454  * if we don't put the device in PCI D3 state (which is what currently happens
9455  * because of the runtime PM support).
9456  *
9457  * For more, read "Display Sequences for Package C8" on the hardware
9458  * documentation.
9459  */
9460 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9461 {
9462         struct drm_device *dev = dev_priv->dev;
9463         uint32_t val;
9464
9465         DRM_DEBUG_KMS("Enabling package C8+\n");
9466
9467         if (HAS_PCH_LPT_LP(dev)) {
9468                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9469                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9470                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9471         }
9472
9473         lpt_disable_clkout_dp(dev);
9474         hsw_disable_lcpll(dev_priv, true, true);
9475 }
9476
9477 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9478 {
9479         struct drm_device *dev = dev_priv->dev;
9480         uint32_t val;
9481
9482         DRM_DEBUG_KMS("Disabling package C8+\n");
9483
9484         hsw_restore_lcpll(dev_priv);
9485         lpt_init_pch_refclk(dev);
9486
9487         if (HAS_PCH_LPT_LP(dev)) {
9488                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9489                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9490                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9491         }
9492
9493         intel_prepare_ddi(dev);
9494 }
9495
9496 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9497 {
9498         struct drm_device *dev = old_state->dev;
9499         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9500
9501         broxton_set_cdclk(dev, req_cdclk);
9502 }
9503
9504 /* compute the max rate for new configuration */
9505 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9506 {
9507         struct intel_crtc *intel_crtc;
9508         struct intel_crtc_state *crtc_state;
9509         int max_pixel_rate = 0;
9510
9511         for_each_intel_crtc(state->dev, intel_crtc) {
9512                 int pixel_rate;
9513
9514                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9515                 if (IS_ERR(crtc_state))
9516                         return PTR_ERR(crtc_state);
9517
9518                 if (!crtc_state->base.enable)
9519                         continue;
9520
9521                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9522
9523                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9524                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9525                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9526
9527                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9528         }
9529
9530         return max_pixel_rate;
9531 }
9532
9533 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9534 {
9535         struct drm_i915_private *dev_priv = dev->dev_private;
9536         uint32_t val, data;
9537         int ret;
9538
9539         if (WARN((I915_READ(LCPLL_CTL) &
9540                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9541                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9542                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9543                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9544                  "trying to change cdclk frequency with cdclk not enabled\n"))
9545                 return;
9546
9547         mutex_lock(&dev_priv->rps.hw_lock);
9548         ret = sandybridge_pcode_write(dev_priv,
9549                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9550         mutex_unlock(&dev_priv->rps.hw_lock);
9551         if (ret) {
9552                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9553                 return;
9554         }
9555
9556         val = I915_READ(LCPLL_CTL);
9557         val |= LCPLL_CD_SOURCE_FCLK;
9558         I915_WRITE(LCPLL_CTL, val);
9559
9560         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9561                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9562                 DRM_ERROR("Switching to FCLK failed\n");
9563
9564         val = I915_READ(LCPLL_CTL);
9565         val &= ~LCPLL_CLK_FREQ_MASK;
9566
9567         switch (cdclk) {
9568         case 450000:
9569                 val |= LCPLL_CLK_FREQ_450;
9570                 data = 0;
9571                 break;
9572         case 540000:
9573                 val |= LCPLL_CLK_FREQ_54O_BDW;
9574                 data = 1;
9575                 break;
9576         case 337500:
9577                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9578                 data = 2;
9579                 break;
9580         case 675000:
9581                 val |= LCPLL_CLK_FREQ_675_BDW;
9582                 data = 3;
9583                 break;
9584         default:
9585                 WARN(1, "invalid cdclk frequency\n");
9586                 return;
9587         }
9588
9589         I915_WRITE(LCPLL_CTL, val);
9590
9591         val = I915_READ(LCPLL_CTL);
9592         val &= ~LCPLL_CD_SOURCE_FCLK;
9593         I915_WRITE(LCPLL_CTL, val);
9594
9595         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9596                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9597                 DRM_ERROR("Switching back to LCPLL failed\n");
9598
9599         mutex_lock(&dev_priv->rps.hw_lock);
9600         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9601         mutex_unlock(&dev_priv->rps.hw_lock);
9602
9603         intel_update_cdclk(dev);
9604
9605         WARN(cdclk != dev_priv->cdclk_freq,
9606              "cdclk requested %d kHz but got %d kHz\n",
9607              cdclk, dev_priv->cdclk_freq);
9608 }
9609
9610 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9611 {
9612         struct drm_i915_private *dev_priv = to_i915(state->dev);
9613         int max_pixclk = ilk_max_pixel_rate(state);
9614         int cdclk;
9615
9616         /*
9617          * FIXME should also account for plane ratio
9618          * once 64bpp pixel formats are supported.
9619          */
9620         if (max_pixclk > 540000)
9621                 cdclk = 675000;
9622         else if (max_pixclk > 450000)
9623                 cdclk = 540000;
9624         else if (max_pixclk > 337500)
9625                 cdclk = 450000;
9626         else
9627                 cdclk = 337500;
9628
9629         /*
9630          * FIXME move the cdclk caclulation to
9631          * compute_config() so we can fail gracegully.
9632          */
9633         if (cdclk > dev_priv->max_cdclk_freq) {
9634                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9635                           cdclk, dev_priv->max_cdclk_freq);
9636                 cdclk = dev_priv->max_cdclk_freq;
9637         }
9638
9639         to_intel_atomic_state(state)->cdclk = cdclk;
9640
9641         return 0;
9642 }
9643
9644 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9645 {
9646         struct drm_device *dev = old_state->dev;
9647         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9648
9649         broadwell_set_cdclk(dev, req_cdclk);
9650 }
9651
9652 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9653                                       struct intel_crtc_state *crtc_state)
9654 {
9655         if (!intel_ddi_pll_select(crtc, crtc_state))
9656                 return -EINVAL;
9657
9658         crtc->lowfreq_avail = false;
9659
9660         return 0;
9661 }
9662
9663 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9664                                 enum port port,
9665                                 struct intel_crtc_state *pipe_config)
9666 {
9667         switch (port) {
9668         case PORT_A:
9669                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9670                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9671                 break;
9672         case PORT_B:
9673                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9674                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9675                 break;
9676         case PORT_C:
9677                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9678                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9679                 break;
9680         default:
9681                 DRM_ERROR("Incorrect port type\n");
9682         }
9683 }
9684
9685 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9686                                 enum port port,
9687                                 struct intel_crtc_state *pipe_config)
9688 {
9689         u32 temp, dpll_ctl1;
9690
9691         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9692         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9693
9694         switch (pipe_config->ddi_pll_sel) {
9695         case SKL_DPLL0:
9696                 /*
9697                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9698                  * of the shared DPLL framework and thus needs to be read out
9699                  * separately
9700                  */
9701                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9702                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9703                 break;
9704         case SKL_DPLL1:
9705                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9706                 break;
9707         case SKL_DPLL2:
9708                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9709                 break;
9710         case SKL_DPLL3:
9711                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9712                 break;
9713         }
9714 }
9715
9716 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9717                                 enum port port,
9718                                 struct intel_crtc_state *pipe_config)
9719 {
9720         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9721
9722         switch (pipe_config->ddi_pll_sel) {
9723         case PORT_CLK_SEL_WRPLL1:
9724                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9725                 break;
9726         case PORT_CLK_SEL_WRPLL2:
9727                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9728                 break;
9729         }
9730 }
9731
9732 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9733                                        struct intel_crtc_state *pipe_config)
9734 {
9735         struct drm_device *dev = crtc->base.dev;
9736         struct drm_i915_private *dev_priv = dev->dev_private;
9737         struct intel_shared_dpll *pll;
9738         enum port port;
9739         uint32_t tmp;
9740
9741         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9742
9743         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9744
9745         if (IS_SKYLAKE(dev))
9746                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9747         else if (IS_BROXTON(dev))
9748                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9749         else
9750                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9751
9752         if (pipe_config->shared_dpll >= 0) {
9753                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9754
9755                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9756                                            &pipe_config->dpll_hw_state));
9757         }
9758
9759         /*
9760          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9761          * DDI E. So just check whether this pipe is wired to DDI E and whether
9762          * the PCH transcoder is on.
9763          */
9764         if (INTEL_INFO(dev)->gen < 9 &&
9765             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9766                 pipe_config->has_pch_encoder = true;
9767
9768                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9769                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9770                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9771
9772                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9773         }
9774 }
9775
9776 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9777                                     struct intel_crtc_state *pipe_config)
9778 {
9779         struct drm_device *dev = crtc->base.dev;
9780         struct drm_i915_private *dev_priv = dev->dev_private;
9781         enum intel_display_power_domain pfit_domain;
9782         uint32_t tmp;
9783
9784         if (!intel_display_power_is_enabled(dev_priv,
9785                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9786                 return false;
9787
9788         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9789         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9790
9791         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9792         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9793                 enum pipe trans_edp_pipe;
9794                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9795                 default:
9796                         WARN(1, "unknown pipe linked to edp transcoder\n");
9797                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9798                 case TRANS_DDI_EDP_INPUT_A_ON:
9799                         trans_edp_pipe = PIPE_A;
9800                         break;
9801                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9802                         trans_edp_pipe = PIPE_B;
9803                         break;
9804                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9805                         trans_edp_pipe = PIPE_C;
9806                         break;
9807                 }
9808
9809                 if (trans_edp_pipe == crtc->pipe)
9810                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9811         }
9812
9813         if (!intel_display_power_is_enabled(dev_priv,
9814                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9815                 return false;
9816
9817         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9818         if (!(tmp & PIPECONF_ENABLE))
9819                 return false;
9820
9821         haswell_get_ddi_port_state(crtc, pipe_config);
9822
9823         intel_get_pipe_timings(crtc, pipe_config);
9824
9825         if (INTEL_INFO(dev)->gen >= 9) {
9826                 skl_init_scalers(dev, crtc, pipe_config);
9827         }
9828
9829         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9830
9831         if (INTEL_INFO(dev)->gen >= 9) {
9832                 pipe_config->scaler_state.scaler_id = -1;
9833                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9834         }
9835
9836         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9837                 if (INTEL_INFO(dev)->gen >= 9)
9838                         skylake_get_pfit_config(crtc, pipe_config);
9839                 else
9840                         ironlake_get_pfit_config(crtc, pipe_config);
9841         }
9842
9843         if (IS_HASWELL(dev))
9844                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9845                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9846
9847         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9848                 pipe_config->pixel_multiplier =
9849                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9850         } else {
9851                 pipe_config->pixel_multiplier = 1;
9852         }
9853
9854         return true;
9855 }
9856
9857 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9858 {
9859         struct drm_device *dev = crtc->dev;
9860         struct drm_i915_private *dev_priv = dev->dev_private;
9861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9862         uint32_t cntl = 0, size = 0;
9863
9864         if (base) {
9865                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9866                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9867                 unsigned int stride = roundup_pow_of_two(width) * 4;
9868
9869                 switch (stride) {
9870                 default:
9871                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9872                                   width, stride);
9873                         stride = 256;
9874                         /* fallthrough */
9875                 case 256:
9876                 case 512:
9877                 case 1024:
9878                 case 2048:
9879                         break;
9880                 }
9881
9882                 cntl |= CURSOR_ENABLE |
9883                         CURSOR_GAMMA_ENABLE |
9884                         CURSOR_FORMAT_ARGB |
9885                         CURSOR_STRIDE(stride);
9886
9887                 size = (height << 12) | width;
9888         }
9889
9890         if (intel_crtc->cursor_cntl != 0 &&
9891             (intel_crtc->cursor_base != base ||
9892              intel_crtc->cursor_size != size ||
9893              intel_crtc->cursor_cntl != cntl)) {
9894                 /* On these chipsets we can only modify the base/size/stride
9895                  * whilst the cursor is disabled.
9896                  */
9897                 I915_WRITE(CURCNTR(PIPE_A), 0);
9898                 POSTING_READ(CURCNTR(PIPE_A));
9899                 intel_crtc->cursor_cntl = 0;
9900         }
9901
9902         if (intel_crtc->cursor_base != base) {
9903                 I915_WRITE(CURBASE(PIPE_A), base);
9904                 intel_crtc->cursor_base = base;
9905         }
9906
9907         if (intel_crtc->cursor_size != size) {
9908                 I915_WRITE(CURSIZE, size);
9909                 intel_crtc->cursor_size = size;
9910         }
9911
9912         if (intel_crtc->cursor_cntl != cntl) {
9913                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9914                 POSTING_READ(CURCNTR(PIPE_A));
9915                 intel_crtc->cursor_cntl = cntl;
9916         }
9917 }
9918
9919 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9920 {
9921         struct drm_device *dev = crtc->dev;
9922         struct drm_i915_private *dev_priv = dev->dev_private;
9923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9924         int pipe = intel_crtc->pipe;
9925         uint32_t cntl;
9926
9927         cntl = 0;
9928         if (base) {
9929                 cntl = MCURSOR_GAMMA_ENABLE;
9930                 switch (intel_crtc->base.cursor->state->crtc_w) {
9931                         case 64:
9932                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9933                                 break;
9934                         case 128:
9935                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9936                                 break;
9937                         case 256:
9938                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9939                                 break;
9940                         default:
9941                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9942                                 return;
9943                 }
9944                 cntl |= pipe << 28; /* Connect to correct pipe */
9945
9946                 if (HAS_DDI(dev))
9947                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9948         }
9949
9950         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9951                 cntl |= CURSOR_ROTATE_180;
9952
9953         if (intel_crtc->cursor_cntl != cntl) {
9954                 I915_WRITE(CURCNTR(pipe), cntl);
9955                 POSTING_READ(CURCNTR(pipe));
9956                 intel_crtc->cursor_cntl = cntl;
9957         }
9958
9959         /* and commit changes on next vblank */
9960         I915_WRITE(CURBASE(pipe), base);
9961         POSTING_READ(CURBASE(pipe));
9962
9963         intel_crtc->cursor_base = base;
9964 }
9965
9966 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9967 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9968                                      bool on)
9969 {
9970         struct drm_device *dev = crtc->dev;
9971         struct drm_i915_private *dev_priv = dev->dev_private;
9972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9973         int pipe = intel_crtc->pipe;
9974         struct drm_plane_state *cursor_state = crtc->cursor->state;
9975         int x = cursor_state->crtc_x;
9976         int y = cursor_state->crtc_y;
9977         u32 base = 0, pos = 0;
9978
9979         if (on)
9980                 base = intel_crtc->cursor_addr;
9981
9982         if (x >= intel_crtc->config->pipe_src_w)
9983                 base = 0;
9984
9985         if (y >= intel_crtc->config->pipe_src_h)
9986                 base = 0;
9987
9988         if (x < 0) {
9989                 if (x + cursor_state->crtc_w <= 0)
9990                         base = 0;
9991
9992                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9993                 x = -x;
9994         }
9995         pos |= x << CURSOR_X_SHIFT;
9996
9997         if (y < 0) {
9998                 if (y + cursor_state->crtc_h <= 0)
9999                         base = 0;
10000
10001                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10002                 y = -y;
10003         }
10004         pos |= y << CURSOR_Y_SHIFT;
10005
10006         if (base == 0 && intel_crtc->cursor_base == 0)
10007                 return;
10008
10009         I915_WRITE(CURPOS(pipe), pos);
10010
10011         /* ILK+ do this automagically */
10012         if (HAS_GMCH_DISPLAY(dev) &&
10013             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10014                 base += (cursor_state->crtc_h *
10015                          cursor_state->crtc_w - 1) * 4;
10016         }
10017
10018         if (IS_845G(dev) || IS_I865G(dev))
10019                 i845_update_cursor(crtc, base);
10020         else
10021                 i9xx_update_cursor(crtc, base);
10022 }
10023
10024 static bool cursor_size_ok(struct drm_device *dev,
10025                            uint32_t width, uint32_t height)
10026 {
10027         if (width == 0 || height == 0)
10028                 return false;
10029
10030         /*
10031          * 845g/865g are special in that they are only limited by
10032          * the width of their cursors, the height is arbitrary up to
10033          * the precision of the register. Everything else requires
10034          * square cursors, limited to a few power-of-two sizes.
10035          */
10036         if (IS_845G(dev) || IS_I865G(dev)) {
10037                 if ((width & 63) != 0)
10038                         return false;
10039
10040                 if (width > (IS_845G(dev) ? 64 : 512))
10041                         return false;
10042
10043                 if (height > 1023)
10044                         return false;
10045         } else {
10046                 switch (width | height) {
10047                 case 256:
10048                 case 128:
10049                         if (IS_GEN2(dev))
10050                                 return false;
10051                 case 64:
10052                         break;
10053                 default:
10054                         return false;
10055                 }
10056         }
10057
10058         return true;
10059 }
10060
10061 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10062                                  u16 *blue, uint32_t start, uint32_t size)
10063 {
10064         int end = (start + size > 256) ? 256 : start + size, i;
10065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10066
10067         for (i = start; i < end; i++) {
10068                 intel_crtc->lut_r[i] = red[i] >> 8;
10069                 intel_crtc->lut_g[i] = green[i] >> 8;
10070                 intel_crtc->lut_b[i] = blue[i] >> 8;
10071         }
10072
10073         intel_crtc_load_lut(crtc);
10074 }
10075
10076 /* VESA 640x480x72Hz mode to set on the pipe */
10077 static struct drm_display_mode load_detect_mode = {
10078         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10079                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10080 };
10081
10082 struct drm_framebuffer *
10083 __intel_framebuffer_create(struct drm_device *dev,
10084                            struct drm_mode_fb_cmd2 *mode_cmd,
10085                            struct drm_i915_gem_object *obj)
10086 {
10087         struct intel_framebuffer *intel_fb;
10088         int ret;
10089
10090         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10091         if (!intel_fb) {
10092                 drm_gem_object_unreference(&obj->base);
10093                 return ERR_PTR(-ENOMEM);
10094         }
10095
10096         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10097         if (ret)
10098                 goto err;
10099
10100         return &intel_fb->base;
10101 err:
10102         drm_gem_object_unreference(&obj->base);
10103         kfree(intel_fb);
10104
10105         return ERR_PTR(ret);
10106 }
10107
10108 static struct drm_framebuffer *
10109 intel_framebuffer_create(struct drm_device *dev,
10110                          struct drm_mode_fb_cmd2 *mode_cmd,
10111                          struct drm_i915_gem_object *obj)
10112 {
10113         struct drm_framebuffer *fb;
10114         int ret;
10115
10116         ret = i915_mutex_lock_interruptible(dev);
10117         if (ret)
10118                 return ERR_PTR(ret);
10119         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10120         mutex_unlock(&dev->struct_mutex);
10121
10122         return fb;
10123 }
10124
10125 static u32
10126 intel_framebuffer_pitch_for_width(int width, int bpp)
10127 {
10128         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10129         return ALIGN(pitch, 64);
10130 }
10131
10132 static u32
10133 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10134 {
10135         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10136         return PAGE_ALIGN(pitch * mode->vdisplay);
10137 }
10138
10139 static struct drm_framebuffer *
10140 intel_framebuffer_create_for_mode(struct drm_device *dev,
10141                                   struct drm_display_mode *mode,
10142                                   int depth, int bpp)
10143 {
10144         struct drm_i915_gem_object *obj;
10145         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10146
10147         obj = i915_gem_alloc_object(dev,
10148                                     intel_framebuffer_size_for_mode(mode, bpp));
10149         if (obj == NULL)
10150                 return ERR_PTR(-ENOMEM);
10151
10152         mode_cmd.width = mode->hdisplay;
10153         mode_cmd.height = mode->vdisplay;
10154         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10155                                                                 bpp);
10156         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10157
10158         return intel_framebuffer_create(dev, &mode_cmd, obj);
10159 }
10160
10161 static struct drm_framebuffer *
10162 mode_fits_in_fbdev(struct drm_device *dev,
10163                    struct drm_display_mode *mode)
10164 {
10165 #ifdef CONFIG_DRM_FBDEV_EMULATION
10166         struct drm_i915_private *dev_priv = dev->dev_private;
10167         struct drm_i915_gem_object *obj;
10168         struct drm_framebuffer *fb;
10169
10170         if (!dev_priv->fbdev)
10171                 return NULL;
10172
10173         if (!dev_priv->fbdev->fb)
10174                 return NULL;
10175
10176         obj = dev_priv->fbdev->fb->obj;
10177         BUG_ON(!obj);
10178
10179         fb = &dev_priv->fbdev->fb->base;
10180         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10181                                                                fb->bits_per_pixel))
10182                 return NULL;
10183
10184         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10185                 return NULL;
10186
10187         return fb;
10188 #else
10189         return NULL;
10190 #endif
10191 }
10192
10193 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10194                                            struct drm_crtc *crtc,
10195                                            struct drm_display_mode *mode,
10196                                            struct drm_framebuffer *fb,
10197                                            int x, int y)
10198 {
10199         struct drm_plane_state *plane_state;
10200         int hdisplay, vdisplay;
10201         int ret;
10202
10203         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10204         if (IS_ERR(plane_state))
10205                 return PTR_ERR(plane_state);
10206
10207         if (mode)
10208                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10209         else
10210                 hdisplay = vdisplay = 0;
10211
10212         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10213         if (ret)
10214                 return ret;
10215         drm_atomic_set_fb_for_plane(plane_state, fb);
10216         plane_state->crtc_x = 0;
10217         plane_state->crtc_y = 0;
10218         plane_state->crtc_w = hdisplay;
10219         plane_state->crtc_h = vdisplay;
10220         plane_state->src_x = x << 16;
10221         plane_state->src_y = y << 16;
10222         plane_state->src_w = hdisplay << 16;
10223         plane_state->src_h = vdisplay << 16;
10224
10225         return 0;
10226 }
10227
10228 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10229                                 struct drm_display_mode *mode,
10230                                 struct intel_load_detect_pipe *old,
10231                                 struct drm_modeset_acquire_ctx *ctx)
10232 {
10233         struct intel_crtc *intel_crtc;
10234         struct intel_encoder *intel_encoder =
10235                 intel_attached_encoder(connector);
10236         struct drm_crtc *possible_crtc;
10237         struct drm_encoder *encoder = &intel_encoder->base;
10238         struct drm_crtc *crtc = NULL;
10239         struct drm_device *dev = encoder->dev;
10240         struct drm_framebuffer *fb;
10241         struct drm_mode_config *config = &dev->mode_config;
10242         struct drm_atomic_state *state = NULL;
10243         struct drm_connector_state *connector_state;
10244         struct intel_crtc_state *crtc_state;
10245         int ret, i = -1;
10246
10247         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10248                       connector->base.id, connector->name,
10249                       encoder->base.id, encoder->name);
10250
10251 retry:
10252         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10253         if (ret)
10254                 goto fail;
10255
10256         /*
10257          * Algorithm gets a little messy:
10258          *
10259          *   - if the connector already has an assigned crtc, use it (but make
10260          *     sure it's on first)
10261          *
10262          *   - try to find the first unused crtc that can drive this connector,
10263          *     and use that if we find one
10264          */
10265
10266         /* See if we already have a CRTC for this connector */
10267         if (encoder->crtc) {
10268                 crtc = encoder->crtc;
10269
10270                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10271                 if (ret)
10272                         goto fail;
10273                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10274                 if (ret)
10275                         goto fail;
10276
10277                 old->dpms_mode = connector->dpms;
10278                 old->load_detect_temp = false;
10279
10280                 /* Make sure the crtc and connector are running */
10281                 if (connector->dpms != DRM_MODE_DPMS_ON)
10282                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10283
10284                 return true;
10285         }
10286
10287         /* Find an unused one (if possible) */
10288         for_each_crtc(dev, possible_crtc) {
10289                 i++;
10290                 if (!(encoder->possible_crtcs & (1 << i)))
10291                         continue;
10292                 if (possible_crtc->state->enable)
10293                         continue;
10294
10295                 crtc = possible_crtc;
10296                 break;
10297         }
10298
10299         /*
10300          * If we didn't find an unused CRTC, don't use any.
10301          */
10302         if (!crtc) {
10303                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10304                 goto fail;
10305         }
10306
10307         ret = drm_modeset_lock(&crtc->mutex, ctx);
10308         if (ret)
10309                 goto fail;
10310         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10311         if (ret)
10312                 goto fail;
10313
10314         intel_crtc = to_intel_crtc(crtc);
10315         old->dpms_mode = connector->dpms;
10316         old->load_detect_temp = true;
10317         old->release_fb = NULL;
10318
10319         state = drm_atomic_state_alloc(dev);
10320         if (!state)
10321                 return false;
10322
10323         state->acquire_ctx = ctx;
10324
10325         connector_state = drm_atomic_get_connector_state(state, connector);
10326         if (IS_ERR(connector_state)) {
10327                 ret = PTR_ERR(connector_state);
10328                 goto fail;
10329         }
10330
10331         connector_state->crtc = crtc;
10332         connector_state->best_encoder = &intel_encoder->base;
10333
10334         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10335         if (IS_ERR(crtc_state)) {
10336                 ret = PTR_ERR(crtc_state);
10337                 goto fail;
10338         }
10339
10340         crtc_state->base.active = crtc_state->base.enable = true;
10341
10342         if (!mode)
10343                 mode = &load_detect_mode;
10344
10345         /* We need a framebuffer large enough to accommodate all accesses
10346          * that the plane may generate whilst we perform load detection.
10347          * We can not rely on the fbcon either being present (we get called
10348          * during its initialisation to detect all boot displays, or it may
10349          * not even exist) or that it is large enough to satisfy the
10350          * requested mode.
10351          */
10352         fb = mode_fits_in_fbdev(dev, mode);
10353         if (fb == NULL) {
10354                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10355                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10356                 old->release_fb = fb;
10357         } else
10358                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10359         if (IS_ERR(fb)) {
10360                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10361                 goto fail;
10362         }
10363
10364         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10365         if (ret)
10366                 goto fail;
10367
10368         drm_mode_copy(&crtc_state->base.mode, mode);
10369
10370         if (drm_atomic_commit(state)) {
10371                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10372                 if (old->release_fb)
10373                         old->release_fb->funcs->destroy(old->release_fb);
10374                 goto fail;
10375         }
10376         crtc->primary->crtc = crtc;
10377
10378         /* let the connector get through one full cycle before testing */
10379         intel_wait_for_vblank(dev, intel_crtc->pipe);
10380         return true;
10381
10382 fail:
10383         drm_atomic_state_free(state);
10384         state = NULL;
10385
10386         if (ret == -EDEADLK) {
10387                 drm_modeset_backoff(ctx);
10388                 goto retry;
10389         }
10390
10391         return false;
10392 }
10393
10394 void intel_release_load_detect_pipe(struct drm_connector *connector,
10395                                     struct intel_load_detect_pipe *old,
10396                                     struct drm_modeset_acquire_ctx *ctx)
10397 {
10398         struct drm_device *dev = connector->dev;
10399         struct intel_encoder *intel_encoder =
10400                 intel_attached_encoder(connector);
10401         struct drm_encoder *encoder = &intel_encoder->base;
10402         struct drm_crtc *crtc = encoder->crtc;
10403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10404         struct drm_atomic_state *state;
10405         struct drm_connector_state *connector_state;
10406         struct intel_crtc_state *crtc_state;
10407         int ret;
10408
10409         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10410                       connector->base.id, connector->name,
10411                       encoder->base.id, encoder->name);
10412
10413         if (old->load_detect_temp) {
10414                 state = drm_atomic_state_alloc(dev);
10415                 if (!state)
10416                         goto fail;
10417
10418                 state->acquire_ctx = ctx;
10419
10420                 connector_state = drm_atomic_get_connector_state(state, connector);
10421                 if (IS_ERR(connector_state))
10422                         goto fail;
10423
10424                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10425                 if (IS_ERR(crtc_state))
10426                         goto fail;
10427
10428                 connector_state->best_encoder = NULL;
10429                 connector_state->crtc = NULL;
10430
10431                 crtc_state->base.enable = crtc_state->base.active = false;
10432
10433                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10434                                                       0, 0);
10435                 if (ret)
10436                         goto fail;
10437
10438                 ret = drm_atomic_commit(state);
10439                 if (ret)
10440                         goto fail;
10441
10442                 if (old->release_fb) {
10443                         drm_framebuffer_unregister_private(old->release_fb);
10444                         drm_framebuffer_unreference(old->release_fb);
10445                 }
10446
10447                 return;
10448         }
10449
10450         /* Switch crtc and encoder back off if necessary */
10451         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10452                 connector->funcs->dpms(connector, old->dpms_mode);
10453
10454         return;
10455 fail:
10456         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10457         drm_atomic_state_free(state);
10458 }
10459
10460 static int i9xx_pll_refclk(struct drm_device *dev,
10461                            const struct intel_crtc_state *pipe_config)
10462 {
10463         struct drm_i915_private *dev_priv = dev->dev_private;
10464         u32 dpll = pipe_config->dpll_hw_state.dpll;
10465
10466         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10467                 return dev_priv->vbt.lvds_ssc_freq;
10468         else if (HAS_PCH_SPLIT(dev))
10469                 return 120000;
10470         else if (!IS_GEN2(dev))
10471                 return 96000;
10472         else
10473                 return 48000;
10474 }
10475
10476 /* Returns the clock of the currently programmed mode of the given pipe. */
10477 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10478                                 struct intel_crtc_state *pipe_config)
10479 {
10480         struct drm_device *dev = crtc->base.dev;
10481         struct drm_i915_private *dev_priv = dev->dev_private;
10482         int pipe = pipe_config->cpu_transcoder;
10483         u32 dpll = pipe_config->dpll_hw_state.dpll;
10484         u32 fp;
10485         intel_clock_t clock;
10486         int port_clock;
10487         int refclk = i9xx_pll_refclk(dev, pipe_config);
10488
10489         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10490                 fp = pipe_config->dpll_hw_state.fp0;
10491         else
10492                 fp = pipe_config->dpll_hw_state.fp1;
10493
10494         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10495         if (IS_PINEVIEW(dev)) {
10496                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10497                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10498         } else {
10499                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10500                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10501         }
10502
10503         if (!IS_GEN2(dev)) {
10504                 if (IS_PINEVIEW(dev))
10505                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10506                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10507                 else
10508                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10509                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10510
10511                 switch (dpll & DPLL_MODE_MASK) {
10512                 case DPLLB_MODE_DAC_SERIAL:
10513                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10514                                 5 : 10;
10515                         break;
10516                 case DPLLB_MODE_LVDS:
10517                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10518                                 7 : 14;
10519                         break;
10520                 default:
10521                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10522                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10523                         return;
10524                 }
10525
10526                 if (IS_PINEVIEW(dev))
10527                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10528                 else
10529                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10530         } else {
10531                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10532                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10533
10534                 if (is_lvds) {
10535                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10536                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10537
10538                         if (lvds & LVDS_CLKB_POWER_UP)
10539                                 clock.p2 = 7;
10540                         else
10541                                 clock.p2 = 14;
10542                 } else {
10543                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10544                                 clock.p1 = 2;
10545                         else {
10546                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10547                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10548                         }
10549                         if (dpll & PLL_P2_DIVIDE_BY_4)
10550                                 clock.p2 = 4;
10551                         else
10552                                 clock.p2 = 2;
10553                 }
10554
10555                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10556         }
10557
10558         /*
10559          * This value includes pixel_multiplier. We will use
10560          * port_clock to compute adjusted_mode.crtc_clock in the
10561          * encoder's get_config() function.
10562          */
10563         pipe_config->port_clock = port_clock;
10564 }
10565
10566 int intel_dotclock_calculate(int link_freq,
10567                              const struct intel_link_m_n *m_n)
10568 {
10569         /*
10570          * The calculation for the data clock is:
10571          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10572          * But we want to avoid losing precison if possible, so:
10573          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10574          *
10575          * and the link clock is simpler:
10576          * link_clock = (m * link_clock) / n
10577          */
10578
10579         if (!m_n->link_n)
10580                 return 0;
10581
10582         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10583 }
10584
10585 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10586                                    struct intel_crtc_state *pipe_config)
10587 {
10588         struct drm_device *dev = crtc->base.dev;
10589
10590         /* read out port_clock from the DPLL */
10591         i9xx_crtc_clock_get(crtc, pipe_config);
10592
10593         /*
10594          * This value does not include pixel_multiplier.
10595          * We will check that port_clock and adjusted_mode.crtc_clock
10596          * agree once we know their relationship in the encoder's
10597          * get_config() function.
10598          */
10599         pipe_config->base.adjusted_mode.crtc_clock =
10600                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10601                                          &pipe_config->fdi_m_n);
10602 }
10603
10604 /** Returns the currently programmed mode of the given pipe. */
10605 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10606                                              struct drm_crtc *crtc)
10607 {
10608         struct drm_i915_private *dev_priv = dev->dev_private;
10609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10610         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10611         struct drm_display_mode *mode;
10612         struct intel_crtc_state pipe_config;
10613         int htot = I915_READ(HTOTAL(cpu_transcoder));
10614         int hsync = I915_READ(HSYNC(cpu_transcoder));
10615         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10616         int vsync = I915_READ(VSYNC(cpu_transcoder));
10617         enum pipe pipe = intel_crtc->pipe;
10618
10619         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10620         if (!mode)
10621                 return NULL;
10622
10623         /*
10624          * Construct a pipe_config sufficient for getting the clock info
10625          * back out of crtc_clock_get.
10626          *
10627          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10628          * to use a real value here instead.
10629          */
10630         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10631         pipe_config.pixel_multiplier = 1;
10632         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10633         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10634         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10635         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10636
10637         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10638         mode->hdisplay = (htot & 0xffff) + 1;
10639         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10640         mode->hsync_start = (hsync & 0xffff) + 1;
10641         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10642         mode->vdisplay = (vtot & 0xffff) + 1;
10643         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10644         mode->vsync_start = (vsync & 0xffff) + 1;
10645         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10646
10647         drm_mode_set_name(mode);
10648
10649         return mode;
10650 }
10651
10652 void intel_mark_busy(struct drm_device *dev)
10653 {
10654         struct drm_i915_private *dev_priv = dev->dev_private;
10655
10656         if (dev_priv->mm.busy)
10657                 return;
10658
10659         intel_runtime_pm_get(dev_priv);
10660         i915_update_gfx_val(dev_priv);
10661         if (INTEL_INFO(dev)->gen >= 6)
10662                 gen6_rps_busy(dev_priv);
10663         dev_priv->mm.busy = true;
10664 }
10665
10666 void intel_mark_idle(struct drm_device *dev)
10667 {
10668         struct drm_i915_private *dev_priv = dev->dev_private;
10669
10670         if (!dev_priv->mm.busy)
10671                 return;
10672
10673         dev_priv->mm.busy = false;
10674
10675         if (INTEL_INFO(dev)->gen >= 6)
10676                 gen6_rps_idle(dev->dev_private);
10677
10678         intel_runtime_pm_put(dev_priv);
10679 }
10680
10681 static void intel_crtc_destroy(struct drm_crtc *crtc)
10682 {
10683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10684         struct drm_device *dev = crtc->dev;
10685         struct intel_unpin_work *work;
10686
10687         spin_lock_irq(&dev->event_lock);
10688         work = intel_crtc->unpin_work;
10689         intel_crtc->unpin_work = NULL;
10690         spin_unlock_irq(&dev->event_lock);
10691
10692         if (work) {
10693                 cancel_work_sync(&work->work);
10694                 kfree(work);
10695         }
10696
10697         drm_crtc_cleanup(crtc);
10698
10699         kfree(intel_crtc);
10700 }
10701
10702 static void intel_unpin_work_fn(struct work_struct *__work)
10703 {
10704         struct intel_unpin_work *work =
10705                 container_of(__work, struct intel_unpin_work, work);
10706         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10707         struct drm_device *dev = crtc->base.dev;
10708         struct drm_plane *primary = crtc->base.primary;
10709
10710         mutex_lock(&dev->struct_mutex);
10711         intel_unpin_fb_obj(work->old_fb, primary->state);
10712         drm_gem_object_unreference(&work->pending_flip_obj->base);
10713
10714         if (work->flip_queued_req)
10715                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10716         mutex_unlock(&dev->struct_mutex);
10717
10718         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10719         drm_framebuffer_unreference(work->old_fb);
10720
10721         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10722         atomic_dec(&crtc->unpin_work_count);
10723
10724         kfree(work);
10725 }
10726
10727 static void do_intel_finish_page_flip(struct drm_device *dev,
10728                                       struct drm_crtc *crtc)
10729 {
10730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10731         struct intel_unpin_work *work;
10732         unsigned long flags;
10733
10734         /* Ignore early vblank irqs */
10735         if (intel_crtc == NULL)
10736                 return;
10737
10738         /*
10739          * This is called both by irq handlers and the reset code (to complete
10740          * lost pageflips) so needs the full irqsave spinlocks.
10741          */
10742         spin_lock_irqsave(&dev->event_lock, flags);
10743         work = intel_crtc->unpin_work;
10744
10745         /* Ensure we don't miss a work->pending update ... */
10746         smp_rmb();
10747
10748         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10749                 spin_unlock_irqrestore(&dev->event_lock, flags);
10750                 return;
10751         }
10752
10753         page_flip_completed(intel_crtc);
10754
10755         spin_unlock_irqrestore(&dev->event_lock, flags);
10756 }
10757
10758 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10759 {
10760         struct drm_i915_private *dev_priv = dev->dev_private;
10761         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10762
10763         do_intel_finish_page_flip(dev, crtc);
10764 }
10765
10766 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10767 {
10768         struct drm_i915_private *dev_priv = dev->dev_private;
10769         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10770
10771         do_intel_finish_page_flip(dev, crtc);
10772 }
10773
10774 /* Is 'a' after or equal to 'b'? */
10775 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10776 {
10777         return !((a - b) & 0x80000000);
10778 }
10779
10780 static bool page_flip_finished(struct intel_crtc *crtc)
10781 {
10782         struct drm_device *dev = crtc->base.dev;
10783         struct drm_i915_private *dev_priv = dev->dev_private;
10784
10785         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10786             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10787                 return true;
10788
10789         /*
10790          * The relevant registers doen't exist on pre-ctg.
10791          * As the flip done interrupt doesn't trigger for mmio
10792          * flips on gmch platforms, a flip count check isn't
10793          * really needed there. But since ctg has the registers,
10794          * include it in the check anyway.
10795          */
10796         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10797                 return true;
10798
10799         /*
10800          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10801          * used the same base address. In that case the mmio flip might
10802          * have completed, but the CS hasn't even executed the flip yet.
10803          *
10804          * A flip count check isn't enough as the CS might have updated
10805          * the base address just after start of vblank, but before we
10806          * managed to process the interrupt. This means we'd complete the
10807          * CS flip too soon.
10808          *
10809          * Combining both checks should get us a good enough result. It may
10810          * still happen that the CS flip has been executed, but has not
10811          * yet actually completed. But in case the base address is the same
10812          * anyway, we don't really care.
10813          */
10814         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10815                 crtc->unpin_work->gtt_offset &&
10816                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10817                                     crtc->unpin_work->flip_count);
10818 }
10819
10820 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10821 {
10822         struct drm_i915_private *dev_priv = dev->dev_private;
10823         struct intel_crtc *intel_crtc =
10824                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10825         unsigned long flags;
10826
10827
10828         /*
10829          * This is called both by irq handlers and the reset code (to complete
10830          * lost pageflips) so needs the full irqsave spinlocks.
10831          *
10832          * NB: An MMIO update of the plane base pointer will also
10833          * generate a page-flip completion irq, i.e. every modeset
10834          * is also accompanied by a spurious intel_prepare_page_flip().
10835          */
10836         spin_lock_irqsave(&dev->event_lock, flags);
10837         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10838                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10839         spin_unlock_irqrestore(&dev->event_lock, flags);
10840 }
10841
10842 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10843 {
10844         /* Ensure that the work item is consistent when activating it ... */
10845         smp_wmb();
10846         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10847         /* and that it is marked active as soon as the irq could fire. */
10848         smp_wmb();
10849 }
10850
10851 static int intel_gen2_queue_flip(struct drm_device *dev,
10852                                  struct drm_crtc *crtc,
10853                                  struct drm_framebuffer *fb,
10854                                  struct drm_i915_gem_object *obj,
10855                                  struct drm_i915_gem_request *req,
10856                                  uint32_t flags)
10857 {
10858         struct intel_engine_cs *ring = req->ring;
10859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10860         u32 flip_mask;
10861         int ret;
10862
10863         ret = intel_ring_begin(req, 6);
10864         if (ret)
10865                 return ret;
10866
10867         /* Can't queue multiple flips, so wait for the previous
10868          * one to finish before executing the next.
10869          */
10870         if (intel_crtc->plane)
10871                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10872         else
10873                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10874         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10875         intel_ring_emit(ring, MI_NOOP);
10876         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10877                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10878         intel_ring_emit(ring, fb->pitches[0]);
10879         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10880         intel_ring_emit(ring, 0); /* aux display base address, unused */
10881
10882         intel_mark_page_flip_active(intel_crtc->unpin_work);
10883         return 0;
10884 }
10885
10886 static int intel_gen3_queue_flip(struct drm_device *dev,
10887                                  struct drm_crtc *crtc,
10888                                  struct drm_framebuffer *fb,
10889                                  struct drm_i915_gem_object *obj,
10890                                  struct drm_i915_gem_request *req,
10891                                  uint32_t flags)
10892 {
10893         struct intel_engine_cs *ring = req->ring;
10894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10895         u32 flip_mask;
10896         int ret;
10897
10898         ret = intel_ring_begin(req, 6);
10899         if (ret)
10900                 return ret;
10901
10902         if (intel_crtc->plane)
10903                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10904         else
10905                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10906         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10907         intel_ring_emit(ring, MI_NOOP);
10908         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10909                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10910         intel_ring_emit(ring, fb->pitches[0]);
10911         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10912         intel_ring_emit(ring, MI_NOOP);
10913
10914         intel_mark_page_flip_active(intel_crtc->unpin_work);
10915         return 0;
10916 }
10917
10918 static int intel_gen4_queue_flip(struct drm_device *dev,
10919                                  struct drm_crtc *crtc,
10920                                  struct drm_framebuffer *fb,
10921                                  struct drm_i915_gem_object *obj,
10922                                  struct drm_i915_gem_request *req,
10923                                  uint32_t flags)
10924 {
10925         struct intel_engine_cs *ring = req->ring;
10926         struct drm_i915_private *dev_priv = dev->dev_private;
10927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10928         uint32_t pf, pipesrc;
10929         int ret;
10930
10931         ret = intel_ring_begin(req, 4);
10932         if (ret)
10933                 return ret;
10934
10935         /* i965+ uses the linear or tiled offsets from the
10936          * Display Registers (which do not change across a page-flip)
10937          * so we need only reprogram the base address.
10938          */
10939         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10940                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10941         intel_ring_emit(ring, fb->pitches[0]);
10942         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10943                         obj->tiling_mode);
10944
10945         /* XXX Enabling the panel-fitter across page-flip is so far
10946          * untested on non-native modes, so ignore it for now.
10947          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10948          */
10949         pf = 0;
10950         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10951         intel_ring_emit(ring, pf | pipesrc);
10952
10953         intel_mark_page_flip_active(intel_crtc->unpin_work);
10954         return 0;
10955 }
10956
10957 static int intel_gen6_queue_flip(struct drm_device *dev,
10958                                  struct drm_crtc *crtc,
10959                                  struct drm_framebuffer *fb,
10960                                  struct drm_i915_gem_object *obj,
10961                                  struct drm_i915_gem_request *req,
10962                                  uint32_t flags)
10963 {
10964         struct intel_engine_cs *ring = req->ring;
10965         struct drm_i915_private *dev_priv = dev->dev_private;
10966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10967         uint32_t pf, pipesrc;
10968         int ret;
10969
10970         ret = intel_ring_begin(req, 4);
10971         if (ret)
10972                 return ret;
10973
10974         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10975                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10976         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10977         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10978
10979         /* Contrary to the suggestions in the documentation,
10980          * "Enable Panel Fitter" does not seem to be required when page
10981          * flipping with a non-native mode, and worse causes a normal
10982          * modeset to fail.
10983          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10984          */
10985         pf = 0;
10986         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10987         intel_ring_emit(ring, pf | pipesrc);
10988
10989         intel_mark_page_flip_active(intel_crtc->unpin_work);
10990         return 0;
10991 }
10992
10993 static int intel_gen7_queue_flip(struct drm_device *dev,
10994                                  struct drm_crtc *crtc,
10995                                  struct drm_framebuffer *fb,
10996                                  struct drm_i915_gem_object *obj,
10997                                  struct drm_i915_gem_request *req,
10998                                  uint32_t flags)
10999 {
11000         struct intel_engine_cs *ring = req->ring;
11001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11002         uint32_t plane_bit = 0;
11003         int len, ret;
11004
11005         switch (intel_crtc->plane) {
11006         case PLANE_A:
11007                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11008                 break;
11009         case PLANE_B:
11010                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11011                 break;
11012         case PLANE_C:
11013                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11014                 break;
11015         default:
11016                 WARN_ONCE(1, "unknown plane in flip command\n");
11017                 return -ENODEV;
11018         }
11019
11020         len = 4;
11021         if (ring->id == RCS) {
11022                 len += 6;
11023                 /*
11024                  * On Gen 8, SRM is now taking an extra dword to accommodate
11025                  * 48bits addresses, and we need a NOOP for the batch size to
11026                  * stay even.
11027                  */
11028                 if (IS_GEN8(dev))
11029                         len += 2;
11030         }
11031
11032         /*
11033          * BSpec MI_DISPLAY_FLIP for IVB:
11034          * "The full packet must be contained within the same cache line."
11035          *
11036          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11037          * cacheline, if we ever start emitting more commands before
11038          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11039          * then do the cacheline alignment, and finally emit the
11040          * MI_DISPLAY_FLIP.
11041          */
11042         ret = intel_ring_cacheline_align(req);
11043         if (ret)
11044                 return ret;
11045
11046         ret = intel_ring_begin(req, len);
11047         if (ret)
11048                 return ret;
11049
11050         /* Unmask the flip-done completion message. Note that the bspec says that
11051          * we should do this for both the BCS and RCS, and that we must not unmask
11052          * more than one flip event at any time (or ensure that one flip message
11053          * can be sent by waiting for flip-done prior to queueing new flips).
11054          * Experimentation says that BCS works despite DERRMR masking all
11055          * flip-done completion events and that unmasking all planes at once
11056          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11057          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11058          */
11059         if (ring->id == RCS) {
11060                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11061                 intel_ring_emit(ring, DERRMR);
11062                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11063                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11064                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11065                 if (IS_GEN8(dev))
11066                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11067                                               MI_SRM_LRM_GLOBAL_GTT);
11068                 else
11069                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11070                                               MI_SRM_LRM_GLOBAL_GTT);
11071                 intel_ring_emit(ring, DERRMR);
11072                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11073                 if (IS_GEN8(dev)) {
11074                         intel_ring_emit(ring, 0);
11075                         intel_ring_emit(ring, MI_NOOP);
11076                 }
11077         }
11078
11079         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11080         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11081         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11082         intel_ring_emit(ring, (MI_NOOP));
11083
11084         intel_mark_page_flip_active(intel_crtc->unpin_work);
11085         return 0;
11086 }
11087
11088 static bool use_mmio_flip(struct intel_engine_cs *ring,
11089                           struct drm_i915_gem_object *obj)
11090 {
11091         /*
11092          * This is not being used for older platforms, because
11093          * non-availability of flip done interrupt forces us to use
11094          * CS flips. Older platforms derive flip done using some clever
11095          * tricks involving the flip_pending status bits and vblank irqs.
11096          * So using MMIO flips there would disrupt this mechanism.
11097          */
11098
11099         if (ring == NULL)
11100                 return true;
11101
11102         if (INTEL_INFO(ring->dev)->gen < 5)
11103                 return false;
11104
11105         if (i915.use_mmio_flip < 0)
11106                 return false;
11107         else if (i915.use_mmio_flip > 0)
11108                 return true;
11109         else if (i915.enable_execlists)
11110                 return true;
11111         else
11112                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11113 }
11114
11115 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11116                              struct intel_unpin_work *work)
11117 {
11118         struct drm_device *dev = intel_crtc->base.dev;
11119         struct drm_i915_private *dev_priv = dev->dev_private;
11120         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11121         const enum pipe pipe = intel_crtc->pipe;
11122         u32 ctl, stride;
11123
11124         ctl = I915_READ(PLANE_CTL(pipe, 0));
11125         ctl &= ~PLANE_CTL_TILED_MASK;
11126         switch (fb->modifier[0]) {
11127         case DRM_FORMAT_MOD_NONE:
11128                 break;
11129         case I915_FORMAT_MOD_X_TILED:
11130                 ctl |= PLANE_CTL_TILED_X;
11131                 break;
11132         case I915_FORMAT_MOD_Y_TILED:
11133                 ctl |= PLANE_CTL_TILED_Y;
11134                 break;
11135         case I915_FORMAT_MOD_Yf_TILED:
11136                 ctl |= PLANE_CTL_TILED_YF;
11137                 break;
11138         default:
11139                 MISSING_CASE(fb->modifier[0]);
11140         }
11141
11142         /*
11143          * The stride is either expressed as a multiple of 64 bytes chunks for
11144          * linear buffers or in number of tiles for tiled buffers.
11145          */
11146         stride = fb->pitches[0] /
11147                  intel_fb_stride_alignment(dev, fb->modifier[0],
11148                                            fb->pixel_format);
11149
11150         /*
11151          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11152          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11153          */
11154         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11155         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11156
11157         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11158         POSTING_READ(PLANE_SURF(pipe, 0));
11159 }
11160
11161 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11162                              struct intel_unpin_work *work)
11163 {
11164         struct drm_device *dev = intel_crtc->base.dev;
11165         struct drm_i915_private *dev_priv = dev->dev_private;
11166         struct intel_framebuffer *intel_fb =
11167                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11168         struct drm_i915_gem_object *obj = intel_fb->obj;
11169         u32 dspcntr;
11170         u32 reg;
11171
11172         reg = DSPCNTR(intel_crtc->plane);
11173         dspcntr = I915_READ(reg);
11174
11175         if (obj->tiling_mode != I915_TILING_NONE)
11176                 dspcntr |= DISPPLANE_TILED;
11177         else
11178                 dspcntr &= ~DISPPLANE_TILED;
11179
11180         I915_WRITE(reg, dspcntr);
11181
11182         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11183         POSTING_READ(DSPSURF(intel_crtc->plane));
11184 }
11185
11186 /*
11187  * XXX: This is the temporary way to update the plane registers until we get
11188  * around to using the usual plane update functions for MMIO flips
11189  */
11190 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11191 {
11192         struct intel_crtc *crtc = mmio_flip->crtc;
11193         struct intel_unpin_work *work;
11194
11195         spin_lock_irq(&crtc->base.dev->event_lock);
11196         work = crtc->unpin_work;
11197         spin_unlock_irq(&crtc->base.dev->event_lock);
11198         if (work == NULL)
11199                 return;
11200
11201         intel_mark_page_flip_active(work);
11202
11203         intel_pipe_update_start(crtc);
11204
11205         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11206                 skl_do_mmio_flip(crtc, work);
11207         else
11208                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11209                 ilk_do_mmio_flip(crtc, work);
11210
11211         intel_pipe_update_end(crtc);
11212 }
11213
11214 static void intel_mmio_flip_work_func(struct work_struct *work)
11215 {
11216         struct intel_mmio_flip *mmio_flip =
11217                 container_of(work, struct intel_mmio_flip, work);
11218
11219         if (mmio_flip->req) {
11220                 WARN_ON(__i915_wait_request(mmio_flip->req,
11221                                             mmio_flip->crtc->reset_counter,
11222                                             false, NULL,
11223                                             &mmio_flip->i915->rps.mmioflips));
11224                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11225         }
11226
11227         intel_do_mmio_flip(mmio_flip);
11228         kfree(mmio_flip);
11229 }
11230
11231 static int intel_queue_mmio_flip(struct drm_device *dev,
11232                                  struct drm_crtc *crtc,
11233                                  struct drm_framebuffer *fb,
11234                                  struct drm_i915_gem_object *obj,
11235                                  struct intel_engine_cs *ring,
11236                                  uint32_t flags)
11237 {
11238         struct intel_mmio_flip *mmio_flip;
11239
11240         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11241         if (mmio_flip == NULL)
11242                 return -ENOMEM;
11243
11244         mmio_flip->i915 = to_i915(dev);
11245         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11246         mmio_flip->crtc = to_intel_crtc(crtc);
11247
11248         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11249         schedule_work(&mmio_flip->work);
11250
11251         return 0;
11252 }
11253
11254 static int intel_default_queue_flip(struct drm_device *dev,
11255                                     struct drm_crtc *crtc,
11256                                     struct drm_framebuffer *fb,
11257                                     struct drm_i915_gem_object *obj,
11258                                     struct drm_i915_gem_request *req,
11259                                     uint32_t flags)
11260 {
11261         return -ENODEV;
11262 }
11263
11264 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11265                                          struct drm_crtc *crtc)
11266 {
11267         struct drm_i915_private *dev_priv = dev->dev_private;
11268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11269         struct intel_unpin_work *work = intel_crtc->unpin_work;
11270         u32 addr;
11271
11272         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11273                 return true;
11274
11275         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11276                 return false;
11277
11278         if (!work->enable_stall_check)
11279                 return false;
11280
11281         if (work->flip_ready_vblank == 0) {
11282                 if (work->flip_queued_req &&
11283                     !i915_gem_request_completed(work->flip_queued_req, true))
11284                         return false;
11285
11286                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11287         }
11288
11289         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11290                 return false;
11291
11292         /* Potential stall - if we see that the flip has happened,
11293          * assume a missed interrupt. */
11294         if (INTEL_INFO(dev)->gen >= 4)
11295                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11296         else
11297                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11298
11299         /* There is a potential issue here with a false positive after a flip
11300          * to the same address. We could address this by checking for a
11301          * non-incrementing frame counter.
11302          */
11303         return addr == work->gtt_offset;
11304 }
11305
11306 void intel_check_page_flip(struct drm_device *dev, int pipe)
11307 {
11308         struct drm_i915_private *dev_priv = dev->dev_private;
11309         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11311         struct intel_unpin_work *work;
11312
11313         WARN_ON(!in_interrupt());
11314
11315         if (crtc == NULL)
11316                 return;
11317
11318         spin_lock(&dev->event_lock);
11319         work = intel_crtc->unpin_work;
11320         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11321                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11322                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11323                 page_flip_completed(intel_crtc);
11324                 work = NULL;
11325         }
11326         if (work != NULL &&
11327             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11328                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11329         spin_unlock(&dev->event_lock);
11330 }
11331
11332 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11333                                 struct drm_framebuffer *fb,
11334                                 struct drm_pending_vblank_event *event,
11335                                 uint32_t page_flip_flags)
11336 {
11337         struct drm_device *dev = crtc->dev;
11338         struct drm_i915_private *dev_priv = dev->dev_private;
11339         struct drm_framebuffer *old_fb = crtc->primary->fb;
11340         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11342         struct drm_plane *primary = crtc->primary;
11343         enum pipe pipe = intel_crtc->pipe;
11344         struct intel_unpin_work *work;
11345         struct intel_engine_cs *ring;
11346         bool mmio_flip;
11347         struct drm_i915_gem_request *request = NULL;
11348         int ret;
11349
11350         /*
11351          * drm_mode_page_flip_ioctl() should already catch this, but double
11352          * check to be safe.  In the future we may enable pageflipping from
11353          * a disabled primary plane.
11354          */
11355         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11356                 return -EBUSY;
11357
11358         /* Can't change pixel format via MI display flips. */
11359         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11360                 return -EINVAL;
11361
11362         /*
11363          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11364          * Note that pitch changes could also affect these register.
11365          */
11366         if (INTEL_INFO(dev)->gen > 3 &&
11367             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11368              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11369                 return -EINVAL;
11370
11371         if (i915_terminally_wedged(&dev_priv->gpu_error))
11372                 goto out_hang;
11373
11374         work = kzalloc(sizeof(*work), GFP_KERNEL);
11375         if (work == NULL)
11376                 return -ENOMEM;
11377
11378         work->event = event;
11379         work->crtc = crtc;
11380         work->old_fb = old_fb;
11381         INIT_WORK(&work->work, intel_unpin_work_fn);
11382
11383         ret = drm_crtc_vblank_get(crtc);
11384         if (ret)
11385                 goto free_work;
11386
11387         /* We borrow the event spin lock for protecting unpin_work */
11388         spin_lock_irq(&dev->event_lock);
11389         if (intel_crtc->unpin_work) {
11390                 /* Before declaring the flip queue wedged, check if
11391                  * the hardware completed the operation behind our backs.
11392                  */
11393                 if (__intel_pageflip_stall_check(dev, crtc)) {
11394                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11395                         page_flip_completed(intel_crtc);
11396                 } else {
11397                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11398                         spin_unlock_irq(&dev->event_lock);
11399
11400                         drm_crtc_vblank_put(crtc);
11401                         kfree(work);
11402                         return -EBUSY;
11403                 }
11404         }
11405         intel_crtc->unpin_work = work;
11406         spin_unlock_irq(&dev->event_lock);
11407
11408         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11409                 flush_workqueue(dev_priv->wq);
11410
11411         /* Reference the objects for the scheduled work. */
11412         drm_framebuffer_reference(work->old_fb);
11413         drm_gem_object_reference(&obj->base);
11414
11415         crtc->primary->fb = fb;
11416         update_state_fb(crtc->primary);
11417
11418         work->pending_flip_obj = obj;
11419
11420         ret = i915_mutex_lock_interruptible(dev);
11421         if (ret)
11422                 goto cleanup;
11423
11424         atomic_inc(&intel_crtc->unpin_work_count);
11425         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11426
11427         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11428                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11429
11430         if (IS_VALLEYVIEW(dev)) {
11431                 ring = &dev_priv->ring[BCS];
11432                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11433                         /* vlv: DISPLAY_FLIP fails to change tiling */
11434                         ring = NULL;
11435         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11436                 ring = &dev_priv->ring[BCS];
11437         } else if (INTEL_INFO(dev)->gen >= 7) {
11438                 ring = i915_gem_request_get_ring(obj->last_write_req);
11439                 if (ring == NULL || ring->id != RCS)
11440                         ring = &dev_priv->ring[BCS];
11441         } else {
11442                 ring = &dev_priv->ring[RCS];
11443         }
11444
11445         mmio_flip = use_mmio_flip(ring, obj);
11446
11447         /* When using CS flips, we want to emit semaphores between rings.
11448          * However, when using mmio flips we will create a task to do the
11449          * synchronisation, so all we want here is to pin the framebuffer
11450          * into the display plane and skip any waits.
11451          */
11452         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11453                                          crtc->primary->state,
11454                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11455         if (ret)
11456                 goto cleanup_pending;
11457
11458         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11459                                                   obj, 0);
11460         work->gtt_offset += intel_crtc->dspaddr_offset;
11461
11462         if (mmio_flip) {
11463                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11464                                             page_flip_flags);
11465                 if (ret)
11466                         goto cleanup_unpin;
11467
11468                 i915_gem_request_assign(&work->flip_queued_req,
11469                                         obj->last_write_req);
11470         } else {
11471                 if (!request) {
11472                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11473                         if (ret)
11474                                 goto cleanup_unpin;
11475                 }
11476
11477                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11478                                                    page_flip_flags);
11479                 if (ret)
11480                         goto cleanup_unpin;
11481
11482                 i915_gem_request_assign(&work->flip_queued_req, request);
11483         }
11484
11485         if (request)
11486                 i915_add_request_no_flush(request);
11487
11488         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11489         work->enable_stall_check = true;
11490
11491         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11492                           to_intel_plane(primary)->frontbuffer_bit);
11493         mutex_unlock(&dev->struct_mutex);
11494
11495         intel_fbc_disable_crtc(intel_crtc);
11496         intel_frontbuffer_flip_prepare(dev,
11497                                        to_intel_plane(primary)->frontbuffer_bit);
11498
11499         trace_i915_flip_request(intel_crtc->plane, obj);
11500
11501         return 0;
11502
11503 cleanup_unpin:
11504         intel_unpin_fb_obj(fb, crtc->primary->state);
11505 cleanup_pending:
11506         if (request)
11507                 i915_gem_request_cancel(request);
11508         atomic_dec(&intel_crtc->unpin_work_count);
11509         mutex_unlock(&dev->struct_mutex);
11510 cleanup:
11511         crtc->primary->fb = old_fb;
11512         update_state_fb(crtc->primary);
11513
11514         drm_gem_object_unreference_unlocked(&obj->base);
11515         drm_framebuffer_unreference(work->old_fb);
11516
11517         spin_lock_irq(&dev->event_lock);
11518         intel_crtc->unpin_work = NULL;
11519         spin_unlock_irq(&dev->event_lock);
11520
11521         drm_crtc_vblank_put(crtc);
11522 free_work:
11523         kfree(work);
11524
11525         if (ret == -EIO) {
11526                 struct drm_atomic_state *state;
11527                 struct drm_plane_state *plane_state;
11528
11529 out_hang:
11530                 state = drm_atomic_state_alloc(dev);
11531                 if (!state)
11532                         return -ENOMEM;
11533                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11534
11535 retry:
11536                 plane_state = drm_atomic_get_plane_state(state, primary);
11537                 ret = PTR_ERR_OR_ZERO(plane_state);
11538                 if (!ret) {
11539                         drm_atomic_set_fb_for_plane(plane_state, fb);
11540
11541                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11542                         if (!ret)
11543                                 ret = drm_atomic_commit(state);
11544                 }
11545
11546                 if (ret == -EDEADLK) {
11547                         drm_modeset_backoff(state->acquire_ctx);
11548                         drm_atomic_state_clear(state);
11549                         goto retry;
11550                 }
11551
11552                 if (ret)
11553                         drm_atomic_state_free(state);
11554
11555                 if (ret == 0 && event) {
11556                         spin_lock_irq(&dev->event_lock);
11557                         drm_send_vblank_event(dev, pipe, event);
11558                         spin_unlock_irq(&dev->event_lock);
11559                 }
11560         }
11561         return ret;
11562 }
11563
11564
11565 /**
11566  * intel_wm_need_update - Check whether watermarks need updating
11567  * @plane: drm plane
11568  * @state: new plane state
11569  *
11570  * Check current plane state versus the new one to determine whether
11571  * watermarks need to be recalculated.
11572  *
11573  * Returns true or false.
11574  */
11575 static bool intel_wm_need_update(struct drm_plane *plane,
11576                                  struct drm_plane_state *state)
11577 {
11578         /* Update watermarks on tiling changes. */
11579         if (!plane->state->fb || !state->fb ||
11580             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11581             plane->state->rotation != state->rotation)
11582                 return true;
11583
11584         if (plane->state->crtc_w != state->crtc_w)
11585                 return true;
11586
11587         return false;
11588 }
11589
11590 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11591                                     struct drm_plane_state *plane_state)
11592 {
11593         struct drm_crtc *crtc = crtc_state->crtc;
11594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11595         struct drm_plane *plane = plane_state->plane;
11596         struct drm_device *dev = crtc->dev;
11597         struct drm_i915_private *dev_priv = dev->dev_private;
11598         struct intel_plane_state *old_plane_state =
11599                 to_intel_plane_state(plane->state);
11600         int idx = intel_crtc->base.base.id, ret;
11601         int i = drm_plane_index(plane);
11602         bool mode_changed = needs_modeset(crtc_state);
11603         bool was_crtc_enabled = crtc->state->active;
11604         bool is_crtc_enabled = crtc_state->active;
11605
11606         bool turn_off, turn_on, visible, was_visible;
11607         struct drm_framebuffer *fb = plane_state->fb;
11608
11609         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11610             plane->type != DRM_PLANE_TYPE_CURSOR) {
11611                 ret = skl_update_scaler_plane(
11612                         to_intel_crtc_state(crtc_state),
11613                         to_intel_plane_state(plane_state));
11614                 if (ret)
11615                         return ret;
11616         }
11617
11618         was_visible = old_plane_state->visible;
11619         visible = to_intel_plane_state(plane_state)->visible;
11620
11621         if (!was_crtc_enabled && WARN_ON(was_visible))
11622                 was_visible = false;
11623
11624         if (!is_crtc_enabled && WARN_ON(visible))
11625                 visible = false;
11626
11627         if (!was_visible && !visible)
11628                 return 0;
11629
11630         turn_off = was_visible && (!visible || mode_changed);
11631         turn_on = visible && (!was_visible || mode_changed);
11632
11633         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11634                          plane->base.id, fb ? fb->base.id : -1);
11635
11636         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11637                          plane->base.id, was_visible, visible,
11638                          turn_off, turn_on, mode_changed);
11639
11640         if (turn_on) {
11641                 intel_crtc->atomic.update_wm_pre = true;
11642                 /* must disable cxsr around plane enable/disable */
11643                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11644                         intel_crtc->atomic.disable_cxsr = true;
11645                         /* to potentially re-enable cxsr */
11646                         intel_crtc->atomic.wait_vblank = true;
11647                         intel_crtc->atomic.update_wm_post = true;
11648                 }
11649         } else if (turn_off) {
11650                 intel_crtc->atomic.update_wm_post = true;
11651                 /* must disable cxsr around plane enable/disable */
11652                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11653                         if (is_crtc_enabled)
11654                                 intel_crtc->atomic.wait_vblank = true;
11655                         intel_crtc->atomic.disable_cxsr = true;
11656                 }
11657         } else if (intel_wm_need_update(plane, plane_state)) {
11658                 intel_crtc->atomic.update_wm_pre = true;
11659         }
11660
11661         if (visible || was_visible)
11662                 intel_crtc->atomic.fb_bits |=
11663                         to_intel_plane(plane)->frontbuffer_bit;
11664
11665         switch (plane->type) {
11666         case DRM_PLANE_TYPE_PRIMARY:
11667                 intel_crtc->atomic.wait_for_flips = true;
11668                 intel_crtc->atomic.pre_disable_primary = turn_off;
11669                 intel_crtc->atomic.post_enable_primary = turn_on;
11670
11671                 if (turn_off) {
11672                         /*
11673                          * FIXME: Actually if we will still have any other
11674                          * plane enabled on the pipe we could let IPS enabled
11675                          * still, but for now lets consider that when we make
11676                          * primary invisible by setting DSPCNTR to 0 on
11677                          * update_primary_plane function IPS needs to be
11678                          * disable.
11679                          */
11680                         intel_crtc->atomic.disable_ips = true;
11681
11682                         intel_crtc->atomic.disable_fbc = true;
11683                 }
11684
11685                 /*
11686                  * FBC does not work on some platforms for rotated
11687                  * planes, so disable it when rotation is not 0 and
11688                  * update it when rotation is set back to 0.
11689                  *
11690                  * FIXME: This is redundant with the fbc update done in
11691                  * the primary plane enable function except that that
11692                  * one is done too late. We eventually need to unify
11693                  * this.
11694                  */
11695
11696                 if (visible &&
11697                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11698                     dev_priv->fbc.crtc == intel_crtc &&
11699                     plane_state->rotation != BIT(DRM_ROTATE_0))
11700                         intel_crtc->atomic.disable_fbc = true;
11701
11702                 /*
11703                  * BDW signals flip done immediately if the plane
11704                  * is disabled, even if the plane enable is already
11705                  * armed to occur at the next vblank :(
11706                  */
11707                 if (turn_on && IS_BROADWELL(dev))
11708                         intel_crtc->atomic.wait_vblank = true;
11709
11710                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11711                 break;
11712         case DRM_PLANE_TYPE_CURSOR:
11713                 break;
11714         case DRM_PLANE_TYPE_OVERLAY:
11715                 if (turn_off && !mode_changed) {
11716                         intel_crtc->atomic.wait_vblank = true;
11717                         intel_crtc->atomic.update_sprite_watermarks |=
11718                                 1 << i;
11719                 }
11720         }
11721         return 0;
11722 }
11723
11724 static bool encoders_cloneable(const struct intel_encoder *a,
11725                                const struct intel_encoder *b)
11726 {
11727         /* masks could be asymmetric, so check both ways */
11728         return a == b || (a->cloneable & (1 << b->type) &&
11729                           b->cloneable & (1 << a->type));
11730 }
11731
11732 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11733                                          struct intel_crtc *crtc,
11734                                          struct intel_encoder *encoder)
11735 {
11736         struct intel_encoder *source_encoder;
11737         struct drm_connector *connector;
11738         struct drm_connector_state *connector_state;
11739         int i;
11740
11741         for_each_connector_in_state(state, connector, connector_state, i) {
11742                 if (connector_state->crtc != &crtc->base)
11743                         continue;
11744
11745                 source_encoder =
11746                         to_intel_encoder(connector_state->best_encoder);
11747                 if (!encoders_cloneable(encoder, source_encoder))
11748                         return false;
11749         }
11750
11751         return true;
11752 }
11753
11754 static bool check_encoder_cloning(struct drm_atomic_state *state,
11755                                   struct intel_crtc *crtc)
11756 {
11757         struct intel_encoder *encoder;
11758         struct drm_connector *connector;
11759         struct drm_connector_state *connector_state;
11760         int i;
11761
11762         for_each_connector_in_state(state, connector, connector_state, i) {
11763                 if (connector_state->crtc != &crtc->base)
11764                         continue;
11765
11766                 encoder = to_intel_encoder(connector_state->best_encoder);
11767                 if (!check_single_encoder_cloning(state, crtc, encoder))
11768                         return false;
11769         }
11770
11771         return true;
11772 }
11773
11774 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11775                                    struct drm_crtc_state *crtc_state)
11776 {
11777         struct drm_device *dev = crtc->dev;
11778         struct drm_i915_private *dev_priv = dev->dev_private;
11779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11780         struct intel_crtc_state *pipe_config =
11781                 to_intel_crtc_state(crtc_state);
11782         struct drm_atomic_state *state = crtc_state->state;
11783         int ret;
11784         bool mode_changed = needs_modeset(crtc_state);
11785
11786         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11787                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11788                 return -EINVAL;
11789         }
11790
11791         if (mode_changed && !crtc_state->active)
11792                 intel_crtc->atomic.update_wm_post = true;
11793
11794         if (mode_changed && crtc_state->enable &&
11795             dev_priv->display.crtc_compute_clock &&
11796             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11797                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11798                                                            pipe_config);
11799                 if (ret)
11800                         return ret;
11801         }
11802
11803         ret = 0;
11804         if (INTEL_INFO(dev)->gen >= 9) {
11805                 if (mode_changed)
11806                         ret = skl_update_scaler_crtc(pipe_config);
11807
11808                 if (!ret)
11809                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11810                                                          pipe_config);
11811         }
11812
11813         return ret;
11814 }
11815
11816 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11817         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11818         .load_lut = intel_crtc_load_lut,
11819         .atomic_begin = intel_begin_crtc_commit,
11820         .atomic_flush = intel_finish_crtc_commit,
11821         .atomic_check = intel_crtc_atomic_check,
11822 };
11823
11824 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11825 {
11826         struct intel_connector *connector;
11827
11828         for_each_intel_connector(dev, connector) {
11829                 if (connector->base.encoder) {
11830                         connector->base.state->best_encoder =
11831                                 connector->base.encoder;
11832                         connector->base.state->crtc =
11833                                 connector->base.encoder->crtc;
11834                 } else {
11835                         connector->base.state->best_encoder = NULL;
11836                         connector->base.state->crtc = NULL;
11837                 }
11838         }
11839 }
11840
11841 static void
11842 connected_sink_compute_bpp(struct intel_connector *connector,
11843                            struct intel_crtc_state *pipe_config)
11844 {
11845         int bpp = pipe_config->pipe_bpp;
11846
11847         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11848                 connector->base.base.id,
11849                 connector->base.name);
11850
11851         /* Don't use an invalid EDID bpc value */
11852         if (connector->base.display_info.bpc &&
11853             connector->base.display_info.bpc * 3 < bpp) {
11854                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11855                               bpp, connector->base.display_info.bpc*3);
11856                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11857         }
11858
11859         /* Clamp bpp to 8 on screens without EDID 1.4 */
11860         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11861                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11862                               bpp);
11863                 pipe_config->pipe_bpp = 24;
11864         }
11865 }
11866
11867 static int
11868 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11869                           struct intel_crtc_state *pipe_config)
11870 {
11871         struct drm_device *dev = crtc->base.dev;
11872         struct drm_atomic_state *state;
11873         struct drm_connector *connector;
11874         struct drm_connector_state *connector_state;
11875         int bpp, i;
11876
11877         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11878                 bpp = 10*3;
11879         else if (INTEL_INFO(dev)->gen >= 5)
11880                 bpp = 12*3;
11881         else
11882                 bpp = 8*3;
11883
11884
11885         pipe_config->pipe_bpp = bpp;
11886
11887         state = pipe_config->base.state;
11888
11889         /* Clamp display bpp to EDID value */
11890         for_each_connector_in_state(state, connector, connector_state, i) {
11891                 if (connector_state->crtc != &crtc->base)
11892                         continue;
11893
11894                 connected_sink_compute_bpp(to_intel_connector(connector),
11895                                            pipe_config);
11896         }
11897
11898         return bpp;
11899 }
11900
11901 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11902 {
11903         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11904                         "type: 0x%x flags: 0x%x\n",
11905                 mode->crtc_clock,
11906                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11907                 mode->crtc_hsync_end, mode->crtc_htotal,
11908                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11909                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11910 }
11911
11912 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11913                                    struct intel_crtc_state *pipe_config,
11914                                    const char *context)
11915 {
11916         struct drm_device *dev = crtc->base.dev;
11917         struct drm_plane *plane;
11918         struct intel_plane *intel_plane;
11919         struct intel_plane_state *state;
11920         struct drm_framebuffer *fb;
11921
11922         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11923                       context, pipe_config, pipe_name(crtc->pipe));
11924
11925         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11926         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11927                       pipe_config->pipe_bpp, pipe_config->dither);
11928         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11929                       pipe_config->has_pch_encoder,
11930                       pipe_config->fdi_lanes,
11931                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11932                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11933                       pipe_config->fdi_m_n.tu);
11934         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11935                       pipe_config->has_dp_encoder,
11936                       pipe_config->lane_count,
11937                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11938                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11939                       pipe_config->dp_m_n.tu);
11940
11941         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11942                       pipe_config->has_dp_encoder,
11943                       pipe_config->lane_count,
11944                       pipe_config->dp_m2_n2.gmch_m,
11945                       pipe_config->dp_m2_n2.gmch_n,
11946                       pipe_config->dp_m2_n2.link_m,
11947                       pipe_config->dp_m2_n2.link_n,
11948                       pipe_config->dp_m2_n2.tu);
11949
11950         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11951                       pipe_config->has_audio,
11952                       pipe_config->has_infoframe);
11953
11954         DRM_DEBUG_KMS("requested mode:\n");
11955         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11956         DRM_DEBUG_KMS("adjusted mode:\n");
11957         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11958         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11959         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11960         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11961                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11962         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11963                       crtc->num_scalers,
11964                       pipe_config->scaler_state.scaler_users,
11965                       pipe_config->scaler_state.scaler_id);
11966         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11967                       pipe_config->gmch_pfit.control,
11968                       pipe_config->gmch_pfit.pgm_ratios,
11969                       pipe_config->gmch_pfit.lvds_border_bits);
11970         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11971                       pipe_config->pch_pfit.pos,
11972                       pipe_config->pch_pfit.size,
11973                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11974         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11975         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11976
11977         if (IS_BROXTON(dev)) {
11978                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11979                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11980                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11981                               pipe_config->ddi_pll_sel,
11982                               pipe_config->dpll_hw_state.ebb0,
11983                               pipe_config->dpll_hw_state.ebb4,
11984                               pipe_config->dpll_hw_state.pll0,
11985                               pipe_config->dpll_hw_state.pll1,
11986                               pipe_config->dpll_hw_state.pll2,
11987                               pipe_config->dpll_hw_state.pll3,
11988                               pipe_config->dpll_hw_state.pll6,
11989                               pipe_config->dpll_hw_state.pll8,
11990                               pipe_config->dpll_hw_state.pll9,
11991                               pipe_config->dpll_hw_state.pll10,
11992                               pipe_config->dpll_hw_state.pcsdw12);
11993         } else if (IS_SKYLAKE(dev)) {
11994                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11995                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11996                               pipe_config->ddi_pll_sel,
11997                               pipe_config->dpll_hw_state.ctrl1,
11998                               pipe_config->dpll_hw_state.cfgcr1,
11999                               pipe_config->dpll_hw_state.cfgcr2);
12000         } else if (HAS_DDI(dev)) {
12001                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12002                               pipe_config->ddi_pll_sel,
12003                               pipe_config->dpll_hw_state.wrpll);
12004         } else {
12005                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12006                               "fp0: 0x%x, fp1: 0x%x\n",
12007                               pipe_config->dpll_hw_state.dpll,
12008                               pipe_config->dpll_hw_state.dpll_md,
12009                               pipe_config->dpll_hw_state.fp0,
12010                               pipe_config->dpll_hw_state.fp1);
12011         }
12012
12013         DRM_DEBUG_KMS("planes on this crtc\n");
12014         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12015                 intel_plane = to_intel_plane(plane);
12016                 if (intel_plane->pipe != crtc->pipe)
12017                         continue;
12018
12019                 state = to_intel_plane_state(plane->state);
12020                 fb = state->base.fb;
12021                 if (!fb) {
12022                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12023                                 "disabled, scaler_id = %d\n",
12024                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12025                                 plane->base.id, intel_plane->pipe,
12026                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12027                                 drm_plane_index(plane), state->scaler_id);
12028                         continue;
12029                 }
12030
12031                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12032                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12033                         plane->base.id, intel_plane->pipe,
12034                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12035                         drm_plane_index(plane));
12036                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12037                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12038                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12039                         state->scaler_id,
12040                         state->src.x1 >> 16, state->src.y1 >> 16,
12041                         drm_rect_width(&state->src) >> 16,
12042                         drm_rect_height(&state->src) >> 16,
12043                         state->dst.x1, state->dst.y1,
12044                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12045         }
12046 }
12047
12048 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12049 {
12050         struct drm_device *dev = state->dev;
12051         struct intel_encoder *encoder;
12052         struct drm_connector *connector;
12053         struct drm_connector_state *connector_state;
12054         unsigned int used_ports = 0;
12055         int i;
12056
12057         /*
12058          * Walk the connector list instead of the encoder
12059          * list to detect the problem on ddi platforms
12060          * where there's just one encoder per digital port.
12061          */
12062         for_each_connector_in_state(state, connector, connector_state, i) {
12063                 if (!connector_state->best_encoder)
12064                         continue;
12065
12066                 encoder = to_intel_encoder(connector_state->best_encoder);
12067
12068                 WARN_ON(!connector_state->crtc);
12069
12070                 switch (encoder->type) {
12071                         unsigned int port_mask;
12072                 case INTEL_OUTPUT_UNKNOWN:
12073                         if (WARN_ON(!HAS_DDI(dev)))
12074                                 break;
12075                 case INTEL_OUTPUT_DISPLAYPORT:
12076                 case INTEL_OUTPUT_HDMI:
12077                 case INTEL_OUTPUT_EDP:
12078                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12079
12080                         /* the same port mustn't appear more than once */
12081                         if (used_ports & port_mask)
12082                                 return false;
12083
12084                         used_ports |= port_mask;
12085                 default:
12086                         break;
12087                 }
12088         }
12089
12090         return true;
12091 }
12092
12093 static void
12094 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12095 {
12096         struct drm_crtc_state tmp_state;
12097         struct intel_crtc_scaler_state scaler_state;
12098         struct intel_dpll_hw_state dpll_hw_state;
12099         enum intel_dpll_id shared_dpll;
12100         uint32_t ddi_pll_sel;
12101         bool force_thru;
12102
12103         /* FIXME: before the switch to atomic started, a new pipe_config was
12104          * kzalloc'd. Code that depends on any field being zero should be
12105          * fixed, so that the crtc_state can be safely duplicated. For now,
12106          * only fields that are know to not cause problems are preserved. */
12107
12108         tmp_state = crtc_state->base;
12109         scaler_state = crtc_state->scaler_state;
12110         shared_dpll = crtc_state->shared_dpll;
12111         dpll_hw_state = crtc_state->dpll_hw_state;
12112         ddi_pll_sel = crtc_state->ddi_pll_sel;
12113         force_thru = crtc_state->pch_pfit.force_thru;
12114
12115         memset(crtc_state, 0, sizeof *crtc_state);
12116
12117         crtc_state->base = tmp_state;
12118         crtc_state->scaler_state = scaler_state;
12119         crtc_state->shared_dpll = shared_dpll;
12120         crtc_state->dpll_hw_state = dpll_hw_state;
12121         crtc_state->ddi_pll_sel = ddi_pll_sel;
12122         crtc_state->pch_pfit.force_thru = force_thru;
12123 }
12124
12125 static int
12126 intel_modeset_pipe_config(struct drm_crtc *crtc,
12127                           struct intel_crtc_state *pipe_config)
12128 {
12129         struct drm_atomic_state *state = pipe_config->base.state;
12130         struct intel_encoder *encoder;
12131         struct drm_connector *connector;
12132         struct drm_connector_state *connector_state;
12133         int base_bpp, ret = -EINVAL;
12134         int i;
12135         bool retry = true;
12136
12137         clear_intel_crtc_state(pipe_config);
12138
12139         pipe_config->cpu_transcoder =
12140                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12141
12142         /*
12143          * Sanitize sync polarity flags based on requested ones. If neither
12144          * positive or negative polarity is requested, treat this as meaning
12145          * negative polarity.
12146          */
12147         if (!(pipe_config->base.adjusted_mode.flags &
12148               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12149                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12150
12151         if (!(pipe_config->base.adjusted_mode.flags &
12152               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12153                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12154
12155         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12156                                              pipe_config);
12157         if (base_bpp < 0)
12158                 goto fail;
12159
12160         /*
12161          * Determine the real pipe dimensions. Note that stereo modes can
12162          * increase the actual pipe size due to the frame doubling and
12163          * insertion of additional space for blanks between the frame. This
12164          * is stored in the crtc timings. We use the requested mode to do this
12165          * computation to clearly distinguish it from the adjusted mode, which
12166          * can be changed by the connectors in the below retry loop.
12167          */
12168         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12169                                &pipe_config->pipe_src_w,
12170                                &pipe_config->pipe_src_h);
12171
12172 encoder_retry:
12173         /* Ensure the port clock defaults are reset when retrying. */
12174         pipe_config->port_clock = 0;
12175         pipe_config->pixel_multiplier = 1;
12176
12177         /* Fill in default crtc timings, allow encoders to overwrite them. */
12178         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12179                               CRTC_STEREO_DOUBLE);
12180
12181         /* Pass our mode to the connectors and the CRTC to give them a chance to
12182          * adjust it according to limitations or connector properties, and also
12183          * a chance to reject the mode entirely.
12184          */
12185         for_each_connector_in_state(state, connector, connector_state, i) {
12186                 if (connector_state->crtc != crtc)
12187                         continue;
12188
12189                 encoder = to_intel_encoder(connector_state->best_encoder);
12190
12191                 if (!(encoder->compute_config(encoder, pipe_config))) {
12192                         DRM_DEBUG_KMS("Encoder config failure\n");
12193                         goto fail;
12194                 }
12195         }
12196
12197         /* Set default port clock if not overwritten by the encoder. Needs to be
12198          * done afterwards in case the encoder adjusts the mode. */
12199         if (!pipe_config->port_clock)
12200                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12201                         * pipe_config->pixel_multiplier;
12202
12203         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12204         if (ret < 0) {
12205                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12206                 goto fail;
12207         }
12208
12209         if (ret == RETRY) {
12210                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12211                         ret = -EINVAL;
12212                         goto fail;
12213                 }
12214
12215                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12216                 retry = false;
12217                 goto encoder_retry;
12218         }
12219
12220         /* Dithering seems to not pass-through bits correctly when it should, so
12221          * only enable it on 6bpc panels. */
12222         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12223         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12224                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12225
12226 fail:
12227         return ret;
12228 }
12229
12230 static void
12231 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12232 {
12233         struct drm_crtc *crtc;
12234         struct drm_crtc_state *crtc_state;
12235         int i;
12236
12237         /* Double check state. */
12238         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12239                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12240
12241                 /* Update hwmode for vblank functions */
12242                 if (crtc->state->active)
12243                         crtc->hwmode = crtc->state->adjusted_mode;
12244                 else
12245                         crtc->hwmode.crtc_clock = 0;
12246
12247                 /*
12248                  * Update legacy state to satisfy fbc code. This can
12249                  * be removed when fbc uses the atomic state.
12250                  */
12251                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12252                         struct drm_plane_state *plane_state = crtc->primary->state;
12253
12254                         crtc->primary->fb = plane_state->fb;
12255                         crtc->x = plane_state->src_x >> 16;
12256                         crtc->y = plane_state->src_y >> 16;
12257                 }
12258         }
12259 }
12260
12261 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12262 {
12263         int diff;
12264
12265         if (clock1 == clock2)
12266                 return true;
12267
12268         if (!clock1 || !clock2)
12269                 return false;
12270
12271         diff = abs(clock1 - clock2);
12272
12273         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12274                 return true;
12275
12276         return false;
12277 }
12278
12279 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12280         list_for_each_entry((intel_crtc), \
12281                             &(dev)->mode_config.crtc_list, \
12282                             base.head) \
12283                 if (mask & (1 <<(intel_crtc)->pipe))
12284
12285 static bool
12286 intel_compare_m_n(unsigned int m, unsigned int n,
12287                   unsigned int m2, unsigned int n2,
12288                   bool exact)
12289 {
12290         if (m == m2 && n == n2)
12291                 return true;
12292
12293         if (exact || !m || !n || !m2 || !n2)
12294                 return false;
12295
12296         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12297
12298         if (m > m2) {
12299                 while (m > m2) {
12300                         m2 <<= 1;
12301                         n2 <<= 1;
12302                 }
12303         } else if (m < m2) {
12304                 while (m < m2) {
12305                         m <<= 1;
12306                         n <<= 1;
12307                 }
12308         }
12309
12310         return m == m2 && n == n2;
12311 }
12312
12313 static bool
12314 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12315                        struct intel_link_m_n *m2_n2,
12316                        bool adjust)
12317 {
12318         if (m_n->tu == m2_n2->tu &&
12319             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12320                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12321             intel_compare_m_n(m_n->link_m, m_n->link_n,
12322                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12323                 if (adjust)
12324                         *m2_n2 = *m_n;
12325
12326                 return true;
12327         }
12328
12329         return false;
12330 }
12331
12332 static bool
12333 intel_pipe_config_compare(struct drm_device *dev,
12334                           struct intel_crtc_state *current_config,
12335                           struct intel_crtc_state *pipe_config,
12336                           bool adjust)
12337 {
12338         bool ret = true;
12339
12340 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12341         do { \
12342                 if (!adjust) \
12343                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12344                 else \
12345                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12346         } while (0)
12347
12348 #define PIPE_CONF_CHECK_X(name) \
12349         if (current_config->name != pipe_config->name) { \
12350                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12351                           "(expected 0x%08x, found 0x%08x)\n", \
12352                           current_config->name, \
12353                           pipe_config->name); \
12354                 ret = false; \
12355         }
12356
12357 #define PIPE_CONF_CHECK_I(name) \
12358         if (current_config->name != pipe_config->name) { \
12359                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12360                           "(expected %i, found %i)\n", \
12361                           current_config->name, \
12362                           pipe_config->name); \
12363                 ret = false; \
12364         }
12365
12366 #define PIPE_CONF_CHECK_M_N(name) \
12367         if (!intel_compare_link_m_n(&current_config->name, \
12368                                     &pipe_config->name,\
12369                                     adjust)) { \
12370                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12371                           "(expected tu %i gmch %i/%i link %i/%i, " \
12372                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12373                           current_config->name.tu, \
12374                           current_config->name.gmch_m, \
12375                           current_config->name.gmch_n, \
12376                           current_config->name.link_m, \
12377                           current_config->name.link_n, \
12378                           pipe_config->name.tu, \
12379                           pipe_config->name.gmch_m, \
12380                           pipe_config->name.gmch_n, \
12381                           pipe_config->name.link_m, \
12382                           pipe_config->name.link_n); \
12383                 ret = false; \
12384         }
12385
12386 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12387         if (!intel_compare_link_m_n(&current_config->name, \
12388                                     &pipe_config->name, adjust) && \
12389             !intel_compare_link_m_n(&current_config->alt_name, \
12390                                     &pipe_config->name, adjust)) { \
12391                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12392                           "(expected tu %i gmch %i/%i link %i/%i, " \
12393                           "or tu %i gmch %i/%i link %i/%i, " \
12394                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12395                           current_config->name.tu, \
12396                           current_config->name.gmch_m, \
12397                           current_config->name.gmch_n, \
12398                           current_config->name.link_m, \
12399                           current_config->name.link_n, \
12400                           current_config->alt_name.tu, \
12401                           current_config->alt_name.gmch_m, \
12402                           current_config->alt_name.gmch_n, \
12403                           current_config->alt_name.link_m, \
12404                           current_config->alt_name.link_n, \
12405                           pipe_config->name.tu, \
12406                           pipe_config->name.gmch_m, \
12407                           pipe_config->name.gmch_n, \
12408                           pipe_config->name.link_m, \
12409                           pipe_config->name.link_n); \
12410                 ret = false; \
12411         }
12412
12413 /* This is required for BDW+ where there is only one set of registers for
12414  * switching between high and low RR.
12415  * This macro can be used whenever a comparison has to be made between one
12416  * hw state and multiple sw state variables.
12417  */
12418 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12419         if ((current_config->name != pipe_config->name) && \
12420                 (current_config->alt_name != pipe_config->name)) { \
12421                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12422                                   "(expected %i or %i, found %i)\n", \
12423                                   current_config->name, \
12424                                   current_config->alt_name, \
12425                                   pipe_config->name); \
12426                         ret = false; \
12427         }
12428
12429 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12430         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12431                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12432                           "(expected %i, found %i)\n", \
12433                           current_config->name & (mask), \
12434                           pipe_config->name & (mask)); \
12435                 ret = false; \
12436         }
12437
12438 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12439         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12440                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12441                           "(expected %i, found %i)\n", \
12442                           current_config->name, \
12443                           pipe_config->name); \
12444                 ret = false; \
12445         }
12446
12447 #define PIPE_CONF_QUIRK(quirk)  \
12448         ((current_config->quirks | pipe_config->quirks) & (quirk))
12449
12450         PIPE_CONF_CHECK_I(cpu_transcoder);
12451
12452         PIPE_CONF_CHECK_I(has_pch_encoder);
12453         PIPE_CONF_CHECK_I(fdi_lanes);
12454         PIPE_CONF_CHECK_M_N(fdi_m_n);
12455
12456         PIPE_CONF_CHECK_I(has_dp_encoder);
12457         PIPE_CONF_CHECK_I(lane_count);
12458
12459         if (INTEL_INFO(dev)->gen < 8) {
12460                 PIPE_CONF_CHECK_M_N(dp_m_n);
12461
12462                 PIPE_CONF_CHECK_I(has_drrs);
12463                 if (current_config->has_drrs)
12464                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12465         } else
12466                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12467
12468         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12469         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12470         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12471         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12472         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12473         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12474
12475         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12476         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12477         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12478         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12479         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12480         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12481
12482         PIPE_CONF_CHECK_I(pixel_multiplier);
12483         PIPE_CONF_CHECK_I(has_hdmi_sink);
12484         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12485             IS_VALLEYVIEW(dev))
12486                 PIPE_CONF_CHECK_I(limited_color_range);
12487         PIPE_CONF_CHECK_I(has_infoframe);
12488
12489         PIPE_CONF_CHECK_I(has_audio);
12490
12491         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12492                               DRM_MODE_FLAG_INTERLACE);
12493
12494         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12495                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12496                                       DRM_MODE_FLAG_PHSYNC);
12497                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12498                                       DRM_MODE_FLAG_NHSYNC);
12499                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12500                                       DRM_MODE_FLAG_PVSYNC);
12501                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12502                                       DRM_MODE_FLAG_NVSYNC);
12503         }
12504
12505         PIPE_CONF_CHECK_X(gmch_pfit.control);
12506         /* pfit ratios are autocomputed by the hw on gen4+ */
12507         if (INTEL_INFO(dev)->gen < 4)
12508                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12509         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12510
12511         if (!adjust) {
12512                 PIPE_CONF_CHECK_I(pipe_src_w);
12513                 PIPE_CONF_CHECK_I(pipe_src_h);
12514
12515                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12516                 if (current_config->pch_pfit.enabled) {
12517                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12518                         PIPE_CONF_CHECK_X(pch_pfit.size);
12519                 }
12520
12521                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12522         }
12523
12524         /* BDW+ don't expose a synchronous way to read the state */
12525         if (IS_HASWELL(dev))
12526                 PIPE_CONF_CHECK_I(ips_enabled);
12527
12528         PIPE_CONF_CHECK_I(double_wide);
12529
12530         PIPE_CONF_CHECK_X(ddi_pll_sel);
12531
12532         PIPE_CONF_CHECK_I(shared_dpll);
12533         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12534         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12535         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12536         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12537         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12538         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12539         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12540         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12541
12542         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12543                 PIPE_CONF_CHECK_I(pipe_bpp);
12544
12545         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12546         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12547
12548 #undef PIPE_CONF_CHECK_X
12549 #undef PIPE_CONF_CHECK_I
12550 #undef PIPE_CONF_CHECK_I_ALT
12551 #undef PIPE_CONF_CHECK_FLAGS
12552 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12553 #undef PIPE_CONF_QUIRK
12554 #undef INTEL_ERR_OR_DBG_KMS
12555
12556         return ret;
12557 }
12558
12559 static void check_wm_state(struct drm_device *dev)
12560 {
12561         struct drm_i915_private *dev_priv = dev->dev_private;
12562         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12563         struct intel_crtc *intel_crtc;
12564         int plane;
12565
12566         if (INTEL_INFO(dev)->gen < 9)
12567                 return;
12568
12569         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12570         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12571
12572         for_each_intel_crtc(dev, intel_crtc) {
12573                 struct skl_ddb_entry *hw_entry, *sw_entry;
12574                 const enum pipe pipe = intel_crtc->pipe;
12575
12576                 if (!intel_crtc->active)
12577                         continue;
12578
12579                 /* planes */
12580                 for_each_plane(dev_priv, pipe, plane) {
12581                         hw_entry = &hw_ddb.plane[pipe][plane];
12582                         sw_entry = &sw_ddb->plane[pipe][plane];
12583
12584                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12585                                 continue;
12586
12587                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12588                                   "(expected (%u,%u), found (%u,%u))\n",
12589                                   pipe_name(pipe), plane + 1,
12590                                   sw_entry->start, sw_entry->end,
12591                                   hw_entry->start, hw_entry->end);
12592                 }
12593
12594                 /* cursor */
12595                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12596                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12597
12598                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12599                         continue;
12600
12601                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12602                           "(expected (%u,%u), found (%u,%u))\n",
12603                           pipe_name(pipe),
12604                           sw_entry->start, sw_entry->end,
12605                           hw_entry->start, hw_entry->end);
12606         }
12607 }
12608
12609 static void
12610 check_connector_state(struct drm_device *dev,
12611                       struct drm_atomic_state *old_state)
12612 {
12613         struct drm_connector_state *old_conn_state;
12614         struct drm_connector *connector;
12615         int i;
12616
12617         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12618                 struct drm_encoder *encoder = connector->encoder;
12619                 struct drm_connector_state *state = connector->state;
12620
12621                 /* This also checks the encoder/connector hw state with the
12622                  * ->get_hw_state callbacks. */
12623                 intel_connector_check_state(to_intel_connector(connector));
12624
12625                 I915_STATE_WARN(state->best_encoder != encoder,
12626                      "connector's atomic encoder doesn't match legacy encoder\n");
12627         }
12628 }
12629
12630 static void
12631 check_encoder_state(struct drm_device *dev)
12632 {
12633         struct intel_encoder *encoder;
12634         struct intel_connector *connector;
12635
12636         for_each_intel_encoder(dev, encoder) {
12637                 bool enabled = false;
12638                 enum pipe pipe;
12639
12640                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12641                               encoder->base.base.id,
12642                               encoder->base.name);
12643
12644                 for_each_intel_connector(dev, connector) {
12645                         if (connector->base.state->best_encoder != &encoder->base)
12646                                 continue;
12647                         enabled = true;
12648
12649                         I915_STATE_WARN(connector->base.state->crtc !=
12650                                         encoder->base.crtc,
12651                              "connector's crtc doesn't match encoder crtc\n");
12652                 }
12653
12654                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12655                      "encoder's enabled state mismatch "
12656                      "(expected %i, found %i)\n",
12657                      !!encoder->base.crtc, enabled);
12658
12659                 if (!encoder->base.crtc) {
12660                         bool active;
12661
12662                         active = encoder->get_hw_state(encoder, &pipe);
12663                         I915_STATE_WARN(active,
12664                              "encoder detached but still enabled on pipe %c.\n",
12665                              pipe_name(pipe));
12666                 }
12667         }
12668 }
12669
12670 static void
12671 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12672 {
12673         struct drm_i915_private *dev_priv = dev->dev_private;
12674         struct intel_encoder *encoder;
12675         struct drm_crtc_state *old_crtc_state;
12676         struct drm_crtc *crtc;
12677         int i;
12678
12679         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12680                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12681                 struct intel_crtc_state *pipe_config, *sw_config;
12682                 bool active;
12683
12684                 if (!needs_modeset(crtc->state) &&
12685                     !to_intel_crtc_state(crtc->state)->update_pipe)
12686                         continue;
12687
12688                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12689                 pipe_config = to_intel_crtc_state(old_crtc_state);
12690                 memset(pipe_config, 0, sizeof(*pipe_config));
12691                 pipe_config->base.crtc = crtc;
12692                 pipe_config->base.state = old_state;
12693
12694                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12695                               crtc->base.id);
12696
12697                 active = dev_priv->display.get_pipe_config(intel_crtc,
12698                                                            pipe_config);
12699
12700                 /* hw state is inconsistent with the pipe quirk */
12701                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12702                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12703                         active = crtc->state->active;
12704
12705                 I915_STATE_WARN(crtc->state->active != active,
12706                      "crtc active state doesn't match with hw state "
12707                      "(expected %i, found %i)\n", crtc->state->active, active);
12708
12709                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12710                      "transitional active state does not match atomic hw state "
12711                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12712
12713                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12714                         enum pipe pipe;
12715
12716                         active = encoder->get_hw_state(encoder, &pipe);
12717                         I915_STATE_WARN(active != crtc->state->active,
12718                                 "[ENCODER:%i] active %i with crtc active %i\n",
12719                                 encoder->base.base.id, active, crtc->state->active);
12720
12721                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12722                                         "Encoder connected to wrong pipe %c\n",
12723                                         pipe_name(pipe));
12724
12725                         if (active)
12726                                 encoder->get_config(encoder, pipe_config);
12727                 }
12728
12729                 if (!crtc->state->active)
12730                         continue;
12731
12732                 sw_config = to_intel_crtc_state(crtc->state);
12733                 if (!intel_pipe_config_compare(dev, sw_config,
12734                                                pipe_config, false)) {
12735                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12736                         intel_dump_pipe_config(intel_crtc, pipe_config,
12737                                                "[hw state]");
12738                         intel_dump_pipe_config(intel_crtc, sw_config,
12739                                                "[sw state]");
12740                 }
12741         }
12742 }
12743
12744 static void
12745 check_shared_dpll_state(struct drm_device *dev)
12746 {
12747         struct drm_i915_private *dev_priv = dev->dev_private;
12748         struct intel_crtc *crtc;
12749         struct intel_dpll_hw_state dpll_hw_state;
12750         int i;
12751
12752         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12753                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12754                 int enabled_crtcs = 0, active_crtcs = 0;
12755                 bool active;
12756
12757                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12758
12759                 DRM_DEBUG_KMS("%s\n", pll->name);
12760
12761                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12762
12763                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12764                      "more active pll users than references: %i vs %i\n",
12765                      pll->active, hweight32(pll->config.crtc_mask));
12766                 I915_STATE_WARN(pll->active && !pll->on,
12767                      "pll in active use but not on in sw tracking\n");
12768                 I915_STATE_WARN(pll->on && !pll->active,
12769                      "pll in on but not on in use in sw tracking\n");
12770                 I915_STATE_WARN(pll->on != active,
12771                      "pll on state mismatch (expected %i, found %i)\n",
12772                      pll->on, active);
12773
12774                 for_each_intel_crtc(dev, crtc) {
12775                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12776                                 enabled_crtcs++;
12777                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12778                                 active_crtcs++;
12779                 }
12780                 I915_STATE_WARN(pll->active != active_crtcs,
12781                      "pll active crtcs mismatch (expected %i, found %i)\n",
12782                      pll->active, active_crtcs);
12783                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12784                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12785                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12786
12787                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12788                                        sizeof(dpll_hw_state)),
12789                      "pll hw state mismatch\n");
12790         }
12791 }
12792
12793 static void
12794 intel_modeset_check_state(struct drm_device *dev,
12795                           struct drm_atomic_state *old_state)
12796 {
12797         check_wm_state(dev);
12798         check_connector_state(dev, old_state);
12799         check_encoder_state(dev);
12800         check_crtc_state(dev, old_state);
12801         check_shared_dpll_state(dev);
12802 }
12803
12804 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12805                                      int dotclock)
12806 {
12807         /*
12808          * FDI already provided one idea for the dotclock.
12809          * Yell if the encoder disagrees.
12810          */
12811         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12812              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12813              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12814 }
12815
12816 static void update_scanline_offset(struct intel_crtc *crtc)
12817 {
12818         struct drm_device *dev = crtc->base.dev;
12819
12820         /*
12821          * The scanline counter increments at the leading edge of hsync.
12822          *
12823          * On most platforms it starts counting from vtotal-1 on the
12824          * first active line. That means the scanline counter value is
12825          * always one less than what we would expect. Ie. just after
12826          * start of vblank, which also occurs at start of hsync (on the
12827          * last active line), the scanline counter will read vblank_start-1.
12828          *
12829          * On gen2 the scanline counter starts counting from 1 instead
12830          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12831          * to keep the value positive), instead of adding one.
12832          *
12833          * On HSW+ the behaviour of the scanline counter depends on the output
12834          * type. For DP ports it behaves like most other platforms, but on HDMI
12835          * there's an extra 1 line difference. So we need to add two instead of
12836          * one to the value.
12837          */
12838         if (IS_GEN2(dev)) {
12839                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12840                 int vtotal;
12841
12842                 vtotal = adjusted_mode->crtc_vtotal;
12843                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12844                         vtotal /= 2;
12845
12846                 crtc->scanline_offset = vtotal - 1;
12847         } else if (HAS_DDI(dev) &&
12848                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12849                 crtc->scanline_offset = 2;
12850         } else
12851                 crtc->scanline_offset = 1;
12852 }
12853
12854 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12855 {
12856         struct drm_device *dev = state->dev;
12857         struct drm_i915_private *dev_priv = to_i915(dev);
12858         struct intel_shared_dpll_config *shared_dpll = NULL;
12859         struct intel_crtc *intel_crtc;
12860         struct intel_crtc_state *intel_crtc_state;
12861         struct drm_crtc *crtc;
12862         struct drm_crtc_state *crtc_state;
12863         int i;
12864
12865         if (!dev_priv->display.crtc_compute_clock)
12866                 return;
12867
12868         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12869                 int dpll;
12870
12871                 intel_crtc = to_intel_crtc(crtc);
12872                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12873                 dpll = intel_crtc_state->shared_dpll;
12874
12875                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12876                         continue;
12877
12878                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12879
12880                 if (!shared_dpll)
12881                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12882
12883                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12884         }
12885 }
12886
12887 /*
12888  * This implements the workaround described in the "notes" section of the mode
12889  * set sequence documentation. When going from no pipes or single pipe to
12890  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12891  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12892  */
12893 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12894 {
12895         struct drm_crtc_state *crtc_state;
12896         struct intel_crtc *intel_crtc;
12897         struct drm_crtc *crtc;
12898         struct intel_crtc_state *first_crtc_state = NULL;
12899         struct intel_crtc_state *other_crtc_state = NULL;
12900         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12901         int i;
12902
12903         /* look at all crtc's that are going to be enabled in during modeset */
12904         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12905                 intel_crtc = to_intel_crtc(crtc);
12906
12907                 if (!crtc_state->active || !needs_modeset(crtc_state))
12908                         continue;
12909
12910                 if (first_crtc_state) {
12911                         other_crtc_state = to_intel_crtc_state(crtc_state);
12912                         break;
12913                 } else {
12914                         first_crtc_state = to_intel_crtc_state(crtc_state);
12915                         first_pipe = intel_crtc->pipe;
12916                 }
12917         }
12918
12919         /* No workaround needed? */
12920         if (!first_crtc_state)
12921                 return 0;
12922
12923         /* w/a possibly needed, check how many crtc's are already enabled. */
12924         for_each_intel_crtc(state->dev, intel_crtc) {
12925                 struct intel_crtc_state *pipe_config;
12926
12927                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12928                 if (IS_ERR(pipe_config))
12929                         return PTR_ERR(pipe_config);
12930
12931                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12932
12933                 if (!pipe_config->base.active ||
12934                     needs_modeset(&pipe_config->base))
12935                         continue;
12936
12937                 /* 2 or more enabled crtcs means no need for w/a */
12938                 if (enabled_pipe != INVALID_PIPE)
12939                         return 0;
12940
12941                 enabled_pipe = intel_crtc->pipe;
12942         }
12943
12944         if (enabled_pipe != INVALID_PIPE)
12945                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12946         else if (other_crtc_state)
12947                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12948
12949         return 0;
12950 }
12951
12952 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12953 {
12954         struct drm_crtc *crtc;
12955         struct drm_crtc_state *crtc_state;
12956         int ret = 0;
12957
12958         /* add all active pipes to the state */
12959         for_each_crtc(state->dev, crtc) {
12960                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12961                 if (IS_ERR(crtc_state))
12962                         return PTR_ERR(crtc_state);
12963
12964                 if (!crtc_state->active || needs_modeset(crtc_state))
12965                         continue;
12966
12967                 crtc_state->mode_changed = true;
12968
12969                 ret = drm_atomic_add_affected_connectors(state, crtc);
12970                 if (ret)
12971                         break;
12972
12973                 ret = drm_atomic_add_affected_planes(state, crtc);
12974                 if (ret)
12975                         break;
12976         }
12977
12978         return ret;
12979 }
12980
12981 static int intel_modeset_checks(struct drm_atomic_state *state)
12982 {
12983         struct drm_device *dev = state->dev;
12984         struct drm_i915_private *dev_priv = dev->dev_private;
12985         int ret;
12986
12987         if (!check_digital_port_conflicts(state)) {
12988                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12989                 return -EINVAL;
12990         }
12991
12992         /*
12993          * See if the config requires any additional preparation, e.g.
12994          * to adjust global state with pipes off.  We need to do this
12995          * here so we can get the modeset_pipe updated config for the new
12996          * mode set on this crtc.  For other crtcs we need to use the
12997          * adjusted_mode bits in the crtc directly.
12998          */
12999         if (dev_priv->display.modeset_calc_cdclk) {
13000                 unsigned int cdclk;
13001
13002                 ret = dev_priv->display.modeset_calc_cdclk(state);
13003
13004                 cdclk = to_intel_atomic_state(state)->cdclk;
13005                 if (!ret && cdclk != dev_priv->cdclk_freq)
13006                         ret = intel_modeset_all_pipes(state);
13007
13008                 if (ret < 0)
13009                         return ret;
13010         } else
13011                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13012
13013         intel_modeset_clear_plls(state);
13014
13015         if (IS_HASWELL(dev))
13016                 return haswell_mode_set_planes_workaround(state);
13017
13018         return 0;
13019 }
13020
13021 /**
13022  * intel_atomic_check - validate state object
13023  * @dev: drm device
13024  * @state: state to validate
13025  */
13026 static int intel_atomic_check(struct drm_device *dev,
13027                               struct drm_atomic_state *state)
13028 {
13029         struct drm_crtc *crtc;
13030         struct drm_crtc_state *crtc_state;
13031         int ret, i;
13032         bool any_ms = false;
13033
13034         ret = drm_atomic_helper_check_modeset(dev, state);
13035         if (ret)
13036                 return ret;
13037
13038         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13039                 struct intel_crtc_state *pipe_config =
13040                         to_intel_crtc_state(crtc_state);
13041
13042                 /* Catch I915_MODE_FLAG_INHERITED */
13043                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13044                         crtc_state->mode_changed = true;
13045
13046                 if (!crtc_state->enable) {
13047                         if (needs_modeset(crtc_state))
13048                                 any_ms = true;
13049                         continue;
13050                 }
13051
13052                 if (!needs_modeset(crtc_state))
13053                         continue;
13054
13055                 /* FIXME: For only active_changed we shouldn't need to do any
13056                  * state recomputation at all. */
13057
13058                 ret = drm_atomic_add_affected_connectors(state, crtc);
13059                 if (ret)
13060                         return ret;
13061
13062                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13063                 if (ret)
13064                         return ret;
13065
13066                 if (intel_pipe_config_compare(state->dev,
13067                                         to_intel_crtc_state(crtc->state),
13068                                         pipe_config, true)) {
13069                         crtc_state->mode_changed = false;
13070                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13071                 }
13072
13073                 if (needs_modeset(crtc_state)) {
13074                         any_ms = true;
13075
13076                         ret = drm_atomic_add_affected_planes(state, crtc);
13077                         if (ret)
13078                                 return ret;
13079                 }
13080
13081                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13082                                        needs_modeset(crtc_state) ?
13083                                        "[modeset]" : "[fastset]");
13084         }
13085
13086         if (any_ms) {
13087                 ret = intel_modeset_checks(state);
13088
13089                 if (ret)
13090                         return ret;
13091         } else
13092                 to_intel_atomic_state(state)->cdclk =
13093                         to_i915(state->dev)->cdclk_freq;
13094
13095         return drm_atomic_helper_check_planes(state->dev, state);
13096 }
13097
13098 /**
13099  * intel_atomic_commit - commit validated state object
13100  * @dev: DRM device
13101  * @state: the top-level driver state object
13102  * @async: asynchronous commit
13103  *
13104  * This function commits a top-level state object that has been validated
13105  * with drm_atomic_helper_check().
13106  *
13107  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13108  * we can only handle plane-related operations and do not yet support
13109  * asynchronous commit.
13110  *
13111  * RETURNS
13112  * Zero for success or -errno.
13113  */
13114 static int intel_atomic_commit(struct drm_device *dev,
13115                                struct drm_atomic_state *state,
13116                                bool async)
13117 {
13118         struct drm_i915_private *dev_priv = dev->dev_private;
13119         struct drm_crtc *crtc;
13120         struct drm_crtc_state *crtc_state;
13121         int ret = 0;
13122         int i;
13123         bool any_ms = false;
13124
13125         if (async) {
13126                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13127                 return -EINVAL;
13128         }
13129
13130         ret = drm_atomic_helper_prepare_planes(dev, state);
13131         if (ret)
13132                 return ret;
13133
13134         drm_atomic_helper_swap_state(dev, state);
13135
13136         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13137                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13138
13139                 if (!needs_modeset(crtc->state))
13140                         continue;
13141
13142                 any_ms = true;
13143                 intel_pre_plane_update(intel_crtc);
13144
13145                 if (crtc_state->active) {
13146                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13147                         dev_priv->display.crtc_disable(crtc);
13148                         intel_crtc->active = false;
13149                         intel_disable_shared_dpll(intel_crtc);
13150                 }
13151         }
13152
13153         /* Only after disabling all output pipelines that will be changed can we
13154          * update the the output configuration. */
13155         intel_modeset_update_crtc_state(state);
13156
13157         if (any_ms) {
13158                 intel_shared_dpll_commit(state);
13159
13160                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13161                 modeset_update_crtc_power_domains(state);
13162         }
13163
13164         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13165         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13166                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13167                 bool modeset = needs_modeset(crtc->state);
13168                 bool update_pipe = !modeset &&
13169                         to_intel_crtc_state(crtc->state)->update_pipe;
13170                 unsigned long put_domains = 0;
13171
13172                 if (modeset && crtc->state->active) {
13173                         update_scanline_offset(to_intel_crtc(crtc));
13174                         dev_priv->display.crtc_enable(crtc);
13175                 }
13176
13177                 if (update_pipe) {
13178                         put_domains = modeset_get_crtc_power_domains(crtc);
13179
13180                         /* make sure intel_modeset_check_state runs */
13181                         any_ms = true;
13182                 }
13183
13184                 if (!modeset)
13185                         intel_pre_plane_update(intel_crtc);
13186
13187                 if (crtc->state->active &&
13188                     (crtc->state->planes_changed || update_pipe))
13189                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13190
13191                 if (put_domains)
13192                         modeset_put_power_domains(dev_priv, put_domains);
13193
13194                 intel_post_plane_update(intel_crtc);
13195         }
13196
13197         /* FIXME: add subpixel order */
13198
13199         drm_atomic_helper_wait_for_vblanks(dev, state);
13200         drm_atomic_helper_cleanup_planes(dev, state);
13201
13202         if (any_ms)
13203                 intel_modeset_check_state(dev, state);
13204
13205         drm_atomic_state_free(state);
13206
13207         return 0;
13208 }
13209
13210 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13211 {
13212         struct drm_device *dev = crtc->dev;
13213         struct drm_atomic_state *state;
13214         struct drm_crtc_state *crtc_state;
13215         int ret;
13216
13217         state = drm_atomic_state_alloc(dev);
13218         if (!state) {
13219                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13220                               crtc->base.id);
13221                 return;
13222         }
13223
13224         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13225
13226 retry:
13227         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13228         ret = PTR_ERR_OR_ZERO(crtc_state);
13229         if (!ret) {
13230                 if (!crtc_state->active)
13231                         goto out;
13232
13233                 crtc_state->mode_changed = true;
13234                 ret = drm_atomic_commit(state);
13235         }
13236
13237         if (ret == -EDEADLK) {
13238                 drm_atomic_state_clear(state);
13239                 drm_modeset_backoff(state->acquire_ctx);
13240                 goto retry;
13241         }
13242
13243         if (ret)
13244 out:
13245                 drm_atomic_state_free(state);
13246 }
13247
13248 #undef for_each_intel_crtc_masked
13249
13250 static const struct drm_crtc_funcs intel_crtc_funcs = {
13251         .gamma_set = intel_crtc_gamma_set,
13252         .set_config = drm_atomic_helper_set_config,
13253         .destroy = intel_crtc_destroy,
13254         .page_flip = intel_crtc_page_flip,
13255         .atomic_duplicate_state = intel_crtc_duplicate_state,
13256         .atomic_destroy_state = intel_crtc_destroy_state,
13257 };
13258
13259 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13260                                       struct intel_shared_dpll *pll,
13261                                       struct intel_dpll_hw_state *hw_state)
13262 {
13263         uint32_t val;
13264
13265         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13266                 return false;
13267
13268         val = I915_READ(PCH_DPLL(pll->id));
13269         hw_state->dpll = val;
13270         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13271         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13272
13273         return val & DPLL_VCO_ENABLE;
13274 }
13275
13276 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13277                                   struct intel_shared_dpll *pll)
13278 {
13279         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13280         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13281 }
13282
13283 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13284                                 struct intel_shared_dpll *pll)
13285 {
13286         /* PCH refclock must be enabled first */
13287         ibx_assert_pch_refclk_enabled(dev_priv);
13288
13289         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13290
13291         /* Wait for the clocks to stabilize. */
13292         POSTING_READ(PCH_DPLL(pll->id));
13293         udelay(150);
13294
13295         /* The pixel multiplier can only be updated once the
13296          * DPLL is enabled and the clocks are stable.
13297          *
13298          * So write it again.
13299          */
13300         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13301         POSTING_READ(PCH_DPLL(pll->id));
13302         udelay(200);
13303 }
13304
13305 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13306                                  struct intel_shared_dpll *pll)
13307 {
13308         struct drm_device *dev = dev_priv->dev;
13309         struct intel_crtc *crtc;
13310
13311         /* Make sure no transcoder isn't still depending on us. */
13312         for_each_intel_crtc(dev, crtc) {
13313                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13314                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13315         }
13316
13317         I915_WRITE(PCH_DPLL(pll->id), 0);
13318         POSTING_READ(PCH_DPLL(pll->id));
13319         udelay(200);
13320 }
13321
13322 static char *ibx_pch_dpll_names[] = {
13323         "PCH DPLL A",
13324         "PCH DPLL B",
13325 };
13326
13327 static void ibx_pch_dpll_init(struct drm_device *dev)
13328 {
13329         struct drm_i915_private *dev_priv = dev->dev_private;
13330         int i;
13331
13332         dev_priv->num_shared_dpll = 2;
13333
13334         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13335                 dev_priv->shared_dplls[i].id = i;
13336                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13337                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13338                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13339                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13340                 dev_priv->shared_dplls[i].get_hw_state =
13341                         ibx_pch_dpll_get_hw_state;
13342         }
13343 }
13344
13345 static void intel_shared_dpll_init(struct drm_device *dev)
13346 {
13347         struct drm_i915_private *dev_priv = dev->dev_private;
13348
13349         if (HAS_DDI(dev))
13350                 intel_ddi_pll_init(dev);
13351         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13352                 ibx_pch_dpll_init(dev);
13353         else
13354                 dev_priv->num_shared_dpll = 0;
13355
13356         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13357 }
13358
13359 /**
13360  * intel_prepare_plane_fb - Prepare fb for usage on plane
13361  * @plane: drm plane to prepare for
13362  * @fb: framebuffer to prepare for presentation
13363  *
13364  * Prepares a framebuffer for usage on a display plane.  Generally this
13365  * involves pinning the underlying object and updating the frontbuffer tracking
13366  * bits.  Some older platforms need special physical address handling for
13367  * cursor planes.
13368  *
13369  * Returns 0 on success, negative error code on failure.
13370  */
13371 int
13372 intel_prepare_plane_fb(struct drm_plane *plane,
13373                        const struct drm_plane_state *new_state)
13374 {
13375         struct drm_device *dev = plane->dev;
13376         struct drm_framebuffer *fb = new_state->fb;
13377         struct intel_plane *intel_plane = to_intel_plane(plane);
13378         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13379         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13380         int ret = 0;
13381
13382         if (!obj && !old_obj)
13383                 return 0;
13384
13385         ret = i915_mutex_lock_interruptible(dev);
13386         if (ret)
13387                 return ret;
13388
13389         if (!obj) {
13390                 ret = 0;
13391         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13392             INTEL_INFO(dev)->cursor_needs_physical) {
13393                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13394                 ret = i915_gem_object_attach_phys(obj, align);
13395                 if (ret)
13396                         DRM_DEBUG_KMS("failed to attach phys object\n");
13397         } else {
13398                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13399         }
13400
13401         if (ret == 0)
13402                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13403
13404         mutex_unlock(&dev->struct_mutex);
13405
13406         return ret;
13407 }
13408
13409 /**
13410  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13411  * @plane: drm plane to clean up for
13412  * @fb: old framebuffer that was on plane
13413  *
13414  * Cleans up a framebuffer that has just been removed from a plane.
13415  */
13416 void
13417 intel_cleanup_plane_fb(struct drm_plane *plane,
13418                        const struct drm_plane_state *old_state)
13419 {
13420         struct drm_device *dev = plane->dev;
13421         struct intel_plane *intel_plane = to_intel_plane(plane);
13422         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13423         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13424
13425         if (!obj && !old_obj)
13426                 return;
13427
13428         mutex_lock(&dev->struct_mutex);
13429         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13430             !INTEL_INFO(dev)->cursor_needs_physical))
13431                 intel_unpin_fb_obj(old_state->fb, old_state);
13432
13433         /* prepare_fb aborted? */
13434         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13435             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13436                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13437         mutex_unlock(&dev->struct_mutex);
13438 }
13439
13440 int
13441 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13442 {
13443         int max_scale;
13444         struct drm_device *dev;
13445         struct drm_i915_private *dev_priv;
13446         int crtc_clock, cdclk;
13447
13448         if (!intel_crtc || !crtc_state)
13449                 return DRM_PLANE_HELPER_NO_SCALING;
13450
13451         dev = intel_crtc->base.dev;
13452         dev_priv = dev->dev_private;
13453         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13454         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13455
13456         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13457                 return DRM_PLANE_HELPER_NO_SCALING;
13458
13459         /*
13460          * skl max scale is lower of:
13461          *    close to 3 but not 3, -1 is for that purpose
13462          *            or
13463          *    cdclk/crtc_clock
13464          */
13465         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13466
13467         return max_scale;
13468 }
13469
13470 static int
13471 intel_check_primary_plane(struct drm_plane *plane,
13472                           struct intel_crtc_state *crtc_state,
13473                           struct intel_plane_state *state)
13474 {
13475         struct drm_crtc *crtc = state->base.crtc;
13476         struct drm_framebuffer *fb = state->base.fb;
13477         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13478         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13479         bool can_position = false;
13480
13481         /* use scaler when colorkey is not required */
13482         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13483             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13484                 min_scale = 1;
13485                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13486                 can_position = true;
13487         }
13488
13489         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13490                                              &state->dst, &state->clip,
13491                                              min_scale, max_scale,
13492                                              can_position, true,
13493                                              &state->visible);
13494 }
13495
13496 static void
13497 intel_commit_primary_plane(struct drm_plane *plane,
13498                            struct intel_plane_state *state)
13499 {
13500         struct drm_crtc *crtc = state->base.crtc;
13501         struct drm_framebuffer *fb = state->base.fb;
13502         struct drm_device *dev = plane->dev;
13503         struct drm_i915_private *dev_priv = dev->dev_private;
13504
13505         crtc = crtc ? crtc : plane->crtc;
13506
13507         dev_priv->display.update_primary_plane(crtc, fb,
13508                                                state->src.x1 >> 16,
13509                                                state->src.y1 >> 16);
13510 }
13511
13512 static void
13513 intel_disable_primary_plane(struct drm_plane *plane,
13514                             struct drm_crtc *crtc)
13515 {
13516         struct drm_device *dev = plane->dev;
13517         struct drm_i915_private *dev_priv = dev->dev_private;
13518
13519         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13520 }
13521
13522 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13523                                     struct drm_crtc_state *old_crtc_state)
13524 {
13525         struct drm_device *dev = crtc->dev;
13526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13527         struct intel_crtc_state *old_intel_state =
13528                 to_intel_crtc_state(old_crtc_state);
13529         bool modeset = needs_modeset(crtc->state);
13530
13531         if (intel_crtc->atomic.update_wm_pre)
13532                 intel_update_watermarks(crtc);
13533
13534         /* Perform vblank evasion around commit operation */
13535         intel_pipe_update_start(intel_crtc);
13536
13537         if (modeset)
13538                 return;
13539
13540         if (to_intel_crtc_state(crtc->state)->update_pipe)
13541                 intel_update_pipe_config(intel_crtc, old_intel_state);
13542         else if (INTEL_INFO(dev)->gen >= 9)
13543                 skl_detach_scalers(intel_crtc);
13544 }
13545
13546 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13547                                      struct drm_crtc_state *old_crtc_state)
13548 {
13549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13550
13551         intel_pipe_update_end(intel_crtc);
13552 }
13553
13554 /**
13555  * intel_plane_destroy - destroy a plane
13556  * @plane: plane to destroy
13557  *
13558  * Common destruction function for all types of planes (primary, cursor,
13559  * sprite).
13560  */
13561 void intel_plane_destroy(struct drm_plane *plane)
13562 {
13563         struct intel_plane *intel_plane = to_intel_plane(plane);
13564         drm_plane_cleanup(plane);
13565         kfree(intel_plane);
13566 }
13567
13568 const struct drm_plane_funcs intel_plane_funcs = {
13569         .update_plane = drm_atomic_helper_update_plane,
13570         .disable_plane = drm_atomic_helper_disable_plane,
13571         .destroy = intel_plane_destroy,
13572         .set_property = drm_atomic_helper_plane_set_property,
13573         .atomic_get_property = intel_plane_atomic_get_property,
13574         .atomic_set_property = intel_plane_atomic_set_property,
13575         .atomic_duplicate_state = intel_plane_duplicate_state,
13576         .atomic_destroy_state = intel_plane_destroy_state,
13577
13578 };
13579
13580 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13581                                                     int pipe)
13582 {
13583         struct intel_plane *primary;
13584         struct intel_plane_state *state;
13585         const uint32_t *intel_primary_formats;
13586         unsigned int num_formats;
13587
13588         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13589         if (primary == NULL)
13590                 return NULL;
13591
13592         state = intel_create_plane_state(&primary->base);
13593         if (!state) {
13594                 kfree(primary);
13595                 return NULL;
13596         }
13597         primary->base.state = &state->base;
13598
13599         primary->can_scale = false;
13600         primary->max_downscale = 1;
13601         if (INTEL_INFO(dev)->gen >= 9) {
13602                 primary->can_scale = true;
13603                 state->scaler_id = -1;
13604         }
13605         primary->pipe = pipe;
13606         primary->plane = pipe;
13607         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13608         primary->check_plane = intel_check_primary_plane;
13609         primary->commit_plane = intel_commit_primary_plane;
13610         primary->disable_plane = intel_disable_primary_plane;
13611         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13612                 primary->plane = !pipe;
13613
13614         if (INTEL_INFO(dev)->gen >= 9) {
13615                 intel_primary_formats = skl_primary_formats;
13616                 num_formats = ARRAY_SIZE(skl_primary_formats);
13617         } else if (INTEL_INFO(dev)->gen >= 4) {
13618                 intel_primary_formats = i965_primary_formats;
13619                 num_formats = ARRAY_SIZE(i965_primary_formats);
13620         } else {
13621                 intel_primary_formats = i8xx_primary_formats;
13622                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13623         }
13624
13625         drm_universal_plane_init(dev, &primary->base, 0,
13626                                  &intel_plane_funcs,
13627                                  intel_primary_formats, num_formats,
13628                                  DRM_PLANE_TYPE_PRIMARY);
13629
13630         if (INTEL_INFO(dev)->gen >= 4)
13631                 intel_create_rotation_property(dev, primary);
13632
13633         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13634
13635         return &primary->base;
13636 }
13637
13638 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13639 {
13640         if (!dev->mode_config.rotation_property) {
13641                 unsigned long flags = BIT(DRM_ROTATE_0) |
13642                         BIT(DRM_ROTATE_180);
13643
13644                 if (INTEL_INFO(dev)->gen >= 9)
13645                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13646
13647                 dev->mode_config.rotation_property =
13648                         drm_mode_create_rotation_property(dev, flags);
13649         }
13650         if (dev->mode_config.rotation_property)
13651                 drm_object_attach_property(&plane->base.base,
13652                                 dev->mode_config.rotation_property,
13653                                 plane->base.state->rotation);
13654 }
13655
13656 static int
13657 intel_check_cursor_plane(struct drm_plane *plane,
13658                          struct intel_crtc_state *crtc_state,
13659                          struct intel_plane_state *state)
13660 {
13661         struct drm_crtc *crtc = crtc_state->base.crtc;
13662         struct drm_framebuffer *fb = state->base.fb;
13663         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13664         unsigned stride;
13665         int ret;
13666
13667         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13668                                             &state->dst, &state->clip,
13669                                             DRM_PLANE_HELPER_NO_SCALING,
13670                                             DRM_PLANE_HELPER_NO_SCALING,
13671                                             true, true, &state->visible);
13672         if (ret)
13673                 return ret;
13674
13675         /* if we want to turn off the cursor ignore width and height */
13676         if (!obj)
13677                 return 0;
13678
13679         /* Check for which cursor types we support */
13680         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13681                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13682                           state->base.crtc_w, state->base.crtc_h);
13683                 return -EINVAL;
13684         }
13685
13686         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13687         if (obj->base.size < stride * state->base.crtc_h) {
13688                 DRM_DEBUG_KMS("buffer is too small\n");
13689                 return -ENOMEM;
13690         }
13691
13692         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13693                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13694                 return -EINVAL;
13695         }
13696
13697         return 0;
13698 }
13699
13700 static void
13701 intel_disable_cursor_plane(struct drm_plane *plane,
13702                            struct drm_crtc *crtc)
13703 {
13704         intel_crtc_update_cursor(crtc, false);
13705 }
13706
13707 static void
13708 intel_commit_cursor_plane(struct drm_plane *plane,
13709                           struct intel_plane_state *state)
13710 {
13711         struct drm_crtc *crtc = state->base.crtc;
13712         struct drm_device *dev = plane->dev;
13713         struct intel_crtc *intel_crtc;
13714         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13715         uint32_t addr;
13716
13717         crtc = crtc ? crtc : plane->crtc;
13718         intel_crtc = to_intel_crtc(crtc);
13719
13720         if (intel_crtc->cursor_bo == obj)
13721                 goto update;
13722
13723         if (!obj)
13724                 addr = 0;
13725         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13726                 addr = i915_gem_obj_ggtt_offset(obj);
13727         else
13728                 addr = obj->phys_handle->busaddr;
13729
13730         intel_crtc->cursor_addr = addr;
13731         intel_crtc->cursor_bo = obj;
13732
13733 update:
13734         intel_crtc_update_cursor(crtc, state->visible);
13735 }
13736
13737 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13738                                                    int pipe)
13739 {
13740         struct intel_plane *cursor;
13741         struct intel_plane_state *state;
13742
13743         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13744         if (cursor == NULL)
13745                 return NULL;
13746
13747         state = intel_create_plane_state(&cursor->base);
13748         if (!state) {
13749                 kfree(cursor);
13750                 return NULL;
13751         }
13752         cursor->base.state = &state->base;
13753
13754         cursor->can_scale = false;
13755         cursor->max_downscale = 1;
13756         cursor->pipe = pipe;
13757         cursor->plane = pipe;
13758         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13759         cursor->check_plane = intel_check_cursor_plane;
13760         cursor->commit_plane = intel_commit_cursor_plane;
13761         cursor->disable_plane = intel_disable_cursor_plane;
13762
13763         drm_universal_plane_init(dev, &cursor->base, 0,
13764                                  &intel_plane_funcs,
13765                                  intel_cursor_formats,
13766                                  ARRAY_SIZE(intel_cursor_formats),
13767                                  DRM_PLANE_TYPE_CURSOR);
13768
13769         if (INTEL_INFO(dev)->gen >= 4) {
13770                 if (!dev->mode_config.rotation_property)
13771                         dev->mode_config.rotation_property =
13772                                 drm_mode_create_rotation_property(dev,
13773                                                         BIT(DRM_ROTATE_0) |
13774                                                         BIT(DRM_ROTATE_180));
13775                 if (dev->mode_config.rotation_property)
13776                         drm_object_attach_property(&cursor->base.base,
13777                                 dev->mode_config.rotation_property,
13778                                 state->base.rotation);
13779         }
13780
13781         if (INTEL_INFO(dev)->gen >=9)
13782                 state->scaler_id = -1;
13783
13784         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13785
13786         return &cursor->base;
13787 }
13788
13789 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13790         struct intel_crtc_state *crtc_state)
13791 {
13792         int i;
13793         struct intel_scaler *intel_scaler;
13794         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13795
13796         for (i = 0; i < intel_crtc->num_scalers; i++) {
13797                 intel_scaler = &scaler_state->scalers[i];
13798                 intel_scaler->in_use = 0;
13799                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13800         }
13801
13802         scaler_state->scaler_id = -1;
13803 }
13804
13805 static void intel_crtc_init(struct drm_device *dev, int pipe)
13806 {
13807         struct drm_i915_private *dev_priv = dev->dev_private;
13808         struct intel_crtc *intel_crtc;
13809         struct intel_crtc_state *crtc_state = NULL;
13810         struct drm_plane *primary = NULL;
13811         struct drm_plane *cursor = NULL;
13812         int i, ret;
13813
13814         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13815         if (intel_crtc == NULL)
13816                 return;
13817
13818         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13819         if (!crtc_state)
13820                 goto fail;
13821         intel_crtc->config = crtc_state;
13822         intel_crtc->base.state = &crtc_state->base;
13823         crtc_state->base.crtc = &intel_crtc->base;
13824
13825         /* initialize shared scalers */
13826         if (INTEL_INFO(dev)->gen >= 9) {
13827                 if (pipe == PIPE_C)
13828                         intel_crtc->num_scalers = 1;
13829                 else
13830                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13831
13832                 skl_init_scalers(dev, intel_crtc, crtc_state);
13833         }
13834
13835         primary = intel_primary_plane_create(dev, pipe);
13836         if (!primary)
13837                 goto fail;
13838
13839         cursor = intel_cursor_plane_create(dev, pipe);
13840         if (!cursor)
13841                 goto fail;
13842
13843         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13844                                         cursor, &intel_crtc_funcs);
13845         if (ret)
13846                 goto fail;
13847
13848         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13849         for (i = 0; i < 256; i++) {
13850                 intel_crtc->lut_r[i] = i;
13851                 intel_crtc->lut_g[i] = i;
13852                 intel_crtc->lut_b[i] = i;
13853         }
13854
13855         /*
13856          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13857          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13858          */
13859         intel_crtc->pipe = pipe;
13860         intel_crtc->plane = pipe;
13861         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13862                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13863                 intel_crtc->plane = !pipe;
13864         }
13865
13866         intel_crtc->cursor_base = ~0;
13867         intel_crtc->cursor_cntl = ~0;
13868         intel_crtc->cursor_size = ~0;
13869
13870         intel_crtc->wm.cxsr_allowed = true;
13871
13872         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13873                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13874         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13875         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13876
13877         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13878
13879         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13880         return;
13881
13882 fail:
13883         if (primary)
13884                 drm_plane_cleanup(primary);
13885         if (cursor)
13886                 drm_plane_cleanup(cursor);
13887         kfree(crtc_state);
13888         kfree(intel_crtc);
13889 }
13890
13891 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13892 {
13893         struct drm_encoder *encoder = connector->base.encoder;
13894         struct drm_device *dev = connector->base.dev;
13895
13896         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13897
13898         if (!encoder || WARN_ON(!encoder->crtc))
13899                 return INVALID_PIPE;
13900
13901         return to_intel_crtc(encoder->crtc)->pipe;
13902 }
13903
13904 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13905                                 struct drm_file *file)
13906 {
13907         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13908         struct drm_crtc *drmmode_crtc;
13909         struct intel_crtc *crtc;
13910
13911         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13912
13913         if (!drmmode_crtc) {
13914                 DRM_ERROR("no such CRTC id\n");
13915                 return -ENOENT;
13916         }
13917
13918         crtc = to_intel_crtc(drmmode_crtc);
13919         pipe_from_crtc_id->pipe = crtc->pipe;
13920
13921         return 0;
13922 }
13923
13924 static int intel_encoder_clones(struct intel_encoder *encoder)
13925 {
13926         struct drm_device *dev = encoder->base.dev;
13927         struct intel_encoder *source_encoder;
13928         int index_mask = 0;
13929         int entry = 0;
13930
13931         for_each_intel_encoder(dev, source_encoder) {
13932                 if (encoders_cloneable(encoder, source_encoder))
13933                         index_mask |= (1 << entry);
13934
13935                 entry++;
13936         }
13937
13938         return index_mask;
13939 }
13940
13941 static bool has_edp_a(struct drm_device *dev)
13942 {
13943         struct drm_i915_private *dev_priv = dev->dev_private;
13944
13945         if (!IS_MOBILE(dev))
13946                 return false;
13947
13948         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13949                 return false;
13950
13951         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13952                 return false;
13953
13954         return true;
13955 }
13956
13957 static bool intel_crt_present(struct drm_device *dev)
13958 {
13959         struct drm_i915_private *dev_priv = dev->dev_private;
13960
13961         if (INTEL_INFO(dev)->gen >= 9)
13962                 return false;
13963
13964         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13965                 return false;
13966
13967         if (IS_CHERRYVIEW(dev))
13968                 return false;
13969
13970         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13971                 return false;
13972
13973         return true;
13974 }
13975
13976 static void intel_setup_outputs(struct drm_device *dev)
13977 {
13978         struct drm_i915_private *dev_priv = dev->dev_private;
13979         struct intel_encoder *encoder;
13980         bool dpd_is_edp = false;
13981
13982         intel_lvds_init(dev);
13983
13984         if (intel_crt_present(dev))
13985                 intel_crt_init(dev);
13986
13987         if (IS_BROXTON(dev)) {
13988                 /*
13989                  * FIXME: Broxton doesn't support port detection via the
13990                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13991                  * detect the ports.
13992                  */
13993                 intel_ddi_init(dev, PORT_A);
13994                 intel_ddi_init(dev, PORT_B);
13995                 intel_ddi_init(dev, PORT_C);
13996         } else if (HAS_DDI(dev)) {
13997                 int found;
13998
13999                 /*
14000                  * Haswell uses DDI functions to detect digital outputs.
14001                  * On SKL pre-D0 the strap isn't connected, so we assume
14002                  * it's there.
14003                  */
14004                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14005                 /* WaIgnoreDDIAStrap: skl */
14006                 if (found || IS_SKYLAKE(dev))
14007                         intel_ddi_init(dev, PORT_A);
14008
14009                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14010                  * register */
14011                 found = I915_READ(SFUSE_STRAP);
14012
14013                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14014                         intel_ddi_init(dev, PORT_B);
14015                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14016                         intel_ddi_init(dev, PORT_C);
14017                 if (found & SFUSE_STRAP_DDID_DETECTED)
14018                         intel_ddi_init(dev, PORT_D);
14019                 /*
14020                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14021                  */
14022                 if (IS_SKYLAKE(dev) &&
14023                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14024                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14025                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14026                         intel_ddi_init(dev, PORT_E);
14027
14028         } else if (HAS_PCH_SPLIT(dev)) {
14029                 int found;
14030                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14031
14032                 if (has_edp_a(dev))
14033                         intel_dp_init(dev, DP_A, PORT_A);
14034
14035                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14036                         /* PCH SDVOB multiplex with HDMIB */
14037                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14038                         if (!found)
14039                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14040                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14041                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14042                 }
14043
14044                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14045                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14046
14047                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14048                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14049
14050                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14051                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14052
14053                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14054                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14055         } else if (IS_VALLEYVIEW(dev)) {
14056                 /*
14057                  * The DP_DETECTED bit is the latched state of the DDC
14058                  * SDA pin at boot. However since eDP doesn't require DDC
14059                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14060                  * eDP ports may have been muxed to an alternate function.
14061                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14062                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14063                  * detect eDP ports.
14064                  */
14065                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14066                     !intel_dp_is_edp(dev, PORT_B))
14067                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14068                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14069                     intel_dp_is_edp(dev, PORT_B))
14070                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14071
14072                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14073                     !intel_dp_is_edp(dev, PORT_C))
14074                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14075                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14076                     intel_dp_is_edp(dev, PORT_C))
14077                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14078
14079                 if (IS_CHERRYVIEW(dev)) {
14080                         /* eDP not supported on port D, so don't check VBT */
14081                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14082                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14083                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14084                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14085                 }
14086
14087                 intel_dsi_init(dev);
14088         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14089                 bool found = false;
14090
14091                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14092                         DRM_DEBUG_KMS("probing SDVOB\n");
14093                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14094                         if (!found && IS_G4X(dev)) {
14095                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14096                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14097                         }
14098
14099                         if (!found && IS_G4X(dev))
14100                                 intel_dp_init(dev, DP_B, PORT_B);
14101                 }
14102
14103                 /* Before G4X SDVOC doesn't have its own detect register */
14104
14105                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14106                         DRM_DEBUG_KMS("probing SDVOC\n");
14107                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14108                 }
14109
14110                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14111
14112                         if (IS_G4X(dev)) {
14113                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14114                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14115                         }
14116                         if (IS_G4X(dev))
14117                                 intel_dp_init(dev, DP_C, PORT_C);
14118                 }
14119
14120                 if (IS_G4X(dev) &&
14121                     (I915_READ(DP_D) & DP_DETECTED))
14122                         intel_dp_init(dev, DP_D, PORT_D);
14123         } else if (IS_GEN2(dev))
14124                 intel_dvo_init(dev);
14125
14126         if (SUPPORTS_TV(dev))
14127                 intel_tv_init(dev);
14128
14129         intel_psr_init(dev);
14130
14131         for_each_intel_encoder(dev, encoder) {
14132                 encoder->base.possible_crtcs = encoder->crtc_mask;
14133                 encoder->base.possible_clones =
14134                         intel_encoder_clones(encoder);
14135         }
14136
14137         intel_init_pch_refclk(dev);
14138
14139         drm_helper_move_panel_connectors_to_head(dev);
14140 }
14141
14142 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14143 {
14144         struct drm_device *dev = fb->dev;
14145         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14146
14147         drm_framebuffer_cleanup(fb);
14148         mutex_lock(&dev->struct_mutex);
14149         WARN_ON(!intel_fb->obj->framebuffer_references--);
14150         drm_gem_object_unreference(&intel_fb->obj->base);
14151         mutex_unlock(&dev->struct_mutex);
14152         kfree(intel_fb);
14153 }
14154
14155 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14156                                                 struct drm_file *file,
14157                                                 unsigned int *handle)
14158 {
14159         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14160         struct drm_i915_gem_object *obj = intel_fb->obj;
14161
14162         return drm_gem_handle_create(file, &obj->base, handle);
14163 }
14164
14165 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14166                                         struct drm_file *file,
14167                                         unsigned flags, unsigned color,
14168                                         struct drm_clip_rect *clips,
14169                                         unsigned num_clips)
14170 {
14171         struct drm_device *dev = fb->dev;
14172         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14173         struct drm_i915_gem_object *obj = intel_fb->obj;
14174
14175         mutex_lock(&dev->struct_mutex);
14176         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14177         mutex_unlock(&dev->struct_mutex);
14178
14179         return 0;
14180 }
14181
14182 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14183         .destroy = intel_user_framebuffer_destroy,
14184         .create_handle = intel_user_framebuffer_create_handle,
14185         .dirty = intel_user_framebuffer_dirty,
14186 };
14187
14188 static
14189 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14190                          uint32_t pixel_format)
14191 {
14192         u32 gen = INTEL_INFO(dev)->gen;
14193
14194         if (gen >= 9) {
14195                 /* "The stride in bytes must not exceed the of the size of 8K
14196                  *  pixels and 32K bytes."
14197                  */
14198                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14199         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14200                 return 32*1024;
14201         } else if (gen >= 4) {
14202                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14203                         return 16*1024;
14204                 else
14205                         return 32*1024;
14206         } else if (gen >= 3) {
14207                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14208                         return 8*1024;
14209                 else
14210                         return 16*1024;
14211         } else {
14212                 /* XXX DSPC is limited to 4k tiled */
14213                 return 8*1024;
14214         }
14215 }
14216
14217 static int intel_framebuffer_init(struct drm_device *dev,
14218                                   struct intel_framebuffer *intel_fb,
14219                                   struct drm_mode_fb_cmd2 *mode_cmd,
14220                                   struct drm_i915_gem_object *obj)
14221 {
14222         unsigned int aligned_height;
14223         int ret;
14224         u32 pitch_limit, stride_alignment;
14225
14226         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14227
14228         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14229                 /* Enforce that fb modifier and tiling mode match, but only for
14230                  * X-tiled. This is needed for FBC. */
14231                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14232                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14233                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14234                         return -EINVAL;
14235                 }
14236         } else {
14237                 if (obj->tiling_mode == I915_TILING_X)
14238                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14239                 else if (obj->tiling_mode == I915_TILING_Y) {
14240                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14241                         return -EINVAL;
14242                 }
14243         }
14244
14245         /* Passed in modifier sanity checking. */
14246         switch (mode_cmd->modifier[0]) {
14247         case I915_FORMAT_MOD_Y_TILED:
14248         case I915_FORMAT_MOD_Yf_TILED:
14249                 if (INTEL_INFO(dev)->gen < 9) {
14250                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14251                                   mode_cmd->modifier[0]);
14252                         return -EINVAL;
14253                 }
14254         case DRM_FORMAT_MOD_NONE:
14255         case I915_FORMAT_MOD_X_TILED:
14256                 break;
14257         default:
14258                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14259                           mode_cmd->modifier[0]);
14260                 return -EINVAL;
14261         }
14262
14263         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14264                                                      mode_cmd->pixel_format);
14265         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14266                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14267                           mode_cmd->pitches[0], stride_alignment);
14268                 return -EINVAL;
14269         }
14270
14271         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14272                                            mode_cmd->pixel_format);
14273         if (mode_cmd->pitches[0] > pitch_limit) {
14274                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14275                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14276                           "tiled" : "linear",
14277                           mode_cmd->pitches[0], pitch_limit);
14278                 return -EINVAL;
14279         }
14280
14281         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14282             mode_cmd->pitches[0] != obj->stride) {
14283                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14284                           mode_cmd->pitches[0], obj->stride);
14285                 return -EINVAL;
14286         }
14287
14288         /* Reject formats not supported by any plane early. */
14289         switch (mode_cmd->pixel_format) {
14290         case DRM_FORMAT_C8:
14291         case DRM_FORMAT_RGB565:
14292         case DRM_FORMAT_XRGB8888:
14293         case DRM_FORMAT_ARGB8888:
14294                 break;
14295         case DRM_FORMAT_XRGB1555:
14296                 if (INTEL_INFO(dev)->gen > 3) {
14297                         DRM_DEBUG("unsupported pixel format: %s\n",
14298                                   drm_get_format_name(mode_cmd->pixel_format));
14299                         return -EINVAL;
14300                 }
14301                 break;
14302         case DRM_FORMAT_ABGR8888:
14303                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14304                         DRM_DEBUG("unsupported pixel format: %s\n",
14305                                   drm_get_format_name(mode_cmd->pixel_format));
14306                         return -EINVAL;
14307                 }
14308                 break;
14309         case DRM_FORMAT_XBGR8888:
14310         case DRM_FORMAT_XRGB2101010:
14311         case DRM_FORMAT_XBGR2101010:
14312                 if (INTEL_INFO(dev)->gen < 4) {
14313                         DRM_DEBUG("unsupported pixel format: %s\n",
14314                                   drm_get_format_name(mode_cmd->pixel_format));
14315                         return -EINVAL;
14316                 }
14317                 break;
14318         case DRM_FORMAT_ABGR2101010:
14319                 if (!IS_VALLEYVIEW(dev)) {
14320                         DRM_DEBUG("unsupported pixel format: %s\n",
14321                                   drm_get_format_name(mode_cmd->pixel_format));
14322                         return -EINVAL;
14323                 }
14324                 break;
14325         case DRM_FORMAT_YUYV:
14326         case DRM_FORMAT_UYVY:
14327         case DRM_FORMAT_YVYU:
14328         case DRM_FORMAT_VYUY:
14329                 if (INTEL_INFO(dev)->gen < 5) {
14330                         DRM_DEBUG("unsupported pixel format: %s\n",
14331                                   drm_get_format_name(mode_cmd->pixel_format));
14332                         return -EINVAL;
14333                 }
14334                 break;
14335         default:
14336                 DRM_DEBUG("unsupported pixel format: %s\n",
14337                           drm_get_format_name(mode_cmd->pixel_format));
14338                 return -EINVAL;
14339         }
14340
14341         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14342         if (mode_cmd->offsets[0] != 0)
14343                 return -EINVAL;
14344
14345         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14346                                                mode_cmd->pixel_format,
14347                                                mode_cmd->modifier[0]);
14348         /* FIXME drm helper for size checks (especially planar formats)? */
14349         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14350                 return -EINVAL;
14351
14352         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14353         intel_fb->obj = obj;
14354         intel_fb->obj->framebuffer_references++;
14355
14356         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14357         if (ret) {
14358                 DRM_ERROR("framebuffer init failed %d\n", ret);
14359                 return ret;
14360         }
14361
14362         return 0;
14363 }
14364
14365 static struct drm_framebuffer *
14366 intel_user_framebuffer_create(struct drm_device *dev,
14367                               struct drm_file *filp,
14368                               struct drm_mode_fb_cmd2 *mode_cmd)
14369 {
14370         struct drm_i915_gem_object *obj;
14371
14372         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14373                                                 mode_cmd->handles[0]));
14374         if (&obj->base == NULL)
14375                 return ERR_PTR(-ENOENT);
14376
14377         return intel_framebuffer_create(dev, mode_cmd, obj);
14378 }
14379
14380 #ifndef CONFIG_DRM_FBDEV_EMULATION
14381 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14382 {
14383 }
14384 #endif
14385
14386 static const struct drm_mode_config_funcs intel_mode_funcs = {
14387         .fb_create = intel_user_framebuffer_create,
14388         .output_poll_changed = intel_fbdev_output_poll_changed,
14389         .atomic_check = intel_atomic_check,
14390         .atomic_commit = intel_atomic_commit,
14391         .atomic_state_alloc = intel_atomic_state_alloc,
14392         .atomic_state_clear = intel_atomic_state_clear,
14393 };
14394
14395 /* Set up chip specific display functions */
14396 static void intel_init_display(struct drm_device *dev)
14397 {
14398         struct drm_i915_private *dev_priv = dev->dev_private;
14399
14400         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14401                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14402         else if (IS_CHERRYVIEW(dev))
14403                 dev_priv->display.find_dpll = chv_find_best_dpll;
14404         else if (IS_VALLEYVIEW(dev))
14405                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14406         else if (IS_PINEVIEW(dev))
14407                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14408         else
14409                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14410
14411         if (INTEL_INFO(dev)->gen >= 9) {
14412                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14413                 dev_priv->display.get_initial_plane_config =
14414                         skylake_get_initial_plane_config;
14415                 dev_priv->display.crtc_compute_clock =
14416                         haswell_crtc_compute_clock;
14417                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14418                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14419                 dev_priv->display.update_primary_plane =
14420                         skylake_update_primary_plane;
14421         } else if (HAS_DDI(dev)) {
14422                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14423                 dev_priv->display.get_initial_plane_config =
14424                         ironlake_get_initial_plane_config;
14425                 dev_priv->display.crtc_compute_clock =
14426                         haswell_crtc_compute_clock;
14427                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14428                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14429                 dev_priv->display.update_primary_plane =
14430                         ironlake_update_primary_plane;
14431         } else if (HAS_PCH_SPLIT(dev)) {
14432                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14433                 dev_priv->display.get_initial_plane_config =
14434                         ironlake_get_initial_plane_config;
14435                 dev_priv->display.crtc_compute_clock =
14436                         ironlake_crtc_compute_clock;
14437                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14438                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14439                 dev_priv->display.update_primary_plane =
14440                         ironlake_update_primary_plane;
14441         } else if (IS_VALLEYVIEW(dev)) {
14442                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14443                 dev_priv->display.get_initial_plane_config =
14444                         i9xx_get_initial_plane_config;
14445                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14446                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14447                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14448                 dev_priv->display.update_primary_plane =
14449                         i9xx_update_primary_plane;
14450         } else {
14451                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14452                 dev_priv->display.get_initial_plane_config =
14453                         i9xx_get_initial_plane_config;
14454                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14455                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14456                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14457                 dev_priv->display.update_primary_plane =
14458                         i9xx_update_primary_plane;
14459         }
14460
14461         /* Returns the core display clock speed */
14462         if (IS_SKYLAKE(dev))
14463                 dev_priv->display.get_display_clock_speed =
14464                         skylake_get_display_clock_speed;
14465         else if (IS_BROXTON(dev))
14466                 dev_priv->display.get_display_clock_speed =
14467                         broxton_get_display_clock_speed;
14468         else if (IS_BROADWELL(dev))
14469                 dev_priv->display.get_display_clock_speed =
14470                         broadwell_get_display_clock_speed;
14471         else if (IS_HASWELL(dev))
14472                 dev_priv->display.get_display_clock_speed =
14473                         haswell_get_display_clock_speed;
14474         else if (IS_VALLEYVIEW(dev))
14475                 dev_priv->display.get_display_clock_speed =
14476                         valleyview_get_display_clock_speed;
14477         else if (IS_GEN5(dev))
14478                 dev_priv->display.get_display_clock_speed =
14479                         ilk_get_display_clock_speed;
14480         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14481                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14482                 dev_priv->display.get_display_clock_speed =
14483                         i945_get_display_clock_speed;
14484         else if (IS_GM45(dev))
14485                 dev_priv->display.get_display_clock_speed =
14486                         gm45_get_display_clock_speed;
14487         else if (IS_CRESTLINE(dev))
14488                 dev_priv->display.get_display_clock_speed =
14489                         i965gm_get_display_clock_speed;
14490         else if (IS_PINEVIEW(dev))
14491                 dev_priv->display.get_display_clock_speed =
14492                         pnv_get_display_clock_speed;
14493         else if (IS_G33(dev) || IS_G4X(dev))
14494                 dev_priv->display.get_display_clock_speed =
14495                         g33_get_display_clock_speed;
14496         else if (IS_I915G(dev))
14497                 dev_priv->display.get_display_clock_speed =
14498                         i915_get_display_clock_speed;
14499         else if (IS_I945GM(dev) || IS_845G(dev))
14500                 dev_priv->display.get_display_clock_speed =
14501                         i9xx_misc_get_display_clock_speed;
14502         else if (IS_PINEVIEW(dev))
14503                 dev_priv->display.get_display_clock_speed =
14504                         pnv_get_display_clock_speed;
14505         else if (IS_I915GM(dev))
14506                 dev_priv->display.get_display_clock_speed =
14507                         i915gm_get_display_clock_speed;
14508         else if (IS_I865G(dev))
14509                 dev_priv->display.get_display_clock_speed =
14510                         i865_get_display_clock_speed;
14511         else if (IS_I85X(dev))
14512                 dev_priv->display.get_display_clock_speed =
14513                         i85x_get_display_clock_speed;
14514         else { /* 830 */
14515                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14516                 dev_priv->display.get_display_clock_speed =
14517                         i830_get_display_clock_speed;
14518         }
14519
14520         if (IS_GEN5(dev)) {
14521                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14522         } else if (IS_GEN6(dev)) {
14523                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14524         } else if (IS_IVYBRIDGE(dev)) {
14525                 /* FIXME: detect B0+ stepping and use auto training */
14526                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14527         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14528                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14529                 if (IS_BROADWELL(dev)) {
14530                         dev_priv->display.modeset_commit_cdclk =
14531                                 broadwell_modeset_commit_cdclk;
14532                         dev_priv->display.modeset_calc_cdclk =
14533                                 broadwell_modeset_calc_cdclk;
14534                 }
14535         } else if (IS_VALLEYVIEW(dev)) {
14536                 dev_priv->display.modeset_commit_cdclk =
14537                         valleyview_modeset_commit_cdclk;
14538                 dev_priv->display.modeset_calc_cdclk =
14539                         valleyview_modeset_calc_cdclk;
14540         } else if (IS_BROXTON(dev)) {
14541                 dev_priv->display.modeset_commit_cdclk =
14542                         broxton_modeset_commit_cdclk;
14543                 dev_priv->display.modeset_calc_cdclk =
14544                         broxton_modeset_calc_cdclk;
14545         }
14546
14547         switch (INTEL_INFO(dev)->gen) {
14548         case 2:
14549                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14550                 break;
14551
14552         case 3:
14553                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14554                 break;
14555
14556         case 4:
14557         case 5:
14558                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14559                 break;
14560
14561         case 6:
14562                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14563                 break;
14564         case 7:
14565         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14566                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14567                 break;
14568         case 9:
14569                 /* Drop through - unsupported since execlist only. */
14570         default:
14571                 /* Default just returns -ENODEV to indicate unsupported */
14572                 dev_priv->display.queue_flip = intel_default_queue_flip;
14573         }
14574
14575         mutex_init(&dev_priv->pps_mutex);
14576 }
14577
14578 /*
14579  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14580  * resume, or other times.  This quirk makes sure that's the case for
14581  * affected systems.
14582  */
14583 static void quirk_pipea_force(struct drm_device *dev)
14584 {
14585         struct drm_i915_private *dev_priv = dev->dev_private;
14586
14587         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14588         DRM_INFO("applying pipe a force quirk\n");
14589 }
14590
14591 static void quirk_pipeb_force(struct drm_device *dev)
14592 {
14593         struct drm_i915_private *dev_priv = dev->dev_private;
14594
14595         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14596         DRM_INFO("applying pipe b force quirk\n");
14597 }
14598
14599 /*
14600  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14601  */
14602 static void quirk_ssc_force_disable(struct drm_device *dev)
14603 {
14604         struct drm_i915_private *dev_priv = dev->dev_private;
14605         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14606         DRM_INFO("applying lvds SSC disable quirk\n");
14607 }
14608
14609 /*
14610  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14611  * brightness value
14612  */
14613 static void quirk_invert_brightness(struct drm_device *dev)
14614 {
14615         struct drm_i915_private *dev_priv = dev->dev_private;
14616         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14617         DRM_INFO("applying inverted panel brightness quirk\n");
14618 }
14619
14620 /* Some VBT's incorrectly indicate no backlight is present */
14621 static void quirk_backlight_present(struct drm_device *dev)
14622 {
14623         struct drm_i915_private *dev_priv = dev->dev_private;
14624         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14625         DRM_INFO("applying backlight present quirk\n");
14626 }
14627
14628 struct intel_quirk {
14629         int device;
14630         int subsystem_vendor;
14631         int subsystem_device;
14632         void (*hook)(struct drm_device *dev);
14633 };
14634
14635 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14636 struct intel_dmi_quirk {
14637         void (*hook)(struct drm_device *dev);
14638         const struct dmi_system_id (*dmi_id_list)[];
14639 };
14640
14641 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14642 {
14643         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14644         return 1;
14645 }
14646
14647 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14648         {
14649                 .dmi_id_list = &(const struct dmi_system_id[]) {
14650                         {
14651                                 .callback = intel_dmi_reverse_brightness,
14652                                 .ident = "NCR Corporation",
14653                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14654                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14655                                 },
14656                         },
14657                         { }  /* terminating entry */
14658                 },
14659                 .hook = quirk_invert_brightness,
14660         },
14661 };
14662
14663 static struct intel_quirk intel_quirks[] = {
14664         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14665         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14666
14667         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14668         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14669
14670         /* 830 needs to leave pipe A & dpll A up */
14671         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14672
14673         /* 830 needs to leave pipe B & dpll B up */
14674         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14675
14676         /* Lenovo U160 cannot use SSC on LVDS */
14677         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14678
14679         /* Sony Vaio Y cannot use SSC on LVDS */
14680         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14681
14682         /* Acer Aspire 5734Z must invert backlight brightness */
14683         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14684
14685         /* Acer/eMachines G725 */
14686         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14687
14688         /* Acer/eMachines e725 */
14689         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14690
14691         /* Acer/Packard Bell NCL20 */
14692         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14693
14694         /* Acer Aspire 4736Z */
14695         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14696
14697         /* Acer Aspire 5336 */
14698         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14699
14700         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14701         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14702
14703         /* Acer C720 Chromebook (Core i3 4005U) */
14704         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14705
14706         /* Apple Macbook 2,1 (Core 2 T7400) */
14707         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14708
14709         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14710         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14711
14712         /* HP Chromebook 14 (Celeron 2955U) */
14713         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14714
14715         /* Dell Chromebook 11 */
14716         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14717 };
14718
14719 static void intel_init_quirks(struct drm_device *dev)
14720 {
14721         struct pci_dev *d = dev->pdev;
14722         int i;
14723
14724         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14725                 struct intel_quirk *q = &intel_quirks[i];
14726
14727                 if (d->device == q->device &&
14728                     (d->subsystem_vendor == q->subsystem_vendor ||
14729                      q->subsystem_vendor == PCI_ANY_ID) &&
14730                     (d->subsystem_device == q->subsystem_device ||
14731                      q->subsystem_device == PCI_ANY_ID))
14732                         q->hook(dev);
14733         }
14734         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14735                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14736                         intel_dmi_quirks[i].hook(dev);
14737         }
14738 }
14739
14740 /* Disable the VGA plane that we never use */
14741 static void i915_disable_vga(struct drm_device *dev)
14742 {
14743         struct drm_i915_private *dev_priv = dev->dev_private;
14744         u8 sr1;
14745         u32 vga_reg = i915_vgacntrl_reg(dev);
14746
14747         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14748         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14749         outb(SR01, VGA_SR_INDEX);
14750         sr1 = inb(VGA_SR_DATA);
14751         outb(sr1 | 1<<5, VGA_SR_DATA);
14752         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14753         udelay(300);
14754
14755         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14756         POSTING_READ(vga_reg);
14757 }
14758
14759 void intel_modeset_init_hw(struct drm_device *dev)
14760 {
14761         intel_update_cdclk(dev);
14762         intel_prepare_ddi(dev);
14763         intel_init_clock_gating(dev);
14764         intel_enable_gt_powersave(dev);
14765 }
14766
14767 void intel_modeset_init(struct drm_device *dev)
14768 {
14769         struct drm_i915_private *dev_priv = dev->dev_private;
14770         int sprite, ret;
14771         enum pipe pipe;
14772         struct intel_crtc *crtc;
14773
14774         drm_mode_config_init(dev);
14775
14776         dev->mode_config.min_width = 0;
14777         dev->mode_config.min_height = 0;
14778
14779         dev->mode_config.preferred_depth = 24;
14780         dev->mode_config.prefer_shadow = 1;
14781
14782         dev->mode_config.allow_fb_modifiers = true;
14783
14784         dev->mode_config.funcs = &intel_mode_funcs;
14785
14786         intel_init_quirks(dev);
14787
14788         intel_init_pm(dev);
14789
14790         if (INTEL_INFO(dev)->num_pipes == 0)
14791                 return;
14792
14793         /*
14794          * There may be no VBT; and if the BIOS enabled SSC we can
14795          * just keep using it to avoid unnecessary flicker.  Whereas if the
14796          * BIOS isn't using it, don't assume it will work even if the VBT
14797          * indicates as much.
14798          */
14799         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14800                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14801                                             DREF_SSC1_ENABLE);
14802
14803                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14804                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14805                                      bios_lvds_use_ssc ? "en" : "dis",
14806                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14807                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14808                 }
14809         }
14810
14811         intel_init_display(dev);
14812         intel_init_audio(dev);
14813
14814         if (IS_GEN2(dev)) {
14815                 dev->mode_config.max_width = 2048;
14816                 dev->mode_config.max_height = 2048;
14817         } else if (IS_GEN3(dev)) {
14818                 dev->mode_config.max_width = 4096;
14819                 dev->mode_config.max_height = 4096;
14820         } else {
14821                 dev->mode_config.max_width = 8192;
14822                 dev->mode_config.max_height = 8192;
14823         }
14824
14825         if (IS_845G(dev) || IS_I865G(dev)) {
14826                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14827                 dev->mode_config.cursor_height = 1023;
14828         } else if (IS_GEN2(dev)) {
14829                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14830                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14831         } else {
14832                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14833                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14834         }
14835
14836         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14837
14838         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14839                       INTEL_INFO(dev)->num_pipes,
14840                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14841
14842         for_each_pipe(dev_priv, pipe) {
14843                 intel_crtc_init(dev, pipe);
14844                 for_each_sprite(dev_priv, pipe, sprite) {
14845                         ret = intel_plane_init(dev, pipe, sprite);
14846                         if (ret)
14847                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14848                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14849                 }
14850         }
14851
14852         intel_update_czclk(dev_priv);
14853         intel_update_cdclk(dev);
14854
14855         intel_shared_dpll_init(dev);
14856
14857         /* Just disable it once at startup */
14858         i915_disable_vga(dev);
14859         intel_setup_outputs(dev);
14860
14861         /* Just in case the BIOS is doing something questionable. */
14862         intel_fbc_disable(dev_priv);
14863
14864         drm_modeset_lock_all(dev);
14865         intel_modeset_setup_hw_state(dev);
14866         drm_modeset_unlock_all(dev);
14867
14868         for_each_intel_crtc(dev, crtc) {
14869                 struct intel_initial_plane_config plane_config = {};
14870
14871                 if (!crtc->active)
14872                         continue;
14873
14874                 /*
14875                  * Note that reserving the BIOS fb up front prevents us
14876                  * from stuffing other stolen allocations like the ring
14877                  * on top.  This prevents some ugliness at boot time, and
14878                  * can even allow for smooth boot transitions if the BIOS
14879                  * fb is large enough for the active pipe configuration.
14880                  */
14881                 dev_priv->display.get_initial_plane_config(crtc,
14882                                                            &plane_config);
14883
14884                 /*
14885                  * If the fb is shared between multiple heads, we'll
14886                  * just get the first one.
14887                  */
14888                 intel_find_initial_plane_obj(crtc, &plane_config);
14889         }
14890 }
14891
14892 static void intel_enable_pipe_a(struct drm_device *dev)
14893 {
14894         struct intel_connector *connector;
14895         struct drm_connector *crt = NULL;
14896         struct intel_load_detect_pipe load_detect_temp;
14897         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14898
14899         /* We can't just switch on the pipe A, we need to set things up with a
14900          * proper mode and output configuration. As a gross hack, enable pipe A
14901          * by enabling the load detect pipe once. */
14902         for_each_intel_connector(dev, connector) {
14903                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14904                         crt = &connector->base;
14905                         break;
14906                 }
14907         }
14908
14909         if (!crt)
14910                 return;
14911
14912         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14913                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14914 }
14915
14916 static bool
14917 intel_check_plane_mapping(struct intel_crtc *crtc)
14918 {
14919         struct drm_device *dev = crtc->base.dev;
14920         struct drm_i915_private *dev_priv = dev->dev_private;
14921         u32 val;
14922
14923         if (INTEL_INFO(dev)->num_pipes == 1)
14924                 return true;
14925
14926         val = I915_READ(DSPCNTR(!crtc->plane));
14927
14928         if ((val & DISPLAY_PLANE_ENABLE) &&
14929             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14930                 return false;
14931
14932         return true;
14933 }
14934
14935 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14936 {
14937         struct drm_device *dev = crtc->base.dev;
14938         struct intel_encoder *encoder;
14939
14940         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14941                 return true;
14942
14943         return false;
14944 }
14945
14946 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14947 {
14948         struct drm_device *dev = crtc->base.dev;
14949         struct drm_i915_private *dev_priv = dev->dev_private;
14950         u32 reg;
14951
14952         /* Clear any frame start delays used for debugging left by the BIOS */
14953         reg = PIPECONF(crtc->config->cpu_transcoder);
14954         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14955
14956         /* restore vblank interrupts to correct state */
14957         drm_crtc_vblank_reset(&crtc->base);
14958         if (crtc->active) {
14959                 struct intel_plane *plane;
14960
14961                 drm_crtc_vblank_on(&crtc->base);
14962
14963                 /* Disable everything but the primary plane */
14964                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14965                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14966                                 continue;
14967
14968                         plane->disable_plane(&plane->base, &crtc->base);
14969                 }
14970         }
14971
14972         /* We need to sanitize the plane -> pipe mapping first because this will
14973          * disable the crtc (and hence change the state) if it is wrong. Note
14974          * that gen4+ has a fixed plane -> pipe mapping.  */
14975         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14976                 bool plane;
14977
14978                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14979                               crtc->base.base.id);
14980
14981                 /* Pipe has the wrong plane attached and the plane is active.
14982                  * Temporarily change the plane mapping and disable everything
14983                  * ...  */
14984                 plane = crtc->plane;
14985                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14986                 crtc->plane = !plane;
14987                 intel_crtc_disable_noatomic(&crtc->base);
14988                 crtc->plane = plane;
14989         }
14990
14991         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14992             crtc->pipe == PIPE_A && !crtc->active) {
14993                 /* BIOS forgot to enable pipe A, this mostly happens after
14994                  * resume. Force-enable the pipe to fix this, the update_dpms
14995                  * call below we restore the pipe to the right state, but leave
14996                  * the required bits on. */
14997                 intel_enable_pipe_a(dev);
14998         }
14999
15000         /* Adjust the state of the output pipe according to whether we
15001          * have active connectors/encoders. */
15002         if (!intel_crtc_has_encoders(crtc))
15003                 intel_crtc_disable_noatomic(&crtc->base);
15004
15005         if (crtc->active != crtc->base.state->active) {
15006                 struct intel_encoder *encoder;
15007
15008                 /* This can happen either due to bugs in the get_hw_state
15009                  * functions or because of calls to intel_crtc_disable_noatomic,
15010                  * or because the pipe is force-enabled due to the
15011                  * pipe A quirk. */
15012                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15013                               crtc->base.base.id,
15014                               crtc->base.state->enable ? "enabled" : "disabled",
15015                               crtc->active ? "enabled" : "disabled");
15016
15017                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15018                 crtc->base.state->active = crtc->active;
15019                 crtc->base.enabled = crtc->active;
15020
15021                 /* Because we only establish the connector -> encoder ->
15022                  * crtc links if something is active, this means the
15023                  * crtc is now deactivated. Break the links. connector
15024                  * -> encoder links are only establish when things are
15025                  *  actually up, hence no need to break them. */
15026                 WARN_ON(crtc->active);
15027
15028                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15029                         encoder->base.crtc = NULL;
15030         }
15031
15032         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15033                 /*
15034                  * We start out with underrun reporting disabled to avoid races.
15035                  * For correct bookkeeping mark this on active crtcs.
15036                  *
15037                  * Also on gmch platforms we dont have any hardware bits to
15038                  * disable the underrun reporting. Which means we need to start
15039                  * out with underrun reporting disabled also on inactive pipes,
15040                  * since otherwise we'll complain about the garbage we read when
15041                  * e.g. coming up after runtime pm.
15042                  *
15043                  * No protection against concurrent access is required - at
15044                  * worst a fifo underrun happens which also sets this to false.
15045                  */
15046                 crtc->cpu_fifo_underrun_disabled = true;
15047                 crtc->pch_fifo_underrun_disabled = true;
15048         }
15049 }
15050
15051 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15052 {
15053         struct intel_connector *connector;
15054         struct drm_device *dev = encoder->base.dev;
15055         bool active = false;
15056
15057         /* We need to check both for a crtc link (meaning that the
15058          * encoder is active and trying to read from a pipe) and the
15059          * pipe itself being active. */
15060         bool has_active_crtc = encoder->base.crtc &&
15061                 to_intel_crtc(encoder->base.crtc)->active;
15062
15063         for_each_intel_connector(dev, connector) {
15064                 if (connector->base.encoder != &encoder->base)
15065                         continue;
15066
15067                 active = true;
15068                 break;
15069         }
15070
15071         if (active && !has_active_crtc) {
15072                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15073                               encoder->base.base.id,
15074                               encoder->base.name);
15075
15076                 /* Connector is active, but has no active pipe. This is
15077                  * fallout from our resume register restoring. Disable
15078                  * the encoder manually again. */
15079                 if (encoder->base.crtc) {
15080                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15081                                       encoder->base.base.id,
15082                                       encoder->base.name);
15083                         encoder->disable(encoder);
15084                         if (encoder->post_disable)
15085                                 encoder->post_disable(encoder);
15086                 }
15087                 encoder->base.crtc = NULL;
15088
15089                 /* Inconsistent output/port/pipe state happens presumably due to
15090                  * a bug in one of the get_hw_state functions. Or someplace else
15091                  * in our code, like the register restore mess on resume. Clamp
15092                  * things to off as a safer default. */
15093                 for_each_intel_connector(dev, connector) {
15094                         if (connector->encoder != encoder)
15095                                 continue;
15096                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15097                         connector->base.encoder = NULL;
15098                 }
15099         }
15100         /* Enabled encoders without active connectors will be fixed in
15101          * the crtc fixup. */
15102 }
15103
15104 void i915_redisable_vga_power_on(struct drm_device *dev)
15105 {
15106         struct drm_i915_private *dev_priv = dev->dev_private;
15107         u32 vga_reg = i915_vgacntrl_reg(dev);
15108
15109         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15110                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15111                 i915_disable_vga(dev);
15112         }
15113 }
15114
15115 void i915_redisable_vga(struct drm_device *dev)
15116 {
15117         struct drm_i915_private *dev_priv = dev->dev_private;
15118
15119         /* This function can be called both from intel_modeset_setup_hw_state or
15120          * at a very early point in our resume sequence, where the power well
15121          * structures are not yet restored. Since this function is at a very
15122          * paranoid "someone might have enabled VGA while we were not looking"
15123          * level, just check if the power well is enabled instead of trying to
15124          * follow the "don't touch the power well if we don't need it" policy
15125          * the rest of the driver uses. */
15126         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15127                 return;
15128
15129         i915_redisable_vga_power_on(dev);
15130 }
15131
15132 static bool primary_get_hw_state(struct intel_plane *plane)
15133 {
15134         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15135
15136         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15137 }
15138
15139 /* FIXME read out full plane state for all planes */
15140 static void readout_plane_state(struct intel_crtc *crtc)
15141 {
15142         struct drm_plane *primary = crtc->base.primary;
15143         struct intel_plane_state *plane_state =
15144                 to_intel_plane_state(primary->state);
15145
15146         plane_state->visible =
15147                 primary_get_hw_state(to_intel_plane(primary));
15148
15149         if (plane_state->visible)
15150                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15151 }
15152
15153 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15154 {
15155         struct drm_i915_private *dev_priv = dev->dev_private;
15156         enum pipe pipe;
15157         struct intel_crtc *crtc;
15158         struct intel_encoder *encoder;
15159         struct intel_connector *connector;
15160         int i;
15161
15162         for_each_intel_crtc(dev, crtc) {
15163                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15164                 memset(crtc->config, 0, sizeof(*crtc->config));
15165                 crtc->config->base.crtc = &crtc->base;
15166
15167                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15168                                                                  crtc->config);
15169
15170                 crtc->base.state->active = crtc->active;
15171                 crtc->base.enabled = crtc->active;
15172
15173                 readout_plane_state(crtc);
15174
15175                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15176                               crtc->base.base.id,
15177                               crtc->active ? "enabled" : "disabled");
15178         }
15179
15180         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15181                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15182
15183                 pll->on = pll->get_hw_state(dev_priv, pll,
15184                                             &pll->config.hw_state);
15185                 pll->active = 0;
15186                 pll->config.crtc_mask = 0;
15187                 for_each_intel_crtc(dev, crtc) {
15188                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15189                                 pll->active++;
15190                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15191                         }
15192                 }
15193
15194                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15195                               pll->name, pll->config.crtc_mask, pll->on);
15196
15197                 if (pll->config.crtc_mask)
15198                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15199         }
15200
15201         for_each_intel_encoder(dev, encoder) {
15202                 pipe = 0;
15203
15204                 if (encoder->get_hw_state(encoder, &pipe)) {
15205                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15206                         encoder->base.crtc = &crtc->base;
15207                         encoder->get_config(encoder, crtc->config);
15208                 } else {
15209                         encoder->base.crtc = NULL;
15210                 }
15211
15212                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15213                               encoder->base.base.id,
15214                               encoder->base.name,
15215                               encoder->base.crtc ? "enabled" : "disabled",
15216                               pipe_name(pipe));
15217         }
15218
15219         for_each_intel_connector(dev, connector) {
15220                 if (connector->get_hw_state(connector)) {
15221                         connector->base.dpms = DRM_MODE_DPMS_ON;
15222                         connector->base.encoder = &connector->encoder->base;
15223                 } else {
15224                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15225                         connector->base.encoder = NULL;
15226                 }
15227                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15228                               connector->base.base.id,
15229                               connector->base.name,
15230                               connector->base.encoder ? "enabled" : "disabled");
15231         }
15232
15233         for_each_intel_crtc(dev, crtc) {
15234                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15235
15236                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15237                 if (crtc->base.state->active) {
15238                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15239                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15240                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15241
15242                         /*
15243                          * The initial mode needs to be set in order to keep
15244                          * the atomic core happy. It wants a valid mode if the
15245                          * crtc's enabled, so we do the above call.
15246                          *
15247                          * At this point some state updated by the connectors
15248                          * in their ->detect() callback has not run yet, so
15249                          * no recalculation can be done yet.
15250                          *
15251                          * Even if we could do a recalculation and modeset
15252                          * right now it would cause a double modeset if
15253                          * fbdev or userspace chooses a different initial mode.
15254                          *
15255                          * If that happens, someone indicated they wanted a
15256                          * mode change, which means it's safe to do a full
15257                          * recalculation.
15258                          */
15259                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15260
15261                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15262                         update_scanline_offset(crtc);
15263                 }
15264         }
15265 }
15266
15267 /* Scan out the current hw modeset state,
15268  * and sanitizes it to the current state
15269  */
15270 static void
15271 intel_modeset_setup_hw_state(struct drm_device *dev)
15272 {
15273         struct drm_i915_private *dev_priv = dev->dev_private;
15274         enum pipe pipe;
15275         struct intel_crtc *crtc;
15276         struct intel_encoder *encoder;
15277         int i;
15278
15279         intel_modeset_readout_hw_state(dev);
15280
15281         /* HW state is read out, now we need to sanitize this mess. */
15282         for_each_intel_encoder(dev, encoder) {
15283                 intel_sanitize_encoder(encoder);
15284         }
15285
15286         for_each_pipe(dev_priv, pipe) {
15287                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15288                 intel_sanitize_crtc(crtc);
15289                 intel_dump_pipe_config(crtc, crtc->config,
15290                                        "[setup_hw_state]");
15291         }
15292
15293         intel_modeset_update_connector_atomic_state(dev);
15294
15295         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15296                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15297
15298                 if (!pll->on || pll->active)
15299                         continue;
15300
15301                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15302
15303                 pll->disable(dev_priv, pll);
15304                 pll->on = false;
15305         }
15306
15307         if (IS_VALLEYVIEW(dev))
15308                 vlv_wm_get_hw_state(dev);
15309         else if (IS_GEN9(dev))
15310                 skl_wm_get_hw_state(dev);
15311         else if (HAS_PCH_SPLIT(dev))
15312                 ilk_wm_get_hw_state(dev);
15313
15314         for_each_intel_crtc(dev, crtc) {
15315                 unsigned long put_domains;
15316
15317                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15318                 if (WARN_ON(put_domains))
15319                         modeset_put_power_domains(dev_priv, put_domains);
15320         }
15321         intel_display_set_init_power(dev_priv, false);
15322 }
15323
15324 void intel_display_resume(struct drm_device *dev)
15325 {
15326         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15327         struct intel_connector *conn;
15328         struct intel_plane *plane;
15329         struct drm_crtc *crtc;
15330         int ret;
15331
15332         if (!state)
15333                 return;
15334
15335         state->acquire_ctx = dev->mode_config.acquire_ctx;
15336
15337         /* preserve complete old state, including dpll */
15338         intel_atomic_get_shared_dpll_state(state);
15339
15340         for_each_crtc(dev, crtc) {
15341                 struct drm_crtc_state *crtc_state =
15342                         drm_atomic_get_crtc_state(state, crtc);
15343
15344                 ret = PTR_ERR_OR_ZERO(crtc_state);
15345                 if (ret)
15346                         goto err;
15347
15348                 /* force a restore */
15349                 crtc_state->mode_changed = true;
15350         }
15351
15352         for_each_intel_plane(dev, plane) {
15353                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15354                 if (ret)
15355                         goto err;
15356         }
15357
15358         for_each_intel_connector(dev, conn) {
15359                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15360                 if (ret)
15361                         goto err;
15362         }
15363
15364         intel_modeset_setup_hw_state(dev);
15365
15366         i915_redisable_vga(dev);
15367         ret = drm_atomic_commit(state);
15368         if (!ret)
15369                 return;
15370
15371 err:
15372         DRM_ERROR("Restoring old state failed with %i\n", ret);
15373         drm_atomic_state_free(state);
15374 }
15375
15376 void intel_modeset_gem_init(struct drm_device *dev)
15377 {
15378         struct drm_crtc *c;
15379         struct drm_i915_gem_object *obj;
15380         int ret;
15381
15382         mutex_lock(&dev->struct_mutex);
15383         intel_init_gt_powersave(dev);
15384         mutex_unlock(&dev->struct_mutex);
15385
15386         intel_modeset_init_hw(dev);
15387
15388         intel_setup_overlay(dev);
15389
15390         /*
15391          * Make sure any fbs we allocated at startup are properly
15392          * pinned & fenced.  When we do the allocation it's too early
15393          * for this.
15394          */
15395         for_each_crtc(dev, c) {
15396                 obj = intel_fb_obj(c->primary->fb);
15397                 if (obj == NULL)
15398                         continue;
15399
15400                 mutex_lock(&dev->struct_mutex);
15401                 ret = intel_pin_and_fence_fb_obj(c->primary,
15402                                                  c->primary->fb,
15403                                                  c->primary->state,
15404                                                  NULL, NULL);
15405                 mutex_unlock(&dev->struct_mutex);
15406                 if (ret) {
15407                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15408                                   to_intel_crtc(c)->pipe);
15409                         drm_framebuffer_unreference(c->primary->fb);
15410                         c->primary->fb = NULL;
15411                         c->primary->crtc = c->primary->state->crtc = NULL;
15412                         update_state_fb(c->primary);
15413                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15414                 }
15415         }
15416
15417         intel_backlight_register(dev);
15418 }
15419
15420 void intel_connector_unregister(struct intel_connector *intel_connector)
15421 {
15422         struct drm_connector *connector = &intel_connector->base;
15423
15424         intel_panel_destroy_backlight(connector);
15425         drm_connector_unregister(connector);
15426 }
15427
15428 void intel_modeset_cleanup(struct drm_device *dev)
15429 {
15430         struct drm_i915_private *dev_priv = dev->dev_private;
15431         struct drm_connector *connector;
15432
15433         intel_disable_gt_powersave(dev);
15434
15435         intel_backlight_unregister(dev);
15436
15437         /*
15438          * Interrupts and polling as the first thing to avoid creating havoc.
15439          * Too much stuff here (turning of connectors, ...) would
15440          * experience fancy races otherwise.
15441          */
15442         intel_irq_uninstall(dev_priv);
15443
15444         /*
15445          * Due to the hpd irq storm handling the hotplug work can re-arm the
15446          * poll handlers. Hence disable polling after hpd handling is shut down.
15447          */
15448         drm_kms_helper_poll_fini(dev);
15449
15450         intel_unregister_dsm_handler();
15451
15452         intel_fbc_disable(dev_priv);
15453
15454         /* flush any delayed tasks or pending work */
15455         flush_scheduled_work();
15456
15457         /* destroy the backlight and sysfs files before encoders/connectors */
15458         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15459                 struct intel_connector *intel_connector;
15460
15461                 intel_connector = to_intel_connector(connector);
15462                 intel_connector->unregister(intel_connector);
15463         }
15464
15465         drm_mode_config_cleanup(dev);
15466
15467         intel_cleanup_overlay(dev);
15468
15469         mutex_lock(&dev->struct_mutex);
15470         intel_cleanup_gt_powersave(dev);
15471         mutex_unlock(&dev->struct_mutex);
15472 }
15473
15474 /*
15475  * Return which encoder is currently attached for connector.
15476  */
15477 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15478 {
15479         return &intel_attached_encoder(connector)->base;
15480 }
15481
15482 void intel_connector_attach_encoder(struct intel_connector *connector,
15483                                     struct intel_encoder *encoder)
15484 {
15485         connector->encoder = encoder;
15486         drm_mode_connector_attach_encoder(&connector->base,
15487                                           &encoder->base);
15488 }
15489
15490 /*
15491  * set vga decode state - true == enable VGA decode
15492  */
15493 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15494 {
15495         struct drm_i915_private *dev_priv = dev->dev_private;
15496         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15497         u16 gmch_ctrl;
15498
15499         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15500                 DRM_ERROR("failed to read control word\n");
15501                 return -EIO;
15502         }
15503
15504         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15505                 return 0;
15506
15507         if (state)
15508                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15509         else
15510                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15511
15512         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15513                 DRM_ERROR("failed to write control word\n");
15514                 return -EIO;
15515         }
15516
15517         return 0;
15518 }
15519
15520 struct intel_display_error_state {
15521
15522         u32 power_well_driver;
15523
15524         int num_transcoders;
15525
15526         struct intel_cursor_error_state {
15527                 u32 control;
15528                 u32 position;
15529                 u32 base;
15530                 u32 size;
15531         } cursor[I915_MAX_PIPES];
15532
15533         struct intel_pipe_error_state {
15534                 bool power_domain_on;
15535                 u32 source;
15536                 u32 stat;
15537         } pipe[I915_MAX_PIPES];
15538
15539         struct intel_plane_error_state {
15540                 u32 control;
15541                 u32 stride;
15542                 u32 size;
15543                 u32 pos;
15544                 u32 addr;
15545                 u32 surface;
15546                 u32 tile_offset;
15547         } plane[I915_MAX_PIPES];
15548
15549         struct intel_transcoder_error_state {
15550                 bool power_domain_on;
15551                 enum transcoder cpu_transcoder;
15552
15553                 u32 conf;
15554
15555                 u32 htotal;
15556                 u32 hblank;
15557                 u32 hsync;
15558                 u32 vtotal;
15559                 u32 vblank;
15560                 u32 vsync;
15561         } transcoder[4];
15562 };
15563
15564 struct intel_display_error_state *
15565 intel_display_capture_error_state(struct drm_device *dev)
15566 {
15567         struct drm_i915_private *dev_priv = dev->dev_private;
15568         struct intel_display_error_state *error;
15569         int transcoders[] = {
15570                 TRANSCODER_A,
15571                 TRANSCODER_B,
15572                 TRANSCODER_C,
15573                 TRANSCODER_EDP,
15574         };
15575         int i;
15576
15577         if (INTEL_INFO(dev)->num_pipes == 0)
15578                 return NULL;
15579
15580         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15581         if (error == NULL)
15582                 return NULL;
15583
15584         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15585                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15586
15587         for_each_pipe(dev_priv, i) {
15588                 error->pipe[i].power_domain_on =
15589                         __intel_display_power_is_enabled(dev_priv,
15590                                                          POWER_DOMAIN_PIPE(i));
15591                 if (!error->pipe[i].power_domain_on)
15592                         continue;
15593
15594                 error->cursor[i].control = I915_READ(CURCNTR(i));
15595                 error->cursor[i].position = I915_READ(CURPOS(i));
15596                 error->cursor[i].base = I915_READ(CURBASE(i));
15597
15598                 error->plane[i].control = I915_READ(DSPCNTR(i));
15599                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15600                 if (INTEL_INFO(dev)->gen <= 3) {
15601                         error->plane[i].size = I915_READ(DSPSIZE(i));
15602                         error->plane[i].pos = I915_READ(DSPPOS(i));
15603                 }
15604                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15605                         error->plane[i].addr = I915_READ(DSPADDR(i));
15606                 if (INTEL_INFO(dev)->gen >= 4) {
15607                         error->plane[i].surface = I915_READ(DSPSURF(i));
15608                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15609                 }
15610
15611                 error->pipe[i].source = I915_READ(PIPESRC(i));
15612
15613                 if (HAS_GMCH_DISPLAY(dev))
15614                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15615         }
15616
15617         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15618         if (HAS_DDI(dev_priv->dev))
15619                 error->num_transcoders++; /* Account for eDP. */
15620
15621         for (i = 0; i < error->num_transcoders; i++) {
15622                 enum transcoder cpu_transcoder = transcoders[i];
15623
15624                 error->transcoder[i].power_domain_on =
15625                         __intel_display_power_is_enabled(dev_priv,
15626                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15627                 if (!error->transcoder[i].power_domain_on)
15628                         continue;
15629
15630                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15631
15632                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15633                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15634                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15635                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15636                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15637                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15638                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15639         }
15640
15641         return error;
15642 }
15643
15644 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15645
15646 void
15647 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15648                                 struct drm_device *dev,
15649                                 struct intel_display_error_state *error)
15650 {
15651         struct drm_i915_private *dev_priv = dev->dev_private;
15652         int i;
15653
15654         if (!error)
15655                 return;
15656
15657         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15658         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15659                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15660                            error->power_well_driver);
15661         for_each_pipe(dev_priv, i) {
15662                 err_printf(m, "Pipe [%d]:\n", i);
15663                 err_printf(m, "  Power: %s\n",
15664                            error->pipe[i].power_domain_on ? "on" : "off");
15665                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15666                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15667
15668                 err_printf(m, "Plane [%d]:\n", i);
15669                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15670                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15671                 if (INTEL_INFO(dev)->gen <= 3) {
15672                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15673                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15674                 }
15675                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15676                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15677                 if (INTEL_INFO(dev)->gen >= 4) {
15678                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15679                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15680                 }
15681
15682                 err_printf(m, "Cursor [%d]:\n", i);
15683                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15684                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15685                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15686         }
15687
15688         for (i = 0; i < error->num_transcoders; i++) {
15689                 err_printf(m, "CPU transcoder: %c\n",
15690                            transcoder_name(error->transcoder[i].cpu_transcoder));
15691                 err_printf(m, "  Power: %s\n",
15692                            error->transcoder[i].power_domain_on ? "on" : "off");
15693                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15694                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15695                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15696                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15697                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15698                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15699                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15700         }
15701 }
15702
15703 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15704 {
15705         struct intel_crtc *crtc;
15706
15707         for_each_intel_crtc(dev, crtc) {
15708                 struct intel_unpin_work *work;
15709
15710                 spin_lock_irq(&dev->event_lock);
15711
15712                 work = crtc->unpin_work;
15713
15714                 if (work && work->event &&
15715                     work->event->base.file_priv == file) {
15716                         kfree(work->event);
15717                         work->event = NULL;
15718                 }
15719
15720                 spin_unlock_irq(&dev->event_lock);
15721         }
15722 }