2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
52 DRM_FORMAT_XRGB8888, \
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
74 static const uint32_t intel_cursor_formats[] = {
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108 if (!connector->mst_port)
109 return connector->encoder;
111 return &connector->mst_port->mst_encoders[pipe]->base;
120 int p2_slow, p2_fast;
123 typedef struct intel_limit intel_limit_t;
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
130 intel_pch_rawclk(struct drm_device *dev)
132 struct drm_i915_private *dev_priv = dev->dev_private;
134 WARN_ON(!HAS_PCH_SPLIT(dev));
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
149 static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
286 static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
299 /* Ironlake / Sandybridge
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
304 static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
370 static const intel_limit_t intel_limits_vlv = {
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
386 static const intel_limit_t intel_limits_chv = {
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4800000, .max = 6480000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
402 static void vlv_clock(int refclk, intel_clock_t *clock)
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
413 * Returns whether any output on the specified pipe is of the specified type
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
456 limit = &intel_limits_ironlake_dual_lvds;
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
461 limit = &intel_limits_ironlake_single_lvds;
464 limit = &intel_limits_ironlake_dac;
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
512 limit = &intel_limits_i9xx_sdvo;
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
519 limit = &intel_limits_i8xx_dac;
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
550 static void chv_clock(int refclk, intel_clock_t *clock)
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
607 struct drm_device *dev = crtc->base.dev;
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
620 clock.p2 = limit->p2.p2_slow;
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
625 clock.p2 = limit->p2.p2_fast;
628 memset(best_clock, 0, sizeof(*best_clock));
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
647 clock.p != match_clock->p)
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
660 return (err != target);
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
668 struct drm_device *dev = crtc->base.dev;
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
681 clock.p2 = limit->p2.p2_slow;
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
686 clock.p2 = limit->p2.p2_fast;
689 memset(best_clock, 0, sizeof(*best_clock));
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
706 clock.p != match_clock->p)
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
719 return (err != target);
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
727 struct drm_device *dev = crtc->base.dev;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
739 clock.p2 = limit->p2.p2_slow;
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
744 clock.p2 = limit->p2.p2_fast;
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
793 if (IS_CHERRYVIEW(dev)) {
796 return calculated_clock->p > best_clock->p;
799 if (WARN_ON_ONCE(!target_freq))
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
816 return *error_ppm + 10 < best_error_ppm;
820 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
821 int target, int refclk, intel_clock_t *match_clock,
822 intel_clock_t *best_clock)
824 struct drm_device *dev = crtc->base.dev;
826 unsigned int bestppm = 1000000;
827 /* min update 19.2 MHz */
828 int max_n = min(limit->n.max, refclk / 19200);
831 target *= 5; /* fast clock */
833 memset(best_clock, 0, sizeof(*best_clock));
835 /* based on hardware requirement, prefer smaller n to precision */
836 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
840 clock.p = clock.p1 * clock.p2;
841 /* based on hardware requirement, prefer bigger m1,m2 values */
842 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
845 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
848 vlv_clock(refclk, &clock);
850 if (!intel_PLL_is_valid(dev, limit,
854 if (!vlv_PLL_is_optimal(dev, target,
872 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
876 struct drm_device *dev = crtc->base.dev;
877 unsigned int best_error_ppm;
882 memset(best_clock, 0, sizeof(*best_clock));
883 best_error_ppm = 1000000;
886 * Based on hardware doc, the n always set to 1, and m1 always
887 * set to 2. If requires to support 200Mhz refclk, we need to
888 * revisit this because n may not 1 anymore.
890 clock.n = 1, clock.m1 = 2;
891 target *= 5; /* fast clock */
893 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
894 for (clock.p2 = limit->p2.p2_fast;
895 clock.p2 >= limit->p2.p2_slow;
896 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
897 unsigned int error_ppm;
899 clock.p = clock.p1 * clock.p2;
901 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
902 clock.n) << 22, refclk * clock.m1);
904 if (m2 > INT_MAX/clock.m1)
909 chv_clock(refclk, &clock);
911 if (!intel_PLL_is_valid(dev, limit, &clock))
914 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
915 best_error_ppm, &error_ppm))
919 best_error_ppm = error_ppm;
927 bool intel_crtc_active(struct drm_crtc *crtc)
929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
931 /* Be paranoid as we can arrive here with only partial
932 * state retrieved from the hardware during setup.
934 * We can ditch the adjusted_mode.crtc_clock check as soon
935 * as Haswell has gained clock readout/fastboot support.
937 * We can ditch the crtc->primary->fb check as soon as we can
938 * properly reconstruct framebuffers.
940 * FIXME: The intel_crtc->active here should be switched to
941 * crtc->state->active once we have proper CRTC states wired up
944 return intel_crtc->active && crtc->primary->state->fb &&
945 intel_crtc->config->base.adjusted_mode.crtc_clock;
948 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
951 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
954 return intel_crtc->config->cpu_transcoder;
957 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 u32 reg = PIPEDSL(pipe);
965 line_mask = DSL_LINEMASK_GEN2;
967 line_mask = DSL_LINEMASK_GEN3;
969 line1 = I915_READ(reg) & line_mask;
971 line2 = I915_READ(reg) & line_mask;
973 return line1 == line2;
977 * intel_wait_for_pipe_off - wait for pipe to turn off
978 * @crtc: crtc whose pipe to wait for
980 * After disabling a pipe, we can't wait for vblank in the usual way,
981 * spinning on the vblank interrupt status bit, since we won't actually
982 * see an interrupt when the pipe is disabled.
985 * wait for the pipe register state bit to turn off
988 * wait for the display line value to settle (it usually
989 * ends up stopping at the start of the next frame).
992 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
994 struct drm_device *dev = crtc->base.dev;
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
997 enum pipe pipe = crtc->pipe;
999 if (INTEL_INFO(dev)->gen >= 4) {
1000 int reg = PIPECONF(cpu_transcoder);
1002 /* Wait for the Pipe State to go off */
1003 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1005 WARN(1, "pipe_off wait timed out\n");
1007 /* Wait for the display line to settle */
1008 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1009 WARN(1, "pipe_off wait timed out\n");
1014 * ibx_digital_port_connected - is the specified port connected?
1015 * @dev_priv: i915 private structure
1016 * @port: the port to test
1018 * Returns true if @port is connected, false otherwise.
1020 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021 struct intel_digital_port *port)
1025 if (HAS_PCH_IBX(dev_priv->dev)) {
1026 switch (port->port) {
1028 bit = SDE_PORTB_HOTPLUG;
1031 bit = SDE_PORTC_HOTPLUG;
1034 bit = SDE_PORTD_HOTPLUG;
1040 switch (port->port) {
1042 bit = SDE_PORTB_HOTPLUG_CPT;
1045 bit = SDE_PORTC_HOTPLUG_CPT;
1048 bit = SDE_PORTD_HOTPLUG_CPT;
1055 return I915_READ(SDEISR) & bit;
1058 static const char *state_string(bool enabled)
1060 return enabled ? "on" : "off";
1063 /* Only for pre-ILK configs */
1064 void assert_pll(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1072 val = I915_READ(reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 I915_STATE_WARN(cur_state != state,
1075 "PLL state assertion failure (expected %s, current %s)\n",
1076 state_string(state), state_string(cur_state));
1079 /* XXX: the dsi pll is shared between MIPI DSI ports */
1080 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1085 mutex_lock(&dev_priv->dpio_lock);
1086 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087 mutex_unlock(&dev_priv->dpio_lock);
1089 cur_state = val & DSI_PLL_VCO_EN;
1090 I915_STATE_WARN(cur_state != state,
1091 "DSI PLL state assertion failure (expected %s, current %s)\n",
1092 state_string(state), state_string(cur_state));
1094 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1097 struct intel_shared_dpll *
1098 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1102 if (crtc->config->shared_dpll < 0)
1105 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1109 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110 struct intel_shared_dpll *pll,
1114 struct intel_dpll_hw_state hw_state;
1117 "asserting DPLL %s with no DPLL\n", state_string(state)))
1120 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1121 I915_STATE_WARN(cur_state != state,
1122 "%s assertion failure (expected %s, current %s)\n",
1123 pll->name, state_string(state), state_string(cur_state));
1126 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1132 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1135 if (HAS_DDI(dev_priv->dev)) {
1136 /* DDI does not have a specific FDI_TX register */
1137 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1138 val = I915_READ(reg);
1139 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1141 reg = FDI_TX_CTL(pipe);
1142 val = I915_READ(reg);
1143 cur_state = !!(val & FDI_TX_ENABLE);
1145 I915_STATE_WARN(cur_state != state,
1146 "FDI TX state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1149 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1152 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153 enum pipe pipe, bool state)
1159 reg = FDI_RX_CTL(pipe);
1160 val = I915_READ(reg);
1161 cur_state = !!(val & FDI_RX_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1175 /* ILK FDI PLL is always enabled */
1176 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (HAS_DDI(dev_priv->dev))
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1195 reg = FDI_RX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1198 I915_STATE_WARN(cur_state != state,
1199 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200 state_string(state), state_string(cur_state));
1203 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1206 struct drm_device *dev = dev_priv->dev;
1209 enum pipe panel_pipe = PIPE_A;
1212 if (WARN_ON(HAS_DDI(dev)))
1215 if (HAS_PCH_SPLIT(dev)) {
1218 pp_reg = PCH_PP_CONTROL;
1219 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1221 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224 /* XXX: else fix for eDP */
1225 } else if (IS_VALLEYVIEW(dev)) {
1226 /* presumably write lock depends on pipe, not port select */
1227 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1230 pp_reg = PP_CONTROL;
1231 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232 panel_pipe = PIPE_B;
1235 val = I915_READ(pp_reg);
1236 if (!(val & PANEL_POWER_ON) ||
1237 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1240 I915_STATE_WARN(panel_pipe == pipe && locked,
1241 "panel assertion failure, pipe %c regs locked\n",
1245 static void assert_cursor(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1248 struct drm_device *dev = dev_priv->dev;
1251 if (IS_845G(dev) || IS_I865G(dev))
1252 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1254 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1256 I915_STATE_WARN(cur_state != state,
1257 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258 pipe_name(pipe), state_string(state), state_string(cur_state));
1260 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, bool state)
1269 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1272 /* if we need the pipe quirk it must be always on */
1273 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1277 if (!intel_display_power_is_enabled(dev_priv,
1278 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1281 reg = PIPECONF(cpu_transcoder);
1282 val = I915_READ(reg);
1283 cur_state = !!(val & PIPECONF_ENABLE);
1286 I915_STATE_WARN(cur_state != state,
1287 "pipe %c assertion failure (expected %s, current %s)\n",
1288 pipe_name(pipe), state_string(state), state_string(cur_state));
1291 static void assert_plane(struct drm_i915_private *dev_priv,
1292 enum plane plane, bool state)
1298 reg = DSPCNTR(plane);
1299 val = I915_READ(reg);
1300 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1301 I915_STATE_WARN(cur_state != state,
1302 "plane %c assertion failure (expected %s, current %s)\n",
1303 plane_name(plane), state_string(state), state_string(cur_state));
1306 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1309 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1312 struct drm_device *dev = dev_priv->dev;
1317 /* Primary planes are fixed to pipes on gen4+ */
1318 if (INTEL_INFO(dev)->gen >= 4) {
1319 reg = DSPCNTR(pipe);
1320 val = I915_READ(reg);
1321 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1322 "plane %c assertion failure, should be disabled but not\n",
1327 /* Need to check both planes against the pipe */
1328 for_each_pipe(dev_priv, i) {
1330 val = I915_READ(reg);
1331 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332 DISPPLANE_SEL_PIPE_SHIFT;
1333 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1334 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(i), pipe_name(pipe));
1339 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1342 struct drm_device *dev = dev_priv->dev;
1346 if (INTEL_INFO(dev)->gen >= 9) {
1347 for_each_sprite(dev_priv, pipe, sprite) {
1348 val = I915_READ(PLANE_CTL(pipe, sprite));
1349 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1350 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351 sprite, pipe_name(pipe));
1353 } else if (IS_VALLEYVIEW(dev)) {
1354 for_each_sprite(dev_priv, pipe, sprite) {
1355 reg = SPCNTR(pipe, sprite);
1356 val = I915_READ(reg);
1357 I915_STATE_WARN(val & SP_ENABLE,
1358 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1359 sprite_name(pipe, sprite), pipe_name(pipe));
1361 } else if (INTEL_INFO(dev)->gen >= 7) {
1363 val = I915_READ(reg);
1364 I915_STATE_WARN(val & SPRITE_ENABLE,
1365 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1366 plane_name(pipe), pipe_name(pipe));
1367 } else if (INTEL_INFO(dev)->gen >= 5) {
1368 reg = DVSCNTR(pipe);
1369 val = I915_READ(reg);
1370 I915_STATE_WARN(val & DVS_ENABLE,
1371 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1372 plane_name(pipe), pipe_name(pipe));
1376 static void assert_vblank_disabled(struct drm_crtc *crtc)
1378 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1379 drm_crtc_vblank_put(crtc);
1382 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1387 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1389 val = I915_READ(PCH_DREF_CONTROL);
1390 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391 DREF_SUPERSPREAD_SOURCE_MASK));
1392 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1395 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1402 reg = PCH_TRANSCONF(pipe);
1403 val = I915_READ(reg);
1404 enabled = !!(val & TRANS_ENABLE);
1405 I915_STATE_WARN(enabled,
1406 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1410 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 port_sel, u32 val)
1413 if ((val & DP_PORT_EN) == 0)
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1434 if ((val & SDVO_ENABLE) == 0)
1437 if (HAS_PCH_CPT(dev_priv->dev)) {
1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1453 if ((val & LVDS_PORT_EN) == 0)
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, int reg, u32 port_sel)
1484 u32 val = I915_READ(reg);
1485 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487 reg, pipe_name(pipe));
1489 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1490 && (val & DP_PIPEB_SELECT),
1491 "IBX PCH dp port still using transcoder B\n");
1494 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, int reg)
1497 u32 val = I915_READ(reg);
1498 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500 reg, pipe_name(pipe));
1502 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1503 && (val & SDVO_PIPE_B_SELECT),
1504 "IBX PCH hdmi port still using transcoder B\n");
1507 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1518 val = I915_READ(reg);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1524 val = I915_READ(reg);
1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1534 static void intel_init_dpio(struct drm_device *dev)
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1538 if (!IS_VALLEYVIEW(dev))
1542 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543 * CHV x1 PHY (DP/HDMI D)
1544 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1546 if (IS_CHERRYVIEW(dev)) {
1547 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1550 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1554 static void vlv_enable_pll(struct intel_crtc *crtc,
1555 const struct intel_crtc_state *pipe_config)
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int reg = DPLL(crtc->pipe);
1560 u32 dpll = pipe_config->dpll_hw_state.dpll;
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1564 /* No really, not for ILK+ */
1565 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1567 /* PLL is protected by panel, make sure we can write it */
1568 if (IS_MOBILE(dev_priv->dev))
1569 assert_panel_unlocked(dev_priv, crtc->pipe);
1571 I915_WRITE(reg, dpll);
1575 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1578 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1579 POSTING_READ(DPLL_MD(crtc->pipe));
1581 /* We do this three times for luck */
1582 I915_WRITE(reg, dpll);
1584 udelay(150); /* wait for warmup */
1585 I915_WRITE(reg, dpll);
1587 udelay(150); /* wait for warmup */
1588 I915_WRITE(reg, dpll);
1590 udelay(150); /* wait for warmup */
1593 static void chv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 int pipe = crtc->pipe;
1599 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1602 assert_pipe_disabled(dev_priv, crtc->pipe);
1604 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1606 mutex_lock(&dev_priv->dpio_lock);
1608 /* Enable back the 10bit clock to display controller */
1609 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 tmp |= DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1614 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1619 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1621 /* Check PLL is locked */
1622 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1623 DRM_ERROR("PLL %d failed to lock\n", pipe);
1625 /* not sure when this should be written */
1626 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627 POSTING_READ(DPLL_MD(pipe));
1629 mutex_unlock(&dev_priv->dpio_lock);
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1634 struct intel_crtc *crtc;
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->active &&
1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 int reg = DPLL(crtc->pipe);
1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
1651 assert_pipe_disabled(dev_priv, crtc->pipe);
1653 /* No really, not for ILK+ */
1654 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1656 /* PLL is protected by panel, make sure we can write it */
1657 if (IS_MOBILE(dev) && !IS_I830(dev))
1658 assert_panel_unlocked(dev_priv, crtc->pipe);
1660 /* Enable DVO 2x clock on both PLLs if necessary */
1661 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1663 * It appears to be important that we don't enable this
1664 * for the current pipe before otherwise configuring the
1665 * PLL. No idea how this should be handled if multiple
1666 * DVO outputs are enabled simultaneosly.
1668 dpll |= DPLL_DVO_2X_MODE;
1669 I915_WRITE(DPLL(!crtc->pipe),
1670 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1673 /* Wait for the clocks to stabilize. */
1677 if (INTEL_INFO(dev)->gen >= 4) {
1678 I915_WRITE(DPLL_MD(crtc->pipe),
1679 crtc->config->dpll_hw_state.dpll_md);
1681 /* The pixel multiplier can only be updated once the
1682 * DPLL is enabled and the clocks are stable.
1684 * So write it again.
1686 I915_WRITE(reg, dpll);
1689 /* We do this three times for luck */
1690 I915_WRITE(reg, dpll);
1692 udelay(150); /* wait for warmup */
1693 I915_WRITE(reg, dpll);
1695 udelay(150); /* wait for warmup */
1696 I915_WRITE(reg, dpll);
1698 udelay(150); /* wait for warmup */
1702 * i9xx_disable_pll - disable a PLL
1703 * @dev_priv: i915 private structure
1704 * @pipe: pipe PLL to disable
1706 * Disable the PLL for @pipe, making sure the pipe is off first.
1708 * Note! This is for pre-ILK only.
1710 static void i9xx_disable_pll(struct intel_crtc *crtc)
1712 struct drm_device *dev = crtc->base.dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 enum pipe pipe = crtc->pipe;
1716 /* Disable DVO 2x clock on both PLLs if necessary */
1718 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1719 intel_num_dvo_pipes(dev) == 1) {
1720 I915_WRITE(DPLL(PIPE_B),
1721 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722 I915_WRITE(DPLL(PIPE_A),
1723 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1726 /* Don't disable pipe or pipe PLLs if needed */
1727 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1734 I915_WRITE(DPLL(pipe), 0);
1735 POSTING_READ(DPLL(pipe));
1738 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1746 * Leave integrated clock source and reference clock enabled for pipe B.
1747 * The latter is needed for VGA hotplug / manual detection.
1750 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
1756 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1758 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
1764 /* Set PLL en = 0 */
1765 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1767 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
1771 mutex_lock(&dev_priv->dpio_lock);
1773 /* Disable 10bit clock to display controller */
1774 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775 val &= ~DPIO_DCLKP_EN;
1776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1778 /* disable left/right clock distribution */
1779 if (pipe != PIPE_B) {
1780 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1784 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1789 mutex_unlock(&dev_priv->dpio_lock);
1792 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793 struct intel_digital_port *dport)
1798 switch (dport->port) {
1800 port_mask = DPLL_PORTB_READY_MASK;
1804 port_mask = DPLL_PORTC_READY_MASK;
1808 port_mask = DPLL_PORTD_READY_MASK;
1809 dpll_reg = DPIO_PHY_STATUS;
1815 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1816 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1817 port_name(dport->port), I915_READ(dpll_reg));
1820 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1822 struct drm_device *dev = crtc->base.dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1826 if (WARN_ON(pll == NULL))
1829 WARN_ON(!pll->config.crtc_mask);
1830 if (pll->active == 0) {
1831 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1833 assert_shared_dpll_disabled(dev_priv, pll);
1835 pll->mode_set(dev_priv, pll);
1840 * intel_enable_shared_dpll - enable PCH PLL
1841 * @dev_priv: i915 private structure
1842 * @pipe: pipe PLL to enable
1844 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845 * drives the transcoder clock.
1847 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1849 struct drm_device *dev = crtc->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1853 if (WARN_ON(pll == NULL))
1856 if (WARN_ON(pll->config.crtc_mask == 0))
1859 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1860 pll->name, pll->active, pll->on,
1861 crtc->base.base.id);
1863 if (pll->active++) {
1865 assert_shared_dpll_enabled(dev_priv, pll);
1870 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1872 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1873 pll->enable(dev_priv, pll);
1877 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1879 struct drm_device *dev = crtc->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1883 /* PCH only available on ILK+ */
1884 BUG_ON(INTEL_INFO(dev)->gen < 5);
1885 if (WARN_ON(pll == NULL))
1888 if (WARN_ON(pll->config.crtc_mask == 0))
1891 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892 pll->name, pll->active, pll->on,
1893 crtc->base.base.id);
1895 if (WARN_ON(pll->active == 0)) {
1896 assert_shared_dpll_disabled(dev_priv, pll);
1900 assert_shared_dpll_enabled(dev_priv, pll);
1905 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1906 pll->disable(dev_priv, pll);
1909 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1912 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1915 struct drm_device *dev = dev_priv->dev;
1916 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1918 uint32_t reg, val, pipeconf_val;
1920 /* PCH only available on ILK+ */
1921 BUG_ON(!HAS_PCH_SPLIT(dev));
1923 /* Make sure PCH DPLL is enabled */
1924 assert_shared_dpll_enabled(dev_priv,
1925 intel_crtc_to_shared_dpll(intel_crtc));
1927 /* FDI must be feeding us bits for PCH ports */
1928 assert_fdi_tx_enabled(dev_priv, pipe);
1929 assert_fdi_rx_enabled(dev_priv, pipe);
1931 if (HAS_PCH_CPT(dev)) {
1932 /* Workaround: Set the timing override bit before enabling the
1933 * pch transcoder. */
1934 reg = TRANS_CHICKEN2(pipe);
1935 val = I915_READ(reg);
1936 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937 I915_WRITE(reg, val);
1940 reg = PCH_TRANSCONF(pipe);
1941 val = I915_READ(reg);
1942 pipeconf_val = I915_READ(PIPECONF(pipe));
1944 if (HAS_PCH_IBX(dev_priv->dev)) {
1946 * make the BPC in transcoder be consistent with
1947 * that in pipeconf reg.
1949 val &= ~PIPECONF_BPC_MASK;
1950 val |= pipeconf_val & PIPECONF_BPC_MASK;
1953 val &= ~TRANS_INTERLACE_MASK;
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1955 if (HAS_PCH_IBX(dev_priv->dev) &&
1956 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1957 val |= TRANS_LEGACY_INTERLACED_ILK;
1959 val |= TRANS_INTERLACED;
1961 val |= TRANS_PROGRESSIVE;
1963 I915_WRITE(reg, val | TRANS_ENABLE);
1964 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1965 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1968 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum transcoder cpu_transcoder)
1971 u32 val, pipeconf_val;
1973 /* PCH only available on ILK+ */
1974 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1976 /* FDI must be feeding us bits for PCH ports */
1977 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1978 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1980 /* Workaround: set timing override bit. */
1981 val = I915_READ(_TRANSA_CHICKEN2);
1982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1983 I915_WRITE(_TRANSA_CHICKEN2, val);
1986 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1988 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989 PIPECONF_INTERLACED_ILK)
1990 val |= TRANS_INTERLACED;
1992 val |= TRANS_PROGRESSIVE;
1994 I915_WRITE(LPT_TRANSCONF, val);
1995 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1996 DRM_ERROR("Failed to enable PCH transcoder\n");
1999 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2002 struct drm_device *dev = dev_priv->dev;
2005 /* FDI relies on the transcoder */
2006 assert_fdi_tx_disabled(dev_priv, pipe);
2007 assert_fdi_rx_disabled(dev_priv, pipe);
2009 /* Ports must be off as well */
2010 assert_pch_ports_disabled(dev_priv, pipe);
2012 reg = PCH_TRANSCONF(pipe);
2013 val = I915_READ(reg);
2014 val &= ~TRANS_ENABLE;
2015 I915_WRITE(reg, val);
2016 /* wait for PCH transcoder off, transcoder state */
2017 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2018 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2020 if (!HAS_PCH_IBX(dev)) {
2021 /* Workaround: Clear the timing override chicken bit again. */
2022 reg = TRANS_CHICKEN2(pipe);
2023 val = I915_READ(reg);
2024 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(reg, val);
2029 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2033 val = I915_READ(LPT_TRANSCONF);
2034 val &= ~TRANS_ENABLE;
2035 I915_WRITE(LPT_TRANSCONF, val);
2036 /* wait for PCH transcoder off, transcoder state */
2037 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2038 DRM_ERROR("Failed to disable PCH transcoder\n");
2040 /* Workaround: clear timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2047 * intel_enable_pipe - enable a pipe, asserting requirements
2048 * @crtc: crtc responsible for the pipe
2050 * Enable @crtc's pipe, making sure that various hardware specific requirements
2051 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2053 static void intel_enable_pipe(struct intel_crtc *crtc)
2055 struct drm_device *dev = crtc->base.dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 enum pipe pipe = crtc->pipe;
2058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2060 enum pipe pch_transcoder;
2064 assert_planes_disabled(dev_priv, pipe);
2065 assert_cursor_disabled(dev_priv, pipe);
2066 assert_sprites_disabled(dev_priv, pipe);
2068 if (HAS_PCH_LPT(dev_priv->dev))
2069 pch_transcoder = TRANSCODER_A;
2071 pch_transcoder = pipe;
2074 * A pipe without a PLL won't actually be able to drive bits from
2075 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2078 if (!HAS_PCH_SPLIT(dev_priv->dev))
2079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2080 assert_dsi_pll_enabled(dev_priv);
2082 assert_pll_enabled(dev_priv, pipe);
2084 if (crtc->config->has_pch_encoder) {
2085 /* if driving the PCH, we need FDI enabled */
2086 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2087 assert_fdi_tx_pll_enabled(dev_priv,
2088 (enum pipe) cpu_transcoder);
2090 /* FIXME: assert CPU port conditions for SNB+ */
2093 reg = PIPECONF(cpu_transcoder);
2094 val = I915_READ(reg);
2095 if (val & PIPECONF_ENABLE) {
2096 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2101 I915_WRITE(reg, val | PIPECONF_ENABLE);
2106 * intel_disable_pipe - disable a pipe, asserting requirements
2107 * @crtc: crtc whose pipes is to be disabled
2109 * Disable the pipe of @crtc, making sure that various hardware
2110 * specific requirements are met, if applicable, e.g. plane
2111 * disabled, panel fitter off, etc.
2113 * Will wait until the pipe has shut down before returning.
2115 static void intel_disable_pipe(struct intel_crtc *crtc)
2117 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2118 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2119 enum pipe pipe = crtc->pipe;
2124 * Make sure planes won't keep trying to pump pixels to us,
2125 * or we might hang the display.
2127 assert_planes_disabled(dev_priv, pipe);
2128 assert_cursor_disabled(dev_priv, pipe);
2129 assert_sprites_disabled(dev_priv, pipe);
2131 reg = PIPECONF(cpu_transcoder);
2132 val = I915_READ(reg);
2133 if ((val & PIPECONF_ENABLE) == 0)
2137 * Double wide has implications for planes
2138 * so best keep it disabled when not needed.
2140 if (crtc->config->double_wide)
2141 val &= ~PIPECONF_DOUBLE_WIDE;
2143 /* Don't disable pipe or pipe PLLs if needed */
2144 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2146 val &= ~PIPECONF_ENABLE;
2148 I915_WRITE(reg, val);
2149 if ((val & PIPECONF_ENABLE) == 0)
2150 intel_wait_for_pipe_off(crtc);
2154 * Plane regs are double buffered, going from enabled->disabled needs a
2155 * trigger in order to latch. The display address reg provides this.
2157 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2160 struct drm_device *dev = dev_priv->dev;
2161 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2163 I915_WRITE(reg, I915_READ(reg));
2168 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2169 * @plane: plane to be enabled
2170 * @crtc: crtc for the plane
2172 * Enable @plane on @crtc, making sure that the pipe is running first.
2174 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175 struct drm_crtc *crtc)
2177 struct drm_device *dev = plane->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2182 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2184 if (intel_crtc->primary_enabled)
2187 intel_crtc->primary_enabled = true;
2189 dev_priv->display.update_primary_plane(crtc, plane->fb,
2193 * BDW signals flip done immediately if the plane
2194 * is disabled, even if the plane enable is already
2195 * armed to occur at the next vblank :(
2197 if (IS_BROADWELL(dev))
2198 intel_wait_for_vblank(dev, intel_crtc->pipe);
2202 * intel_disable_primary_hw_plane - disable the primary hardware plane
2203 * @plane: plane to be disabled
2204 * @crtc: crtc for the plane
2206 * Disable @plane on @crtc, making sure that the pipe is running first.
2208 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209 struct drm_crtc *crtc)
2211 struct drm_device *dev = plane->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215 if (WARN_ON(!intel_crtc->active))
2218 if (!intel_crtc->primary_enabled)
2221 intel_crtc->primary_enabled = false;
2223 dev_priv->display.update_primary_plane(crtc, plane->fb,
2227 static bool need_vtd_wa(struct drm_device *dev)
2229 #ifdef CONFIG_INTEL_IOMMU
2230 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2237 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238 uint64_t fb_format_modifier)
2240 unsigned int tile_height;
2241 uint32_t pixel_bytes;
2243 switch (fb_format_modifier) {
2244 case DRM_FORMAT_MOD_NONE:
2247 case I915_FORMAT_MOD_X_TILED:
2248 tile_height = IS_GEN2(dev) ? 16 : 8;
2250 case I915_FORMAT_MOD_Y_TILED:
2253 case I915_FORMAT_MOD_Yf_TILED:
2254 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255 switch (pixel_bytes) {
2269 "128-bit pixels are not supported for display!");
2275 MISSING_CASE(fb_format_modifier);
2284 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285 uint32_t pixel_format, uint64_t fb_format_modifier)
2287 return ALIGN(height, intel_tile_height(dev, pixel_format,
2288 fb_format_modifier));
2292 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2293 const struct drm_plane_state *plane_state)
2295 struct intel_rotation_info *info = &view->rotation_info;
2296 static const struct i915_ggtt_view rotated_view =
2297 { .type = I915_GGTT_VIEW_ROTATED };
2299 *view = i915_ggtt_view_normal;
2304 if (!intel_rotation_90_or_270(plane_state->rotation))
2307 *view = rotated_view;
2309 info->height = fb->height;
2310 info->pixel_format = fb->pixel_format;
2311 info->pitch = fb->pitches[0];
2312 info->fb_modifier = fb->modifier[0];
2314 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2315 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2317 "Y or Yf tiling is needed for 90/270 rotation!\n");
2325 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2326 struct drm_framebuffer *fb,
2327 const struct drm_plane_state *plane_state,
2328 struct intel_engine_cs *pipelined)
2330 struct drm_device *dev = fb->dev;
2331 struct drm_i915_private *dev_priv = dev->dev_private;
2332 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333 struct i915_ggtt_view view;
2337 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2339 switch (fb->modifier[0]) {
2340 case DRM_FORMAT_MOD_NONE:
2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2344 alignment = 128 * 1024;
2345 else if (INTEL_INFO(dev)->gen >= 4)
2346 alignment = 4 * 1024;
2348 alignment = 64 * 1024;
2350 case I915_FORMAT_MOD_X_TILED:
2351 if (INTEL_INFO(dev)->gen >= 9)
2352 alignment = 256 * 1024;
2354 /* pin() will align the object as required by fence */
2358 case I915_FORMAT_MOD_Y_TILED:
2359 case I915_FORMAT_MOD_Yf_TILED:
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361 "Y tiling bo slipped through, driver bug!\n"))
2363 alignment = 1 * 1024 * 1024;
2366 MISSING_CASE(fb->modifier[0]);
2370 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2374 /* Note that the w/a also requires 64 PTE of padding following the
2375 * bo. We currently fill all unused PTE with the shadow page and so
2376 * we should always have valid PTE following the scanout preventing
2379 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380 alignment = 256 * 1024;
2383 * Global gtt pte registers are special registers which actually forward
2384 * writes to a chunk of system memory. Which means that there is no risk
2385 * that the register values disappear as soon as we call
2386 * intel_runtime_pm_put(), so it is correct to wrap only the
2387 * pin/unpin/fence and not more.
2389 intel_runtime_pm_get(dev_priv);
2391 dev_priv->mm.interruptible = false;
2392 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2395 goto err_interruptible;
2397 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398 * fence, whereas 965+ only requires a fence if using
2399 * framebuffer compression. For simplicity, we always install
2400 * a fence as the cost is not that onerous.
2402 ret = i915_gem_object_get_fence(obj);
2406 i915_gem_object_pin_fence(obj);
2408 dev_priv->mm.interruptible = true;
2409 intel_runtime_pm_put(dev_priv);
2413 i915_gem_object_unpin_from_display_plane(obj, &view);
2415 dev_priv->mm.interruptible = true;
2416 intel_runtime_pm_put(dev_priv);
2420 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2421 const struct drm_plane_state *plane_state)
2423 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2424 struct i915_ggtt_view view;
2427 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430 WARN_ONCE(ret, "Couldn't get view from plane state!");
2432 i915_gem_object_unpin_fence(obj);
2433 i915_gem_object_unpin_from_display_plane(obj, &view);
2436 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2437 * is assumed to be a power-of-two. */
2438 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2439 unsigned int tiling_mode,
2443 if (tiling_mode != I915_TILING_NONE) {
2444 unsigned int tile_rows, tiles;
2449 tiles = *x / (512/cpp);
2452 return tile_rows * pitch * 8 + tiles * 4096;
2454 unsigned int offset;
2456 offset = *y * pitch + *x * cpp;
2458 *x = (offset & 4095) / cpp;
2459 return offset & -4096;
2463 static int i9xx_format_to_fourcc(int format)
2466 case DISPPLANE_8BPP:
2467 return DRM_FORMAT_C8;
2468 case DISPPLANE_BGRX555:
2469 return DRM_FORMAT_XRGB1555;
2470 case DISPPLANE_BGRX565:
2471 return DRM_FORMAT_RGB565;
2473 case DISPPLANE_BGRX888:
2474 return DRM_FORMAT_XRGB8888;
2475 case DISPPLANE_RGBX888:
2476 return DRM_FORMAT_XBGR8888;
2477 case DISPPLANE_BGRX101010:
2478 return DRM_FORMAT_XRGB2101010;
2479 case DISPPLANE_RGBX101010:
2480 return DRM_FORMAT_XBGR2101010;
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2487 case PLANE_CTL_FORMAT_RGB_565:
2488 return DRM_FORMAT_RGB565;
2490 case PLANE_CTL_FORMAT_XRGB_8888:
2493 return DRM_FORMAT_ABGR8888;
2495 return DRM_FORMAT_XBGR8888;
2498 return DRM_FORMAT_ARGB8888;
2500 return DRM_FORMAT_XRGB8888;
2502 case PLANE_CTL_FORMAT_XRGB_2101010:
2504 return DRM_FORMAT_XBGR2101010;
2506 return DRM_FORMAT_XRGB2101010;
2511 intel_alloc_plane_obj(struct intel_crtc *crtc,
2512 struct intel_initial_plane_config *plane_config)
2514 struct drm_device *dev = crtc->base.dev;
2515 struct drm_i915_gem_object *obj = NULL;
2516 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2517 struct drm_framebuffer *fb = &plane_config->fb->base;
2518 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2519 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2522 size_aligned -= base_aligned;
2524 if (plane_config->size == 0)
2527 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2534 obj->tiling_mode = plane_config->tiling;
2535 if (obj->tiling_mode == I915_TILING_X)
2536 obj->stride = fb->pitches[0];
2538 mode_cmd.pixel_format = fb->pixel_format;
2539 mode_cmd.width = fb->width;
2540 mode_cmd.height = fb->height;
2541 mode_cmd.pitches[0] = fb->pitches[0];
2542 mode_cmd.modifier[0] = fb->modifier[0];
2543 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2545 mutex_lock(&dev->struct_mutex);
2547 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2549 DRM_DEBUG_KMS("intel fb init failed\n");
2553 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2554 mutex_unlock(&dev->struct_mutex);
2556 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2560 drm_gem_object_unreference(&obj->base);
2561 mutex_unlock(&dev->struct_mutex);
2565 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2567 update_state_fb(struct drm_plane *plane)
2569 if (plane->fb == plane->state->fb)
2572 if (plane->state->fb)
2573 drm_framebuffer_unreference(plane->state->fb);
2574 plane->state->fb = plane->fb;
2575 if (plane->state->fb)
2576 drm_framebuffer_reference(plane->state->fb);
2580 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2581 struct intel_initial_plane_config *plane_config)
2583 struct drm_device *dev = intel_crtc->base.dev;
2584 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct intel_crtc *i;
2587 struct drm_i915_gem_object *obj;
2589 if (!plane_config->fb)
2592 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2593 struct drm_plane *primary = intel_crtc->base.primary;
2595 primary->fb = &plane_config->fb->base;
2596 primary->state->crtc = &intel_crtc->base;
2597 update_state_fb(primary);
2602 kfree(plane_config->fb);
2605 * Failed to alloc the obj, check to see if we should share
2606 * an fb with another CRTC instead
2608 for_each_crtc(dev, c) {
2609 i = to_intel_crtc(c);
2611 if (c == &intel_crtc->base)
2617 obj = intel_fb_obj(c->primary->fb);
2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2622 struct drm_plane *primary = intel_crtc->base.primary;
2624 if (obj->tiling_mode != I915_TILING_NONE)
2625 dev_priv->preserve_bios_swizzle = true;
2627 drm_framebuffer_reference(c->primary->fb);
2628 primary->fb = c->primary->fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 update_state_fb(intel_crtc->base.primary);
2631 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2637 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2638 struct drm_framebuffer *fb,
2641 struct drm_device *dev = crtc->dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2644 struct drm_i915_gem_object *obj;
2645 int plane = intel_crtc->plane;
2646 unsigned long linear_offset;
2648 u32 reg = DSPCNTR(plane);
2651 if (!intel_crtc->primary_enabled) {
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2656 I915_WRITE(DSPADDR(plane), 0);
2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2669 dspcntr |= DISPLAY_PLANE_ENABLE;
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2678 I915_WRITE(DSPSIZE(plane),
2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
2681 I915_WRITE(DSPPOS(plane), 0);
2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2690 switch (fb->pixel_format) {
2692 dspcntr |= DISPPLANE_8BPP;
2694 case DRM_FORMAT_XRGB1555:
2695 case DRM_FORMAT_ARGB1555:
2696 dspcntr |= DISPPLANE_BGRX555;
2698 case DRM_FORMAT_RGB565:
2699 dspcntr |= DISPPLANE_BGRX565;
2701 case DRM_FORMAT_XRGB8888:
2702 case DRM_FORMAT_ARGB8888:
2703 dspcntr |= DISPPLANE_BGRX888;
2705 case DRM_FORMAT_XBGR8888:
2706 case DRM_FORMAT_ABGR8888:
2707 dspcntr |= DISPPLANE_RGBX888;
2709 case DRM_FORMAT_XRGB2101010:
2710 case DRM_FORMAT_ARGB2101010:
2711 dspcntr |= DISPPLANE_BGRX101010;
2713 case DRM_FORMAT_XBGR2101010:
2714 case DRM_FORMAT_ABGR2101010:
2715 dspcntr |= DISPPLANE_RGBX101010;
2721 if (INTEL_INFO(dev)->gen >= 4 &&
2722 obj->tiling_mode != I915_TILING_NONE)
2723 dspcntr |= DISPPLANE_TILED;
2726 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2728 linear_offset = y * fb->pitches[0] + x * pixel_size;
2730 if (INTEL_INFO(dev)->gen >= 4) {
2731 intel_crtc->dspaddr_offset =
2732 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2735 linear_offset -= intel_crtc->dspaddr_offset;
2737 intel_crtc->dspaddr_offset = linear_offset;
2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741 dspcntr |= DISPPLANE_ROTATE_180;
2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2753 I915_WRITE(reg, dspcntr);
2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2766 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 struct drm_i915_gem_object *obj;
2774 int plane = intel_crtc->plane;
2775 unsigned long linear_offset;
2777 u32 reg = DSPCNTR(plane);
2780 if (!intel_crtc->primary_enabled) {
2782 I915_WRITE(DSPSURF(plane), 0);
2787 obj = intel_fb_obj(fb);
2788 if (WARN_ON(obj == NULL))
2791 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2793 dspcntr = DISPPLANE_GAMMA_ENABLE;
2795 dspcntr |= DISPLAY_PLANE_ENABLE;
2797 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2798 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2800 switch (fb->pixel_format) {
2802 dspcntr |= DISPPLANE_8BPP;
2804 case DRM_FORMAT_RGB565:
2805 dspcntr |= DISPPLANE_BGRX565;
2807 case DRM_FORMAT_XRGB8888:
2808 case DRM_FORMAT_ARGB8888:
2809 dspcntr |= DISPPLANE_BGRX888;
2811 case DRM_FORMAT_XBGR8888:
2812 case DRM_FORMAT_ABGR8888:
2813 dspcntr |= DISPPLANE_RGBX888;
2815 case DRM_FORMAT_XRGB2101010:
2816 case DRM_FORMAT_ARGB2101010:
2817 dspcntr |= DISPPLANE_BGRX101010;
2819 case DRM_FORMAT_XBGR2101010:
2820 case DRM_FORMAT_ABGR2101010:
2821 dspcntr |= DISPPLANE_RGBX101010;
2827 if (obj->tiling_mode != I915_TILING_NONE)
2828 dspcntr |= DISPPLANE_TILED;
2830 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2831 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2833 linear_offset = y * fb->pitches[0] + x * pixel_size;
2834 intel_crtc->dspaddr_offset =
2835 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2838 linear_offset -= intel_crtc->dspaddr_offset;
2839 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2840 dspcntr |= DISPPLANE_ROTATE_180;
2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2843 x += (intel_crtc->config->pipe_src_w - 1);
2844 y += (intel_crtc->config->pipe_src_h - 1);
2846 /* Finding the last pixel of the last line of the display
2847 data and adding to linear_offset*/
2849 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2850 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2854 I915_WRITE(reg, dspcntr);
2856 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2857 I915_WRITE(DSPSURF(plane),
2858 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2859 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2860 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2862 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2863 I915_WRITE(DSPLINOFF(plane), linear_offset);
2868 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2869 uint32_t pixel_format)
2871 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2874 * The stride is either expressed as a multiple of 64 bytes
2875 * chunks for linear buffers or in number of tiles for tiled
2878 switch (fb_modifier) {
2879 case DRM_FORMAT_MOD_NONE:
2881 case I915_FORMAT_MOD_X_TILED:
2882 if (INTEL_INFO(dev)->gen == 2)
2885 case I915_FORMAT_MOD_Y_TILED:
2886 /* No need to check for old gens and Y tiling since this is
2887 * about the display engine and those will be blocked before
2891 case I915_FORMAT_MOD_Yf_TILED:
2892 if (bits_per_pixel == 8)
2897 MISSING_CASE(fb_modifier);
2902 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2903 struct drm_i915_gem_object *obj)
2905 enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2907 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908 view = I915_GGTT_VIEW_ROTATED;
2910 return i915_gem_obj_ggtt_offset_view(obj, view);
2913 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2914 struct drm_framebuffer *fb,
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 struct drm_i915_gem_object *obj;
2921 int pipe = intel_crtc->pipe;
2922 u32 plane_ctl, stride_div;
2923 unsigned long surf_addr;
2925 if (!intel_crtc->primary_enabled) {
2926 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2927 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2928 POSTING_READ(PLANE_CTL(pipe, 0));
2932 plane_ctl = PLANE_CTL_ENABLE |
2933 PLANE_CTL_PIPE_GAMMA_ENABLE |
2934 PLANE_CTL_PIPE_CSC_ENABLE;
2936 switch (fb->pixel_format) {
2937 case DRM_FORMAT_RGB565:
2938 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2940 case DRM_FORMAT_XRGB8888:
2941 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2943 case DRM_FORMAT_ARGB8888:
2944 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2945 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2947 case DRM_FORMAT_XBGR8888:
2948 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2949 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2951 case DRM_FORMAT_ABGR8888:
2952 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2953 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2954 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2956 case DRM_FORMAT_XRGB2101010:
2957 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2959 case DRM_FORMAT_XBGR2101010:
2960 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2961 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2967 switch (fb->modifier[0]) {
2968 case DRM_FORMAT_MOD_NONE:
2970 case I915_FORMAT_MOD_X_TILED:
2971 plane_ctl |= PLANE_CTL_TILED_X;
2973 case I915_FORMAT_MOD_Y_TILED:
2974 plane_ctl |= PLANE_CTL_TILED_Y;
2976 case I915_FORMAT_MOD_Yf_TILED:
2977 plane_ctl |= PLANE_CTL_TILED_YF;
2980 MISSING_CASE(fb->modifier[0]);
2983 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2984 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2985 plane_ctl |= PLANE_CTL_ROTATE_180;
2987 obj = intel_fb_obj(fb);
2988 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2990 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
2992 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2993 I915_WRITE(PLANE_POS(pipe, 0), 0);
2994 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2995 I915_WRITE(PLANE_SIZE(pipe, 0),
2996 (intel_crtc->config->pipe_src_h - 1) << 16 |
2997 (intel_crtc->config->pipe_src_w - 1));
2998 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2999 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3001 POSTING_READ(PLANE_SURF(pipe, 0));
3004 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3006 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3007 int x, int y, enum mode_set_atomic state)
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3012 if (dev_priv->display.disable_fbc)
3013 dev_priv->display.disable_fbc(dev);
3015 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3020 static void intel_complete_page_flips(struct drm_device *dev)
3022 struct drm_crtc *crtc;
3024 for_each_crtc(dev, crtc) {
3025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3026 enum plane plane = intel_crtc->plane;
3028 intel_prepare_page_flip(dev, plane);
3029 intel_finish_page_flip_plane(dev, plane);
3033 static void intel_update_primary_planes(struct drm_device *dev)
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct drm_crtc *crtc;
3038 for_each_crtc(dev, crtc) {
3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041 drm_modeset_lock(&crtc->mutex, NULL);
3043 * FIXME: Once we have proper support for primary planes (and
3044 * disabling them without disabling the entire crtc) allow again
3045 * a NULL crtc->primary->fb.
3047 if (intel_crtc->active && crtc->primary->fb)
3048 dev_priv->display.update_primary_plane(crtc,
3052 drm_modeset_unlock(&crtc->mutex);
3056 void intel_prepare_reset(struct drm_device *dev)
3058 struct drm_i915_private *dev_priv = to_i915(dev);
3059 struct intel_crtc *crtc;
3061 /* no reset support for gen2 */
3065 /* reset doesn't touch the display */
3066 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3069 drm_modeset_lock_all(dev);
3072 * Disabling the crtcs gracefully seems nicer. Also the
3073 * g33 docs say we should at least disable all the planes.
3075 for_each_intel_crtc(dev, crtc) {
3077 dev_priv->display.crtc_disable(&crtc->base);
3081 void intel_finish_reset(struct drm_device *dev)
3083 struct drm_i915_private *dev_priv = to_i915(dev);
3086 * Flips in the rings will be nuked by the reset,
3087 * so complete all pending flips so that user space
3088 * will get its events and not get stuck.
3090 intel_complete_page_flips(dev);
3092 /* no reset support for gen2 */
3096 /* reset doesn't touch the display */
3097 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3099 * Flips in the rings have been nuked by the reset,
3100 * so update the base address of all primary
3101 * planes to the the last fb to make sure we're
3102 * showing the correct fb after a reset.
3104 intel_update_primary_planes(dev);
3109 * The display has been reset as well,
3110 * so need a full re-initialization.
3112 intel_runtime_pm_disable_interrupts(dev_priv);
3113 intel_runtime_pm_enable_interrupts(dev_priv);
3115 intel_modeset_init_hw(dev);
3117 spin_lock_irq(&dev_priv->irq_lock);
3118 if (dev_priv->display.hpd_irq_setup)
3119 dev_priv->display.hpd_irq_setup(dev);
3120 spin_unlock_irq(&dev_priv->irq_lock);
3122 intel_modeset_setup_hw_state(dev, true);
3124 intel_hpd_init(dev_priv);
3126 drm_modeset_unlock_all(dev);
3130 intel_finish_fb(struct drm_framebuffer *old_fb)
3132 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3133 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3134 bool was_interruptible = dev_priv->mm.interruptible;
3137 /* Big Hammer, we also need to ensure that any pending
3138 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3139 * current scanout is retired before unpinning the old
3142 * This should only fail upon a hung GPU, in which case we
3143 * can safely continue.
3145 dev_priv->mm.interruptible = false;
3146 ret = i915_gem_object_finish_gpu(obj);
3147 dev_priv->mm.interruptible = was_interruptible;
3152 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3154 struct drm_device *dev = crtc->dev;
3155 struct drm_i915_private *dev_priv = dev->dev_private;
3156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3160 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3163 spin_lock_irq(&dev->event_lock);
3164 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3165 spin_unlock_irq(&dev->event_lock);
3170 static void intel_update_pipe_size(struct intel_crtc *crtc)
3172 struct drm_device *dev = crtc->base.dev;
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 const struct drm_display_mode *adjusted_mode;
3180 * Update pipe size and adjust fitter if needed: the reason for this is
3181 * that in compute_mode_changes we check the native mode (not the pfit
3182 * mode) to see if we can flip rather than do a full mode set. In the
3183 * fastboot case, we'll flip, but if we don't update the pipesrc and
3184 * pfit state, we'll end up with a big fb scanned out into the wrong
3187 * To fix this properly, we need to hoist the checks up into
3188 * compute_mode_changes (or above), check the actual pfit state and
3189 * whether the platform allows pfit disable with pipe active, and only
3190 * then update the pipesrc and pfit state, even on the flip path.
3193 adjusted_mode = &crtc->config->base.adjusted_mode;
3195 I915_WRITE(PIPESRC(crtc->pipe),
3196 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3197 (adjusted_mode->crtc_vdisplay - 1));
3198 if (!crtc->config->pch_pfit.enabled &&
3199 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3200 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3201 I915_WRITE(PF_CTL(crtc->pipe), 0);
3202 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3203 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3205 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3206 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3209 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3211 struct drm_device *dev = crtc->dev;
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214 int pipe = intel_crtc->pipe;
3217 /* enable normal train */
3218 reg = FDI_TX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 if (IS_IVYBRIDGE(dev)) {
3221 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3222 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3224 temp &= ~FDI_LINK_TRAIN_NONE;
3225 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3227 I915_WRITE(reg, temp);
3229 reg = FDI_RX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 if (HAS_PCH_CPT(dev)) {
3232 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3233 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3235 temp &= ~FDI_LINK_TRAIN_NONE;
3236 temp |= FDI_LINK_TRAIN_NONE;
3238 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3240 /* wait one idle pattern time */
3244 /* IVB wants error correction enabled */
3245 if (IS_IVYBRIDGE(dev))
3246 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3247 FDI_FE_ERRC_ENABLE);
3250 /* The FDI link training functions for ILK/Ibexpeak. */
3251 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3253 struct drm_device *dev = crtc->dev;
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3256 int pipe = intel_crtc->pipe;
3257 u32 reg, temp, tries;
3259 /* FDI needs bits from pipe first */
3260 assert_pipe_enabled(dev_priv, pipe);
3262 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3264 reg = FDI_RX_IMR(pipe);
3265 temp = I915_READ(reg);
3266 temp &= ~FDI_RX_SYMBOL_LOCK;
3267 temp &= ~FDI_RX_BIT_LOCK;
3268 I915_WRITE(reg, temp);
3272 /* enable CPU FDI TX and PCH FDI RX */
3273 reg = FDI_TX_CTL(pipe);
3274 temp = I915_READ(reg);
3275 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3276 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3277 temp &= ~FDI_LINK_TRAIN_NONE;
3278 temp |= FDI_LINK_TRAIN_PATTERN_1;
3279 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3281 reg = FDI_RX_CTL(pipe);
3282 temp = I915_READ(reg);
3283 temp &= ~FDI_LINK_TRAIN_NONE;
3284 temp |= FDI_LINK_TRAIN_PATTERN_1;
3285 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3290 /* Ironlake workaround, enable clock pointer after FDI enable*/
3291 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3292 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3293 FDI_RX_PHASE_SYNC_POINTER_EN);
3295 reg = FDI_RX_IIR(pipe);
3296 for (tries = 0; tries < 5; tries++) {
3297 temp = I915_READ(reg);
3298 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3300 if ((temp & FDI_RX_BIT_LOCK)) {
3301 DRM_DEBUG_KMS("FDI train 1 done.\n");
3302 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3307 DRM_ERROR("FDI train 1 fail!\n");
3310 reg = FDI_TX_CTL(pipe);
3311 temp = I915_READ(reg);
3312 temp &= ~FDI_LINK_TRAIN_NONE;
3313 temp |= FDI_LINK_TRAIN_PATTERN_2;
3314 I915_WRITE(reg, temp);
3316 reg = FDI_RX_CTL(pipe);
3317 temp = I915_READ(reg);
3318 temp &= ~FDI_LINK_TRAIN_NONE;
3319 temp |= FDI_LINK_TRAIN_PATTERN_2;
3320 I915_WRITE(reg, temp);
3325 reg = FDI_RX_IIR(pipe);
3326 for (tries = 0; tries < 5; tries++) {
3327 temp = I915_READ(reg);
3328 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330 if (temp & FDI_RX_SYMBOL_LOCK) {
3331 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3332 DRM_DEBUG_KMS("FDI train 2 done.\n");
3337 DRM_ERROR("FDI train 2 fail!\n");
3339 DRM_DEBUG_KMS("FDI train done\n");
3343 static const int snb_b_fdi_train_param[] = {
3344 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3345 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3346 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3347 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3350 /* The FDI link training functions for SNB/Cougarpoint. */
3351 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3353 struct drm_device *dev = crtc->dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356 int pipe = intel_crtc->pipe;
3357 u32 reg, temp, i, retry;
3359 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3361 reg = FDI_RX_IMR(pipe);
3362 temp = I915_READ(reg);
3363 temp &= ~FDI_RX_SYMBOL_LOCK;
3364 temp &= ~FDI_RX_BIT_LOCK;
3365 I915_WRITE(reg, temp);
3370 /* enable CPU FDI TX and PCH FDI RX */
3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3374 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_PATTERN_1;
3377 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3379 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3380 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3382 I915_WRITE(FDI_RX_MISC(pipe),
3383 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3385 reg = FDI_RX_CTL(pipe);
3386 temp = I915_READ(reg);
3387 if (HAS_PCH_CPT(dev)) {
3388 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3389 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3391 temp &= ~FDI_LINK_TRAIN_NONE;
3392 temp |= FDI_LINK_TRAIN_PATTERN_1;
3394 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3399 for (i = 0; i < 4; i++) {
3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3403 temp |= snb_b_fdi_train_param[i];
3404 I915_WRITE(reg, temp);
3409 for (retry = 0; retry < 5; retry++) {
3410 reg = FDI_RX_IIR(pipe);
3411 temp = I915_READ(reg);
3412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413 if (temp & FDI_RX_BIT_LOCK) {
3414 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3415 DRM_DEBUG_KMS("FDI train 1 done.\n");
3424 DRM_ERROR("FDI train 1 fail!\n");
3427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_LINK_TRAIN_NONE;
3430 temp |= FDI_LINK_TRAIN_PATTERN_2;
3432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3436 I915_WRITE(reg, temp);
3438 reg = FDI_RX_CTL(pipe);
3439 temp = I915_READ(reg);
3440 if (HAS_PCH_CPT(dev)) {
3441 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_2;
3447 I915_WRITE(reg, temp);
3452 for (i = 0; i < 4; i++) {
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3456 temp |= snb_b_fdi_train_param[i];
3457 I915_WRITE(reg, temp);
3462 for (retry = 0; retry < 5; retry++) {
3463 reg = FDI_RX_IIR(pipe);
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466 if (temp & FDI_RX_SYMBOL_LOCK) {
3467 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3468 DRM_DEBUG_KMS("FDI train 2 done.\n");
3477 DRM_ERROR("FDI train 2 fail!\n");
3479 DRM_DEBUG_KMS("FDI train done.\n");
3482 /* Manual link training for Ivy Bridge A0 parts */
3483 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3485 struct drm_device *dev = crtc->dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488 int pipe = intel_crtc->pipe;
3489 u32 reg, temp, i, j;
3491 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3493 reg = FDI_RX_IMR(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_RX_SYMBOL_LOCK;
3496 temp &= ~FDI_RX_BIT_LOCK;
3497 I915_WRITE(reg, temp);
3502 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3503 I915_READ(FDI_RX_IIR(pipe)));
3505 /* Try each vswing and preemphasis setting twice before moving on */
3506 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3507 /* disable first in case we need to retry */
3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3511 temp &= ~FDI_TX_ENABLE;
3512 I915_WRITE(reg, temp);
3514 reg = FDI_RX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 temp &= ~FDI_LINK_TRAIN_AUTO;
3517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518 temp &= ~FDI_RX_ENABLE;
3519 I915_WRITE(reg, temp);
3521 /* enable CPU FDI TX and PCH FDI RX */
3522 reg = FDI_TX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3525 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3526 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3528 temp |= snb_b_fdi_train_param[j/2];
3529 temp |= FDI_COMPOSITE_SYNC;
3530 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3532 I915_WRITE(FDI_RX_MISC(pipe),
3533 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3535 reg = FDI_RX_CTL(pipe);
3536 temp = I915_READ(reg);
3537 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3538 temp |= FDI_COMPOSITE_SYNC;
3539 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3542 udelay(1); /* should be 0.5us */
3544 for (i = 0; i < 4; i++) {
3545 reg = FDI_RX_IIR(pipe);
3546 temp = I915_READ(reg);
3547 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3549 if (temp & FDI_RX_BIT_LOCK ||
3550 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3551 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3556 udelay(1); /* should be 0.5us */
3559 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3564 reg = FDI_TX_CTL(pipe);
3565 temp = I915_READ(reg);
3566 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3567 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3568 I915_WRITE(reg, temp);
3570 reg = FDI_RX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3574 I915_WRITE(reg, temp);
3577 udelay(2); /* should be 1.5us */
3579 for (i = 0; i < 4; i++) {
3580 reg = FDI_RX_IIR(pipe);
3581 temp = I915_READ(reg);
3582 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3584 if (temp & FDI_RX_SYMBOL_LOCK ||
3585 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3586 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3587 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3591 udelay(2); /* should be 1.5us */
3594 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3598 DRM_DEBUG_KMS("FDI train done.\n");
3601 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3603 struct drm_device *dev = intel_crtc->base.dev;
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3605 int pipe = intel_crtc->pipe;
3609 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3610 reg = FDI_RX_CTL(pipe);
3611 temp = I915_READ(reg);
3612 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3613 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3614 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3615 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3620 /* Switch from Rawclk to PCDclk */
3621 temp = I915_READ(reg);
3622 I915_WRITE(reg, temp | FDI_PCDCLK);
3627 /* Enable CPU FDI TX PLL, always on for Ironlake */
3628 reg = FDI_TX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3631 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3638 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3640 struct drm_device *dev = intel_crtc->base.dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 int pipe = intel_crtc->pipe;
3645 /* Switch from PCDclk to Rawclk */
3646 reg = FDI_RX_CTL(pipe);
3647 temp = I915_READ(reg);
3648 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3650 /* Disable CPU FDI TX PLL */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3658 reg = FDI_RX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3662 /* Wait for the clocks to turn off. */
3667 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3669 struct drm_device *dev = crtc->dev;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3672 int pipe = intel_crtc->pipe;
3675 /* disable CPU FDI tx and PCH FDI rx */
3676 reg = FDI_TX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3681 reg = FDI_RX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~(0x7 << 16);
3684 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3685 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3690 /* Ironlake workaround, disable clock pointer after downing FDI */
3691 if (HAS_PCH_IBX(dev))
3692 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3694 /* still set train pattern 1 */
3695 reg = FDI_TX_CTL(pipe);
3696 temp = I915_READ(reg);
3697 temp &= ~FDI_LINK_TRAIN_NONE;
3698 temp |= FDI_LINK_TRAIN_PATTERN_1;
3699 I915_WRITE(reg, temp);
3701 reg = FDI_RX_CTL(pipe);
3702 temp = I915_READ(reg);
3703 if (HAS_PCH_CPT(dev)) {
3704 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3705 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3707 temp &= ~FDI_LINK_TRAIN_NONE;
3708 temp |= FDI_LINK_TRAIN_PATTERN_1;
3710 /* BPC in FDI rx is consistent with that in PIPECONF */
3711 temp &= ~(0x07 << 16);
3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3713 I915_WRITE(reg, temp);
3719 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3721 struct intel_crtc *crtc;
3723 /* Note that we don't need to be called with mode_config.lock here
3724 * as our list of CRTC objects is static for the lifetime of the
3725 * device and so cannot disappear as we iterate. Similarly, we can
3726 * happily treat the predicates as racy, atomic checks as userspace
3727 * cannot claim and pin a new fb without at least acquring the
3728 * struct_mutex and so serialising with us.
3730 for_each_intel_crtc(dev, crtc) {
3731 if (atomic_read(&crtc->unpin_work_count) == 0)
3734 if (crtc->unpin_work)
3735 intel_wait_for_vblank(dev, crtc->pipe);
3743 static void page_flip_completed(struct intel_crtc *intel_crtc)
3745 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3746 struct intel_unpin_work *work = intel_crtc->unpin_work;
3748 /* ensure that the unpin work is consistent wrt ->pending. */
3750 intel_crtc->unpin_work = NULL;
3753 drm_send_vblank_event(intel_crtc->base.dev,
3757 drm_crtc_vblank_put(&intel_crtc->base);
3759 wake_up_all(&dev_priv->pending_flip_queue);
3760 queue_work(dev_priv->wq, &work->work);
3762 trace_i915_flip_complete(intel_crtc->plane,
3763 work->pending_flip_obj);
3766 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3768 struct drm_device *dev = crtc->dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3771 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3772 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3773 !intel_crtc_has_pending_flip(crtc),
3775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777 spin_lock_irq(&dev->event_lock);
3778 if (intel_crtc->unpin_work) {
3779 WARN_ONCE(1, "Removing stuck page flip\n");
3780 page_flip_completed(intel_crtc);
3782 spin_unlock_irq(&dev->event_lock);
3785 if (crtc->primary->fb) {
3786 mutex_lock(&dev->struct_mutex);
3787 intel_finish_fb(crtc->primary->fb);
3788 mutex_unlock(&dev->struct_mutex);
3792 /* Program iCLKIP clock to the desired frequency */
3793 static void lpt_program_iclkip(struct drm_crtc *crtc)
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3798 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3801 mutex_lock(&dev_priv->dpio_lock);
3803 /* It is necessary to ungate the pixclk gate prior to programming
3804 * the divisors, and gate it back when it is done.
3806 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3808 /* Disable SSCCTL */
3809 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3810 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3814 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3815 if (clock == 20000) {
3820 /* The iCLK virtual clock root frequency is in MHz,
3821 * but the adjusted_mode->crtc_clock in in KHz. To get the
3822 * divisors, it is necessary to divide one by another, so we
3823 * convert the virtual clock precision to KHz here for higher
3826 u32 iclk_virtual_root_freq = 172800 * 1000;
3827 u32 iclk_pi_range = 64;
3828 u32 desired_divisor, msb_divisor_value, pi_value;
3830 desired_divisor = (iclk_virtual_root_freq / clock);
3831 msb_divisor_value = desired_divisor / iclk_pi_range;
3832 pi_value = desired_divisor % iclk_pi_range;
3835 divsel = msb_divisor_value - 2;
3836 phaseinc = pi_value;
3839 /* This should not happen with any sane values */
3840 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3841 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3842 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3843 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3845 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3852 /* Program SSCDIVINTPHASE6 */
3853 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3854 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3855 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3856 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3857 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3858 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3859 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3860 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3862 /* Program SSCAUXDIV */
3863 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3864 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3865 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3866 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3868 /* Enable modulator and associated divider */
3869 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3870 temp &= ~SBI_SSCCTL_DISABLE;
3871 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3873 /* Wait for initialization time */
3876 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3878 mutex_unlock(&dev_priv->dpio_lock);
3881 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3882 enum pipe pch_transcoder)
3884 struct drm_device *dev = crtc->base.dev;
3885 struct drm_i915_private *dev_priv = dev->dev_private;
3886 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3888 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3889 I915_READ(HTOTAL(cpu_transcoder)));
3890 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3891 I915_READ(HBLANK(cpu_transcoder)));
3892 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3893 I915_READ(HSYNC(cpu_transcoder)));
3895 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3896 I915_READ(VTOTAL(cpu_transcoder)));
3897 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3898 I915_READ(VBLANK(cpu_transcoder)));
3899 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3900 I915_READ(VSYNC(cpu_transcoder)));
3901 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3902 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3905 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3910 temp = I915_READ(SOUTH_CHICKEN1);
3911 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3914 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3915 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3917 temp &= ~FDI_BC_BIFURCATION_SELECT;
3919 temp |= FDI_BC_BIFURCATION_SELECT;
3921 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3922 I915_WRITE(SOUTH_CHICKEN1, temp);
3923 POSTING_READ(SOUTH_CHICKEN1);
3926 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3928 struct drm_device *dev = intel_crtc->base.dev;
3930 switch (intel_crtc->pipe) {
3934 if (intel_crtc->config->fdi_lanes > 2)
3935 cpt_set_fdi_bc_bifurcation(dev, false);
3937 cpt_set_fdi_bc_bifurcation(dev, true);
3941 cpt_set_fdi_bc_bifurcation(dev, true);
3950 * Enable PCH resources required for PCH ports:
3952 * - FDI training & RX/TX
3953 * - update transcoder timings
3954 * - DP transcoding bits
3957 static void ironlake_pch_enable(struct drm_crtc *crtc)
3959 struct drm_device *dev = crtc->dev;
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3962 int pipe = intel_crtc->pipe;
3965 assert_pch_transcoder_disabled(dev_priv, pipe);
3967 if (IS_IVYBRIDGE(dev))
3968 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3970 /* Write the TU size bits before fdi link training, so that error
3971 * detection works. */
3972 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3973 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3975 /* For PCH output, training FDI link */
3976 dev_priv->display.fdi_link_train(crtc);
3978 /* We need to program the right clock selection before writing the pixel
3979 * mutliplier into the DPLL. */
3980 if (HAS_PCH_CPT(dev)) {
3983 temp = I915_READ(PCH_DPLL_SEL);
3984 temp |= TRANS_DPLL_ENABLE(pipe);
3985 sel = TRANS_DPLLB_SEL(pipe);
3986 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3990 I915_WRITE(PCH_DPLL_SEL, temp);
3993 /* XXX: pch pll's can be enabled any time before we enable the PCH
3994 * transcoder, and we actually should do this to not upset any PCH
3995 * transcoder that already use the clock when we share it.
3997 * Note that enable_shared_dpll tries to do the right thing, but
3998 * get_shared_dpll unconditionally resets the pll - we need that to have
3999 * the right LVDS enable sequence. */
4000 intel_enable_shared_dpll(intel_crtc);
4002 /* set transcoder timing, panel must allow it */
4003 assert_panel_unlocked(dev_priv, pipe);
4004 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4006 intel_fdi_normal_train(crtc);
4008 /* For PCH DP, enable TRANS_DP_CTL */
4009 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4010 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4011 reg = TRANS_DP_CTL(pipe);
4012 temp = I915_READ(reg);
4013 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4014 TRANS_DP_SYNC_MASK |
4016 temp |= (TRANS_DP_OUTPUT_ENABLE |
4017 TRANS_DP_ENH_FRAMING);
4018 temp |= bpc << 9; /* same format but at 11:9 */
4020 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4021 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4022 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4023 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4025 switch (intel_trans_dp_port_sel(crtc)) {
4027 temp |= TRANS_DP_PORT_SEL_B;
4030 temp |= TRANS_DP_PORT_SEL_C;
4033 temp |= TRANS_DP_PORT_SEL_D;
4039 I915_WRITE(reg, temp);
4042 ironlake_enable_pch_transcoder(dev_priv, pipe);
4045 static void lpt_pch_enable(struct drm_crtc *crtc)
4047 struct drm_device *dev = crtc->dev;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4050 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4052 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4054 lpt_program_iclkip(crtc);
4056 /* Set transcoder timing. */
4057 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4059 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4062 void intel_put_shared_dpll(struct intel_crtc *crtc)
4064 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4069 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4070 WARN(1, "bad %s crtc mask\n", pll->name);
4074 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4075 if (pll->config.crtc_mask == 0) {
4077 WARN_ON(pll->active);
4080 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4083 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4084 struct intel_crtc_state *crtc_state)
4086 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4087 struct intel_shared_dpll *pll;
4088 enum intel_dpll_id i;
4090 if (HAS_PCH_IBX(dev_priv->dev)) {
4091 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4092 i = (enum intel_dpll_id) crtc->pipe;
4093 pll = &dev_priv->shared_dplls[i];
4095 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4096 crtc->base.base.id, pll->name);
4098 WARN_ON(pll->new_config->crtc_mask);
4103 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4104 pll = &dev_priv->shared_dplls[i];
4106 /* Only want to check enabled timings first */
4107 if (pll->new_config->crtc_mask == 0)
4110 if (memcmp(&crtc_state->dpll_hw_state,
4111 &pll->new_config->hw_state,
4112 sizeof(pll->new_config->hw_state)) == 0) {
4113 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4114 crtc->base.base.id, pll->name,
4115 pll->new_config->crtc_mask,
4121 /* Ok no matching timings, maybe there's a free one? */
4122 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4123 pll = &dev_priv->shared_dplls[i];
4124 if (pll->new_config->crtc_mask == 0) {
4125 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4126 crtc->base.base.id, pll->name);
4134 if (pll->new_config->crtc_mask == 0)
4135 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4137 crtc_state->shared_dpll = i;
4138 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4139 pipe_name(crtc->pipe));
4141 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4147 * intel_shared_dpll_start_config - start a new PLL staged config
4148 * @dev_priv: DRM device
4149 * @clear_pipes: mask of pipes that will have their PLLs freed
4151 * Starts a new PLL staged config, copying the current config but
4152 * releasing the references of pipes specified in clear_pipes.
4154 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4155 unsigned clear_pipes)
4157 struct intel_shared_dpll *pll;
4158 enum intel_dpll_id i;
4160 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4161 pll = &dev_priv->shared_dplls[i];
4163 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4165 if (!pll->new_config)
4168 pll->new_config->crtc_mask &= ~clear_pipes;
4175 pll = &dev_priv->shared_dplls[i];
4176 kfree(pll->new_config);
4177 pll->new_config = NULL;
4183 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4185 struct intel_shared_dpll *pll;
4186 enum intel_dpll_id i;
4188 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4189 pll = &dev_priv->shared_dplls[i];
4191 WARN_ON(pll->new_config == &pll->config);
4193 pll->config = *pll->new_config;
4194 kfree(pll->new_config);
4195 pll->new_config = NULL;
4199 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4201 struct intel_shared_dpll *pll;
4202 enum intel_dpll_id i;
4204 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4205 pll = &dev_priv->shared_dplls[i];
4207 WARN_ON(pll->new_config == &pll->config);
4209 kfree(pll->new_config);
4210 pll->new_config = NULL;
4214 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 int dslreg = PIPEDSL(pipe);
4220 temp = I915_READ(dslreg);
4222 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4223 if (wait_for(I915_READ(dslreg) != temp, 5))
4224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4228 static void skylake_pfit_enable(struct intel_crtc *crtc)
4230 struct drm_device *dev = crtc->base.dev;
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 int pipe = crtc->pipe;
4234 if (crtc->config->pch_pfit.enabled) {
4235 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4236 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4237 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4241 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4243 struct drm_device *dev = crtc->base.dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 int pipe = crtc->pipe;
4247 if (crtc->config->pch_pfit.enabled) {
4248 /* Force use of hard-coded filter coefficients
4249 * as some pre-programmed values are broken,
4252 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4253 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4254 PF_PIPE_SEL_IVB(pipe));
4256 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4257 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4258 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4262 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4264 struct drm_device *dev = crtc->dev;
4265 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4266 struct drm_plane *plane;
4267 struct intel_plane *intel_plane;
4269 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4270 intel_plane = to_intel_plane(plane);
4271 if (intel_plane->pipe == pipe)
4272 intel_plane_restore(&intel_plane->base);
4277 * Disable a plane internally without actually modifying the plane's state.
4278 * This will allow us to easily restore the plane later by just reprogramming
4281 static void disable_plane_internal(struct drm_plane *plane)
4283 struct intel_plane *intel_plane = to_intel_plane(plane);
4284 struct drm_plane_state *state =
4285 plane->funcs->atomic_duplicate_state(plane);
4286 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4288 intel_state->visible = false;
4289 intel_plane->commit_plane(plane, intel_state);
4291 intel_plane_destroy_state(plane, state);
4294 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4296 struct drm_device *dev = crtc->dev;
4297 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4298 struct drm_plane *plane;
4299 struct intel_plane *intel_plane;
4301 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4302 intel_plane = to_intel_plane(plane);
4303 if (plane->fb && intel_plane->pipe == pipe)
4304 disable_plane_internal(plane);
4308 void hsw_enable_ips(struct intel_crtc *crtc)
4310 struct drm_device *dev = crtc->base.dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4313 if (!crtc->config->ips_enabled)
4316 /* We can only enable IPS after we enable a plane and wait for a vblank */
4317 intel_wait_for_vblank(dev, crtc->pipe);
4319 assert_plane_enabled(dev_priv, crtc->plane);
4320 if (IS_BROADWELL(dev)) {
4321 mutex_lock(&dev_priv->rps.hw_lock);
4322 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4323 mutex_unlock(&dev_priv->rps.hw_lock);
4324 /* Quoting Art Runyan: "its not safe to expect any particular
4325 * value in IPS_CTL bit 31 after enabling IPS through the
4326 * mailbox." Moreover, the mailbox may return a bogus state,
4327 * so we need to just enable it and continue on.
4330 I915_WRITE(IPS_CTL, IPS_ENABLE);
4331 /* The bit only becomes 1 in the next vblank, so this wait here
4332 * is essentially intel_wait_for_vblank. If we don't have this
4333 * and don't wait for vblanks until the end of crtc_enable, then
4334 * the HW state readout code will complain that the expected
4335 * IPS_CTL value is not the one we read. */
4336 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4337 DRM_ERROR("Timed out waiting for IPS enable\n");
4341 void hsw_disable_ips(struct intel_crtc *crtc)
4343 struct drm_device *dev = crtc->base.dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4346 if (!crtc->config->ips_enabled)
4349 assert_plane_enabled(dev_priv, crtc->plane);
4350 if (IS_BROADWELL(dev)) {
4351 mutex_lock(&dev_priv->rps.hw_lock);
4352 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4353 mutex_unlock(&dev_priv->rps.hw_lock);
4354 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4355 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4356 DRM_ERROR("Timed out waiting for IPS disable\n");
4358 I915_WRITE(IPS_CTL, 0);
4359 POSTING_READ(IPS_CTL);
4362 /* We need to wait for a vblank before we can disable the plane. */
4363 intel_wait_for_vblank(dev, crtc->pipe);
4366 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4367 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4369 struct drm_device *dev = crtc->dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372 enum pipe pipe = intel_crtc->pipe;
4373 int palreg = PALETTE(pipe);
4375 bool reenable_ips = false;
4377 /* The clocks have to be on to load the palette. */
4378 if (!crtc->state->enable || !intel_crtc->active)
4381 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4382 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4383 assert_dsi_pll_enabled(dev_priv);
4385 assert_pll_enabled(dev_priv, pipe);
4388 /* use legacy palette for Ironlake */
4389 if (!HAS_GMCH_DISPLAY(dev))
4390 palreg = LGC_PALETTE(pipe);
4392 /* Workaround : Do not read or write the pipe palette/gamma data while
4393 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4395 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4396 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4397 GAMMA_MODE_MODE_SPLIT)) {
4398 hsw_disable_ips(intel_crtc);
4399 reenable_ips = true;
4402 for (i = 0; i < 256; i++) {
4403 I915_WRITE(palreg + 4 * i,
4404 (intel_crtc->lut_r[i] << 16) |
4405 (intel_crtc->lut_g[i] << 8) |
4406 intel_crtc->lut_b[i]);
4410 hsw_enable_ips(intel_crtc);
4413 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4415 if (!enable && intel_crtc->overlay) {
4416 struct drm_device *dev = intel_crtc->base.dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4419 mutex_lock(&dev->struct_mutex);
4420 dev_priv->mm.interruptible = false;
4421 (void) intel_overlay_switch_off(intel_crtc->overlay);
4422 dev_priv->mm.interruptible = true;
4423 mutex_unlock(&dev->struct_mutex);
4426 /* Let userspace switch the overlay on again. In most cases userspace
4427 * has to recompute where to put it anyway.
4431 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4433 struct drm_device *dev = crtc->dev;
4434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435 int pipe = intel_crtc->pipe;
4437 intel_enable_primary_hw_plane(crtc->primary, crtc);
4438 intel_enable_sprite_planes(crtc);
4439 intel_crtc_update_cursor(crtc, true);
4440 intel_crtc_dpms_overlay(intel_crtc, true);
4442 hsw_enable_ips(intel_crtc);
4444 mutex_lock(&dev->struct_mutex);
4445 intel_fbc_update(dev);
4446 mutex_unlock(&dev->struct_mutex);
4449 * FIXME: Once we grow proper nuclear flip support out of this we need
4450 * to compute the mask of flip planes precisely. For the time being
4451 * consider this a flip from a NULL plane.
4453 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4456 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4458 struct drm_device *dev = crtc->dev;
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461 int pipe = intel_crtc->pipe;
4463 intel_crtc_wait_for_pending_flips(crtc);
4465 if (dev_priv->fbc.crtc == intel_crtc)
4466 intel_fbc_disable(dev);
4468 hsw_disable_ips(intel_crtc);
4470 intel_crtc_dpms_overlay(intel_crtc, false);
4471 intel_crtc_update_cursor(crtc, false);
4472 intel_disable_sprite_planes(crtc);
4473 intel_disable_primary_hw_plane(crtc->primary, crtc);
4476 * FIXME: Once we grow proper nuclear flip support out of this we need
4477 * to compute the mask of flip planes precisely. For the time being
4478 * consider this a flip to a NULL plane.
4480 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4483 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4485 struct drm_device *dev = crtc->dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4488 struct intel_encoder *encoder;
4489 int pipe = intel_crtc->pipe;
4491 WARN_ON(!crtc->state->enable);
4493 if (intel_crtc->active)
4496 if (intel_crtc->config->has_pch_encoder)
4497 intel_prepare_shared_dpll(intel_crtc);
4499 if (intel_crtc->config->has_dp_encoder)
4500 intel_dp_set_m_n(intel_crtc, M1_N1);
4502 intel_set_pipe_timings(intel_crtc);
4504 if (intel_crtc->config->has_pch_encoder) {
4505 intel_cpu_transcoder_set_m_n(intel_crtc,
4506 &intel_crtc->config->fdi_m_n, NULL);
4509 ironlake_set_pipeconf(crtc);
4511 intel_crtc->active = true;
4513 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4514 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4516 for_each_encoder_on_crtc(dev, crtc, encoder)
4517 if (encoder->pre_enable)
4518 encoder->pre_enable(encoder);
4520 if (intel_crtc->config->has_pch_encoder) {
4521 /* Note: FDI PLL enabling _must_ be done before we enable the
4522 * cpu pipes, hence this is separate from all the other fdi/pch
4524 ironlake_fdi_pll_enable(intel_crtc);
4526 assert_fdi_tx_disabled(dev_priv, pipe);
4527 assert_fdi_rx_disabled(dev_priv, pipe);
4530 ironlake_pfit_enable(intel_crtc);
4533 * On ILK+ LUT must be loaded before the pipe is running but with
4536 intel_crtc_load_lut(crtc);
4538 intel_update_watermarks(crtc);
4539 intel_enable_pipe(intel_crtc);
4541 if (intel_crtc->config->has_pch_encoder)
4542 ironlake_pch_enable(crtc);
4544 assert_vblank_disabled(crtc);
4545 drm_crtc_vblank_on(crtc);
4547 for_each_encoder_on_crtc(dev, crtc, encoder)
4548 encoder->enable(encoder);
4550 if (HAS_PCH_CPT(dev))
4551 cpt_verify_modeset(dev, intel_crtc->pipe);
4553 intel_crtc_enable_planes(crtc);
4556 /* IPS only exists on ULT machines and is tied to pipe A. */
4557 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4559 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4563 * This implements the workaround described in the "notes" section of the mode
4564 * set sequence documentation. When going from no pipes or single pipe to
4565 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4566 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4568 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4570 struct drm_device *dev = crtc->base.dev;
4571 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4573 /* We want to get the other_active_crtc only if there's only 1 other
4575 for_each_intel_crtc(dev, crtc_it) {
4576 if (!crtc_it->active || crtc_it == crtc)
4579 if (other_active_crtc)
4582 other_active_crtc = crtc_it;
4584 if (!other_active_crtc)
4587 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4588 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4591 static void haswell_crtc_enable(struct drm_crtc *crtc)
4593 struct drm_device *dev = crtc->dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596 struct intel_encoder *encoder;
4597 int pipe = intel_crtc->pipe;
4599 WARN_ON(!crtc->state->enable);
4601 if (intel_crtc->active)
4604 if (intel_crtc_to_shared_dpll(intel_crtc))
4605 intel_enable_shared_dpll(intel_crtc);
4607 if (intel_crtc->config->has_dp_encoder)
4608 intel_dp_set_m_n(intel_crtc, M1_N1);
4610 intel_set_pipe_timings(intel_crtc);
4612 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4613 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4614 intel_crtc->config->pixel_multiplier - 1);
4617 if (intel_crtc->config->has_pch_encoder) {
4618 intel_cpu_transcoder_set_m_n(intel_crtc,
4619 &intel_crtc->config->fdi_m_n, NULL);
4622 haswell_set_pipeconf(crtc);
4624 intel_set_pipe_csc(crtc);
4626 intel_crtc->active = true;
4628 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4629 for_each_encoder_on_crtc(dev, crtc, encoder)
4630 if (encoder->pre_enable)
4631 encoder->pre_enable(encoder);
4633 if (intel_crtc->config->has_pch_encoder) {
4634 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4636 dev_priv->display.fdi_link_train(crtc);
4639 intel_ddi_enable_pipe_clock(intel_crtc);
4641 if (IS_SKYLAKE(dev))
4642 skylake_pfit_enable(intel_crtc);
4644 ironlake_pfit_enable(intel_crtc);
4647 * On ILK+ LUT must be loaded before the pipe is running but with
4650 intel_crtc_load_lut(crtc);
4652 intel_ddi_set_pipe_settings(crtc);
4653 intel_ddi_enable_transcoder_func(crtc);
4655 intel_update_watermarks(crtc);
4656 intel_enable_pipe(intel_crtc);
4658 if (intel_crtc->config->has_pch_encoder)
4659 lpt_pch_enable(crtc);
4661 if (intel_crtc->config->dp_encoder_is_mst)
4662 intel_ddi_set_vc_payload_alloc(crtc, true);
4664 assert_vblank_disabled(crtc);
4665 drm_crtc_vblank_on(crtc);
4667 for_each_encoder_on_crtc(dev, crtc, encoder) {
4668 encoder->enable(encoder);
4669 intel_opregion_notify_encoder(encoder, true);
4672 /* If we change the relative order between pipe/planes enabling, we need
4673 * to change the workaround. */
4674 haswell_mode_set_planes_workaround(intel_crtc);
4675 intel_crtc_enable_planes(crtc);
4678 static void skylake_pfit_disable(struct intel_crtc *crtc)
4680 struct drm_device *dev = crtc->base.dev;
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4682 int pipe = crtc->pipe;
4684 /* To avoid upsetting the power well on haswell only disable the pfit if
4685 * it's in use. The hw state code will make sure we get this right. */
4686 if (crtc->config->pch_pfit.enabled) {
4687 I915_WRITE(PS_CTL(pipe), 0);
4688 I915_WRITE(PS_WIN_POS(pipe), 0);
4689 I915_WRITE(PS_WIN_SZ(pipe), 0);
4693 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4695 struct drm_device *dev = crtc->base.dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 int pipe = crtc->pipe;
4699 /* To avoid upsetting the power well on haswell only disable the pfit if
4700 * it's in use. The hw state code will make sure we get this right. */
4701 if (crtc->config->pch_pfit.enabled) {
4702 I915_WRITE(PF_CTL(pipe), 0);
4703 I915_WRITE(PF_WIN_POS(pipe), 0);
4704 I915_WRITE(PF_WIN_SZ(pipe), 0);
4708 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4710 struct drm_device *dev = crtc->dev;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct intel_encoder *encoder;
4714 int pipe = intel_crtc->pipe;
4717 if (!intel_crtc->active)
4720 intel_crtc_disable_planes(crtc);
4722 for_each_encoder_on_crtc(dev, crtc, encoder)
4723 encoder->disable(encoder);
4725 drm_crtc_vblank_off(crtc);
4726 assert_vblank_disabled(crtc);
4728 if (intel_crtc->config->has_pch_encoder)
4729 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4731 intel_disable_pipe(intel_crtc);
4733 ironlake_pfit_disable(intel_crtc);
4735 for_each_encoder_on_crtc(dev, crtc, encoder)
4736 if (encoder->post_disable)
4737 encoder->post_disable(encoder);
4739 if (intel_crtc->config->has_pch_encoder) {
4740 ironlake_fdi_disable(crtc);
4742 ironlake_disable_pch_transcoder(dev_priv, pipe);
4744 if (HAS_PCH_CPT(dev)) {
4745 /* disable TRANS_DP_CTL */
4746 reg = TRANS_DP_CTL(pipe);
4747 temp = I915_READ(reg);
4748 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4749 TRANS_DP_PORT_SEL_MASK);
4750 temp |= TRANS_DP_PORT_SEL_NONE;
4751 I915_WRITE(reg, temp);
4753 /* disable DPLL_SEL */
4754 temp = I915_READ(PCH_DPLL_SEL);
4755 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4756 I915_WRITE(PCH_DPLL_SEL, temp);
4759 /* disable PCH DPLL */
4760 intel_disable_shared_dpll(intel_crtc);
4762 ironlake_fdi_pll_disable(intel_crtc);
4765 intel_crtc->active = false;
4766 intel_update_watermarks(crtc);
4768 mutex_lock(&dev->struct_mutex);
4769 intel_fbc_update(dev);
4770 mutex_unlock(&dev->struct_mutex);
4773 static void haswell_crtc_disable(struct drm_crtc *crtc)
4775 struct drm_device *dev = crtc->dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778 struct intel_encoder *encoder;
4779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4781 if (!intel_crtc->active)
4784 intel_crtc_disable_planes(crtc);
4786 for_each_encoder_on_crtc(dev, crtc, encoder) {
4787 intel_opregion_notify_encoder(encoder, false);
4788 encoder->disable(encoder);
4791 drm_crtc_vblank_off(crtc);
4792 assert_vblank_disabled(crtc);
4794 if (intel_crtc->config->has_pch_encoder)
4795 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4797 intel_disable_pipe(intel_crtc);
4799 if (intel_crtc->config->dp_encoder_is_mst)
4800 intel_ddi_set_vc_payload_alloc(crtc, false);
4802 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4804 if (IS_SKYLAKE(dev))
4805 skylake_pfit_disable(intel_crtc);
4807 ironlake_pfit_disable(intel_crtc);
4809 intel_ddi_disable_pipe_clock(intel_crtc);
4811 if (intel_crtc->config->has_pch_encoder) {
4812 lpt_disable_pch_transcoder(dev_priv);
4813 intel_ddi_fdi_disable(crtc);
4816 for_each_encoder_on_crtc(dev, crtc, encoder)
4817 if (encoder->post_disable)
4818 encoder->post_disable(encoder);
4820 intel_crtc->active = false;
4821 intel_update_watermarks(crtc);
4823 mutex_lock(&dev->struct_mutex);
4824 intel_fbc_update(dev);
4825 mutex_unlock(&dev->struct_mutex);
4827 if (intel_crtc_to_shared_dpll(intel_crtc))
4828 intel_disable_shared_dpll(intel_crtc);
4831 static void ironlake_crtc_off(struct drm_crtc *crtc)
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 intel_put_shared_dpll(intel_crtc);
4838 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4840 struct drm_device *dev = crtc->base.dev;
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 struct intel_crtc_state *pipe_config = crtc->config;
4844 if (!pipe_config->gmch_pfit.control)
4848 * The panel fitter should only be adjusted whilst the pipe is disabled,
4849 * according to register description and PRM.
4851 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4852 assert_pipe_disabled(dev_priv, crtc->pipe);
4854 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4855 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4857 /* Border color in case we don't scale up to the full screen. Black by
4858 * default, change to something else for debugging. */
4859 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4862 static enum intel_display_power_domain port_to_power_domain(enum port port)
4866 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4868 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4870 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4872 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4875 return POWER_DOMAIN_PORT_OTHER;
4879 #define for_each_power_domain(domain, mask) \
4880 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4881 if ((1 << (domain)) & (mask))
4883 enum intel_display_power_domain
4884 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4886 struct drm_device *dev = intel_encoder->base.dev;
4887 struct intel_digital_port *intel_dig_port;
4889 switch (intel_encoder->type) {
4890 case INTEL_OUTPUT_UNKNOWN:
4891 /* Only DDI platforms should ever use this output type */
4892 WARN_ON_ONCE(!HAS_DDI(dev));
4893 case INTEL_OUTPUT_DISPLAYPORT:
4894 case INTEL_OUTPUT_HDMI:
4895 case INTEL_OUTPUT_EDP:
4896 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4897 return port_to_power_domain(intel_dig_port->port);
4898 case INTEL_OUTPUT_DP_MST:
4899 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4900 return port_to_power_domain(intel_dig_port->port);
4901 case INTEL_OUTPUT_ANALOG:
4902 return POWER_DOMAIN_PORT_CRT;
4903 case INTEL_OUTPUT_DSI:
4904 return POWER_DOMAIN_PORT_DSI;
4906 return POWER_DOMAIN_PORT_OTHER;
4910 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4912 struct drm_device *dev = crtc->dev;
4913 struct intel_encoder *intel_encoder;
4914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4915 enum pipe pipe = intel_crtc->pipe;
4917 enum transcoder transcoder;
4919 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4921 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4922 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4923 if (intel_crtc->config->pch_pfit.enabled ||
4924 intel_crtc->config->pch_pfit.force_thru)
4925 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4927 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4928 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4933 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4936 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4937 struct intel_crtc *crtc;
4940 * First get all needed power domains, then put all unneeded, to avoid
4941 * any unnecessary toggling of the power wells.
4943 for_each_intel_crtc(dev, crtc) {
4944 enum intel_display_power_domain domain;
4946 if (!crtc->base.state->enable)
4949 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4951 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4952 intel_display_power_get(dev_priv, domain);
4955 if (dev_priv->display.modeset_global_resources)
4956 dev_priv->display.modeset_global_resources(dev);
4958 for_each_intel_crtc(dev, crtc) {
4959 enum intel_display_power_domain domain;
4961 for_each_power_domain(domain, crtc->enabled_power_domains)
4962 intel_display_power_put(dev_priv, domain);
4964 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4967 intel_display_set_init_power(dev_priv, false);
4970 /* returns HPLL frequency in kHz */
4971 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4973 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4975 /* Obtain SKU information */
4976 mutex_lock(&dev_priv->dpio_lock);
4977 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4978 CCK_FUSE_HPLL_FREQ_MASK;
4979 mutex_unlock(&dev_priv->dpio_lock);
4981 return vco_freq[hpll_freq] * 1000;
4984 static void vlv_update_cdclk(struct drm_device *dev)
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4988 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4989 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4990 dev_priv->vlv_cdclk_freq);
4993 * Program the gmbus_freq based on the cdclk frequency.
4994 * BSpec erroneously claims we should aim for 4MHz, but
4995 * in fact 1MHz is the correct frequency.
4997 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
5000 /* Adjust CDclk dividers to allow high res or save power if possible */
5001 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5006 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5008 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5010 else if (cdclk == 266667)
5015 mutex_lock(&dev_priv->rps.hw_lock);
5016 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5017 val &= ~DSPFREQGUAR_MASK;
5018 val |= (cmd << DSPFREQGUAR_SHIFT);
5019 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5020 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5021 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5023 DRM_ERROR("timed out waiting for CDclk change\n");
5025 mutex_unlock(&dev_priv->rps.hw_lock);
5027 if (cdclk == 400000) {
5030 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5032 mutex_lock(&dev_priv->dpio_lock);
5033 /* adjust cdclk divider */
5034 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5035 val &= ~DISPLAY_FREQUENCY_VALUES;
5037 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5039 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5040 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5042 DRM_ERROR("timed out waiting for CDclk change\n");
5043 mutex_unlock(&dev_priv->dpio_lock);
5046 mutex_lock(&dev_priv->dpio_lock);
5047 /* adjust self-refresh exit latency value */
5048 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5052 * For high bandwidth configs, we set a higher latency in the bunit
5053 * so that the core display fetch happens in time to avoid underruns.
5055 if (cdclk == 400000)
5056 val |= 4500 / 250; /* 4.5 usec */
5058 val |= 3000 / 250; /* 3.0 usec */
5059 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5060 mutex_unlock(&dev_priv->dpio_lock);
5062 vlv_update_cdclk(dev);
5065 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5070 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5079 MISSING_CASE(cdclk);
5084 * Specs are full of misinformation, but testing on actual
5085 * hardware has shown that we just need to write the desired
5086 * CCK divider into the Punit register.
5088 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5090 mutex_lock(&dev_priv->rps.hw_lock);
5091 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5092 val &= ~DSPFREQGUAR_MASK_CHV;
5093 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5094 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5095 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5096 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5098 DRM_ERROR("timed out waiting for CDclk change\n");
5100 mutex_unlock(&dev_priv->rps.hw_lock);
5102 vlv_update_cdclk(dev);
5105 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5108 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5109 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5112 * Really only a few cases to deal with, as only 4 CDclks are supported:
5115 * 320/333MHz (depends on HPLL freq)
5117 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5118 * of the lower bin and adjust if needed.
5120 * We seem to get an unstable or solid color picture at 200MHz.
5121 * Not sure what's wrong. For now use 200MHz only when all pipes
5124 if (!IS_CHERRYVIEW(dev_priv) &&
5125 max_pixclk > freq_320*limit/100)
5127 else if (max_pixclk > 266667*limit/100)
5129 else if (max_pixclk > 0)
5135 /* compute the max pixel clock for new configuration */
5136 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5138 struct drm_device *dev = dev_priv->dev;
5139 struct intel_crtc *intel_crtc;
5142 for_each_intel_crtc(dev, intel_crtc) {
5143 if (intel_crtc->new_enabled)
5144 max_pixclk = max(max_pixclk,
5145 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5151 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5152 unsigned *prepare_pipes)
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 struct intel_crtc *intel_crtc;
5156 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5158 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5159 dev_priv->vlv_cdclk_freq)
5162 /* disable/enable all currently active pipes while we change cdclk */
5163 for_each_intel_crtc(dev, intel_crtc)
5164 if (intel_crtc->base.state->enable)
5165 *prepare_pipes |= (1 << intel_crtc->pipe);
5168 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5170 unsigned int credits, default_credits;
5172 if (IS_CHERRYVIEW(dev_priv))
5173 default_credits = PFI_CREDIT(12);
5175 default_credits = PFI_CREDIT(8);
5177 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5178 /* CHV suggested value is 31 or 63 */
5179 if (IS_CHERRYVIEW(dev_priv))
5180 credits = PFI_CREDIT_31;
5182 credits = PFI_CREDIT(15);
5184 credits = default_credits;
5188 * WA - write default credits before re-programming
5189 * FIXME: should we also set the resend bit here?
5191 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5194 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5195 credits | PFI_CREDIT_RESEND);
5198 * FIXME is this guaranteed to clear
5199 * immediately or should we poll for it?
5201 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5204 static void valleyview_modeset_global_resources(struct drm_device *dev)
5206 struct drm_i915_private *dev_priv = dev->dev_private;
5207 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5208 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5210 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5212 * FIXME: We can end up here with all power domains off, yet
5213 * with a CDCLK frequency other than the minimum. To account
5214 * for this take the PIPE-A power domain, which covers the HW
5215 * blocks needed for the following programming. This can be
5216 * removed once it's guaranteed that we get here either with
5217 * the minimum CDCLK set, or the required power domains
5220 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5222 if (IS_CHERRYVIEW(dev))
5223 cherryview_set_cdclk(dev, req_cdclk);
5225 valleyview_set_cdclk(dev, req_cdclk);
5227 vlv_program_pfi_credits(dev_priv);
5229 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5233 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_i915_private *dev_priv = to_i915(dev);
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 struct intel_encoder *encoder;
5239 int pipe = intel_crtc->pipe;
5242 WARN_ON(!crtc->state->enable);
5244 if (intel_crtc->active)
5247 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5250 if (IS_CHERRYVIEW(dev))
5251 chv_prepare_pll(intel_crtc, intel_crtc->config);
5253 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5256 if (intel_crtc->config->has_dp_encoder)
5257 intel_dp_set_m_n(intel_crtc, M1_N1);
5259 intel_set_pipe_timings(intel_crtc);
5261 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5264 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5265 I915_WRITE(CHV_CANVAS(pipe), 0);
5268 i9xx_set_pipeconf(intel_crtc);
5270 intel_crtc->active = true;
5272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5274 for_each_encoder_on_crtc(dev, crtc, encoder)
5275 if (encoder->pre_pll_enable)
5276 encoder->pre_pll_enable(encoder);
5279 if (IS_CHERRYVIEW(dev))
5280 chv_enable_pll(intel_crtc, intel_crtc->config);
5282 vlv_enable_pll(intel_crtc, intel_crtc->config);
5285 for_each_encoder_on_crtc(dev, crtc, encoder)
5286 if (encoder->pre_enable)
5287 encoder->pre_enable(encoder);
5289 i9xx_pfit_enable(intel_crtc);
5291 intel_crtc_load_lut(crtc);
5293 intel_update_watermarks(crtc);
5294 intel_enable_pipe(intel_crtc);
5296 assert_vblank_disabled(crtc);
5297 drm_crtc_vblank_on(crtc);
5299 for_each_encoder_on_crtc(dev, crtc, encoder)
5300 encoder->enable(encoder);
5302 intel_crtc_enable_planes(crtc);
5304 /* Underruns don't raise interrupts, so check manually. */
5305 i9xx_check_fifo_underruns(dev_priv);
5308 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5310 struct drm_device *dev = crtc->base.dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5313 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5314 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5317 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5319 struct drm_device *dev = crtc->dev;
5320 struct drm_i915_private *dev_priv = to_i915(dev);
5321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5322 struct intel_encoder *encoder;
5323 int pipe = intel_crtc->pipe;
5325 WARN_ON(!crtc->state->enable);
5327 if (intel_crtc->active)
5330 i9xx_set_pll_dividers(intel_crtc);
5332 if (intel_crtc->config->has_dp_encoder)
5333 intel_dp_set_m_n(intel_crtc, M1_N1);
5335 intel_set_pipe_timings(intel_crtc);
5337 i9xx_set_pipeconf(intel_crtc);
5339 intel_crtc->active = true;
5342 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5344 for_each_encoder_on_crtc(dev, crtc, encoder)
5345 if (encoder->pre_enable)
5346 encoder->pre_enable(encoder);
5348 i9xx_enable_pll(intel_crtc);
5350 i9xx_pfit_enable(intel_crtc);
5352 intel_crtc_load_lut(crtc);
5354 intel_update_watermarks(crtc);
5355 intel_enable_pipe(intel_crtc);
5357 assert_vblank_disabled(crtc);
5358 drm_crtc_vblank_on(crtc);
5360 for_each_encoder_on_crtc(dev, crtc, encoder)
5361 encoder->enable(encoder);
5363 intel_crtc_enable_planes(crtc);
5366 * Gen2 reports pipe underruns whenever all planes are disabled.
5367 * So don't enable underrun reporting before at least some planes
5369 * FIXME: Need to fix the logic to work when we turn off all planes
5370 * but leave the pipe running.
5373 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5375 /* Underruns don't raise interrupts, so check manually. */
5376 i9xx_check_fifo_underruns(dev_priv);
5379 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5381 struct drm_device *dev = crtc->base.dev;
5382 struct drm_i915_private *dev_priv = dev->dev_private;
5384 if (!crtc->config->gmch_pfit.control)
5387 assert_pipe_disabled(dev_priv, crtc->pipe);
5389 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5390 I915_READ(PFIT_CONTROL));
5391 I915_WRITE(PFIT_CONTROL, 0);
5394 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5396 struct drm_device *dev = crtc->dev;
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5399 struct intel_encoder *encoder;
5400 int pipe = intel_crtc->pipe;
5402 if (!intel_crtc->active)
5406 * Gen2 reports pipe underruns whenever all planes are disabled.
5407 * So diasble underrun reporting before all the planes get disabled.
5408 * FIXME: Need to fix the logic to work when we turn off all planes
5409 * but leave the pipe running.
5412 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5415 * Vblank time updates from the shadow to live plane control register
5416 * are blocked if the memory self-refresh mode is active at that
5417 * moment. So to make sure the plane gets truly disabled, disable
5418 * first the self-refresh mode. The self-refresh enable bit in turn
5419 * will be checked/applied by the HW only at the next frame start
5420 * event which is after the vblank start event, so we need to have a
5421 * wait-for-vblank between disabling the plane and the pipe.
5423 intel_set_memory_cxsr(dev_priv, false);
5424 intel_crtc_disable_planes(crtc);
5427 * On gen2 planes are double buffered but the pipe isn't, so we must
5428 * wait for planes to fully turn off before disabling the pipe.
5429 * We also need to wait on all gmch platforms because of the
5430 * self-refresh mode constraint explained above.
5432 intel_wait_for_vblank(dev, pipe);
5434 for_each_encoder_on_crtc(dev, crtc, encoder)
5435 encoder->disable(encoder);
5437 drm_crtc_vblank_off(crtc);
5438 assert_vblank_disabled(crtc);
5440 intel_disable_pipe(intel_crtc);
5442 i9xx_pfit_disable(intel_crtc);
5444 for_each_encoder_on_crtc(dev, crtc, encoder)
5445 if (encoder->post_disable)
5446 encoder->post_disable(encoder);
5448 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5449 if (IS_CHERRYVIEW(dev))
5450 chv_disable_pll(dev_priv, pipe);
5451 else if (IS_VALLEYVIEW(dev))
5452 vlv_disable_pll(dev_priv, pipe);
5454 i9xx_disable_pll(intel_crtc);
5458 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5460 intel_crtc->active = false;
5461 intel_update_watermarks(crtc);
5463 mutex_lock(&dev->struct_mutex);
5464 intel_fbc_update(dev);
5465 mutex_unlock(&dev->struct_mutex);
5468 static void i9xx_crtc_off(struct drm_crtc *crtc)
5472 /* Master function to enable/disable CRTC and corresponding power wells */
5473 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5478 enum intel_display_power_domain domain;
5479 unsigned long domains;
5482 if (!intel_crtc->active) {
5483 domains = get_crtc_power_domains(crtc);
5484 for_each_power_domain(domain, domains)
5485 intel_display_power_get(dev_priv, domain);
5486 intel_crtc->enabled_power_domains = domains;
5488 dev_priv->display.crtc_enable(crtc);
5491 if (intel_crtc->active) {
5492 dev_priv->display.crtc_disable(crtc);
5494 domains = intel_crtc->enabled_power_domains;
5495 for_each_power_domain(domain, domains)
5496 intel_display_power_put(dev_priv, domain);
5497 intel_crtc->enabled_power_domains = 0;
5503 * Sets the power management mode of the pipe and plane.
5505 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5507 struct drm_device *dev = crtc->dev;
5508 struct intel_encoder *intel_encoder;
5509 bool enable = false;
5511 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5512 enable |= intel_encoder->connectors_active;
5514 intel_crtc_control(crtc, enable);
5517 static void intel_crtc_disable(struct drm_crtc *crtc)
5519 struct drm_device *dev = crtc->dev;
5520 struct drm_connector *connector;
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5523 /* crtc should still be enabled when we disable it. */
5524 WARN_ON(!crtc->state->enable);
5526 dev_priv->display.crtc_disable(crtc);
5527 dev_priv->display.off(crtc);
5529 crtc->primary->funcs->disable_plane(crtc->primary);
5531 /* Update computed state. */
5532 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5533 if (!connector->encoder || !connector->encoder->crtc)
5536 if (connector->encoder->crtc != crtc)
5539 connector->dpms = DRM_MODE_DPMS_OFF;
5540 to_intel_encoder(connector->encoder)->connectors_active = false;
5544 void intel_encoder_destroy(struct drm_encoder *encoder)
5546 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5548 drm_encoder_cleanup(encoder);
5549 kfree(intel_encoder);
5552 /* Simple dpms helper for encoders with just one connector, no cloning and only
5553 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5554 * state of the entire output pipe. */
5555 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5557 if (mode == DRM_MODE_DPMS_ON) {
5558 encoder->connectors_active = true;
5560 intel_crtc_update_dpms(encoder->base.crtc);
5562 encoder->connectors_active = false;
5564 intel_crtc_update_dpms(encoder->base.crtc);
5568 /* Cross check the actual hw state with our own modeset state tracking (and it's
5569 * internal consistency). */
5570 static void intel_connector_check_state(struct intel_connector *connector)
5572 if (connector->get_hw_state(connector)) {
5573 struct intel_encoder *encoder = connector->encoder;
5574 struct drm_crtc *crtc;
5575 bool encoder_enabled;
5578 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5579 connector->base.base.id,
5580 connector->base.name);
5582 /* there is no real hw state for MST connectors */
5583 if (connector->mst_port)
5586 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5587 "wrong connector dpms state\n");
5588 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5589 "active connector not linked to encoder\n");
5592 I915_STATE_WARN(!encoder->connectors_active,
5593 "encoder->connectors_active not set\n");
5595 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5596 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5597 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5600 crtc = encoder->base.crtc;
5602 I915_STATE_WARN(!crtc->state->enable,
5603 "crtc not enabled\n");
5604 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5605 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5606 "encoder active on the wrong pipe\n");
5611 /* Even simpler default implementation, if there's really no special case to
5613 void intel_connector_dpms(struct drm_connector *connector, int mode)
5615 /* All the simple cases only support two dpms states. */
5616 if (mode != DRM_MODE_DPMS_ON)
5617 mode = DRM_MODE_DPMS_OFF;
5619 if (mode == connector->dpms)
5622 connector->dpms = mode;
5624 /* Only need to change hw state when actually enabled */
5625 if (connector->encoder)
5626 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5628 intel_modeset_check_state(connector->dev);
5631 /* Simple connector->get_hw_state implementation for encoders that support only
5632 * one connector and no cloning and hence the encoder state determines the state
5633 * of the connector. */
5634 bool intel_connector_get_hw_state(struct intel_connector *connector)
5637 struct intel_encoder *encoder = connector->encoder;
5639 return encoder->get_hw_state(encoder, &pipe);
5642 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5644 struct intel_crtc *crtc =
5645 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5647 if (crtc->base.state->enable &&
5648 crtc->config->has_pch_encoder)
5649 return crtc->config->fdi_lanes;
5654 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5655 struct intel_crtc_state *pipe_config)
5657 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5658 pipe_name(pipe), pipe_config->fdi_lanes);
5659 if (pipe_config->fdi_lanes > 4) {
5660 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5661 pipe_name(pipe), pipe_config->fdi_lanes);
5665 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5666 if (pipe_config->fdi_lanes > 2) {
5667 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5668 pipe_config->fdi_lanes);
5675 if (INTEL_INFO(dev)->num_pipes == 2)
5678 /* Ivybridge 3 pipe is really complicated */
5683 if (pipe_config->fdi_lanes > 2 &&
5684 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5685 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5686 pipe_name(pipe), pipe_config->fdi_lanes);
5691 if (pipe_config->fdi_lanes > 2) {
5692 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5693 pipe_name(pipe), pipe_config->fdi_lanes);
5696 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5697 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5707 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5708 struct intel_crtc_state *pipe_config)
5710 struct drm_device *dev = intel_crtc->base.dev;
5711 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5712 int lane, link_bw, fdi_dotclock;
5713 bool setup_ok, needs_recompute = false;
5716 /* FDI is a binary signal running at ~2.7GHz, encoding
5717 * each output octet as 10 bits. The actual frequency
5718 * is stored as a divider into a 100MHz clock, and the
5719 * mode pixel clock is stored in units of 1KHz.
5720 * Hence the bw of each lane in terms of the mode signal
5723 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5725 fdi_dotclock = adjusted_mode->crtc_clock;
5727 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5728 pipe_config->pipe_bpp);
5730 pipe_config->fdi_lanes = lane;
5732 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5733 link_bw, &pipe_config->fdi_m_n);
5735 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5736 intel_crtc->pipe, pipe_config);
5737 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5738 pipe_config->pipe_bpp -= 2*3;
5739 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5740 pipe_config->pipe_bpp);
5741 needs_recompute = true;
5742 pipe_config->bw_constrained = true;
5747 if (needs_recompute)
5750 return setup_ok ? 0 : -EINVAL;
5753 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5754 struct intel_crtc_state *pipe_config)
5756 pipe_config->ips_enabled = i915.enable_ips &&
5757 hsw_crtc_supports_ips(crtc) &&
5758 pipe_config->pipe_bpp <= 24;
5761 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5762 struct intel_crtc_state *pipe_config)
5764 struct drm_device *dev = crtc->base.dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5768 /* FIXME should check pixel clock limits on all platforms */
5769 if (INTEL_INFO(dev)->gen < 4) {
5771 dev_priv->display.get_display_clock_speed(dev);
5774 * Enable pixel doubling when the dot clock
5775 * is > 90% of the (display) core speed.
5777 * GDG double wide on either pipe,
5778 * otherwise pipe A only.
5780 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5781 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5783 pipe_config->double_wide = true;
5786 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5791 * Pipe horizontal size must be even in:
5793 * - LVDS dual channel mode
5794 * - Double wide pipe
5796 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5797 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5798 pipe_config->pipe_src_w &= ~1;
5800 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5801 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5803 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5804 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5807 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5808 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5809 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5810 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5812 pipe_config->pipe_bpp = 8*3;
5816 hsw_compute_ips_config(crtc, pipe_config);
5818 if (pipe_config->has_pch_encoder)
5819 return ironlake_fdi_compute_config(crtc, pipe_config);
5824 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5826 struct drm_i915_private *dev_priv = dev->dev_private;
5830 if (dev_priv->hpll_freq == 0)
5831 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5833 mutex_lock(&dev_priv->dpio_lock);
5834 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5835 mutex_unlock(&dev_priv->dpio_lock);
5837 divider = val & DISPLAY_FREQUENCY_VALUES;
5839 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5840 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5841 "cdclk change in progress\n");
5843 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5846 static int i945_get_display_clock_speed(struct drm_device *dev)
5851 static int i915_get_display_clock_speed(struct drm_device *dev)
5856 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5861 static int pnv_get_display_clock_speed(struct drm_device *dev)
5865 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5867 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5868 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5870 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5872 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5874 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5877 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5878 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5880 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5885 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5889 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5891 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5894 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5895 case GC_DISPLAY_CLOCK_333_MHZ:
5898 case GC_DISPLAY_CLOCK_190_200_MHZ:
5904 static int i865_get_display_clock_speed(struct drm_device *dev)
5909 static int i855_get_display_clock_speed(struct drm_device *dev)
5912 /* Assume that the hardware is in the high speed state. This
5913 * should be the default.
5915 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5916 case GC_CLOCK_133_200:
5917 case GC_CLOCK_100_200:
5919 case GC_CLOCK_166_250:
5921 case GC_CLOCK_100_133:
5925 /* Shouldn't happen */
5929 static int i830_get_display_clock_speed(struct drm_device *dev)
5935 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5937 while (*num > DATA_LINK_M_N_MASK ||
5938 *den > DATA_LINK_M_N_MASK) {
5944 static void compute_m_n(unsigned int m, unsigned int n,
5945 uint32_t *ret_m, uint32_t *ret_n)
5947 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5948 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5949 intel_reduce_m_n_ratio(ret_m, ret_n);
5953 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5954 int pixel_clock, int link_clock,
5955 struct intel_link_m_n *m_n)
5959 compute_m_n(bits_per_pixel * pixel_clock,
5960 link_clock * nlanes * 8,
5961 &m_n->gmch_m, &m_n->gmch_n);
5963 compute_m_n(pixel_clock, link_clock,
5964 &m_n->link_m, &m_n->link_n);
5967 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5969 if (i915.panel_use_ssc >= 0)
5970 return i915.panel_use_ssc != 0;
5971 return dev_priv->vbt.lvds_use_ssc
5972 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5975 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5977 struct drm_device *dev = crtc->base.dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5981 if (IS_VALLEYVIEW(dev)) {
5983 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5984 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5985 refclk = dev_priv->vbt.lvds_ssc_freq;
5986 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5987 } else if (!IS_GEN2(dev)) {
5996 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5998 return (1 << dpll->n) << 16 | dpll->m2;
6001 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6003 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6006 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6007 struct intel_crtc_state *crtc_state,
6008 intel_clock_t *reduced_clock)
6010 struct drm_device *dev = crtc->base.dev;
6013 if (IS_PINEVIEW(dev)) {
6014 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6016 fp2 = pnv_dpll_compute_fp(reduced_clock);
6018 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6020 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6023 crtc_state->dpll_hw_state.fp0 = fp;
6025 crtc->lowfreq_avail = false;
6026 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6028 crtc_state->dpll_hw_state.fp1 = fp2;
6029 crtc->lowfreq_avail = true;
6031 crtc_state->dpll_hw_state.fp1 = fp;
6035 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6041 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6042 * and set it to a reasonable value instead.
6044 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6045 reg_val &= 0xffffff00;
6046 reg_val |= 0x00000030;
6047 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6049 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6050 reg_val &= 0x8cffffff;
6051 reg_val = 0x8c000000;
6052 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6054 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6055 reg_val &= 0xffffff00;
6056 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6058 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6059 reg_val &= 0x00ffffff;
6060 reg_val |= 0xb0000000;
6061 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6064 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6065 struct intel_link_m_n *m_n)
6067 struct drm_device *dev = crtc->base.dev;
6068 struct drm_i915_private *dev_priv = dev->dev_private;
6069 int pipe = crtc->pipe;
6071 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6072 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6073 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6074 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6077 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6078 struct intel_link_m_n *m_n,
6079 struct intel_link_m_n *m2_n2)
6081 struct drm_device *dev = crtc->base.dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 int pipe = crtc->pipe;
6084 enum transcoder transcoder = crtc->config->cpu_transcoder;
6086 if (INTEL_INFO(dev)->gen >= 5) {
6087 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6088 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6089 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6090 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6091 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6092 * for gen < 8) and if DRRS is supported (to make sure the
6093 * registers are not unnecessarily accessed).
6095 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6096 crtc->config->has_drrs) {
6097 I915_WRITE(PIPE_DATA_M2(transcoder),
6098 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6099 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6100 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6101 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6104 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6105 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6106 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6107 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6111 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6113 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6116 dp_m_n = &crtc->config->dp_m_n;
6117 dp_m2_n2 = &crtc->config->dp_m2_n2;
6118 } else if (m_n == M2_N2) {
6121 * M2_N2 registers are not supported. Hence m2_n2 divider value
6122 * needs to be programmed into M1_N1.
6124 dp_m_n = &crtc->config->dp_m2_n2;
6126 DRM_ERROR("Unsupported divider value\n");
6130 if (crtc->config->has_pch_encoder)
6131 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6133 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6136 static void vlv_update_pll(struct intel_crtc *crtc,
6137 struct intel_crtc_state *pipe_config)
6142 * Enable DPIO clock input. We should never disable the reference
6143 * clock for pipe B, since VGA hotplug / manual detection depends
6146 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6147 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6148 /* We should never disable this, set it here for state tracking */
6149 if (crtc->pipe == PIPE_B)
6150 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6151 dpll |= DPLL_VCO_ENABLE;
6152 pipe_config->dpll_hw_state.dpll = dpll;
6154 dpll_md = (pipe_config->pixel_multiplier - 1)
6155 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6156 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6159 static void vlv_prepare_pll(struct intel_crtc *crtc,
6160 const struct intel_crtc_state *pipe_config)
6162 struct drm_device *dev = crtc->base.dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 int pipe = crtc->pipe;
6166 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6167 u32 coreclk, reg_val;
6169 mutex_lock(&dev_priv->dpio_lock);
6171 bestn = pipe_config->dpll.n;
6172 bestm1 = pipe_config->dpll.m1;
6173 bestm2 = pipe_config->dpll.m2;
6174 bestp1 = pipe_config->dpll.p1;
6175 bestp2 = pipe_config->dpll.p2;
6177 /* See eDP HDMI DPIO driver vbios notes doc */
6179 /* PLL B needs special handling */
6181 vlv_pllb_recal_opamp(dev_priv, pipe);
6183 /* Set up Tx target for periodic Rcomp update */
6184 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6186 /* Disable target IRef on PLL */
6187 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6188 reg_val &= 0x00ffffff;
6189 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6191 /* Disable fast lock */
6192 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6194 /* Set idtafcrecal before PLL is enabled */
6195 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6196 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6197 mdiv |= ((bestn << DPIO_N_SHIFT));
6198 mdiv |= (1 << DPIO_K_SHIFT);
6201 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6202 * but we don't support that).
6203 * Note: don't use the DAC post divider as it seems unstable.
6205 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6206 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6208 mdiv |= DPIO_ENABLE_CALIBRATION;
6209 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6211 /* Set HBR and RBR LPF coefficients */
6212 if (pipe_config->port_clock == 162000 ||
6213 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6214 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6215 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6218 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6221 if (pipe_config->has_dp_encoder) {
6222 /* Use SSC source */
6224 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6227 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6229 } else { /* HDMI or VGA */
6230 /* Use bend source */
6232 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6239 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6240 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6241 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6242 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6243 coreclk |= 0x01000000;
6244 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6247 mutex_unlock(&dev_priv->dpio_lock);
6250 static void chv_update_pll(struct intel_crtc *crtc,
6251 struct intel_crtc_state *pipe_config)
6253 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6254 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6256 if (crtc->pipe != PIPE_A)
6257 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6259 pipe_config->dpll_hw_state.dpll_md =
6260 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6263 static void chv_prepare_pll(struct intel_crtc *crtc,
6264 const struct intel_crtc_state *pipe_config)
6266 struct drm_device *dev = crtc->base.dev;
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268 int pipe = crtc->pipe;
6269 int dpll_reg = DPLL(crtc->pipe);
6270 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6271 u32 loopfilter, tribuf_calcntr;
6272 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6276 bestn = pipe_config->dpll.n;
6277 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6278 bestm1 = pipe_config->dpll.m1;
6279 bestm2 = pipe_config->dpll.m2 >> 22;
6280 bestp1 = pipe_config->dpll.p1;
6281 bestp2 = pipe_config->dpll.p2;
6282 vco = pipe_config->dpll.vco;
6287 * Enable Refclk and SSC
6289 I915_WRITE(dpll_reg,
6290 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6292 mutex_lock(&dev_priv->dpio_lock);
6294 /* p1 and p2 divider */
6295 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6296 5 << DPIO_CHV_S1_DIV_SHIFT |
6297 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6298 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6299 1 << DPIO_CHV_K_DIV_SHIFT);
6301 /* Feedback post-divider - m2 */
6302 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6304 /* Feedback refclk divider - n and m1 */
6305 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6306 DPIO_CHV_M1_DIV_BY_2 |
6307 1 << DPIO_CHV_N_DIV_SHIFT);
6309 /* M2 fraction division */
6311 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6313 /* M2 fraction division enable */
6314 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6315 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6316 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6318 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6319 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6321 /* Program digital lock detect threshold */
6322 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6323 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6324 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6325 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6327 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6328 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6331 if (vco == 5400000) {
6332 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6333 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6334 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6335 tribuf_calcntr = 0x9;
6336 } else if (vco <= 6200000) {
6337 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6338 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6339 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6340 tribuf_calcntr = 0x9;
6341 } else if (vco <= 6480000) {
6342 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6343 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6344 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6345 tribuf_calcntr = 0x8;
6347 /* Not supported. Apply the same limits as in the max case */
6348 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6349 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6350 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6353 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6355 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6356 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6357 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6358 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6361 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6362 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6365 mutex_unlock(&dev_priv->dpio_lock);
6369 * vlv_force_pll_on - forcibly enable just the PLL
6370 * @dev_priv: i915 private structure
6371 * @pipe: pipe PLL to enable
6372 * @dpll: PLL configuration
6374 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6375 * in cases where we need the PLL enabled even when @pipe is not going to
6378 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6379 const struct dpll *dpll)
6381 struct intel_crtc *crtc =
6382 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6383 struct intel_crtc_state pipe_config = {
6384 .pixel_multiplier = 1,
6388 if (IS_CHERRYVIEW(dev)) {
6389 chv_update_pll(crtc, &pipe_config);
6390 chv_prepare_pll(crtc, &pipe_config);
6391 chv_enable_pll(crtc, &pipe_config);
6393 vlv_update_pll(crtc, &pipe_config);
6394 vlv_prepare_pll(crtc, &pipe_config);
6395 vlv_enable_pll(crtc, &pipe_config);
6400 * vlv_force_pll_off - forcibly disable just the PLL
6401 * @dev_priv: i915 private structure
6402 * @pipe: pipe PLL to disable
6404 * Disable the PLL for @pipe. To be used in cases where we need
6405 * the PLL enabled even when @pipe is not going to be enabled.
6407 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6409 if (IS_CHERRYVIEW(dev))
6410 chv_disable_pll(to_i915(dev), pipe);
6412 vlv_disable_pll(to_i915(dev), pipe);
6415 static void i9xx_update_pll(struct intel_crtc *crtc,
6416 struct intel_crtc_state *crtc_state,
6417 intel_clock_t *reduced_clock,
6420 struct drm_device *dev = crtc->base.dev;
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6424 struct dpll *clock = &crtc_state->dpll;
6426 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6428 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6429 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6431 dpll = DPLL_VGA_MODE_DIS;
6433 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6434 dpll |= DPLLB_MODE_LVDS;
6436 dpll |= DPLLB_MODE_DAC_SERIAL;
6438 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6439 dpll |= (crtc_state->pixel_multiplier - 1)
6440 << SDVO_MULTIPLIER_SHIFT_HIRES;
6444 dpll |= DPLL_SDVO_HIGH_SPEED;
6446 if (crtc_state->has_dp_encoder)
6447 dpll |= DPLL_SDVO_HIGH_SPEED;
6449 /* compute bitmask from p1 value */
6450 if (IS_PINEVIEW(dev))
6451 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6453 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6454 if (IS_G4X(dev) && reduced_clock)
6455 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6457 switch (clock->p2) {
6459 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6462 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6465 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6468 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6471 if (INTEL_INFO(dev)->gen >= 4)
6472 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6474 if (crtc_state->sdvo_tv_clock)
6475 dpll |= PLL_REF_INPUT_TVCLKINBC;
6476 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6477 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6478 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6480 dpll |= PLL_REF_INPUT_DREFCLK;
6482 dpll |= DPLL_VCO_ENABLE;
6483 crtc_state->dpll_hw_state.dpll = dpll;
6485 if (INTEL_INFO(dev)->gen >= 4) {
6486 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6487 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6488 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6492 static void i8xx_update_pll(struct intel_crtc *crtc,
6493 struct intel_crtc_state *crtc_state,
6494 intel_clock_t *reduced_clock,
6497 struct drm_device *dev = crtc->base.dev;
6498 struct drm_i915_private *dev_priv = dev->dev_private;
6500 struct dpll *clock = &crtc_state->dpll;
6502 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6504 dpll = DPLL_VGA_MODE_DIS;
6506 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6507 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6510 dpll |= PLL_P1_DIVIDE_BY_TWO;
6512 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6514 dpll |= PLL_P2_DIVIDE_BY_4;
6517 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6518 dpll |= DPLL_DVO_2X_MODE;
6520 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6521 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6522 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6524 dpll |= PLL_REF_INPUT_DREFCLK;
6526 dpll |= DPLL_VCO_ENABLE;
6527 crtc_state->dpll_hw_state.dpll = dpll;
6530 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6532 struct drm_device *dev = intel_crtc->base.dev;
6533 struct drm_i915_private *dev_priv = dev->dev_private;
6534 enum pipe pipe = intel_crtc->pipe;
6535 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6536 struct drm_display_mode *adjusted_mode =
6537 &intel_crtc->config->base.adjusted_mode;
6538 uint32_t crtc_vtotal, crtc_vblank_end;
6541 /* We need to be careful not to changed the adjusted mode, for otherwise
6542 * the hw state checker will get angry at the mismatch. */
6543 crtc_vtotal = adjusted_mode->crtc_vtotal;
6544 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6546 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6547 /* the chip adds 2 halflines automatically */
6549 crtc_vblank_end -= 1;
6551 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6552 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6554 vsyncshift = adjusted_mode->crtc_hsync_start -
6555 adjusted_mode->crtc_htotal / 2;
6557 vsyncshift += adjusted_mode->crtc_htotal;
6560 if (INTEL_INFO(dev)->gen > 3)
6561 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6563 I915_WRITE(HTOTAL(cpu_transcoder),
6564 (adjusted_mode->crtc_hdisplay - 1) |
6565 ((adjusted_mode->crtc_htotal - 1) << 16));
6566 I915_WRITE(HBLANK(cpu_transcoder),
6567 (adjusted_mode->crtc_hblank_start - 1) |
6568 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6569 I915_WRITE(HSYNC(cpu_transcoder),
6570 (adjusted_mode->crtc_hsync_start - 1) |
6571 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6573 I915_WRITE(VTOTAL(cpu_transcoder),
6574 (adjusted_mode->crtc_vdisplay - 1) |
6575 ((crtc_vtotal - 1) << 16));
6576 I915_WRITE(VBLANK(cpu_transcoder),
6577 (adjusted_mode->crtc_vblank_start - 1) |
6578 ((crtc_vblank_end - 1) << 16));
6579 I915_WRITE(VSYNC(cpu_transcoder),
6580 (adjusted_mode->crtc_vsync_start - 1) |
6581 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6583 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6584 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6585 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6587 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6588 (pipe == PIPE_B || pipe == PIPE_C))
6589 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6591 /* pipesrc controls the size that is scaled from, which should
6592 * always be the user's requested size.
6594 I915_WRITE(PIPESRC(pipe),
6595 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6596 (intel_crtc->config->pipe_src_h - 1));
6599 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6600 struct intel_crtc_state *pipe_config)
6602 struct drm_device *dev = crtc->base.dev;
6603 struct drm_i915_private *dev_priv = dev->dev_private;
6604 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6607 tmp = I915_READ(HTOTAL(cpu_transcoder));
6608 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6609 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6610 tmp = I915_READ(HBLANK(cpu_transcoder));
6611 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6612 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6613 tmp = I915_READ(HSYNC(cpu_transcoder));
6614 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6615 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6617 tmp = I915_READ(VTOTAL(cpu_transcoder));
6618 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6619 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6620 tmp = I915_READ(VBLANK(cpu_transcoder));
6621 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6622 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6623 tmp = I915_READ(VSYNC(cpu_transcoder));
6624 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6625 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6627 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6628 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6629 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6630 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6633 tmp = I915_READ(PIPESRC(crtc->pipe));
6634 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6635 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6637 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6638 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6641 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6642 struct intel_crtc_state *pipe_config)
6644 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6645 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6646 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6647 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6649 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6650 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6651 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6652 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6654 mode->flags = pipe_config->base.adjusted_mode.flags;
6656 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6657 mode->flags |= pipe_config->base.adjusted_mode.flags;
6660 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6662 struct drm_device *dev = intel_crtc->base.dev;
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6668 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6669 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6670 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6672 if (intel_crtc->config->double_wide)
6673 pipeconf |= PIPECONF_DOUBLE_WIDE;
6675 /* only g4x and later have fancy bpc/dither controls */
6676 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6677 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6678 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6679 pipeconf |= PIPECONF_DITHER_EN |
6680 PIPECONF_DITHER_TYPE_SP;
6682 switch (intel_crtc->config->pipe_bpp) {
6684 pipeconf |= PIPECONF_6BPC;
6687 pipeconf |= PIPECONF_8BPC;
6690 pipeconf |= PIPECONF_10BPC;
6693 /* Case prevented by intel_choose_pipe_bpp_dither. */
6698 if (HAS_PIPE_CXSR(dev)) {
6699 if (intel_crtc->lowfreq_avail) {
6700 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6701 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6703 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6707 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6708 if (INTEL_INFO(dev)->gen < 4 ||
6709 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6710 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6712 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6714 pipeconf |= PIPECONF_PROGRESSIVE;
6716 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6717 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6719 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6720 POSTING_READ(PIPECONF(intel_crtc->pipe));
6723 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6724 struct intel_crtc_state *crtc_state)
6726 struct drm_device *dev = crtc->base.dev;
6727 struct drm_i915_private *dev_priv = dev->dev_private;
6728 int refclk, num_connectors = 0;
6729 intel_clock_t clock, reduced_clock;
6730 bool ok, has_reduced_clock = false;
6731 bool is_lvds = false, is_dsi = false;
6732 struct intel_encoder *encoder;
6733 const intel_limit_t *limit;
6735 for_each_intel_encoder(dev, encoder) {
6736 if (encoder->new_crtc != crtc)
6739 switch (encoder->type) {
6740 case INTEL_OUTPUT_LVDS:
6743 case INTEL_OUTPUT_DSI:
6756 if (!crtc_state->clock_set) {
6757 refclk = i9xx_get_refclk(crtc, num_connectors);
6760 * Returns a set of divisors for the desired target clock with
6761 * the given refclk, or FALSE. The returned values represent
6762 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6765 limit = intel_limit(crtc, refclk);
6766 ok = dev_priv->display.find_dpll(limit, crtc,
6767 crtc_state->port_clock,
6768 refclk, NULL, &clock);
6770 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6774 if (is_lvds && dev_priv->lvds_downclock_avail) {
6776 * Ensure we match the reduced clock's P to the target
6777 * clock. If the clocks don't match, we can't switch
6778 * the display clock by using the FP0/FP1. In such case
6779 * we will disable the LVDS downclock feature.
6782 dev_priv->display.find_dpll(limit, crtc,
6783 dev_priv->lvds_downclock,
6787 /* Compat-code for transition, will disappear. */
6788 crtc_state->dpll.n = clock.n;
6789 crtc_state->dpll.m1 = clock.m1;
6790 crtc_state->dpll.m2 = clock.m2;
6791 crtc_state->dpll.p1 = clock.p1;
6792 crtc_state->dpll.p2 = clock.p2;
6796 i8xx_update_pll(crtc, crtc_state,
6797 has_reduced_clock ? &reduced_clock : NULL,
6799 } else if (IS_CHERRYVIEW(dev)) {
6800 chv_update_pll(crtc, crtc_state);
6801 } else if (IS_VALLEYVIEW(dev)) {
6802 vlv_update_pll(crtc, crtc_state);
6804 i9xx_update_pll(crtc, crtc_state,
6805 has_reduced_clock ? &reduced_clock : NULL,
6812 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6813 struct intel_crtc_state *pipe_config)
6815 struct drm_device *dev = crtc->base.dev;
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6819 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6822 tmp = I915_READ(PFIT_CONTROL);
6823 if (!(tmp & PFIT_ENABLE))
6826 /* Check whether the pfit is attached to our pipe. */
6827 if (INTEL_INFO(dev)->gen < 4) {
6828 if (crtc->pipe != PIPE_B)
6831 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6835 pipe_config->gmch_pfit.control = tmp;
6836 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6837 if (INTEL_INFO(dev)->gen < 5)
6838 pipe_config->gmch_pfit.lvds_border_bits =
6839 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6842 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6843 struct intel_crtc_state *pipe_config)
6845 struct drm_device *dev = crtc->base.dev;
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 int pipe = pipe_config->cpu_transcoder;
6848 intel_clock_t clock;
6850 int refclk = 100000;
6852 /* In case of MIPI DPLL will not even be used */
6853 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6856 mutex_lock(&dev_priv->dpio_lock);
6857 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6858 mutex_unlock(&dev_priv->dpio_lock);
6860 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6861 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6862 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6863 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6864 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6866 vlv_clock(refclk, &clock);
6868 /* clock.dot is the fast clock */
6869 pipe_config->port_clock = clock.dot / 5;
6873 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6874 struct intel_initial_plane_config *plane_config)
6876 struct drm_device *dev = crtc->base.dev;
6877 struct drm_i915_private *dev_priv = dev->dev_private;
6878 u32 val, base, offset;
6879 int pipe = crtc->pipe, plane = crtc->plane;
6880 int fourcc, pixel_format;
6881 unsigned int aligned_height;
6882 struct drm_framebuffer *fb;
6883 struct intel_framebuffer *intel_fb;
6885 val = I915_READ(DSPCNTR(plane));
6886 if (!(val & DISPLAY_PLANE_ENABLE))
6889 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6891 DRM_DEBUG_KMS("failed to alloc fb\n");
6895 fb = &intel_fb->base;
6897 if (INTEL_INFO(dev)->gen >= 4) {
6898 if (val & DISPPLANE_TILED) {
6899 plane_config->tiling = I915_TILING_X;
6900 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6904 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6905 fourcc = i9xx_format_to_fourcc(pixel_format);
6906 fb->pixel_format = fourcc;
6907 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6909 if (INTEL_INFO(dev)->gen >= 4) {
6910 if (plane_config->tiling)
6911 offset = I915_READ(DSPTILEOFF(plane));
6913 offset = I915_READ(DSPLINOFF(plane));
6914 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6916 base = I915_READ(DSPADDR(plane));
6918 plane_config->base = base;
6920 val = I915_READ(PIPESRC(pipe));
6921 fb->width = ((val >> 16) & 0xfff) + 1;
6922 fb->height = ((val >> 0) & 0xfff) + 1;
6924 val = I915_READ(DSPSTRIDE(pipe));
6925 fb->pitches[0] = val & 0xffffffc0;
6927 aligned_height = intel_fb_align_height(dev, fb->height,
6931 plane_config->size = fb->pitches[0] * aligned_height;
6933 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6934 pipe_name(pipe), plane, fb->width, fb->height,
6935 fb->bits_per_pixel, base, fb->pitches[0],
6936 plane_config->size);
6938 plane_config->fb = intel_fb;
6941 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6942 struct intel_crtc_state *pipe_config)
6944 struct drm_device *dev = crtc->base.dev;
6945 struct drm_i915_private *dev_priv = dev->dev_private;
6946 int pipe = pipe_config->cpu_transcoder;
6947 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6948 intel_clock_t clock;
6949 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6950 int refclk = 100000;
6952 mutex_lock(&dev_priv->dpio_lock);
6953 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6954 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6955 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6956 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6957 mutex_unlock(&dev_priv->dpio_lock);
6959 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6960 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6961 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6962 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6963 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6965 chv_clock(refclk, &clock);
6967 /* clock.dot is the fast clock */
6968 pipe_config->port_clock = clock.dot / 5;
6971 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6972 struct intel_crtc_state *pipe_config)
6974 struct drm_device *dev = crtc->base.dev;
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6978 if (!intel_display_power_is_enabled(dev_priv,
6979 POWER_DOMAIN_PIPE(crtc->pipe)))
6982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6983 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6985 tmp = I915_READ(PIPECONF(crtc->pipe));
6986 if (!(tmp & PIPECONF_ENABLE))
6989 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6990 switch (tmp & PIPECONF_BPC_MASK) {
6992 pipe_config->pipe_bpp = 18;
6995 pipe_config->pipe_bpp = 24;
6997 case PIPECONF_10BPC:
6998 pipe_config->pipe_bpp = 30;
7005 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7006 pipe_config->limited_color_range = true;
7008 if (INTEL_INFO(dev)->gen < 4)
7009 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7011 intel_get_pipe_timings(crtc, pipe_config);
7013 i9xx_get_pfit_config(crtc, pipe_config);
7015 if (INTEL_INFO(dev)->gen >= 4) {
7016 tmp = I915_READ(DPLL_MD(crtc->pipe));
7017 pipe_config->pixel_multiplier =
7018 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7019 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7020 pipe_config->dpll_hw_state.dpll_md = tmp;
7021 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7022 tmp = I915_READ(DPLL(crtc->pipe));
7023 pipe_config->pixel_multiplier =
7024 ((tmp & SDVO_MULTIPLIER_MASK)
7025 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7027 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7028 * port and will be fixed up in the encoder->get_config
7030 pipe_config->pixel_multiplier = 1;
7032 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7033 if (!IS_VALLEYVIEW(dev)) {
7035 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7036 * on 830. Filter it out here so that we don't
7037 * report errors due to that.
7040 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7042 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7043 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7045 /* Mask out read-only status bits. */
7046 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7047 DPLL_PORTC_READY_MASK |
7048 DPLL_PORTB_READY_MASK);
7051 if (IS_CHERRYVIEW(dev))
7052 chv_crtc_clock_get(crtc, pipe_config);
7053 else if (IS_VALLEYVIEW(dev))
7054 vlv_crtc_clock_get(crtc, pipe_config);
7056 i9xx_crtc_clock_get(crtc, pipe_config);
7061 static void ironlake_init_pch_refclk(struct drm_device *dev)
7063 struct drm_i915_private *dev_priv = dev->dev_private;
7064 struct intel_encoder *encoder;
7066 bool has_lvds = false;
7067 bool has_cpu_edp = false;
7068 bool has_panel = false;
7069 bool has_ck505 = false;
7070 bool can_ssc = false;
7072 /* We need to take the global config into account */
7073 for_each_intel_encoder(dev, encoder) {
7074 switch (encoder->type) {
7075 case INTEL_OUTPUT_LVDS:
7079 case INTEL_OUTPUT_EDP:
7081 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7089 if (HAS_PCH_IBX(dev)) {
7090 has_ck505 = dev_priv->vbt.display_clock_mode;
7091 can_ssc = has_ck505;
7097 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7098 has_panel, has_lvds, has_ck505);
7100 /* Ironlake: try to setup display ref clock before DPLL
7101 * enabling. This is only under driver's control after
7102 * PCH B stepping, previous chipset stepping should be
7103 * ignoring this setting.
7105 val = I915_READ(PCH_DREF_CONTROL);
7107 /* As we must carefully and slowly disable/enable each source in turn,
7108 * compute the final state we want first and check if we need to
7109 * make any changes at all.
7112 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7114 final |= DREF_NONSPREAD_CK505_ENABLE;
7116 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7118 final &= ~DREF_SSC_SOURCE_MASK;
7119 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7120 final &= ~DREF_SSC1_ENABLE;
7123 final |= DREF_SSC_SOURCE_ENABLE;
7125 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7126 final |= DREF_SSC1_ENABLE;
7129 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7130 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7132 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7134 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7136 final |= DREF_SSC_SOURCE_DISABLE;
7137 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7143 /* Always enable nonspread source */
7144 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7147 val |= DREF_NONSPREAD_CK505_ENABLE;
7149 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7152 val &= ~DREF_SSC_SOURCE_MASK;
7153 val |= DREF_SSC_SOURCE_ENABLE;
7155 /* SSC must be turned on before enabling the CPU output */
7156 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7157 DRM_DEBUG_KMS("Using SSC on panel\n");
7158 val |= DREF_SSC1_ENABLE;
7160 val &= ~DREF_SSC1_ENABLE;
7162 /* Get SSC going before enabling the outputs */
7163 I915_WRITE(PCH_DREF_CONTROL, val);
7164 POSTING_READ(PCH_DREF_CONTROL);
7167 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7169 /* Enable CPU source on CPU attached eDP */
7171 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7172 DRM_DEBUG_KMS("Using SSC on eDP\n");
7173 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7175 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7177 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7179 I915_WRITE(PCH_DREF_CONTROL, val);
7180 POSTING_READ(PCH_DREF_CONTROL);
7183 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7185 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7187 /* Turn off CPU output */
7188 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7190 I915_WRITE(PCH_DREF_CONTROL, val);
7191 POSTING_READ(PCH_DREF_CONTROL);
7194 /* Turn off the SSC source */
7195 val &= ~DREF_SSC_SOURCE_MASK;
7196 val |= DREF_SSC_SOURCE_DISABLE;
7199 val &= ~DREF_SSC1_ENABLE;
7201 I915_WRITE(PCH_DREF_CONTROL, val);
7202 POSTING_READ(PCH_DREF_CONTROL);
7206 BUG_ON(val != final);
7209 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7213 tmp = I915_READ(SOUTH_CHICKEN2);
7214 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7215 I915_WRITE(SOUTH_CHICKEN2, tmp);
7217 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7218 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7219 DRM_ERROR("FDI mPHY reset assert timeout\n");
7221 tmp = I915_READ(SOUTH_CHICKEN2);
7222 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7223 I915_WRITE(SOUTH_CHICKEN2, tmp);
7225 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7226 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7227 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7230 /* WaMPhyProgramming:hsw */
7231 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7235 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7236 tmp &= ~(0xFF << 24);
7237 tmp |= (0x12 << 24);
7238 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7240 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7242 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7244 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7246 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7248 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7249 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7250 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7252 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7253 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7254 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7256 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7259 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7261 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7264 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7266 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7269 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7271 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7274 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7276 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7277 tmp &= ~(0xFF << 16);
7278 tmp |= (0x1C << 16);
7279 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7281 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7282 tmp &= ~(0xFF << 16);
7283 tmp |= (0x1C << 16);
7284 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7286 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7288 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7290 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7292 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7294 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7295 tmp &= ~(0xF << 28);
7297 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7299 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7300 tmp &= ~(0xF << 28);
7302 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7305 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7306 * Programming" based on the parameters passed:
7307 * - Sequence to enable CLKOUT_DP
7308 * - Sequence to enable CLKOUT_DP without spread
7309 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7311 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7314 struct drm_i915_private *dev_priv = dev->dev_private;
7317 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7319 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7320 with_fdi, "LP PCH doesn't have FDI\n"))
7323 mutex_lock(&dev_priv->dpio_lock);
7325 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7326 tmp &= ~SBI_SSCCTL_DISABLE;
7327 tmp |= SBI_SSCCTL_PATHALT;
7328 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7333 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7334 tmp &= ~SBI_SSCCTL_PATHALT;
7335 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7338 lpt_reset_fdi_mphy(dev_priv);
7339 lpt_program_fdi_mphy(dev_priv);
7343 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7344 SBI_GEN0 : SBI_DBUFF0;
7345 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7346 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7347 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7349 mutex_unlock(&dev_priv->dpio_lock);
7352 /* Sequence to disable CLKOUT_DP */
7353 static void lpt_disable_clkout_dp(struct drm_device *dev)
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7358 mutex_lock(&dev_priv->dpio_lock);
7360 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7361 SBI_GEN0 : SBI_DBUFF0;
7362 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7363 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7364 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7366 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7367 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7368 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7369 tmp |= SBI_SSCCTL_PATHALT;
7370 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7373 tmp |= SBI_SSCCTL_DISABLE;
7374 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7377 mutex_unlock(&dev_priv->dpio_lock);
7380 static void lpt_init_pch_refclk(struct drm_device *dev)
7382 struct intel_encoder *encoder;
7383 bool has_vga = false;
7385 for_each_intel_encoder(dev, encoder) {
7386 switch (encoder->type) {
7387 case INTEL_OUTPUT_ANALOG:
7396 lpt_enable_clkout_dp(dev, true, true);
7398 lpt_disable_clkout_dp(dev);
7402 * Initialize reference clocks when the driver loads
7404 void intel_init_pch_refclk(struct drm_device *dev)
7406 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7407 ironlake_init_pch_refclk(dev);
7408 else if (HAS_PCH_LPT(dev))
7409 lpt_init_pch_refclk(dev);
7412 static int ironlake_get_refclk(struct drm_crtc *crtc)
7414 struct drm_device *dev = crtc->dev;
7415 struct drm_i915_private *dev_priv = dev->dev_private;
7416 struct intel_encoder *encoder;
7417 int num_connectors = 0;
7418 bool is_lvds = false;
7420 for_each_intel_encoder(dev, encoder) {
7421 if (encoder->new_crtc != to_intel_crtc(crtc))
7424 switch (encoder->type) {
7425 case INTEL_OUTPUT_LVDS:
7434 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7435 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7436 dev_priv->vbt.lvds_ssc_freq);
7437 return dev_priv->vbt.lvds_ssc_freq;
7443 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7445 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447 int pipe = intel_crtc->pipe;
7452 switch (intel_crtc->config->pipe_bpp) {
7454 val |= PIPECONF_6BPC;
7457 val |= PIPECONF_8BPC;
7460 val |= PIPECONF_10BPC;
7463 val |= PIPECONF_12BPC;
7466 /* Case prevented by intel_choose_pipe_bpp_dither. */
7470 if (intel_crtc->config->dither)
7471 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7473 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7474 val |= PIPECONF_INTERLACED_ILK;
7476 val |= PIPECONF_PROGRESSIVE;
7478 if (intel_crtc->config->limited_color_range)
7479 val |= PIPECONF_COLOR_RANGE_SELECT;
7481 I915_WRITE(PIPECONF(pipe), val);
7482 POSTING_READ(PIPECONF(pipe));
7486 * Set up the pipe CSC unit.
7488 * Currently only full range RGB to limited range RGB conversion
7489 * is supported, but eventually this should handle various
7490 * RGB<->YCbCr scenarios as well.
7492 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7494 struct drm_device *dev = crtc->dev;
7495 struct drm_i915_private *dev_priv = dev->dev_private;
7496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7497 int pipe = intel_crtc->pipe;
7498 uint16_t coeff = 0x7800; /* 1.0 */
7501 * TODO: Check what kind of values actually come out of the pipe
7502 * with these coeff/postoff values and adjust to get the best
7503 * accuracy. Perhaps we even need to take the bpc value into
7507 if (intel_crtc->config->limited_color_range)
7508 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7511 * GY/GU and RY/RU should be the other way around according
7512 * to BSpec, but reality doesn't agree. Just set them up in
7513 * a way that results in the correct picture.
7515 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7516 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7518 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7519 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7521 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7522 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7524 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7525 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7526 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7528 if (INTEL_INFO(dev)->gen > 6) {
7529 uint16_t postoff = 0;
7531 if (intel_crtc->config->limited_color_range)
7532 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7534 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7535 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7536 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7538 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7540 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7542 if (intel_crtc->config->limited_color_range)
7543 mode |= CSC_BLACK_SCREEN_OFFSET;
7545 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7549 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7551 struct drm_device *dev = crtc->dev;
7552 struct drm_i915_private *dev_priv = dev->dev_private;
7553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7554 enum pipe pipe = intel_crtc->pipe;
7555 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7560 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7561 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7563 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7564 val |= PIPECONF_INTERLACED_ILK;
7566 val |= PIPECONF_PROGRESSIVE;
7568 I915_WRITE(PIPECONF(cpu_transcoder), val);
7569 POSTING_READ(PIPECONF(cpu_transcoder));
7571 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7572 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7574 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7577 switch (intel_crtc->config->pipe_bpp) {
7579 val |= PIPEMISC_DITHER_6_BPC;
7582 val |= PIPEMISC_DITHER_8_BPC;
7585 val |= PIPEMISC_DITHER_10_BPC;
7588 val |= PIPEMISC_DITHER_12_BPC;
7591 /* Case prevented by pipe_config_set_bpp. */
7595 if (intel_crtc->config->dither)
7596 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7598 I915_WRITE(PIPEMISC(pipe), val);
7602 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7603 struct intel_crtc_state *crtc_state,
7604 intel_clock_t *clock,
7605 bool *has_reduced_clock,
7606 intel_clock_t *reduced_clock)
7608 struct drm_device *dev = crtc->dev;
7609 struct drm_i915_private *dev_priv = dev->dev_private;
7610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7612 const intel_limit_t *limit;
7613 bool ret, is_lvds = false;
7615 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7617 refclk = ironlake_get_refclk(crtc);
7620 * Returns a set of divisors for the desired target clock with the given
7621 * refclk, or FALSE. The returned values represent the clock equation:
7622 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7624 limit = intel_limit(intel_crtc, refclk);
7625 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7626 crtc_state->port_clock,
7627 refclk, NULL, clock);
7631 if (is_lvds && dev_priv->lvds_downclock_avail) {
7633 * Ensure we match the reduced clock's P to the target clock.
7634 * If the clocks don't match, we can't switch the display clock
7635 * by using the FP0/FP1. In such case we will disable the LVDS
7636 * downclock feature.
7638 *has_reduced_clock =
7639 dev_priv->display.find_dpll(limit, intel_crtc,
7640 dev_priv->lvds_downclock,
7648 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7651 * Account for spread spectrum to avoid
7652 * oversubscribing the link. Max center spread
7653 * is 2.5%; use 5% for safety's sake.
7655 u32 bps = target_clock * bpp * 21 / 20;
7656 return DIV_ROUND_UP(bps, link_bw * 8);
7659 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7661 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7664 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7665 struct intel_crtc_state *crtc_state,
7667 intel_clock_t *reduced_clock, u32 *fp2)
7669 struct drm_crtc *crtc = &intel_crtc->base;
7670 struct drm_device *dev = crtc->dev;
7671 struct drm_i915_private *dev_priv = dev->dev_private;
7672 struct intel_encoder *intel_encoder;
7674 int factor, num_connectors = 0;
7675 bool is_lvds = false, is_sdvo = false;
7677 for_each_intel_encoder(dev, intel_encoder) {
7678 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7681 switch (intel_encoder->type) {
7682 case INTEL_OUTPUT_LVDS:
7685 case INTEL_OUTPUT_SDVO:
7686 case INTEL_OUTPUT_HDMI:
7696 /* Enable autotuning of the PLL clock (if permissible) */
7699 if ((intel_panel_use_ssc(dev_priv) &&
7700 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7701 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7703 } else if (crtc_state->sdvo_tv_clock)
7706 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7709 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7715 dpll |= DPLLB_MODE_LVDS;
7717 dpll |= DPLLB_MODE_DAC_SERIAL;
7719 dpll |= (crtc_state->pixel_multiplier - 1)
7720 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7723 dpll |= DPLL_SDVO_HIGH_SPEED;
7724 if (crtc_state->has_dp_encoder)
7725 dpll |= DPLL_SDVO_HIGH_SPEED;
7727 /* compute bitmask from p1 value */
7728 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7730 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7732 switch (crtc_state->dpll.p2) {
7734 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7737 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7740 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7743 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7747 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7748 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7750 dpll |= PLL_REF_INPUT_DREFCLK;
7752 return dpll | DPLL_VCO_ENABLE;
7755 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7756 struct intel_crtc_state *crtc_state)
7758 struct drm_device *dev = crtc->base.dev;
7759 intel_clock_t clock, reduced_clock;
7760 u32 dpll = 0, fp = 0, fp2 = 0;
7761 bool ok, has_reduced_clock = false;
7762 bool is_lvds = false;
7763 struct intel_shared_dpll *pll;
7765 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7767 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7768 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7770 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7771 &has_reduced_clock, &reduced_clock);
7772 if (!ok && !crtc_state->clock_set) {
7773 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7776 /* Compat-code for transition, will disappear. */
7777 if (!crtc_state->clock_set) {
7778 crtc_state->dpll.n = clock.n;
7779 crtc_state->dpll.m1 = clock.m1;
7780 crtc_state->dpll.m2 = clock.m2;
7781 crtc_state->dpll.p1 = clock.p1;
7782 crtc_state->dpll.p2 = clock.p2;
7785 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7786 if (crtc_state->has_pch_encoder) {
7787 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7788 if (has_reduced_clock)
7789 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7791 dpll = ironlake_compute_dpll(crtc, crtc_state,
7792 &fp, &reduced_clock,
7793 has_reduced_clock ? &fp2 : NULL);
7795 crtc_state->dpll_hw_state.dpll = dpll;
7796 crtc_state->dpll_hw_state.fp0 = fp;
7797 if (has_reduced_clock)
7798 crtc_state->dpll_hw_state.fp1 = fp2;
7800 crtc_state->dpll_hw_state.fp1 = fp;
7802 pll = intel_get_shared_dpll(crtc, crtc_state);
7804 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7805 pipe_name(crtc->pipe));
7810 if (is_lvds && has_reduced_clock)
7811 crtc->lowfreq_avail = true;
7813 crtc->lowfreq_avail = false;
7818 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7819 struct intel_link_m_n *m_n)
7821 struct drm_device *dev = crtc->base.dev;
7822 struct drm_i915_private *dev_priv = dev->dev_private;
7823 enum pipe pipe = crtc->pipe;
7825 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7826 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7827 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7829 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7830 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7831 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7834 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7835 enum transcoder transcoder,
7836 struct intel_link_m_n *m_n,
7837 struct intel_link_m_n *m2_n2)
7839 struct drm_device *dev = crtc->base.dev;
7840 struct drm_i915_private *dev_priv = dev->dev_private;
7841 enum pipe pipe = crtc->pipe;
7843 if (INTEL_INFO(dev)->gen >= 5) {
7844 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7845 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7846 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7848 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7849 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7850 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7851 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7852 * gen < 8) and if DRRS is supported (to make sure the
7853 * registers are not unnecessarily read).
7855 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7856 crtc->config->has_drrs) {
7857 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7858 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7859 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7861 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7862 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7863 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7866 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7867 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7868 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7870 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7871 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7872 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7876 void intel_dp_get_m_n(struct intel_crtc *crtc,
7877 struct intel_crtc_state *pipe_config)
7879 if (pipe_config->has_pch_encoder)
7880 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7882 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7883 &pipe_config->dp_m_n,
7884 &pipe_config->dp_m2_n2);
7887 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7888 struct intel_crtc_state *pipe_config)
7890 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7891 &pipe_config->fdi_m_n, NULL);
7894 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7895 struct intel_crtc_state *pipe_config)
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7901 tmp = I915_READ(PS_CTL(crtc->pipe));
7903 if (tmp & PS_ENABLE) {
7904 pipe_config->pch_pfit.enabled = true;
7905 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7906 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7911 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7912 struct intel_initial_plane_config *plane_config)
7914 struct drm_device *dev = crtc->base.dev;
7915 struct drm_i915_private *dev_priv = dev->dev_private;
7916 u32 val, base, offset, stride_mult, tiling;
7917 int pipe = crtc->pipe;
7918 int fourcc, pixel_format;
7919 unsigned int aligned_height;
7920 struct drm_framebuffer *fb;
7921 struct intel_framebuffer *intel_fb;
7923 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7925 DRM_DEBUG_KMS("failed to alloc fb\n");
7929 fb = &intel_fb->base;
7931 val = I915_READ(PLANE_CTL(pipe, 0));
7932 if (!(val & PLANE_CTL_ENABLE))
7935 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7936 fourcc = skl_format_to_fourcc(pixel_format,
7937 val & PLANE_CTL_ORDER_RGBX,
7938 val & PLANE_CTL_ALPHA_MASK);
7939 fb->pixel_format = fourcc;
7940 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7942 tiling = val & PLANE_CTL_TILED_MASK;
7944 case PLANE_CTL_TILED_LINEAR:
7945 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7947 case PLANE_CTL_TILED_X:
7948 plane_config->tiling = I915_TILING_X;
7949 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7951 case PLANE_CTL_TILED_Y:
7952 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7954 case PLANE_CTL_TILED_YF:
7955 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7958 MISSING_CASE(tiling);
7962 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7963 plane_config->base = base;
7965 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7967 val = I915_READ(PLANE_SIZE(pipe, 0));
7968 fb->height = ((val >> 16) & 0xfff) + 1;
7969 fb->width = ((val >> 0) & 0x1fff) + 1;
7971 val = I915_READ(PLANE_STRIDE(pipe, 0));
7972 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7974 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7976 aligned_height = intel_fb_align_height(dev, fb->height,
7980 plane_config->size = fb->pitches[0] * aligned_height;
7982 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7983 pipe_name(pipe), fb->width, fb->height,
7984 fb->bits_per_pixel, base, fb->pitches[0],
7985 plane_config->size);
7987 plane_config->fb = intel_fb;
7994 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7995 struct intel_crtc_state *pipe_config)
7997 struct drm_device *dev = crtc->base.dev;
7998 struct drm_i915_private *dev_priv = dev->dev_private;
8001 tmp = I915_READ(PF_CTL(crtc->pipe));
8003 if (tmp & PF_ENABLE) {
8004 pipe_config->pch_pfit.enabled = true;
8005 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8006 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8008 /* We currently do not free assignements of panel fitters on
8009 * ivb/hsw (since we don't use the higher upscaling modes which
8010 * differentiates them) so just WARN about this case for now. */
8012 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8013 PF_PIPE_SEL_IVB(crtc->pipe));
8019 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8020 struct intel_initial_plane_config *plane_config)
8022 struct drm_device *dev = crtc->base.dev;
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 u32 val, base, offset;
8025 int pipe = crtc->pipe;
8026 int fourcc, pixel_format;
8027 unsigned int aligned_height;
8028 struct drm_framebuffer *fb;
8029 struct intel_framebuffer *intel_fb;
8031 val = I915_READ(DSPCNTR(pipe));
8032 if (!(val & DISPLAY_PLANE_ENABLE))
8035 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8037 DRM_DEBUG_KMS("failed to alloc fb\n");
8041 fb = &intel_fb->base;
8043 if (INTEL_INFO(dev)->gen >= 4) {
8044 if (val & DISPPLANE_TILED) {
8045 plane_config->tiling = I915_TILING_X;
8046 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8050 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8051 fourcc = i9xx_format_to_fourcc(pixel_format);
8052 fb->pixel_format = fourcc;
8053 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8055 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8056 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8057 offset = I915_READ(DSPOFFSET(pipe));
8059 if (plane_config->tiling)
8060 offset = I915_READ(DSPTILEOFF(pipe));
8062 offset = I915_READ(DSPLINOFF(pipe));
8064 plane_config->base = base;
8066 val = I915_READ(PIPESRC(pipe));
8067 fb->width = ((val >> 16) & 0xfff) + 1;
8068 fb->height = ((val >> 0) & 0xfff) + 1;
8070 val = I915_READ(DSPSTRIDE(pipe));
8071 fb->pitches[0] = val & 0xffffffc0;
8073 aligned_height = intel_fb_align_height(dev, fb->height,
8077 plane_config->size = fb->pitches[0] * aligned_height;
8079 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8080 pipe_name(pipe), fb->width, fb->height,
8081 fb->bits_per_pixel, base, fb->pitches[0],
8082 plane_config->size);
8084 plane_config->fb = intel_fb;
8087 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8088 struct intel_crtc_state *pipe_config)
8090 struct drm_device *dev = crtc->base.dev;
8091 struct drm_i915_private *dev_priv = dev->dev_private;
8094 if (!intel_display_power_is_enabled(dev_priv,
8095 POWER_DOMAIN_PIPE(crtc->pipe)))
8098 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8099 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8101 tmp = I915_READ(PIPECONF(crtc->pipe));
8102 if (!(tmp & PIPECONF_ENABLE))
8105 switch (tmp & PIPECONF_BPC_MASK) {
8107 pipe_config->pipe_bpp = 18;
8110 pipe_config->pipe_bpp = 24;
8112 case PIPECONF_10BPC:
8113 pipe_config->pipe_bpp = 30;
8115 case PIPECONF_12BPC:
8116 pipe_config->pipe_bpp = 36;
8122 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8123 pipe_config->limited_color_range = true;
8125 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8126 struct intel_shared_dpll *pll;
8128 pipe_config->has_pch_encoder = true;
8130 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8131 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8132 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8134 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8136 if (HAS_PCH_IBX(dev_priv->dev)) {
8137 pipe_config->shared_dpll =
8138 (enum intel_dpll_id) crtc->pipe;
8140 tmp = I915_READ(PCH_DPLL_SEL);
8141 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8142 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8144 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8147 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8149 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8150 &pipe_config->dpll_hw_state));
8152 tmp = pipe_config->dpll_hw_state.dpll;
8153 pipe_config->pixel_multiplier =
8154 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8155 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8157 ironlake_pch_clock_get(crtc, pipe_config);
8159 pipe_config->pixel_multiplier = 1;
8162 intel_get_pipe_timings(crtc, pipe_config);
8164 ironlake_get_pfit_config(crtc, pipe_config);
8169 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8171 struct drm_device *dev = dev_priv->dev;
8172 struct intel_crtc *crtc;
8174 for_each_intel_crtc(dev, crtc)
8175 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8176 pipe_name(crtc->pipe));
8178 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8179 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8180 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8181 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8182 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8183 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8184 "CPU PWM1 enabled\n");
8185 if (IS_HASWELL(dev))
8186 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8187 "CPU PWM2 enabled\n");
8188 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8189 "PCH PWM1 enabled\n");
8190 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8191 "Utility pin enabled\n");
8192 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8195 * In theory we can still leave IRQs enabled, as long as only the HPD
8196 * interrupts remain enabled. We used to check for that, but since it's
8197 * gen-specific and since we only disable LCPLL after we fully disable
8198 * the interrupts, the check below should be enough.
8200 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8203 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8205 struct drm_device *dev = dev_priv->dev;
8207 if (IS_HASWELL(dev))
8208 return I915_READ(D_COMP_HSW);
8210 return I915_READ(D_COMP_BDW);
8213 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8215 struct drm_device *dev = dev_priv->dev;
8217 if (IS_HASWELL(dev)) {
8218 mutex_lock(&dev_priv->rps.hw_lock);
8219 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8221 DRM_ERROR("Failed to write to D_COMP\n");
8222 mutex_unlock(&dev_priv->rps.hw_lock);
8224 I915_WRITE(D_COMP_BDW, val);
8225 POSTING_READ(D_COMP_BDW);
8230 * This function implements pieces of two sequences from BSpec:
8231 * - Sequence for display software to disable LCPLL
8232 * - Sequence for display software to allow package C8+
8233 * The steps implemented here are just the steps that actually touch the LCPLL
8234 * register. Callers should take care of disabling all the display engine
8235 * functions, doing the mode unset, fixing interrupts, etc.
8237 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8238 bool switch_to_fclk, bool allow_power_down)
8242 assert_can_disable_lcpll(dev_priv);
8244 val = I915_READ(LCPLL_CTL);
8246 if (switch_to_fclk) {
8247 val |= LCPLL_CD_SOURCE_FCLK;
8248 I915_WRITE(LCPLL_CTL, val);
8250 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8251 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8252 DRM_ERROR("Switching to FCLK failed\n");
8254 val = I915_READ(LCPLL_CTL);
8257 val |= LCPLL_PLL_DISABLE;
8258 I915_WRITE(LCPLL_CTL, val);
8259 POSTING_READ(LCPLL_CTL);
8261 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8262 DRM_ERROR("LCPLL still locked\n");
8264 val = hsw_read_dcomp(dev_priv);
8265 val |= D_COMP_COMP_DISABLE;
8266 hsw_write_dcomp(dev_priv, val);
8269 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8271 DRM_ERROR("D_COMP RCOMP still in progress\n");
8273 if (allow_power_down) {
8274 val = I915_READ(LCPLL_CTL);
8275 val |= LCPLL_POWER_DOWN_ALLOW;
8276 I915_WRITE(LCPLL_CTL, val);
8277 POSTING_READ(LCPLL_CTL);
8282 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8285 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8289 val = I915_READ(LCPLL_CTL);
8291 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8292 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8296 * Make sure we're not on PC8 state before disabling PC8, otherwise
8297 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8299 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8301 if (val & LCPLL_POWER_DOWN_ALLOW) {
8302 val &= ~LCPLL_POWER_DOWN_ALLOW;
8303 I915_WRITE(LCPLL_CTL, val);
8304 POSTING_READ(LCPLL_CTL);
8307 val = hsw_read_dcomp(dev_priv);
8308 val |= D_COMP_COMP_FORCE;
8309 val &= ~D_COMP_COMP_DISABLE;
8310 hsw_write_dcomp(dev_priv, val);
8312 val = I915_READ(LCPLL_CTL);
8313 val &= ~LCPLL_PLL_DISABLE;
8314 I915_WRITE(LCPLL_CTL, val);
8316 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8317 DRM_ERROR("LCPLL not locked yet\n");
8319 if (val & LCPLL_CD_SOURCE_FCLK) {
8320 val = I915_READ(LCPLL_CTL);
8321 val &= ~LCPLL_CD_SOURCE_FCLK;
8322 I915_WRITE(LCPLL_CTL, val);
8324 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8325 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8326 DRM_ERROR("Switching back to LCPLL failed\n");
8329 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8333 * Package states C8 and deeper are really deep PC states that can only be
8334 * reached when all the devices on the system allow it, so even if the graphics
8335 * device allows PC8+, it doesn't mean the system will actually get to these
8336 * states. Our driver only allows PC8+ when going into runtime PM.
8338 * The requirements for PC8+ are that all the outputs are disabled, the power
8339 * well is disabled and most interrupts are disabled, and these are also
8340 * requirements for runtime PM. When these conditions are met, we manually do
8341 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8342 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8345 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8346 * the state of some registers, so when we come back from PC8+ we need to
8347 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8348 * need to take care of the registers kept by RC6. Notice that this happens even
8349 * if we don't put the device in PCI D3 state (which is what currently happens
8350 * because of the runtime PM support).
8352 * For more, read "Display Sequences for Package C8" on the hardware
8355 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8357 struct drm_device *dev = dev_priv->dev;
8360 DRM_DEBUG_KMS("Enabling package C8+\n");
8362 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8363 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8364 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8365 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8368 lpt_disable_clkout_dp(dev);
8369 hsw_disable_lcpll(dev_priv, true, true);
8372 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8374 struct drm_device *dev = dev_priv->dev;
8377 DRM_DEBUG_KMS("Disabling package C8+\n");
8379 hsw_restore_lcpll(dev_priv);
8380 lpt_init_pch_refclk(dev);
8382 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8383 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8384 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8385 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8388 intel_prepare_ddi(dev);
8391 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8392 struct intel_crtc_state *crtc_state)
8394 if (!intel_ddi_pll_select(crtc, crtc_state))
8397 crtc->lowfreq_avail = false;
8402 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8404 struct intel_crtc_state *pipe_config)
8406 u32 temp, dpll_ctl1;
8408 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8409 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8411 switch (pipe_config->ddi_pll_sel) {
8414 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8415 * of the shared DPLL framework and thus needs to be read out
8418 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8419 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8422 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8425 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8428 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8433 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8435 struct intel_crtc_state *pipe_config)
8437 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8439 switch (pipe_config->ddi_pll_sel) {
8440 case PORT_CLK_SEL_WRPLL1:
8441 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8443 case PORT_CLK_SEL_WRPLL2:
8444 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8449 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8450 struct intel_crtc_state *pipe_config)
8452 struct drm_device *dev = crtc->base.dev;
8453 struct drm_i915_private *dev_priv = dev->dev_private;
8454 struct intel_shared_dpll *pll;
8458 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8460 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8462 if (IS_SKYLAKE(dev))
8463 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8465 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8467 if (pipe_config->shared_dpll >= 0) {
8468 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8470 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8471 &pipe_config->dpll_hw_state));
8475 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8476 * DDI E. So just check whether this pipe is wired to DDI E and whether
8477 * the PCH transcoder is on.
8479 if (INTEL_INFO(dev)->gen < 9 &&
8480 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8481 pipe_config->has_pch_encoder = true;
8483 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8484 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8485 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8487 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8491 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8492 struct intel_crtc_state *pipe_config)
8494 struct drm_device *dev = crtc->base.dev;
8495 struct drm_i915_private *dev_priv = dev->dev_private;
8496 enum intel_display_power_domain pfit_domain;
8499 if (!intel_display_power_is_enabled(dev_priv,
8500 POWER_DOMAIN_PIPE(crtc->pipe)))
8503 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8504 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8506 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8507 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8508 enum pipe trans_edp_pipe;
8509 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8511 WARN(1, "unknown pipe linked to edp transcoder\n");
8512 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8513 case TRANS_DDI_EDP_INPUT_A_ON:
8514 trans_edp_pipe = PIPE_A;
8516 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8517 trans_edp_pipe = PIPE_B;
8519 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8520 trans_edp_pipe = PIPE_C;
8524 if (trans_edp_pipe == crtc->pipe)
8525 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8528 if (!intel_display_power_is_enabled(dev_priv,
8529 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8532 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8533 if (!(tmp & PIPECONF_ENABLE))
8536 haswell_get_ddi_port_state(crtc, pipe_config);
8538 intel_get_pipe_timings(crtc, pipe_config);
8540 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8541 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8542 if (IS_SKYLAKE(dev))
8543 skylake_get_pfit_config(crtc, pipe_config);
8545 ironlake_get_pfit_config(crtc, pipe_config);
8548 if (IS_HASWELL(dev))
8549 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8550 (I915_READ(IPS_CTL) & IPS_ENABLE);
8552 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8553 pipe_config->pixel_multiplier =
8554 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8556 pipe_config->pixel_multiplier = 1;
8562 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8564 struct drm_device *dev = crtc->dev;
8565 struct drm_i915_private *dev_priv = dev->dev_private;
8566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8567 uint32_t cntl = 0, size = 0;
8570 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8571 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8572 unsigned int stride = roundup_pow_of_two(width) * 4;
8576 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8587 cntl |= CURSOR_ENABLE |
8588 CURSOR_GAMMA_ENABLE |
8589 CURSOR_FORMAT_ARGB |
8590 CURSOR_STRIDE(stride);
8592 size = (height << 12) | width;
8595 if (intel_crtc->cursor_cntl != 0 &&
8596 (intel_crtc->cursor_base != base ||
8597 intel_crtc->cursor_size != size ||
8598 intel_crtc->cursor_cntl != cntl)) {
8599 /* On these chipsets we can only modify the base/size/stride
8600 * whilst the cursor is disabled.
8602 I915_WRITE(_CURACNTR, 0);
8603 POSTING_READ(_CURACNTR);
8604 intel_crtc->cursor_cntl = 0;
8607 if (intel_crtc->cursor_base != base) {
8608 I915_WRITE(_CURABASE, base);
8609 intel_crtc->cursor_base = base;
8612 if (intel_crtc->cursor_size != size) {
8613 I915_WRITE(CURSIZE, size);
8614 intel_crtc->cursor_size = size;
8617 if (intel_crtc->cursor_cntl != cntl) {
8618 I915_WRITE(_CURACNTR, cntl);
8619 POSTING_READ(_CURACNTR);
8620 intel_crtc->cursor_cntl = cntl;
8624 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8626 struct drm_device *dev = crtc->dev;
8627 struct drm_i915_private *dev_priv = dev->dev_private;
8628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629 int pipe = intel_crtc->pipe;
8634 cntl = MCURSOR_GAMMA_ENABLE;
8635 switch (intel_crtc->base.cursor->state->crtc_w) {
8637 cntl |= CURSOR_MODE_64_ARGB_AX;
8640 cntl |= CURSOR_MODE_128_ARGB_AX;
8643 cntl |= CURSOR_MODE_256_ARGB_AX;
8646 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8649 cntl |= pipe << 28; /* Connect to correct pipe */
8651 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8652 cntl |= CURSOR_PIPE_CSC_ENABLE;
8655 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8656 cntl |= CURSOR_ROTATE_180;
8658 if (intel_crtc->cursor_cntl != cntl) {
8659 I915_WRITE(CURCNTR(pipe), cntl);
8660 POSTING_READ(CURCNTR(pipe));
8661 intel_crtc->cursor_cntl = cntl;
8664 /* and commit changes on next vblank */
8665 I915_WRITE(CURBASE(pipe), base);
8666 POSTING_READ(CURBASE(pipe));
8668 intel_crtc->cursor_base = base;
8671 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8672 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8675 struct drm_device *dev = crtc->dev;
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8678 int pipe = intel_crtc->pipe;
8679 int x = crtc->cursor_x;
8680 int y = crtc->cursor_y;
8681 u32 base = 0, pos = 0;
8684 base = intel_crtc->cursor_addr;
8686 if (x >= intel_crtc->config->pipe_src_w)
8689 if (y >= intel_crtc->config->pipe_src_h)
8693 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8696 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8699 pos |= x << CURSOR_X_SHIFT;
8702 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8705 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8708 pos |= y << CURSOR_Y_SHIFT;
8710 if (base == 0 && intel_crtc->cursor_base == 0)
8713 I915_WRITE(CURPOS(pipe), pos);
8715 /* ILK+ do this automagically */
8716 if (HAS_GMCH_DISPLAY(dev) &&
8717 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8718 base += (intel_crtc->base.cursor->state->crtc_h *
8719 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8722 if (IS_845G(dev) || IS_I865G(dev))
8723 i845_update_cursor(crtc, base);
8725 i9xx_update_cursor(crtc, base);
8728 static bool cursor_size_ok(struct drm_device *dev,
8729 uint32_t width, uint32_t height)
8731 if (width == 0 || height == 0)
8735 * 845g/865g are special in that they are only limited by
8736 * the width of their cursors, the height is arbitrary up to
8737 * the precision of the register. Everything else requires
8738 * square cursors, limited to a few power-of-two sizes.
8740 if (IS_845G(dev) || IS_I865G(dev)) {
8741 if ((width & 63) != 0)
8744 if (width > (IS_845G(dev) ? 64 : 512))
8750 switch (width | height) {
8765 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8766 u16 *blue, uint32_t start, uint32_t size)
8768 int end = (start + size > 256) ? 256 : start + size, i;
8769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8771 for (i = start; i < end; i++) {
8772 intel_crtc->lut_r[i] = red[i] >> 8;
8773 intel_crtc->lut_g[i] = green[i] >> 8;
8774 intel_crtc->lut_b[i] = blue[i] >> 8;
8777 intel_crtc_load_lut(crtc);
8780 /* VESA 640x480x72Hz mode to set on the pipe */
8781 static struct drm_display_mode load_detect_mode = {
8782 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8783 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8786 struct drm_framebuffer *
8787 __intel_framebuffer_create(struct drm_device *dev,
8788 struct drm_mode_fb_cmd2 *mode_cmd,
8789 struct drm_i915_gem_object *obj)
8791 struct intel_framebuffer *intel_fb;
8794 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8796 drm_gem_object_unreference(&obj->base);
8797 return ERR_PTR(-ENOMEM);
8800 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8804 return &intel_fb->base;
8806 drm_gem_object_unreference(&obj->base);
8809 return ERR_PTR(ret);
8812 static struct drm_framebuffer *
8813 intel_framebuffer_create(struct drm_device *dev,
8814 struct drm_mode_fb_cmd2 *mode_cmd,
8815 struct drm_i915_gem_object *obj)
8817 struct drm_framebuffer *fb;
8820 ret = i915_mutex_lock_interruptible(dev);
8822 return ERR_PTR(ret);
8823 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8824 mutex_unlock(&dev->struct_mutex);
8830 intel_framebuffer_pitch_for_width(int width, int bpp)
8832 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8833 return ALIGN(pitch, 64);
8837 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8839 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8840 return PAGE_ALIGN(pitch * mode->vdisplay);
8843 static struct drm_framebuffer *
8844 intel_framebuffer_create_for_mode(struct drm_device *dev,
8845 struct drm_display_mode *mode,
8848 struct drm_i915_gem_object *obj;
8849 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8851 obj = i915_gem_alloc_object(dev,
8852 intel_framebuffer_size_for_mode(mode, bpp));
8854 return ERR_PTR(-ENOMEM);
8856 mode_cmd.width = mode->hdisplay;
8857 mode_cmd.height = mode->vdisplay;
8858 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8860 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8862 return intel_framebuffer_create(dev, &mode_cmd, obj);
8865 static struct drm_framebuffer *
8866 mode_fits_in_fbdev(struct drm_device *dev,
8867 struct drm_display_mode *mode)
8869 #ifdef CONFIG_DRM_I915_FBDEV
8870 struct drm_i915_private *dev_priv = dev->dev_private;
8871 struct drm_i915_gem_object *obj;
8872 struct drm_framebuffer *fb;
8874 if (!dev_priv->fbdev)
8877 if (!dev_priv->fbdev->fb)
8880 obj = dev_priv->fbdev->fb->obj;
8883 fb = &dev_priv->fbdev->fb->base;
8884 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8885 fb->bits_per_pixel))
8888 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8897 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8898 struct drm_display_mode *mode,
8899 struct intel_load_detect_pipe *old,
8900 struct drm_modeset_acquire_ctx *ctx)
8902 struct intel_crtc *intel_crtc;
8903 struct intel_encoder *intel_encoder =
8904 intel_attached_encoder(connector);
8905 struct drm_crtc *possible_crtc;
8906 struct drm_encoder *encoder = &intel_encoder->base;
8907 struct drm_crtc *crtc = NULL;
8908 struct drm_device *dev = encoder->dev;
8909 struct drm_framebuffer *fb;
8910 struct drm_mode_config *config = &dev->mode_config;
8913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8914 connector->base.id, connector->name,
8915 encoder->base.id, encoder->name);
8918 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8923 * Algorithm gets a little messy:
8925 * - if the connector already has an assigned crtc, use it (but make
8926 * sure it's on first)
8928 * - try to find the first unused crtc that can drive this connector,
8929 * and use that if we find one
8932 /* See if we already have a CRTC for this connector */
8933 if (encoder->crtc) {
8934 crtc = encoder->crtc;
8936 ret = drm_modeset_lock(&crtc->mutex, ctx);
8939 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8943 old->dpms_mode = connector->dpms;
8944 old->load_detect_temp = false;
8946 /* Make sure the crtc and connector are running */
8947 if (connector->dpms != DRM_MODE_DPMS_ON)
8948 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8953 /* Find an unused one (if possible) */
8954 for_each_crtc(dev, possible_crtc) {
8956 if (!(encoder->possible_crtcs & (1 << i)))
8958 if (possible_crtc->state->enable)
8960 /* This can occur when applying the pipe A quirk on resume. */
8961 if (to_intel_crtc(possible_crtc)->new_enabled)
8964 crtc = possible_crtc;
8969 * If we didn't find an unused CRTC, don't use any.
8972 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8976 ret = drm_modeset_lock(&crtc->mutex, ctx);
8979 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8982 intel_encoder->new_crtc = to_intel_crtc(crtc);
8983 to_intel_connector(connector)->new_encoder = intel_encoder;
8985 intel_crtc = to_intel_crtc(crtc);
8986 intel_crtc->new_enabled = true;
8987 intel_crtc->new_config = intel_crtc->config;
8988 old->dpms_mode = connector->dpms;
8989 old->load_detect_temp = true;
8990 old->release_fb = NULL;
8993 mode = &load_detect_mode;
8995 /* We need a framebuffer large enough to accommodate all accesses
8996 * that the plane may generate whilst we perform load detection.
8997 * We can not rely on the fbcon either being present (we get called
8998 * during its initialisation to detect all boot displays, or it may
8999 * not even exist) or that it is large enough to satisfy the
9002 fb = mode_fits_in_fbdev(dev, mode);
9004 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9005 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9006 old->release_fb = fb;
9008 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9010 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9014 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
9015 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9016 if (old->release_fb)
9017 old->release_fb->funcs->destroy(old->release_fb);
9020 crtc->primary->crtc = crtc;
9022 /* let the connector get through one full cycle before testing */
9023 intel_wait_for_vblank(dev, intel_crtc->pipe);
9027 intel_crtc->new_enabled = crtc->state->enable;
9028 if (intel_crtc->new_enabled)
9029 intel_crtc->new_config = intel_crtc->config;
9031 intel_crtc->new_config = NULL;
9033 if (ret == -EDEADLK) {
9034 drm_modeset_backoff(ctx);
9041 void intel_release_load_detect_pipe(struct drm_connector *connector,
9042 struct intel_load_detect_pipe *old)
9044 struct intel_encoder *intel_encoder =
9045 intel_attached_encoder(connector);
9046 struct drm_encoder *encoder = &intel_encoder->base;
9047 struct drm_crtc *crtc = encoder->crtc;
9048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9050 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9051 connector->base.id, connector->name,
9052 encoder->base.id, encoder->name);
9054 if (old->load_detect_temp) {
9055 to_intel_connector(connector)->new_encoder = NULL;
9056 intel_encoder->new_crtc = NULL;
9057 intel_crtc->new_enabled = false;
9058 intel_crtc->new_config = NULL;
9059 intel_set_mode(crtc, NULL, 0, 0, NULL);
9061 if (old->release_fb) {
9062 drm_framebuffer_unregister_private(old->release_fb);
9063 drm_framebuffer_unreference(old->release_fb);
9069 /* Switch crtc and encoder back off if necessary */
9070 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9071 connector->funcs->dpms(connector, old->dpms_mode);
9074 static int i9xx_pll_refclk(struct drm_device *dev,
9075 const struct intel_crtc_state *pipe_config)
9077 struct drm_i915_private *dev_priv = dev->dev_private;
9078 u32 dpll = pipe_config->dpll_hw_state.dpll;
9080 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9081 return dev_priv->vbt.lvds_ssc_freq;
9082 else if (HAS_PCH_SPLIT(dev))
9084 else if (!IS_GEN2(dev))
9090 /* Returns the clock of the currently programmed mode of the given pipe. */
9091 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9092 struct intel_crtc_state *pipe_config)
9094 struct drm_device *dev = crtc->base.dev;
9095 struct drm_i915_private *dev_priv = dev->dev_private;
9096 int pipe = pipe_config->cpu_transcoder;
9097 u32 dpll = pipe_config->dpll_hw_state.dpll;
9099 intel_clock_t clock;
9100 int refclk = i9xx_pll_refclk(dev, pipe_config);
9102 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9103 fp = pipe_config->dpll_hw_state.fp0;
9105 fp = pipe_config->dpll_hw_state.fp1;
9107 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9108 if (IS_PINEVIEW(dev)) {
9109 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9110 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9112 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9113 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9116 if (!IS_GEN2(dev)) {
9117 if (IS_PINEVIEW(dev))
9118 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9119 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9121 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9122 DPLL_FPA01_P1_POST_DIV_SHIFT);
9124 switch (dpll & DPLL_MODE_MASK) {
9125 case DPLLB_MODE_DAC_SERIAL:
9126 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9129 case DPLLB_MODE_LVDS:
9130 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9134 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9135 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9139 if (IS_PINEVIEW(dev))
9140 pineview_clock(refclk, &clock);
9142 i9xx_clock(refclk, &clock);
9144 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9145 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9148 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9149 DPLL_FPA01_P1_POST_DIV_SHIFT);
9151 if (lvds & LVDS_CLKB_POWER_UP)
9156 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9159 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9160 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9162 if (dpll & PLL_P2_DIVIDE_BY_4)
9168 i9xx_clock(refclk, &clock);
9172 * This value includes pixel_multiplier. We will use
9173 * port_clock to compute adjusted_mode.crtc_clock in the
9174 * encoder's get_config() function.
9176 pipe_config->port_clock = clock.dot;
9179 int intel_dotclock_calculate(int link_freq,
9180 const struct intel_link_m_n *m_n)
9183 * The calculation for the data clock is:
9184 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9185 * But we want to avoid losing precison if possible, so:
9186 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9188 * and the link clock is simpler:
9189 * link_clock = (m * link_clock) / n
9195 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9198 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9199 struct intel_crtc_state *pipe_config)
9201 struct drm_device *dev = crtc->base.dev;
9203 /* read out port_clock from the DPLL */
9204 i9xx_crtc_clock_get(crtc, pipe_config);
9207 * This value does not include pixel_multiplier.
9208 * We will check that port_clock and adjusted_mode.crtc_clock
9209 * agree once we know their relationship in the encoder's
9210 * get_config() function.
9212 pipe_config->base.adjusted_mode.crtc_clock =
9213 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9214 &pipe_config->fdi_m_n);
9217 /** Returns the currently programmed mode of the given pipe. */
9218 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9219 struct drm_crtc *crtc)
9221 struct drm_i915_private *dev_priv = dev->dev_private;
9222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9223 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9224 struct drm_display_mode *mode;
9225 struct intel_crtc_state pipe_config;
9226 int htot = I915_READ(HTOTAL(cpu_transcoder));
9227 int hsync = I915_READ(HSYNC(cpu_transcoder));
9228 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9229 int vsync = I915_READ(VSYNC(cpu_transcoder));
9230 enum pipe pipe = intel_crtc->pipe;
9232 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9237 * Construct a pipe_config sufficient for getting the clock info
9238 * back out of crtc_clock_get.
9240 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9241 * to use a real value here instead.
9243 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9244 pipe_config.pixel_multiplier = 1;
9245 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9246 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9247 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9248 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9250 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9251 mode->hdisplay = (htot & 0xffff) + 1;
9252 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9253 mode->hsync_start = (hsync & 0xffff) + 1;
9254 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9255 mode->vdisplay = (vtot & 0xffff) + 1;
9256 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9257 mode->vsync_start = (vsync & 0xffff) + 1;
9258 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9260 drm_mode_set_name(mode);
9265 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9267 struct drm_device *dev = crtc->dev;
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9271 if (!HAS_GMCH_DISPLAY(dev))
9274 if (!dev_priv->lvds_downclock_avail)
9278 * Since this is called by a timer, we should never get here in
9281 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9282 int pipe = intel_crtc->pipe;
9283 int dpll_reg = DPLL(pipe);
9286 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9288 assert_panel_unlocked(dev_priv, pipe);
9290 dpll = I915_READ(dpll_reg);
9291 dpll |= DISPLAY_RATE_SELECT_FPA1;
9292 I915_WRITE(dpll_reg, dpll);
9293 intel_wait_for_vblank(dev, pipe);
9294 dpll = I915_READ(dpll_reg);
9295 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9296 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9301 void intel_mark_busy(struct drm_device *dev)
9303 struct drm_i915_private *dev_priv = dev->dev_private;
9305 if (dev_priv->mm.busy)
9308 intel_runtime_pm_get(dev_priv);
9309 i915_update_gfx_val(dev_priv);
9310 if (INTEL_INFO(dev)->gen >= 6)
9311 gen6_rps_busy(dev_priv);
9312 dev_priv->mm.busy = true;
9315 void intel_mark_idle(struct drm_device *dev)
9317 struct drm_i915_private *dev_priv = dev->dev_private;
9318 struct drm_crtc *crtc;
9320 if (!dev_priv->mm.busy)
9323 dev_priv->mm.busy = false;
9325 for_each_crtc(dev, crtc) {
9326 if (!crtc->primary->fb)
9329 intel_decrease_pllclock(crtc);
9332 if (INTEL_INFO(dev)->gen >= 6)
9333 gen6_rps_idle(dev->dev_private);
9335 intel_runtime_pm_put(dev_priv);
9338 static void intel_crtc_set_state(struct intel_crtc *crtc,
9339 struct intel_crtc_state *crtc_state)
9341 kfree(crtc->config);
9342 crtc->config = crtc_state;
9343 crtc->base.state = &crtc_state->base;
9346 static void intel_crtc_destroy(struct drm_crtc *crtc)
9348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9349 struct drm_device *dev = crtc->dev;
9350 struct intel_unpin_work *work;
9352 spin_lock_irq(&dev->event_lock);
9353 work = intel_crtc->unpin_work;
9354 intel_crtc->unpin_work = NULL;
9355 spin_unlock_irq(&dev->event_lock);
9358 cancel_work_sync(&work->work);
9362 intel_crtc_set_state(intel_crtc, NULL);
9363 drm_crtc_cleanup(crtc);
9368 static void intel_unpin_work_fn(struct work_struct *__work)
9370 struct intel_unpin_work *work =
9371 container_of(__work, struct intel_unpin_work, work);
9372 struct drm_device *dev = work->crtc->dev;
9373 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9375 mutex_lock(&dev->struct_mutex);
9376 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9377 drm_gem_object_unreference(&work->pending_flip_obj->base);
9379 intel_fbc_update(dev);
9381 if (work->flip_queued_req)
9382 i915_gem_request_assign(&work->flip_queued_req, NULL);
9383 mutex_unlock(&dev->struct_mutex);
9385 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9386 drm_framebuffer_unreference(work->old_fb);
9388 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9389 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9394 static void do_intel_finish_page_flip(struct drm_device *dev,
9395 struct drm_crtc *crtc)
9397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9398 struct intel_unpin_work *work;
9399 unsigned long flags;
9401 /* Ignore early vblank irqs */
9402 if (intel_crtc == NULL)
9406 * This is called both by irq handlers and the reset code (to complete
9407 * lost pageflips) so needs the full irqsave spinlocks.
9409 spin_lock_irqsave(&dev->event_lock, flags);
9410 work = intel_crtc->unpin_work;
9412 /* Ensure we don't miss a work->pending update ... */
9415 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9416 spin_unlock_irqrestore(&dev->event_lock, flags);
9420 page_flip_completed(intel_crtc);
9422 spin_unlock_irqrestore(&dev->event_lock, flags);
9425 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9427 struct drm_i915_private *dev_priv = dev->dev_private;
9428 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9430 do_intel_finish_page_flip(dev, crtc);
9433 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9435 struct drm_i915_private *dev_priv = dev->dev_private;
9436 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9438 do_intel_finish_page_flip(dev, crtc);
9441 /* Is 'a' after or equal to 'b'? */
9442 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9444 return !((a - b) & 0x80000000);
9447 static bool page_flip_finished(struct intel_crtc *crtc)
9449 struct drm_device *dev = crtc->base.dev;
9450 struct drm_i915_private *dev_priv = dev->dev_private;
9452 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9453 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9457 * The relevant registers doen't exist on pre-ctg.
9458 * As the flip done interrupt doesn't trigger for mmio
9459 * flips on gmch platforms, a flip count check isn't
9460 * really needed there. But since ctg has the registers,
9461 * include it in the check anyway.
9463 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9467 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9468 * used the same base address. In that case the mmio flip might
9469 * have completed, but the CS hasn't even executed the flip yet.
9471 * A flip count check isn't enough as the CS might have updated
9472 * the base address just after start of vblank, but before we
9473 * managed to process the interrupt. This means we'd complete the
9476 * Combining both checks should get us a good enough result. It may
9477 * still happen that the CS flip has been executed, but has not
9478 * yet actually completed. But in case the base address is the same
9479 * anyway, we don't really care.
9481 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9482 crtc->unpin_work->gtt_offset &&
9483 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9484 crtc->unpin_work->flip_count);
9487 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9489 struct drm_i915_private *dev_priv = dev->dev_private;
9490 struct intel_crtc *intel_crtc =
9491 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9492 unsigned long flags;
9496 * This is called both by irq handlers and the reset code (to complete
9497 * lost pageflips) so needs the full irqsave spinlocks.
9499 * NB: An MMIO update of the plane base pointer will also
9500 * generate a page-flip completion irq, i.e. every modeset
9501 * is also accompanied by a spurious intel_prepare_page_flip().
9503 spin_lock_irqsave(&dev->event_lock, flags);
9504 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9505 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9506 spin_unlock_irqrestore(&dev->event_lock, flags);
9509 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9511 /* Ensure that the work item is consistent when activating it ... */
9513 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9514 /* and that it is marked active as soon as the irq could fire. */
9518 static int intel_gen2_queue_flip(struct drm_device *dev,
9519 struct drm_crtc *crtc,
9520 struct drm_framebuffer *fb,
9521 struct drm_i915_gem_object *obj,
9522 struct intel_engine_cs *ring,
9525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9529 ret = intel_ring_begin(ring, 6);
9533 /* Can't queue multiple flips, so wait for the previous
9534 * one to finish before executing the next.
9536 if (intel_crtc->plane)
9537 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9539 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9540 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9541 intel_ring_emit(ring, MI_NOOP);
9542 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9543 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9544 intel_ring_emit(ring, fb->pitches[0]);
9545 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9546 intel_ring_emit(ring, 0); /* aux display base address, unused */
9548 intel_mark_page_flip_active(intel_crtc);
9549 __intel_ring_advance(ring);
9553 static int intel_gen3_queue_flip(struct drm_device *dev,
9554 struct drm_crtc *crtc,
9555 struct drm_framebuffer *fb,
9556 struct drm_i915_gem_object *obj,
9557 struct intel_engine_cs *ring,
9560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9564 ret = intel_ring_begin(ring, 6);
9568 if (intel_crtc->plane)
9569 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9571 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9572 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9573 intel_ring_emit(ring, MI_NOOP);
9574 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9575 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9576 intel_ring_emit(ring, fb->pitches[0]);
9577 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9578 intel_ring_emit(ring, MI_NOOP);
9580 intel_mark_page_flip_active(intel_crtc);
9581 __intel_ring_advance(ring);
9585 static int intel_gen4_queue_flip(struct drm_device *dev,
9586 struct drm_crtc *crtc,
9587 struct drm_framebuffer *fb,
9588 struct drm_i915_gem_object *obj,
9589 struct intel_engine_cs *ring,
9592 struct drm_i915_private *dev_priv = dev->dev_private;
9593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9594 uint32_t pf, pipesrc;
9597 ret = intel_ring_begin(ring, 4);
9601 /* i965+ uses the linear or tiled offsets from the
9602 * Display Registers (which do not change across a page-flip)
9603 * so we need only reprogram the base address.
9605 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9606 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9607 intel_ring_emit(ring, fb->pitches[0]);
9608 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9611 /* XXX Enabling the panel-fitter across page-flip is so far
9612 * untested on non-native modes, so ignore it for now.
9613 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9616 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9617 intel_ring_emit(ring, pf | pipesrc);
9619 intel_mark_page_flip_active(intel_crtc);
9620 __intel_ring_advance(ring);
9624 static int intel_gen6_queue_flip(struct drm_device *dev,
9625 struct drm_crtc *crtc,
9626 struct drm_framebuffer *fb,
9627 struct drm_i915_gem_object *obj,
9628 struct intel_engine_cs *ring,
9631 struct drm_i915_private *dev_priv = dev->dev_private;
9632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9633 uint32_t pf, pipesrc;
9636 ret = intel_ring_begin(ring, 4);
9640 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9641 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9642 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9643 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9645 /* Contrary to the suggestions in the documentation,
9646 * "Enable Panel Fitter" does not seem to be required when page
9647 * flipping with a non-native mode, and worse causes a normal
9649 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9652 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9653 intel_ring_emit(ring, pf | pipesrc);
9655 intel_mark_page_flip_active(intel_crtc);
9656 __intel_ring_advance(ring);
9660 static int intel_gen7_queue_flip(struct drm_device *dev,
9661 struct drm_crtc *crtc,
9662 struct drm_framebuffer *fb,
9663 struct drm_i915_gem_object *obj,
9664 struct intel_engine_cs *ring,
9667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9668 uint32_t plane_bit = 0;
9671 switch (intel_crtc->plane) {
9673 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9676 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9679 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9682 WARN_ONCE(1, "unknown plane in flip command\n");
9687 if (ring->id == RCS) {
9690 * On Gen 8, SRM is now taking an extra dword to accommodate
9691 * 48bits addresses, and we need a NOOP for the batch size to
9699 * BSpec MI_DISPLAY_FLIP for IVB:
9700 * "The full packet must be contained within the same cache line."
9702 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9703 * cacheline, if we ever start emitting more commands before
9704 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9705 * then do the cacheline alignment, and finally emit the
9708 ret = intel_ring_cacheline_align(ring);
9712 ret = intel_ring_begin(ring, len);
9716 /* Unmask the flip-done completion message. Note that the bspec says that
9717 * we should do this for both the BCS and RCS, and that we must not unmask
9718 * more than one flip event at any time (or ensure that one flip message
9719 * can be sent by waiting for flip-done prior to queueing new flips).
9720 * Experimentation says that BCS works despite DERRMR masking all
9721 * flip-done completion events and that unmasking all planes at once
9722 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9723 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9725 if (ring->id == RCS) {
9726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9727 intel_ring_emit(ring, DERRMR);
9728 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9729 DERRMR_PIPEB_PRI_FLIP_DONE |
9730 DERRMR_PIPEC_PRI_FLIP_DONE));
9732 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9733 MI_SRM_LRM_GLOBAL_GTT);
9735 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9736 MI_SRM_LRM_GLOBAL_GTT);
9737 intel_ring_emit(ring, DERRMR);
9738 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9740 intel_ring_emit(ring, 0);
9741 intel_ring_emit(ring, MI_NOOP);
9745 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9746 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9747 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9748 intel_ring_emit(ring, (MI_NOOP));
9750 intel_mark_page_flip_active(intel_crtc);
9751 __intel_ring_advance(ring);
9755 static bool use_mmio_flip(struct intel_engine_cs *ring,
9756 struct drm_i915_gem_object *obj)
9759 * This is not being used for older platforms, because
9760 * non-availability of flip done interrupt forces us to use
9761 * CS flips. Older platforms derive flip done using some clever
9762 * tricks involving the flip_pending status bits and vblank irqs.
9763 * So using MMIO flips there would disrupt this mechanism.
9769 if (INTEL_INFO(ring->dev)->gen < 5)
9772 if (i915.use_mmio_flip < 0)
9774 else if (i915.use_mmio_flip > 0)
9776 else if (i915.enable_execlists)
9779 return ring != i915_gem_request_get_ring(obj->last_read_req);
9782 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9784 struct drm_device *dev = intel_crtc->base.dev;
9785 struct drm_i915_private *dev_priv = dev->dev_private;
9786 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9787 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9788 struct drm_i915_gem_object *obj = intel_fb->obj;
9789 const enum pipe pipe = intel_crtc->pipe;
9792 ctl = I915_READ(PLANE_CTL(pipe, 0));
9793 ctl &= ~PLANE_CTL_TILED_MASK;
9794 if (obj->tiling_mode == I915_TILING_X)
9795 ctl |= PLANE_CTL_TILED_X;
9798 * The stride is either expressed as a multiple of 64 bytes chunks for
9799 * linear buffers or in number of tiles for tiled buffers.
9801 stride = fb->pitches[0] >> 6;
9802 if (obj->tiling_mode == I915_TILING_X)
9803 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9806 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9807 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9809 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9810 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9812 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9813 POSTING_READ(PLANE_SURF(pipe, 0));
9816 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9818 struct drm_device *dev = intel_crtc->base.dev;
9819 struct drm_i915_private *dev_priv = dev->dev_private;
9820 struct intel_framebuffer *intel_fb =
9821 to_intel_framebuffer(intel_crtc->base.primary->fb);
9822 struct drm_i915_gem_object *obj = intel_fb->obj;
9826 reg = DSPCNTR(intel_crtc->plane);
9827 dspcntr = I915_READ(reg);
9829 if (obj->tiling_mode != I915_TILING_NONE)
9830 dspcntr |= DISPPLANE_TILED;
9832 dspcntr &= ~DISPPLANE_TILED;
9834 I915_WRITE(reg, dspcntr);
9836 I915_WRITE(DSPSURF(intel_crtc->plane),
9837 intel_crtc->unpin_work->gtt_offset);
9838 POSTING_READ(DSPSURF(intel_crtc->plane));
9843 * XXX: This is the temporary way to update the plane registers until we get
9844 * around to using the usual plane update functions for MMIO flips
9846 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9848 struct drm_device *dev = intel_crtc->base.dev;
9850 u32 start_vbl_count;
9852 intel_mark_page_flip_active(intel_crtc);
9854 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9856 if (INTEL_INFO(dev)->gen >= 9)
9857 skl_do_mmio_flip(intel_crtc);
9859 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9860 ilk_do_mmio_flip(intel_crtc);
9863 intel_pipe_update_end(intel_crtc, start_vbl_count);
9866 static void intel_mmio_flip_work_func(struct work_struct *work)
9868 struct intel_crtc *crtc =
9869 container_of(work, struct intel_crtc, mmio_flip.work);
9870 struct intel_mmio_flip *mmio_flip;
9872 mmio_flip = &crtc->mmio_flip;
9874 WARN_ON(__i915_wait_request(mmio_flip->req,
9875 crtc->reset_counter,
9876 false, NULL, NULL) != 0);
9878 intel_do_mmio_flip(crtc);
9879 if (mmio_flip->req) {
9880 mutex_lock(&crtc->base.dev->struct_mutex);
9881 i915_gem_request_assign(&mmio_flip->req, NULL);
9882 mutex_unlock(&crtc->base.dev->struct_mutex);
9886 static int intel_queue_mmio_flip(struct drm_device *dev,
9887 struct drm_crtc *crtc,
9888 struct drm_framebuffer *fb,
9889 struct drm_i915_gem_object *obj,
9890 struct intel_engine_cs *ring,
9893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9895 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9896 obj->last_write_req);
9898 schedule_work(&intel_crtc->mmio_flip.work);
9903 static int intel_default_queue_flip(struct drm_device *dev,
9904 struct drm_crtc *crtc,
9905 struct drm_framebuffer *fb,
9906 struct drm_i915_gem_object *obj,
9907 struct intel_engine_cs *ring,
9913 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9914 struct drm_crtc *crtc)
9916 struct drm_i915_private *dev_priv = dev->dev_private;
9917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9918 struct intel_unpin_work *work = intel_crtc->unpin_work;
9921 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9924 if (!work->enable_stall_check)
9927 if (work->flip_ready_vblank == 0) {
9928 if (work->flip_queued_req &&
9929 !i915_gem_request_completed(work->flip_queued_req, true))
9932 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9935 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9938 /* Potential stall - if we see that the flip has happened,
9939 * assume a missed interrupt. */
9940 if (INTEL_INFO(dev)->gen >= 4)
9941 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9943 addr = I915_READ(DSPADDR(intel_crtc->plane));
9945 /* There is a potential issue here with a false positive after a flip
9946 * to the same address. We could address this by checking for a
9947 * non-incrementing frame counter.
9949 return addr == work->gtt_offset;
9952 void intel_check_page_flip(struct drm_device *dev, int pipe)
9954 struct drm_i915_private *dev_priv = dev->dev_private;
9955 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9958 WARN_ON(!in_interrupt());
9963 spin_lock(&dev->event_lock);
9964 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9965 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9966 intel_crtc->unpin_work->flip_queued_vblank,
9967 drm_vblank_count(dev, pipe));
9968 page_flip_completed(intel_crtc);
9970 spin_unlock(&dev->event_lock);
9973 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9974 struct drm_framebuffer *fb,
9975 struct drm_pending_vblank_event *event,
9976 uint32_t page_flip_flags)
9978 struct drm_device *dev = crtc->dev;
9979 struct drm_i915_private *dev_priv = dev->dev_private;
9980 struct drm_framebuffer *old_fb = crtc->primary->fb;
9981 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9983 struct drm_plane *primary = crtc->primary;
9984 enum pipe pipe = intel_crtc->pipe;
9985 struct intel_unpin_work *work;
9986 struct intel_engine_cs *ring;
9990 * drm_mode_page_flip_ioctl() should already catch this, but double
9991 * check to be safe. In the future we may enable pageflipping from
9992 * a disabled primary plane.
9994 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9997 /* Can't change pixel format via MI display flips. */
9998 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10002 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10003 * Note that pitch changes could also affect these register.
10005 if (INTEL_INFO(dev)->gen > 3 &&
10006 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10007 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10010 if (i915_terminally_wedged(&dev_priv->gpu_error))
10013 work = kzalloc(sizeof(*work), GFP_KERNEL);
10017 work->event = event;
10019 work->old_fb = old_fb;
10020 INIT_WORK(&work->work, intel_unpin_work_fn);
10022 ret = drm_crtc_vblank_get(crtc);
10026 /* We borrow the event spin lock for protecting unpin_work */
10027 spin_lock_irq(&dev->event_lock);
10028 if (intel_crtc->unpin_work) {
10029 /* Before declaring the flip queue wedged, check if
10030 * the hardware completed the operation behind our backs.
10032 if (__intel_pageflip_stall_check(dev, crtc)) {
10033 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10034 page_flip_completed(intel_crtc);
10036 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10037 spin_unlock_irq(&dev->event_lock);
10039 drm_crtc_vblank_put(crtc);
10044 intel_crtc->unpin_work = work;
10045 spin_unlock_irq(&dev->event_lock);
10047 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10048 flush_workqueue(dev_priv->wq);
10050 /* Reference the objects for the scheduled work. */
10051 drm_framebuffer_reference(work->old_fb);
10052 drm_gem_object_reference(&obj->base);
10054 crtc->primary->fb = fb;
10055 update_state_fb(crtc->primary);
10057 work->pending_flip_obj = obj;
10059 ret = i915_mutex_lock_interruptible(dev);
10063 atomic_inc(&intel_crtc->unpin_work_count);
10064 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10066 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10067 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10069 if (IS_VALLEYVIEW(dev)) {
10070 ring = &dev_priv->ring[BCS];
10071 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10072 /* vlv: DISPLAY_FLIP fails to change tiling */
10074 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10075 ring = &dev_priv->ring[BCS];
10076 } else if (INTEL_INFO(dev)->gen >= 7) {
10077 ring = i915_gem_request_get_ring(obj->last_read_req);
10078 if (ring == NULL || ring->id != RCS)
10079 ring = &dev_priv->ring[BCS];
10081 ring = &dev_priv->ring[RCS];
10084 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10085 crtc->primary->state, ring);
10087 goto cleanup_pending;
10089 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10090 + intel_crtc->dspaddr_offset;
10092 if (use_mmio_flip(ring, obj)) {
10093 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10096 goto cleanup_unpin;
10098 i915_gem_request_assign(&work->flip_queued_req,
10099 obj->last_write_req);
10101 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10104 goto cleanup_unpin;
10106 i915_gem_request_assign(&work->flip_queued_req,
10107 intel_ring_get_request(ring));
10110 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10111 work->enable_stall_check = true;
10113 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10114 INTEL_FRONTBUFFER_PRIMARY(pipe));
10116 intel_fbc_disable(dev);
10117 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10118 mutex_unlock(&dev->struct_mutex);
10120 trace_i915_flip_request(intel_crtc->plane, obj);
10125 intel_unpin_fb_obj(fb, crtc->primary->state);
10127 atomic_dec(&intel_crtc->unpin_work_count);
10128 mutex_unlock(&dev->struct_mutex);
10130 crtc->primary->fb = old_fb;
10131 update_state_fb(crtc->primary);
10133 drm_gem_object_unreference_unlocked(&obj->base);
10134 drm_framebuffer_unreference(work->old_fb);
10136 spin_lock_irq(&dev->event_lock);
10137 intel_crtc->unpin_work = NULL;
10138 spin_unlock_irq(&dev->event_lock);
10140 drm_crtc_vblank_put(crtc);
10146 ret = intel_plane_restore(primary);
10147 if (ret == 0 && event) {
10148 spin_lock_irq(&dev->event_lock);
10149 drm_send_vblank_event(dev, pipe, event);
10150 spin_unlock_irq(&dev->event_lock);
10156 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10157 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10158 .load_lut = intel_crtc_load_lut,
10159 .atomic_begin = intel_begin_crtc_commit,
10160 .atomic_flush = intel_finish_crtc_commit,
10164 * intel_modeset_update_staged_output_state
10166 * Updates the staged output configuration state, e.g. after we've read out the
10167 * current hw state.
10169 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10171 struct intel_crtc *crtc;
10172 struct intel_encoder *encoder;
10173 struct intel_connector *connector;
10175 for_each_intel_connector(dev, connector) {
10176 connector->new_encoder =
10177 to_intel_encoder(connector->base.encoder);
10180 for_each_intel_encoder(dev, encoder) {
10181 encoder->new_crtc =
10182 to_intel_crtc(encoder->base.crtc);
10185 for_each_intel_crtc(dev, crtc) {
10186 crtc->new_enabled = crtc->base.state->enable;
10188 if (crtc->new_enabled)
10189 crtc->new_config = crtc->config;
10191 crtc->new_config = NULL;
10196 * intel_modeset_commit_output_state
10198 * This function copies the stage display pipe configuration to the real one.
10200 static void intel_modeset_commit_output_state(struct drm_device *dev)
10202 struct intel_crtc *crtc;
10203 struct intel_encoder *encoder;
10204 struct intel_connector *connector;
10206 for_each_intel_connector(dev, connector) {
10207 connector->base.encoder = &connector->new_encoder->base;
10210 for_each_intel_encoder(dev, encoder) {
10211 encoder->base.crtc = &encoder->new_crtc->base;
10214 for_each_intel_crtc(dev, crtc) {
10215 crtc->base.state->enable = crtc->new_enabled;
10216 crtc->base.enabled = crtc->new_enabled;
10221 connected_sink_compute_bpp(struct intel_connector *connector,
10222 struct intel_crtc_state *pipe_config)
10224 int bpp = pipe_config->pipe_bpp;
10226 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10227 connector->base.base.id,
10228 connector->base.name);
10230 /* Don't use an invalid EDID bpc value */
10231 if (connector->base.display_info.bpc &&
10232 connector->base.display_info.bpc * 3 < bpp) {
10233 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10234 bpp, connector->base.display_info.bpc*3);
10235 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10238 /* Clamp bpp to 8 on screens without EDID 1.4 */
10239 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10240 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10242 pipe_config->pipe_bpp = 24;
10247 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10248 struct drm_framebuffer *fb,
10249 struct intel_crtc_state *pipe_config)
10251 struct drm_device *dev = crtc->base.dev;
10252 struct intel_connector *connector;
10255 switch (fb->pixel_format) {
10256 case DRM_FORMAT_C8:
10257 bpp = 8*3; /* since we go through a colormap */
10259 case DRM_FORMAT_XRGB1555:
10260 case DRM_FORMAT_ARGB1555:
10261 /* checked in intel_framebuffer_init already */
10262 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10264 case DRM_FORMAT_RGB565:
10265 bpp = 6*3; /* min is 18bpp */
10267 case DRM_FORMAT_XBGR8888:
10268 case DRM_FORMAT_ABGR8888:
10269 /* checked in intel_framebuffer_init already */
10270 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10272 case DRM_FORMAT_XRGB8888:
10273 case DRM_FORMAT_ARGB8888:
10276 case DRM_FORMAT_XRGB2101010:
10277 case DRM_FORMAT_ARGB2101010:
10278 case DRM_FORMAT_XBGR2101010:
10279 case DRM_FORMAT_ABGR2101010:
10280 /* checked in intel_framebuffer_init already */
10281 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10285 /* TODO: gen4+ supports 16 bpc floating point, too. */
10287 DRM_DEBUG_KMS("unsupported depth\n");
10291 pipe_config->pipe_bpp = bpp;
10293 /* Clamp display bpp to EDID value */
10294 for_each_intel_connector(dev, connector) {
10295 if (!connector->new_encoder ||
10296 connector->new_encoder->new_crtc != crtc)
10299 connected_sink_compute_bpp(connector, pipe_config);
10305 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10307 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10308 "type: 0x%x flags: 0x%x\n",
10310 mode->crtc_hdisplay, mode->crtc_hsync_start,
10311 mode->crtc_hsync_end, mode->crtc_htotal,
10312 mode->crtc_vdisplay, mode->crtc_vsync_start,
10313 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10316 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10317 struct intel_crtc_state *pipe_config,
10318 const char *context)
10320 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10321 context, pipe_name(crtc->pipe));
10323 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10324 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10325 pipe_config->pipe_bpp, pipe_config->dither);
10326 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10327 pipe_config->has_pch_encoder,
10328 pipe_config->fdi_lanes,
10329 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10330 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10331 pipe_config->fdi_m_n.tu);
10332 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10333 pipe_config->has_dp_encoder,
10334 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10335 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10336 pipe_config->dp_m_n.tu);
10338 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10339 pipe_config->has_dp_encoder,
10340 pipe_config->dp_m2_n2.gmch_m,
10341 pipe_config->dp_m2_n2.gmch_n,
10342 pipe_config->dp_m2_n2.link_m,
10343 pipe_config->dp_m2_n2.link_n,
10344 pipe_config->dp_m2_n2.tu);
10346 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10347 pipe_config->has_audio,
10348 pipe_config->has_infoframe);
10350 DRM_DEBUG_KMS("requested mode:\n");
10351 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10352 DRM_DEBUG_KMS("adjusted mode:\n");
10353 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10354 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10355 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10356 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10357 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10358 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10359 pipe_config->gmch_pfit.control,
10360 pipe_config->gmch_pfit.pgm_ratios,
10361 pipe_config->gmch_pfit.lvds_border_bits);
10362 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10363 pipe_config->pch_pfit.pos,
10364 pipe_config->pch_pfit.size,
10365 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10366 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10367 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10370 static bool encoders_cloneable(const struct intel_encoder *a,
10371 const struct intel_encoder *b)
10373 /* masks could be asymmetric, so check both ways */
10374 return a == b || (a->cloneable & (1 << b->type) &&
10375 b->cloneable & (1 << a->type));
10378 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10379 struct intel_encoder *encoder)
10381 struct drm_device *dev = crtc->base.dev;
10382 struct intel_encoder *source_encoder;
10384 for_each_intel_encoder(dev, source_encoder) {
10385 if (source_encoder->new_crtc != crtc)
10388 if (!encoders_cloneable(encoder, source_encoder))
10395 static bool check_encoder_cloning(struct intel_crtc *crtc)
10397 struct drm_device *dev = crtc->base.dev;
10398 struct intel_encoder *encoder;
10400 for_each_intel_encoder(dev, encoder) {
10401 if (encoder->new_crtc != crtc)
10404 if (!check_single_encoder_cloning(crtc, encoder))
10411 static bool check_digital_port_conflicts(struct drm_device *dev)
10413 struct intel_connector *connector;
10414 unsigned int used_ports = 0;
10417 * Walk the connector list instead of the encoder
10418 * list to detect the problem on ddi platforms
10419 * where there's just one encoder per digital port.
10421 for_each_intel_connector(dev, connector) {
10422 struct intel_encoder *encoder = connector->new_encoder;
10427 WARN_ON(!encoder->new_crtc);
10429 switch (encoder->type) {
10430 unsigned int port_mask;
10431 case INTEL_OUTPUT_UNKNOWN:
10432 if (WARN_ON(!HAS_DDI(dev)))
10434 case INTEL_OUTPUT_DISPLAYPORT:
10435 case INTEL_OUTPUT_HDMI:
10436 case INTEL_OUTPUT_EDP:
10437 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10439 /* the same port mustn't appear more than once */
10440 if (used_ports & port_mask)
10443 used_ports |= port_mask;
10452 static struct intel_crtc_state *
10453 intel_modeset_pipe_config(struct drm_crtc *crtc,
10454 struct drm_framebuffer *fb,
10455 struct drm_display_mode *mode)
10457 struct drm_device *dev = crtc->dev;
10458 struct intel_encoder *encoder;
10459 struct intel_crtc_state *pipe_config;
10460 int plane_bpp, ret = -EINVAL;
10463 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10464 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10465 return ERR_PTR(-EINVAL);
10468 if (!check_digital_port_conflicts(dev)) {
10469 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10470 return ERR_PTR(-EINVAL);
10473 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10475 return ERR_PTR(-ENOMEM);
10477 pipe_config->base.crtc = crtc;
10478 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10479 drm_mode_copy(&pipe_config->base.mode, mode);
10481 pipe_config->cpu_transcoder =
10482 (enum transcoder) to_intel_crtc(crtc)->pipe;
10483 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10486 * Sanitize sync polarity flags based on requested ones. If neither
10487 * positive or negative polarity is requested, treat this as meaning
10488 * negative polarity.
10490 if (!(pipe_config->base.adjusted_mode.flags &
10491 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10492 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10494 if (!(pipe_config->base.adjusted_mode.flags &
10495 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10496 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10498 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10499 * plane pixel format and any sink constraints into account. Returns the
10500 * source plane bpp so that dithering can be selected on mismatches
10501 * after encoders and crtc also have had their say. */
10502 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10508 * Determine the real pipe dimensions. Note that stereo modes can
10509 * increase the actual pipe size due to the frame doubling and
10510 * insertion of additional space for blanks between the frame. This
10511 * is stored in the crtc timings. We use the requested mode to do this
10512 * computation to clearly distinguish it from the adjusted mode, which
10513 * can be changed by the connectors in the below retry loop.
10515 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10516 &pipe_config->pipe_src_w,
10517 &pipe_config->pipe_src_h);
10520 /* Ensure the port clock defaults are reset when retrying. */
10521 pipe_config->port_clock = 0;
10522 pipe_config->pixel_multiplier = 1;
10524 /* Fill in default crtc timings, allow encoders to overwrite them. */
10525 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10526 CRTC_STEREO_DOUBLE);
10528 /* Pass our mode to the connectors and the CRTC to give them a chance to
10529 * adjust it according to limitations or connector properties, and also
10530 * a chance to reject the mode entirely.
10532 for_each_intel_encoder(dev, encoder) {
10534 if (&encoder->new_crtc->base != crtc)
10537 if (!(encoder->compute_config(encoder, pipe_config))) {
10538 DRM_DEBUG_KMS("Encoder config failure\n");
10543 /* Set default port clock if not overwritten by the encoder. Needs to be
10544 * done afterwards in case the encoder adjusts the mode. */
10545 if (!pipe_config->port_clock)
10546 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10547 * pipe_config->pixel_multiplier;
10549 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10551 DRM_DEBUG_KMS("CRTC fixup failed\n");
10555 if (ret == RETRY) {
10556 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10561 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10563 goto encoder_retry;
10566 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10567 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10568 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10570 return pipe_config;
10572 kfree(pipe_config);
10573 return ERR_PTR(ret);
10576 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10577 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10579 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10580 unsigned *prepare_pipes, unsigned *disable_pipes)
10582 struct intel_crtc *intel_crtc;
10583 struct drm_device *dev = crtc->dev;
10584 struct intel_encoder *encoder;
10585 struct intel_connector *connector;
10586 struct drm_crtc *tmp_crtc;
10588 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10590 /* Check which crtcs have changed outputs connected to them, these need
10591 * to be part of the prepare_pipes mask. We don't (yet) support global
10592 * modeset across multiple crtcs, so modeset_pipes will only have one
10593 * bit set at most. */
10594 for_each_intel_connector(dev, connector) {
10595 if (connector->base.encoder == &connector->new_encoder->base)
10598 if (connector->base.encoder) {
10599 tmp_crtc = connector->base.encoder->crtc;
10601 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10604 if (connector->new_encoder)
10606 1 << connector->new_encoder->new_crtc->pipe;
10609 for_each_intel_encoder(dev, encoder) {
10610 if (encoder->base.crtc == &encoder->new_crtc->base)
10613 if (encoder->base.crtc) {
10614 tmp_crtc = encoder->base.crtc;
10616 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10619 if (encoder->new_crtc)
10620 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10623 /* Check for pipes that will be enabled/disabled ... */
10624 for_each_intel_crtc(dev, intel_crtc) {
10625 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10628 if (!intel_crtc->new_enabled)
10629 *disable_pipes |= 1 << intel_crtc->pipe;
10631 *prepare_pipes |= 1 << intel_crtc->pipe;
10635 /* set_mode is also used to update properties on life display pipes. */
10636 intel_crtc = to_intel_crtc(crtc);
10637 if (intel_crtc->new_enabled)
10638 *prepare_pipes |= 1 << intel_crtc->pipe;
10641 * For simplicity do a full modeset on any pipe where the output routing
10642 * changed. We could be more clever, but that would require us to be
10643 * more careful with calling the relevant encoder->mode_set functions.
10645 if (*prepare_pipes)
10646 *modeset_pipes = *prepare_pipes;
10648 /* ... and mask these out. */
10649 *modeset_pipes &= ~(*disable_pipes);
10650 *prepare_pipes &= ~(*disable_pipes);
10653 * HACK: We don't (yet) fully support global modesets. intel_set_config
10654 * obies this rule, but the modeset restore mode of
10655 * intel_modeset_setup_hw_state does not.
10657 *modeset_pipes &= 1 << intel_crtc->pipe;
10658 *prepare_pipes &= 1 << intel_crtc->pipe;
10660 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10661 *modeset_pipes, *prepare_pipes, *disable_pipes);
10664 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10666 struct drm_encoder *encoder;
10667 struct drm_device *dev = crtc->dev;
10669 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10670 if (encoder->crtc == crtc)
10677 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10679 struct drm_i915_private *dev_priv = dev->dev_private;
10680 struct intel_encoder *intel_encoder;
10681 struct intel_crtc *intel_crtc;
10682 struct drm_connector *connector;
10684 intel_shared_dpll_commit(dev_priv);
10686 for_each_intel_encoder(dev, intel_encoder) {
10687 if (!intel_encoder->base.crtc)
10690 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10692 if (prepare_pipes & (1 << intel_crtc->pipe))
10693 intel_encoder->connectors_active = false;
10696 intel_modeset_commit_output_state(dev);
10698 /* Double check state. */
10699 for_each_intel_crtc(dev, intel_crtc) {
10700 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10701 WARN_ON(intel_crtc->new_config &&
10702 intel_crtc->new_config != intel_crtc->config);
10703 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10706 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10707 if (!connector->encoder || !connector->encoder->crtc)
10710 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10712 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10713 struct drm_property *dpms_property =
10714 dev->mode_config.dpms_property;
10716 connector->dpms = DRM_MODE_DPMS_ON;
10717 drm_object_property_set_value(&connector->base,
10721 intel_encoder = to_intel_encoder(connector->encoder);
10722 intel_encoder->connectors_active = true;
10728 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10732 if (clock1 == clock2)
10735 if (!clock1 || !clock2)
10738 diff = abs(clock1 - clock2);
10740 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10746 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10747 list_for_each_entry((intel_crtc), \
10748 &(dev)->mode_config.crtc_list, \
10750 if (mask & (1 <<(intel_crtc)->pipe))
10753 intel_pipe_config_compare(struct drm_device *dev,
10754 struct intel_crtc_state *current_config,
10755 struct intel_crtc_state *pipe_config)
10757 #define PIPE_CONF_CHECK_X(name) \
10758 if (current_config->name != pipe_config->name) { \
10759 DRM_ERROR("mismatch in " #name " " \
10760 "(expected 0x%08x, found 0x%08x)\n", \
10761 current_config->name, \
10762 pipe_config->name); \
10766 #define PIPE_CONF_CHECK_I(name) \
10767 if (current_config->name != pipe_config->name) { \
10768 DRM_ERROR("mismatch in " #name " " \
10769 "(expected %i, found %i)\n", \
10770 current_config->name, \
10771 pipe_config->name); \
10775 /* This is required for BDW+ where there is only one set of registers for
10776 * switching between high and low RR.
10777 * This macro can be used whenever a comparison has to be made between one
10778 * hw state and multiple sw state variables.
10780 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10781 if ((current_config->name != pipe_config->name) && \
10782 (current_config->alt_name != pipe_config->name)) { \
10783 DRM_ERROR("mismatch in " #name " " \
10784 "(expected %i or %i, found %i)\n", \
10785 current_config->name, \
10786 current_config->alt_name, \
10787 pipe_config->name); \
10791 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10792 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10793 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10794 "(expected %i, found %i)\n", \
10795 current_config->name & (mask), \
10796 pipe_config->name & (mask)); \
10800 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10801 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10802 DRM_ERROR("mismatch in " #name " " \
10803 "(expected %i, found %i)\n", \
10804 current_config->name, \
10805 pipe_config->name); \
10809 #define PIPE_CONF_QUIRK(quirk) \
10810 ((current_config->quirks | pipe_config->quirks) & (quirk))
10812 PIPE_CONF_CHECK_I(cpu_transcoder);
10814 PIPE_CONF_CHECK_I(has_pch_encoder);
10815 PIPE_CONF_CHECK_I(fdi_lanes);
10816 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10817 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10818 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10819 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10820 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10822 PIPE_CONF_CHECK_I(has_dp_encoder);
10824 if (INTEL_INFO(dev)->gen < 8) {
10825 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10826 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10827 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10828 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10829 PIPE_CONF_CHECK_I(dp_m_n.tu);
10831 if (current_config->has_drrs) {
10832 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10833 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10834 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10835 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10836 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10839 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10840 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10841 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10842 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10843 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10846 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10847 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10848 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10849 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10850 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10851 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10853 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10854 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10855 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10856 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10857 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10858 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10860 PIPE_CONF_CHECK_I(pixel_multiplier);
10861 PIPE_CONF_CHECK_I(has_hdmi_sink);
10862 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10863 IS_VALLEYVIEW(dev))
10864 PIPE_CONF_CHECK_I(limited_color_range);
10865 PIPE_CONF_CHECK_I(has_infoframe);
10867 PIPE_CONF_CHECK_I(has_audio);
10869 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10870 DRM_MODE_FLAG_INTERLACE);
10872 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10873 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10874 DRM_MODE_FLAG_PHSYNC);
10875 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10876 DRM_MODE_FLAG_NHSYNC);
10877 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10878 DRM_MODE_FLAG_PVSYNC);
10879 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10880 DRM_MODE_FLAG_NVSYNC);
10883 PIPE_CONF_CHECK_I(pipe_src_w);
10884 PIPE_CONF_CHECK_I(pipe_src_h);
10887 * FIXME: BIOS likes to set up a cloned config with lvds+external
10888 * screen. Since we don't yet re-compute the pipe config when moving
10889 * just the lvds port away to another pipe the sw tracking won't match.
10891 * Proper atomic modesets with recomputed global state will fix this.
10892 * Until then just don't check gmch state for inherited modes.
10894 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10895 PIPE_CONF_CHECK_I(gmch_pfit.control);
10896 /* pfit ratios are autocomputed by the hw on gen4+ */
10897 if (INTEL_INFO(dev)->gen < 4)
10898 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10899 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10902 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10903 if (current_config->pch_pfit.enabled) {
10904 PIPE_CONF_CHECK_I(pch_pfit.pos);
10905 PIPE_CONF_CHECK_I(pch_pfit.size);
10908 /* BDW+ don't expose a synchronous way to read the state */
10909 if (IS_HASWELL(dev))
10910 PIPE_CONF_CHECK_I(ips_enabled);
10912 PIPE_CONF_CHECK_I(double_wide);
10914 PIPE_CONF_CHECK_X(ddi_pll_sel);
10916 PIPE_CONF_CHECK_I(shared_dpll);
10917 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10918 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10919 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10920 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10921 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10922 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10923 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10924 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10926 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10927 PIPE_CONF_CHECK_I(pipe_bpp);
10929 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10930 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10932 #undef PIPE_CONF_CHECK_X
10933 #undef PIPE_CONF_CHECK_I
10934 #undef PIPE_CONF_CHECK_I_ALT
10935 #undef PIPE_CONF_CHECK_FLAGS
10936 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10937 #undef PIPE_CONF_QUIRK
10942 static void check_wm_state(struct drm_device *dev)
10944 struct drm_i915_private *dev_priv = dev->dev_private;
10945 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10946 struct intel_crtc *intel_crtc;
10949 if (INTEL_INFO(dev)->gen < 9)
10952 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10953 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10955 for_each_intel_crtc(dev, intel_crtc) {
10956 struct skl_ddb_entry *hw_entry, *sw_entry;
10957 const enum pipe pipe = intel_crtc->pipe;
10959 if (!intel_crtc->active)
10963 for_each_plane(dev_priv, pipe, plane) {
10964 hw_entry = &hw_ddb.plane[pipe][plane];
10965 sw_entry = &sw_ddb->plane[pipe][plane];
10967 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10970 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10971 "(expected (%u,%u), found (%u,%u))\n",
10972 pipe_name(pipe), plane + 1,
10973 sw_entry->start, sw_entry->end,
10974 hw_entry->start, hw_entry->end);
10978 hw_entry = &hw_ddb.cursor[pipe];
10979 sw_entry = &sw_ddb->cursor[pipe];
10981 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10984 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10985 "(expected (%u,%u), found (%u,%u))\n",
10987 sw_entry->start, sw_entry->end,
10988 hw_entry->start, hw_entry->end);
10993 check_connector_state(struct drm_device *dev)
10995 struct intel_connector *connector;
10997 for_each_intel_connector(dev, connector) {
10998 /* This also checks the encoder/connector hw state with the
10999 * ->get_hw_state callbacks. */
11000 intel_connector_check_state(connector);
11002 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11003 "connector's staged encoder doesn't match current encoder\n");
11008 check_encoder_state(struct drm_device *dev)
11010 struct intel_encoder *encoder;
11011 struct intel_connector *connector;
11013 for_each_intel_encoder(dev, encoder) {
11014 bool enabled = false;
11015 bool active = false;
11016 enum pipe pipe, tracked_pipe;
11018 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11019 encoder->base.base.id,
11020 encoder->base.name);
11022 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11023 "encoder's stage crtc doesn't match current crtc\n");
11024 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11025 "encoder's active_connectors set, but no crtc\n");
11027 for_each_intel_connector(dev, connector) {
11028 if (connector->base.encoder != &encoder->base)
11031 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11035 * for MST connectors if we unplug the connector is gone
11036 * away but the encoder is still connected to a crtc
11037 * until a modeset happens in response to the hotplug.
11039 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11042 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11043 "encoder's enabled state mismatch "
11044 "(expected %i, found %i)\n",
11045 !!encoder->base.crtc, enabled);
11046 I915_STATE_WARN(active && !encoder->base.crtc,
11047 "active encoder with no crtc\n");
11049 I915_STATE_WARN(encoder->connectors_active != active,
11050 "encoder's computed active state doesn't match tracked active state "
11051 "(expected %i, found %i)\n", active, encoder->connectors_active);
11053 active = encoder->get_hw_state(encoder, &pipe);
11054 I915_STATE_WARN(active != encoder->connectors_active,
11055 "encoder's hw state doesn't match sw tracking "
11056 "(expected %i, found %i)\n",
11057 encoder->connectors_active, active);
11059 if (!encoder->base.crtc)
11062 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11063 I915_STATE_WARN(active && pipe != tracked_pipe,
11064 "active encoder's pipe doesn't match"
11065 "(expected %i, found %i)\n",
11066 tracked_pipe, pipe);
11072 check_crtc_state(struct drm_device *dev)
11074 struct drm_i915_private *dev_priv = dev->dev_private;
11075 struct intel_crtc *crtc;
11076 struct intel_encoder *encoder;
11077 struct intel_crtc_state pipe_config;
11079 for_each_intel_crtc(dev, crtc) {
11080 bool enabled = false;
11081 bool active = false;
11083 memset(&pipe_config, 0, sizeof(pipe_config));
11085 DRM_DEBUG_KMS("[CRTC:%d]\n",
11086 crtc->base.base.id);
11088 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11089 "active crtc, but not enabled in sw tracking\n");
11091 for_each_intel_encoder(dev, encoder) {
11092 if (encoder->base.crtc != &crtc->base)
11095 if (encoder->connectors_active)
11099 I915_STATE_WARN(active != crtc->active,
11100 "crtc's computed active state doesn't match tracked active state "
11101 "(expected %i, found %i)\n", active, crtc->active);
11102 I915_STATE_WARN(enabled != crtc->base.state->enable,
11103 "crtc's computed enabled state doesn't match tracked enabled state "
11104 "(expected %i, found %i)\n", enabled,
11105 crtc->base.state->enable);
11107 active = dev_priv->display.get_pipe_config(crtc,
11110 /* hw state is inconsistent with the pipe quirk */
11111 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11112 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11113 active = crtc->active;
11115 for_each_intel_encoder(dev, encoder) {
11117 if (encoder->base.crtc != &crtc->base)
11119 if (encoder->get_hw_state(encoder, &pipe))
11120 encoder->get_config(encoder, &pipe_config);
11123 I915_STATE_WARN(crtc->active != active,
11124 "crtc active state doesn't match with hw state "
11125 "(expected %i, found %i)\n", crtc->active, active);
11128 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11129 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11130 intel_dump_pipe_config(crtc, &pipe_config,
11132 intel_dump_pipe_config(crtc, crtc->config,
11139 check_shared_dpll_state(struct drm_device *dev)
11141 struct drm_i915_private *dev_priv = dev->dev_private;
11142 struct intel_crtc *crtc;
11143 struct intel_dpll_hw_state dpll_hw_state;
11146 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11147 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11148 int enabled_crtcs = 0, active_crtcs = 0;
11151 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11153 DRM_DEBUG_KMS("%s\n", pll->name);
11155 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11157 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11158 "more active pll users than references: %i vs %i\n",
11159 pll->active, hweight32(pll->config.crtc_mask));
11160 I915_STATE_WARN(pll->active && !pll->on,
11161 "pll in active use but not on in sw tracking\n");
11162 I915_STATE_WARN(pll->on && !pll->active,
11163 "pll in on but not on in use in sw tracking\n");
11164 I915_STATE_WARN(pll->on != active,
11165 "pll on state mismatch (expected %i, found %i)\n",
11168 for_each_intel_crtc(dev, crtc) {
11169 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11171 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11174 I915_STATE_WARN(pll->active != active_crtcs,
11175 "pll active crtcs mismatch (expected %i, found %i)\n",
11176 pll->active, active_crtcs);
11177 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11178 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11179 hweight32(pll->config.crtc_mask), enabled_crtcs);
11181 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11182 sizeof(dpll_hw_state)),
11183 "pll hw state mismatch\n");
11188 intel_modeset_check_state(struct drm_device *dev)
11190 check_wm_state(dev);
11191 check_connector_state(dev);
11192 check_encoder_state(dev);
11193 check_crtc_state(dev);
11194 check_shared_dpll_state(dev);
11197 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11201 * FDI already provided one idea for the dotclock.
11202 * Yell if the encoder disagrees.
11204 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11205 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11206 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11209 static void update_scanline_offset(struct intel_crtc *crtc)
11211 struct drm_device *dev = crtc->base.dev;
11214 * The scanline counter increments at the leading edge of hsync.
11216 * On most platforms it starts counting from vtotal-1 on the
11217 * first active line. That means the scanline counter value is
11218 * always one less than what we would expect. Ie. just after
11219 * start of vblank, which also occurs at start of hsync (on the
11220 * last active line), the scanline counter will read vblank_start-1.
11222 * On gen2 the scanline counter starts counting from 1 instead
11223 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11224 * to keep the value positive), instead of adding one.
11226 * On HSW+ the behaviour of the scanline counter depends on the output
11227 * type. For DP ports it behaves like most other platforms, but on HDMI
11228 * there's an extra 1 line difference. So we need to add two instead of
11229 * one to the value.
11231 if (IS_GEN2(dev)) {
11232 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11235 vtotal = mode->crtc_vtotal;
11236 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11239 crtc->scanline_offset = vtotal - 1;
11240 } else if (HAS_DDI(dev) &&
11241 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11242 crtc->scanline_offset = 2;
11244 crtc->scanline_offset = 1;
11247 static struct intel_crtc_state *
11248 intel_modeset_compute_config(struct drm_crtc *crtc,
11249 struct drm_display_mode *mode,
11250 struct drm_framebuffer *fb,
11251 unsigned *modeset_pipes,
11252 unsigned *prepare_pipes,
11253 unsigned *disable_pipes)
11255 struct intel_crtc_state *pipe_config = NULL;
11257 intel_modeset_affected_pipes(crtc, modeset_pipes,
11258 prepare_pipes, disable_pipes);
11260 if ((*modeset_pipes) == 0)
11264 * Note this needs changes when we start tracking multiple modes
11265 * and crtcs. At that point we'll need to compute the whole config
11266 * (i.e. one pipe_config for each crtc) rather than just the one
11269 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11270 if (IS_ERR(pipe_config)) {
11273 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11277 return pipe_config;
11280 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11281 unsigned modeset_pipes,
11282 unsigned disable_pipes)
11284 struct drm_i915_private *dev_priv = to_i915(dev);
11285 unsigned clear_pipes = modeset_pipes | disable_pipes;
11286 struct intel_crtc *intel_crtc;
11289 if (!dev_priv->display.crtc_compute_clock)
11292 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11296 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11297 struct intel_crtc_state *state = intel_crtc->new_config;
11298 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11301 intel_shared_dpll_abort_config(dev_priv);
11310 static int __intel_set_mode(struct drm_crtc *crtc,
11311 struct drm_display_mode *mode,
11312 int x, int y, struct drm_framebuffer *fb,
11313 struct intel_crtc_state *pipe_config,
11314 unsigned modeset_pipes,
11315 unsigned prepare_pipes,
11316 unsigned disable_pipes)
11318 struct drm_device *dev = crtc->dev;
11319 struct drm_i915_private *dev_priv = dev->dev_private;
11320 struct drm_display_mode *saved_mode;
11321 struct intel_crtc *intel_crtc;
11324 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11328 *saved_mode = crtc->mode;
11331 to_intel_crtc(crtc)->new_config = pipe_config;
11334 * See if the config requires any additional preparation, e.g.
11335 * to adjust global state with pipes off. We need to do this
11336 * here so we can get the modeset_pipe updated config for the new
11337 * mode set on this crtc. For other crtcs we need to use the
11338 * adjusted_mode bits in the crtc directly.
11340 if (IS_VALLEYVIEW(dev)) {
11341 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11343 /* may have added more to prepare_pipes than we should */
11344 prepare_pipes &= ~disable_pipes;
11347 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11351 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11352 intel_crtc_disable(&intel_crtc->base);
11354 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11355 if (intel_crtc->base.state->enable)
11356 dev_priv->display.crtc_disable(&intel_crtc->base);
11359 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11360 * to set it here already despite that we pass it down the callchain.
11362 * Note we'll need to fix this up when we start tracking multiple
11363 * pipes; here we assume a single modeset_pipe and only track the
11364 * single crtc and mode.
11366 if (modeset_pipes) {
11367 crtc->mode = *mode;
11368 /* mode_set/enable/disable functions rely on a correct pipe
11370 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11373 * Calculate and store various constants which
11374 * are later needed by vblank and swap-completion
11375 * timestamping. They are derived from true hwmode.
11377 drm_calc_timestamping_constants(crtc,
11378 &pipe_config->base.adjusted_mode);
11381 /* Only after disabling all output pipelines that will be changed can we
11382 * update the the output configuration. */
11383 intel_modeset_update_state(dev, prepare_pipes);
11385 modeset_update_crtc_power_domains(dev);
11387 /* Set up the DPLL and any encoders state that needs to adjust or depend
11390 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11391 struct drm_plane *primary = intel_crtc->base.primary;
11392 int vdisplay, hdisplay;
11394 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11395 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11397 hdisplay, vdisplay,
11399 hdisplay << 16, vdisplay << 16);
11402 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11403 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11404 update_scanline_offset(intel_crtc);
11406 dev_priv->display.crtc_enable(&intel_crtc->base);
11409 /* FIXME: add subpixel order */
11411 if (ret && crtc->state->enable)
11412 crtc->mode = *saved_mode;
11418 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11419 struct drm_display_mode *mode,
11420 int x, int y, struct drm_framebuffer *fb,
11421 struct intel_crtc_state *pipe_config,
11422 unsigned modeset_pipes,
11423 unsigned prepare_pipes,
11424 unsigned disable_pipes)
11428 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11429 prepare_pipes, disable_pipes);
11432 intel_modeset_check_state(crtc->dev);
11437 static int intel_set_mode(struct drm_crtc *crtc,
11438 struct drm_display_mode *mode,
11439 int x, int y, struct drm_framebuffer *fb)
11441 struct intel_crtc_state *pipe_config;
11442 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11444 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11449 if (IS_ERR(pipe_config))
11450 return PTR_ERR(pipe_config);
11452 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11453 modeset_pipes, prepare_pipes,
11457 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11459 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11462 #undef for_each_intel_crtc_masked
11464 static void intel_set_config_free(struct intel_set_config *config)
11469 kfree(config->save_connector_encoders);
11470 kfree(config->save_encoder_crtcs);
11471 kfree(config->save_crtc_enabled);
11475 static int intel_set_config_save_state(struct drm_device *dev,
11476 struct intel_set_config *config)
11478 struct drm_crtc *crtc;
11479 struct drm_encoder *encoder;
11480 struct drm_connector *connector;
11483 config->save_crtc_enabled =
11484 kcalloc(dev->mode_config.num_crtc,
11485 sizeof(bool), GFP_KERNEL);
11486 if (!config->save_crtc_enabled)
11489 config->save_encoder_crtcs =
11490 kcalloc(dev->mode_config.num_encoder,
11491 sizeof(struct drm_crtc *), GFP_KERNEL);
11492 if (!config->save_encoder_crtcs)
11495 config->save_connector_encoders =
11496 kcalloc(dev->mode_config.num_connector,
11497 sizeof(struct drm_encoder *), GFP_KERNEL);
11498 if (!config->save_connector_encoders)
11501 /* Copy data. Note that driver private data is not affected.
11502 * Should anything bad happen only the expected state is
11503 * restored, not the drivers personal bookkeeping.
11506 for_each_crtc(dev, crtc) {
11507 config->save_crtc_enabled[count++] = crtc->state->enable;
11511 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11512 config->save_encoder_crtcs[count++] = encoder->crtc;
11516 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11517 config->save_connector_encoders[count++] = connector->encoder;
11523 static void intel_set_config_restore_state(struct drm_device *dev,
11524 struct intel_set_config *config)
11526 struct intel_crtc *crtc;
11527 struct intel_encoder *encoder;
11528 struct intel_connector *connector;
11532 for_each_intel_crtc(dev, crtc) {
11533 crtc->new_enabled = config->save_crtc_enabled[count++];
11535 if (crtc->new_enabled)
11536 crtc->new_config = crtc->config;
11538 crtc->new_config = NULL;
11542 for_each_intel_encoder(dev, encoder) {
11543 encoder->new_crtc =
11544 to_intel_crtc(config->save_encoder_crtcs[count++]);
11548 for_each_intel_connector(dev, connector) {
11549 connector->new_encoder =
11550 to_intel_encoder(config->save_connector_encoders[count++]);
11555 is_crtc_connector_off(struct drm_mode_set *set)
11559 if (set->num_connectors == 0)
11562 if (WARN_ON(set->connectors == NULL))
11565 for (i = 0; i < set->num_connectors; i++)
11566 if (set->connectors[i]->encoder &&
11567 set->connectors[i]->encoder->crtc == set->crtc &&
11568 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11575 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11576 struct intel_set_config *config)
11579 /* We should be able to check here if the fb has the same properties
11580 * and then just flip_or_move it */
11581 if (is_crtc_connector_off(set)) {
11582 config->mode_changed = true;
11583 } else if (set->crtc->primary->fb != set->fb) {
11585 * If we have no fb, we can only flip as long as the crtc is
11586 * active, otherwise we need a full mode set. The crtc may
11587 * be active if we've only disabled the primary plane, or
11588 * in fastboot situations.
11590 if (set->crtc->primary->fb == NULL) {
11591 struct intel_crtc *intel_crtc =
11592 to_intel_crtc(set->crtc);
11594 if (intel_crtc->active) {
11595 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11596 config->fb_changed = true;
11598 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11599 config->mode_changed = true;
11601 } else if (set->fb == NULL) {
11602 config->mode_changed = true;
11603 } else if (set->fb->pixel_format !=
11604 set->crtc->primary->fb->pixel_format) {
11605 config->mode_changed = true;
11607 config->fb_changed = true;
11611 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11612 config->fb_changed = true;
11614 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11615 DRM_DEBUG_KMS("modes are different, full mode set\n");
11616 drm_mode_debug_printmodeline(&set->crtc->mode);
11617 drm_mode_debug_printmodeline(set->mode);
11618 config->mode_changed = true;
11621 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11622 set->crtc->base.id, config->mode_changed, config->fb_changed);
11626 intel_modeset_stage_output_state(struct drm_device *dev,
11627 struct drm_mode_set *set,
11628 struct intel_set_config *config)
11630 struct intel_connector *connector;
11631 struct intel_encoder *encoder;
11632 struct intel_crtc *crtc;
11635 /* The upper layers ensure that we either disable a crtc or have a list
11636 * of connectors. For paranoia, double-check this. */
11637 WARN_ON(!set->fb && (set->num_connectors != 0));
11638 WARN_ON(set->fb && (set->num_connectors == 0));
11640 for_each_intel_connector(dev, connector) {
11641 /* Otherwise traverse passed in connector list and get encoders
11643 for (ro = 0; ro < set->num_connectors; ro++) {
11644 if (set->connectors[ro] == &connector->base) {
11645 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11650 /* If we disable the crtc, disable all its connectors. Also, if
11651 * the connector is on the changing crtc but not on the new
11652 * connector list, disable it. */
11653 if ((!set->fb || ro == set->num_connectors) &&
11654 connector->base.encoder &&
11655 connector->base.encoder->crtc == set->crtc) {
11656 connector->new_encoder = NULL;
11658 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11659 connector->base.base.id,
11660 connector->base.name);
11664 if (&connector->new_encoder->base != connector->base.encoder) {
11665 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11666 connector->base.base.id,
11667 connector->base.name);
11668 config->mode_changed = true;
11671 /* connector->new_encoder is now updated for all connectors. */
11673 /* Update crtc of enabled connectors. */
11674 for_each_intel_connector(dev, connector) {
11675 struct drm_crtc *new_crtc;
11677 if (!connector->new_encoder)
11680 new_crtc = connector->new_encoder->base.crtc;
11682 for (ro = 0; ro < set->num_connectors; ro++) {
11683 if (set->connectors[ro] == &connector->base)
11684 new_crtc = set->crtc;
11687 /* Make sure the new CRTC will work with the encoder */
11688 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11692 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11694 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11695 connector->base.base.id,
11696 connector->base.name,
11697 new_crtc->base.id);
11700 /* Check for any encoders that needs to be disabled. */
11701 for_each_intel_encoder(dev, encoder) {
11702 int num_connectors = 0;
11703 for_each_intel_connector(dev, connector) {
11704 if (connector->new_encoder == encoder) {
11705 WARN_ON(!connector->new_encoder->new_crtc);
11710 if (num_connectors == 0)
11711 encoder->new_crtc = NULL;
11712 else if (num_connectors > 1)
11715 /* Only now check for crtc changes so we don't miss encoders
11716 * that will be disabled. */
11717 if (&encoder->new_crtc->base != encoder->base.crtc) {
11718 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11719 encoder->base.base.id,
11720 encoder->base.name);
11721 config->mode_changed = true;
11724 /* Now we've also updated encoder->new_crtc for all encoders. */
11725 for_each_intel_connector(dev, connector) {
11726 if (connector->new_encoder)
11727 if (connector->new_encoder != connector->encoder)
11728 connector->encoder = connector->new_encoder;
11730 for_each_intel_crtc(dev, crtc) {
11731 crtc->new_enabled = false;
11733 for_each_intel_encoder(dev, encoder) {
11734 if (encoder->new_crtc == crtc) {
11735 crtc->new_enabled = true;
11740 if (crtc->new_enabled != crtc->base.state->enable) {
11741 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11742 crtc->base.base.id,
11743 crtc->new_enabled ? "en" : "dis");
11744 config->mode_changed = true;
11747 if (crtc->new_enabled)
11748 crtc->new_config = crtc->config;
11750 crtc->new_config = NULL;
11756 static void disable_crtc_nofb(struct intel_crtc *crtc)
11758 struct drm_device *dev = crtc->base.dev;
11759 struct intel_encoder *encoder;
11760 struct intel_connector *connector;
11762 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11763 pipe_name(crtc->pipe));
11765 for_each_intel_connector(dev, connector) {
11766 if (connector->new_encoder &&
11767 connector->new_encoder->new_crtc == crtc)
11768 connector->new_encoder = NULL;
11771 for_each_intel_encoder(dev, encoder) {
11772 if (encoder->new_crtc == crtc)
11773 encoder->new_crtc = NULL;
11776 crtc->new_enabled = false;
11777 crtc->new_config = NULL;
11780 static int intel_crtc_set_config(struct drm_mode_set *set)
11782 struct drm_device *dev;
11783 struct drm_mode_set save_set;
11784 struct intel_set_config *config;
11785 struct intel_crtc_state *pipe_config;
11786 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11790 BUG_ON(!set->crtc);
11791 BUG_ON(!set->crtc->helper_private);
11793 /* Enforce sane interface api - has been abused by the fb helper. */
11794 BUG_ON(!set->mode && set->fb);
11795 BUG_ON(set->fb && set->num_connectors == 0);
11798 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11799 set->crtc->base.id, set->fb->base.id,
11800 (int)set->num_connectors, set->x, set->y);
11802 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11805 dev = set->crtc->dev;
11808 config = kzalloc(sizeof(*config), GFP_KERNEL);
11812 ret = intel_set_config_save_state(dev, config);
11816 save_set.crtc = set->crtc;
11817 save_set.mode = &set->crtc->mode;
11818 save_set.x = set->crtc->x;
11819 save_set.y = set->crtc->y;
11820 save_set.fb = set->crtc->primary->fb;
11822 /* Compute whether we need a full modeset, only an fb base update or no
11823 * change at all. In the future we might also check whether only the
11824 * mode changed, e.g. for LVDS where we only change the panel fitter in
11826 intel_set_config_compute_mode_changes(set, config);
11828 ret = intel_modeset_stage_output_state(dev, set, config);
11832 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11837 if (IS_ERR(pipe_config)) {
11838 ret = PTR_ERR(pipe_config);
11840 } else if (pipe_config) {
11841 if (pipe_config->has_audio !=
11842 to_intel_crtc(set->crtc)->config->has_audio)
11843 config->mode_changed = true;
11846 * Note we have an issue here with infoframes: current code
11847 * only updates them on the full mode set path per hw
11848 * requirements. So here we should be checking for any
11849 * required changes and forcing a mode set.
11853 /* set_mode will free it in the mode_changed case */
11854 if (!config->mode_changed)
11855 kfree(pipe_config);
11857 intel_update_pipe_size(to_intel_crtc(set->crtc));
11859 if (config->mode_changed) {
11860 ret = intel_set_mode_pipes(set->crtc, set->mode,
11861 set->x, set->y, set->fb, pipe_config,
11862 modeset_pipes, prepare_pipes,
11864 } else if (config->fb_changed) {
11865 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11866 struct drm_plane *primary = set->crtc->primary;
11867 int vdisplay, hdisplay;
11869 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11870 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11871 0, 0, hdisplay, vdisplay,
11872 set->x << 16, set->y << 16,
11873 hdisplay << 16, vdisplay << 16);
11876 * We need to make sure the primary plane is re-enabled if it
11877 * has previously been turned off.
11879 if (!intel_crtc->primary_enabled && ret == 0) {
11880 WARN_ON(!intel_crtc->active);
11881 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11885 * In the fastboot case this may be our only check of the
11886 * state after boot. It would be better to only do it on
11887 * the first update, but we don't have a nice way of doing that
11888 * (and really, set_config isn't used much for high freq page
11889 * flipping, so increasing its cost here shouldn't be a big
11892 if (i915.fastboot && ret == 0)
11893 intel_modeset_check_state(set->crtc->dev);
11897 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11898 set->crtc->base.id, ret);
11900 intel_set_config_restore_state(dev, config);
11903 * HACK: if the pipe was on, but we didn't have a framebuffer,
11904 * force the pipe off to avoid oopsing in the modeset code
11905 * due to fb==NULL. This should only happen during boot since
11906 * we don't yet reconstruct the FB from the hardware state.
11908 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11909 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11911 /* Try to restore the config */
11912 if (config->mode_changed &&
11913 intel_set_mode(save_set.crtc, save_set.mode,
11914 save_set.x, save_set.y, save_set.fb))
11915 DRM_ERROR("failed to restore config after modeset failure\n");
11919 intel_set_config_free(config);
11923 static const struct drm_crtc_funcs intel_crtc_funcs = {
11924 .gamma_set = intel_crtc_gamma_set,
11925 .set_config = intel_crtc_set_config,
11926 .destroy = intel_crtc_destroy,
11927 .page_flip = intel_crtc_page_flip,
11928 .atomic_duplicate_state = intel_crtc_duplicate_state,
11929 .atomic_destroy_state = intel_crtc_destroy_state,
11932 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11933 struct intel_shared_dpll *pll,
11934 struct intel_dpll_hw_state *hw_state)
11938 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11941 val = I915_READ(PCH_DPLL(pll->id));
11942 hw_state->dpll = val;
11943 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11944 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11946 return val & DPLL_VCO_ENABLE;
11949 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11950 struct intel_shared_dpll *pll)
11952 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11953 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11956 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11957 struct intel_shared_dpll *pll)
11959 /* PCH refclock must be enabled first */
11960 ibx_assert_pch_refclk_enabled(dev_priv);
11962 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11964 /* Wait for the clocks to stabilize. */
11965 POSTING_READ(PCH_DPLL(pll->id));
11968 /* The pixel multiplier can only be updated once the
11969 * DPLL is enabled and the clocks are stable.
11971 * So write it again.
11973 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11974 POSTING_READ(PCH_DPLL(pll->id));
11978 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11979 struct intel_shared_dpll *pll)
11981 struct drm_device *dev = dev_priv->dev;
11982 struct intel_crtc *crtc;
11984 /* Make sure no transcoder isn't still depending on us. */
11985 for_each_intel_crtc(dev, crtc) {
11986 if (intel_crtc_to_shared_dpll(crtc) == pll)
11987 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11990 I915_WRITE(PCH_DPLL(pll->id), 0);
11991 POSTING_READ(PCH_DPLL(pll->id));
11995 static char *ibx_pch_dpll_names[] = {
12000 static void ibx_pch_dpll_init(struct drm_device *dev)
12002 struct drm_i915_private *dev_priv = dev->dev_private;
12005 dev_priv->num_shared_dpll = 2;
12007 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12008 dev_priv->shared_dplls[i].id = i;
12009 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12010 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12011 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12012 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12013 dev_priv->shared_dplls[i].get_hw_state =
12014 ibx_pch_dpll_get_hw_state;
12018 static void intel_shared_dpll_init(struct drm_device *dev)
12020 struct drm_i915_private *dev_priv = dev->dev_private;
12023 intel_ddi_pll_init(dev);
12024 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12025 ibx_pch_dpll_init(dev);
12027 dev_priv->num_shared_dpll = 0;
12029 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12033 * intel_wm_need_update - Check whether watermarks need updating
12034 * @plane: drm plane
12035 * @state: new plane state
12037 * Check current plane state versus the new one to determine whether
12038 * watermarks need to be recalculated.
12040 * Returns true or false.
12042 bool intel_wm_need_update(struct drm_plane *plane,
12043 struct drm_plane_state *state)
12045 /* Update watermarks on tiling changes. */
12046 if (!plane->state->fb || !state->fb ||
12047 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12048 plane->state->rotation != state->rotation)
12055 * intel_prepare_plane_fb - Prepare fb for usage on plane
12056 * @plane: drm plane to prepare for
12057 * @fb: framebuffer to prepare for presentation
12059 * Prepares a framebuffer for usage on a display plane. Generally this
12060 * involves pinning the underlying object and updating the frontbuffer tracking
12061 * bits. Some older platforms need special physical address handling for
12064 * Returns 0 on success, negative error code on failure.
12067 intel_prepare_plane_fb(struct drm_plane *plane,
12068 struct drm_framebuffer *fb,
12069 const struct drm_plane_state *new_state)
12071 struct drm_device *dev = plane->dev;
12072 struct intel_plane *intel_plane = to_intel_plane(plane);
12073 enum pipe pipe = intel_plane->pipe;
12074 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12075 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12076 unsigned frontbuffer_bits = 0;
12082 switch (plane->type) {
12083 case DRM_PLANE_TYPE_PRIMARY:
12084 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12086 case DRM_PLANE_TYPE_CURSOR:
12087 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12089 case DRM_PLANE_TYPE_OVERLAY:
12090 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12094 mutex_lock(&dev->struct_mutex);
12096 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12097 INTEL_INFO(dev)->cursor_needs_physical) {
12098 int align = IS_I830(dev) ? 16 * 1024 : 256;
12099 ret = i915_gem_object_attach_phys(obj, align);
12101 DRM_DEBUG_KMS("failed to attach phys object\n");
12103 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12107 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12109 mutex_unlock(&dev->struct_mutex);
12115 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12116 * @plane: drm plane to clean up for
12117 * @fb: old framebuffer that was on plane
12119 * Cleans up a framebuffer that has just been removed from a plane.
12122 intel_cleanup_plane_fb(struct drm_plane *plane,
12123 struct drm_framebuffer *fb,
12124 const struct drm_plane_state *old_state)
12126 struct drm_device *dev = plane->dev;
12127 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12132 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12133 !INTEL_INFO(dev)->cursor_needs_physical) {
12134 mutex_lock(&dev->struct_mutex);
12135 intel_unpin_fb_obj(fb, old_state);
12136 mutex_unlock(&dev->struct_mutex);
12141 intel_check_primary_plane(struct drm_plane *plane,
12142 struct intel_plane_state *state)
12144 struct drm_device *dev = plane->dev;
12145 struct drm_i915_private *dev_priv = dev->dev_private;
12146 struct drm_crtc *crtc = state->base.crtc;
12147 struct intel_crtc *intel_crtc;
12148 struct drm_framebuffer *fb = state->base.fb;
12149 struct drm_rect *dest = &state->dst;
12150 struct drm_rect *src = &state->src;
12151 const struct drm_rect *clip = &state->clip;
12154 crtc = crtc ? crtc : plane->crtc;
12155 intel_crtc = to_intel_crtc(crtc);
12157 ret = drm_plane_helper_check_update(plane, crtc, fb,
12159 DRM_PLANE_HELPER_NO_SCALING,
12160 DRM_PLANE_HELPER_NO_SCALING,
12161 false, true, &state->visible);
12165 if (intel_crtc->active) {
12166 intel_crtc->atomic.wait_for_flips = true;
12169 * FBC does not work on some platforms for rotated
12170 * planes, so disable it when rotation is not 0 and
12171 * update it when rotation is set back to 0.
12173 * FIXME: This is redundant with the fbc update done in
12174 * the primary plane enable function except that that
12175 * one is done too late. We eventually need to unify
12178 if (intel_crtc->primary_enabled &&
12179 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12180 dev_priv->fbc.crtc == intel_crtc &&
12181 state->base.rotation != BIT(DRM_ROTATE_0)) {
12182 intel_crtc->atomic.disable_fbc = true;
12185 if (state->visible) {
12187 * BDW signals flip done immediately if the plane
12188 * is disabled, even if the plane enable is already
12189 * armed to occur at the next vblank :(
12191 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12192 intel_crtc->atomic.wait_vblank = true;
12195 intel_crtc->atomic.fb_bits |=
12196 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12198 intel_crtc->atomic.update_fbc = true;
12200 if (intel_wm_need_update(plane, &state->base))
12201 intel_crtc->atomic.update_wm = true;
12208 intel_commit_primary_plane(struct drm_plane *plane,
12209 struct intel_plane_state *state)
12211 struct drm_crtc *crtc = state->base.crtc;
12212 struct drm_framebuffer *fb = state->base.fb;
12213 struct drm_device *dev = plane->dev;
12214 struct drm_i915_private *dev_priv = dev->dev_private;
12215 struct intel_crtc *intel_crtc;
12216 struct drm_rect *src = &state->src;
12218 crtc = crtc ? crtc : plane->crtc;
12219 intel_crtc = to_intel_crtc(crtc);
12222 crtc->x = src->x1 >> 16;
12223 crtc->y = src->y1 >> 16;
12225 if (intel_crtc->active) {
12226 if (state->visible) {
12227 /* FIXME: kill this fastboot hack */
12228 intel_update_pipe_size(intel_crtc);
12230 intel_crtc->primary_enabled = true;
12232 dev_priv->display.update_primary_plane(crtc, plane->fb,
12236 * If clipping results in a non-visible primary plane,
12237 * we'll disable the primary plane. Note that this is
12238 * a bit different than what happens if userspace
12239 * explicitly disables the plane by passing fb=0
12240 * because plane->fb still gets set and pinned.
12242 intel_disable_primary_hw_plane(plane, crtc);
12247 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12249 struct drm_device *dev = crtc->dev;
12250 struct drm_i915_private *dev_priv = dev->dev_private;
12251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12252 struct intel_plane *intel_plane;
12253 struct drm_plane *p;
12254 unsigned fb_bits = 0;
12256 /* Track fb's for any planes being disabled */
12257 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12258 intel_plane = to_intel_plane(p);
12260 if (intel_crtc->atomic.disabled_planes &
12261 (1 << drm_plane_index(p))) {
12263 case DRM_PLANE_TYPE_PRIMARY:
12264 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12266 case DRM_PLANE_TYPE_CURSOR:
12267 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12269 case DRM_PLANE_TYPE_OVERLAY:
12270 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12274 mutex_lock(&dev->struct_mutex);
12275 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12276 mutex_unlock(&dev->struct_mutex);
12280 if (intel_crtc->atomic.wait_for_flips)
12281 intel_crtc_wait_for_pending_flips(crtc);
12283 if (intel_crtc->atomic.disable_fbc)
12284 intel_fbc_disable(dev);
12286 if (intel_crtc->atomic.pre_disable_primary)
12287 intel_pre_disable_primary(crtc);
12289 if (intel_crtc->atomic.update_wm)
12290 intel_update_watermarks(crtc);
12292 intel_runtime_pm_get(dev_priv);
12294 /* Perform vblank evasion around commit operation */
12295 if (intel_crtc->active)
12296 intel_crtc->atomic.evade =
12297 intel_pipe_update_start(intel_crtc,
12298 &intel_crtc->atomic.start_vbl_count);
12301 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12303 struct drm_device *dev = crtc->dev;
12304 struct drm_i915_private *dev_priv = dev->dev_private;
12305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12306 struct drm_plane *p;
12308 if (intel_crtc->atomic.evade)
12309 intel_pipe_update_end(intel_crtc,
12310 intel_crtc->atomic.start_vbl_count);
12312 intel_runtime_pm_put(dev_priv);
12314 if (intel_crtc->atomic.wait_vblank)
12315 intel_wait_for_vblank(dev, intel_crtc->pipe);
12317 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12319 if (intel_crtc->atomic.update_fbc) {
12320 mutex_lock(&dev->struct_mutex);
12321 intel_fbc_update(dev);
12322 mutex_unlock(&dev->struct_mutex);
12325 if (intel_crtc->atomic.post_enable_primary)
12326 intel_post_enable_primary(crtc);
12328 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12329 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12330 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12333 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12337 * intel_plane_destroy - destroy a plane
12338 * @plane: plane to destroy
12340 * Common destruction function for all types of planes (primary, cursor,
12343 void intel_plane_destroy(struct drm_plane *plane)
12345 struct intel_plane *intel_plane = to_intel_plane(plane);
12346 drm_plane_cleanup(plane);
12347 kfree(intel_plane);
12350 const struct drm_plane_funcs intel_plane_funcs = {
12351 .update_plane = drm_plane_helper_update,
12352 .disable_plane = drm_plane_helper_disable,
12353 .destroy = intel_plane_destroy,
12354 .set_property = drm_atomic_helper_plane_set_property,
12355 .atomic_get_property = intel_plane_atomic_get_property,
12356 .atomic_set_property = intel_plane_atomic_set_property,
12357 .atomic_duplicate_state = intel_plane_duplicate_state,
12358 .atomic_destroy_state = intel_plane_destroy_state,
12362 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12365 struct intel_plane *primary;
12366 struct intel_plane_state *state;
12367 const uint32_t *intel_primary_formats;
12370 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12371 if (primary == NULL)
12374 state = intel_create_plane_state(&primary->base);
12379 primary->base.state = &state->base;
12381 primary->can_scale = false;
12382 primary->max_downscale = 1;
12383 primary->pipe = pipe;
12384 primary->plane = pipe;
12385 primary->check_plane = intel_check_primary_plane;
12386 primary->commit_plane = intel_commit_primary_plane;
12387 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12388 primary->plane = !pipe;
12390 if (INTEL_INFO(dev)->gen <= 3) {
12391 intel_primary_formats = intel_primary_formats_gen2;
12392 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12394 intel_primary_formats = intel_primary_formats_gen4;
12395 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12398 drm_universal_plane_init(dev, &primary->base, 0,
12399 &intel_plane_funcs,
12400 intel_primary_formats, num_formats,
12401 DRM_PLANE_TYPE_PRIMARY);
12403 if (INTEL_INFO(dev)->gen >= 4) {
12404 if (!dev->mode_config.rotation_property)
12405 dev->mode_config.rotation_property =
12406 drm_mode_create_rotation_property(dev,
12407 BIT(DRM_ROTATE_0) |
12408 BIT(DRM_ROTATE_180));
12409 if (dev->mode_config.rotation_property)
12410 drm_object_attach_property(&primary->base.base,
12411 dev->mode_config.rotation_property,
12412 state->base.rotation);
12415 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12417 return &primary->base;
12421 intel_check_cursor_plane(struct drm_plane *plane,
12422 struct intel_plane_state *state)
12424 struct drm_crtc *crtc = state->base.crtc;
12425 struct drm_device *dev = plane->dev;
12426 struct drm_framebuffer *fb = state->base.fb;
12427 struct drm_rect *dest = &state->dst;
12428 struct drm_rect *src = &state->src;
12429 const struct drm_rect *clip = &state->clip;
12430 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12431 struct intel_crtc *intel_crtc;
12435 crtc = crtc ? crtc : plane->crtc;
12436 intel_crtc = to_intel_crtc(crtc);
12438 ret = drm_plane_helper_check_update(plane, crtc, fb,
12440 DRM_PLANE_HELPER_NO_SCALING,
12441 DRM_PLANE_HELPER_NO_SCALING,
12442 true, true, &state->visible);
12447 /* if we want to turn off the cursor ignore width and height */
12451 /* Check for which cursor types we support */
12452 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12453 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12454 state->base.crtc_w, state->base.crtc_h);
12458 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12459 if (obj->base.size < stride * state->base.crtc_h) {
12460 DRM_DEBUG_KMS("buffer is too small\n");
12464 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12465 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12470 if (intel_crtc->active) {
12471 if (plane->state->crtc_w != state->base.crtc_w)
12472 intel_crtc->atomic.update_wm = true;
12474 intel_crtc->atomic.fb_bits |=
12475 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12482 intel_commit_cursor_plane(struct drm_plane *plane,
12483 struct intel_plane_state *state)
12485 struct drm_crtc *crtc = state->base.crtc;
12486 struct drm_device *dev = plane->dev;
12487 struct intel_crtc *intel_crtc;
12488 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12491 crtc = crtc ? crtc : plane->crtc;
12492 intel_crtc = to_intel_crtc(crtc);
12494 plane->fb = state->base.fb;
12495 crtc->cursor_x = state->base.crtc_x;
12496 crtc->cursor_y = state->base.crtc_y;
12498 if (intel_crtc->cursor_bo == obj)
12503 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12504 addr = i915_gem_obj_ggtt_offset(obj);
12506 addr = obj->phys_handle->busaddr;
12508 intel_crtc->cursor_addr = addr;
12509 intel_crtc->cursor_bo = obj;
12512 if (intel_crtc->active)
12513 intel_crtc_update_cursor(crtc, state->visible);
12516 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12519 struct intel_plane *cursor;
12520 struct intel_plane_state *state;
12522 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12523 if (cursor == NULL)
12526 state = intel_create_plane_state(&cursor->base);
12531 cursor->base.state = &state->base;
12533 cursor->can_scale = false;
12534 cursor->max_downscale = 1;
12535 cursor->pipe = pipe;
12536 cursor->plane = pipe;
12537 cursor->check_plane = intel_check_cursor_plane;
12538 cursor->commit_plane = intel_commit_cursor_plane;
12540 drm_universal_plane_init(dev, &cursor->base, 0,
12541 &intel_plane_funcs,
12542 intel_cursor_formats,
12543 ARRAY_SIZE(intel_cursor_formats),
12544 DRM_PLANE_TYPE_CURSOR);
12546 if (INTEL_INFO(dev)->gen >= 4) {
12547 if (!dev->mode_config.rotation_property)
12548 dev->mode_config.rotation_property =
12549 drm_mode_create_rotation_property(dev,
12550 BIT(DRM_ROTATE_0) |
12551 BIT(DRM_ROTATE_180));
12552 if (dev->mode_config.rotation_property)
12553 drm_object_attach_property(&cursor->base.base,
12554 dev->mode_config.rotation_property,
12555 state->base.rotation);
12558 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12560 return &cursor->base;
12563 static void intel_crtc_init(struct drm_device *dev, int pipe)
12565 struct drm_i915_private *dev_priv = dev->dev_private;
12566 struct intel_crtc *intel_crtc;
12567 struct intel_crtc_state *crtc_state = NULL;
12568 struct drm_plane *primary = NULL;
12569 struct drm_plane *cursor = NULL;
12572 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12573 if (intel_crtc == NULL)
12576 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12579 intel_crtc_set_state(intel_crtc, crtc_state);
12580 crtc_state->base.crtc = &intel_crtc->base;
12582 primary = intel_primary_plane_create(dev, pipe);
12586 cursor = intel_cursor_plane_create(dev, pipe);
12590 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12591 cursor, &intel_crtc_funcs);
12595 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12596 for (i = 0; i < 256; i++) {
12597 intel_crtc->lut_r[i] = i;
12598 intel_crtc->lut_g[i] = i;
12599 intel_crtc->lut_b[i] = i;
12603 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12604 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12606 intel_crtc->pipe = pipe;
12607 intel_crtc->plane = pipe;
12608 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12609 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12610 intel_crtc->plane = !pipe;
12613 intel_crtc->cursor_base = ~0;
12614 intel_crtc->cursor_cntl = ~0;
12615 intel_crtc->cursor_size = ~0;
12617 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12618 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12619 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12620 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12622 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12624 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12626 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12631 drm_plane_cleanup(primary);
12633 drm_plane_cleanup(cursor);
12638 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12640 struct drm_encoder *encoder = connector->base.encoder;
12641 struct drm_device *dev = connector->base.dev;
12643 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12645 if (!encoder || WARN_ON(!encoder->crtc))
12646 return INVALID_PIPE;
12648 return to_intel_crtc(encoder->crtc)->pipe;
12651 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12652 struct drm_file *file)
12654 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12655 struct drm_crtc *drmmode_crtc;
12656 struct intel_crtc *crtc;
12658 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12660 if (!drmmode_crtc) {
12661 DRM_ERROR("no such CRTC id\n");
12665 crtc = to_intel_crtc(drmmode_crtc);
12666 pipe_from_crtc_id->pipe = crtc->pipe;
12671 static int intel_encoder_clones(struct intel_encoder *encoder)
12673 struct drm_device *dev = encoder->base.dev;
12674 struct intel_encoder *source_encoder;
12675 int index_mask = 0;
12678 for_each_intel_encoder(dev, source_encoder) {
12679 if (encoders_cloneable(encoder, source_encoder))
12680 index_mask |= (1 << entry);
12688 static bool has_edp_a(struct drm_device *dev)
12690 struct drm_i915_private *dev_priv = dev->dev_private;
12692 if (!IS_MOBILE(dev))
12695 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12698 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12704 static bool intel_crt_present(struct drm_device *dev)
12706 struct drm_i915_private *dev_priv = dev->dev_private;
12708 if (INTEL_INFO(dev)->gen >= 9)
12711 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12714 if (IS_CHERRYVIEW(dev))
12717 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12723 static void intel_setup_outputs(struct drm_device *dev)
12725 struct drm_i915_private *dev_priv = dev->dev_private;
12726 struct intel_encoder *encoder;
12727 struct drm_connector *connector;
12728 bool dpd_is_edp = false;
12730 intel_lvds_init(dev);
12732 if (intel_crt_present(dev))
12733 intel_crt_init(dev);
12735 if (HAS_DDI(dev)) {
12739 * Haswell uses DDI functions to detect digital outputs.
12740 * On SKL pre-D0 the strap isn't connected, so we assume
12743 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12744 /* WaIgnoreDDIAStrap: skl */
12746 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12747 intel_ddi_init(dev, PORT_A);
12749 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12751 found = I915_READ(SFUSE_STRAP);
12753 if (found & SFUSE_STRAP_DDIB_DETECTED)
12754 intel_ddi_init(dev, PORT_B);
12755 if (found & SFUSE_STRAP_DDIC_DETECTED)
12756 intel_ddi_init(dev, PORT_C);
12757 if (found & SFUSE_STRAP_DDID_DETECTED)
12758 intel_ddi_init(dev, PORT_D);
12759 } else if (HAS_PCH_SPLIT(dev)) {
12761 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12763 if (has_edp_a(dev))
12764 intel_dp_init(dev, DP_A, PORT_A);
12766 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12767 /* PCH SDVOB multiplex with HDMIB */
12768 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12770 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12771 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12772 intel_dp_init(dev, PCH_DP_B, PORT_B);
12775 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12776 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12778 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12779 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12781 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12782 intel_dp_init(dev, PCH_DP_C, PORT_C);
12784 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12785 intel_dp_init(dev, PCH_DP_D, PORT_D);
12786 } else if (IS_VALLEYVIEW(dev)) {
12788 * The DP_DETECTED bit is the latched state of the DDC
12789 * SDA pin at boot. However since eDP doesn't require DDC
12790 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12791 * eDP ports may have been muxed to an alternate function.
12792 * Thus we can't rely on the DP_DETECTED bit alone to detect
12793 * eDP ports. Consult the VBT as well as DP_DETECTED to
12794 * detect eDP ports.
12796 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12797 !intel_dp_is_edp(dev, PORT_B))
12798 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12800 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12801 intel_dp_is_edp(dev, PORT_B))
12802 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12804 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12805 !intel_dp_is_edp(dev, PORT_C))
12806 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12808 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12809 intel_dp_is_edp(dev, PORT_C))
12810 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12812 if (IS_CHERRYVIEW(dev)) {
12813 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12814 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12816 /* eDP not supported on port D, so don't check VBT */
12817 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12818 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12821 intel_dsi_init(dev);
12822 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12823 bool found = false;
12825 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12826 DRM_DEBUG_KMS("probing SDVOB\n");
12827 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12828 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12829 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12830 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12833 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12834 intel_dp_init(dev, DP_B, PORT_B);
12837 /* Before G4X SDVOC doesn't have its own detect register */
12839 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12840 DRM_DEBUG_KMS("probing SDVOC\n");
12841 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12844 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12846 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12847 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12848 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12850 if (SUPPORTS_INTEGRATED_DP(dev))
12851 intel_dp_init(dev, DP_C, PORT_C);
12854 if (SUPPORTS_INTEGRATED_DP(dev) &&
12855 (I915_READ(DP_D) & DP_DETECTED))
12856 intel_dp_init(dev, DP_D, PORT_D);
12857 } else if (IS_GEN2(dev))
12858 intel_dvo_init(dev);
12860 if (SUPPORTS_TV(dev))
12861 intel_tv_init(dev);
12864 * FIXME: We don't have full atomic support yet, but we want to be
12865 * able to enable/test plane updates via the atomic interface in the
12866 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12867 * will take some atomic codepaths to lookup properties during
12868 * drmModeGetConnector() that unconditionally dereference
12869 * connector->state.
12871 * We create a dummy connector state here for each connector to ensure
12872 * the DRM core doesn't try to dereference a NULL connector->state.
12873 * The actual connector properties will never be updated or contain
12874 * useful information, but since we're doing this specifically for
12875 * testing/debug of the plane operations (and only when a specific
12876 * kernel module option is given), that shouldn't really matter.
12878 * Once atomic support for crtc's + connectors lands, this loop should
12879 * be removed since we'll be setting up real connector state, which
12880 * will contain Intel-specific properties.
12882 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12883 list_for_each_entry(connector,
12884 &dev->mode_config.connector_list,
12886 if (!WARN_ON(connector->state)) {
12888 kzalloc(sizeof(*connector->state),
12894 intel_psr_init(dev);
12896 for_each_intel_encoder(dev, encoder) {
12897 encoder->base.possible_crtcs = encoder->crtc_mask;
12898 encoder->base.possible_clones =
12899 intel_encoder_clones(encoder);
12902 intel_init_pch_refclk(dev);
12904 drm_helper_move_panel_connectors_to_head(dev);
12907 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12909 struct drm_device *dev = fb->dev;
12910 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12912 drm_framebuffer_cleanup(fb);
12913 mutex_lock(&dev->struct_mutex);
12914 WARN_ON(!intel_fb->obj->framebuffer_references--);
12915 drm_gem_object_unreference(&intel_fb->obj->base);
12916 mutex_unlock(&dev->struct_mutex);
12920 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12921 struct drm_file *file,
12922 unsigned int *handle)
12924 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12925 struct drm_i915_gem_object *obj = intel_fb->obj;
12927 return drm_gem_handle_create(file, &obj->base, handle);
12930 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12931 .destroy = intel_user_framebuffer_destroy,
12932 .create_handle = intel_user_framebuffer_create_handle,
12936 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12937 uint32_t pixel_format)
12939 u32 gen = INTEL_INFO(dev)->gen;
12942 /* "The stride in bytes must not exceed the of the size of 8K
12943 * pixels and 32K bytes."
12945 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12946 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12948 } else if (gen >= 4) {
12949 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12953 } else if (gen >= 3) {
12954 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12959 /* XXX DSPC is limited to 4k tiled */
12964 static int intel_framebuffer_init(struct drm_device *dev,
12965 struct intel_framebuffer *intel_fb,
12966 struct drm_mode_fb_cmd2 *mode_cmd,
12967 struct drm_i915_gem_object *obj)
12969 unsigned int aligned_height;
12971 u32 pitch_limit, stride_alignment;
12973 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12975 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12976 /* Enforce that fb modifier and tiling mode match, but only for
12977 * X-tiled. This is needed for FBC. */
12978 if (!!(obj->tiling_mode == I915_TILING_X) !=
12979 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12980 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12984 if (obj->tiling_mode == I915_TILING_X)
12985 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12986 else if (obj->tiling_mode == I915_TILING_Y) {
12987 DRM_DEBUG("No Y tiling for legacy addfb\n");
12992 /* Passed in modifier sanity checking. */
12993 switch (mode_cmd->modifier[0]) {
12994 case I915_FORMAT_MOD_Y_TILED:
12995 case I915_FORMAT_MOD_Yf_TILED:
12996 if (INTEL_INFO(dev)->gen < 9) {
12997 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12998 mode_cmd->modifier[0]);
13001 case DRM_FORMAT_MOD_NONE:
13002 case I915_FORMAT_MOD_X_TILED:
13005 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13006 mode_cmd->modifier[0]);
13010 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13011 mode_cmd->pixel_format);
13012 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13013 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13014 mode_cmd->pitches[0], stride_alignment);
13018 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13019 mode_cmd->pixel_format);
13020 if (mode_cmd->pitches[0] > pitch_limit) {
13021 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13022 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13023 "tiled" : "linear",
13024 mode_cmd->pitches[0], pitch_limit);
13028 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13029 mode_cmd->pitches[0] != obj->stride) {
13030 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13031 mode_cmd->pitches[0], obj->stride);
13035 /* Reject formats not supported by any plane early. */
13036 switch (mode_cmd->pixel_format) {
13037 case DRM_FORMAT_C8:
13038 case DRM_FORMAT_RGB565:
13039 case DRM_FORMAT_XRGB8888:
13040 case DRM_FORMAT_ARGB8888:
13042 case DRM_FORMAT_XRGB1555:
13043 case DRM_FORMAT_ARGB1555:
13044 if (INTEL_INFO(dev)->gen > 3) {
13045 DRM_DEBUG("unsupported pixel format: %s\n",
13046 drm_get_format_name(mode_cmd->pixel_format));
13050 case DRM_FORMAT_XBGR8888:
13051 case DRM_FORMAT_ABGR8888:
13052 case DRM_FORMAT_XRGB2101010:
13053 case DRM_FORMAT_ARGB2101010:
13054 case DRM_FORMAT_XBGR2101010:
13055 case DRM_FORMAT_ABGR2101010:
13056 if (INTEL_INFO(dev)->gen < 4) {
13057 DRM_DEBUG("unsupported pixel format: %s\n",
13058 drm_get_format_name(mode_cmd->pixel_format));
13062 case DRM_FORMAT_YUYV:
13063 case DRM_FORMAT_UYVY:
13064 case DRM_FORMAT_YVYU:
13065 case DRM_FORMAT_VYUY:
13066 if (INTEL_INFO(dev)->gen < 5) {
13067 DRM_DEBUG("unsupported pixel format: %s\n",
13068 drm_get_format_name(mode_cmd->pixel_format));
13073 DRM_DEBUG("unsupported pixel format: %s\n",
13074 drm_get_format_name(mode_cmd->pixel_format));
13078 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13079 if (mode_cmd->offsets[0] != 0)
13082 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13083 mode_cmd->pixel_format,
13084 mode_cmd->modifier[0]);
13085 /* FIXME drm helper for size checks (especially planar formats)? */
13086 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13089 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13090 intel_fb->obj = obj;
13091 intel_fb->obj->framebuffer_references++;
13093 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13095 DRM_ERROR("framebuffer init failed %d\n", ret);
13102 static struct drm_framebuffer *
13103 intel_user_framebuffer_create(struct drm_device *dev,
13104 struct drm_file *filp,
13105 struct drm_mode_fb_cmd2 *mode_cmd)
13107 struct drm_i915_gem_object *obj;
13109 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13110 mode_cmd->handles[0]));
13111 if (&obj->base == NULL)
13112 return ERR_PTR(-ENOENT);
13114 return intel_framebuffer_create(dev, mode_cmd, obj);
13117 #ifndef CONFIG_DRM_I915_FBDEV
13118 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13123 static const struct drm_mode_config_funcs intel_mode_funcs = {
13124 .fb_create = intel_user_framebuffer_create,
13125 .output_poll_changed = intel_fbdev_output_poll_changed,
13126 .atomic_check = intel_atomic_check,
13127 .atomic_commit = intel_atomic_commit,
13130 /* Set up chip specific display functions */
13131 static void intel_init_display(struct drm_device *dev)
13133 struct drm_i915_private *dev_priv = dev->dev_private;
13135 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13136 dev_priv->display.find_dpll = g4x_find_best_dpll;
13137 else if (IS_CHERRYVIEW(dev))
13138 dev_priv->display.find_dpll = chv_find_best_dpll;
13139 else if (IS_VALLEYVIEW(dev))
13140 dev_priv->display.find_dpll = vlv_find_best_dpll;
13141 else if (IS_PINEVIEW(dev))
13142 dev_priv->display.find_dpll = pnv_find_best_dpll;
13144 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13146 if (INTEL_INFO(dev)->gen >= 9) {
13147 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13148 dev_priv->display.get_initial_plane_config =
13149 skylake_get_initial_plane_config;
13150 dev_priv->display.crtc_compute_clock =
13151 haswell_crtc_compute_clock;
13152 dev_priv->display.crtc_enable = haswell_crtc_enable;
13153 dev_priv->display.crtc_disable = haswell_crtc_disable;
13154 dev_priv->display.off = ironlake_crtc_off;
13155 dev_priv->display.update_primary_plane =
13156 skylake_update_primary_plane;
13157 } else if (HAS_DDI(dev)) {
13158 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13159 dev_priv->display.get_initial_plane_config =
13160 ironlake_get_initial_plane_config;
13161 dev_priv->display.crtc_compute_clock =
13162 haswell_crtc_compute_clock;
13163 dev_priv->display.crtc_enable = haswell_crtc_enable;
13164 dev_priv->display.crtc_disable = haswell_crtc_disable;
13165 dev_priv->display.off = ironlake_crtc_off;
13166 dev_priv->display.update_primary_plane =
13167 ironlake_update_primary_plane;
13168 } else if (HAS_PCH_SPLIT(dev)) {
13169 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13170 dev_priv->display.get_initial_plane_config =
13171 ironlake_get_initial_plane_config;
13172 dev_priv->display.crtc_compute_clock =
13173 ironlake_crtc_compute_clock;
13174 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13175 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13176 dev_priv->display.off = ironlake_crtc_off;
13177 dev_priv->display.update_primary_plane =
13178 ironlake_update_primary_plane;
13179 } else if (IS_VALLEYVIEW(dev)) {
13180 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13181 dev_priv->display.get_initial_plane_config =
13182 i9xx_get_initial_plane_config;
13183 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13184 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13185 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13186 dev_priv->display.off = i9xx_crtc_off;
13187 dev_priv->display.update_primary_plane =
13188 i9xx_update_primary_plane;
13190 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13191 dev_priv->display.get_initial_plane_config =
13192 i9xx_get_initial_plane_config;
13193 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13194 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13195 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13196 dev_priv->display.off = i9xx_crtc_off;
13197 dev_priv->display.update_primary_plane =
13198 i9xx_update_primary_plane;
13201 /* Returns the core display clock speed */
13202 if (IS_VALLEYVIEW(dev))
13203 dev_priv->display.get_display_clock_speed =
13204 valleyview_get_display_clock_speed;
13205 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13206 dev_priv->display.get_display_clock_speed =
13207 i945_get_display_clock_speed;
13208 else if (IS_I915G(dev))
13209 dev_priv->display.get_display_clock_speed =
13210 i915_get_display_clock_speed;
13211 else if (IS_I945GM(dev) || IS_845G(dev))
13212 dev_priv->display.get_display_clock_speed =
13213 i9xx_misc_get_display_clock_speed;
13214 else if (IS_PINEVIEW(dev))
13215 dev_priv->display.get_display_clock_speed =
13216 pnv_get_display_clock_speed;
13217 else if (IS_I915GM(dev))
13218 dev_priv->display.get_display_clock_speed =
13219 i915gm_get_display_clock_speed;
13220 else if (IS_I865G(dev))
13221 dev_priv->display.get_display_clock_speed =
13222 i865_get_display_clock_speed;
13223 else if (IS_I85X(dev))
13224 dev_priv->display.get_display_clock_speed =
13225 i855_get_display_clock_speed;
13226 else /* 852, 830 */
13227 dev_priv->display.get_display_clock_speed =
13228 i830_get_display_clock_speed;
13230 if (IS_GEN5(dev)) {
13231 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13232 } else if (IS_GEN6(dev)) {
13233 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13234 } else if (IS_IVYBRIDGE(dev)) {
13235 /* FIXME: detect B0+ stepping and use auto training */
13236 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13237 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13238 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13239 } else if (IS_VALLEYVIEW(dev)) {
13240 dev_priv->display.modeset_global_resources =
13241 valleyview_modeset_global_resources;
13244 switch (INTEL_INFO(dev)->gen) {
13246 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13250 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13255 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13259 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13262 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13263 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13266 /* Drop through - unsupported since execlist only. */
13268 /* Default just returns -ENODEV to indicate unsupported */
13269 dev_priv->display.queue_flip = intel_default_queue_flip;
13272 intel_panel_init_backlight_funcs(dev);
13274 mutex_init(&dev_priv->pps_mutex);
13278 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13279 * resume, or other times. This quirk makes sure that's the case for
13280 * affected systems.
13282 static void quirk_pipea_force(struct drm_device *dev)
13284 struct drm_i915_private *dev_priv = dev->dev_private;
13286 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13287 DRM_INFO("applying pipe a force quirk\n");
13290 static void quirk_pipeb_force(struct drm_device *dev)
13292 struct drm_i915_private *dev_priv = dev->dev_private;
13294 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13295 DRM_INFO("applying pipe b force quirk\n");
13299 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13301 static void quirk_ssc_force_disable(struct drm_device *dev)
13303 struct drm_i915_private *dev_priv = dev->dev_private;
13304 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13305 DRM_INFO("applying lvds SSC disable quirk\n");
13309 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13312 static void quirk_invert_brightness(struct drm_device *dev)
13314 struct drm_i915_private *dev_priv = dev->dev_private;
13315 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13316 DRM_INFO("applying inverted panel brightness quirk\n");
13319 /* Some VBT's incorrectly indicate no backlight is present */
13320 static void quirk_backlight_present(struct drm_device *dev)
13322 struct drm_i915_private *dev_priv = dev->dev_private;
13323 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13324 DRM_INFO("applying backlight present quirk\n");
13327 struct intel_quirk {
13329 int subsystem_vendor;
13330 int subsystem_device;
13331 void (*hook)(struct drm_device *dev);
13334 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13335 struct intel_dmi_quirk {
13336 void (*hook)(struct drm_device *dev);
13337 const struct dmi_system_id (*dmi_id_list)[];
13340 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13342 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13346 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13348 .dmi_id_list = &(const struct dmi_system_id[]) {
13350 .callback = intel_dmi_reverse_brightness,
13351 .ident = "NCR Corporation",
13352 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13353 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13356 { } /* terminating entry */
13358 .hook = quirk_invert_brightness,
13362 static struct intel_quirk intel_quirks[] = {
13363 /* HP Mini needs pipe A force quirk (LP: #322104) */
13364 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13366 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13367 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13369 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13370 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13372 /* 830 needs to leave pipe A & dpll A up */
13373 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13375 /* 830 needs to leave pipe B & dpll B up */
13376 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13378 /* Lenovo U160 cannot use SSC on LVDS */
13379 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13381 /* Sony Vaio Y cannot use SSC on LVDS */
13382 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13384 /* Acer Aspire 5734Z must invert backlight brightness */
13385 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13387 /* Acer/eMachines G725 */
13388 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13390 /* Acer/eMachines e725 */
13391 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13393 /* Acer/Packard Bell NCL20 */
13394 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13396 /* Acer Aspire 4736Z */
13397 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13399 /* Acer Aspire 5336 */
13400 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13402 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13403 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13405 /* Acer C720 Chromebook (Core i3 4005U) */
13406 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13408 /* Apple Macbook 2,1 (Core 2 T7400) */
13409 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13411 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13412 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13414 /* HP Chromebook 14 (Celeron 2955U) */
13415 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13417 /* Dell Chromebook 11 */
13418 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13421 static void intel_init_quirks(struct drm_device *dev)
13423 struct pci_dev *d = dev->pdev;
13426 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13427 struct intel_quirk *q = &intel_quirks[i];
13429 if (d->device == q->device &&
13430 (d->subsystem_vendor == q->subsystem_vendor ||
13431 q->subsystem_vendor == PCI_ANY_ID) &&
13432 (d->subsystem_device == q->subsystem_device ||
13433 q->subsystem_device == PCI_ANY_ID))
13436 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13437 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13438 intel_dmi_quirks[i].hook(dev);
13442 /* Disable the VGA plane that we never use */
13443 static void i915_disable_vga(struct drm_device *dev)
13445 struct drm_i915_private *dev_priv = dev->dev_private;
13447 u32 vga_reg = i915_vgacntrl_reg(dev);
13449 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13450 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13451 outb(SR01, VGA_SR_INDEX);
13452 sr1 = inb(VGA_SR_DATA);
13453 outb(sr1 | 1<<5, VGA_SR_DATA);
13454 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13457 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13458 POSTING_READ(vga_reg);
13461 void intel_modeset_init_hw(struct drm_device *dev)
13463 intel_prepare_ddi(dev);
13465 if (IS_VALLEYVIEW(dev))
13466 vlv_update_cdclk(dev);
13468 intel_init_clock_gating(dev);
13470 intel_enable_gt_powersave(dev);
13473 void intel_modeset_init(struct drm_device *dev)
13475 struct drm_i915_private *dev_priv = dev->dev_private;
13478 struct intel_crtc *crtc;
13480 drm_mode_config_init(dev);
13482 dev->mode_config.min_width = 0;
13483 dev->mode_config.min_height = 0;
13485 dev->mode_config.preferred_depth = 24;
13486 dev->mode_config.prefer_shadow = 1;
13488 dev->mode_config.allow_fb_modifiers = true;
13490 dev->mode_config.funcs = &intel_mode_funcs;
13492 intel_init_quirks(dev);
13494 intel_init_pm(dev);
13496 if (INTEL_INFO(dev)->num_pipes == 0)
13499 intel_init_display(dev);
13500 intel_init_audio(dev);
13502 if (IS_GEN2(dev)) {
13503 dev->mode_config.max_width = 2048;
13504 dev->mode_config.max_height = 2048;
13505 } else if (IS_GEN3(dev)) {
13506 dev->mode_config.max_width = 4096;
13507 dev->mode_config.max_height = 4096;
13509 dev->mode_config.max_width = 8192;
13510 dev->mode_config.max_height = 8192;
13513 if (IS_845G(dev) || IS_I865G(dev)) {
13514 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13515 dev->mode_config.cursor_height = 1023;
13516 } else if (IS_GEN2(dev)) {
13517 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13518 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13520 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13521 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13524 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13526 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13527 INTEL_INFO(dev)->num_pipes,
13528 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13530 for_each_pipe(dev_priv, pipe) {
13531 intel_crtc_init(dev, pipe);
13532 for_each_sprite(dev_priv, pipe, sprite) {
13533 ret = intel_plane_init(dev, pipe, sprite);
13535 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13536 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13540 intel_init_dpio(dev);
13542 intel_shared_dpll_init(dev);
13544 /* Just disable it once at startup */
13545 i915_disable_vga(dev);
13546 intel_setup_outputs(dev);
13548 /* Just in case the BIOS is doing something questionable. */
13549 intel_fbc_disable(dev);
13551 drm_modeset_lock_all(dev);
13552 intel_modeset_setup_hw_state(dev, false);
13553 drm_modeset_unlock_all(dev);
13555 for_each_intel_crtc(dev, crtc) {
13560 * Note that reserving the BIOS fb up front prevents us
13561 * from stuffing other stolen allocations like the ring
13562 * on top. This prevents some ugliness at boot time, and
13563 * can even allow for smooth boot transitions if the BIOS
13564 * fb is large enough for the active pipe configuration.
13566 if (dev_priv->display.get_initial_plane_config) {
13567 dev_priv->display.get_initial_plane_config(crtc,
13568 &crtc->plane_config);
13570 * If the fb is shared between multiple heads, we'll
13571 * just get the first one.
13573 intel_find_plane_obj(crtc, &crtc->plane_config);
13578 static void intel_enable_pipe_a(struct drm_device *dev)
13580 struct intel_connector *connector;
13581 struct drm_connector *crt = NULL;
13582 struct intel_load_detect_pipe load_detect_temp;
13583 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13585 /* We can't just switch on the pipe A, we need to set things up with a
13586 * proper mode and output configuration. As a gross hack, enable pipe A
13587 * by enabling the load detect pipe once. */
13588 for_each_intel_connector(dev, connector) {
13589 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13590 crt = &connector->base;
13598 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13599 intel_release_load_detect_pipe(crt, &load_detect_temp);
13603 intel_check_plane_mapping(struct intel_crtc *crtc)
13605 struct drm_device *dev = crtc->base.dev;
13606 struct drm_i915_private *dev_priv = dev->dev_private;
13609 if (INTEL_INFO(dev)->num_pipes == 1)
13612 reg = DSPCNTR(!crtc->plane);
13613 val = I915_READ(reg);
13615 if ((val & DISPLAY_PLANE_ENABLE) &&
13616 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13622 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13624 struct drm_device *dev = crtc->base.dev;
13625 struct drm_i915_private *dev_priv = dev->dev_private;
13628 /* Clear any frame start delays used for debugging left by the BIOS */
13629 reg = PIPECONF(crtc->config->cpu_transcoder);
13630 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13632 /* restore vblank interrupts to correct state */
13633 drm_crtc_vblank_reset(&crtc->base);
13634 if (crtc->active) {
13635 update_scanline_offset(crtc);
13636 drm_crtc_vblank_on(&crtc->base);
13639 /* We need to sanitize the plane -> pipe mapping first because this will
13640 * disable the crtc (and hence change the state) if it is wrong. Note
13641 * that gen4+ has a fixed plane -> pipe mapping. */
13642 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13643 struct intel_connector *connector;
13646 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13647 crtc->base.base.id);
13649 /* Pipe has the wrong plane attached and the plane is active.
13650 * Temporarily change the plane mapping and disable everything
13652 plane = crtc->plane;
13653 crtc->plane = !plane;
13654 crtc->primary_enabled = true;
13655 dev_priv->display.crtc_disable(&crtc->base);
13656 crtc->plane = plane;
13658 /* ... and break all links. */
13659 for_each_intel_connector(dev, connector) {
13660 if (connector->encoder->base.crtc != &crtc->base)
13663 connector->base.dpms = DRM_MODE_DPMS_OFF;
13664 connector->base.encoder = NULL;
13666 /* multiple connectors may have the same encoder:
13667 * handle them and break crtc link separately */
13668 for_each_intel_connector(dev, connector)
13669 if (connector->encoder->base.crtc == &crtc->base) {
13670 connector->encoder->base.crtc = NULL;
13671 connector->encoder->connectors_active = false;
13674 WARN_ON(crtc->active);
13675 crtc->base.state->enable = false;
13676 crtc->base.enabled = false;
13679 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13680 crtc->pipe == PIPE_A && !crtc->active) {
13681 /* BIOS forgot to enable pipe A, this mostly happens after
13682 * resume. Force-enable the pipe to fix this, the update_dpms
13683 * call below we restore the pipe to the right state, but leave
13684 * the required bits on. */
13685 intel_enable_pipe_a(dev);
13688 /* Adjust the state of the output pipe according to whether we
13689 * have active connectors/encoders. */
13690 intel_crtc_update_dpms(&crtc->base);
13692 if (crtc->active != crtc->base.state->enable) {
13693 struct intel_encoder *encoder;
13695 /* This can happen either due to bugs in the get_hw_state
13696 * functions or because the pipe is force-enabled due to the
13698 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13699 crtc->base.base.id,
13700 crtc->base.state->enable ? "enabled" : "disabled",
13701 crtc->active ? "enabled" : "disabled");
13703 crtc->base.state->enable = crtc->active;
13704 crtc->base.enabled = crtc->active;
13706 /* Because we only establish the connector -> encoder ->
13707 * crtc links if something is active, this means the
13708 * crtc is now deactivated. Break the links. connector
13709 * -> encoder links are only establish when things are
13710 * actually up, hence no need to break them. */
13711 WARN_ON(crtc->active);
13713 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13714 WARN_ON(encoder->connectors_active);
13715 encoder->base.crtc = NULL;
13719 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13721 * We start out with underrun reporting disabled to avoid races.
13722 * For correct bookkeeping mark this on active crtcs.
13724 * Also on gmch platforms we dont have any hardware bits to
13725 * disable the underrun reporting. Which means we need to start
13726 * out with underrun reporting disabled also on inactive pipes,
13727 * since otherwise we'll complain about the garbage we read when
13728 * e.g. coming up after runtime pm.
13730 * No protection against concurrent access is required - at
13731 * worst a fifo underrun happens which also sets this to false.
13733 crtc->cpu_fifo_underrun_disabled = true;
13734 crtc->pch_fifo_underrun_disabled = true;
13738 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13740 struct intel_connector *connector;
13741 struct drm_device *dev = encoder->base.dev;
13743 /* We need to check both for a crtc link (meaning that the
13744 * encoder is active and trying to read from a pipe) and the
13745 * pipe itself being active. */
13746 bool has_active_crtc = encoder->base.crtc &&
13747 to_intel_crtc(encoder->base.crtc)->active;
13749 if (encoder->connectors_active && !has_active_crtc) {
13750 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13751 encoder->base.base.id,
13752 encoder->base.name);
13754 /* Connector is active, but has no active pipe. This is
13755 * fallout from our resume register restoring. Disable
13756 * the encoder manually again. */
13757 if (encoder->base.crtc) {
13758 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13759 encoder->base.base.id,
13760 encoder->base.name);
13761 encoder->disable(encoder);
13762 if (encoder->post_disable)
13763 encoder->post_disable(encoder);
13765 encoder->base.crtc = NULL;
13766 encoder->connectors_active = false;
13768 /* Inconsistent output/port/pipe state happens presumably due to
13769 * a bug in one of the get_hw_state functions. Or someplace else
13770 * in our code, like the register restore mess on resume. Clamp
13771 * things to off as a safer default. */
13772 for_each_intel_connector(dev, connector) {
13773 if (connector->encoder != encoder)
13775 connector->base.dpms = DRM_MODE_DPMS_OFF;
13776 connector->base.encoder = NULL;
13779 /* Enabled encoders without active connectors will be fixed in
13780 * the crtc fixup. */
13783 void i915_redisable_vga_power_on(struct drm_device *dev)
13785 struct drm_i915_private *dev_priv = dev->dev_private;
13786 u32 vga_reg = i915_vgacntrl_reg(dev);
13788 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13789 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13790 i915_disable_vga(dev);
13794 void i915_redisable_vga(struct drm_device *dev)
13796 struct drm_i915_private *dev_priv = dev->dev_private;
13798 /* This function can be called both from intel_modeset_setup_hw_state or
13799 * at a very early point in our resume sequence, where the power well
13800 * structures are not yet restored. Since this function is at a very
13801 * paranoid "someone might have enabled VGA while we were not looking"
13802 * level, just check if the power well is enabled instead of trying to
13803 * follow the "don't touch the power well if we don't need it" policy
13804 * the rest of the driver uses. */
13805 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13808 i915_redisable_vga_power_on(dev);
13811 static bool primary_get_hw_state(struct intel_crtc *crtc)
13813 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13818 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13821 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13823 struct drm_i915_private *dev_priv = dev->dev_private;
13825 struct intel_crtc *crtc;
13826 struct intel_encoder *encoder;
13827 struct intel_connector *connector;
13830 for_each_intel_crtc(dev, crtc) {
13831 memset(crtc->config, 0, sizeof(*crtc->config));
13833 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13835 crtc->active = dev_priv->display.get_pipe_config(crtc,
13838 crtc->base.state->enable = crtc->active;
13839 crtc->base.enabled = crtc->active;
13840 crtc->primary_enabled = primary_get_hw_state(crtc);
13842 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13843 crtc->base.base.id,
13844 crtc->active ? "enabled" : "disabled");
13847 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13848 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13850 pll->on = pll->get_hw_state(dev_priv, pll,
13851 &pll->config.hw_state);
13853 pll->config.crtc_mask = 0;
13854 for_each_intel_crtc(dev, crtc) {
13855 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13857 pll->config.crtc_mask |= 1 << crtc->pipe;
13861 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13862 pll->name, pll->config.crtc_mask, pll->on);
13864 if (pll->config.crtc_mask)
13865 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13868 for_each_intel_encoder(dev, encoder) {
13871 if (encoder->get_hw_state(encoder, &pipe)) {
13872 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13873 encoder->base.crtc = &crtc->base;
13874 encoder->get_config(encoder, crtc->config);
13876 encoder->base.crtc = NULL;
13879 encoder->connectors_active = false;
13880 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13881 encoder->base.base.id,
13882 encoder->base.name,
13883 encoder->base.crtc ? "enabled" : "disabled",
13887 for_each_intel_connector(dev, connector) {
13888 if (connector->get_hw_state(connector)) {
13889 connector->base.dpms = DRM_MODE_DPMS_ON;
13890 connector->encoder->connectors_active = true;
13891 connector->base.encoder = &connector->encoder->base;
13893 connector->base.dpms = DRM_MODE_DPMS_OFF;
13894 connector->base.encoder = NULL;
13896 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13897 connector->base.base.id,
13898 connector->base.name,
13899 connector->base.encoder ? "enabled" : "disabled");
13903 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13904 * and i915 state tracking structures. */
13905 void intel_modeset_setup_hw_state(struct drm_device *dev,
13906 bool force_restore)
13908 struct drm_i915_private *dev_priv = dev->dev_private;
13910 struct intel_crtc *crtc;
13911 struct intel_encoder *encoder;
13914 intel_modeset_readout_hw_state(dev);
13917 * Now that we have the config, copy it to each CRTC struct
13918 * Note that this could go away if we move to using crtc_config
13919 * checking everywhere.
13921 for_each_intel_crtc(dev, crtc) {
13922 if (crtc->active && i915.fastboot) {
13923 intel_mode_from_pipe_config(&crtc->base.mode,
13925 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13926 crtc->base.base.id);
13927 drm_mode_debug_printmodeline(&crtc->base.mode);
13931 /* HW state is read out, now we need to sanitize this mess. */
13932 for_each_intel_encoder(dev, encoder) {
13933 intel_sanitize_encoder(encoder);
13936 for_each_pipe(dev_priv, pipe) {
13937 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13938 intel_sanitize_crtc(crtc);
13939 intel_dump_pipe_config(crtc, crtc->config,
13940 "[setup_hw_state]");
13943 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13944 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13946 if (!pll->on || pll->active)
13949 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13951 pll->disable(dev_priv, pll);
13956 skl_wm_get_hw_state(dev);
13957 else if (HAS_PCH_SPLIT(dev))
13958 ilk_wm_get_hw_state(dev);
13960 if (force_restore) {
13961 i915_redisable_vga(dev);
13964 * We need to use raw interfaces for restoring state to avoid
13965 * checking (bogus) intermediate states.
13967 for_each_pipe(dev_priv, pipe) {
13968 struct drm_crtc *crtc =
13969 dev_priv->pipe_to_crtc_mapping[pipe];
13971 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13972 crtc->primary->fb);
13975 intel_modeset_update_staged_output_state(dev);
13978 intel_modeset_check_state(dev);
13981 void intel_modeset_gem_init(struct drm_device *dev)
13983 struct drm_i915_private *dev_priv = dev->dev_private;
13984 struct drm_crtc *c;
13985 struct drm_i915_gem_object *obj;
13987 mutex_lock(&dev->struct_mutex);
13988 intel_init_gt_powersave(dev);
13989 mutex_unlock(&dev->struct_mutex);
13992 * There may be no VBT; and if the BIOS enabled SSC we can
13993 * just keep using it to avoid unnecessary flicker. Whereas if the
13994 * BIOS isn't using it, don't assume it will work even if the VBT
13995 * indicates as much.
13997 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13998 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14001 intel_modeset_init_hw(dev);
14003 intel_setup_overlay(dev);
14006 * Make sure any fbs we allocated at startup are properly
14007 * pinned & fenced. When we do the allocation it's too early
14010 mutex_lock(&dev->struct_mutex);
14011 for_each_crtc(dev, c) {
14012 obj = intel_fb_obj(c->primary->fb);
14016 if (intel_pin_and_fence_fb_obj(c->primary,
14020 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14021 to_intel_crtc(c)->pipe);
14022 drm_framebuffer_unreference(c->primary->fb);
14023 c->primary->fb = NULL;
14024 update_state_fb(c->primary);
14027 mutex_unlock(&dev->struct_mutex);
14029 intel_backlight_register(dev);
14032 void intel_connector_unregister(struct intel_connector *intel_connector)
14034 struct drm_connector *connector = &intel_connector->base;
14036 intel_panel_destroy_backlight(connector);
14037 drm_connector_unregister(connector);
14040 void intel_modeset_cleanup(struct drm_device *dev)
14042 struct drm_i915_private *dev_priv = dev->dev_private;
14043 struct drm_connector *connector;
14045 intel_disable_gt_powersave(dev);
14047 intel_backlight_unregister(dev);
14050 * Interrupts and polling as the first thing to avoid creating havoc.
14051 * Too much stuff here (turning of connectors, ...) would
14052 * experience fancy races otherwise.
14054 intel_irq_uninstall(dev_priv);
14057 * Due to the hpd irq storm handling the hotplug work can re-arm the
14058 * poll handlers. Hence disable polling after hpd handling is shut down.
14060 drm_kms_helper_poll_fini(dev);
14062 mutex_lock(&dev->struct_mutex);
14064 intel_unregister_dsm_handler();
14066 intel_fbc_disable(dev);
14068 mutex_unlock(&dev->struct_mutex);
14070 /* flush any delayed tasks or pending work */
14071 flush_scheduled_work();
14073 /* destroy the backlight and sysfs files before encoders/connectors */
14074 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14075 struct intel_connector *intel_connector;
14077 intel_connector = to_intel_connector(connector);
14078 intel_connector->unregister(intel_connector);
14081 drm_mode_config_cleanup(dev);
14083 intel_cleanup_overlay(dev);
14085 mutex_lock(&dev->struct_mutex);
14086 intel_cleanup_gt_powersave(dev);
14087 mutex_unlock(&dev->struct_mutex);
14091 * Return which encoder is currently attached for connector.
14093 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14095 return &intel_attached_encoder(connector)->base;
14098 void intel_connector_attach_encoder(struct intel_connector *connector,
14099 struct intel_encoder *encoder)
14101 connector->encoder = encoder;
14102 drm_mode_connector_attach_encoder(&connector->base,
14107 * set vga decode state - true == enable VGA decode
14109 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14111 struct drm_i915_private *dev_priv = dev->dev_private;
14112 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14115 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14116 DRM_ERROR("failed to read control word\n");
14120 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14124 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14126 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14128 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14129 DRM_ERROR("failed to write control word\n");
14136 struct intel_display_error_state {
14138 u32 power_well_driver;
14140 int num_transcoders;
14142 struct intel_cursor_error_state {
14147 } cursor[I915_MAX_PIPES];
14149 struct intel_pipe_error_state {
14150 bool power_domain_on;
14153 } pipe[I915_MAX_PIPES];
14155 struct intel_plane_error_state {
14163 } plane[I915_MAX_PIPES];
14165 struct intel_transcoder_error_state {
14166 bool power_domain_on;
14167 enum transcoder cpu_transcoder;
14180 struct intel_display_error_state *
14181 intel_display_capture_error_state(struct drm_device *dev)
14183 struct drm_i915_private *dev_priv = dev->dev_private;
14184 struct intel_display_error_state *error;
14185 int transcoders[] = {
14193 if (INTEL_INFO(dev)->num_pipes == 0)
14196 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14200 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14201 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14203 for_each_pipe(dev_priv, i) {
14204 error->pipe[i].power_domain_on =
14205 __intel_display_power_is_enabled(dev_priv,
14206 POWER_DOMAIN_PIPE(i));
14207 if (!error->pipe[i].power_domain_on)
14210 error->cursor[i].control = I915_READ(CURCNTR(i));
14211 error->cursor[i].position = I915_READ(CURPOS(i));
14212 error->cursor[i].base = I915_READ(CURBASE(i));
14214 error->plane[i].control = I915_READ(DSPCNTR(i));
14215 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14216 if (INTEL_INFO(dev)->gen <= 3) {
14217 error->plane[i].size = I915_READ(DSPSIZE(i));
14218 error->plane[i].pos = I915_READ(DSPPOS(i));
14220 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14221 error->plane[i].addr = I915_READ(DSPADDR(i));
14222 if (INTEL_INFO(dev)->gen >= 4) {
14223 error->plane[i].surface = I915_READ(DSPSURF(i));
14224 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14227 error->pipe[i].source = I915_READ(PIPESRC(i));
14229 if (HAS_GMCH_DISPLAY(dev))
14230 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14233 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14234 if (HAS_DDI(dev_priv->dev))
14235 error->num_transcoders++; /* Account for eDP. */
14237 for (i = 0; i < error->num_transcoders; i++) {
14238 enum transcoder cpu_transcoder = transcoders[i];
14240 error->transcoder[i].power_domain_on =
14241 __intel_display_power_is_enabled(dev_priv,
14242 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14243 if (!error->transcoder[i].power_domain_on)
14246 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14248 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14249 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14250 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14251 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14252 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14253 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14254 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14260 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14263 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14264 struct drm_device *dev,
14265 struct intel_display_error_state *error)
14267 struct drm_i915_private *dev_priv = dev->dev_private;
14273 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14274 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14275 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14276 error->power_well_driver);
14277 for_each_pipe(dev_priv, i) {
14278 err_printf(m, "Pipe [%d]:\n", i);
14279 err_printf(m, " Power: %s\n",
14280 error->pipe[i].power_domain_on ? "on" : "off");
14281 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14282 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14284 err_printf(m, "Plane [%d]:\n", i);
14285 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14286 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14287 if (INTEL_INFO(dev)->gen <= 3) {
14288 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14289 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14291 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14292 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14293 if (INTEL_INFO(dev)->gen >= 4) {
14294 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14295 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14298 err_printf(m, "Cursor [%d]:\n", i);
14299 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14300 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14301 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14304 for (i = 0; i < error->num_transcoders; i++) {
14305 err_printf(m, "CPU transcoder: %c\n",
14306 transcoder_name(error->transcoder[i].cpu_transcoder));
14307 err_printf(m, " Power: %s\n",
14308 error->transcoder[i].power_domain_on ? "on" : "off");
14309 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14310 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14311 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14312 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14313 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14314 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14315 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14319 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14321 struct intel_crtc *crtc;
14323 for_each_intel_crtc(dev, crtc) {
14324 struct intel_unpin_work *work;
14326 spin_lock_irq(&dev->event_lock);
14328 work = crtc->unpin_work;
14330 if (work && work->event &&
14331 work->event->base.file_priv == file) {
14332 kfree(work->event);
14333 work->event = NULL;
14336 spin_unlock_irq(&dev->event_lock);